Application Note

VISHAY SEMICONDUCTORS
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Diodes
Application Note
Soldering Recommendations for Chip Level Package (CLP)
By Henry Karrer
INTRODUCTION
The trend in mobile applications towards reducing the
package size and thickness of components is supported by
Vishay Semiconductors chip level package (CLP)
technology. The following guidelines are intended to help
customers avoid trial and error in PCB design and reflow
process tuning.
The following parameters are key to success:
• Using solder mask defined (SMD) solder lands
Solder Mask Defined (SMD) Solder Lands
The solder land size is defined by the solder mask opening.
Considering the offset tolerances for the solder masking
process, the copper must be larger than the actual solder
land by at least 75 μm on each side. This value may vary
depending on the class of PCB used.
The advantage of SMD solder lands is that their size is much
more accurate compared to NSMD solder lands,
independent of any process tolerances in PCB copper
etching and solder mask placement.
SMD solder lands are recommended for CLP products.
• Using the right amount of solder paste
By following these guidelines, the quality of the soldered
CLP product will meet key requirements:
• Self-centering of the CLP product on the PCB
• Optimum stand-off
• Minimum tilt, and rotation
• No shorts
Solder Land Size:
These parameters have been verified by internal tests at
Vishay.
For CLP products, the exact size of the solder land is very
important. The device foot-pad size must be the same as
the solder land size.
PCB SOLDER LAND DESIGN
Non-Solder Mask Defined (NSMD) Solder Lands
Revision: 28-Aug-15
LAND SIZE 1
LAND SIZE 2
CLP0603 
(VBUS, VCUT)
140 μm x 240 μm
140 μm x 240 μm
CLP0603 (VSKY)
120 μm x 210 μm
120 μm x 190 μm
CLP1006 (VSKY)
240 μm x 490 μm
240 μm x 490 μm
CLP1007-5L
150 μm x 250 μm
5 x same size
CLP1406
TBD
TBD
CLP1608
280 μm x 620 μm
880 μm x 620 μm
CLP1515
TBD
TBD
Document Number: 85917
1
For technical questions, contact: Design-support@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
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APPLICATION NOTE
The size of the solder lands is defined by the copper area
(and its tolerances), with the effective solder land being
equal to the copper area. The solder mask layer does not
touch the solder lands; the typical solder mask layer offset
must be at least 75 μm wider than the solder land. This value
may vary depending on the class of PCB used. NSMD
solder lands are not recommended for CLP products.
TABLE 1: SOLDER LAND SIZES
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PCB SOLDERING PAD METALLIZATION
0.24
0.24
Soldering Recommendations for Chip Level Package (CLP)
0.54
There are several common soldering pad metallization /
finishes, including organic solderability protectant (OSP),
hot air solder level (HASL), and electroless nickel /
immersion gold (ENiAu) over copper pad plating. For CLP
products, Vishay only recommends ENiAu over copper pad
plating.
0.14
0.14
0.21
Footprint: CLP0603-2L (VBUS, VCUT)
There are different methods available for applying the solder
paste to the PCB.
0.19
0.50
Screen Print Using a Stencil
Stencil screening of the solder paste onto the PCB is
commonly used in the industry. Laser-cut openings with
plasma treatment for good release of the solder paste are
important features of the stencil in applying an accurate
amount of solder paste onto the PCB.
Stencil thickness, openings, and opening design (radius) are
all considerations in applying the right amount of solder
paste onto the PCB.
0.12
0.12
0.49
0.49
Footprint: CLP0603-2L (VSKY)
0.89
Recommendation for Amount of Solder Paste (Liquid
State)
0.24
0.24
AMOUNT OF SOLDER PASTE
TABLE 2: SOLDER PASTE AMOUNT (LIQUID)
Footprint: CLP1006-2L (VSKY)
VOLUME OF SOLDER PASTE
0.85
0.35
07
5
PAD 1
(10-3 mm3)
PAD 2
(10-3 mm3)
CLP0603-2L 
(VBUS, VCUT)
2.02
2.02
CLP0603-2L (VSKY)
1.51
1.37
CLP1006-2L (VSKY)
7.06
x)
0.65
0.
(5
CLP1007-5L
0.25 (5x)
0.15 (5x)
0.35
Footprint: CLP1007-5L (VBUS)
Example of solder paste calculation based on:
CLP1608-2L / Pad 1 (large pad):
Ink Jet
0.62
Revision: 28-Aug-15
10.4
0.28
Lately a new method for solder paste application has been
established. Originally this application method had been
developed for the soldering of through-hole devices (reflow
instead of wave or hand soldering). However, the process is
also available for solder paste amounts required for CLP
products. The accuracy of jet printing and easy fine tuning
of the solder paste amount are both advantage of the
process.
For the amount of solder paste to be applied, see Table 2
Document Number: 85917
2
For technical questions, contact: Design-support@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
APPLICATION NOTE
Footprint: CLP1608-2L (VSKY)
32.7
0.88 mm x 0.62 mm x 0.60 μm stencil height = 32.7 x 10-3 mm3
1.47
0.88
CLP1608-2L
7.06
3.00 (5 x)
Application Note
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Vishay Semiconductors
Soldering Recommendations for Chip Level Package (CLP)
RECOMMENDED SOLDER PASTE
Stencil Screening: 
Use type 4 or higher (smaller ball size). In our evaluations we
used the Cookson Electronics Alpha OM-338 CSP (96.5 %
Sn / 3 % Ag / 0.5 % Cu) solder paste.
Ink Jet Application: 
Use type 5 or higher (smaller ball size). Usually ink jet
equipment suppliers recommend the solder paste to be
used. In our evaluations we used the Senju UK - M705
LFAC19 (96.5 % Sn / 3 % Ag / 0.5 % Cu).
REFLOW SOLDERING PROCESS
A standard surface-mount reflow soldering process can be used (reference: JPC/JEDEC® J-STD-020D).
However, for an optimum process, recommendations from the solder paste supplier should be considered. Variations in
chemistry and viscosity of the fluxer may require small adjustments to the soldering profile.
Supplier TP ≥ TC
User TP ≤ TC
TC
Supplier tP
TC
- 5 °C
User tP
TP
tp
Max. Ramp Up Rate = 3 °C/s
Max. Ramp Down Rate = 6 °C/s
TL
Temperature
TSmax.
TC - 5 °C
tL
Preheat Area
TSmin.
tS
25
Time 25 °C to Peak
Time
Reflow Soldering profile according to JEDEC® - J-STD-020D
Document Number: 85917
3
For technical questions, contact: Design-support@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
APPLICATION NOTE
Revision: 28-Aug-15
Application Note
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Vishay Semiconductors
Soldering Recommendations for Chip Level Package (CLP)
TABLE 3 - CLASSIFICATION REFLOW PROFILES
PROFILE FEATURE
SnPb EUTECTIC ASSEMBLY
LEAD (Pb)-FREE ASSEMBLY
PREHEAT AND SOAK
Temperature min. (TSmin.)
100 °C
150 °C
150 °C
200 °C
Temperature max. (TSmax.)
Time (TSmin. to TSmax.) (tS)
60 s to 120 s
60 s to 120 s
Average ramp-up rate (TSmax. to Tp)
3 °C/s maximum
183 °C
217 °C
Liquidous temperature (TL)
Time to liquidous (tL)
60 s to 150 s
60 s to 150 s
Peak package temperature (Tp) (1)
See classification temperature in table 3
See classification temperature in table 4
Time (tp) (2) with 5 °C of the specified
(2)
30 s (2)
20 s
classification temperature (TC)
Average ramp-down rate (Tp to TSmax.)
6 °C/s maximum
Time 25 °C to peak temperature
6 min maximum
8 min maximum
Notes
(1) Tolerance for peak profile temperature (T ) is defined as a supplier minimum and user maximum
p
(2) Tolerance for time at peak profile temperature (T ) is defined as a supplier minimum and user maximum
p
Notes
1. All temperatures refer to the center of the package, measured on the package body surface that is facing up during assembly reflow
(e.g. live-bug). If parts are reflowed in other than the normal live-bug assembly reflow orientation (i.e. dead-bug), Tp shall be within ± 2 °C
of the live-bug Tp and still meet the TC requirements, otherwise, the profile shall be adjusted to achieve the latter. To accurately measure
actual peak package body temperatures refer to JEP140 for the recommended thermocouple use.
2. Reflow profiles in this document are for classification/preconditioning and are not meant to specify board assembly profiles. Actual board
assembly profiles should be developed based on specific process needs and board designs and should not exceed the parameters in
table 3. For example, if TC is 260 °C and time tp is 30 s, this means the following for the supplier and the user:
- For a supplier: The peak temperature must be at least 260 °C. The time above 255 °C must be at least 30 s.
- For a user: The peak temperature must not exceed 260 °C. The time above 255 °C must not exceed 30 s.
3. All components in the test load shall meet the classification profile requirements.
4. SMD packages classified to a given moisture sensitivity level by using procedures or criteria defined within any previous version of
J-STD-020, JESD22-A112 (rescinded), IPC-SM-786 (rescinded) do not need to be reclassified to the current revision unless a change in
classification level or a higher peak classification temperature is desired.
TABLE 4 - SnPb EUTECTIC PROCESS - CLASSIFICATION TEMPERATURES (TC)
PACKAGE THICKNESS
< 2.5 mm
 2.5 mm
VOLUME mm3
< 350
235 °C
220 °C
VOLUME mm3
 350
220 °C
220 °C
TABLE 5 - LEAD (Pb)-FREE PROCESS - CLASSIFICATION TEMPERATURES (TC)
PACKAGE THICKNESS
VOLUME mm3
350 to 2000
260 °C
250 °C
245 °C
VOLUME mm3
> 2000
260 °C
245 °C
245 °C
< 1.6 mm
1.6 mm to 2.5 mm
> 2.5 mm
Notes
5. At the direction of the device manufacturer, but not the board assembler/user, the maximum peak package body temperature (Tp) can
exceed the values specified in tables 2 and 3. The use of a higher Tp does not change the classification temperature (TC).
6. Package volume excludes external terminals (e.g., balls, bumps, lands, leads) and/or non-integral heat sinks.
7. The maximum component temperature reached during reflow depends on package thickness and volume. The use on convection reflow
processes reduces the thermal gradients between packages. However, thermal gradients due to differences in thermal mass of SMD
packages may still exist.
8. Moisture sensitivity levels of components intended for use in a lead (Pb)-free assembly process shall be evaluated using the lead (Pb)-free
classification temperatures and profiles defined in table 3 and 5, whether or not lead (Pb)-free.
9. SMD packages classified to a given moisture sensitivity level by using procedures or criteria defined within any previous version of
J-STD-020, JESD22-A112 (rescinded), or IPC-SM-786 (rescinded) do not need to be reclassified to the current revision unless a change in
classification level or a higher peak classification temperature is desired.
Revision: 28-Aug-15
Document Number: 85917
4
For technical questions, contact: Design-support@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
APPLICATION NOTE
VOLUME mm3
< 350
260 °C
260 °C
250 °C
Application Note
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Vishay Semiconductors
Soldering Recommendations for Chip Level Package (CLP)
SOLDERING QUALITY INSPECTION
An X-ray inspection system is required to find defects such
as shorts between pads, open contacts, and voids within
the solder.
REWORK PROCEDURE
For rework, the CLP package must be removed from the
PCB if there is any issue with the solder joints. Standard
SMT rework systems are recommended for this. 
INTERCHANGEABILITY OF THE CLP PRODUCTS
WITH A PLASTIC PACKAGE OF THE SAME SIZE
Based on our studies, the CLP is 100 % compatible with
competitor’s products, and exchangeable with plastic
packages of the same size and foot print.
Document Number: 85917
5
For technical questions, contact: Design-support@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
APPLICATION NOTE
Revision: 28-Aug-15
Due to the small size of the package, the rework system
should be equipped with a proper magnification aid.