2016 DCAN IP Core Configurable CAN Bus Controller v. 1.12 ● ● ● COMPANY OVERVIEW Digital Core Design is a leading IP Core provider and a System-on-Chip design house. The company was founded in 1999 and since the very beginning has been focused on IP Core architecture improvements. Our innovative, silicon proven solutions have been employed by over 300 customers and with more than 500 hundred licenses sold to companies like Intel, Siemens, Philips, General Electric, Sony and Toyota. Based on more than 70 different architectures, starting from serial interfaces to advanced microcontrollers and SoCs, we are designing solutions tailored to your needs. IP CORE OVERVIEW The DCAN is a standalone controller for the Controller Area Network (CAN), widely used in automotive and industrial applications. It conforms to Bosch CAN 2.0B specification (2.0B Active). The core has a simple CPU interface (8/16/32 bit configurable data width), with small or big endian addressing scheme. Hardware message filtering and 64 byte receive FIFO enable back-to-back message reception, with minimum CPU load. The DCAN is described at RTL level, allowing target use in FPGA or ASIC technologies. FEATURES ● Conforms to Bosch CAN 2.0B Active ● 8/16/32-bit CPU slave interface with small or big endianness Simple interface allows easy connection to CPU Supports both standard (11-bit identifier) and extended (29 bit identifier) frames Data rate up to 1 Mbps Hardware message filtering (dual/single filter) 64 byte receive FIFO 16-byte transmit buffer Overload frame is generated on FIFO overflow Normal & Listen Only Mode Single Shot transmission Ability to abort transmission Readable error counters Last Error Code Fully synthesizable Static synchronous design with positive edge clocking and synchronous reset No internal tri-states Scan test ready ○ ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● 11 and 29 bit wide message identifiers DELIVERABLES ♦ Technical documentation ● ● ● ♦ ♦ ♦ Installation notes HDL core specification Datasheet Synthesis scripts Example application Technical support ● ● IP Core implementation support 3 months maintenance ● Delivery of the IP Core and documentation updates, minor ● and major versions changes Phone & email support LICENSING Comprehensible and clearly defined licensing methods without royalty-per-chip fees make use of our IP Cores easy and simple. Single-Site license option – dedicated to small and middle sized companies, which run their business in one place. Multi-Site license option – dedicated to corporate customers, who operate at several locations. The licensed product can be used in selected company branches. In all cases the number of IP Core instantiations within a project and the number of manufactured chips are unlimited. The license is royalty-per-chip free. There are no restrictions regarding the time of use. There are two formats of the delivered IP Core: VHDL or Verilog RTL synthesizable source code called HDL Source code FPGA EDIF/NGO/NGD/QXP/VQM called Netlist PINOUT clk rst cs rd wr be(3:0)2 datai(31:0)1 addr(4:0) rxd qmr(31:0) RX FIFO qmt(31:0) TX FIFO Source code: ● ● ● ♦ ♦ Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference responses VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF datao(31:0)1 int txd dmr(31:0) waddrmr(3:0) raddrmr(3:0) enrmr enwmr dmt(31:0) waddrmt(1:0) raddrmt(1:0) enrmt enwmt 1 – configured data bus - 8-, 16- or 32 2 – byte enable (be) size is set accordingly to data bus size VHDL & VERILOG test bench environment 1 Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved. All trademarks mentioned in this document are the property of their respective owners. BLOCK DIAGRAM TX RAM pins TX RAM Interface clk rst BRP BSP txd BTL rxd Bit Timing Logic rd Baud Rate Prescaler Bit Stream Processor EML IML cs Interface Management Logic wr Error Management Logic ACF Acceptance Filtering be(3:0) addr(4:0) datai(31:0) int datao(31:0) RX RAM Receive FIFO Interface RX RAM pins clk TX RAM clk rst cs rd CPU wr DCAN be txd datai rxd CAN Transceiver addr datao irq docdbusctrl clk RX RAM 2 Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved. All trademarks mentioned in this document are the property of their respective owners. PINS DESCRIPTION PIN TYPE DESCRIPTION clk rst input input Global clock Global reset cs input Chip select rd input Read data strobe wr input Write data strobe addr(4:0) input Host address bus be(3:0) 2 input Host byte enable datai(31:0)1 input Host output data bus qmr(31:0) input RX DPRAM data output qmt(31:0) input TX DPRAM data output rxd input CAN receive data docdbusctrl input DoCD debugger input datao(31:0) 1 PERFORMANCE The following table gives a survey about the Core area and performance in ALTERA® devices after Place & Route (all key features included): Device Speed grade Logic Cells Fmax ARRIA -6 1228/569 + 2 ESB 132 MHz ARRIA II -3 1222/568 + 2 ESB 223 MHz ARRIA V -6 799 + 2 ESB 138 MHz CYCLONE -6 1985 + 2 ESB 123 MHz CYCLONE II -6 1945 + 2 ESB 141 MHz CYCLONE III -6 1941 + 2 ESB 160 MHz CYCLONE IV -6 1953 + 2 ESB 158 MHz CYCLONE V -8 815 + 2 ESB 115 MHz STRATIX -5 1956 + 2 ESB 130 MHz STRATIX II -3 1956 + 2 ESB 188 MHz STRATIX GX -5 1956 + 2 ESB 131 MHz STRATIX III -2 1227 + 2 ESB 271 MHz STRATIX IV -2 1225 + 2 ESB 276 MHz STRATIX V -3 854 + 2 ESB 284 MHz 8-bit CPU Core performance in ALTERA® devices output Host input data bus int dmr(31:0) output output Interrupt signal RX DPRAM data input waddrmr(3:0) output RX DPRAM write address raddrmr(3:0) output RX DPRAM read address enrmr output RX DPRAM read enable enwmr output RX DPRAM write enable Digital Core Design Headquarters: dmt(31:0) output TX DPRAM data input Wroclawska 94, 41-902 Bytom, POLAND waddrmt(1:0) output TX DPRAM write address e-mail: [email protected] raddrmt(1:0) output TX DPRAM read address tel.: 0048 32 282 82 66 enrmt output TX DPRAM read enable fax: 0048 32 282 74 37 enwmt output TX DPRAM write enable txd output CAN transmit data Distributors: CONTACT Please check: http://dcd.pl/sales UNITS SUMMARY Interface Management Logic (IML) – interprets commands from the CPU, provides interrupt and status indication. Bit Stream Processor (BSP) – translates messages into frames and vice versa. Baud Rate Prescaler (BRP) – defines the length of time quantum. Bit Timing Logic (BTL) – processes the bit time, calculates position of the sample point and performs synchronization. Error Management Logic (EML) – is responsible for fault confinement handling. Acceptance Filter (ACF) – decides, whether incoming messages are accepted or not, based on filter registers settings. TX/RX RAM interfaces – interfaces to external dual port memories used by the DCAN core, to store received and transmitted frames. DSPI allows direct interface to almost any existing synchronous serial peripheral. 3 Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved. All trademarks mentioned in this document are the property of their respective owners.