DCD DMAC

DMAC
Media Access Controller
ver 2.07
OVERVIEW
The DMAC is hardware implementation of
media access control protocol defined by the
IEEE standard. DMAC in cooperation with
external PHY device enables network functionality in design. It is capable of transmitting
and receiving Ethernet frames to and from
the network. Half and full duplex modes are
supported, as well 10 and 100 Mbit/s speed.
The core is able to work with wide range of
processors: 8, 16 and 32 bit data bus, with
little or big endian byte order format. Design
is technology independent and thus can be
implemented in variety of process technologies. This core strictly conforms to IEEE
802.3 standard.
KEY FEATURES
●
Conforms to IEEE 802.3-2002 specification
●
8/16/32-bit CPU slave interface with little
or big endianess
●
Simple interface allows easy connection
to CPU
●
Narrow address bus with indirect I/O interface to the transmit and receive data
dual port memories
●
●
Supports 10BASE-T and 100BASETX/FX IEEE 802.3 compliant MII PHYs
●
Supports full and half duplex operation at
10 Mbps or 100 Mbps
●
CRC-32 algorithm calculates the FCS
nibble at a time, automatic FCS generation and checking, able to capture frames
with CRC errors if required
●
Lite design, small gate count and fast
operation
●
Programmable or fixed MAC address
●
Promiscuous mode support
●
Dynamic PHY configuration by MII management interface
●
Receive FIFO able to store many messages at a time
●
Allows operation from a wide range of
input bus clock frequencies
●
Fully synthesizable
●
Static synchronous design with positive
edge clocking and synchronous reset
●
No internal tri-states
●
Scan test ready
APPLICATIONS
●
Embedded microprocessor boards
●
Networking devices (Network Interface
Cards, routers, switches)
●
Communications systems
Media Independent Interface (MII) for
connection to external 10/100 Mbps PHY
transceivers
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
PINS DESCRIPTION
DELIVERABLES
♦ Source code:
◊ VHDL Source Code or/and
◊ VERILOG Source Code or/and
◊ Encrypted, or plain text EDIF netlist
♦ VHDL & VERILOG test bench environment
◊ Active-HDL automatic simulation macros
◊ ModelSim automatic simulation macros
◊ Tests with reference responses
♦ Technical documentation
◊ Installation notes
◊ HDL core specification
◊ Datasheet
♦ Synthesis scripts
♦ Example application
♦ Technical support
◊ IP Core implementation support
◊ 3 months maintenance
●
●
●
Delivery the IP Core updates, minor
and major versions changes
Delivery the documentation updates
Phone & email support
SYMBOL
rst
rdcs
wrcs
qmt(31:0)
rd
wr
be(3:0)2
datai(31:0)1
rdaddr(4:0)
wraddr(4:0)
clk
qmr(31:0)
rxdata(3:0)
rxdv
rxer
rxclk
crs
col
txclk
mdi
docdbusctrl
PIN
TYPE
clk
input
Global clock
rst
input
Global reset
rdcs
input
Read chip select
wrcs
input
Write chip select
rd
input
Read data strobe
wr
input
Write data strobe
rdaddr(4:0)
input
Host read address bus
wraddr(4:0)
be(3:0)
2
datai(31:0)
1
datao(31:0)1
irq
dmr(31:0)
waddrmr(8:0)
raddrmr(8:0)
enrmr
enwmr
txdata(3:0)
txen
txer
mdc
mdo
mdoe
input
Host write address bus
input
Host byte enable
input
Host output data bus
qmr(31:0)
input
RX DPRAM data output
qmt(31:0)
input
TX DPRAM data output
rxdata(3:0)
input
Ethernet receive data
rxdv
input
Ethernet receive data valid
rxer
input
Ethernet receive error
rxclk
input
Ethernet receive clock
txclk
input
Ethernet transmit clock
crs
input
Ethernet carrier sense
col
input
Ethernet collision detection
mdi
input
Management data input
docdbusctrl
input
DoCD debugger input
1
dmt(31:0)
waddrmt(8:0)
raddrmt(8:0)
enrmt
enwmt
DESCRIPTION
datao(31:0)
output Host input data bus
irq
output Interrupt signal
dmr(31:0)
output RX DPRAM data input
waddrmr(8:0)
output RX DPRAM write address
raddrmr(8:0)
output RX DPRAM read address
enrmr
output RX DPRAM read enable
enwmr
output RX DPRAM write enable
dmt(31:0)
output TX DPRAM data input
waddrmt(8:0)
output TX DPRAM write address
raddrmt(8:0)
output TX DPRAM read address
enrmt
output TX DPRAM read enable
enwmt
output TX DPRAM write enable
txer
output Ethernet transmit error
txen
output Ethernet transmit enable
txdata(3:0)
output Ethernet transmit data
mdc
output Management clock
mdo
output Management data output
mdoe
output Management data output enable
clk
input
Global clock
rst
input
Global reset
rdcs
input
Read chip select
wrcs
input
Write chip select
1 – data bus can be configured as 8-, 16- or 32- bit depends
on processor’s bus size
2 – byte enable (be) size is set accordingly to data bus size
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
BLOCK DIAGRAM
PERFORMANCE
Figure below shows the DMAC IP Core block
diagram.
The following table gives a survey about the
Core area and performance in the ALTERA®
devices after Place & Route (all key features
have been included):
TX RAM pins
txclk
crs
col
txen
txer
txdata(3:0)
mdi
mdc
mdo
mdoe
rxclk
rxdv
rxer
rxdata(3:0)
Transmit
module
STA
Receive
module
TX RAM interface
Synchronization
logic
Control &
I/O logic
RX FIFO
docdbusctrl
clk
rst
rdcs
wrcs
rd
wr
be(3:0)
rdaddr(4:0)
wraddr(4:0)
datai(31:0)
irq
datao(31:0)
RX RAM pins
Transmit module – Performs transmit management functions, sends frames to Ethernet
medium.
Device
Speed
grade
Logic Cells
STRATIX II
CYCLONE II
STRATIX GX
STRATIX
CYCLONE
APEX II
APEX20KC
APEX20KE
APEX20K
-3
-6
-5
-5
-6
-7
-7
-1
-1
967 + 4 kB RAM
1222 + 4 kB RAM
1255 + 4 kB RAM
1255 + 4 kB RAM
1254 + 4 kB RAM
1622 + 4 kB RAM
1622 + 4 kB RAM
1622 + 4 kB RAM
1622 + 4 kB RAM
Fmax [MHz]
clk / rxclk / txclk
211 / 200 / 175
150 / 156 / 152
152 / 156 / 138
162 / 147 / 137
148 / 133 / 133
145 / 106 / 111
127 / 118 / 117
108 / 99 / 111
86 / 87 / 88
Core performance in ALTERA® devices
Receive module – is responsible for receiving frames from the Ethernet. Provides necessary functions for frame decapsulation,
CRC checking, address recognizing and error
detection.
Synchronization logic – There are 3 clock
domains in the DMAC core. This module performs synchronization between these.
TX RAM / RX FIFO RAM interfaces – Interfaces to external dual port memories used by
the DMAC core to store received and transmitted frames.
Control and I/O logic – This module provides interface to CPU/BUS. It exchanges
data and control logic with transmit and receive modules, thus controls these to perform
transmit and receive operations.
STA – Station Management entity provides
capability to communicate with PHY by simple serial management interface.
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
CONTACTS
For any modification or special request
please contact to Digital Core Design or local
distributors.
Headquarters:
Wroclawska 94
41-902 Bytom, POLAND
nfo@dcd.pl
e-mail: iinfo@dcd.pl
tel.
: +48 32 282 82 66
fax
: +48 32 282 74 37
Distributors:
ttp://www.dcd.pl/apartn.php
Please check hhttp://www.dcd.pl/apartn.php
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.