ASIC Datasheet

2016
DMAC IP Core
Media Access Controller v. 2.09
COMPANY OVERVIEW
LICENSING
Digital Core Design is a leading IP Core provider
and a System-on-Chip design house. The company
was founded in 1999 and since the very beginning
has been focused on IP Core architecture improvements. Our innovative, silicon proven solutions have been employed by over 300 customers
and with more than 500 hundred licenses sold to
companies like Intel, Siemens, Philips, General
Electric, Sony and Toyota. Based on more than 70
different architectures, starting from serial interfaces to advanced microcontrollers and SoCs, we
are designing solutions tailored to your needs.
Comprehensible and clearly defined licensing
methods without royalty-per-chip fees make use
of our IP Cores easy and simple.
IP CORE OVERVIEW
The DMAC is a hardware implementation of the
media access control protocol, defined by the IEEE
standard. The DMAC, in cooperation with external
PHY device, enables network functionality in design. It is capable of transmitting and receiving
Ethernet frames, to and from the network. Half
and full duplex modes are supported, as well as 10
and 100 Mbit/s speed. The core is able to work
with a wide range of processors: 8, 16 and 32 bit
data bus, with little or big endian byte order format. The design is technology independent and
thus can be implemented in various process technologies. This core strictly conforms to the IEEE
802.3 standard.
KEY FEATURES
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Conforms to IEEE 802.3-2002 specification
8/16/32-bit CPU slave interface with little or big
endianness
Simple interface allows easy connection to CPU
Supports 10BASE-T and 100BASE-TX/FX IEEE 802.3
compliant MII PHYs
Media Independent Interface (MII) for connection to
external 10/100 Mbps PHY transceivers
Supports full and half duplex operation at 10 or 100
Mbps
CRC-32 algorithm calculates the FCS nibble at a time,
automatic FCS generation and checking, able to capture frames with CRC errors if required
Lite design, small gate count and fast operation
Programmable or fixed MAC address
Promiscuous mode support
Dynamic PHY configuration by STA management
interface
Receive FIFO able to store many messages at a time
Allows operation from a wide range of input bus clock
frequencies
Fully synthesizable
Static synchronous design with positive edge clocking
and synchronous reset
No internal tri-states
Scan test ready
Single-Site license option – dedicated to small and
middle sized companies, which run their business
in one place.
Multi-Site license option – dedicated to corporate
customers, who operate at several locations. The
licensed product can be used in selected company
branches.
In all cases the number of IP Core instantiations
within a project and the number of manufactured
chips are unlimited. The license is royalty-per-chip
free. There are no restrictions regarding the time
of use. There are two formats of the delivered IP
Core:
VHDL or Verilog RTL synthesizable source code
called HDL Source code
FPGA EDIF/NGO/NGD/QXP/VQM called Netlist
SYMBOL
rst
rdcs
wrcs
qmt(31:0)
rd
wr
be(3:0)2
datai(31:0)1
rdaddr(4:0)
wraddr(4:0)
clk
qmr(31:0)
rxdata(3:0)
rxdv
rxer
rxclk
crs
col
txclk
mdi
docdbusctrl
dmt(31:0)
waddrmt(8:0)
raddrmt(8:0)
enrmt
enwmt
datao(31:0)1
irq
dmr(31:0)
waddrmr(8:0)
raddrmr(8:0)
enrmr
enwmr
txdata(3:0)
txen
txer
mdc
mdo
mdoe
1 – data bus can be configured as 8-, 16- or 32- bit depends on
processor’s bus size
2 – byte enable (be) size is set accordingly to data bus size
3
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
BLOCK DIAGRAM
The figure below shows the DMAC IP Core block diagram.
TX RAM pins
txclk
crs
col
txen
txer
txdata(3:0)
mdi
mdc
mdo
mdoe
rxclk
rxdv
rxer
rxdata(3:0)
Transmit
Module
STA
Receive
Module
TX RAM Interface
Synchronization
Logic
Control &
I/O Logic
RX FIFO
docdbusctrl
clk
rst
rdcs
wrcs
rd
wr
be(3:0)
rdaddr(4:0)
wraddr(4:0)
datai(31:0)
irq
datao(31:0)
RX RAM pins
DELIVERABLES
UNITS SUMMARY
Transmit module – Performs transmit management functions, sends frames to Ethernet medium.
Receive module – is responsible for receiving
frames from the Ethernet. Provides necessary
functions for frame decapsulation, CRC checking,
address recognizing and error detection.
Synchronization logic – There are 3 clock domains
in the DMAC core - this module performs synchronization between them.
TX RAM / RX FIFO RAM interfaces – Interfaces
to external dual port memories used by the DMAC
core, to store received and transmitted frames.
♦
♦
♦
♦
♦
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Control and I/O logic – This module provides interface to CPU/BUS. It exchanges data and control
logic with transmit and receive modules, thus controls these, to perform transmit and receive operations.
STA – Station Management entity, enables communication with PHY, via simple serial management interface.
Source code:
● VHDL Source Code or/and
● VERILOG Source Code or/and
● Encrypted, or plain text EDIF
VHDL & VERILOG test bench environment
● Active-HDL automatic simulation macros
● ModelSim automatic simulation macros
● Tests with reference responses
Technical documentation
● Installation notes
● HDL core specification
● Datasheet
Synthesis scripts
Example application
Technical support
● IP Core implementation support
● 3 months maintenance
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Delivery of the IP Core and documentation updates, minor
and major versions changes
Phone & email support
APPLICATIONS
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Embedded microprocessor boards
Networking devices (Network Interface Cards,
routers, switches)
Communications systems
3
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
PINS DESCRIPTION
PIN
clk
rst
rdcs
wrcs
rd
wr
rdaddr(4:0)
wraddr(4:0)
2
be(3:0)
1
datai(31:0)
qmr(31:0)
qmt(31:0)
rxdata(3:0)
rxdv
rxer
rxclk
txclk
crs
col
mdi
docdbusctrl
1
datao(31:0)
irq
dmr(31:0)
addrmr(8:0)
raddrmr(8:0)
enrmr
enwmr
dmt(31:0)
addrmt(8:0)
raddrmt(8:0)
enrmt
enwmt
txer
txen
txdata(3:0)
mdc
mdo
mdoe
TYPE
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
Device
DESCRIPTION
Global clock
Global reset
Read chip select
Write chip select
Read data strobe
Write data strobe
Host read address bus
Host write address bus
Host byte enable
Host output data bus
RX DPRAM data output
TX DPRAM data output
Ethernet receive data
Ethernet receive data valid
Ethernet receive error
Ethernet receive clock
Ethernet transmit clock
Ethernet carrier sense
Ethernet collision detection
Management data input
DoCD debugger input
Host input data bus
Interrupt signal
RX DPRAM data input
RX DPRAM write address
RX DPRAM read address
RX DPRAM read enable
RX DPRAM write enable
TX DPRAM data input
TX DPRAM write address
TX DPRAM read address
TX DPRAM read enable
TX DPRAM write enable
Ethernet transmit error
Ethernet transmit enable
Ethernet transmit data
Management clock
Management data output
Management data output enable
Speed
Min area
Fmax [MHz]
clk / txclk / rxclk
250 / >50 / >50
360 / >50 / >50
800 / >50 / >50
900 / >50 / >50
0.25 um
typical
7800 gates
0.18 um
typical
7800 gates
0.09 um
typical
6400 gates
0.06 um
typical
6300 gates
rxclk, txclk – design clock is 25 MHz
Core performance in ASIC devices
CONTACT
Digital Core Design Headquarters:
Wroclawska 94, 41-902 Bytom, POLAND
e-mail:
tel.:
fax:
[email protected]
0048 32 282 82 66
0048 32 282 74 37
Distributors:
Please check:
http://dcd.pl/sales
PERFORMANCE
The following table gives a survey about the Core
area and performance in ASIC devices (all key features included):
Component
RX
RX FIFO
TX
Control & I/O logic
STA
Total area
Area
[gates]
2200
1100
2400
1500
600
7800
[FFs]
172
131
197
202
53
755
3
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
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