Work-In-Progress Option Information www.vishay.com Vishay Siliconix MIL-PRF-19500 JAN/TX/TXV Process Test Conditions per MIL-STD-750 JAN JANTX JANTXV WAFER LOT ACCEPTANCE WAFER LOT ACCEPTANCE WAFER LOT ACCEPTANCE PRESEAL INSPECTION M-2072 LOT NORM THERMAL IMPEDANCE TESTING LOT NORM THERMAL IMPEDANCE TESTING THERMAL IMPEDANCE TESTING STABILIZATION BAKE M-1032, 24 HR, 150 °C STABILIZATION BAKE M-1032, 24 HR, 150 °C TEMP CYCLE M-1051 CONDITION C, -55 °C TO +150 °C TEMP CYCLE M-1051 CONDITION C, -55 °C TO +150 °C CONSTANT ACCELERATION M-2006, 20 KG, Y1 AXIS CONSTANT ACCELERATION M-2006, 20 KG, Y1 AXIS PRE-BURNIN ELECTRICAL PRE-BURNIN ELECTRICAL HTGB M-1042 80 % VGS, 48 HR, 150 °C HTGB M-1042 80 % VGS, 48 HR, 150 °C INTERIM ELECTRICAL TESTING INTERIM ELECTRICAL TESTING HTRB M-1042 80 % BVDSS, 160 HR, 150 °C HTRB M-1042 80 % BVDSS, 160 HR, 150 °C PDA 5 % FINAL ELECTRICAL Revision: 28-Apr-15 LOT NORM FINAL ELECTRICAL FINE/GROSS LEAK METHOD 1071 FINE/GROSS LEAK METHOD 1071 QUALITY CONFORMANCE GROUP A, B, C, D and E QUALITY CONFORMANCE GROUP A, B, C, D and E PDA 5 % FINAL ELECTRICAL FINE/GROSS LEAK METHOD 1071 QUALITY CONFORMANCE GROUP A, B, C, D and E Document Number: 63437 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000