RT7300B PFC Controller with Critical Conduction Mode General Description Features The RT7300B is an active Power Factor Correction (PFC) controller with critical conduction mode (CRM) operation that is designed to meet line current harmonic regulations for the applications of AC/DC adapters, electronic ballasts and medium off-line power converters (<300W). The CRM and Feed-Forward schemes provide near unity power factor across a wide range of input voltages and output powers. The totem-pole gate driver with 600mA sourcing current and 800mA sinking current provides powerful driving capability for power MOSFET to improve conversion efficiency. The RT7300B features an extra low start-up current (≤20A) and supports a disable function to reduce power consumption in standby mode, which makes it easy to comply with energy saving regulations such as Blue Angel, Energy Star and Energy 2000. This controller integrates comprehensive safety protection functions for robust designs including input under voltage lockout, output over voltage protection, under voltage protection and cycle-by-cycle current limit. The RT7300B is a cost-effective solution for PFC power converter with minimum external components. It is available in the SOP-8 package. Critical Conduction Mode (CRM) Operation Constant On-Time Control (Voltage Mode) Near Unity Power Factor Ultra Low Start-up Current (<20A) Input Voltage Feed-Forward Compensation Wide Supply Voltage Range from 12V to 25V Totem Pole Gate Driver with 600mA/800mA Maximum Frequency Clamping (120kHz) DCM THD Optimization Fast Dynamic Response Light Load Burst Mode Operation Disable Function Maximum/Minimum On-Time Limit Cycle-by-Cycle Current Limit Output Over Voltage Protection (OVP) Under Voltage Lockout (UVLO) RoHS Compliant and Halogen Free Applications Electrical Lamp Ballast LED Lighting AC/DC Adapter/Charger for Desktop PC, NB, TV, Monitor, Etc. Entry-Level Server, Web Server Simplified Application Circuit PSR Converter SSR Converter BD BD DOUT Line VOUT+ VOUT+ Neutral VOUTRG Neutral VOUT- GD ZCD RAUX Q1 ROPTO RZCD GD ZCD CS RAUX RCS RT7300B CS U2A CFB R FB RINV RINV1 VDD VDD INV RST ROUT1 RCS RT7300B DVDD VDD DVDD VDD CVDD AUX RG AUX Q1 AUX RZCD COUT CSIN COUT CSIN AUX DOUT Line CVDD RINV2 VDD VDD INV RST ROUT2 DINV U2B RFF1 RFF2 RFF1 COMP CFF CCOMP GND Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS7300B-01 COMP FF RCOMP FF April 2016 RFF2 CCOMP CFF GND is a registered trademark of Richtek Technology Corporation. www.richtek.com 1 RT7300B Ordering Information Marking Information RT7300B RT7300BGS : Product Number YMDNN : Date Code RT7300B GSYMDNN Package Type S : SOP-8 Lead Plating System G : Green (Halogen Free and Pb Free) Pin Configurations (TOP VIEW) Note : Richtek products are : 8 INV RoHS compliant and compatible with the current VDD COMP 2 7 GD requirements of IPC/JEDEC J-STD-020. FF 3 6 GND Suitable for use in SnPb or Pb-free soldering processes. CS 4 5 ZCD SOP-8 Functional Pin Description Pin No. Pin Name Pin Function 1 INV Inverting Input of the Internal Error Amplifier. Connect a resistive divider from output voltage to this pin for voltage feedback. It also used for OVP and UVP detections. 2 COMP Output of the Internal Error Amplifier. Connect a compensation network between this pin and GND for dynamic load performance. 3 FF Feed-Forward Input for Line Voltage. This pin senses the line input voltage via a resistive divider. Connect a suitable capacitor to filter out the line voltage ripple & noise. 4 CS Current Sense Input. The current sense resistor between this pin and GND is used for current limit setting. 5 ZCD Zero Current Detection Input. Input from secondary winding of PFC choke for detecting demagnetization timing of PFC choke. This pin also can be used to enable/disable the controller. 6 GND Ground of the Controller. 7 GD Gate Driver Output for External Power MOSFET. 8 VDD Supply Voltage Input. The controller will be enabled when VDD exceeds VON_TH (16V typ.) and disabled when VDD decreases lower than VOFF_TH (9V typ.). Function Block Diagram ZCD Clamping Circuit Zero Current Detect Blank & Maximum Frequency Clamping Disable CS Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 2 GD GND + - COMP Soft Driver + Leading Edge Blanking Feed- Forward & THD Optimize Ramp Generator Q R Start 0.4V FF S UVLO OVP INV + + GM - VDD 1.65V 1.5V is a registered trademark of Richtek Technology Corporation. DS7300B-01 April 2016 RT7300B Operation Critical Conduction Mode (CRM) The Critical Conduction Mode is also called Transition Mode or Boundary Mode. Figure 1 shows the CRM operating at the boundary between Continuous Conduction Mode (CCM) and Discontinuous Conduction Mode (DCM). In CRM, the power switch turns on immediately when the inductor current decreases to zero. The CRM is the preferred control method for medium power (<300W) applications due to the features of zero current switching and lower peak current than that in DCM. control, the envelope of inductor peak current will follow the input voltage waveform with in-phase. The average inductor current will be half of the peak current shown as Figure 3. Therefore, the near unity power factor is easy to be achieved by this control scheme. IL_pk | sinθ | = VIN_pk | sinθ | tON LPFC (2) Inductor Current DCM CRM CCM Figure 1. Inductor Current of DCM, CRM and CCM Constant On-Time Voltage Mode Control Figure 2 shows a typical flyback converter. When the MOSFET turns on with a fixed on-time (tON), the inductor current can be calculated by the following equation (1). TX1 NP:NS DOUT IL COUT LPFC VIN + VOUT - MOSFET Current Iin_avg Average Input Current IDOUT Output Diode Current VQ1_GATE MOSFET Gate Voltage Figure 3. Inductor Current of CRM with Constant On-Time Voltage Mode Control The maximum VDD voltage is set at 27V typically for over voltage protection shown as Figure 4. An internal 29V zener diode is also used to avoid over voltage stress for the internal circuits. (1) rectified by a bridge rectifier, the inductor current can be expressed with equation (2). When the converter operates in CRM with constant on-time voltage mode Copyright © 2016 Richtek Technology Corporation. All rights reserved. April 2016 IQ1 The controller will be enabled when VDD exceeds VON_TH (16V typ.) and disabled when VDD decreases lower than VOFF_TH (9V typ.). ROUT If the input voltage is a sinusoidal waveform and DS7300B-01 Peak Inductor Current Under Voltage Lockout Figure 2. Typical flyback Converter VIN tON LPFC Input Voltage IL_PK IOUT Q1 IL_PK = VIN When the VDD is available, the precise reference is generated for internal circuitries such as Error Amplifier, Current Sense, OVP, UVP. The internal reference equips with excellent temperature coefficient performance so that the RT7300B can be operated in varied environments. is a registered trademark of Richtek Technology Corporation. www.richtek.com 3 RT7300B ICOMP_Sourcing Current UVLO + Bias & Band Gap - VDD Hys. = 7V >1mA 29V + 16V + 10µs De-Bounce - + OV 27V OVP 1.35V 1.5V 1.65V GM =1 00 µA /V Figure 4. VDD and UVLO Feedback Voltage Detection Figure 5 shows the feedback voltage detection circuit. The INV pin is the inverting input of the Error Amplifier with 1.5V reference voltage. Over voltage protection is provided with threshold voltage 1.65V. If the INV voltage is over 1.65V, the gate driver will be disabled to prevent output over voltage condition or feedback open condition. Although the INV is an input pin with high impedance, it is suggested that the bias current of the potential divider should be over 30µA for noise immunity. COMP ROUT1 INV ROUT2 1.65V + GM - Feed-Forward Compensation The FF pin is an input pin with high impedance to detect the line input voltage shown as Figure 7. A proper voltage divider should be applied to sense the line voltage after bridge diode rectifier. Since the FF voltage is proportional to the line input voltage, it provides a feed-forward signal to compensate the loop bandwidth for high line and low line input conditions. VCSIN - OVP + CINV RFF1 RFF2 FF Feed- Forward & THD Optimize Ramp Generator CFF VD 1.5V Figure 5. Feedback Voltage Detection Transconductance Error Amplifier The RT7300B implements transconductance error amplifier with non-linear GM design to regulate the Flyback output voltage and provide fast dynamic response. The transconductance value is 100µA/V in normal operation. When the INV voltage increases over 1.65V or decreases under 1.35V, the output of error amplifier will source or sink 1mA maximum current at COMP pin respectively shown as Figure 6. Thus, the non-linear GM design can provide fast response for the dynamic load of PFC converters even though the bandwidth of control loop is lower than line frequency. Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 4 INV + GM - + + - 1.5V VOUT+ Figure 6. Non-linear GM PWM OFF - COMP Figure 7. FF Detection Circuit The constant on-time, tON, can be derived from the following equations. t PIN 1 VIN_pk IL_pk ON 4 tS IL_pk VIN_pk tON LPFC 2 VIN_pk (VIN_pk ) t t PIN 1 VIN_pk tON ON 1 tON ON 4 LPFC tS 4 LPFC tS 4 PIN LPFC t ON (3) VIN_pk 2 tON tS is a registered trademark of Richtek Technology Corporation. DS7300B-01 April 2016 RT7300B In RT7300B, the tON is implemented by a constant current charging a capacitor till VCOMP threshold voltage is reached. Therefore, the tON is a function of FF K x (VFF) 2 gmramp + GM Cramp tON tS VCOMP. Cramp VCOMP VD Iramp Ramp Generator (4) Then, the VCOMP can be derived from equation (3) and (4). Cramp VCOMP VD 4 PIN LPFC Iramp 2 t ON VIN_pk tS Iramp 4 PIN LPFC VCOMP + VD C ramp VIN_pk 2 tON tS (5) high and low input voltages. This variation will impact tON, Burst mode entry level and loop bandwidth. In order to compensate the variation, the Iramp is designed to be proportional to the input voltage shown as equation (6). Iramp (VIN_pk ) k VFF t gmramp ON tS RFF2 2 2 = k VIN_RMS RFF1 + RFF2 2 tON gm ramp tS (6) 2 VFF2 gm 8 ramp PIN LPFC RFF1 + RFF2 VComp (FF) + VD 2 Cramp (7) When k = 0.5, the VCOMP is compensated to be proportional to the power only. So, the tON will be stable to support good power factor for high and low line voltage conditions. Ramp Generator The RT7300B provides constant on-time voltage mode control to achieve near unity power factor for the CRM Flyback converters. Figure 8 shows the Ramp Generator with Feed-Forward compensation and THD optimization circuit for the constant on-time operation. Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS7300B-01 April 2016 1.5V INV + GM - + PWM OFF - COMP Figure 8. Ramp Generator According to equation (5), the VCOMP is reversely proportional to the input voltage so that the VCOMP has a large variation for the change of line voltage between 2 VD + - tON = The charging current of ramp generator is modulated following the squared FF voltage with line voltage compensation and the THD optimization scheme is implemented to compensate the harmonic distortion. ZCD and Enable Function In CRM operation, when the power switch turns on, the inductor current increases linearly to the peak value. When the power switch turns off, the inductor current decreases linearly to zero. The zero current can be detected by the ZCD pin with the auxiliary winding of Flyback inductor. Figure 9 and Figure 10 show the ZCD block diagram and related waveforms. The ZCD block diagram provides zero current detection, voltage clamp and shutdown control functions. When the inductor current decreases to zero, the auxiliary winding voltage will turn from high to low. Once the ZCD voltage decreases to the VZCDT threshold, the controller will generate a signal for gate driver. The hysteresis voltage between the threshold VZCDA and VZCDT is designed to avoid mis-triggering. In order to prevent over voltage stress, the ZCD pin voltage is clamped at VZCDH if the input voltage is too high from the auxiliary winding and the ZCD pin voltage is clamped at VZCDL if the input voltage is lower than zero. is a registered trademark of Richtek Technology Corporation. www.richtek.com 5 RT7300B The RT7300B also provides ZCD time-out detection function. If the controller runs at maximum frequency and there is no ZCD signal being detected after 4µs DOUT VOUT+ NS NAUX COUT VOUT- delay time, the PWM will be turned on for ZCD time-out detection. + RZCD Upper Clamp ZCD Lower Clamp VZCDA 1.6V - VZCDT 1V + Q Dmag R Q VAUX - 0.25V/1V S + Disable ILPFC Figure 9.ZCD Block Diagram The RT7300B provides shutdown function to save power consumption in standby mode. When the ZCD pin is pulled lower than 250mV, the gate driver will be turned off and operate in standby mode with low quiescent current less than 600µA. Once the ZCD pin is released, the controller will be activated. GD VZCD Upper Clamp VZCDA VZCDT VZCD_en VZCD_dis Lower Clamp Figure 10. ZCD Related Waveforms. Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 6 is a registered trademark of Richtek Technology Corporation. DS7300B-01 April 2016 RT7300B Absolute Maximum Ratings (Note 1) Supply Voltage, VDD --------------------------------------------------------------------------------------------- 0.3 to 30V Gate Driver Output, GD ------------------------------------------------------------------------------------------ 0.3V to 20V Other Pins ----------------------------------------------------------------------------------------------------------- 0.3V to 6V Power Dissipation, PD @ TA = 25°C SOP-8 ------------------------------------------------------------------------------------------------------------------ 0.625W Package Thermal Resistance (Note 2) SOP-8, JA ------------------------------------------------------------------------------------------------------------ 160°C/W Junction Temperature -------------------------------------------------------------------------------------------- 150°C Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------ 260°C Storage Temperature Range ------------------------------------------------------------------------------------- 65°C to 150°C ESD Susceptibility (Note 3) HBM (Human Body Model) --------------------------------------------------------------------------------------- 2kV MM (Machine Model) --------------------------------------------------------------------------------------------- 200V Recommended Operating Conditions (Note 4) Supply Voltage, VDD ----------------------------------------------------------------------------------------------- 12V to 25V Junction Temperature Range ------------------------------------------------------------------------------------ 40°C to 125°C Electrical Characteristics (VDD = 15V, TA = 25C, unless otherwise specification) Parameter Symbol Test Conditions Min Typ Max Unit 25.5 27 28.5 V -- 10 -- s VDD Section VDD OVP Threshold Voltage VOVP VDD OVP De-bounce Time VDD On Threshold Voltage VON_TH 15 16 17 V VDD Off Threshold Voltage VOFF_TH 8 9 10 V Zener Voltage 29 -- -- V Operating Supply Current VZ IDD_OP IZCD = 0, and GD open -- -- 2.5 mA Quiescent Current IQ At burst mode, and GD open -- -- 1.7 mA -- -- 0.6 mA IDD_ST PFC is disabled Before VON_TH -- -- 20 A Upper Clamp Voltage VZC_DH IZCD = 2.5mA 4.5 4.8 5.5 V Lower Clamp Voltage VZC_DL IZCD = 2.5mA 0.3 0.65 -- V Arming Voltage VZC_DA (Note 5) -- 1.6 -- V Trigger Voltage VZC_DT (Note 5) -- 1 -- V Delay Time Between Trigger Point and Gate Turn On -- 100 170 ns Sourcing Current Capability 2.5 -- 6.5 mA Standby Current Start-Up Current ZCD Section Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS7300B-01 April 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 7 RT7300B Parameter Symbol Test Conditions Sinking Current Capability Min Typ Max Unit 2.5 -- -- mA Disable Voltage VZCD_ DIS -- -- 250 mV Restart Voltage VZCD_ EN 1 -- -- V 30 75 100 A -- -- 1 A 1.47 1.5 1.53 V -- -- 1 A |VERROR| < 0.25V 80 100 120 A/V |VERROR| 0.25V -- 1 -- mA 4.25 -- -- V 1.55 1.65 1.75 V -- 20 -- s Pull-High Current After Disable FF Section Input Bias Current IBIAS Leakage Current of FF Pin GM Section Non-Inverting Input Reference VREF INV Bias Current Transconduction gm Non-linear Gm COMP Maximum Voltage VCOMP_OP PWM Section INV OVP Threshold Voltage INV OVP De-bounce Time Burst Mode Entry Level High VBURST_H Measure at COMP Pin 1.85 2.15 2.45 Level Low VBURST_L Measure at COMP Pin 1.75 2.05 2.35 1.5 2 4 s -- 70 -- mV/s De-bounce Time of Burst Mode V Ramp Slope VFF=0.8V Minimum On-Time tON(MIN)_PFC = 3pF x 2.5V / (IZCD x 0.02), IZCD = 75A 4.4 5.4 6.4 s LEB + Delay 240 400 570 ns 0.35 0.4 0.45 V Current Sense Section Leading Edge Blanking Time tLEB_PFC Current Sense Threshold Voltage VCS_PFC (Note 6) Gate Driver Section Rising Time tR CL = 1nF -- 40 80 ns Falling Time tF CL = 1nF -- 30 70 ns VDD = 25V -- 13 -- V -- 12 -- k Gate Output Clamping Voltage VCLAMP Internal Pull Low Resistor Oscillator Section Valley Mask Time tMASK 7 8.5 10 s Duration of Starter tSTART 75 130 300 s Maximum On-Time tON(MAX)_PFC -- 50 -- s Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability Note 2. Note 3. Note 4. Note 5. Note 6. JA is measured at TA = 25C on a low effective thermal conductivity single-layer test board per JEDEC 51-3. Devices are ESD sensitive. Handling precaution is recommended The device is not guaranteed to function outside its operating conditions. Guaranteed by Design. Leading edge blanking time and internal propagation delay time is guaranteed by design. Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 8 is a registered trademark of Richtek Technology Corporation. DS7300B-01 April 2016 RT7300B Typical Application Circuit Typical PSR Application Circuit C RSN2 SN2 BD F1 DOUT Line VOUT+ RSN1 CSN1 COUT CSIN RNTC DSN DG Neutral VOUTAUX RG AUX RZCD 5 7 GD ZCD RAUX CS Q1 4 RCS RT7300B DVDD VDD 8 INV VDD CVDD VDD RST RINV2 RFF1 COMP 3 RFF2 RINV1 1 2 RCOMP FF CFF GND CCOMP 6 Typical SSR Application Circuit C RSN2 SN2 BD F1 DOUT Line VOUT+ RSN1 CSN1 COUT CSIN RNTC DSN DG Neutral VOUTAUX RG AUX RZCD 5 ZCD RAUX DVDD CS VDD INV CFB R FB 1 RINV VDD ROUT2 DINV COMP 3 U2B 2 FF CCOMP CFF GND Copyright © 2016 Richtek Technology Corporation. All rights reserved. ROUT1 RCS RST RFF1 April 2016 U2A RT7300B CVDD DS7300B-01 4 VDD 8 RFF2 Q1 ROPTO 7 GD 6 is a registered trademark of Richtek Technology Corporation. www.richtek.com 9 RT7300B Typical Operating Characteristics Transconduction vs. Temperature 102 1.52 100 Transconduction (µA/V)1 Non-inverting Reference (V) Non-inverting Input Reference vs. VDD 1.53 1.51 1.50 1.49 1.48 98 VDD = 10V VDD = 26V 96 VDD = 16V 94 92 90 VCOMP = 0.5V 88 1.47 9 14 19 24 -50 29 -25 0 Transconduction vs. Temperature 50 0 100 125 100 Non-linear Region -500 98 I COMP (µA) 1 VDD = 10V VDD = 26V 96 VDD = 16V 94 -1000 VDD = 26V, TA = 25°C -1500 VDD = 10V, TA = 25°C VDD = 26V, TA = 125°C VDD = 10V, TA = 125°C -2000 92 VDD = 26V, TA = 40°C VCOMP = 4V 90 VDD = 10V, TA = 40°C -2500 -50 -25 0 25 50 75 100 125 0 1 2 ICOMP vs. VCOMP (Sinking) 1800 3 4 5 VCOMP (V) Temperature (°C) Maximum COMP Voltage vs. VDD 4.440 Maximum COMP Voltage (V)1 Non-linear Region 1500 I COMP (µA) 1 75 ICOMP vs. VCOMP (Sourcing) 102 Transconduction (µA/V)1 25 Temperature (°C) VDD (V) 1200 VDD = 26V, TA = 25°C 900 VDD = 10V, TA = 25°C VDD = 26V, TA = 125°C 600 VDD = 10V, TA = 125°C VDD = 26V, TA = 40°C 300 VDD = 10V, TA = 40°C 4.435 4.430 4.425 4.420 4.415 4.410 0 0 1 2 3 4 VCOMP (V) Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 10 5 8 10.5 13 15.5 18 20.5 23 25.5 28 VDD (V) is a registered trademark of Richtek Technology Corporation. DS7300B-01 April 2016 RT7300B Maximum COMP Voltage vs. Temperature Burst Mode Entry Level vs. VDD 2.18 Burst Mode Entry Level (V) Maximum COMP Voltage (V)1 4.43 4.42 4.41 4.40 4.39 4.38 4.37 VBurst_H 2.16 2.14 2.12 2.10 2.08 VBurst_L 2.06 VDD = 10V 2.04 4.36 -50 -25 0 25 50 75 100 8 125 13 18 23 28 VDD (V) Temperature (°C) On-Time vs. COMP Voltage On-Time vs. Feed-Forward Voltage 3.5 50 45 3.0 On-Time (µs) On-Time (µs) 40 2.5 2.0 1.5 35 30 25 20 15 1.0 10 0.5 VCOMP = 4V 5 FF = 2.8V 0.0 VCOMP = 3V 0 0 1 2 3 4 COMP Voltage (V) Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS7300B-01 April 2016 5 0 0.5 1 1.5 2 2.5 3 Feed-Forward Voltage (V) is a registered trademark of Richtek Technology Corporation. www.richtek.com 11 RT7300B Application Information Start-Up Circuit Design VCSIN BD Line where VIN ac_min is the minimum input voltage. Note that the start-up resistor must have adequate voltage rating for reliability. 2 resistors in series can be applied for most of applications. CSIN Neutral IST RSTART IDD_ST VDD IchVDD RT7300B DVDD CVDD For example, the system required start-up time is 3sec, VIN ac_min = 75V and maximum IDD_ST = 20A. If CVDD AUX. = 22F is selected and the leakage current of CVDD can be ignored, the start-up resistor should be less than 772k. Ileakage GND The capacitor CFF is applied to filter out the input ripple voltage. The corner frequency should be lower than line frequency (f line). If the FF pin voltage is not flat, the PF and THD performance will be degraded. Figure 11. Start-Up Circuit tstart VDD VON_TH 1 < 0.1 fline 2 (RFF1 // RFF2 ) CFF VOFF_TH (10) Thermal Considerations Supplied by IST IDD IDD_ST ~20µA For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. Supplied by AUX. and IST ~ mA Figure 12. Start-Up Waveforms of VDD and IDD Figure 11 and Figure 12 show the equivalent start-up circuit and VDD waveform during start-up. In general, the start-up time (tstart) is required from system specification. The charging current (IchVDD) can be estimated by the following equation. IchVDD = CVDD VON_TH t start (8) where CVDD is the capacitor connected between VDD and GND, VON_TH is the power on threshold (16V typ.). The start-up resistor (Rstart) connected between VCSIN and VDD should be able to support the charging current (IchVDD), start-up current (IDD_ST) and leakage current (Ileakage) of CVDD before the VDD is supported by the auxiliary winding. The maximum start-up resistance can be calculated by the equation (9). 2 Vinac_min RStart = IDD_ST IchVDD Ileakage Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 12 (9) The maximum power dissipation can be calculated by the following formula : PD(MAX) = (TJ(MAX) TA) / JA where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and JA is the junction to ambient thermal resistance. For recommended operating condition specifications, the maximum junction temperature is 125C. The junction to ambient thermal resistance, JA, is layout dependent. For SOP-8 package, the thermal resistance, JA, is 160C/W on a standard JEDEC 51-3 single-layer thermal test board. The maximum power dissipation at TA = 25C can be calculated by the following formula : PD(MAX) = (125C 25C) / (160C/W) = 0.625W for SOP-8 package The maximum power dissipation depends on the operating ambient temperature for fixed TJ(MAX) and thermal resistance, JA. The derating curve in Figure is a registered trademark of Richtek Technology Corporation. DS7300B-01 April 2016 RT7300B 13 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. MOSFET, RCS return to input capacitor is also a high frequency current loop. They must be as short as possible to decrease noise coupling and kept a space to other low voltage traces, such as IC control circuit paths, especially. Besides, the path(3) between MOSFET ground(b) and IC ground(d) is recommended to be as short as possible, too. It is good for reducing noise, output ripple and EMI issue to separate ground traces of input capacitor(a), MOSFET(b), auxiliary winding(c) and IC control circuit(d). Finally, connect them together on input capacitor ground(a). The areas of these ground traces should be kept large. Figure 13. Derating Curve of Maximum Power Dissipation Placing bypass capacitor for abating noise on IC is highly recommended. The capacitors CINV and CCS should be placed as close to controller as possible. Layout Considerations A proper PCB layout can abate unknown noise interference and EMI issue in the switching power supply. Please refer to the guidelines when designing a PCB layout for switching power supply. In addition, apply sufficient copper area at the anode and cathode terminal of the diode for heat-sinking. It is recommended to apply a larger area at the quiet cathode terminal. A large anode area will induce high-frequency radiated EMI. The current path(1) from input capacitor, transformer, MOSFET, RCS return to input capacitor is a high frequency current loop. The path(2) from GD pin, BD Line VOUT+ Neutral VOUT(a) Q1 AUX RCS (1) GD ZCD CS (2) (b) RT7300B VDD AUX INV (c) VDD VDD Input capacitor Ground(a) COMP Trace FF Trace Trace (3) GND (d) IC Ground(d) Auxiliary Ground(c) MOSFET Ground(b) Figure 14. PCB Layout Guide Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS7300B-01 April 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 13 RT7300B Outline Dimension Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 4.801 5.004 0.189 0.197 B 3.810 3.988 0.150 0.157 C 1.346 1.753 0.053 0.069 D 0.330 0.508 0.013 0.020 F 1.194 1.346 0.047 0.053 H 0.170 0.254 0.007 0.010 I 0.050 0.254 0.002 0.010 J 5.791 6.200 0.228 0.244 M 0.400 1.270 0.016 0.050 8-Lead SOP Plastic Package Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 14 is a registered trademark of Richtek Technology Corporation. DS7300B-01 April 2016