Down

A80
STN1
N1A
Log
Logiic Leve
evell
al Tr
yri st
or
B i -D
-Diir ect
ectii on
ona
Trii ode Th
Thy
stor
F eatu res
■ Repetitive Peak off-State Voltage: 800V
■ R.M.S On- State Current( IT(RMS) =1A
■ Low on-state voltage: V TM =1.2(typ.)@ ITM
■ Low reverse and forward blocking current:
[email protected]=125℃
■ Low holding curr ent: IH=4mA (typ.)
■ High Commutation dV/dt.
Gener al Descript
ptiion
General purpose switc hing and phase control appli cations.
These devi ces are intended to be inter faced dir ectly to
microcontrollers,logic integrated circuits and other low power
gate trigger ci rcuits such as fan speed and temperature
modulati on control, lighting control and stati c switching relay.
s (TJ=25℃ unless otherwise specified)
Ab solute Max
axiimum Rating
ings
ol
Sy mb
mbo
P a r a m ete r
V DRM
Peak Repetitive Forward Blocking Voltage(gate open) (Note 1)
T (RMS)
Forwar d Current RMS (All Conduction Angle s, TL=50℃)
IT SM
Peak For ward Surge Current, ( full Cycle, Sine Wave, 50/60 Hz)
Circuit Fusing Considerations (tp= 10 ms)
P GM
PG (AV)
Average Gate Power — Forwar d, (Over any 20ms period)
Critical rate of rise of on-state current
U n i ts
8 00
V
1
A
9.1/10
A
0 .4 1
Peak Gate Power — Forward, ( Tc = 58°C,Pulse with≤1.0us)
dI/ dt
V a l ue
T J=125℃
5
W
0.1
W
50
A/μ s
A
ITM = 1.5A; IG = 200mA; dIG/dt = 200mA/ms
I FGM
Peak Gate Current — Forward, Tj = 125°C (20 μs, 120 PPS)
0.5
VRGM
Peak Gate Voltage — Reverse, Tj = 125°C (20 μs, 120 PPS)
6
V
TJ,
Junction Temperature
-40 ~ 125
℃
T stg
Storage Temperature
-40~150
℃
2
g
mass
Not e1 : .Although not r ecommended, off-state voltages up to 800V may be applied without damage, but the TRIAC may
switch to the on-state. The r ate of rise of curr ent should not exceed 3A/us.
Th
er mal Ch
aracteri
sti
cs
The
Cha
ris
tic
Value
Typ
Max
Symbol
Pa ra m ete r
R QJC
Thermal Resistance, Junction- to-Case
-
-
60
℃ /W
RQJA
ThermalResistance,Junction-to-Ambient
-
-
120
℃ /W
Rev. B
Min
Nov.2008
Copyr [email protected] Microelectronics Co., Ltd., All right reserved.
Units
A80
STN1
N1A
cal Ch
arac
te
ri
sti cs (T J = 25°C unless otherwise specified)
Elect ri
ric
Cha
acte
teri
ris
Symbol
I DRM
VTM
C ha ra cte ristics
Min
V D=V DRM,Single Phase, Half Wave TJ =125℃
For war d “On” Voltage ( ITM = 1.5 A)
Typ.
Max
Unit
-
-
0 .5
mA
-
1.2
1.5
V
-
0.4
5
-
1.3
5
-
1.4
5
-
3.8
7
-
-
1.2
-
-
1.2
-
-
1.2
-
-
1.5
0.2
-
-
10
20
-
1.3
5
-
1.2
5
-
4.0
8
-
1.0
5
-
2.5
8
-
-
42 0
(Note2)
T2+G+
Gate Trigger Current (C ontinuous dc)
IGT
(V D = 12 Vdc, RL = 33 Ω )
T2+GT2-G-
mA
T 2 -G +
T2 + G+
VG T
Gate Trigger Voltage (Continuous dc)
T 2+ G -
(V D =12 Vdc, RL = 33 Ω )
T2- G -
V
T 2-G +
VGD
Gate threshold voltage(TJ=125℃, VD=V DRM ,R L=3.3KΩ)
Critical rate of rise of commutation Voltage
V
-
dV/dt
V/μs
(V D=0.67VDRM,gate open)
IH
IL
Rd
Holding Current ( VD =12 V, IGT = 100 mA)
latching current ( V D = 12 V; IGT = 100 mA)
T2+G+
T2+GT2-GT2-G+
Dynamic r esistance ( TJ=125℃)
mA
mA
mΩ
Note 2. For ward current applie d for 1 ms maximum duration, duty cycle
2/5
Steady, keep you advance
A80
STN1
N1A
Fig.1 Maximum permissible non-repetitive
Peak on-state current ITSM versus number of
Cycles,for sinusoidal currents,f=50Hz.
Fig.3 Maximum permissible repetitive rms
On-state current IT (RMS),versus surge duration,
For sinusoidal currents,f=50HZ;Tlead≤66℃
Fig.2 Maximum permissible non-repetitive
Peak on-state current IT SM,versus pulse
width tp for sinusoidal currents,tp ≤20ms
Fig.4 Maximum permissible rms current
IT(RM S), versus lead temperature Tlea d
VT(V)
Fig.5 Typical and maximum on-state
characteristic
IR(RMS) A
Fig.6 Maximum on-state dissipation,Ptot
versus rms on-state current,IT (RM S) where
α=conduction angle.
3/5
Steady, keep you advance
A80
STN1
N1A
Fig.7 Normalis ed gate trigger current IGT (T i)/
IG T(25℃),versus junction temperature T i-
Fig.8 Normalised gate trigger voltage V GT (T j)/
V GT(25℃),versus junction temperature Tj-
Fig.9 Normalis ed holding current IH(Tj)/IH (25℃)
Versus junction temperature T i-
Fig.10 Transient thermal impedance Zth
j-lead,versus pulse width tp-
Fig.11 Gate Trigger Characteristics Test Circuit
4/5
Steady, keep you advance
A80
STN1
N1A
age Dim
ension
TO
TO--92 Pack
cka
Dime
5/5
Steady, keep you advance