1/13 ◇STRUCTURE Silicon Monolithic Integrated Circuit ◇PRODUCT 1,024×8 bit Electrically Erasable PROM ◇PART NUMBER BＵ9832ＧＵＬ－Ｗ ◇PHYSICAL DIMENSION Fig.1 (Plastic Mold) ◇BLOCK DIAGRAM Fig.2 ◇USE General purpose ◇FEATURES ・ 1,024 words × 8 bits architecture serial EEPROM ・Wide operating voltage range (1.8V～5.5V) ・Serial Peripheral Interface (CPOL,CPHA)=(0.0),(1.1) ･Self-timed write cycle with automatic erase ・Low power consumption Write ( 5V ) : 1.5mA (Typ.) Read ( 5V ) : 0.5mA (Typ.) Standby ( 5V ) : 0.1μA(Typ.) ･Auto-increment of registers address for Read mode ・32 byte Page Write mode ・DATA security Defaults to power up with write-disabled state Software instructions for write–enable/disable Write status register protect feature (WPB pin) Block writes protection by status register Write inhibit at low VCC ・WL-CSP package ------ VCSP50L2 ・High reliability fine pattern CMOS technology ・Initial data FFh in all address and 00h in status register ・Data retention : 40 years ・Endurance : 1,000,000 erase/write cycles ◇ ABSOLUTE MAXIMUM RATING (Ta=25℃) Parameter Symbol Rating Unit Supply Voltage VCC -0.3～6.5 V Power Dissipation Storage Temperature Operating Temperature Terminal Voltage *Degradation is done at 2.2mW/℃ Ｐｄ VCSP50L2 220 Tstg -65～125 Topr -40～85 － -0.3～VCC+0.3 for operation above 25℃ REV. B mW ℃ ℃ V 2/13 ◇RECOMMENDED OPERATING CONDITION Parameter Symbol Rating Unit Supply Voltage Vcc 1.8～5.5 V Input Voltage VIN 0～Vcc V ◇DC OPERATING CHARACTERISTICS (Unless otherwise specified Ta=-40～85℃､VCC=1.8～5.5V) Parameter Specification Symbol Unit Min. Typ. Max. test condition “H” Input Voltage1 VIH1 0.7×Vcc － Vcc+0.3 V 1.8V≦Vcc≦5.5V “L” Input Voltage1 VIL1 -0.3 － 0.3×Vcc V 1.8V≦Vcc≦5.5V “L” Output Voltage1 VOL1 0 － 0.4 V IOL=2.1mA，2.5V≦Vcc≦5.5V “L” Output Voltage2 VOL2 0 － 0.2 V IOL=100μA，1.8V≦Vcc＜2.5V “H” Output Voltage1 VOH1 Vcc-0.5 － Vcc V IOH=-0.4mA (2.5V≦Vcc≦5.5V) “H” Output Voltage2 VOH2 Vcc-0.2 － Vcc V IOH=-100μA (1.8V≦Vcc＜2.5V) Input Leakage Current ILI -1 － 1 μA VIN=0V～Vcc Output Leakage Current ILO -1 － 1 μA VOUT=0V～Vcc，CSB=Vcc Vcc=1.8V，fSCK=2MHz，tE/W=5ms ICC1 － 1.0 － mA Byte Write，Page Write Write Status Register Vcc=2.5V，fSCK=5MHz，tE/W=5ms Operating Current Write ICC2 － 2.0 － mA Byte Write，Page Write Write Status Register Vcc=5.5V，fSCK=5MHz，tE/W=5ms ICC3 － 3.0 － mA Byte Write，Page Write Write Status Register ICC3 － － 1.5 mA ICC4 － － 2.0 mA ISB － － 2.0 μA Operating Current Read Standby Current Vcc=2.5V，fSCK=5MHz Read，Read Status Register Vcc=5.5V，fSCK=5MHz Read，Read Status Register Vcc=5.5V，CS=HOLD=WP=Vcc， SCK=SI=Vcc or GND, SO=OPEN ○This product is not designed for protection against radioactive rays. ◇MEMORY CELL CHARACTERISTICS(Ta=25℃、Vcc=1.8～5.5V) Parameter Write/Erase Cycle Data Retention ※1 ※1 Min. Specification Typ. Max. 1,000,000 40 － － － － Unit Cycle Year ◇Input/Output Capacitance (Ta=25℃ frequency=5MHz) Parameter Input Capacitance ※1 Output Capacitance ※1 Symbol CIN COUT Condition VIN=GND VOUT=GND REV. B Min. - Max. Unit 8 pF 8 pF ※1:Not 100% Tested 3/13 9832 0.55 LOT NO. Fig.1 PHYSICAL DIMENSION REV. B 4/13 ◇PIN CONFIGURATION VOLTAGE DETECTION INSTRUCTION DECODE CS CONTROL CLOCK SCK GENERATION WRITE HIGH VOLTAGE INHIBITION GENERATOR INSTRUCTION SI REGISTER STATUS REGISTER ADDRESS HOLD ADDRESS 10bit REGISTER 10bit DECODER 8,192 bit EEPROM WP DATA R/W 8bit REGISTER 8bit AMP Fig.2 BLOCK DIAGRAM SO ◇PIN CONFIGURATION C1 C C2 B1 C3 B3 B INDEX A1 A2 A3 1 2 3 POST A Ｆｉｇ-3 BU9832GUL-W （bottom view） ◇PIN NAME Land No. PIN NAME I/O FUNCTION A1 WP IN Write Protect Input When WPEN bit is high in status register, WP input pin become active and is able to inhibit “Write Status Register” A2 GND － Ground （0V） A3 SI IN Start Bit，Op.code，Address，Serial Data Input B1 SO B3 C1 SCK CS OUT IN IN C2 Vcc － Power Suppｌｙ C3 HOLD IN Hold Input Hold Input is able to suspend data transmission for a time. Serial Data Output Serial Data Clock Input Chip Select Control REV. B 5/13 ◇SYNCHRONOUS DATA TIMING tCSS tCS CSB tSCKS tSCKWL tRC tSCKWH tFC SCK tDIS tDIH SI Hi-Z SO Fig.4 DATA INPUT TIMING SI data is latched into the chip at the rising edge of SCK clock. Address and data must be transferred from MSB. tCS CSB tSCKH tCSH SCK SI tPD tOZ tRO,tFO tOH Hi-Z SO Fig.5 INPUT AND OUTPUT TIMING SO data toggles at the falling edge of SCK clock. Output data toggles from MSB. "H" CSB "L" tHFS tHFH tHRS tHRH SCK tDIS SI n+1 n tHOZ SO Dn+1 n-1 tHPD Hi-Z Dn Dn Dn-1 HOLDB Fig.6 HOLD TIMING AC Condition Parameter Symbol Load Capacitance 1 Load Capacitance 2 Input Rise times Input Fall times Input Pulse Voltage CL1 CL2 - Input and Output Timing Reference Voltages - MIN - Specification TYP 0.2Vcc/0.8Vcc 0.3Vcc/0.7Vcc REV. B MAX 100 30 50 50 Unit pF pF ns ns V V 6/13 ◇AC OPERATING CHARACTERISTICS （Ｔａ＝-40～85℃） Parameter Symbol *Load capacitance1 CL1=100pF 1.8≦Vcc＜2.5V 2.5≦Vcc≦5.5V Unit Min. Typ. Max. Min. Typ. Max. fSCK - - 2 - - 5 MHz SCK High Time tSCKWH 200 - - 85 - - ns SCK Low Time tSCKWL 200 - - 85 - - ns CS High Time tCS 200 - - 85 - - ns CS Setup Time tCSS 200 - - 90 - - ns CS Hold Time tCSH 200 - - 85 - - ns SCK Setup Time tSCKS 200 - - 90 - - ns SCK Hold Time tSCKH 200 - - 90 - - ns SI Setup Time tDIS 40 - - 20 - - ns SI Hold Time tDIH 50 - - 40 - - ns Output Data Delay Time1 ｔPD1 - - 150 - - 70 ns Output Data Delay Time2 (CL2=30pF) tPD2 - - 145 - - 55 ns Output Hold Time tOH 0 - - 0 - - ns Output Disable Time tOZ - - 250 - - 100 ns Clock High Setup Time before HOLD Active. tHFS 120 - - 60 - - ns Clock Low Hold Time after HOLD Active. tHFH 90 - - 40 - - ns tHRS 120 - - 60 - - ns tHRH 140 - - 70 - - ns HOLD to Output High-Z tHOZ - - 250 - - 100 ns HOLD to Output Valid tHPD - - 150 - - 70 ns SCK clock Frequency Clock High Setup Time before HOLD not Active. Clock Low Hold Time after HOLD not Active. SCK Rise Time *1 tRC - - 1 - - 1 μs SCK Fall Time *1 tFC - - 1 - - 1 μs Output Rise Time *1 tRO - - 100 - - 50 ns Output Fall Time *1 tFO - - 100 - - 50 ns tE/W - - 5 - - 5 ms Write Cycle Time *1 Not 100% TESTED REV. B 7/13 ◇Functional Description ○Status Register The device has status register. Status register consists of 8bits and is shown following parameters. 3bits(WPEN, BP0 and BP1) are set by “Write Status Register” commands, which are non-volatile. Specification of endurance and data retention are as well as memory array. WEN bit is set by “Write enable” and “Write Disable” commands. After power become on, the device is disable mode. R/B bit is a read-only and status bit. The device is clocked out value of the status register by “Read Status Register” command input. Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 WPEN 0 0 0 BP1 BP0 WEN R/B ×:Don't care Bit WPEN BP0/BP1 WEN R/B Definition WP pin ENABLE Bit WPEN=0 ： no use WPEN=1 Protect Block write protection for memory array （EEPROM） Write enable/disable state bit WEN=0 ： write disable WEN=1 ： write enable READY／BUSY status bit R/B=0 ： READY R/B=1 ： BUSY Table1. Status Register BP1 0 0 1 1 BP0 0 1 0 1 Block Write Protection None 300h-3FFh 200h-3FFh 000h-3FFh Table2. Block Write Protection ○WP pin The device inhibits to write the data into status register during WP is low. WPEN bit in status register needs to be high to enable WP pin function. ○HOLD pin HOLD pin is able to suspend data transmission for a time (Hold state). HOLD pin is normally high for transmission of the data. SCK and SI input are “Don’t Care” and SO output state is Hi-Z for hold state. After HOLD pin is brought high to release hold state during SCK is low, the device resumes to transfer the data. For example, in case the device is hold state after A5 (the address data) input in read command, to resume the data transmission enable starting A4 (the address data) input after hold state is release. When CS is brought high with hold state, the device is reset and cannot resume the data transmission. REV. B 8/13 ◇INSTRUCTION CODE Instruction Operation Op.Code Address WREN Write enable 0000 0110 - WRDI Write disable 0000 0100 - READ Read data from memory array 0000 0011 A9 ～ A0 WRITE Write data to memory array 0000 0010 A9 ～ A0 RDSR Read status register 0000 0101 - WRSR Write status register 0000 0001 - REV. B 9/13 ◇TIMING CHART 1.WREN （WRITE ENABLE） CSB SCK SI SO 0 0 1 2 0 0 3 0 4 0 5 1 6 1 7 0 Hi-Z Fig.7 WRITE ENABLE CYCLE TIMING CSB SCK SI SO 0 0 1 0 2 0 3 0 4 0 5 1 6 0 7 0 Hi-Z Fig.8 WRITE DISABLE CYCLE TIMING 2.WRDI (WRITE DISABLE) The device has both of the enable and disable mode. After “Write Enable” is executed, the device becomes in the enable mode. After “Write Disable” is executed, the device becomes in the disable mode. After CS goes low, each of Op.code is recognized at the rising edge of 7th clock. Each of instructions is effective inputting seven or more SCK clocks. This “Write Enable” instruction must be proceeded before the any write commands. The device ignores inputting the any write commands in the disable mode. Once the any write commands is executed in the enable mode, the device becomes the disable mode. After the power become on, the device is in the disable mode. REV. B 10/13 3.READ ～ ～ ～ ～ 0 1 2 3 4 5 7 6 8 14 0 0 0 1 1 * 30 * A9 A1 A0 ～ ～ 0 ～ ～ 0 ～ ～ 0 24 ～ ～ ～ ～ SI 23 ～ ～ SCK ～ ～ ～ ～ ～ ～ CSB ～ ～ ～ ～ ～ ～ Hi-Z D7 D6 ～ ～ SO D2 D1 D0 *=Don't care Fig.9 READ CYCLE TIMING The data stored in the memory are clocked out after “Read” instruction is received. After CS goes low, the address need to be sent following by Op.code of “Read”. The data at the address specified are clocked out from D7 to D0, which is start at the falling edge of 23th clock. This device has the auto-increment feature that provides the whole data of the memory array with one read command, outputs the next address data following the addressed 8bits of data by keeping SCK clocking. When the highest address is reached, the address counter rolls over to the lowest address allowing the continuous read cycle. REV. B 11/13 4.WRITE ～ ～ ～ ～ ～ ～ CSB ～ ～ ～ ～ 0 1 3 2 5 4 6 7 8 0 1 0 * * A9 A1 A0 D7 D6 ～ ～ 0 30 31 ～ ～ 0 ～ ～ D2 D1 D0 ～ ～ ～ ～ Hi-Z 0 ～ ～ SO 0 ～ ～ 0 24 ～ ～ ～ ～ SI 23 ～ ～ SCK *=Don't care Fig.10 WRITE CYCLE TIMING This “Write” command writes 8bits of data into the specified address. After CS goes low,the address need to be sent following by Op.code of “Write”. Between the rising edge of the 31th clock and it of the 32th clock, the rising edge of CS initiates high voltage cycle, which writes the data into non-volatile memory array, but the command is cancelled if CS is high except that period. It takes maximum 5ms in high voltage cycle (tE/W). The device does not receive any command except for “Read Status Register” command during this high voltage cycle. This device is capable of writing the data of maximum 32byte into memory array at the same time, which keep inputting two or more byte data with CS “L”after 8bits of data input. For this Page Write commands, the six higher order bits of address are set, the four low order address bits are internally incremented by 5bits of data input. If more than 32 words, are transmitted the address counter “roll over”, and the previous transmitted data is overwritten. REV. B 12/13 5. RDSR (READ STATUS REGISTER) CSB SCK SI SO 0 0 1 0 2 0 Hi-Z Fig.11 3 0 4 0 6 5 1 0 7 10 8 9 11 Bit7 Bit6 Bit5 Bit4 WPBN 0 0 0 12 13 14 15 1 Bit3 Bit2 Bit1 Bit0 BP1 BP0 WEN R/B READ STATUS REGISTER CYCLE TIMING The data stored in the status register is clocked out after “Read Status Register” instruction is received. After CS goes low, Op.code of “Read Status Register” need to sent. The data stored in the status register is clocked out of the device on the falling edge of 7th clock. Bit6, Bit5 and Bit4 in the status register are read as 0. This device has the auto-increment feature as well as “Read” that outputs the 8bits of the same data following it to keep SCK clocking. It is possible to see ready and busy state by executing this command during tE/W. REV. B 13/13 5.WRSR (WRITE STATUS RESISTER) CSB SCK 0 SI SO 0 1 0 2 0 3 0 4 0 5 0 6 0 7 1 8 9 10 11 Bit7 Bit6 Bit5 Bit4 WPEN * * * 12 Bit3 13 Bit2 BP1 BP0 14 15 Bit1 Bit0 * * Hi-Z *=Don't care Fig.12 WRITE STATUS REGISTER WRITE CYCLE TIMING This “Write Status Register” command writes the data, two (BP1, BP0) of the eight bits, into the status register. Write protection is set by BP1 and BP0 bits. After CS goes low, Op.code of “Read Status Register” need to sent. Between the rising edgeof the 15th clock and it of the 16th clock, the rising edge of CS initiates high voltage cycle, which writes the data into non-volatile memory array, but the command is cancelled if CS is high exceptthat period. It takes maximum 5ms in high voltage cycle (tE/W) as well as “Write”.Block write protection is determined by BP1 and BP0 bits, which is selected from quarter, half and the entire memory array. (See Table2 BLOCK WRITE PROTECTION.) REV. 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