INTERSIL HA9P2556-9Z

HA-2556
®
Data Sheet
April 29, 2008
57MHz, Wideband, Four Quadrant,
Voltage Output Analog Multiplier
FN2477.6
Features
• High Speed Voltage Output . . . . . . . . . . . . . . . . . 450V/µs
The HA-2556 is a monolithic, high speed, four quadrant,
analog multiplier constructed in the Intersil Dielectrically
Isolated High Frequency Process. The voltage output
simplifies many designs by eliminating the current-to-voltage
conversion stage required for current output multipliers. The
HA-2556 provides a 450V/µs slew rate and maintains
52MHz and 57MHz bandwidths for the X and Y channels
respectively, making it an ideal part for use in video systems.
The suitability for precision video applications is
demonstrated further by the Y-Channel 0.1dB gain flatness
to 5.0MHz, 1.5% multiplication error, -50dB feedthrough and
differential inputs with 8µA bias current. The HA-2556 also
has low differential gain (0.1%) and phase (0.1°) errors.
• Low Multiplication Error . . . . . . . . . . . . . . . . . . . . . . . 1.5%
• Input Bias Currents . . . . . . . . . . . . . . . . . . . . . . . . . . .8µA
• 5MHz Feedthrough . . . . . . . . . . . . . . . . . . . . . . . . . -50dB
• Wide Y-Channel Bandwidth . . . . . . . . . . . . . . . . . . 57MHz
• Wide X-Channel Bandwidth . . . . . . . . . . . . . . . . . . 52MHz
• VY 0.1dB Gain Flatness . . . . . . . . . . . . . . . . . . . . 5.0MHz
• Pb-free available (RoHS compliant)
Applications
• Military Avionics
The HA-2556 is well suited for AGC circuits as well as mixer
applications for sonar, radar, and medical imaging
equipment. The HA-2556 is not limited to multiplication
applications only; frequency doubling, power detection, as
well as many other configurations are possible.
• Missile Guidance Systems
For MIL-STD-883 compliant product consult the
HA-2556/883 datasheet.
• Radar Signal Conditioning
PART
MARKING
HA9P2556-9
HA9P2556 -9
• Sonar AGC Processors
• Vector Generators
TEMP
RANGE (°C)
PACKAGE
PKG
DWG. #
-40 to +85
16 Ld SOIC
M16.3
HA9P2556-9Z HA9P2556 -9Z
(Note)
-40 to +85
16 Ld SOIC
(Pb-free)
M16.3
HA1-2556-9
-40 to +85
16 Ld CERDIP F16.3
HA1-2556-9
• Video Mixers
• Voltage Controlled Amplifier
Ordering Information
PART
NUMBER
• Medical Imaging Displays
NOTE: These Intersil Pb-free plastic packaged products employ special
Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Functional Block Diagram
HA-2556
VX+
VOUT
+
VX-
-
A
X
+
1/SF
VY+
+
-
VY-
∑
Y
Z
VZ+
+
-
VZ-
NOTE: The transfer equation for the HA-2556 is:
(VX+ -VX-) (VY+ -VY-) = SF (VZ+ -VZ-),
where SF = Scale Factor = 5V; VX, VY,
VZ = Differential Inputs.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 1998, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HA-2556
Pinout
HA-2556
(16 LD CERDIP, SOIC)
TOP VIEW
16 VXIOA
GND 1
VREF 2
REF
15 VXIOB
14 NC
VYIOB 3
VYIOA 4
VY+ 5
VY - 6
V- 7
VOUT 8
2
X
13 VX+
12 VX-
Y
11 V+
+
Σ
-
Z
10 VZ 9 VZ +
FN2477.6
April 29, 2008
HA-2556
Absolute Maximum Ratings
Thermal Information
Voltage Between V+ and V- Terminals. . . . . . . . . . . . . . . . . . . . 35V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±60mA
Thermal Resistance (Typical, Note 1)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
θJA (°C/W)
θJC (°C/W)
16 Ld SOIC Package . . . . . . . . . . . . . .
90
N/A
16 Ld CERDIP Package. . . . . . . . . . . .
75
20
Maximum Junction Temperature (Ceramic Package) . . . . . . . +175°C
Maximum Junction Temperature (Plastic Packages) . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . -65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
VSUPPLY = ±15V, RF = 50Ω, RL = 1kΩ, CL = 20pF, Unless Otherwise Specified.
PARAMETER
TEST CONDITIONS
TEMP (°C)
MIN
(Note 10)
TYP
MAX
(Note 10)
UNITS
MULTIPLIER PERFORMANCE
Transfer Function
( V X+ – V X- ) × ( V Y+ – V Y- )
V OUT = A -------------------------------------------------------------------- – ( V Z+ – V Z- )
5
Multiplication Error
(Note 2)
25
-
1.5
3
%
Full
-
3.0
6
%
Multiplication Error Drift
Full
-
0.003
-
%/°C
Scale Factor
25
-
5
-
V
VX, VY = ±3V, Full Scale = 3V
25
-
0.02
-
%
VX, VY = ±4V, Full Scale = 4V
25
-
0.05
0.25
%
VX, VY = ±5V, Full Scale = 5V
25
-
0.2
0.5
%
VY = 200mVP-P, VX = 5V
25
-
57
-
MHz
VX = 200mVP-P, VY = 5V
25
-
52
-
MHz
Full Power Bandwidth (-3dB)
10VP-P
25
-
32
-
MHz
Slew Rate
(Note 5)
25
420
450
-
V/µs
Rise Time
(Note 6)
25
-
8
-
ns
Linearity Error
AC CHARACTERISTICS
Small Signal Bandwidth (-3dB)
Overshoot
(Note 6)
25
-
20
-
%
Settling Time
To 0.1%, (Note 5)
25
-
100
-
ns
Differential Gain
(Note 3)
25
-
0.1
0.2
%
Differential Phase
(Note 3)
25
-
0.1
0.3
°
VY 0.1dB Gain Flatness
200mVP-P, VX = 5V,
25
4.0
5.0
-
MHz
VX 0.1dB Gain Flatness
200mVP-P, VY = 5V,
25
2.0
4.0
-
MHz
THD + N
(Note 4)
25
-
0.03
-
%
1MHz Feedthrough
200mVP-P, Other Channel Nulled
25
-
-65
-
dB
5MHz Feedthrough
200mVP-P, Other Channel Nulled
25
-
-50
-
dB
Input Offset Voltage
25
-
3
15
mV
Full
-
8
25
mV
Average Offset Voltage Drift
Full
-
45
-
µV/°C
Input Bias Current
25
-
8
15
µA
Full
-
12
20
µA
SIGNAL INPUT (VX, VY, VZ)
3
FN2477.6
April 29, 2008
HA-2556
Electrical Specifications
VSUPPLY = ±15V, RF = 50Ω, RL = 1kΩ, CL = 20pF, Unless Otherwise Specified. (Continued)
PARAMETER
TEST CONDITIONS
Input Offset Current
TEMP (°C)
MIN
(Note 10)
TYP
MAX
(Note 10)
UNITS
25
-
0.5
2
µA
Full
-
1.0
3
µA
Differential Input Resistance
25
-
1
-
MΩ
Full Scale Differential Input (VX, VY, VZ)
25
±5
-
-
V
VX Common Mode Range
25
-
±10
-
V
VY Common Mode Range
25
-
+9, -10
-
V
CMRR Within Common Mode Range
Full
65
78
-
dB
f = 1kHz
25
-
150
-
nV/√Hz
f = 100kHz
25
-
40
-
nV/√Hz
(Note 9)
Full
±5.0
±6.05
-
V
Output Current
Full
±20
±45
-
mA
Output Resistance
25
-
0.7
1.0
Ω
Voltage Noise (Note 8)
OUTPUT CHARACTERISTICS
Output Voltage Swing
POWER SUPPLY
+PSRR
(Note 7)
Full
65
80
-
dB
-PSRR
(Note 7)
Full
45
55
-
dB
Full
-
18
22
mA
Supply Current
NOTES:
2. Error is percent of full scale, 1% = 50mV.
3. f = 4.43MHz, VY = 300mVP-P, 0VDC to 1VDC offset, VX = 5V.
4. f = 10kHz, VY = 1VRMS, VX = 5V.
5. VOUT = 0V to ±4V.
6. VOUT = 0mV to ±100mV.
7. VS = ±12V to ±15V.
8. VX = VY = 0V.
9. VX = 5.5V, VY = ±5.5V.
10. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
4
FN2477.6
April 29, 2008
HA-2556
Simplified Schematic
V+
VBIAS
VBIAS
VX+
VX-
VY+
REF
VCC
VYVZ +
OUT
VZ -
+
-
VXIO A
VXIOB
VYIO A
GND
Application Information
Operation at Reduced Supply Voltages
The HA-2556 will operate over a range of supply voltages,
±5V to ±15V. Use of supply voltages below ±12V will reduce
input and output voltage ranges. See “Typical Performance
Curves” on page 12 for more information.
Offset Adjustment
X-Channel and Y-Channel offset voltages may be nulled by
using a 20k potentiometer between the VYIO or VXIO adjust
pin A and B and connecting the wiper to V-. Reducing the
channel offset voltage, will reduce AC feedthrough and
improve the multiplication error. Output offset voltage can
also be nulled by connecting VZ- to the wiper of a
potentiometer which is tied between V+ and V-.
Capacitive Drive Capability
When driving capacitive loads >20pF a 50Ω resistor should
be connected between VOUT and VZ+, using VZ+ as the
output (see Figure 1). This will prevent the multiplier from
going unstable and reduce gain peaking at high frequencies.
The 50Ω resistor will dampen the resonance formed with the
capacitive load and the inductance of the output at Pin 8.
Gain accuracy will be maintained because the resistor is
inside the feedback loop.
Theory of Operation
The HA-2556 creates an output voltage that is the product
of the X and Y input voltages divided by a constant scale
factor of 5V. The resulting output has the correct polarity in
each of the four quadrants defined by the combinations of
positive and negative X and Y inputs. The Z stage provides
the means for negative feedback (in the multiplier
configuration) and an input for summation into the output.
5
V-
VYIOB
This results in Equation 1, where X, Y and Z are high
impedance differential inputs.
1
NC
2
REF
16
NC
15
NC
NC
VX+
NC
3
14
NC
4
13
VY+
5
6
-15V
7
+
-
+
-
12
11
+
Σ
8
- +
10
9
+15V
VZ VZ +
50Ω
1kΩ
VOUT
20pF
FIGURE 1. DRIVING CAPACITIVE LOAD
XxY
V OUT = Z = -------------5
(EQ. 1)
To accomplish this the differential input voltages are first
converted into differential currents by the X and Y input
transconductance stages. The currents are then scaled by a
constant reference and combined in the multiplier core. The
multiplier core is a basic Gilbert Cell that produces a
differential output current proportional to the product of X and
Y input signal currents. This current becomes the output for
the HA-2557.
The HA-2556 takes the output current of the core and feeds it
to a transimpedance amplifier, that converts the current to a
voltage. In the multiplier configuration, negative feedback is
provided with the Z transconductance amplifier by connecting
VOUT to the Z input. The Z stage converts VOUT to a current
which is subtracted from the multiplier core before being
applied to the high gain transimpedance amp. The Z stage, by
virtue of it’s similarity to the X and Y stages, also cancels
FN2477.6
April 29, 2008
HA-2556
second order errors introduced by the dependence of VBE on
collector current in the X and Y stages.
The purpose of the reference circuit is to provide a stable
current, used in setting the scale factor to 5V. This is
achieved with a bandgap reference circuit to produce a
temperature stable voltage of 1.2V which is forced across a
NiCr resistor. Slight adjustments to scale factor may be
possible by overriding the internal reference with the VREF
pin. The scale factor is used to maintain the output of the
multiplier within the normal operating range of ±5V when
full scale inputs are applied.
The Balance Concept
The open loop transfer for the HA-2556 is calculated using
Equation 2:
( V X+ -V X- ) x ( V Y+ – V Y- )
V OUT = A ------------------------------------------------------------------- - ( V Z+ -V Z- )
5V
(EQ. 2)
Signals A and B are input to the multiplier and the signal W
is the result. By substituting the signal values into the
Balance equation yields Equation 5:
And solving for W yields Equation 6:
AxB
W = -------------5
(EQ. 6)
Notice that the output (W) enters the equation in the
feedback to the Z stage. The Balance Equation does not test
for stability, so remember that you must provide negative
feedback. In the multiplier configuration, the feedback path is
connected to VZ+ input, not VZ-. This is due to the inversion
that takes place at the summing node just prior to the output
amplifier. Feedback is not restricted to the Z stage, other
feedback paths are possible as in the Divider Configuration
shown in Figure 3.
HA-2556
VX+
where;
A =
(EQ. 5)
(A) x (B) = 5(W)
VOUT
+
-
Output Amplifier Open Loop Gain
VX, VY, VZ =
VX1/5V
VY+
5V = Fixed Scaled Factor
B
An understanding of the transfer function can be gained by
assuming that the open loop gain, A, of the output amplifier
is infinite. With this assumption, any value of VOUT can be
generated with an infinitesimally small value for the terms
within the brackets. Therefore we can write Equation 3:
(EQ. 3)
which simplifies to Equation 4:
(EQ. 4)
This form of the transfer equation provides a useful tool to
analyze multiplier application circuits and will be called the
Balance Concept.
Typical Applications
Let’s first examine the Balance Concept as it applies to the
standard multiplier configuration (Figure 2).
VX+
HA-2556
-
A
+
-
VY+
B
+
W
X
1/5V
Y
Z
-
VZ +
+
-
VY-
A
VZ -
FIGURE 3. DIVIDER
Inserting the signal values A, B and W into the Balance
Equation for the divider configuration yields Equation 7:
(EQ. 7)
( -W ) ( B ) = 5V x ( -A )
(EQ. 8)
5A
W = ------B
Notice that, in the divider configuration, signal B must remain
≥0 (positive) for the feedback to be negative. If signal B is
negative, then it will be multiplied by the VX- input to produce
positive feedback and the output will swing into the rail.
Signals may be applied to more than one input at a time as
in the Squaring configuration in Figure 4:
(A) x (A) = 5(W)
(EQ. 9)
∑
Z
-
Y
∑
Here the Balance equation will appear as Equation 9:
VOUT
+
VX-
-
Solving for W yields Equation 8:
( V X+ -V X- ) x ( V Y+ -V Y- ) = 5V ( V Z+ -V Z- )
A
+
W
X
+
Differential Input Voltages
( V X+ -V X- ) x ( V Y+ -V Y- )
0 = ----------------------------------------------------------------- - ( V Z+ -V Z- )
5V
A
VZ +
+
-
VY-
VZ -
FIGURE 2. MULTIPLIER
6
FN2477.6
April 29, 2008
HA-2556
A
Square Root
HA-2556
VX+
+
VX-
A
-
W
X
+
1/5V
∑
-
VY+
Y
+
VY -
VOUT
VZ +
Z
+
-
-
VZ -
FIGURE 4. SQUARE
Communications
Which simplifies to Equation 10:
(EQ. 10)
A2
W = ------5
The last basic configuration is the Square Root as shown in
Figure 5. Here feedback is provided to both X and Y inputs.
HA-2556
VX+
VOUT
+
-
VX-
VY+
+
W
A
X
The Multiplier configuration has applications in AM Signal
Generation, Synchronous AM Detection and Phase
Detection to mention a few. These circuit configurations are
shown in Figures 6, 7 and 8. The HA-2556 is particularly
useful in applications that require high speed signals on all
inputs.
ACos(ωΑτ)
VX+
-
VX-
Y
∑
Z
-
CCos(ωCτ)
+
A
VZ -
VY+
+
W
X
+
-
∑
Y
VZ +
Z
+
-
CARRIER
-
VY-
FIGURE 5. SQUARE ROOT (FOR A > 0)
VZ -
AC
W = -------- ( Cos ( ω C – ω A )τ + Cos ( ω C + ω A )τ )
10
FIGURE 6. AM SIGNAL GENERATION
The Balance equation takes the form of Equation 11:
( W ) × ( –W ) = 5 ( –A )
VOUT
A
1/5V
VZ +
-
VY-
(EQ. 11)
AM SIGNAL
VX+
VX-
(EQ. 12)
5A
HA-2556
VOUT
+
Which equates to Equation 12:
W =
HA-2556
+
AUDIO
+
1/5V
The Square Root function can serve as a precision/wide
bandwidth compander for audio or video applications. A
compander improves the Signal-to-Noise Ratio for your
system by amplifying low level signals while attenuating or
compressing large signals (refer to Figure 17; X0.5 curve).
This provides for better low level signal immunity to noise
during transmission. On the receiving end, the original signal
may be reconstructed with the standard Square function.
-
X
+
1/5V
The four basic configurations (Multiply, Divide, Square and
Square Root) as well as variations of these basic circuits
have many uses.
VY+
CARRIER
+
W
A
-
∑
Y
VZ+
Z
+
-
-
VY-
VZ-
LIKE THE FREQUENCY DOUBLER YOU GET AUDIO CENTERED AT DC
AND 2FC.
Frequency Doubler
For example, if ACos(ωτ) is substituted for signal A in the
Square function, then it becomes a Frequency Doubler and
the equation takes the form of Equation 13:
( ACos ( ωτ ) ) × ( ACos ( ωτ ) ) = 5 ( W )
(EQ. 13)
FIGURE 7. SYNCHRONOUS AM DETECTION
VX-
-
A
+
VY+
+
(EQ. 14)
-
W
X
1/5V
ACos(ωτ+φ)
W = ------- ( 1 + Cos ( 2ωτ ) )
10
VOUT
+
And using some trigonometric identities gives the result in
Equation 14:
A2
HA-2556
VX+
ACos(ωτ)
Y
∑
Z
VZ +
+
-
VY-
VZ -
A2
W = ------- ( Cos ( φ ) + Cos ( 2ωτ + φ ) )
10
DC COMPONENT IS PROPORTIONAL TO COS(f)
FIGURE 8. PHASE DETECTION
7
FN2477.6
April 29, 2008
HA-2556
Each input X, Y and Z have similar wide bandwidth and input
characteristics. This is unlike earlier products where one
input was dedicated to a slow moving control function as is
required for Automatic Gain Control. The HA-2556 is
versatile enough for both.
Although the X and Y inputs have similar AC characteristics,
they are not the same. The designer should consider input
parameters such as small signal bandwidth, AC feedthrough
and 0.1dB gain flatness to get the most performance from
the HA-2556. The Y-Channel is the faster of the two inputs
with a small signal bandwidth of typically 57MHz vs 52MHz
for the X-Channel. Therefore in AM Signal Generation, the
best performance will be obtained with the Carrier applied to
the Y-Channel and the modulation signal (lower frequency)
applied to the X-Channel.
Scale Factor Control
VX+
HA-2556
VOUT
+
-
VX-
A
+
1/5V
B
W
X
-
VY+
+
A×B
1
I OUT = -------------- × -------------------------------5
R CONVERT
Y
∑
Z
VZ +
1kΩ
RF
The Video Fader circuit provides a unique function. Here
Channel B is applied to the minus Z input in addition to the
minus Y input. In this way, the function in Figure 11 is
generated. VMIX will control the percentage of Channel A and
Channel B that are mixed together to produce a resulting
video image or other signal.
HA-2556
VX+
VY-
-
VX-
VZ -
+
B
VY+
+
-
∑
Y
(EQ. 15)
VZ +
Z
+
-
-
VY-
VZ -
FIGURE 10. CURRENT OUTPUT
The Balance equation looks like Equation 17:
( V MIX ) × ( ChA – ChB ) = 5 ( V OUT – ChB )
(EQ. 17)
Which simplifies to Equation 18:
(EQ. 18)
V MIX
V OUT = ChB + -------------- ( ChA – ChB )
5
When VMIX is 0V the equation becomes VOUT = ChB and
ChA is removed, conversely when VMIX is 5V the equation
becomes VOUT = ChA eliminating ChB. For VMIX values 0V
≤ VMIX ≤ 5V the output is a blend of ChA and ChB.
250Ω
RG
One caveat is that the output bandwidth will also drop by this
factor of 5. The multiplier equation then becomes
Equation 15:
IOUT
X
1
FIGURE 9. EXTERNAL GAIN OF 5
5AB
W = ------------ = A × B
5
A
1/5V
+
RF
ExternalGain = -------- + 1
RG
VOUT RCONVERT
+
-
-
(EQ. 16)
Video Fader
A
The HA-2556 is able to operate over a wide supply voltage
range ±5V to ±17.5V. The ±5V range is particularly useful in
video applications. At ±5V the input voltage range is reduced
to ±1.4V. The output cannot reach its full scale value with
this restricted input, so it may become necessary to modify
the scale factor. Adjusting the scale factor may also be
useful when the input signal itself is restricted to a small
portion of the full scale level. Here, we can make use of the
high gain output amplifier by adding external gain resistors.
Generating the maximum output possible for a given input
signal will improve the Signal-to-Noise Ratio and Dynamic
Range of the system. For example, let’s assume that the
input signals are 1VPEAK each then, the maximum output for
the HA-2556 will be 200mV. (1V x 1V)/(5V) = 200mV. It
would be nice to have the output at the same full scale as
our input, so let’s add a gain of 5 as shown in Figure 9.
A
100MHz of bandwidth, but its scale factor is fixed and does not
have an output amplifier for additional scaling. Fortunately, the
circuit in Figure 10 provides an output current that can be
scaled with the value of RCONVERT and provides an output
impedance of typically 1MΩ. IOUT then becomes Equation 16:
ChA
VY+
ChB
VY-
NC
2
NC
3
NC
4
-15V
5
6
REF
+
-
+
-
16
NC
15
NC
14
NC
VX +
13
12
11
+
7
Σ
8
- +
VMIX
(0V TO 5V)
10
9
+15V
VZ VZ +
VOUT
50Ω
FIGURE 11. VIDEO FADER
Current Output
Another useful circuit for low voltage applications allows the
user to convert the voltage output of the HA2556 to an output
current. The HA-2557 is a current output version offering
8
Other Applications
As previously shown, a function may contain several
different operators at the same time and use only one
FN2477.6
April 29, 2008
HA-2556
HA-2556. Some other possible multi-operator functions are
shown in Figures 12, 13 and 14.
control input. At DC the circuit is an integrator automatically
compensating for Offset and other constant error terms.
Of course the HA-2556 is also well suited to standard
multiplier applications such as Automatic Gain Control and
Voltage Controlled Amplifier.
This multiplier has the advantage over other AGC circuits, in
that the signal bandwidth is not affected by the control signal
gain adjustment.
A
HA-2556
VX+
+
5k
A
-
VX-
+
VY+
-
Y
+
∑
5k
VZ +
Z
+
-
5k
-
VY-
5k
VZ -
NC
2
NC
3
NC
4
VY+
5
6
FIGURE 12. DIFFERENCE OF SQUARES
V-
VOUT
+
-
VX+
A
+
A-B
W = 100 A
∑
Y
B
+
-
10kΩ
VZ 5kΩ
R1 and R2 set scale to 1V/%, other scale factors possible.
For A ≥ 0V.
FIGURE 13. PERCENTAGE DEVIATION
HA-2556
VX-
VOUT
+
A
10
Z
9
0.1μF
+15V
0.01μF
-
+
HA-5127
5.6V
0.1μF
A-B
W = 10 B + A
∑
Y
Z
-
5k
-
FIGURE 15. AUTOMATIC GAIN CONTROL
Voltage Controlled Amplifier
+
+
Σ
20kΩ
X
1/5V
VY+
11 V+
+
50Ω
VZ +
Z
VY-
-
12
Y
1N914
-
VX+
13
X
10kΩ
+
VY+
14 NC
7
X
1/5V
A
15 NC
VOUT
HA-2556
R2
VX-
REF
8
95k
R1
5k
16 NC
1
X
1/5V
B
HA-2556
W = 5(A2-B2)
VZ +
B
A
+
-
VY-
VZ -
5k
A wide range of gain adjustment is available with the Voltage
Controlled Amplifier configuration shown in Figure 16. Here
the gain of the HFA0002 can be swept from 20V/V to a gain
of almost 1000V/V with a DC voltage from 0V to 5V.
Wave Shaping Circuits
FIGURE 14. DIFFERENCE DIVIDED BY SUM S (For A + B ≥ 0V)
Automatic Gain Control
Figure 15 shows the HA-2556 configured in an Automatic
Gain Control or AGC application. The HA-5127 low noise
amplifier provides the gain control signal to the X input. This
control signal sets the peak output voltage of the multiplier to
match the preset reference level. The feedback network
around the HA-5127 provides a response time adjustment.
High frequency changes in the peak are rejected as noise or
the desired signal to be transmitted. These signals do not
indicate a change in the average peak value and therefore
no gain adjustment is needed. Lower frequency changes in
the peak value are given a gain of -1 for feedback to the
9
Wave shaping or curve fitting is another class of application
for the analog multiplier. For example, where a nonlinear
sensor requires corrective curve fitting to improve linearity
the HA-2556 can provide nonintegral powers in the range of
1 to 2 or nonintegral roots in the range of 0.5 to 1.0 (refer to
“References” on page 11). This effect is displayed in
Figure 17.
FN2477.6
April 29, 2008
HA-2556
Figure 18 compares the function VOUT = VIN0.7 to the
approximation VOUT = 0.5VIN0.5 + 0.5VIN.
.
HA-2556
REF
15 NC
NC 4
X
5
6
0.8
14 NC
NC 3
Y
13 VX + (VGAIN)
OUTPUT (V)
NC 2
1.0
16 NC
1
12
11 V+
+
V- 7
Σ
-
10
X0.7
0.6
0.5X0.5+ 0.5X
0.4
Z
9
8
0.2
X
0
5kΩ
500Ω
-
1.0
X0.5
X0.7
0.6
0.6
16 NC
1
X1.5
X2
0.2
NC
2
NC
3
NC
0.2
0.4
0.6
INPUT (V)
0.8
1.0
6
V-
FIGURE 17. EFFECT OF NONINTEGRAL POWERS/ROOTS
A multiplier can’t do nonintegral roots “exactly”, but it can
yield a close approximation. We can approximate
nonintegral roots with Equations 19 and 20 of the form:
V O = ( 1 – α )V IN 2 + αV IN
(EQ. 19)
7
8
0.5 ≤ M ≤ 1.0
0V ≤ VIN ≤ 1V
REF
15 NC
14 NC
+
4
5
0
1.0
HA-2556
0.4
0
0.8
This function can be easily built using an HA-2556 and a
potentiometer for easy adjustment as shown in Figures 19 and
20. If a fixed nonintegral power is desired, the circuit shown in
Figure 21 eliminates the need for the output buffer amp. These
circuits approximate the function VINM where M is the desired
nonintegral power or root.
FIGURE 16. VOLTAGE CONTROLLED AMPLIFIER
.
OUTPUT (V)
0.4
FIGURE 18. COMPARE APPROXIMATION TO NONINTEGRAL
ROOT
HFA0002
0.8
0.2
INPUT (V)
+
VOUT
0
VIN
X
+
13
- 12
Y
11 V+
+
Σ
-
+
Z
-
10
9
-
+
1-α
VIN
α
VOUT
HA-5127
FIGURE 19. NONINTEGRAL ROOTS - ADJUSTABLE
V O = ( 1 – α )V IN 1/2 + αV IN
(EQ. 20)
10
FN2477.6
April 29, 2008
HA-2556
Sine Function Generators
HA-2556
REF
NC 2
15 NC
14 NC
NC 3
+
NC 4
5
6
V-
Similar functions can be formulated to approximate a SINE
function converter as shown in Figure 22. With a linearly
changing (0V to 5V) input the output will follow 0° to 90° of a
sine function (0V to 5V) output. This configuration is
theoretically capable of ±2.1% maximum error to full scale.
16 NC
1
X
+
VIN
13
- 12
Y
11 V+
+
7
Σ
-
+
Z
8
-
By adding a second HA-2556 to the circuit an improved fit
may be achieved with a theoretical maximum error of ±0.5%
as shown in Figure 23. Figure 23 has the added benefit that it
will work for positive and negative input signals. This makes a
convenient triangle (±5V input) to sine wave (±5V output)
converter.
1-α
10
α
9
1.0 ≤ M ≤ 2.0
VOUT
-
0V ≤ VIN ≤ 1V
HA-2556
+
HA-5127
NC
2
NC
3
NC
4
HA-2556
3
NC
4
5
6
VOUT
REF
2
NC
+
X
+
1.2 ≤ M ≤ 2.0
6
VIN
13
11
+-
Σ
+
Z
+
X
+
R2
470
R6
470
R1
262
1410
13
- 12
Y
11 V+
+
7
Σ
-
+
Z
-
10
R5
9
R3 , 644
-
9
R3
R2
⎛ R3
⎞ ⎛ R2 ⎞
α = ⎜ ------- + 1⎟ ⎜ ---------------------⎟
⎝ R4
⎠ ⎝ R 1 + R 2⎠
(EQ. 21)
(EQ. 22)
Values for α to give a desired M root or power are as follows:
ROOTS - FIGURE 19
POWERS - FIGURE 20
M
α
M
α
0.5
0
1.0
1
0.6
1.2
0.9
≈0.25
≈0.50
≈0.70
≈0.85
1.8
≈0.75
≈0.50
≈0.30
≈0.15
1.0
1
2.0
0
1.4
1.6
11
R4, 1k
FIGURE 22. SINE-FUNCTION GENERATOR
References
R4
Setting:
0.8
14 NC
R1
V+
10
⎞
⎛ R3
⎞ ⎛ R2 ⎞
1 ⎛ R3
V OUT = --- ⎜ ------- + 1⎟ V IN2 + ⎜ ------- + 1⎟ ⎜ ---------------------⎟ V IN
5 ⎝ R4
⎠
⎝ R4
⎠ ⎝ R 1 + R 2⎠
0.7
15 NC
8
FIGURE 21. NONINTEGRAL POWERS - FIXED
⎞
1 ⎛ R3
1 – α = --- ⎜ ------- + 1⎟
5 ⎝ R4
⎠
V-
VOUT
REF
- 12
Y
8
0V ≤ VIN ≤ 1V
5
15 NC
14 NC
7
V-
VIN
16 NC
1
NC
16 NC
1
FIGURE 20. NONINTEGRAL POWERS - ADJUSTABLE
[1] Pacifico Cofrancesco, “RF Mixers and Modulators made
with a Monolithic Four-Quadrant Multiplier” Microwave
Journal, December 1991 pg. 58 - 70.
[2] Richard Goller, “IC Generates Nonintegral Roots”
Electronic Design, December 3, 1992.
( 1 – 0.1284V IN )
π V IN
V OUT = V IN --------------------------------------------------- ≈ 5sin ⎛ --- ⋅ ---------⎞
⎝2 5 ⎠
( 0.6082 – 0.05V IN )
for; 0V ≤ VIN ≤ 5V
where:
R4 ;
0.6082 = --------------------R3 + R4
(EQ. 23)
Max Theoretical Error = 2.1%FS
R2
5 ( 0.1284 ) = --------------------R1 + R2
R6
5 ( 0.05 ) = --------------------R5 + R6
(EQ. 24)
3
5V IN – 0.05494V IN
π V IN
V OUT = ------------------------------------------------------------------- ≈ 5sin ⎛ --- ⋅ ---------⎞
⎝
2
2 5 ⎠
3.18167 + 0.0177919V
(EQ. 25)
IN
for; -5V ≤ VIN ≤ 5V
Max Theoretical Error = 0.5%FS
FN2477.6
April 29, 2008
HA-2556
71.5k
23.1k
X+
VOUT
X-
VIN
X+
10k
X-
VOUT
HA-2556
Y+
Z+
Y-
Z-
VOUT
5.71k
HA-2556
Y+
Z+
Y-
Z-
10k
FIGURE 23. BIPOLAR SINE-FUNCTION GENERATOR
Typical Performance Curves
1.5
1.0
Y = -4
Y = -5
1.0
Y = -3
Y=0
ERROR (%FS)
ERROR (%FS)
0.5
0
Y=1
Y=3
Y=4
Y = -1
Y=0
0
-0.5
-1.0
Y=5
-4
0.5
Y=2
-0.5
-1
-6
Y = -2
-2
0
2
4
-1.5
6
-6
-4
-2
X INPUT (V)
0
2
4
6
X INPUT (V)
FIGURE 24. X-CHANNEL MULTIPLIER ERROR
FIGURE 25. X-CHANNEL MULTIPLIER ERROR
1.5
1.0
X = -3
X = -2
1.0
0.5
0.5
ERROR (%FS)
ERROR (%FS)
X = -4
X = -1
X=0
0
X=0
0
X=5
X=1
-0.5
X = -5
X=2
-1.0
-0.5
X=4
X=3
-1.0
-6
-4
-2
0
2
4
Y INPUT (V)
FIGURE 26. Y-CHANNEL MULTIPLIER ERROR
12
6
-1.5
-6
-4
-2
0
2
4
6
Y INPUT (V)
FIGURE 27. Y-CHANNEL MULTIPLIER ERROR
FN2477.6
April 29, 2008
HA-2556
(Continued)
8
200
4
100
OUTPUT (mV)
OUTPUT (V)
Typical Performance Curves
0
0
-100
-4
VY = ±100mV PULSE
VX = 5VDC
VX = ±4V PULSE
VY = 5VDC
-200
-8
0ns
500ns
0ns
1µs
250ns
FIGURE 28. LARGE SIGNAL RESPONSE
4
3
FIGURE 29. SMALL SIGNAL RESPONSE
Y-CHANNEL = 10VP-P
X-CHANNEL = 5VDC
4
3
Y-CHANNEL = 4VP-P
X-CHANNEL = 5VDC
2
1
GAIN (dB)
GAIN (dB)
2
0
-1
1
0
-1
-2
-2
-3
-3
-3dB
AT 32.5MHz
-4
10k
100k
1M
-4
10k
10M
100k
FREQUENCY (Hz)
X-CHANNEL = 4VP-P
Y-CHANNEL = 5VDC
4
3
2
2
1
1
GAIN (dB)
GAIN (dB)
X-CHANNEL = 10VP-P
Y-CHANNEL = 5VDC
0
-1
0
-1
-2
-2
-3
-3
-4
-4
100k
1M
10M
FREQUENCY (Hz)
FIGURE 32. X-CHANNEL FULL POWER BANDWIDTH
13
10M
FIGURE 31. Y-CHANNEL FULL POWER BANDWIDTH
3
10k
1M
FREQUENCY (Hz)
FIGURE 30. Y-CHANNEL FULL POWER BANDWIDTH
4
500ns
50mV/DIV; 50ns/DIV
2V/DIV; 100ns/DIV
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 33. X-CHANNEL FULL POWER BANDWIDTH
FN2477.6
April 29, 2008
HA-2556
Typical Performance Curves
(Continued)
0
0
VY = 5VDC
VX = 5VDC
-6
GAIN (dB)
GAIN (dB)
-6
VX = 2VDC
-12
-18
VY = 2VDC
-12
-18
VY = 0.5VDC
-24
VY = 200mVP-P
VX = 0.5VDC
10k
100k
1M
10M
-24
VX = 200mVP-P
10k
100M
100k
VY +, VY- = 200mVRMS
VX = 5VDC
-10
-20
-30
CMRR (dB)
CMRR (dB)
VX +, VX - = 200mVRMS
VY = 5VDC
-20
-30
-40
-50
5MHz
-38.8dB
-60
-50
-60
-70
-80
-80
100k
1M
10M
5MHz
-26.2dB
-40
-70
10k
10k
100M
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 37. X-CHANNEL CMRR vs FREQUENCY
FIGURE 36. Y-CHANNEL CMRR vs FREQUENCY
0
0
VX = 200mVP-P
VY = 200mVP-P
VX = NULLED
-10
VY = NULLED
-20
FEEDTHROUGH (dB)
FEEDTHROUGH (dB)
100M
0
0
-10
-20
10M
FIGURE 35. X-CHANNEL BANDWIDTH vs Y-CHANNEL
FIGURE 34. Y-CHANNEL BANDWIDTH vs X-CHANNEL
-10
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
-30
-40
-52.6dB
AT 5MHz
-50
-60
-70
-80
-30
-49dB
AT 5MHz
-40
-50
-60
-70
-80
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 38. FEEDTHROUGH vs FREQUENCY
14
100M
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 39. FEEDTHROUGH vs FREQUENCY
FN2477.6
April 29, 2008
HA-2556
Typical Performance Curves
(Continued)
14
8
13
12
6
BIAS CURRENT (µA)
OFFSET VOLTAGE (mV)
7
|VIOZ|
5
4
3
|VIOX|
2
11
10
9
8
7
6
1
5
|VIOY|
0
-100
-50
0
50
100
4
-100
150
-50
0
FIGURE 40. OFFSET VOLTAGE vs TEMPERATURE
100
150
FIGURE 41. INPUT BIAS CURRENT (VX, VY, VZ) vs
TEMPERATURE
2.0
6
1.5
INPUT VOLTAGE RANGE (V)
SCALE FACTOR ERROR (%)
50
TEMPERATURE (°C)
TEMPERATURE (°C)
1.0
0.5
0
-0.5
-1
-100
5
X INPUT
Y INPUT
4
3
2
1
-50
0
50
100
4
150
6
8
10
12
14
16
SUPPLY VOLTAGE (±V)
TEMPERATURE (°C)
FIGURE 42. SCALE FACTOR ERROR vs TEMPERATURE
FIGURE 43. INPUT VOLTAGE RANGE vs SUPPLY VOLTAGE
25
15
X INPUT
SUPPLY CURRENT (mA)
10
Y INPUT
CMR (V)
5
0
-5
X AND Y INPUT
20
ICC
IEE
15
10
5
-10
0
-15
4
6
8
10
12
14
SUPPLY VOLTAGE (±V)
FIGURE 44. INPUT COMMON MODE RANGE vs SUPPLY
VOLTAGE
15
16
0
5
10
15
20
SUPPLY VOLTAGE (±V)
FIGURE 45. SUPPLY CURRENT vs SUPPLY VOLTAGE
FN2477.6
April 29, 2008
HA-2556
Typical Performance Curves
(Continued)
MAX OUTPUT VOLTAGE (V)
5.0
4.8
4.6
4.4
4.2
100
300
500
700
RLOAD (Ω)
900
1100
FIGURE 46. OUTPUT VOLTAGE vs RLOAD
Die Characteristics
Metallization Mask Layout
DIE DIMENSIONS:
HA-2556
VREF GND
(2)
(1)
71 mils x 100 mils x 19 mils
VXIOA
(16)
VXIOB
(15)
METALLIZATION:
Type: Al, 1% Cu
Thickness: 16kÅ ±2kÅ
VYIOB
(3)
VYIOA
(4)
PASSIVATION:
Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos)
Silox Thickness: 12kÅ ±2kÅ
Nitride Thickness: 3.5kÅ ±2kÅ
VX+
(13)
TRANSISTOR COUNT:
VY+
(5)
84
SUBSTRATE POTENTIAL:
V-
VX(12)
VY(6)
V+
(11)
(8)
(7)
V- VOUT
16
(9) (10)
VZ+ VZ-
FN2477.6
April 29, 2008
HA-2556
Small Outline Plastic Packages (SOIC)
M16.3 (JEDEC MS-013-AA ISSUE C)
N
16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
H
0.25(0.010) M
B M
INCHES
E
-B1
2
3
L
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
A1
0.0040
0.0118
0.10
0.30
-
B
0.013
0.0200
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.3977
0.4133
10.10
10.50
3
E
0.2914
0.2992
7.40
7.60
4
e
α
B S
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
0.050 BSC
1.27 BSC
-
H
0.394
0.419
10.00
10.65
-
h
0.010
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
N
α
NOTES:
MILLIMETERS
16
0°
16
8°
0°
7
8°
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm (0.024
inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
17
FN2477.6
April 29, 2008
HA-2556
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
BASE
METAL
E
M
-Bbbb S
C A-B S
(c)
Q
-C-
SEATING
PLANE
S1
b2
C A-B S
eA/2
NOTES
-
0.200
-
5.08
-
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D
-
0.840
-
21.34
5
E
0.220
0.310
5.59
7.87
5
c
aaa M C A - B S D S
D S
MAX
0.014
eA
e
b
MIN
b
α
A A
MILLIMETERS
MAX
A
A
L
MIN
M
(b)
SECTION A-A
D S
INCHES
SYMBOL
b1
D
BASE
PLANE
ccc M
F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A)
16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
LEAD FINISH
c1
-D-
-A-
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
e
0.100 BSC
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
-
eA/2
0.150 BSC
3.81 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.060
0.38
1.52
6
S1
0.005
-
0.13
-
7
105o
90o
105o
-
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
α
90o
aaa
-
0.015
-
0.38
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
bbb
-
0.030
-
0.76
-
ccc
-
0.010
-
0.25
-
M
-
0.0015
-
0.038
2, 3
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
N
16
16
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
8
Rev. 0 4/94
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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FN2477.6
April 29, 2008