Datasheet

UNISONIC TECHNOLOGIES CO., LTD
CCVGA7C5
Preliminary
TVS
VGA PORT COMPANION
CIRCUIT

DESCRIPTION
The UTC CCVGA7C5 is an ESD solution for the VGA port
connector. This device integrates ESD protection for all signals,
Two non-inverting drivers provide buffering for the HSYNC
and VSYNC signals from the video controller IC. These buffers
accept TTL input levels and convert them to CMOS output levels
that swing between Ground and VCC 。 These drivers have a
nominal 60Ω output impedance to match the characteristic
impedance of the HSYNC and VSYNC lines of the video cables
typically used. The inputs of these drivers also have high
impedance pull−ups (50kΩ nom.) pulling up to the VAUX rail.
In addition, the DDC_CLOCK and DDC_DATA channels have
1.8kΩ resistors pulling these inputs up to the main 5V (VCC) rail.
The upper ESD diodes for the R, G and B channels are connected to a separate supply rail (VRGB) to facilitate
interfacing to graphics controller ICs with low voltage supplies. The remaining channels are connected to the main 5
V rail (VCC). The lower diodes for the R, G and B channels are also connected to a dedicated ground pin (GNDA) to
minimize crosstalk due to common ground impedance.
ESD protection is implemented with current steering diodes designed to safely handle the high peak surge currents
associated with the IEC−1000−4−2 Level−4 ESD Protection Standard (±8kV contact discharge). When the channels
are subjected to an electrostatic discharge, the ESD current pulse is diverted via the protection diodes into the
positive supply rails or ground where they may be safely dissipated.

FEATURES
* 7 Channels of ESD Protection Designed to Meet
IEC−1000−4−2 Level−4 ESD Requirements (±8kV Contact
Discharge)
* Three Independent Supply Pins (VCC, VRGB and VAUX) to
Facilitate Operation with Sub−Micron Graphics Controller ICs
* Very Low Loading Capacitance from ESD Protection Diodes
at Less than 5pF Typical

* TTL to CMOS Level−Translating Buffers for the
HSYNC and VSYNC Lines
* High impedance Pull−Ups (50kΩ Nominal to
VAUX) for HSYNC and VSYNC Inputs
* Pull−Up Resistors (1.8kΩ Nominal to VCC) for
DDC_CLK and DDC_DATA Lines
ORDERING INFORMATION
Ordering Number
Lead Free
Halogen Free
CCVGA7C5L-R16-T
CCVGA7C5G-R16-T
CCVGA7C5L-R16-R
CCVGA7C5G-R16-R
Package
Packing
SSOP-16
SSOP-16
Tube
Tape Reel
CCVGA7C5L-R16-T
(1)Packing Type
(1) T: Tube, R: Tape Reel
(2)Package Type
(2) R16: SSOP-16
(3)Lead Free
(3) L: Lead Free, G: Halogen Free
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Copyright © 2013 Unisonic Technologies Co., Ltd
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CCVGA7C5
Preliminary

PIN CONFIGURATION

PIN DESCRIPTION
PIN NO.
PIN NAME
1
HSYNC_OUT
2
HSYNC
3, 11
GNDD
4
VRGB
5
B
6
G
7
R
8
GNDA
9, 16
VCC
10
12
DDC_DATA
DDC_CLK
13
VAUX
14
VSYNC
15
VSYNC_OUT
TVS
DESCRIPTION
Horizontal sync signal buffer output. Connects to the video connector side of the
horizontal sync line.
Horizontal sync signal buffer input. Connects to the VGA Controller side of the
horizontal sync line.
Digital ground reference supply pin.
VRGB supply pin. This is an isolated supply pin for the R, G and B ESD protection
circuits.
Blue signal video protection channel. This pin is typically tied to the B video line
between the VGA controller device and the video connector.
Green signal video protection channel. This pin is typically tied to the G video line
between the VGA controller device and the video connector.
Red signal video protection channel. This pin is typically tied to the R video line
between the VGA controller device and the video connector.
Analog ground reference supply pin.
VCC supply pin. This is the main supply input for the DDC_CLK and DDC_DATA pullup
resistors and ESD protection circuits. It is also connected to the sync buffers and to the
ESD protection diodes present on the HSYNC_OUT and VSYNC_OUT lines.
DDC data pin.
DDC clock pin.
VAUX supply pin. This is the supply input for the 50kΩ pullups connected to the HSYNC
and VSYNC buffer inputs.
Vertical sync signal buffer input. Connects to the VGA Controller side of the vertical
sync line.
Vertical sync signal buffer output. Connects to the video connector side of the vertical
sync line.
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CCVGA7C5

Preliminary
TVS
BLOCK DIAGRAM
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
Preliminary
TVS
ABSOLUTE MAXIMUM RATING
PARAMETER
SYMBOL
RATINGS
UNIT
Supply Voltage Inputs
VCC, VRGB, VAUX
GND-0.5 ~ +6.0
V
Diode Forward Current
20
mA
(One Diode Conducting at a Time)
R, G, B
GND-0.5 ~ VRGB +0.5
V
DC Voltage at Inputs
HSYNC, VSYNC
GND-0.5 ~ VAUX +0.5
V
DDC_CLK, DDC_DATA
GND-0.5 ~ VCC +0.5
V
Package Power Rating
750
mW
Operating Temperature Range
TOPR
0 ~ +70
°C
Storage Temperature Range
TSTG
−40 ~ +150
°C
Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.

STANDARD OPERATING CONDITIONS
PARAMETER
SYMBOL
TEST CONDITIONS
Main Supply Voltage
VCC
RGB Supply Voltage
VRGB
Auxiliary Supply Voltage
VAUX
Logic High Input Voltage (Note)
VIH
Logic Low Input Voltage (Note)
VIL
RGB
Input Voltage
HSYNC, VSYNC
VI
DDC_CLK, DDC_DATA
High Level Output Current (Note 1)
IOH
Low Level Output Current (Note 1)
IOL
Free−Air Operating Temperature
TA
Note: These parameters apply only to the HSYNC and VSYNC signals.
UNISONIC TECHNOLOGIES CO., LTD
www.unisonic.com.tw
MIN
4.5
1.7
2.9
2.0
0
0
0
0
TYP
MAX
5.5
3.7
3.7
0.8
VRGB
VAUX
VCC
-8
8
+70
UNIT
V
V
V
V
V
V
V
V
mA
mA
°C
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
Preliminary
TVS
ELECTRICAL CHARACTERISTICS (Note 1)
PARAMETER
Diode Forward Voltage
Logic High Output Voltage
Logic Low Output Voltage
R, G and B Pins
HSYNC, VSYNC
Input
Pins
Current
HSYNC, VSYNC
Pins
SYMBOL
TEST CONDITIONS
VF
IF=10mA
VOH
IOH=-4mA, VCC=4.5V
VOL
IOL=4mA, VCC=4.5V
VRGB=3.63V, VIN=VRGB or GND
IIN
ICC
VRGB supply Current
IRGB
TYP
0.4
±1
UNIT
V
V
V
μA
VCC=5.5V, VAUX=VRGB=2.97V, All Inputs
and Outputs Floating
R, G and B Pins at VCC r GND, All
Inputs and Outputs Floating
MAX
1.0
±1
μA
-72.5
-95.0
μA
35
100
μA
10
μA
4.0
VAUX=3.63V, VIN=VAUX
VAUX=3.63V, VIN=GND
VCC upply Current
MIN
-30.0
R, G and B pins
5
pF
HSYNC,
10
pF
Input
CIN
VSYNC pins
Note 2 Applies for All Cases
Capacitance
DDC_DATA,
5
pF
DDC_CLK pins
Pull−up Resistance
RPU
1.52
1.80
1.98
kΩ
DDC_DATA, DDC_CLK pins
ESD Withstand Voltage
VESD
VCC=5 V, VRGB=3.3V, VAUX=3.3 V
±8
kV
SYNC Buffer L≥H Propagation
tPLH
CL=50pF, VCC=5.0V, RL=500Ω (Note 3)
7.0
15.0
ns
Delay
SYNC Buffer H≥L Propagation
tPHL
CL=50pF, VCC=5.0V, RL=500Ω (Note 3)
7.0
15.0
ns
Delay
SYNC Buffer Output Rise &
tR, tF
CL=50pF, VCC=5.0V, RL=500Ω (Note 3)
7.0
ns
Fall Times
Notes: 1. All parameters specified over standard operating conditions unless otherwise noted.
2. Measured at 1MHz. R/G/B inputs biased at 1.65V with VRGB=3.3V. DDC_CLK and DDC_DATA biased at
2.5V with VCC=5V. HSYNC and VSYNC inputs biased at VAUX or GND with VAUX=3.3V and VCC=5V.
3. Applicable to the SYNC buffers only. Input signals swing between 0V and 3.0V, with rise and fall times ≤5
ns. Guaranteed by correlation to buffer output drive currents.
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CCVGA7C5
TVS
TYPICAL APPLICATION CIRCUIT
To Video
DAC VDD
0.2µF
Video Controller
4
VRGB
H-Sync
V-Sync
DDC_Data
DDC_Clk
Red
Green
Blue
VF**
VF**
VF**
5V
3.3V
0.2µF
9, 16
VCC
13
VAUX
2
8
HSYNC
GNDA
14
3, 11
VSYNC
GNDD
10 DDC_DATA
12
DDC_CLK
Digital Analog
UTC
GND GND
CCVGA7C5
1
HSYNC_OUT
VSYNC_OUT 15
SF**
7
R
6 G
5 B
SF**
Video Connector

Preliminary
H-Sync
V-Sync
DDC_Data
DDC_Clk
Red
Green
Blue
VF** − VIDEO EMI Filter
SF** − SYNC EMI Filter
GNDA, the negative voltage rail for the R, G and B diodes is not connected internally to GNDD. GNDA should
ideally be connected to the ground of the video DAC IC. This will prevent any ground bounce caused by digital
signals from injecting noise onto the R, G and B signals. Analog GND and digital GND are typically connected on the
printed circuit board.
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
UNISONIC TECHNOLOGIES CO., LTD
www.unisonic.com.tw
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