1.2 MB

The following document contains information on Cypress products.
FUJITSU MICROELECTRONICS
DATA SHEET
DS07-12504-6E
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89860 Series
MB89865/867/P867/W867
■ DESCRIPTION
The MB89860 series has been developed as a general-purpose version of the F2MC*-8L family consisting of
proprietary 8-bit, single-chip, microcontrollers.
In addition to the F2MC-8L CPU core which can operate at low voltage but at high speed, the microcontrollers
contain a variety of peripheral functions such as a timer unit, PWM timers, a UART, a serial interface, a 10-bit
A/D converter, and an external interrupt.
The MB89860 series is applicable to a wide range of applications from welfare products to industrial equipment,
including portable devices.
*: F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■ FEATURES
• Various package options
QFP package (80 pins): MB89860
• High-speed processing at low voltage
Minimum execution time: 0.4 µs/3.5 V, 0.8 µs/2.7 V
(Continued)
For the information for microcontroller supports, see the following web site.
http://edevice.fujitsu.com/micom/en-support/
Copyright©1996-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2008.10
MB89860 Series
(Continued)
• F2MC-8L family CPU core
Instruction set optimized for controllers
Multiplication and division instructions
16-bit arithmetic operations
Test and branch instructions
Bit manipulation instructions, etc.
• 8-bit PWM timers: 2 channels
Also usable as a reload timer
• UART
Full-duplex double buffer
Synchronous and asynchronous data transfer
• 8-bit serial I/O
Switchable transfer direction allows communication with various equipment.
• 10-bit A/D converter
Conversion time: 13.2 µs
Activation by an external input or a timer unit capable
• External interrupt: 4 channels
Four channels are independent and capable of wake-up from low-power consumption modes (with an edge
detection function).
• Low-power consumption modes
Stop mode (Oscillation stops to minimize the current consumption.)
Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal.)
• Bus interface functions
Including hold and ready functions
• Timer unit
Outputs non-overlap three-phase waveforms to control an AC inverter motor.
Also usable as a PWM timer (4 channels)
2
DS07-12504-6E
MB89860 Series
■ PRODUCT LINEUP
Part number
Parameter
MB89865
MB89P867
MB89W867
MB89867
Classification
Mass production products (mask ROM products)
ROM size
32 K × 8 bits
(internal mask ROM)
16 K × 8 bits
(internal mask ROM)
RAM size
512 × 8 bits
One-time PROM pruducts/
EPROM products, also
used for evaluation
32 K × 8 bits
(internal PROM, programming
with general-purpose EPROM
programmer)
1 K × 8 bits
CPU functions
Number of instructions:
Instruction bit length:
Instruction length:
Data bit length:
Minimum execution time:
Interrupt processing time:
136
8 bits
1 to 3 bytes
1, 8, 16 bits
0.4 µs/10 MHz
3.6 µs/10 MHz
Ports
Input ports:
Output ports (N-ch open drain):
I/O ports (N-ch open drain):
Output ports (CMOS):
I/O ports (CMOS):
Total:
5 (All also serve as peripherals)
8 (All also serve as peripherals)
15
8 (All also serve as bus control pins)
32 (All also serve as bus pins or peripherals)
68
Timer unit
8-bit PWM timer 1,
8-bit PWM timer 2
UART
8-bit serial I/O
10-bit A/D converter
10-bit up/down count timer × 1
Compare registers with buffer × 4
Compare timer unit clear register with buffer × 1
Zero detection pin control
4 output channels
Non-overlap three-phase waveform output
Independent three-phase dead-time timer
8-bit reload timer operation (toggled output capable, operating clock cycle: 0.4 µs to
25.6 µs)
8-bit resolution PWM operation (conversion cycle: 102 µs to 6.528 ms)
8 bits
Clock synchronous/asynchronous data transfer capable
8 bits
LSB first/MSB first selectability
One clock selectable from four transfer clocks
(one external shift clock, three internal shift clocks: 0.8 µs, 3.2 µs, 12.8 µs)
10-bit resolution × 8 channels
A/D conversion time: 13.2 µs
Continous activation by a compare channel 0 in timer unit or an external activation capable
External interrupt
4 independent channels (edge selection, interrupt vector, source flag)
Rising edge/falling edge selectability.
Used also for wake-up from stop/sleep mode. (Edge detection is also permitted in stop mode.)
Standby modes
Sleep mode, stop mode
Process
Operating voltage*
CMOS
2.7 V to 6.0 V
2.7 V to 5.5 V
* : Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics”.)
DS07-12504-6E
3
MB89860 Series
■ PACKAGE AND CORRESPONDING PRODUCTS
Package
MB89865
MB89867
MB89P867
MB89W867
×
FPT-80P-M06
×
FPT-80C-A02
: Available
×
×
× : Not available
Note: For more information about each package, see section “■ Package Dimensions”.
■ DIFFERENCES AMONG PRODUCTS
1. Memory Size
Before evaluating using the OTPROM (one-time PROM) products (also used for evaluation), verify its differences
from the product that will actually be used.
Take particular care on the following point:
• The stack area, etc., is set at the upper limit of the RAM.
2. Current Consumption
When operated at low speed, the product with an OTPROM or an EPROM will consume more current than the
product with a mask ROM.
However, the current consumption in sleep/stop modes is the same.
3. Mask Options
In the MB89P867/W867, no option can be set.
Before using options check section “■ Mask Options”.
Take particular care on the following point:
• A pull-up resistor can be set for P00 to P07, P10 to P17 and P20 to P27 only at single-chip mode.
4
DS07-12504-6E
MB89860 Series
■ PIN ASSIGNMENT
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
P83
AVSS
AVR
AVCC
P57/AN7
P56/AN6
P55/AN5
P54/AN4
P53/AN3
P52/AN2
P51/AN1
P50/AN0
P84
P85
P86
P87
(Top view)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
N.C.
P40/RTO0
P41/RTO1/U
P42/RTO2/V
P43/RTO3/W
P44/X
VSS
P45/Y
P46/Z
VCC
P47/TRGI
P60/INT0
P61/INT1
P62/INT2
P63/INT3/ADST
P64/DTTI
P30/SCK1
P31/SO1
P32/SI1
P33/SCK2
P34/SO2
P35/SI2
P36/PTO1
P37/PTO2
P17/A15
P16/A14
P15/A13
P14/A12
P13/A11
P12/A10
P11/A09
P10/A08
P07/AD7
P06/AD6
P05/AD5
P04/AD4
P03/AD3
P02/AD2
P01/AD1
P00/AD0
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
P82
P81
P80
P76
P75
P74
P73
P72
P71
P70
MOD0
MOD1
X0
X1
VSS
RST
P27/A L E
P26/RD
P25/WR
P24/C L K
P23/RDY
P22/HRQ
P21/HAK
P20/BUFC
(FPT-80P-M06)
(FPT-80C-A02)
DS07-12504-6E
5
MB89860 Series
■ PIN DESCRIPTION
Pin no.
Pin name
QFP*
13
X0
14
X1
11
MOD0
12
MOD1
16
Circuit
type
Function
A
Crystal oscillator pins (10 MHz)
B
Operating mode selection pins
Connect directly to VCC or VSS.
RST
C
Reset I/O pin
This pin is an N-ch open-drain output type with a pull-up resistor,
and a hysteresis input type. “L” is output from this pin by an
internal reset source. The internal circuit is initialized by the input
of “L”.
40 to 33
P00 /AD0 to
P07/AD7
D
General-purpose I/O ports
When an external bus is used, these ports function as multiplex
pins of lower address output and data I/O.
32 to 25
P10 /A08 to
P17/A15
D
General-purpose I/O ports
When an external bus is used, these ports function as upper
address output.
24
P20/BUFC
F
General-purpose output port
When an external bus is used, this port can also be used as a
buffer control output.
23
P21/HAK
F
General-purpose output port
When an external bus is used, this port can also be used as a hold
acknowledge output.
22
P22/HRQ
D
General-purpose output port
When an external bus is used, this port can also be used as a
hold request input.
21
P23/RDY
D
General-purpose output port
When an external bus is used, this port functions as a ready
input.
20
P24/CLK
F
General-purpose output port
When an external bus is used, this port functions as a clock
output.
19
P25/WR
F
General-purpose output port
When an external bus is used, this port functions as a write
signal output.
18
P26/RD
F
General-purpose output port
When an external bus is used, this port functions as a read signal
output.
17
P27/ALE
F
General-purpose output port
When an external bus is used, this port functions as an address
latch signal output.
48
P30/SCK1
E
General-purpose I/O port
Also serves as the clock I/O for the UART.
This port is a hysteresis input type.
* : FPT-80P-M06, FPT-80C-A02
(Continued)
6
DS07-12504-6E
MB89860 Series
Pin no.
Pin name
QFP*
Circuit
type
Function
47
P31/SO1
E
General-purpose I/O port
Also serves as the data output for the UART.
This port is a hysteresis input type.
46
P32/SI1
E
General-purpose I/O port
Also serves as the data input for the UART.
This port is a hysteresis input type.
45
P33/SCK2
E
General-purpose I/O port
Also serves as the clock I/O for the 8-bit serial I/O.
This port is a hysteresis input type.
44
P34/SO2
E
General-purpose I/O port
Also serves as the data output for the 8-bit serial I/O.
This port is a hysteresis input type.
43
P35/SI2
E
General-purpose I/O port
Also serves as the data input for the 8-bit serial I/O.
This port is a hysteresis input type.
42
P36/PTO1
E
General-purpose I/O port
Also serves as the pulse output for the 8-bit PWM timer 1.
This port is a hysteresis input type.
41
P37/PTO2
E
General-purpose I/O port
Also serves as the pulse output for the 8-bit PWM timer 2.
This port is a hysteresis input type.
63
P40/RTO0
E
General-purpose I/O port
Also serves as the pulse output for the timer unit.
This port is a hystereisis input type.
62,
61,
60
P41/RTO1/U,
P42/RTO2/V,
P43/RTO3/W
E
General-purpose I/O ports
Also serve as the pulse output for the timer unit or a non-overlap
three-phase waveform output.
These ports are a hysteresis input type.
59,
57,
56
P44/X,
P45/Y,
P46/Z
E
General-purpose I/O ports
Also serve as a non-overlap three-phase output.
These ports are a hysteresis input type.
54
P47/TRGI
E
General-purpose I/O port
Also serves as the trigger input for the timer unit.
This port is a hysteresis input type.
69 to 76
P50/AN0 to
P57/AN7
H
N-ch open-drain output ports
Also serve as the analog input for the A/D converter.
53 to 51
P60/INT0 to
P62/INT2
I
General-purpose input ports
Also serve as an external interrupt input.
These ports are a hysteresis input type.
P63/INT3/
ADST
I
General-purpose input port
Also serves as an external interrupt input and as the activation
trigger input for the A/D converter.
This port is a hysteresis input type.
50
* : FPT-80P-M06, FPT-80C-A02
(Continued)
DS07-12504-6E
7
MB89860 Series
(Continued)
Pin no.
Pin name
QFP*
49
Circuit
type
Function
P64/DTTI
I
General-purpose input port
Also serves as a dead-time timer disable input.
This port is a hysteresis input type.
DTTI input is with a noise canceller.
10 to 4
P70 to P76
G
N-ch open-drain I/O ports
These ports are a hysteresis input type.
3 to 1, 80,
68 to 65
P80 to P87
G
N-ch open-drain I/O ports
These ports are a hysteresis input type.
55
VCC
—
Power supply pin
15, 58
VSS
—
Power supply (GND) pins
77
AVCC
—
A/D converter power supply pin
78
AVR
—
A/D converter reference voltage input pin
79
AVSS
—
A/D converter power supply (GND) pin
Use this pin at the same voltage as VSS.
64
N.C.
—
Internally connected pin
Be sure to leave it open.
* : FPT-80P-M06, FPT-80C-A02
8
DS07-12504-6E
MB89860 Series
■ I/O CIRCUIT TYPE
Type
Circuit
A
Remarks
• At an oscillation feedback resitor of approximately
1 MΩ/5.0 V
X1
X0
Standby control signal
B
C
• At an output pull-up resistor (P-ch) of approximately
50 kΩ/5.0 V
• Hysteresis input
R
P-ch
N-ch
D
• CMOS output
• CMOS input
R
P-ch
P-ch
N-ch
• Pull-up resistor optional (Mask ROM products)
• At a pull-up resistor of approximately 50 kΩ/5.0 V
E
• CMOS output
• Hysteresis input
R
P-ch
P-ch
N-ch
• Pull-up resistor optional (Mask ROM products)
• At a pull-up resistor of approximately 50 kΩ/5.0 V
(Continued)
DS07-12504-6E
9
MB89860 Series
(Continued)
Type
Circuit
Remarks
F
• CMOS output
R
P-ch
P-ch
N-ch
G
• Pull-up resistor optional (Mask ROM products)
• At a pull-up resistor of approximately 50 kΩ/5.0 V
• N-ch open-drain output
• Hysteresis input
R
P-ch
P-ch
N-ch
• Pull-up resistor optional (Mask ROM products)
• At a pull-up resistor of approximately 50 kΩ/5.0 V
H
• N-ch open-drain output
• Analog input
P-ch
N-ch
Analog input
I
R
10
• Hysteresis input
• Pull-up resistor optional (Mask ROM products)
• At a pull-up resistor of approximately 50 kΩ/5.0 V
DS07-12504-6E
MB89860 Series
■ HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum
Ratings” in section “■ Electrical Characteristics” is applied between VCC and VSS.
When latchup occurs, power supply current increases rapidly and might thermally damage elements. When
using, take great care not to exceed the absolute maximum ratings.
Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital
power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down
resistor.
3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters
Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use.
4. Treatment of N.C. Pin
Be sure to leave (internally connected) N.C. pin open.
5. Power Supply Voltage Fluctuations
Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage
could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore
important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P
value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient
fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.
6. Precautions when Using an External Clock
Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and
wake-up from stop mode.
DS07-12504-6E
11
MB89860 Series
■ PROGRAMMING TO THE EPROM ON THE MB89P867/W867
The MB89P867/W867 are an OTPROM version of the MB89860 series.
1. Features
• 32-Kbyte PROM on chip
• Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)
2. Memory Space
Memory space in EPROM mode is diagrammed below.
Address
Single chip
0000H
EPROM mode
( Corresponding addresses on the EPROM programmer)
I/O
0080H
RAM
0480H
Not available
8000H
0000H
PROM
32 KB
FFFFH
EPROM
32 KB
7FFFH
3. Programming to the EPROM
In EPROM mode, the MB89P867/W867 functions equivalent to the MBM27C256A. This allows the PROM to
be programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used)
by using the dedicated socket adapter.
• Programming procedure
(1) Set the EPROM programmer to the MBM27C256A.
(2) Load program data into the EPROM programmer at 0000H to 7FFFH (note that addresses 8000H to FFFFH
while operating as a single chip assign to addresses 0000H to 7FFFH in EPROM mode.)
(3) Program to 0000H to 7FFFH with the EPROM programmer.
12
DS07-12504-6E
MB89860 Series
4. Recommended Screening Conditions
High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked
OTPROM microcomputer program.
Program, verify
Aging
+150 °C, 48 h
Data verification
Assembly
5. Programming Yield
All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature.
For this reason, a programming yield of 100% cannot be assured at all times.
6. Erasure
In order to clear all locations of their programmed contents, it is necessary to expose the internal EPROM to an
ultraviolet light source. A dosage of 10 W-seconds/cm2 is required to completely erase an internal EPROM. This
dosage can be obtained by exposure to an ultraviolet lamp (wavelength of 2537 Angstroms (Å)) with intensity
of 12000 µW/cm2 for 15 to 21 minutes. The internal EPROM should be about one inch from the source and all
filters should be removed from the UV light source prior to erasure.
It is important to note that the internal EPROM and similar devices, will erase with light sources having
wavelengths shorter than 4000 Å. Although erasure time will be much longer than with UV source at 2537 Å,
nevertheless the exposure to fluorescent light and sunlight will eventually erase the internal EPROM, and
exposure to them should be prevented to realize maximum system reliability. If used in such an environment,
the package windows should be covered by an opaque label or substance.
DS07-12504-6E
13
MB89860 Series
■ BLOCK DIAGRAM
Time-base timer
Oscillator
Clock controller
Reset circuit
(WDT)
RST
MOD0
MOD1
P36/PTO1
8-bit serial I/O
P35/SI2
P34/SO2
P33/SCK2
External bus
interface
P32/SI1
P31/SO1
P30/SCK1
UART
CMOS I/O port
CMOS I/O port
Port 2
P27/ALE
P26/RD
P25/WR
P24/CLK
P23/RDY
P22/HRQ
P21/HAK
P20/BUFC
8-bit PWM timer 1
6
P47/TRGI
P46/Z
P45/Y
P44/X
P43/RTO3/W
P42/RTO2/V
P41/RTO1/U
P40/RTO0
Port 4
8
Internal bus
P10/A08
to P17/A15
8
P37/PTO2
CMOS I/O port
Port 0 and port 1
P00/AD0
to P07/AD7
8-bit PWM timer 2
Port 3
X0
X1
Timer unit
CMOS output port
(Dead-time timer)
4
RAM
External interrupt
Port 6
P64/DTTI
3
P60/INT0
to P62/INT2
P63/INT3/ADST
F2MC-8L
Input port
CPU
AVR
AVCC
AVSS
8
Other pins
VCC , VSS × 2
Part number
MB89865
MB89867
10-bit A/D converter
RAM size
ROM size
512 bytes
16 Kbytes
1 Kbyte
32 Kbytes
14
1 Kbyte
32 Kbytes
(EPROM)
8
P50/AN0
to P57/AN7
N-ch open-drain output port
7
P70 to P76
N-ch open-drain I/O port
Port 7 and port 8
MB89W867/P867
Port 5
ROM
8
P80 to P87
DS07-12504-6E
MB89860 Series
■ CPU CORE
1. Memory Space
The microcontrollers of the MB89860 series offer a memory space of 64 Kbytes for storing all of I/O, data, and
program areas. The I/O area is located at the lowest address. The data area is provided immediately above the
I/O area. The data area can be divided into register, stack, and direct areas according to the application. The
program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of
interrupt reset vectors and vector call instructions toward the highest address within the program area. The
memory space of the MB89860 series is structured as illustrated below.
Memory Space
MB89867
MB89W867/P867
MB89865
0000H
0000H
I/O
0080H
I/O
0080H
RAM
512 B
0100H
RAM
1 KB
0100H
Register
Register
0200H
0200H
0280H
0480H
External area
External area
8000H
C000H
ROM *
32 KB
ROM *
16 KB
FFFFH
FFFF H
*: The ROM area is an external area depending on the mode.
DS07-12504-6E
15
MB89860 Series
2. Registers
The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers
in the memory. The following dedicated registers are provided:
Program counter (PC):
A 16-bit register for indicating instruction storage positions
Accumulator (A):
A 16-bit temporary register for storing arithmetic operations, etc. When the
instruction is an 8-bit data processing instruction, the lower byte is used.
Temporary accumulator (T):
A 16-bit register which performs arithmetic operations with the accumulator
When the instruction is an 8-bit data processing instruction, the lower byte is used.
Index register (IX):
A 16-bit register for index modification
Extra pointer (EP):
A 16-bit pointer for indicating a memory address
Stack pointer (SP):
A 16-bit register for indicating a stack area
Program status (PS):
A 16-bit register for storing a register pointer, a condition code
Initial value
16 bits
FFFDH
: Program counter
PC
A
: Accumulator
Undefined
T
: Temporary accumulator
Undefined
IX
: Index register
Undefined
EP
: Extra pointer
Undefined
SP
: Stack pointer
Undefined
PS
: Program status
I-flag = 0, IL1, 0 = 11
Other bits are undefined.
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for
use as a condition code register (CCR). (See the diagram below.)
Structure of the Program Status Register
15
PS
14
13
12
RP
10
9
8
Vacancy Vacancy Vacancy
RP
16
11
7
6
H
I
5
4
IL1, 0
3
2
1
0
N
Z
V
C
CCR
DS07-12504-6E
MB89860 Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents
and the actual address is based on the conversion rule illustrated below.
Rule for Conversion of Actual Addresses of the General-purpose Register Area
RP
Lower OP codes
“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
b1
b0
↓
↓
Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and
bits for control of CPU operations at the time of an interrupt.
H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared
otherwise. This flag is for decimal adjustment instructions.
I-flag:
Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0
when reset.
IL1, 0:
Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is
higher than the value indicated by this bit.
IL1
IL0
Interrupt level
0
0
0
1
1
0
2
1
1
3
1
High-low
High
Low = no interrupt
N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0.
Z-flag:
Set when an arithmetic operation results in 0. Cleared otherwise.
V-flag:
Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does
not occur.
C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise.
Set to the shift-out value in the case of a shift instruction.
DS07-12504-6E
17
MB89860 Series
The following general-purpose registers are provided:
General-purpose registers: An 8-bit register for storing data
The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains
eight registers and up to a total of 32 banks can be used on the MB89860 series. The bank currently in use is
indicated by the register bank pointer (RP).
Note: The number of register banks that can be used varies with the RAM size.
Register Bank Configuration
This address = 0100H + 8 × (RP)
R0
R1
R2
R3
R4
R5
R6
R7
32 banks
Memory area
18
DS07-12504-6E
MB89860 Series
■ I/O MAP
Address
Read/write
Register name
Register description
00H
(R/W)
PDR0
Port 0 data register
01H
(W)
DDR0
Port 0 data direction register
02H
(R/W)
PDR1
Port 1 data register
03H
(W)
DDR1
Port 1 data direction register
04H
(R/W)
PDR2
Port 2 data register
05H
(W)
BCTR
External bus pin control register
06H
Vacancy
07H
Vacancy
08H
(R/W)
STBC
Standby control register
09H
(W)
WDTC
Watchdog timer control register
0AH
(R/W)
TBTC
Time-base timer control register
Vacancy
0BH
0CH
(R/W)
PDR3
Port 3 data register
0DH
(W)
DDR3
Port 3 data direction register
0EH
(R/W)
PDR4
Port 4 data register
0FH
(W)
DDR4
Port 4 data direction register
10H
(R/W)
PDR5
Port 5 data register
Vacancy
11H
12H
(R)
PDR6
Vacancy
13H
14H
(R/W)
PDR7
Port 7 data register
Vacancy
15H
16H
Port 6 data register
(R/W)
PDR8
17H to 1BH
Port 8 data register
Vacancy
1CH
(R/W)
CTR1
PWM control register 1
1DH
(W)
CMR1
PWM compare register 1
1EH
(R/W)
CTR2
PWM control register 2
1FH
(W)
CMR2
PWM compare register 2
20H
(R/W)
SMC
UART serial mode control register
21H
(R/W)
SRC
UART serial rate control register
22H
(R/W)
SSD
UART serial status/data register
23H
(R/W)
SIDR/SODR
24H
(R/W)
SMR
Serial mode register
25H
(R/W)
SDR
Serial data register
UART serial data register
(Continued)
DS07-12504-6E
19
MB89860 Series
(Continued)
Address
Read/write
Register name
Register description
26H
(R/W)
EIC1
External interrupt control register 1
27H
(R/W)
EIC2
External interrupt control register 2
28H
(R/W)
ADC1
A/D converter control register 1
29H
(R/W)
ADC2
A/D converter control register 2
2AH
(R)
ADDH
A/D converter data register (H)
2BH
(R)
ADDL
A/D converter data register (L)
Vacancy
2CH
2DH
(W)
ZOCTR
2EH
(W)
CLRBRH
Compare clear buffer register (H)
2FH
(W)
CLRBRL
Compare clear buffer register (L)
30H
(R/W)
TCSR
Timer control status register
31H
(R/W)
CICR
Compare interrupt control register
32H
(R/W)
TMCR
Timer mode control register
33H
(R/W)
COER
Compare/port selection register
34H
(R/W)
CMCR
Compare buffer mode control register
35H
(R/W)
DTCR
Dead-time timer control register
36H
(W)
DTSR
Dead-time setting register
37H
(R/W)
OCTBR
38H
(W)
OCPBR0H
Output compare buffer register 0 (H)
39H
(W)
OCPBR0L
Output compare buffer register 0 (L)
3AH
(W)
OCPBR1H
Output compare buffer register 1 (H)
3BH
(W)
OCPBR1L
Output compare buffer register 1 (L)
3CH
(W)
OCPBR2H
Output compare buffer register 2 (H)
3DH
(W)
OCPBR2L
Output compare buffer register 2 (L)
3EH
(W)
OCPBR3H
Output compare buffer register 3 (H)
3FH
(W)
OCPBR3L
Output compare buffer register 3 (L)
40H to 7BH
Zero detection output control register
Output control buffer register
Vacancy
7CH
(W)
ILR1
Interrupt level setting register 1
7DH
(W)
ILR2
Interrupt level setting register 2
7EH
(W)
ILR3
Interrupt level setting register 3
7FH
Vacancy
Notes: • Do not use vacancies.
• When a read-modify-write instruction (such as bit set) is used to access a write-only register or a register
containing a write-only bit, a bit designated by the instruction will have a predetermined value. However,
a write-only bit included, if any, in bits not defined by the instruction will cause a malfunction. So no access
to the register should be tried with any read-modefy-write instruction.
20
DS07-12504-6E
MB89860 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(AVSS = VSS = 0.0 V)
Parameter
Symbol
Value
Min.
Max.
Unit
Remarks
Power supply voltage
VCC
AVCC
VSS – 0.3
VSS + 7.0
V
*
A/D converter reference input
voltage
AVR
VSS – 0.3
VSS + 7.0
V
AVR must not exceed AVCC +
0.3 V.
Program voltage
VPP
VSS – 0.3
13.0
V
MOD1 pins of MB89P867/
W867
Input voltage
VI
VSS – 0.3
VCC + 0.3
V
Output voltage
VO
VSS – 0.3
VSS + 0.3
V
“L” level maximum output current
IOL
—
20
mA
“L” level average output current
IOLAV1
—
4
mA
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
P50 to P57, P70 to P76,
P80 to P87
IOLAV2
—
15
mA
P40 to P47
ΣIOLAV1
—
30
mA
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
P50 to P57, P70 to P76,
P80 to P87
ΣIOLAV2
—
50
mA
P40 to P47
“H” level maximum output current IOH
—
–20
mA
“H” level average output current
IOHAV
—
–4
mA
“H” level total maximum output
current
ΣIOH
—
–20
mA
Power consumption
PD
—
300
mW
Operating temperature
TA
–40
+85
°C
Storage temperature
Tstg
–55
+150
°C
“L” level total average output
current
*: Use AVCC and VCC set at the same voltage.
Take care so that AVCC does not exceed VCC, such as when power is turned on.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
DS07-12504-6E
21
MB89860 Series
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Parameter
Symbol
VCC
AVCC
Power supply voltage
Value
Unit
Remarks
Min.
Max.
2.7*
6.0*
V
Normal operation assurance
range*
MB89867/865
2.7*
5.5*
V
Normal operation assurance
range*
MB89P867/W867
1.5
6.0
V
Retains the RAM state in stop
mode
A/D converter reference input
voltage
AVR
0.0
AVCC
V
Operating temperature
TA
–40
+85
°C
*: These values vary with the operating frequency, instruction cycle, and analog assurance range. See Figure 1
and “5. A/D Converter Electrical Characteristics”.
Note: Connect the MOD0 and MOD1 pins to VCC or VSS.
6
5.5
Analog accuracy assured in the
VCC = AVCC = 3.5 V to 6.0 V range
5
Operating voltage (V)
Operation assurance range
4
3
2
1
1
2
3
4
5
6
7
8
9
10
Clock operating frequency (MHz)
(µs)
4.0
2.0
0.8
0.4
Minimum execution time (instruction cycle)
Note: The shaded area is assured only for the MB89865/867.
Figure 1
22
Operating Voltage vs. Clock Operating Frequency
DS07-12504-6E
MB89860 Series
3. DC Characteristics
(AVCC = VCC = +5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Pin
Condition
VIH
P00 to P07, P10 to P17,
P22, P23
VIHS
Input leackage
current
Max.
—
0.7 VCC
—
VCC +
0.3
V
RST, P30 to P37,
P40 to P47, P60 to P64,
P70 to P76, P80 to P87
—
0.8 VCC
—
VCC +
0.3
V
VIL
P00 to P07, P10 to P17,
P22, P23
—
VSS –
0.3
—
0.3 VCC
V
VILS
RST, P30 to P37,
P40 to P47, P60 to P64,
P70 to P76, P80 to P87
—
VSS –
0.3
—
0.2 VCC
V
VOH
P00 to P07, P10 to P17, IOH = –2.0
P20 to P27, P30 to P37,
mA
P40 to P47
2.4
—
—
V
VOL1
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
P50 to P57, P70 to P76, IOL = 1.8 mA
P80 to P87
—
—
0.4
V
VOL2
P40 to P47
IOL = 15 mA
—
—
1.5
V
ILI1
P00 to P07, P10 to P17,
P20 to P27, P30 to P37, 0.0 V < VI <
P40 to P47, P60 to P64,
P70 to P76, P80 to P87, VCC
MOD0, MOD1
—
—
±5
µA
RST
25
50
100
kΩ
18
Normal
operation
mA mode
(External
clock)
Pull-up resistance RPULL
VI = 0.0 V
FC = 10 MHz
ICC
—
15
VCC
Power supply
current
With pullup resistor
ICCS
FC = 10 MHz
—
6
8
Sleep
mode
mA
(External
clock)
ICCH
TA = +25°C
—
—
10
µA
AVCC
FC = 10 MHz,
—
6
—
when A/D
mA conversion
is activated
Other than AVCC,
AVSS, VCC, and VSS
f = 1 MHz
—
10
—
pF
IA
Input capacitance CIN
DS07-12504-6E
Remarks
Typ.
“L” level input
voltage
“L” level output
voltage
Unit
Min.
“H” level input
voltage
“H” level output
voltage
Value
Stop mode
23
MB89860 Series
4. AC Characteristics
(1) Reset Timing
(VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Parameter
Symbol
RST “L” pulse width
Condition
tZLZH
Unit
—
Min.
Max.
16 tXCYL*
—
Remarks
ns
* : tXCYL is the oscillation cycle (1/FC) to input to the X0 pin.
t ZLZH
RST
0.2 VCC
0.2 VCC
(2) Power-on Reset
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Parameter
Power supply rising time
Symbol
Condition
tR
Unit
Remarks
50
ms
Power-on reset function only
—
ms
Due to repeated operations
Min.
Max.
—
1
—
Power supply cut-off time
tOFF
Note: Make sure that power supply rises within the selected oscillation stabilization time.
If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended.
tOFF
tR
2.0 V
VCC
24
0.2 V
0.2 V
0.2 V
DS07-12504-6E
MB89860 Series
(3) Clock Timing
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Clock frequency
FC
Clock cycle time
tXCYL
Input clock pulse width
PWH
PWL
Input clock rising/falling time
tCR
tCF
Pin
Condition
X0, X1
Value
Unit
Remarks
Min.
Max.
1
10
MHz
100
1000
ns
20
—
ns
External clock
—
10
ns
External clock
—
X0
X0 and X1 Timing Conditions
tXCYL
PWH
PWL
tCR
0.8 VCC
tCF
0.8 VCC
X0
0.2 VCC
0.2 VCC
0.2 VCC
Clock Conditions
When a crystal
or
ceramic resonator is used
X0
When an external clock is used
X1
X0
X1
Open
(4) Instruction Cycle
Parameter
Instruction cycle
(minimum execution time)
DS07-12504-6E
Symbol
tinst
Value
Min.
Typ.
4/FC
Max.
Unit
Remarks
µs
tinst = 0.4 µs when
operating at FC = 10 MHz
25
MB89860 Series
(5) Clock Output Timing
(VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Cycle time
Symbol
Pin
tCYC
CLK
CLK ↑ → CLK ↓
tCHCL
Value
Condition
Load
condition:
50 pF
Unit
Remarks
—
ns
tXCYL × 2 at 10 MHz
oscillation
100
ns
Approx. tCYC/2 at
10 MHz oscillation
Min.
Max.
200
30
t CYC
t CHCL
2.4 V
2.4 V
CLK
0.8 V
26
DS07-12504-6E
MB89860 Series
(6) Bus Read Timing
(VCC = +5.0 V±10%, FC = 10 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Pin
Condition
Value (10 MHz)
Min.
Max.
Unit
Remarks
Valid address → RD ↓
time
tAVRL
RD, A15 to A08,
AD7 to AD0
1/4 tinst* – 64 ns
—
ns
RD pulse width
tRLRH
RD
1/2 tinst* – 20 ns
—
ns
Valid address → data
read time
tAVDV
AD7 to AD0,
A15 to A08
—
1/2 tinst*
ns
No wait
RD ↓ → data read time
tRLDV
RD, AD7 to AD0
—
1/2 tinst* – 80 ns
ns
No wait
RD ↑ → data hold time
tRHDX
AD7 to AD0, RD Load
0
—
ns
1/4 tinst* – 40 ns
—
ns
1/4 tinst* – 40 ns
—
ns
1/4 tinst* – 60 ns
—
ns
0
—
ns
RD ↑ → ALE ↑ time
tRHLH
RD ↑ → address invalid time tRHAX
condition:
50 pF
RD, ALE
RD, A15 to A08
RD ↓ → CLK ↑ time
tRLCH
CLK ↓ → RD ↑ time
tCLRH
RD ↓ → BUFC ↓ time
tRLBL
RD, BUFC
–5
—
ns
BUFC ↑ → valid
address time
tBHAV
A15 to A08,
AD7 to AD0,
BUFC
5
—
ns
RD, CLK
* : For information on tinst, see “(4) Instruction Cycle”.
2.4 V
CLK
0.8 V
tRHLH
ALE
0.8 V
AD
2.4 V
0.7 VCC
0.7 VCC
2.4 V
0.8 V
0.3 VCC
0.3 VCC
0.8 V
tRHDX
tAVDV
A
2.4 V
tCLRH
0.8 V
2.4 V
tRLCH
0.8 V
tAVRL
tRLDV
2.4 V
0.8 V
tRHAX
tRLRH
RD
2.4 V
0.8 V
tRLBL
tBHAV
2.4 V
BUFC
0.8 V
DS07-12504-6E
27
MB89860 Series
(7) Bus Write Timing
(VCC = +5.0 V±10%, FC = 10 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Valid address → ALE ↓ time tAVLL
Pin
Value (10 MHz)
Condition
Unit
Min.
Max.
1/4 tinst*1 – 64 ns
—
ns
5
—
ns
1/4 tinst*1 – 60 ns
—
ns
ALE ↓ time → address
invalid time
tLLAX
AD7 to AD0,
ALE, A15 to
A08
Valid address → WR ↓ time
tAVWL
WR, ALE
WR pulse width
tWLWH
WR
1/2 t
– 20 ns
—
ns
AD7 to AD0, WR
1/2 tinst*1 – 60 ns
—
ns
1/4 tinst*1 – 40 ns
Write data → WR ↑ time tDVWH
WR ↑ → data hold time tWHDX
Load
WR, A15 to A08
condition:
AD7 to AD0, WR 50 pF
WR ↑ → ALE ↑ time
tWHLH
WR, ALE
WR ↓ → CLK ↑ time
tWLCH
CLK ↓ → WR ↑ time
tCLWH
ALE pulse width
tLHLL
ALE ↓ → CLK ↑ time
tLLCH
WR ↑ → address invalid time
tWHAX
WR, CLK
inst*1
—
ns
*1
—
ns
*1
1/4 tinst – 40 ns
—
ns
1/4 tinst*1 – 60 ns
—
ns
0
1/4 tinst – 40 ns
—
ns
ALE
tXCYL – 35 ns
*2
—
ns
ALE, CLK
tXCYL – 35 ns*2
—
ns
Remarks
*1: For information on tinst, see “(4) Instruction Cycle”.
*2: These characteristics are also applicable to the bus read timing.
2.4 V
CLK
0.8 V
tLHLL
ALE
tLLCH
t WHLH
2.4 V
0.8 V
tAVLL
AD
0.8 V
tLLAX
2.4 V 2.4 V
2.4 V
2.4 V
0.8 V 0.8 V
0.8 V
0.8 V
tDVWH
A
2.4 V
0.8 V
tWHDX
2.4 V
tCLWH
0.8 V
tWLCH
tAVWL
tWHAX
tWLWH
WR
2.4 V
0.8 V
28
DS07-12504-6E
MB89860 Series
(8) Ready Input Timing
(VCC = +5.0 V±10%, FC = 10 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Parameter
Symbol
RDY valid → CLK ↑ time
tYVCH
CLK ↑ → RDY invalid time
tCHYX
Pin
Condition
RDY,
CLK
Load condition:
50 pF
Unit
Remarks
—
ns
*
—
ns
*
Min.
Max.
60
0
* : These characteristics are also applicable to the read cycle.
2.4 V
CLK
2.4 V
ALE
AD
Address
Data
A
WR
t YVCH t CHYX
0.7 VCC
0.7 VCC
RDY
0.3 VCC
0.3 VCC
t YVCH t CHYX
Note: The bus cycle is also extended in the read cycle in the same manner.
DS07-12504-6E
29
MB89860 Series
(9) UART and Serial I/O Timing
(VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Pin
Serial clock cycle time
tSCYC
SCK1,SCK2
SCK1 ↓ → SO1 time
SCK2 ↓ → SO2 time
tSLOV
SCK1, SO1
SCK2, SO2
Valid SI1 → SCK1 ↑
Valid SI2 → SCK2 ↑
tIVSH
SI1, SCK1
SI2, SCK2
SCK1 ↑ → valid SI1 hold time
SCK2 ↑ → valid SI2 hold time tSHIX
SCK1, SI1
SCK2, SI2
Serial clock “H” pulse width
tSHSL
Serial clock “L” pulse width
tSLSH
Condition
Internal shift
clock mode
Load
condition:
50 pF
SCK1, SCK2
SCK1 ↓ → SO1 time
SCK2 ↓ → SO2 time
tSLOV
SCK1, SO1
SCK2, SO2
Valid SI1 → SCK1 ↑
Valid SI2 → SCK2 ↑
tIVSH
SI1, SCK1
SI2, SCK2
SCK1 ↑ → valid SI1 hold time
SCK2 ↑ → valid SI2 hold time tSHIX
SCK1, SI1
SCK2, SI2
External shift
clock mode
Load
condition:
50 pF
Value
Unit
Min.
Max.
2 tinst*
—
µs
–200
200
ns
1/2 tinst*
—
µs
1/2 tinst*
—
µs
1 tinst*
—
µs
1 tinst*
—
µs
0
200
ns
1/2 tinst*
—
µs
1/2 tinst*
—
µs
Remarks
* : For information on tinst, see “(4) Instruction Cycle”.
30
DS07-12504-6E
MB89860 Series
Internal Shift Clock Mode
tSCYC
SCK1
SCK2
2.4 V
0.8 V
0.8 V
tSLOV
2.4 V
SO1
SO2
0.8 V
tIVSH
SI1
SI2
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
External Shift Clock Mode
t SLSH
t SHSL
SCK1
SCK2
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
t SLOV
SO1
SO2
2.4 V
0.8 V
tIVSH
SI1
SI2
DS07-12504-6E
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
31
MB89860 Series
(10) Peripheral Input Timing
(VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Parameter
Symbol
Peripheral input “H”
pulse width 1
tILIH1
Peripheral input “L”
pulse width 1
tIHIL1
Pin
Condition
Unit
Load
condition:
50 pF
TRGI, DTTI,
ADST,
INT0 to INT3
Min.
Max.
2 tinst*
—
µs
2 tinst*
—
µs
Remarks
* : For information on tinst, see “(4) Instruction Cycle”.
TRGI
DTTI
ADST
INT0 to INT3
tIHIL1
tILIH1
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
5. A/D Converter Electrical Characteristics
(AVCC = VCC = +3.5 V to +6.0 V, FC = 10 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Pin
Condition
Typ.
Max.
—
—
10
bit
—
—
±2.0
LSB
—
—
±1.5
LSB
—
—
±3.0
LSB
AVSS –
1.5 LSB
AVSS +
0.5 LSB
AVSS +
2.5 LSB
V
AVR –
3.5 LSB
AVR –
1.5 LSB
AVR +
0.5 LSB
V
—
—
4
LSB
—
—
33 tinst*
—
µs
—
—
—
10
µA
—
0
—
AVR
V
—
0
—
AVCC
V
AVR = 5.0
V
—
200
—
µA
—
Differential linearity error
Total error
AVCC = VCC
Zero transition voltage
VOT
AN0 to
AN7
Full-scale transition voltage VFST
Interchannel disparity
—
A/D mode conversion time
Analog port input current
IAIN
Analog input voltage
AN0 to
AN7
—
Reference voltage
Reference voltage supply
current
—
IR
AVR
Unit Remarks
Min.
Resolution
Linearity error
Value
* : For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics”.
32
DS07-12504-6E
MB89860 Series
(1) A/D Glossary
• Resolution
Analog changes that are identifiable with the A/D converter
• Linearity error
The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000 0001”) with
the full-scale transition point (“11 1111 1111” ↔´“11 1111 1110”) from actual conversion characteristics
• Differential linearity error
The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value
• Total error
The total error indicates the difference between the actual value and theoretical value. This error is caused by
the zero transition error, full-scale transition error, linearity error, quantization, and noise.
Theoretical I/O value
Total error
VFST
3FF
3FF
3FE
3FE
1.5 LSB
3FD
Digital output
Digital output
3FD
004
003
Actual conversion
value
(1 LSB × N + 0.5 LSB)
004
VNT
003
VOT
002
Actual conversion
value
002
1 LSB
Theoretical value
001
001
0.5 LSB
AVSS
AVR
Analog input
1 LSB =
VFST – VOT
1022
AVSS
AVR
Analog input
(V)
Total error of digital output “N” =
VNT – (1 LSB × N + 0.5 LSB)
1 LSB
(Continued)
DS07-12504-6E
33
MB89860 Series
(Continued)
004
Zero transition error
Full-scale transition error
3FF
Theoretical value
003
Actual conversion
value
Actual conversion
value
Digital output
Digital output
3FE
002
001
Actual conversion
value
3FD
VFST
(Measured value)
Actual conversion
value
3FC
VOT (Measured value)
AVR
AVSS
Analog input
Linearity error
Differential linearity error
3FF
N+1
Theoretical value
Actual conversion
value
3FE
(1 LSB × N + VOT)
N
004
VNT
Digital output
3FD
Digital output
AVR
AVSS
Analog input
VFST
(Measured
value)
003
N−1
N−2
Actual conversion
value
Theoretical value
001
V(N + 1)T
VNT
Actual conversion
value
002
Actual conversion
value
VOT (Measured value)
AVSS
AVR
Analog input
Linearity error of digital output "N" =
AVR
Analog input
VNT − (1 LSB × N + VOT)
1 LSB
34
AVSS
Differential linearity error of digital output "N" =
V(N + 1)T − VNT
1 LSB
−1
DS07-12504-6E
MB89860 Series
(2) Precautions
• Input impedance of the analog input pins
The A/D converter used for the MB89860 series contains a sample & hold circuit as illustrated below to fetch
analog input voltage into the sample & hold capacitor for fifteen instruction cycles after activation A/D conversion.
For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage
might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output
impedance of the external circuit low (below 10 kΩ).
Note that if the impedance connot be kept low, it is recommended to connect an external capacitor of about
0.1 µF for the analog input pin.
Analog Input Equivalent Circuit
Sample & hold circuit
.
C =. 64 pF
Anlog input pin
Comparator
If the analog input
impedance is higher
than 10 kΩ, it is
recommended to
connect an external
capacitor of approx.
0.1 µF.
.
R =. 3 kΩ
Close for 15 instruction cycles
after activating A/D conversion.
Analog channel selector
• Error
The smaller the | AVR – AVSS |, the greater the error would become relatively.
DS07-12504-6E
35
MB89860 Series
■ EXAMPLE CHARACTERISTICS
(1) “L” Level Output Voltage (P00 to P07, P10 to
P17, P20 to P27, P30 to P37, P50 to P57, P70 to
P76, and P80 to P87)
(2) “L” Level Output Voltage (P40 to P47)
VOL vs. IOL
VOL vs. IOL
VOL (V)
VOL (mV)
600
TA = +25˚C
TA = +25˚C
0.5
500
VCC = 3.0 V
VCC = 3.0 V
0.4
400
VCC = 4.0 V
VCC = 5.0 V
VCC = 6.0 V
0.3
VCC = 4.0 V
300
VCC = 5.0 V
VCC = 6.0 V
200
0.2
100
0.1
0
1
2
3
4
5
6
7
8
9
10
IOL (mA)
(3) “H” Level Output Voltage (P00 to P07, P10 to
P17, P20 to P27, P30 to P37, and P40 to P47)
0
0 1 2 3 4 5 6 7 8 9 1011121314151617181920
IOL (mA)
(4) Pull-up Resistance
RPULL vs. VCC
VCC − VOH vs. IOH
RPULL (kΩ)
1000
VCC − VOH (V)
1.0
TA = +25˚C
TA = +25˚C
0.9
0.8
0.7
VCC = 3.0 V
0.6
0.5
VCC = 4.0 V
VCC = 5.0 V
VCC = 6.0 V
0.4
100
0.3
0.2
0.1
0.0
0.0
36
−0.5
−1.0
−1.5
−2.0
−2.5
−3.0
IOH (mA)
10 to 1
1
2
3
4
5
6
VCC (V)
DS07-12504-6E
MB89860 Series
(5) “H” Level Input Voltage/“L” Level Input
Voltage (CMOS Input)
(6) “H” Level Input Voltage/“L” level Input
Voltage (Hysteresis Input)
VIN vs. VCC
VIN vs. VCC
VIN (V)
5.0
VIN (V)
5.0
TA = +25˚C
4.5
TA = +25˚C
4.5
4.0
4.0
3.5
3.5
3.0
3.0
2.5
2.5
2.0
2.0
1.5
1.5
1.0
1.0
0.5
0.5
0
VIHS
VILS
0
1
2
3
4
5
6
7
1
2
3
4
5
6
VCC (V)
7
VCC (V)
VIHS: Threshold when input voltage in hysteresis
characteristics is set to “H” level
VILS: Threshold when input voltage in hysteresis
characteristics is set to “L” level
(7) Operating Supply Current vs. Frequency
(8) Operating Supply Current vs. VCC
ICC vs. FC
ICC vs. VCC
ICC (mA)
25
ICC (mA)
25
TA = +25˚C
TA = +25˚C
20
FC = 10 MHz
20
VCC = 5.0 V
15
10
VCC = 3.5 V
5
VCC = 3.0 V
0
FC = 8 MHz
15
FC = 6 MHz
FC = 4 MHz
10
5
0
2
DS07-12504-6E
4
6
8
10
FC (MHz)
3.0 3.5 4.0 4.5 5.0 5.5 6.0
VCC (V)
37
MB89860 Series
(9) Sleep Power Supply Current vs. Frequency
(10) Sleep Power Supply Current vs. VCC
ICCS vs. VCC
ICCS vs. FC
ICCS (mA)
10
ICCS (mA)
10
TA = +25˚C
TA = +25˚C
8
8
FC = 10 MHz
6
VCC = 5.0 V
4
FC = 8 MHz
6
FC = 6 MHz
4
FC = 4 MHz
VCC = 3.5 V
2
VCC = 3.0 V
0
0
2
38
2
4
6
8
10
FC (MHz)
3.0 3.5 4.0 4.5 5.0 5.5 6.0
VCC (V)
DS07-12504-6E
MB89860 Series
■ MASK OPTIONS (MB89865/867)
Option type
Option selection
Power-on reset
0: Without power-on reset
1: With power-on reset
Initial value of oscillation
stabilization delay time
0: 218/FC (s) (Crystal oscillator)
1: 214/FC (s) (Ceramic oscillator)
Reset pin output
0: Without reset output
1: With reset output
Pull-up resistor at port pin
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
P40 to P47, P60 to P64,
P70 to P76, P80 to P87
1: Without pull-up resistor
0: With pull-up resistor
Remarks
—
Selects the initial value of the OSCS bit
in the STBC register during power-on
reset.
—
• Can be set per pin.
• P00 to P07, P10 to P17, and P20 to
P27 with a pull-up resistor can be set
only for single-chip mode.
■ STANDARD OPTION LIST
Part number
Parameter
MB89P867/W867
Power-on reset
Available
Initial value of oscillation
stabilization delay time
218/FC (s)
Output at reset pin
Available
Pull-up resistor at port pin
Not available
■ ORDERING INFORMATION
Part number
Package
MB89865PF
MB89867PF
MB89P867PF
80-pin Plastic QFP
(FPT-80P-M06)
MB89W867CF
80-pin Ceramic QFP
(FPT-80C-A02)
DS07-12504-6E
Remarks
ES level only
39
MB89860 Series
■ PACKAGE DIMENSIONS
80-pin plastic QFP
Lead pitch
0.80 mm
Package width ×
package length
14.00 × 20.00 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
3.35 mm MAX
Code
(Reference)
P-QFP80-14×20-0.80
(FPT-80P-M06)
80-pin plastic QFP
(FPT-80P-M06)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
23.90±0.40(.941±.016)
* 20.00±0.20(.787±.008)
64
41
40
65
0.10(.004)
17.90±0.40
(.705±.016)
* 14.00±0.20
(.551±.008)
INDEX
Details of "A" part
25
80
0.25(.010)
+0.30
3.05 –0.20
+.012
.120 –.008
(Mounting height)
1
24
0.80(.031)
0.37±0.05
(.015±.002)
0.16(.006)
0~8°
M
0.17±0.06
(.007±.002)
"A"
C
2002-2008 FUJITSU MICROELECTRONICS LIMITED F80010S-c-6-6
0.80±0.20
(.031±.008)
0.88±0.15
(.035±.006)
+0.10
0.30 –0.25
+.004
.012 –.010
(Stand off)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
40
DS07-12504-6E
MB89860 Series
(Continued)
80-pin ceramic QFP
Lead pitch
0.8 mm
Lead shape
Gullwing
Sealing method
Metal seal
(FPT-80C-A02)
80-pin ceramic QFP
(FPT-80C-A02)
0.51(.020) TYP
17.91(.705)
TYP
16.00(.630)
14.00±0.25
TYP
(.551±.010)
12.00(.472)
REF
8.50(.335)TYP
16.31(.642)
TYP
INDEX AREA
+0.08
0.80±0.10
0.35 –0.07
(.0315±.0040)
(.014±.003)
18.40(.725) REF
0.15±0.05
(.006±.002)
1.60(.063) TYP
0.80±0.10
(.0315±.0040)
20.00±0.25
(.787±.010)
23.90(.941) TYP
4.45(.175)MAX
22.00(.866) TYP
22.30(.878) TYP
C
0.80(.0315) TYP
1994-2008 FUJITSU MICROELECTRONICS LIMITED F80014SC-1-3
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
DS07-12504-6E
41
MB89860 Series
■ MAIN CHANGES IN THIS EDITION
Page
Section
Change Results
⎯
⎯
Changed the series name;
MB89860/850 series → MB89860 series
⎯
⎯
Deleted the part numbers.
MB89855, MB89857, MB89P857, MB89W857, MB89T855
⎯
⎯
Deleted the package code.
DIP-64P-M01, DIP-64C-A06
13
■ PROGRAMMING TO THE EPROM
ON THE MB89P867/W867
Deleted the “7. EPROM Programmer Socket Adapter”.
25
■ ELECTRICAL CHARACTERISTICS
4. AC Characteristics
Deleted the “(5) Recommended Resonator Manufacturers”.
32
38
■ ELECTRICAL CHARACTERISTICS
5. A/D Converter Electrical
Characteristics
Changed the items of "Zero transition voltage" and "Full-scale
transition voltage".
Unit : LSB → V
AVSS/AVR ± value → AVSS/AVR ± value LSB
■ INSTRUCTIONS
Deleted the “INSTRUCTIONS”.
■ INSTRUCTION MAP
Deleted the “INSTRUCTION MAP”.
The vertical lines marked in the left side of the page show the changes.
42
DS07-12504-6E
MB89860 Series
MEMO
DS07-12504-6E
43
MB89860 Series
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome,
Shinjuku-ku, Tokyo 163-0722, Japan
Tel: +81-3-5322-3347 Fax: +81-3-5322-3387
http://jp.fujitsu.com/fml/en/
For further information please contact:
North and South America
FUJITSU MICROELECTRONICS AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://www.fma.fujitsu.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://www.fmal.fujitsu.com/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/microelectronics/
FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.
Rm. 3102, Bund Center, No.222 Yan An Road (E),
Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fmc/
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
206 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fmk/
FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fmc/en/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS
does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS
or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or
other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to
the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear
facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon
system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising
in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of
the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Business & Media Promotion Dept.
Similar pages