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FUJITSU MICROELECTRONICS
CONTROLLER MANUAL
CM44-10128-5E
F2MC-16LX
16-BIT MICROCONTROLLER
MB90800 Series
HARDWARE MANUAL
F2MC-16LX
16-BIT MICROCONTROLLER
MB90800 Series
HARDWARE MANUAL
For the information for microcontroller supports, see the following web site.
This web site includes the "Customer Design Review Supplement" which provides the latest cautions on
system development and the minimal requirements to be checked to prevent problems before the system
development.
http://edevice.fujitsu.com/micom/en-support/
FUJITSU MICROELECTRONICS LIMITED
Preface
■ Purpose of this document and intended reader
We sincerely thank you for your continued use of Fujitsu semiconductor products.
MB90800 series is a general-purpose 16-bit microcontroller with a built-in 48-segment, 4-common LCD
controller circuit.
This manual describes the functions and operation of the MB90800 series and is intended for engineers
engaged in the development of actual products using the MB90800 series. Please read through this
manual.
Note: F2MC stands for FUJITSU Flexible Microcontroller.
■ Trademarks
Other system and product names used in this manual are trademarks of the related companies.
The symbols TM and (R) are sometimes omitted in the text.
■ Organization of this document
This manual contains the following 26 chapters and an appendix.
Chapter 1 EDSU OVERVIEW
This chapter describes the characteristics and basic specifications of the MB90800 series.
Chapter 2 CPU
This chapter describes the features of the MB90800 series CPU and its memory space.
Chapter 3 RESET
This chapter explains reset of the MB90800 series.
Chapter 4 CLOCK
This chapter explains the clock of the MB90800 series.
Chapter 5 LOW-POWER CONSUMPTION MODE
This chapter describes the low-power consumption mode of the MB90800 series.
Chapter 6 INTERRUPTS
This chapter describes interrupts of the MB90800 series and the functions and operations of Extended
Intelligent I/O Service (EI2OS).
Chapter 7 MODE SETTING
This chapter describes the MB90800 series operation mode and memory access mode.
Chapter 8 INPUT/OUTPUT PORT
This chapter describes the MB90800 series input/output port functions and operations.
Chapter 9 SERIAL I/O
This chapter describes the MB90800 series serial I/O functions and operations.
Chapter 10 TIMEBASE TIMER
This chapter describes the function and operations of the timebase timer of the MB90800 series.
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Chapter 11 WATCHDOG TIMER
This chapter describes the MB90800 series watchdog timer functions and operations.
Chapter 12 WATCH TIMER
This chapter describes the functions and operations of the watch timer of the MB90800 series.
Chapter 13 16-BIT RELOAD TIMER
This chapter describes the functions and operations of the 16-bit reload timer built in the MB90800
series.
Chapter 14 16-BIT I/O TIMER
This chapter describes the MB90800 series 16-bit input/output timer functions and operations.
Chapter 15 PPG TIMER
This chapter explains the PPG timer of the MB90800 series.
Chapter 16 UART
This chapter describes the functions and the operations of MB90800 series UART.
Chapter 17 EXTERNAL INTERRRUPT CIRCUIT
This chapter describes the functions and the operations of the MB90800 series DTP/External interrupt
circuit.
Chapter 18 I2C INTERFACE
This chapter describes the functions and the operations of the MB90800 series I2C interface.
Chapter 19 8/10-BIT A/D CONVERTER
This chapter describes the functions and the operations of the MB90800 series 8/10 bit A/D converter.
Chapter 20 LCD CONTROL CIRCUIT
This chapter describes the MB90800 series LCD control circuit functions and operations.
Chapter 21 CLOCK OUTPUT
This chapter describes the MB90800 series Watch clock output functions and operations.
Chapter 22 DELAYED INTERRUPT GENERATION MODULE
This chapter describes the MB90800 series delayed interrupt generation module functions and
operations.
Chapter 23 ADDRESS MATCH DETECTING FUNCTION
This chapter describes the MB90800 series address detection functions and operations.
Chapter 24 ROM MIRROR FUNCTION SELECTION MODULE
This chapter describes the MB90800 series ROM mirror function selection module.
Chapter 25 2M BIT FLASH MEMORY
This chapter describes the MB90800 series 2M-bit flash memory functions and operations.
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Chapter 26 CONNECTION EXAMPLES FOR SERIAL WRITING
This chapter describes a connection example for serial write using the AF220 flash microcontroller
programmer manufactured by YDC Corporation.
APPENDIX
In Appendices, I/O map and list of instructions are described.
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The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU
MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When
you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of
such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU
MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any thirdparty's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS assumes no
liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use
of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured,
could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss
(i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life
support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible
repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or
damages arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the
regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Copyright ©2006-2010 FUJITSU MICROELECTRONICS LIMITED All rights reserved.
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CONTENTS
CONTENTS.............................................................................................................................. v
CHAPTER 1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.10
Features .............................................................................................................................................. 2
Product Lineup .................................................................................................................................... 5
Block Diagram .................................................................................................................................... 7
Package Dimension ............................................................................................................................ 8
Pin Assignment ................................................................................................................................... 9
Pin Description .................................................................................................................................. 10
I/O Circuit Type ................................................................................................................................. 16
Notes Concerning Handling of Device .............................................................................................. 20
Clock Supply Map ............................................................................................................................. 23
Low-power Consumption Mode ........................................................................................................ 24
CHAPTER 2
2.1
2.2
2.3
2.4
2.4.1
2.4.2
2.5
2.6
2.7
2.7.1
2.7.2
2.7.3
2.7.4
2.7.5
2.7.6
2.7.7
2.7.8
2.7.9
2.8
2.9
2.9.1
2.9.2
2.9.3
2.9.4
CPU ............................................................................................................ 25
CPU ..................................................................................................................................................
Memory Space ..................................................................................................................................
Memory Map .....................................................................................................................................
Addressing ........................................................................................................................................
Linear Addressing ........................................................................................................................
Bank Addressing .........................................................................................................................
Allocation of Multi-byte Data on Memory ..........................................................................................
Registers ...........................................................................................................................................
Dedicated Registers .........................................................................................................................
Accumulator (A) ...........................................................................................................................
Stack Pointer (USP, SSP) ...........................................................................................................
Processor Status (PS) .................................................................................................................
Condition Code Register (PS: CCR) ...........................................................................................
Register Bank Pointer (PS: RP) ..................................................................................................
Interrupt Level Mask Register (PS:ILM) ......................................................................................
Program Counter (PC) .................................................................................................................
Direct Page Register (DPR) ........................................................................................................
Bank Register (PCB, DTB, USB, SSB, and ADB) .......................................................................
General-purpose Register ................................................................................................................
Prefix Code .......................................................................................................................................
Bank Select Prefix (PCB, DTB, ADB, and SPB) ..........................................................................
Common Register Bank Prefix (CMR) .........................................................................................
Flag Change Inhibit Prefix (NCC) ................................................................................................
Restrictions on Prefix Code .........................................................................................................
CHAPTER 3
3.1
OVERVIEW ................................................................................................... 1
26
27
29
31
32
33
35
37
38
40
43
45
46
48
49
50
51
52
54
56
57
58
59
60
RESET ........................................................................................................ 63
Overview of Reset ............................................................................................................................ 64
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3.2
3.3
3.4
3.5
3.6
Reset Factors and Oscillation Stabilization Wait Times ...................................................................
External Reset Pin ............................................................................................................................
Reset Operation ................................................................................................................................
Reset Factor Bit ................................................................................................................................
State of Each Pin at Reset ................................................................................................................
CHAPTER 4
4.1
4.2
4.3
4.4
4.5
4.6
5.1
5.2
5.3
5.4
5.5
5.5.1
5.5.2
5.5.3
5.5.4
5.6
5.7
5.8
76
77
79
82
86
87
LOW-POWER CONSUMPTION MODE ..................................................... 89
Low-power Consumption Mode ........................................................................................................ 90
Block Diagram of Low-power Consumption Control Circuit .............................................................. 93
Low-power Consumption Mode Control Register (LPMCR) ............................................................. 95
CPU Intermittent Operation Mode .................................................................................................... 98
Standby Mode ................................................................................................................................... 99
Sleep Mode ............................................................................................................................... 100
Timebase Timer Mode ............................................................................................................... 102
Watch Mode .............................................................................................................................. 104
Stop Mode ................................................................................................................................. 106
State Transition Diagram ................................................................................................................ 108
The Pin States in Standby Mode or Reset State ............................................................................ 110
Precautions when Using Low-power Consumption Mode .............................................................. 111
CHAPTER 6
6.1
6.2
6.3
6.3.1
6.3.2
6.4
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.5
6.6
6.6.1
6.6.2
6.6.3
6.6.4
6.6.5
CLOCK ....................................................................................................... 75
Overview of Clock .............................................................................................................................
Block Diagram of Clock Generation Section .....................................................................................
Clock Select Register (CKSCR) .......................................................................................................
Clock Mode .......................................................................................................................................
Oscillation Stabilization Wait Time ....................................................................................................
Connection of Oscillator and External Clock ....................................................................................
CHAPTER 5
66
67
68
70
73
INTERRUPT ............................................................................................. 115
Overview of Interrupt ......................................................................................................................
Interrupt Cause and Interrupt Vector ..............................................................................................
Interrupt Control Register and Function in Surrounding .................................................................
Interrupt Control Registers (ICR00 to ICR15) ............................................................................
Interrupt Control Register Functions ..........................................................................................
Hardware Interrupt ..........................................................................................................................
Operation of Hardware Interrupt ................................................................................................
Interrupt Processing ..................................................................................................................
Procedure for Use of Hardware Interrupt ..................................................................................
Multiple Interrupts ......................................................................................................................
Hardware Interrupt Processing Time .........................................................................................
Software Interrupt ...........................................................................................................................
Interrupts by Extended Intelligent I/O Service (EI2OS) ...................................................................
Extended Intelligent I/O Service (EI2OS) Descriptor (ISD) ........................................................
Each Register of Extended Intelligent I/O Service (EI2OS) Descriptor (ISD) ............................
Operation of Extended Intelligent I/O Service (EI2OS) ..............................................................
Procedure for Use of Extended Intelligent I/O Service (EI2OS) ................................................
Extended Intelligent I/O Service (EI2OS) Processing Time .......................................................
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116
118
121
123
125
128
131
133
135
136
138
140
142
144
145
147
148
149
6.7
6.8
6.9
Exception Processing Interrupt ....................................................................................................... 152
Stack Operation of Interrupt Processing ......................................................................................... 153
Example of Interrupt Processing Program ...................................................................................... 155
CHAPTER 7
7.1
7.2
7.3
SETTING MODE ....................................................................................... 159
Overview of Setting Mode ............................................................................................................... 160
Mode Pins (MD2 to MD0) ............................................................................................................... 161
Mode Data ...................................................................................................................................... 162
CHAPTER 8
I/O PORT .................................................................................................. 165
8.1
Overview of Input/Output Port ........................................................................................................
8.2
Explanation of Register of Input/Output Port ..................................................................................
8.3
Port 0 ..............................................................................................................................................
8.3.1
Port 0 Registers (PDR0, DDR0) ................................................................................................
8.3.2
Operation of Port 0 ....................................................................................................................
8.4
Port 1 ..............................................................................................................................................
8.4.1
Registers for Port 1 (PDR1, DDR1) ...........................................................................................
8.4.2
Operation of Port 1 ....................................................................................................................
8.5
Port 2 ..............................................................................................................................................
8.5.1
Registers for Port 2 (PDR2, DDR2) ...........................................................................................
8.5.2
Operation of Port 2 ....................................................................................................................
8.6
Port 3 ..............................................................................................................................................
8.6.1
Registers for Port 3 (PDR3, DDR3) ...........................................................................................
8.6.2
Operation of Port 3 ....................................................................................................................
8.7
Port 4 ..............................................................................................................................................
8.7.1
Registers for Port 4 (PDR4, DDR4) ...........................................................................................
8.7.2
Operation of Port 4 ....................................................................................................................
8.8
Port 5 ..............................................................................................................................................
8.8.1
port 5 Registers (PDR5, DDR5) ................................................................................................
8.8.2
Operation of Port 5 ....................................................................................................................
8.9
Port 6 ..............................................................................................................................................
8.9.1
Port 6 Registers (PDR6, DDR6) ................................................................................................
8.9.2
Operation of Port 6 ....................................................................................................................
8.10 Port 7 ..............................................................................................................................................
8.10.1 Port 7 Registers (PDR7, DDR7) ................................................................................................
8.10.2 Operation of Port 7 ....................................................................................................................
8.11 Port 8 ..............................................................................................................................................
8.11.1 Port 8 Registers (PDR8, DDR8) ................................................................................................
8.11.2 Operation of Port 8 ....................................................................................................................
8.12 Port 9 ..............................................................................................................................................
8.12.1 Port 9 Registers (PDR9, DDR9) ................................................................................................
8.12.2 Operation of Port 9 ....................................................................................................................
8.13 Example of Programming Input/Output Port ...................................................................................
CHAPTER 9
9.1
9.2
166
168
170
171
172
174
175
176
178
179
180
182
184
185
187
188
189
191
193
194
196
198
200
202
204
206
208
210
211
213
214
215
217
SERIAL I/O ............................................................................................... 219
Overview of Serial I/O ..................................................................................................................... 220
Register of Serial I/O ...................................................................................................................... 221
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9.2.1
Serial Mode Control Status Register (SMCS0, SMCS1) ...........................................................
9.2.2
Serial Shift Data Register (SDR0, SDR1) ..................................................................................
9.3
Serial I/O Prescaler Register (SDCR0, SDCR1) ............................................................................
9.4
Operation of Serial I/O ....................................................................................................................
9.4.1
Shift Clock .................................................................................................................................
9.4.2
Serial I/O Operation Status ........................................................................................................
9.4.3
Start/Stop Timing of Shift Operation ..........................................................................................
9.4.4
Interrupt Function of Serial I/O ..................................................................................................
222
226
227
229
230
231
233
235
CHAPTER 10 TIMEBASE TIMER ................................................................................... 237
10.1
10.2
10.3
10.4
10.5
10.6
Overview of Timebase Timer ..........................................................................................................
Configuration of Timebase Timer ...................................................................................................
Timebase Timer Control Register (TBTC) ......................................................................................
Interrupt of Timebase Timer ...........................................................................................................
Explanation of Operations of Timebase Timer Functions ...............................................................
Precautions when Using Timebase Timer ......................................................................................
238
240
242
244
245
248
CHAPTER 11 WATCHDOG TIMER ................................................................................ 249
11.1
11.2
11.3
11.4
11.5
11.6
Overview of Watchdog Timer .........................................................................................................
Watchdog Timer Control Register (WDTC) ....................................................................................
Configuration of Watchdog Timer ...................................................................................................
Operations of Watchdog Timer .......................................................................................................
Precautions when Using Watchdog Timer ......................................................................................
Program Examples of Watchdog Timer ..........................................................................................
250
252
254
256
258
259
CHAPTER 12 WATCH TIMER ........................................................................................ 261
12.1
12.2
12.3
12.4
Overview of Watch Timer ...............................................................................................................
Configuration of Watch Timer .........................................................................................................
Watch Timer Control Register (WTC) .............................................................................................
Operation of Watch timer ................................................................................................................
262
263
264
266
CHAPTER 13 16-BIT RELOAD TIMER ........................................................................... 267
13.1 Overview of 16-bit Reload Timer ....................................................................................................
13.2 Configuration of 16-bit Reload Timer ..............................................................................................
13.3 Pins of 16-bit Reload Timer ............................................................................................................
13.4 Registers of 16-bit Reload Timer ....................................................................................................
13.4.1 Timer Control Status Register Higher (TMCSR) .......................................................................
13.4.2 Timer Control Status Register Lower (TMCSR) ........................................................................
13.4.3 16-bit Timer Register (TMR) ......................................................................................................
13.4.4 16-bit Reload Register (TMRLR) ...............................................................................................
13.5 Interrupts of 16-bit Reload Timer ....................................................................................................
13.6 Explanation of Operation of 16-bit Reload Timer ............................................................................
13.6.1 Internal Clock Mode (Reload Mode) ..........................................................................................
13.6.2 Internal Clock Mode (One-Shot Mode) ......................................................................................
13.6.3 Event Count Mode .....................................................................................................................
13.7 16-bit Reload Timer Notes on Use .................................................................................................
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268
271
273
274
275
277
279
280
281
282
284
287
290
292
CHAPTER 14 INPUT/OUTPUT TIMER ........................................................................... 293
14.1 Outline of I/O Timer ........................................................................................................................
14.2 Block Diagram of I/O Timer ............................................................................................................
14.3 List of Register in I/O Timer ............................................................................................................
14.3.1 Explanation of Register of 16-bit Free-run Timer ......................................................................
14.3.2 Detailed Description of Input Capture Registers .......................................................................
14.3.3 Detailed Description of Output Compare Registers ...................................................................
14.4 Interruption of I/O Timer ..................................................................................................................
14.4.1 Interruption of 16-bit Free-run Timer .........................................................................................
14.4.2 Interruption of Input Capture ......................................................................................................
14.4.3 Interruption of Output Compare .................................................................................................
14.5 Operation Explanation of I/O Timer ................................................................................................
14.5.1 16-bit Free-run Timer .................................................................................................................
14.5.2 Input Capture .............................................................................................................................
14.5.3 Output Compare ........................................................................................................................
294
295
296
298
303
305
308
309
310
311
312
313
315
316
CHAPTER 15 PPG TIMER .............................................................................................. 317
15.1 Overview of PPG Timer ..................................................................................................................
15.2 Block Diagram of PPG Timer ..........................................................................................................
15.3 Register of PPG Timer ....................................................................................................................
15.3.1 Explanation of Register of PPG Timer .......................................................................................
15.4 Explanation of Operation of PPG Timer .........................................................................................
15.5 Notes on Use of PPG Timer ...........................................................................................................
15.6 Example of Using PPG Timer .........................................................................................................
318
320
321
323
328
331
332
CHAPTER 16 UART ........................................................................................................ 335
16.1 Overview of UART ..........................................................................................................................
16.2 Configuration of UART ....................................................................................................................
16.3 UART Pins ......................................................................................................................................
16.4 Register of UART ............................................................................................................................
16.4.1 Control Register (SCR0/SCR1) .................................................................................................
16.4.2 Mode Register (SMR0/SMR1) ...................................................................................................
16.4.3 Status Register (SSR0/SSR1) ...................................................................................................
16.4.4 Input Data Register (SIDR0/SIDR1), Output Data Register (SODR0/SODR1) .........................
16.4.5 Communication Prescaler Control Register (CDCR0/CDCR1) .................................................
16.5 UART Interrupt ................................................................................................................................
16.5.1 Receive Interrupt Generation and Flag Set Timing ...................................................................
16.5.2 Timing for the Transmission Interrupt Output and Flag Set .......................................................
16.6 UART Baud Rate ............................................................................................................................
16.6.1 Baud Rate by Dedicated Baud Rate Generator ........................................................................
16.6.2 Baud Rate by Internal Timer ......................................................................................................
16.6.3 Baud Rate by External Clock .....................................................................................................
16.7 Explanation of Operation of UART .................................................................................................
16.7.1 Operation in Asynchronous Mode (Operation Mode 0 or 1) ......................................................
16.7.2 Operation in Synchronous Mode (Operation mode 2) ...............................................................
16.7.3 Bidirectional Communication Function (Normal mode) .............................................................
16.7.4 Master/Slave Mode Communication Function (Multi-processor mode) .....................................
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336
338
341
342
343
346
348
351
353
355
357
359
360
362
364
366
367
369
372
374
376
16.8
Notes on Using UART .................................................................................................................... 379
CHAPTER 17 DTP/EXTERNAL INTERRUPT CIRCUIT ................................................. 381
17.1 Overview of DTP/External Interrupt Circuit .....................................................................................
17.2 Configuration of DTP/External Interrupt Circuit ..............................................................................
17.3 Pins of External DTP/Interrupt Circuit .............................................................................................
17.4 Register for DTP/External Interrupt Circuit .....................................................................................
17.4.1 DTP/External Interruption Factor Register (EIRR) ....................................................................
17.4.2 DTP/External Interruption Permission Register (ENIR) .............................................................
17.4.3 Request Level Setting Register (ELVR) ....................................................................................
17.5 Operation of DTP/External Interrupt Circuit ....................................................................................
17.5.1 External Interrupt Function ........................................................................................................
17.5.2 DTP Function .............................................................................................................................
17.6 Notes on Using DTP/External Interrupt Circuit ...............................................................................
382
384
386
387
388
391
393
395
397
398
399
CHAPTER 18 I2C INTERFACE ....................................................................................... 401
18.1 I2C Interface Outline .......................................................................................................................
18.2 Block Diagram and Unit Configuration of I2C Interface ..................................................................
18.3 I2C Interface Register .....................................................................................................................
18.3.1 I2C Status Register (IBSR) ........................................................................................................
18.3.2 I2C Control Register (IBCR) ......................................................................................................
18.3.3 I2C Clock Control Register (ICCR) ............................................................................................
18.3.4 I2C Address Register (IADR) .....................................................................................................
18.3.5 I2C Data Register (IDAR) ..........................................................................................................
18.4 I2C Interface Operation ...................................................................................................................
18.4.1 I2C Interface Transfer Flow .......................................................................................................
18.4.2 Mode Flow of I2C Interface ........................................................................................................
18.4.3 Operation Flow of I2C Interface .................................................................................................
402
403
405
406
408
413
416
417
418
421
423
424
CHAPTER 19 8/10-BIT A/D CONVERTER ..................................................................... 427
19.1 Overview of 8/10-bit A/D Converter ................................................................................................
19.2 Configuration of 8/10-bit A/D Converter ..........................................................................................
19.3 Pins of 8/10-bit A/D Converter ........................................................................................................
19.4 Register of 8/10-bit A/D Converter ..................................................................................................
19.4.1 A/D Control Status Register 1(ADCS1) .....................................................................................
19.4.2 A/D Control Status Register 0(ADCS0) .....................................................................................
19.4.3 A/D Data Register (ADCR0/ADCR1) .........................................................................................
19.4.4 Analog to Digital Conversion Channel Set Register (ADMR) ....................................................
19.5 Interrupt of 8/10-bit A/D Converter ..................................................................................................
19.6 Explanation of Operation of 8/10-bit A/D Converter .......................................................................
19.6.1 Conversion Using EI2OS ...........................................................................................................
19.6.2 A/D-converted Data Protection Function ...................................................................................
428
429
431
433
434
436
438
440
442
443
445
446
CHAPTER 20 LCD CONTROLLER/DRIVER .................................................................. 449
20.1 Outline of LCD Controller/Driver ..................................................................................................... 450
20.2 Composition of LCD Controller/Driver ............................................................................................ 451
20.2.1 Internal Division Register of LCD Controller/Driver ................................................................... 454
x
20.2.2 External Division Register of LCD Controller/Driver ..................................................................
20.3 Terminal of LCD Controller/Driver ..................................................................................................
20.4 Register of LCD Controller/Driver ...................................................................................................
20.4.1 LCDC Control Register Lower (LCRL) ......................................................................................
20.4.2 LCDC Control Register Higher (LCRH) .....................................................................................
20.4.3 LCDC Range Register (LCRR) ..................................................................................................
20.5 Display RAM of LCD Controller/Driver ............................................................................................
20.6 Operation Explanation of LCD Controller/Driver .............................................................................
20.6.1 Output Waveform at LCD Controller/Driver Operation (1/2 duty) ..............................................
20.6.2 Output Waveform at LCD Controller/Driver Operation (1/3 duty) ..............................................
20.6.3 Output Waveform at LCD Controller/Driver Operation (1/4 duty) ..............................................
456
458
461
462
464
466
468
472
474
477
480
CHAPTER 21 WATCH CLOCK OUTPUT ....................................................................... 483
21.1
21.2
21.3
Outline of Watch Clock Output ....................................................................................................... 484
Configuration of Watch Clock Output Circuit .................................................................................. 485
Watch Clock Output Control Register (TMCS) ............................................................................... 486
CHAPTER 22 DELAYED INTERRUPT GENERATION MODULE .................................. 489
22.1
22.2
22.3
22.4
Overview of Delayed Interrupt Generation Module .........................................................................
Delay Interruption Factor Generation/release Register (DIRR) ......................................................
Operation of Delayed Interrupt Generation Module ........................................................................
Notes on Use of Delay Interruption Generation Module .................................................................
490
491
492
493
CHAPTER 23 ADDRESS MATCH DETECTING FUNCTION ......................................... 495
23.1 Overview of Address Match Detection Function .............................................................................
23.2 Address Match Detection Function .................................................................................................
23.2.1 Program Address Detection Register (PADR0/PADR1) ............................................................
23.2.2 Program Address Detection Control Status Register (PACSR) ................................................
23.3 Operation Explanation of Address Match Detection Function ........................................................
23.4 Example of Using Address Match Detection Function ....................................................................
496
497
498
499
500
501
CHAPTER 24 ROM MIRROR FUNCTION SELECTION MODULE ................................ 505
24.1
24.2
Overview of ROM Mirror Function Selection Module ...................................................................... 506
ROM Mirror Function Select Register (ROMM) .............................................................................. 507
CHAPTER 25 2M-BIT FLASH MEMORY ........................................................................ 509
25.1 Overview of 2M-bit Flash Memory ..................................................................................................
25.2 Registers and Sector Configuration of Flash Memory ....................................................................
25.3 Flash Memory Control Status Register (FMCS) .............................................................................
25.4 Flash Memory Automatic Algorithm Start-up Method .....................................................................
25.5 Details of Programming/Erasing Flash Memory .............................................................................
25.5.1 Read/Reset State in Flash Memory ...........................................................................................
25.5.2 Writing Data to Flash Memory ...................................................................................................
25.5.3 Erasing All Data from Flash Memory (Chip Erase) ....................................................................
25.5.4 Erasing Any Data in Flash Memory (Sector Erasing) ................................................................
25.5.5 The Flash Memory Sector Erase Suspension ...........................................................................
25.5.6 The Flash Memory Sector Erase Resumption ...........................................................................
xi
510
511
512
515
516
517
518
520
521
523
524
CHAPTER 26 CONNECTION EXAMPLES FOR SERIAL WRITING .............................. 525
26.1
26.2
The Basic Component of Serial Writing Connection ....................................................................... 526
Example of Connecting Serial Writing (User power supply used) .................................................. 529
APPENDIX ......................................................................................................................... 537
APPENDIX A I/O Map ................................................................................................................................
APPENDIX B Instructions ...........................................................................................................................
B.1 Instruction Types ............................................................................................................................
B.2 Addressing .....................................................................................................................................
B.3 Direct Addressing ...........................................................................................................................
B.4 Indirect Addressing ........................................................................................................................
B.5 Execution Cycle Count ...................................................................................................................
B.6 Effective address field ....................................................................................................................
B.7 How to Read the Instruction List ....................................................................................................
B.8 F2MC-16LX Instruction List ............................................................................................................
B.9 Instruction Map ...............................................................................................................................
538
546
547
548
550
556
564
567
568
571
585
INDEX................................................................................................................................... 607
xii
Main changes in this edition
Page
-
Changes (For details, refer to main body.)
-
Corrected the model name.
Deleted "MB90802/S"
Added "MB90F809/S"
5
CHAPTER 1 OVERVIEW
1.2 Product Lineup
■ Product Lineup
Corrected Table 1.2-1.
7
1.3 Block Diagram
■ Block Diagram
Corrected Figure 1.3-1.
MB90802S/803S, MB90F804-101: P90, P91 →
X0A/X1A and P90/P91 can be switched by the option.
MB90802/803, MB90F804-201: X0A, X1A →
X0A/X1A: With sub clock Part number of products without "S" suffix/
201 option.
29
CHAPTER 2 CPU
2.3 Memory Map
■ Memory Map
Corrected table.
MB90802/802S → MB90803/S, MB90F803/S
MB90803/803S → MB90F809/S
MB90V800 → MB90V800-101/201
0008FFH → 0010FFH
0010FFH → 0028FFH
FC0000H → FD0000H
30
Corrected Notes:
("FF8000H" to "FFFFFFH") → ("FF4000H" to "FFFFFFH")
438
CHAPTER 19 8/10-BIT A/D
CONVERTER
19.4.3 A/D Data Register (ADCR0/
ADCR1)
■ A/D Data Register
(ADCR0/ADCR1)
Corrected Figure 19.4-4
(at φ=8MHz, 5.50μs)) → (at [email protected])
(at φ=16MHz, 4.12μs) → (at [email protected])
(at φ=16MHz, 5.50μs) → (at [email protected])
(at φ=25MHz, 7.04μs) → (at [email protected])
(at φ=8MHz, 2.5μs) → (at [email protected])
(at φ=16MHz, 2.0μs) → (at [email protected])
(at φ=16MHz, 3.0μs) → (at [email protected])
(at φ=25MHz, 5.12μs) → (at [email protected])
552
B.3 Direct Addressing
● I/O direct addressing (io)
Corrected Figure B.3-5.
(MOVW A, i : 0C0H → MOVW A, I:0C0H)
Added the note to Figure B.3-5.
553
B.3 Direct Addressing
● Abbreviated direct addressing
(dir)
Added the note to Figure B.3-6.
xiii
Page
554
Changes (For details, refer to main body.)
B.3 Direct Addressing
● I/O direct bit addressing (io:bp)
Changed Figure B.3-8.
(SETB i : 0C1H : 0 → SETB I:0C1H:0)
Added the note to Figure B.3-8.
B.3 Direct Addressing
● Abbreviated direct bit addressing (dir:bp)
Added the note to Figure B.3-9.
560
B.4 Indirect Addressing
● Program counter relative branch
addressing (rel)
Changed Figure B.4-7.
(BRA 10H → BRA 3C32H)
561
B.4 Indirect Addressing
● Register list (rlst)
Changed Figure B.4-9.
(POPW, RW0, RW4 → POPW RW0, RW4)
586
B.9 Instruction Map
■ Structure of Instruction Map
Changed column: instruction in Table B.9-1.
(@RW2+d8, #8, rel → CBNE @RW2+d8, #8, rel)
587
Changed the operand at row: +0, column: E0 in Table B.9-2.
(#4 → #vct4)
Changed the mnemonic at row: +0, column: D0 in Table B.9-2.
(MOV → MOVN)
Changed the mnemonic at row: +0, column: B0 in Table B.9-2.
(MOV → MOVX)
Changed the mnemonic at row: +8, column: B0 in Table B.9-2.
(MOV → MOVW)
589
Changed the mnemonic at row: +0, column: E0 in Table B.9-4.
(FILSI → FILSWI)
590
Changed Table B.9-5.
(· Moved "MUL A" and "MULW A" instruction from column:60 to column:70.
· Changed mnemonic and moved the Instruction from column:60,
row:+A to column:70, row:+A.
(DIVU → DIV))
591
Changed the operand at row: +E and +F, column: F0 in Table B.9-6.
(,#8, rel → #8, rel)
594
Changed the operand at row: +8 to +E, column: 50 in Table B.9-9.
(@@ → @)
Changed the operand at row: +0 to +7, column: 20 in Table B.9-9.
(RWi → @RWi)
595
Changed the operand at column: E0 and F0 in Table B.9-10.
(,r → ,rel)
xiv
Page
596
Changes (For details, refer to main body.)
B.9 Instruction Map
■ Structure of Instruction Map
Changed the operand at column: 70 in Table B.9-11.
(NEG A, → NEG)
597
Changed the operand at column: E0 and F0 in Table B.9-12.
(,r → ,rel)
605
Changed B.9-20.
(Column "A" → Column "A0",
Changed row "+A" ( W2+d16,A → @RW2+d16 ))
The vertical lines marked in the left side of the page show the changes.
xv
xvi
CHAPTER 1
OVERVIEW
This chapter explains the features and basic
specifications of the MB90800 series products.
1.1 Features
1.2 Product Lineup
1.3 Block Diagram
1.4 Package Dimension
1.5 Pin Assignment
1.6 Pin Description
1.7 I/O Circuit Type
1.8 Notes Concerning Handling of Device
1.9 Clock Supply Map
1.10 Low-power Consumption Mode
1
CHAPTER 1 OVERVIEW
1.1
Features
The MB90800 series is a general-purpose 16-bit microcontroller that has been
developed for high-speed real-time processing required for industrial and office
automation equipment and process control, etc. The LCD controller of four 48 segment
common is built into.
Instruction set has taken over the same AT architecture as in the F2MC-8L and F2MC
16L, and is further enhanced to support high level languages, extend addressing mode,
enhanced divide/multiply instructions with sign and enrichment of bit processing. In
addition, long word processing is now available by introducing a 32-bit accumulator.
■ Feature of MB90800 Series
● Clock
• Built-in PLL clock multiplying circuit
• Operating clock (PLL clock) can be selected from divided-by-2 of oscillation or 1 to 4 times the
oscillation (at oscillation of 6.25 MHz, 6.25 MHz to 25 MHz).
• Minimum instruction execution time of 40.0 ns (at oscillation of 6.25 MHz, four times the PLL clock,
operation at VCC of 3.3V)
● Maximum size of memory space: 16M-byte
• Internal 24-bit addressing
• Addressing
● Instruction system optimized for controllers
• Various data types (bit, byte, word, long word)
• 23 types of addressing modes
• High code efficiency
• Enhanced high-precision arithmetic operation by a 32-bit accumulator
• Enhance Multiply/Divide instructions with sign and the RETI instruction
● Instruction system for high-level language (C language)/multi-task
• System stack pointer
• System stack pointer, instruction set symmetry and barrel shift instructions
● Program patch function (2 address pointer)
● Higher execution speed
4-byte instruction queue
2
CHAPTER 1 OVERVIEW
● Powerful interrupt function (the priority level is now programmable. 8 levels of priority can be set.)
Strong interruption function of 32 factors
■ Function (resource) Around Internal of MB90800 series
● Data transfer function (extended intelligent I/O service function: 16 channels max.)
● Low-power consumption (standby mode)
• Sleep mode (stops CPU clock)
• Timebase timer mode (operates only oscillation clock and sub clock, timebase timer and watch timer)
• Watch timer mode (mode in which only the sub clock and watch timers operate)
• Stop mode (stops oscillation clock and sub clock)
• CPU Intermittent operation mode
● Package
QFP-100(FPT-100P-M06:0.65mm pin pitch)
● Process: CMOS Technology
● I/O port:68 or less (70 when not using sub clock)
● Timebase timer
● Watchdog timer
● Watch timer
● LCD controller
48 Segments 4 Commons
● 8/10-bit A/D converter: 12 channels
8-bit resolution or 10-bit resolution can be set.
● Multi-functional timer
• 16-bit free-run timer: 1 channel
• 16-bit output compare: 2 channels
• An interrupt request can be output when the count value of the 16-bit free-run timer and the setting
value in the compare register match.
• 16-bit input capture: 2 channels
3
CHAPTER 1 OVERVIEW
• Upon detecting a valid edge of the signal input from the external input pin, the count value of the 16-bit
free-run timer is loaded into the input capture data register and an interrupt request can be output.
• 16-bit PPG timer:2 channels
• 16-bit reload timer: 3 channels
● UART:2 Channels
● I/O extended serial interface:2 channels
● DTP/external interrupt (4 channels)
• Activate the extended intelligent I/O service by external interrupt input.
• Interrupt output by external interrupt input
● Clock output circuit
● Delayed interrupt output module
Output an interrupt request for task switching
● I2C Interface: 1 channel
4
CHAPTER 1 OVERVIEW
1.2
Product Lineup
Table 1.2-1 shows the MB90800 series product lineup list.
■ Product Lineup
Table 1.2-1 MB90800 series Product Lineup List (1/2)
Product Lineup
Feature
MB90V800101/201
MB90F804101/201
MB90803/
MB90803S
Evaluation
product
Flash memory
product
Mask ROM
product
MB90F803/
MB90F803S
MB90F809/
MB90F809S
Flash memory product
On-chip PLL clock multiplication method (×1, ×2, ×3, ×4, 1/2 when PLL stops)
Minimum instruction execution time of 40.0 ns (at oscillation of 6.25 MHz, four times
the PLL clock)
System clock
Sub clock
With sub clock:
201 option
Without sub clock: 101 option
With sub clock:
Part number of products without "S" suffix
Without sub clock:
Part number of products with "S" suffix
ROM
RAM
None
256 Kbytes
128 Kbytes
128 Kbytes
dual
operation
28 Kbytes
16 Kbytes
4 Kbytes
4 Kbytes
192 Kbytes
10 Kbytes
CPU function
Basic instruction:351 instructions
Minimum instruction execution time: 40.0 ns/at oscillation of 6.25 MHz (When 4
times is used: Machine clock of 25 MHz)
Addressing type: 23 types
Program patch function: 2 address pointer
The maximum memory space:16MB
Port
I/O port (CMOS): 68 ports (shared with resources), (70 ports when the sub clock is not
used)
LCD controller/driver
Segment driver that can drive the LCD panel (liquid crystal display) directly, and
common driver 48 Segments ×4 Commons
Input/Output
timer
16-bit
free run timer
1 Channel
Overflow interruption
Output
comparison
2 Channels
Pin input factor: matching of the compare register
Input capture
2 Channels
Register update by pin input (rise/fall/both edges)
16-bit reload timer
16-bit reload timer operation (Selectable toggle output or one-shot output)
The event count function is optional.
3 channels are built in.
5
CHAPTER 1 OVERVIEW
Table 1.2-1 MB90800 series Product Lineup List (2/2)
Product Lineup
MB90V800101/201
MB90F804101/201
MB90803/
MB90803S
MB90F803/
MB90F803S
16-bit PPG timer
Output Pin ×2
Operation clock frequency: fcp-fcp/27 (8 kinds)
2 channels are built in.
Clock output circuit
Clock with a frequency of external input clock divided by 16/32/64/128 can be output
externally.
I2C bus
One I2C interface channel is built in.
8/10-bit A/D converter
12 channels (input multiplex)
8-bit resolution or 10-bit resolution can be set.
Conversion time:5.9μs (When machine clock 16.8MHz works).
UART
Full-duplicate double-buffer
Asynchronous/synchronous transmit (with start/stop bits)
2 channels are built in.
I/O extended serial Interface
2 channels are built in.
Delay interrupt
1 channel.
DTP/external interrupt
4 channel
Interrupt factor: "L" → "H" edge/"H" → "L" edge/"L" level/"H" level optional
Low-power Consumption Mode
Sleep mode/Timebase timer mode/Watch mode/Stop mode/CPU intermittent mode
Process
CMOS
Operating voltage
3.3V ± 0.3V
Emulator power supply *
Included
-
*:It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used. Please refer to the
MB2147-01 or MB2147-20 hardware manual (3.3 Emulator-dedicated Power Supply Switching) about
details.
6
MB90F809/
MB90F809S
CHAPTER 1 OVERVIEW
1.3
Block Diagram
Figure 1.3-1 shows the block diagram.
■ Block Diagram
Figure 1.3-1 Block Diagram
Clock control
circuit
F2MC-16LX BUS
Port 8
8
Port 0
Port 1
External interrupt
(4ch)
I 2C
P70/AN8/INT3
P71/AN9/SC1
P72/AN10/SO1
P73/AN11/SI2
P74/SDA/SC2
P75/SCL/SO2
P76
P90*
P91*
Prescaler 2/3
OCU0/1
Port 4
ICU0/1
Watch clock output
Reload timer
0/1/2
PPG0/PPG1
Port 5
P50/SEG44/TIN0
P51/SEG45/TIN1
P52/SEG46/TIN2/PPG0
P53/SEG47/PPG1
P54/SI0
P55/SC0
P56/SO0
P57/SI1
P60/AN0
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5/INT0
P66/AN6/INT1
P67/AN7/INT2
Serial I/O 2/3
Free-run timer
P40/LED0
P41/LED1
P42/LED2
P43/LED3
P44/LED4
P45/LED5/TOT0
P46/LED6/TOT1
P47/LED7/TOT2
Port 6
P30/SEG36/SO3
P31/SEG37/SC3
P32/SEG38/SI3
P33/SEG39/TMCK
P34/SEG40/IC0
P35/SEG41/IC1
P36/SEG42/OCU0
P37/SEG43/OCU1
8
Interrupt controller
10 bit
A/D converter
Port 2
P20/SEG28 to P27/SEG35
8
Port 3
P10/SEG20 to P17/SEG27
ROM/Flash (128/256 KB)
12
SEG0 to SEG11
P00/SEG12 to P07/SEG19
RAM (2/4/16/28 KB)
LCD controller/
driver
Port 7
V0/P80
V1/P81
V2/P82
V3
COM0
COM1
P83/COM2
P84/COM3
CPU
F2MC-16LX core
Port 9
X0, X1
X0A*, X1A*
RST
UART0/1
*: X0A/X1A and P90/P91 can be switched by
the option.
X0A/X1A: With sub clock Part number of
products without "S" suffix/201 option.
P90/P91: Without sub clock Part number of
products with "S" suffix/101 option.
Note:
Specification of evaluation device (MB90V800)
No internal ROM provided.
Internal RAM is 28Kbytes.
Prescaler 0/1
7
CHAPTER 1 OVERVIEW
1.4
Package Dimension
The MB90800 series package outline dimensions are shown below.
■ FPT-100P-M06 Package Dimensions
100-pin plastic QFP
Lead pitch
0.65 mm
Package width ×
package length
14.00 × 20.00 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
3.35 mm MAX
Code
(Reference)
P-QFP100-14×20-0.65
(FPT-100P-M06)
100-pin plastic QFP
(FPT-100P-M06)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
23.90±0.40(.941±.016)
* 20.00±0.20(.787±.008)
80
51
81
50
0.10(.004)
17.90±0.40
(.705±.016)
*14.00±0.20
(.551±.008)
INDEX
Details of "A" part
100
0.25(.010)
+0.35
3.00 –0.20
+.014
.118 –.008
(Mounting height)
0~8˚
31
1
30
0.65(.026)
0.32±0.05
(.013±.002)
0.13(.005)
M
0.17±0.06
(.007±.002)
"A"
©2002-2008
FUJITSU MICROELECTRONICS LIMITED F100008S-c-5-6
C
2002 FUJITSU LIMITED F100008S-c-5-5
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
8
0.80±0.20
(.031±.008)
0.88±0.15
(.035±.006)
0.25±0.20
(.010±.008)
(Stand off)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
CHAPTER 1 OVERVIEW
1.5
Pin Assignment
Figure 1.5-1 shows the pin assignment.
■ Pin Assignment
Figure 1.5-1 Pin Assignment
P04/SEG16 81
P05/SEG17 82
P06/SEG18 83
P07/SEG19 84
P10/SEG20 85
P11/SEG21 86
P12/SEG22 87
P13/SEG23 88
P14/SEG24 89
VCC 90
VSS 91
X1 92
X0 93
P15/SEG25 94
P16/SEG26 95
P17/SEG27 96
P20/SEG28 97
P21/SEG29 98
P22/SEG30 99
P23/SEG31 100
P24/SEG32
P25/SEG33
P26/SEG34
P27/SEG35
P30/SEG36/SO3
P31/SEG37/SC3
P32/SEG38/SI3
P33/SEG39/TMCK
P34/SEG40/IC0
P35/SEG41/IC1
P36/SEG42/OCU0
P37/SEG43/OCU1
X0A/P90 *
X1A/P91 *
VCC
VSS
P40/LED0
P41/LED1
P42/LED2
P43/LED3
P44/LED4
P45/LED5/TOT0
P46/LED6/TOT1
P47/LED7/TOT2
P50/SEG44/TIN0
P51/SEG45/TIN1
P52/SEG46/TIN2/PPG0
P53/SEG47/PPG1
P54/SI0
P55/SC0
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P03/SEG15
P02/SEG14
P01/SEG13
P00/SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
VSS
VCC
SEG1
SEG0
P84/COM3
P83/COM2
COM1
COM0
V3
V2/P82
V1/P81
V0/P80
RST
MD0
MD1
MD2
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
P75/SCL/SO2
P74/SDA/SC2
P73/AN11/SI2
P72/AN10/SO1
P71/AN9/SC1
P70/AN8/INT3
VSS
P67/AN7/INT2
P66/AN6/INT1
P65/AN5/INT0
P64/AN4
P63/AN3
P62/AN2
P61/AN1
P60/AN0
AVSS
P76
P57/SI1
AVCC
P56/SO0
*: X0A/X1A and P90/P91 can be switched by the option.
X0A/X1A: With sub clock Part number of products without "S" suffix/201 option.
P90/P91: Without sub clock Part number of products with "S" suffix/101 option.
9
CHAPTER 1 OVERVIEW
1.6
Pin Description
Table 1.6-1 shows the pin functional description.
■ Pin Functional Description
Table 1.6-1 Pin functional Description (1/6)
Pin number
Pin name
QFP
Circuit
type
At a reset/
function
Functional description
Oscillation
state
These are terminals which connect the oscillator.
When connecting an external clock, leave the x1 pin side
unconnected.
B
Oscillation
state
Sub clock oscillation pins (32kHz).
(Dual system clock products)
P90, P91
G
Port input
(Hi-Z)
General-purpose I/O port
(One system clock products)
51
MD2
M
Mode pin
Input pin for selecting operation mode
Connect them directly to VSS.
52, 53
MD1,
MD0
L
Mode Pin
Input pin for selecting operation mode
Connect them directly to VCC.
54
RST
K
Reset input
Input pin for external reset
63, 64,
67 to 72,
73 to 76
SEG0 to
SEG11
LCD SEG
output
Segment output terminals of the LCD controller driver.
D
92, 93
X0, X1
A
X0A, X1A
13, 14
10
CHAPTER 1 OVERVIEW
Table 1.6-1 Pin functional Description (2/6)
Pin number
Pin name
QFP
77 to 84
85 to 89,
94 to 96
97 to 100,
1 to 4
SEG12 to
SEG19
Circuit
type
E
At a reset/
function
Port input
(Hi-Z)
Functional description
Segment output terminals of the LCD controller driver.
P00 to P07
General-purpose I/O port
SEG20 to
SEG27
Segment output terminals of the LCD controller driver.
E
P10 to P17
General-purpose I/O port
SEG28 to
SEG35
Segment output terminals of the LCD controller driver.
E
P20 to P27
General-purpose I/O port
SEG36
A segment output terminal of the LCD controller driver.
P30
5
General-purpose I/O port
E
SO3
Serial data output pin of Serial I/O channel 3
Valid when serial data output of serial I/O channel 3 is
enabled.
SEG37
A segment output terminal of the LCD controller driver.
P31
6
General-purpose I/O port
E
SC3
Serial clock I/O pin of serial I/O channel 3
Valid when serial clock output of serial I/O channel 3 is
enabled.
SEG38
A segment output terminal of the LCD controller driver.
P32
General-purpose I/O port
7
E
SI3
Serial data input pin of serial I/O channel 3
This pin may be used at any time during serial I/O
channel 3 in input mode, so do not use it as other pin
functions.
11
CHAPTER 1 OVERVIEW
Table 1.6-1 Pin functional Description (3/6)
Pin number
Pin name
QFP
Circuit
type
SEG39
8
P33
Port input
(Hi-Z)
E
SEG40,
SEG41
P34, P35
E
17 to 21
22 to 24
E
General-purpose I/O port
OCU0,
OCU1
Output compare output pins
LED0 to
LED4
Output terminals for LED (IOL=15mA).
F
P40 to P44
General-purpose I/O port
LED5 to
LED7
Output terminals for LED (IOL=15mA).
P45 to P47
F
P50, P51
TIN0,
TIN1
General-purpose I/O port
External event output pins of reload timer channel 0 to
channel 2
It is effective when permitting external event output.
SEG44,
SEG45
12
General-purpose I/O port
Segment output terminals of the LCD controller driver.
TOT0 to
TOT2
25, 26
General-purpose I/O port
External trigger input pins of input capture channel 0/
channel 1
SEG42,
SEG43
P36, P37
Segment output terminal of the LCD controller driver.
Segment output terminals of the LCD controller driver.
IC0, IC1
11, 12
Functional description
Clock output pin.
It is effective when permitting the power output.
TMCK
9, 10
At a reset/
function
Segment output terminals of the LCD controller driver.
E
General-purpose I/O port
External clock input pins of reload timer channel 0,
channel 1.
It is effective when permitting external clock input.
CHAPTER 1 OVERVIEW
Table 1.6-1 Pin functional Description (4/6)
Pin number
Pin name
QFP
Circuit
type
SEG46
Port input
(Hi-Z)
P52
27
28
E
Functional description
A segment output terminal of the LCD controller driver.
General-purpose I/O port
TIN2
External clock input pin of reload timer channel 2.
It is effective when permitting external clock input.
PPG0
It is PPG timer ch.0 output terminal.
SEG47
A segment output terminal of the LCD controller driver.
P53
E
General-purpose I/O port
PPG1
It is PPG timer ch.1 output terminal.
SI0
Serial data input pin of UART ch.0
This pin may be used at any time during UART channel
0 in receiving mode, so do not use it as other pin
functions.
29
G
P54
General-purpose I/O port
SC0
Serial clock input/output pin of UART ch.0
It is effective when permitting serial clock output of
UART ch.0.
30
G
P55
General-purpose I/O port
SO0
Serial data output pin of UART ch.0
It is effective when permitting serial data of UART ch.0.
31
G
P56
General-purpose I/O port
SI1
Serial data input pin of UART ch.1
This pin may be used at any time during UART channel
1 in receiving mode, so do not use it as other pin
functions.
33
G
P57
34
At a reset/
function
P76
General-purpose I/O port
G
General-purpose I/O port
13
CHAPTER 1 OVERVIEW
Table 1.6-1 Pin functional Description (5/6)
Pin number
Pin name
QFP
Circuit
type
AN0 to AN4
36 to 40
41 to 43
I
47
AN5 to AN7
Analog input pin channel 5 to 7 of A/D converter.
Enabled when analog input setting is "enabled" (set by
ADER).
P65 to P67
P70
I
General-purpose I/O port
Function as input pins for external interrupt ch.0-ch.2.
Analog input pin channel 8 of A/D converter. Enabled
when analog input setting is "enabled" (set by ADER).
I
General-purpose I/O port
INT3
External interrupt ch.3 input pin
AN9
Analog input pin channel 9 of A/D converter. Enabled
when analog input setting is "enabled" (set by ADER).
P71
I
General-purpose I/O port
SC1
Serial clock input/output pin of UART ch.1
It is effective when permitting serial clock output of
UART ch.1.
AN10
Analog input pin channel 10 of A/D converter. Enabled
when analog input setting is "enabled" (set by ADER).
P72
I
General-purpose I/O port
SO1
Serial data output pin of UART ch.1
It is effective when permitting serial data output of
UART ch.1.
AN11
Analog input pin channel 11 of A/D converter. Enabled
when analog input setting is "enabled" (set by ADER).
P73
48
General-purpose I/O port
I
SI2
14
Analog input pin channel 0 to 4 of A/D converter.
Enabled when analog input setting is "enabled" (set by
ADER).
General-purpose I/O port
AN8
46
Analog
input
(Hi-Z)
Functional description
P60 to P64
INT0 to
INT2
45
At a reset/
function
Serial data input pin of serial I/O ch.2
This pin may be used at any time during serial I/O
channel 2 in input mode, so do not use it as other pin
functions.
CHAPTER 1 OVERVIEW
Table 1.6-1 Pin functional Description (6/6)
Pin number
Pin name
QFP
Circuit
type
At a reset/
function
Port input
(Hi-Z)
SDA
49
H
It is a data input-output terminal in the I2C interface.
This function is enabled when the operation of the I2C
interface is permitted. While the I2C interface is
running, the port must be set for input use.
P74
General-purpose I/O port
(However, N-ch Open drain)
SC2
Serial clock I/O pin of serial I/O channel 2
Valid when serial clock output of serial I/O channel 2 is
enabled.
SCL
It is a clock input-output terminal in the I2C interface.
This function is enabled when the operation of the I2C
interface is permitted. While the I2C interface is
running, the port must be set for input use.
50
H
P75
General-purpose I/O port
(However, N-ch Open drain)
SO2
Serial data output pin of serial I/O channel 2
Valid when serial data output of serial I/O channel 2 is
enabled.
V0 to V2
55 to 57
J
P80 to P82
59, 60
Functional description
COM0, COM1
D
P83, P84
61, 62
E
LCD drive
power
supply
LCD controller/driver reference power supply voltage
pin
LCD COM
output
Common power output terminal of LCD controller/
driver
Port input
(Hi-Z)
General-purpose I/O port
Power
supply
A/D converter-exclusive power supply input pin.
COM2, COM3
General-purpose I/O port
Common power output terminal of LCD controller/
driver
32
AVCC
C
35
AVSS
C
A/D converter-exclusive GND power supply pin.
58
V3
J
LCD controller/driver reference power supply voltage
pin
15, 65, 90
VCC
-
Power input pin.
16, 44, 66, 91
VSS
-
GND power supply pin
15
CHAPTER 1 OVERVIEW
1.7
I/O Circuit Type
Table 1.7-1 shows the I/O circuit types.
■ I/O Circuit Type
Table 1.7-1 I/O circuit types (1/4)
Circuit
Classification
Remark
• Oscillation return resistance about 1MΩ
A
X1
Clock input
P-ch N-ch
X0
Standby control signal
B
X1A
Clock input
P-ch N-ch
• Oscillation feedback resistor for low speed
about 10 MΩ
X0A
Standby control signal
• Analog power supply input protector circuit
C
P-ch
Analog input
N-ch
• LCDC output
D
P-ch
R
LCDC output
N-ch
16
CHAPTER 1 OVERVIEW
Table 1.7-1 I/O circuit types (2/4)
Circuit
Classification
Remark
E
P-ch
Pout
N-ch
Nout
• CMOS output
• LCDC output
• Hysteresis input
(With input interception function at standby)
R
LCDC output
R
Input signal
Standby control
signal
F
P-ch
Pout
N-ch
Nout
• CMOS output
(Heavy-current IOL=15mA for LED drive)
• Hysteresis input
(With input interception function at standby)
R
Input signal
Standby control
signal
G
P-ch
Pout
N-ch
Nout
• CMOS output
• Hysteresis input
(With input interception function at standby)
Note:
Power output and built-in resource output of
input-output port share one output buffer.
Input and built-in resource input of input-output
port share one input buffer.
R
Input signal
Standby control
signal
17
CHAPTER 1 OVERVIEW
Table 1.7-1 I/O circuit types (3/4)
Circuit
Classification
Remark
• Hysteresis input
(With input interception function at standby)
• N-ch open drain output
H
P-ch
Nout
R
Hysteresis input
Standby control
signal
I
P-ch
Pout
N-ch
Nout
R
Input signal
Standby
control signal
A/D converter
analog input
J
P-ch
Pout
N-ch
Nout
CMOS output
CMOS hysteresis input
(With input interception function at standby)
• Analog input
(If the bit of the analog input enable register
(ADER) = 1, analog input of A/D converter is
enable.)
Note:
Power output and built-in resource output of
input-output port share one output buffer.
Input and built-in resource input of input-output
port share one input buffer.
CMOS output
CMOS hysteresis input
(With input interception function at standby)
• LCD drive power supply input
R
Input signal
Standby
control signal
LCD drive
power supply
K
CMOS hysteresis input with pull-up resistor
• Resistance about 50 kΩ
R
R
Reset input
L
CMOS hysteresis input
R
Input
18
CHAPTER 1 OVERVIEW
Table 1.7-1 I/O circuit types (4/4)
Circuit
Classification
Remark
M
CMOS hysteresis input
• Pull-down resistance about 50 kΩ
(without Flash memory products)
R
Input
R
19
CHAPTER 1 OVERVIEW
1.8
Notes Concerning Handling of Device
Observe the following when handling devices.
• Observe the maximum rated voltage (prevention of latch-up)
• Stabilization of supply voltage
• Processing of unused input terminal
• Precautions of using external clock
• Power supply pin
• Crystal oscillator circuit
• Turning-on sequence of power supply to A/D converter and analog inputs
• Handling pins when not using A/D converter
• About the pin processing of using LCD
■ Observing the Maximum Rated Voltage (Prevention of Latch-up)
• In CMOS ICs, a latch-up phenomenon may occur when a voltage exceeding VCC or a voltage below
VSS is applied to input or output pins other than middle/high voltage pins or a voltage exceeding the
rating is applied across VCC and VSS.
• In actual operation, make sure not to exceed the maximum rating because, once latch up has occurred,
drastic increase in power supply current may cause thermal destruction.
• In turning on/turning off the analog power supply, make sure the analog power voltage (AVCC) and
analog input voltage should not exceed the digital power supply voltage (VCC).
■ Stabilization of Supply Voltage
Even within the operation guarantee range, a rapid change of power supply voltage can cause a malfunction
so be sure to stabilize the VCC power supply voltage.
As a criteria for stabilization, stabilize the power supply voltage so that the VCC ripple fluctuation (Peak to
Peak value) at commercial frequency (50 to 60 Hz) should be below 10 of the standard VCC power supply
voltage value. For instantaneous voltage fluctuation at power supply switching, stabilize power supply
voltage so that the transient fluctuation should be below the 0.1V/ms.
■ Processing of Unused Input Terminal
Leaving unused input pins unconnected can cause a malfunction or latch-up which may cause permanent
damage. To prevent this, clamp the pin level by connecting it to a pull-up or a pull-down resistor of 2 kΩ or
higher. Also if any input/output pins are unused, set them to the output state and leave them open or set
them to the input state and apply the same treatment as for input pins.
20
CHAPTER 1 OVERVIEW
■ Precautions of Using External Clock
In using an external clock, drive pin X0 only and leave pin X1 unconnected. The example of Using an
External Clock is shown below.
X0
MB90800 series
OPEN
X1
Please set X0A=GND and X1A=open without subclock mode. The following figure shows the using
sample.
X0A
MB90800 series
OPEN
X1A
■ About Power pins
• When there are a number of VCC/VSS terminals, for device design purposes, those terminals that should
have the same potential are connected within the device in order to prevent a latch-up or other erroneous
operation. To reduce extraneous emission, prevent erroneous operation of the strobe signal due to
increases in the ground level, and to maintain the total output current standard, connect the VCC/VSS
terminals to an external power source and ground them.
• Make sure to connect VCC and VSS pins to MB90800 devices via lowest impedance from the current
supply source.
• To prevent power supply noise, connect a bypass capacitor of around 0.1 μF between VCC and VSS pins
near the device.
■ Crystal Oscillator Circuit
Noise around X0 and X1pins may be possible causes of abnormal operations. Make sure to design a printed
circuit board so that the X0 and X1 pins, the crystal resonator (or ceramic resonator) and the bypass
capacitor are arranged near the X0 and X1pins and the lines of the X0 and X1pins will not cross other lines.
Stable operation can be expected from the printed circuit art work that encloses the X0 and X1 terminals
with the ground.
Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device.
■ Procedure of A/D Converter/Analog Input Power-on
• Make sure to turn on the A/D converter power supply (AVCC) and analog inputs (AN0 to AN11) after
turning on the digital power supply (VCC).
• Turn off the digital power supply (VCC) after turning off the A/D converter power supply and analog
input.
21
CHAPTER 1 OVERVIEW
• When using a port pin shared with analog input as an input port, make sure that the analog input voltage
should not exceed AVCC.
■ Pin handling when no A/D Converter is Used
If no A/D converter is used, connect as AVCC = VCC and AVSS = VSS.
■ About the Terminal Processing of Using LCD
COM0 to COM3 pins and SEG0 to SEG11 pins are opened. Please process pull-up or pull-down to V0 to
V3 pins through the resistance of 2kΩ or more.
22
CHAPTER 1 OVERVIEW
1.9
Clock Supply Map
Figure 1.9-1 shows the clock supply map.
■ Clock Supply Map
Figure 1.9-1 Clock Supply Map
Clock generation circuit
Watch clock divider
X0
X1
Oscillation
circuit
Watch timer
Watchdog timer
Selector
X0A
X1A
Internal resource group
Oscillation
circuit
Timebase timer
1
2
3
4
Multiple circuit
LCD control block
16-bit reload timer
8/10-bit A/D converter
Serial I/O
Free-run timer
Input capture
Output compare
PCLK
CPU(F2MC-16LX)
2-division circuit
HCLK
Selector
MCLK
ROM/RAM (memory)
2-division circuit
SCLK
HCLK : Oscillation clock frequency
MCLK : Main clock frequency
PCLK : PLL clock frequency
SCLK : Sub clock frequency
23
CHAPTER 1 OVERVIEW
1.10
Low-power Consumption Mode
This section explains an overview of low-power consumption mode. The MB90800
series provides the following modes. Depending on mode, different functions/clocks
stop. Please refer to "CHAPTER 4 CLOCK" for details.
■ Operating State of Low-power Consumption Mode
Table 1.10-1 Operating State of Low-power Consumption Mode
PLL
Main
Clock
Sub
Clock
PLL
Clock
Operation
Operation
Operation
PLL sleep
CPU
Operation
Peripheral
Operation
Watch
Timebase
Timers
Operation
Operation
Stops
PLL timebase timer
Clock
source
PLL
Clock
Stops
PLL Stop
Stops
Stops
Stops
Stops
Stops
PLL Oscillation
Stabilization Waiting
Operation
Operation
Operation
Operation
Operation
Main
Operation
Operation
Stops
Operation
Operation
Main sleep
Operation
Operation
Stops
Main timebase timer
Main
Clock
Stops
Main stop
Stops
Stops
Stops
Stops
Main Oscillation
Stabilization Waiting
Operation
Operation
Operation
Operation
Sub
Stops
Operation
Operation
Stops
Sub
Clock
Operation
Main
Clock
Stops
Sub sleep
Operation
Operation
Stops
Watch
Stops
Sub-stop
Stops
Stops
Sub Oscillation
Stabilization Waiting
Operation
Operation
Power on reset
Reset
24
Operation
Operation
Stops
Operation
Stops
Stops
Operation
CHAPTER 2
CPU
This chapter describes the features of the MB90800
series CPU and its memory space.
2.1 CPU
2.2 Memory Space
2.3 Memory Map
2.4 Addressing
2.5 Allocation of Multi-byte Data on Memory
2.6 Registers
2.7 Dedicated Registers
2.8 General-purpose Register
2.9 Prefix Code
25
CHAPTER 2 CPU
2.1
CPU
The F2MC-16LX CPU core is a 16-bit CPU designed for applications such as consumer
appliances or automobile electronics requiring high-speed real time processing. The
F2MC-16LX instruction set has been specifically designed for high-speed and highthroughput controller applications.
The F2MC-16LX CPU core contains an internal 32-bit accumulator for 32-bit data
processing. The maximum memory space is 16M bytes and it is addressable either in
linear-or bank-access mode. The instruction repertoire is based on the F2MC-8L AT
architecture and enhanced by adding the C language feature instructions, extended
addressing modes, multiply/divide instructions, and bit processing functions. Next, the
feature of F2MC-16LX CPU is shown.
■ CPU
● Minimum instruction execution time: 40.0 ns (6.25MHz: quadruple clock mode)
● The maximum memory space is 16M bytes and it is addressable either in linear-or bank-access mode.
● Instruction
Data types: Bit/Byte/Word/Long word
Addressing mode: 23 types
Extended arithmetic precision with 32-bit accumulator
Signed multiplication and division, and enhanced RETI instructions
● Interrupt Function
Eight priority levels (programmable)
● Automatic forwarding function not shown in CPU
Extended and intelligent I/O service to 16ch or less
● Instruction set geared for C language and multi-tasking
System stack pointer, instruction set symmetry and barrel shift instructions
● Higher execution speed: 4 bytes que
26
CHAPTER 2 CPU
2.2
Memory Space
The F2MC-16LX I/O ports, programs and data are allocated in the 16M-byte memory
space. The RAM area is used for extended intelligent I/O service (EI2OS) descriptors,
general-purpose registers, vector tables, etc.
■ Memory Space
The I/O ports, programs, and data are allocated in the 16M-byte memory space of F2MC-16LX CPU. The
CPU can access to incorporated peripheral functions (resources) by specifying the memory space addresses
through the 24-bit address bus.
Figure 2.2-1 Example of Relationship between F2MC-16LX System and Memory Map
F2MC-16LX device
FFFFFFH
Vector table area
FFFC00H
Program
FF0000H
*1
ROM area
Program area
F2MC-16LX
CPU
Internal data bus
100000H
External area*4
010000H
Data
004000H
002000H
000D00H
EI2OS
000380H
000180H
000100H
Interrupt
Peripheral
circuit
General
-purpose port
0000C0H
0000B0H
000020H
000000H
*2
ROM area
(Image of FF bank)
External area*4
*3
Data area
General-purpose register
RAM area
EI2OS descriptor area
External area*4
Interrupt control register area
Peripheral function control register area
I/O area
I/O port control register area
*1 : Capacitance of built-in ROM is different depending on products.
*2 : The area which can be accessed by image is different depending on products.
*3 : Capacitance of built-in ROM is different depending on products.
*4 : Without access at single-chip mode.
27
CHAPTER 2 CPU
■ ROM Area
● Vector table area (address: FFFC00H to FFFFFFH)
• This is used as a vector table for vector call instructions, interrupt vectors, and reset vectors.
• This is allocated in the highest addresses of the ROM area and used to set the start addresses of
corresponding routines at the addresses of the vector table for vector call instructions, interrupt vectors,
and reset vectors as data.
● Program area (address: to FFFBFFH)
• ROM is contained as the internal program area.
• The capacity of the internal ROM depends on the product.
■ RAM Area
● Data area (address: from 000100H)
• Static RAM is contained as the internal data area.
• The capacity of the internal RAM depends on the product.
● General-purpose register area (address: 000180H to 00037FH)
• General-purpose registers are allocated for 8-, 16-, or 32-bit arithmetic and transfer operations.
• The area can be used as ordinary RAM when not used as general-purpose registers.
• When the area is used as general-purpose registers, general-purpose register addressing scheme is
enabled, allowing accesses with short instruction cycles.
● Expanded intelligent I/O service (EI2OS) descriptor area (address: 000100H to 00017FH)
• Sets the extended intelligent I/O service (EI2OS) transfer mode, I/O addresses, transfer count, and buffer
addresses.
• If the extended intelligent I/O service (EI2OS) should not be used, this area can be used as normal RAM
area.
■ I/O Area
● Interrupt control register area (addresses: "0000B0H to 0000BFH")
The interrupt control registers (ICR00 to ICR15) are corresponding to the embedded peripheral functions
(resources) with interrupt functions. Following can be set: interrupt level setting, the extended intelligent I/
O service (EI2OS).
● Peripheral function control register area (address: 000020H to 0000AFH)
The built-in peripheral function (resource) can be set.
● Input/output port control register area (addresses: "000000H to 00001FH")
The input-output port can be set.
28
CHAPTER 2 CPU
2.3
Memory Map
MB90800 series memory map is shown for each device.
■ Memory Map
Figure 2.3-1 Memory Map
(with ROM mirror function)
FFFFFFH
ROM area
Address #2
00FFFFH
008000H
007917H
007900H
ROM mirror area
32KB
Extended I/O area 2
Address #1
Register
RAM
area
000100H
0000CFH
0000C0H
0000BFH
000000H
Extended I/O area 1
I/O area
Model
Address #1
Address #2
MB90803/S, MB90F803/S
0010FFH
FE0000H
MB90F809/S
0028FFH
FD0000H
MB90F804-101/201
0040FFH
FC0000H
MB90V800-101/201
0070FFH
F80000H*
*: ROM is not built into the MB90V800. Treat this address as the ROM decode area used by the tools.
The ROM mirror function is for using the C compiler small model.
The lower 16-bit addresses of bank FF are equivalent to those of bank 00. Note that because the ROM area
of bank FF exceeds 32K bytes, all data in the ROM area cannot be shown in mirror image in bank 00.
When the C compiler small model is used, the data table mirror image can be shown at "008000H" to
"00FFFFH" by storing the data table at "FF8000H" to "FFFFFFH". Therefore, data tables in the ROM area
can be referred without declaring the far addressing with the pointer.
29
CHAPTER 2 CPU
Notes:
• When the ROM mirror function register has been set, the mirror image data at higher addresses
("FF4000H" to "FFFFFFH") of bank FF is visible from the higher addresses ("008000H" to
"00FFFFH") of bank 00.
• For setting of the ROM mirror function, see "Chapter 24 ROM Mirror Function Selection Module".
30
CHAPTER 2 CPU
2.4
Addressing
There are two address generation modes: linear mode and bank mode.
In the linear mode, the 16M-byte space is specified directly by contiguous 24-bit
addresses.
In the bank mode, the 16M-byte space is divided into 256 64K-byte banks, allowing to
specify the higher 8-bit addresses with the bank registers and to specify the lower 16-bit
addresses directly by the instruction.
The F2MC-16LX family uses basically bank addressing.
■ Linear Addressing and Bank Addressing
Figure 2.4-1 Memory Management in Linear and Bank Types
Linear mode
FFFFFFH
Bank mode
FFFFFFH
FF0000H
FEFFFFH
FE0000H
FDFFFFH
FD0000H
123456H
FF bank
64 Kbytes
FE bank
FD bank
123456H
12 bank
04FFFFH
040000H
03FFFFH
030000H
02FFFFH
020000H
01FFFFH
010000H
00FFFFH
000000 H
000000H
123456H
Specification by all instruction
04 bank
03 bank
02 bank
01 bank
00 bank
123456H
Specification by instruction
Setting by bank register corresponding for use
31
CHAPTER 2 CPU
2.4.1
Linear Addressing
There are two types of linear addressing, the method to directly specify the 24-bit
address by the operand and the method to quote the lower 24 bits as the address out of
32-bit general-purpose register content.
■ Linear Addressing by Specifying 24-bit Operand
Figure 2.4-2 Example of 24-bit Physical Direct Addressing in Linear Type
JMPP 123456H
Old program counter
+ program bank
17
452D
17452DH
New program counter
12
+ program bank
3456
123456H
JMPP 123456H
Next instruction
■ Addressing by Indirect-specifying 32-bit Register
Figure 2.4-3 Example of indirect-specifying 32-bit General-purpose Register in Linear Type
MOV A,@RL1+7
Old AL
XXXX
090700 H
3AH
+7
New AL
003A
RL1
(Ignore upper 8-bit)
RL1 : 32-bit (long word) general purpose register
32
240906F9H
CHAPTER 2 CPU
2.4.2
Bank Addressing
For bank-mode addressing, the 16M-byte memory space is divided into 256 64K-byte
banks, allowing to specify the higher 8 bits of the address with the bank registers. The
lower 16-bit addresses are directly specified in the instruction.
Bank register has the following five types depending on the use.
• Program counter bank register (PCB)
• Data bank register (DTB)
• User stack bank register (USB)
• System stack bank register (SSB)
• Additional data bank register (ADB)
■ Bank Registers and Access Space
Table 2.4-1 Access Space of Each Bank Register and Main Usage
Bank register name
Access space
Main usage
At a reset
Program counter bank
register (PCB)
Program (PC) space
Stores the instruction codes, vector tables, and
immediate data.
FFH
Data bank register
(DTB)
Data (DT) space
Sores the readable/writable data, and accesses to the
control register/data register of internal/external
peripherals.
00H
User stack bank register
(USB)
Stack (SP) space
These are used for the stack accessing such as the
PUSH/POP instruction and the register saving at an
interrupt.
SSB is used when the stack flag (CCR: S) of the
condition register is "1", and USB is used when it is
"0".*
00H
00H
Data etc. not to finish entering data (DT) space are
stored.
00H
System stack bank
register (SSB)*
Additional data bank
register (ADB)
Additional (AD)
space
*: SSB is always used for the stack at an interrupt.
For the details of bank registers, see "2.7.9 Bank Register (PCB, DTB, USB, SSB, and ADB)".
33
CHAPTER 2 CPU
Figure 2.4-4 Example of Bank Addressing
FFFFFFH
FF0000 H
Program
space
FFH
: PCB (Program counter bank register)
0FH
: ADB (Additional data bank register)
0DH
: USB (User stack bank register)
0BH
: DTB (Data bank register)
07H
: SSB (System stack bank register)
Physical address
0FFFFF H
0F0000 H
0DFFFFH
0D0000 H
Additional
space
User stack
space
0BFFFFH
Data space
0B0000 H
07FFFF H
070000 H
System stack
space
000000 H
■ Bank Addressing and Default Space
For improving the instruction coding efficiency, the default space is defined for each addressing method of
instructions as listed in Table 2.4-2 .When using space other than the default space, set the prefix code for
the related bank preceding the instruction to enable accessing the bank space related to the prefix code. For
the details of prefix code, see "2.9 Prefix Code".
Table 2.4-2 Addressing and Default Spaces
Default spaces
34
Addressing
Program space
PC indirect addressing, program-access addressing, branch instruction addressing
Data space
Addressing with @RW0,@RW1,@RW4,@RW5,@A.addr16.dir
Stack space
Addressing with PUSHW,POPW,@RW3,@RW7
Additional space
Addressing with @RW2 and @RW6
CHAPTER 2 CPU
2.5
Allocation of Multi-byte Data on Memory
Multi-byte data is written to memory in sequence starting from the low address. 32-bit
long data is transferred in the order of the lower 16 bits and then the higher 16 bits.
Note that if an external reset signal is input immediately after writing the lower 16 bits,
the higher 16 bits may not be transferred.
■ Store of Multi-byte Data in RAM
Lower 8 bits are allocated to n address, and in order of n + 1, n + 2, n + 3.
Figure 2.5-1 Store of Multi-byte Data in RAM
MSB
"H"
LSB
01010101B 11001100B 11111111B 00010100B
01010101B
11001100B
11111111B
n address
00010100B
"L"
MSB : Uppermost bit
LSB : Lowest bit
■ Storage of Multi-byte Length Operand
Figure 2.5-2 Storage of Multi-byte Operand
JMPP 123456H
"H"
JMPP 1 2 3 4 5 6H
12H
34H
56H
n address
63H
"L"
35
CHAPTER 2 CPU
■ Storage of Multi-byte Data in Stack
Figure 2.5-3 Storage of Multi-byte Data in Stack
PUSHW RW1,RW3
"H"
PUSHW
RW1,
RW3
(35A4H) (6DF0H)
SP
6DH
F0H
35H
A4H
n address
"L"
RW1 : 35A4H
RW3 : 6DF0H
Note: Stack state of after PUSHW instruction execution
■ Access to Multi-byte Data
Accessing to multi-byte data is in principle performed within a bank. For an command that accesses multibyte data, the address following "FFFFH" is "0000H" in the same bank.
Figure 2.5-4 Access to Multi-byte Data on Bank Boundary
"H"
AL before execution
80FFFFH
??
??
23H
01H
01H
MOVW A, 080FFFFH
800000H
"L"
36
23H
AL after execution
CHAPTER 2 CPU
2.6
Registers
F2MC-16LX has the dedicated registers incorporated in the CPU and the generalpurpose registers allocated in the built-in RAM.
■ Dedicated Registers and General-purpose Register
The dedicated registers are hardware in the CPU and their usage is predefined by the CPU architecture.
The general-purpose registers coexist with RAM in the CPU address space. The general-purpose registers
are similar to dedicated registers in that they are accessible by the register numbers. They can be used as
ordinary memory as specified by the users.
Figure 2.6-1 Dedicated Registers and General-purpose Register
CPU
Dedicated register
RAM
RAM
General purpose
register
Accumulator
User stack pointer
Processor status
Program counter
Direct page register
Program bank register
Internal data bus
System stack pointer
Data bank register
User stack bank register
System stack bank register
Additional data bank register
37
CHAPTER 2 CPU
2.7
Dedicated Registers
The CPU incorporates 11 dedicated registers listed below.
• Accumulator (A)
• User stack pointer (USP)
• System stack pointer (SSP)
• processor status (PS)
• Program counter (PC)
• Direct page register (DPR)
• Program counter bank register (PCB)
• Data bank register (DPP)
• User stack bank register (USB)
• System stack bank register (SSB)
• Additional data bank register (ADB)
■ Configuration of Dedicated Registers
Figure 2.7-1 Configuration of Dedicated Registers
AH
AL
: Accumulator (A)
16-bit  2 register used for storing of calculating result.
Usable as 32-bit register continuously
USP
: User stack pointer (USP)
16-bit pointer for indicating user stack address
SSP
: System stack pointer (SSP)
16-bit pointer for indicating system stack address
PS
: Processor status (PS)
16-bit register for indicating system state
PC
: Program counter (PC)
16-bit counter register for indicating program address
DPR
: Direct page register (DPR)
When executing contraction direct addressing, indicates
bit8 to bit15 of operand address. Page register of 8-bit.
PCB
: Program counter bank register (PCB)
8-bit bank register for indicating program space
DTB
: Data bank register (DTB)
8-bit bank register for indicating data space
USB
: User stack bank register (USB)
8-bit bank register for indicating user stack space
SSB
: System stack bank register (SSB)
8-bit bank register for indicating system stack space
ADB
8 bits
: Additional data bank register (ADB)
8-bit bank register for indicating additional space
16 bits
32 bits
38
CHAPTER 2 CPU
Table 2.7-1 Dedicated Registers
Dedicated register
Initial value
Accumulator (A)
Undefined
User stack pointer (USP)
Undefined
System stack pointer (SSP)
Undefined
Program counter (PC)
Direct page register (DPR)
Program counter bank register
(PCB)
Data bank register (DTB)
PS
bit15 to bit13 bit12
ILM
0
0
0
0
0
to
RP
0
bit8 bit7
0
0
-
0
1
to
CCR
X
X
bit0
X
X
X
Value in reset vector (contents of FFFFDCH, FFFFDDH)
01H
Value in reset vector (contents of FFFFDEH)
User stack bank register (USB)
00H
System stack bank register
(SSB)
00H
Additional data bank register
(ADB)
00H
Processor status (PS)
00H
Note:
The initial values shown above are device initial values and will be different from ICE (emulator, etc.)
39
CHAPTER 2 CPU
2.7.1
Accumulator (A)
The accumulator (A) consists of two 16-bit arithmetic registers (AH and AL). These
registers are used for temporary storage of operation results and/or data.
Accumulator (A) can be used as 32/16/8-bit registers. Operations can be performed
between memory and other registers, or between the higher 16-bit arithmetic register
(AH) and the lower 16-bit arithmetic register (AL). In addition, when data, word long or
less, is transferred to the lower 16-bit arithmetic register (AL), the transferred data is
stored and held in the higher 16-bit arithmetic register (AH) (Data is not held for some
instructions).
■ Accumulator (A)
● Data transfer to accumulator
The accumulator can process 32-bit (long word), 16-bit (word), and 8-bit (byte) data. As an exception,
there is a 4-bit data transfer instruction (MOVN), which is processed similarly to 8-bit data.
• For 32-bit data processing, the higher arithmetic register (AH) and lower arithmetic register (AL) are
concatenated.
• For 16-or 8-bit data, the lower arithmetic register (AL) is used; the higher arithmetic register (AH) holds
data of the lower arithmetic register (AL).
• Data of byte length or less transferred to the lower arithmetic register (AL) is sign-or zero-extended to
16-bit data and stored in the lower arithmetic register (AL). The data stored in the lower arithmetic
register (AL) can be treated as 16-or 8-bit data.
For actual transfer examples, see Figure 2.7-3 to Figure 2.7-6 .
Figure 2.7-2 Data transfer to accumulator
32 bits
AH
AL
32-bit data transmission
Data transmission Data transmission
AH
16-bit data transmission
AL
Data evacuation
Data transmission
AH
8-bit data transmission
AL
Data evacuation
Data transmission
"00H" or "FFH"*
(Zero expansion or symbol expansion)
* : When 4-bit transmitting instruction, it becomes "000H" or "FFFH".
40
CHAPTER 2 CPU
● Arithmetic operation of byte processing of accumulator
When an arithmetic instruction for byte processing is executed for the lower arithmetic register (AL), the
higher 8 bits of the lower arithmetic register (AL) are ignored and the higher 8 bits of the arithmetic
operation result are set to all "0. "
● Initial value of accumulator
Initial value becomes undefined after reset.
Figure 2.7-3 Example of transfer between AL and AH of accumulator (A)
(8-bit immediate value, zero extension)
MOV A,3000H
(Instruction for zero expanding contents of 3000H address
and storing in AL register)
MSB
Before
execution
AH
AL
XXXXH
2456H
DTB
After
execution
2456H
B53000H
Memory space
77H
LSB
88H
B5H
: Undefined
X
MSB : Uppermost bit
LSB : Lowest bit
DTB : Data bank register
0088H
Figure 2.7-4 Example of transfer between AL and AH of accumulator (A)
(8-bit immediate value, sign extension)
MOVW A,3000H
(Instruction for storing in AL register contents of 3000H address)
MSB
Before
execution
AH
AL
XXXXH
2456H
DTB
After
execution
2456H
7788H
B53000H
Memory space
77H
LSB
88H
B5H
X : Undefined
MSB : Uppermost bit
LSB : Lowest bit
DTB : Data bank register
41
CHAPTER 2 CPU
Figure 2.7-5 Example of 32-bit data transfer to accumulator (A) (register indirect)
(Instruction for executing long word length read as address for result of
RW1 contents + 3-bit length offset and storing its contents in A register)
MOVL A,@RW1+6
Before
execution
AH
XXXXH
AL
XXXXH
A6H
DTB
After
execution
8F74H
MSB
Memory space
A61540H
A6153EH
8FH
2BH
74H
52H
RW1
15H
38H
LSB
+6
2B52H
X : Undefined
MSB : Uppermost bit
LSB : Lowest bit
DTB : Data bank register
Figure 2.7-6 Example of transfer between AL and AH of accumulator (A) (16 bits, register indirect)
(Instruction for executing word length read as address for result of
RW1 contents + 8-bit length offset and storing its contents in A register)
MOVW A,@RW1+6
AH
Before
execution
XXXXH
1234H
DTB
After
execution
1234H
MSB Memory space
AL
2B52H
A6153EH
8FH
2BH
74H
52H
RW1
15H
38H
A61540H
A6H
+6
X : Undefined
MSB : Uppermost bit
LSB : Lowest bit
DTB : Data bank register
42
LSB
CHAPTER 2 CPU
2.7.2
Stack Pointer (USP, SSP)
There are two stack pointers: user stack pointer (USP) and system stack pointer (SSP);
they are used to indicate the addresses where data is saved or control returned when
the PUSH/POP instruction or subroutines are executed. The higher 8 bits of the stack
address are specified in the user stack bank register (USB) or system stack bank
register (SSB).
The USP and USB registers are enabled when the S flag in the condition code register
(CCR) is "0", and the SSP and SSB register are enabled when the S flag is "1".
■ Setting of Stack
For F2MC-16LX, two types of stacks: system stack and user stack are available. The stack addresses are
determined according to the S flag in the processor status (PS: CCR) as listed in Table 2.7-2 .
Table 2.7-2 Stack Address Specification
Stack address
S flag
Higher 8 bits
Lower 16 bits
0
User stack bank register (USB)
User stack pointer (USP)
1
System stack bank register (SSB)
System stack pointer (SSP)
: Initial value
Because the S flag is initialized to "1" by reset, the system stack is used at initial setting. When an interrupt
has been accepted, the stack flag (CCR: S) is set to "1", the system stack pointer is always used, and, for
stack operation other than an interrupt routine, the user stack is used. If the stack space is not to be divided,
use the system stack.
43
CHAPTER 2 CPU
Figure 2.7-7 Stack Operation Instructions and Stack Pointers
PUSHW A at S flag = "0"
Before
executing
AL
A624H
USB C6H
USP F328H
0
SSB 56H
SSP 1234H
A624H
USB C6H
USP F326H
SSB 56H
SSP 1234H
S flag
After
executing
AL
MSB
S flag
0
C6F326H
LSB
XXH
XXH
User stack is used because
S flag is "0".
C6F326H
A6H
24H
PUSHW A at S flag = "1"
MSB
Before
executing
AL
USB C6H
USP F328H
1
SSB 56H
SSP 1234H
A624H
USB C6H
USP F328H
SSB 56H
SSP 1232H
A624H
S flag
After
executing
AL
S flag
1
LSB
561232 H
XXH
XXH
561232 H
A6H
24H
User stack is used because
S flag is "1".
: Undefined bit
X
MSB : Uppermost bit
LSB : Lowest bit
Notes:
• For stack addresses in the stack pointer, use an even address. Whenever an odd address is set,
word access is divided into two, and access efficiency is degraded.
• The USP and SSP register initial values are undefined.
• Allocate the system stack, user stack, and data areas so that they do not overlap each other.
■ System Stack Pointer (SSP)
When setting the system stack pointer (SSP), set "1" in the S flag in the condition code register (CCR).
When "1" is set in the S flag, the higher 8 bits of the address used for stack operation are indicated in the
system stack bank register (SSB).
For details of the condition code register (CCR), see "2.7.4 Condition Code Register (PS: CCR)". For
details of system stack bank register (PS: CCR), see "2.7.9 Bank Register (PCB, DTB, USB, SSB, and
ADB)".
■ User Stack Pointer (USP)
When setting the user stack pointer (USP), set "0" in the S flag in the condition code register (CCR). When
"0" is set in the S flag, the higher 8 bits of the address used for stack operation are indicated in the user
stack bank register (USB).
For details of the condition code register (CCR), see "2.7.4 Condition Code Register (PS: CCR)". For
details of system stack bank register (PS: CCR), see "2.7.9 Bank Register (PCB, DTB, USB, SSB, and
ADB)".
44
CHAPTER 2 CPU
2.7.3
Processor Status (PS)
The processor status (PS) consists of the bits controlling CPU and various bits
indicating the CPU status. The PS register consists of three registers listed below.
• Interrupt level mask register (ILM)
• Register bank pointer (RP)
• Condition Code Register (CCR)
■ Configuration of Processor Status (PS)
The processor status (PS) consists of bits controlling CPU and various bits indicating the CPU status.
Figure 2.7-8 Configuration of Processor Status (PS)
ILM
RP
CCR
Bit
15 14 13 12 11 10
9
8
PS
ILM2 ILM1 ILM0 B4 B3 B2 B1 B0
7
6
5
4
3
2
1
0
I
S
T
N
Z
V
C
● Condition code register (CCR)
Consists of various flags which are set to "1" or cleared to "0" according to the instruction execution results
or interrupt output.
For details of the flags, see "2.7.4 Condition Code Register (PS: CCR)".
● Register bank pointer (RP)
Pointer that sets the start address of the memory block (register bank) used as general-purpose registers in
the RAM area.
There are 32 banks of general-purpose registers and one of the banks is specified by setting value "00H" to
"1FH" in the register bank pointer (RP).
For the setup method and details, see "2.7.5 Register Bank Pointer (PS: RP)".
● Interrupt level mask register (ILM)
Indicates the level of the interrupt currently accepted by the CPU and compares it with the interrupt level
set bits (ICR: IL0 to IL2) of the interrupt control registers (ICR00 to ICR15) set corresponding to the
interrupt request for each peripheral function (resource).
For the setup method and details, see "2.7.6 Interrupt Level Mask Register (PS:ILM)".
45
CHAPTER 2 CPU
2.7.4
Condition Code Register (PS: CCR)
The condition code register (CCR) is an 8-bit register consisting of the bits shown
below.
• Bit by which content of result and forwarding data is shown
• Bit by which acceptance of interrupt request is controlled
■ Configuration of Condition Code Register (CCR)
For the state of the condition code register (CCR) during instruction execution, refer to "F2MC-16LX
Programming Manual".
Figure 2.7-9 Configuration of Condition Code Register (CCR)
ILM
RP
CCR
Bit
15 14 13 12 11 10
PS
ILM2 ILM1 ILM0 B4 B3 B2 B1 B0
9
8
7
6
5
4
3
2
1
0
I
S
T
N
Z
V
C
CCR initial value
X01XXXXXB
Instruction enable flag
Stack flag
Sticky bit flag
Negative flag
Zero flag
Overflow flag
Carry flag
X : Indefinite
: Undefined
● Interrupt flag (I)
An interrupt request is enabled when "1" is set in the interrupt enable flag (I) corresponding to interrupt
request other than software interrupts and it is disabled when the interrupt enable flag (I) is cleared to "0". It
is cleared to "0" by external or software reset.
● Stack flag (S)
Flag indicating the pointer used for stack operation. The user stack pointer (USP) is enabled when the stack
flag (S) is cleared to "0" and the system stack pointer (SSP) is enabled when "1" is set in the stack flag (S).
When an interrupt request is accepted or the external reset and software reset are asserted, "1" is set.
For details of the stack pointers, see "2.7.2 Stack Pointer (USP, SSP)".
● Sticky-bit flag (T)
After executing a logical right-shift instruction or arithmetic right-shift instruction, "1" is set in the sticky
bit flag (T) if the data shifted out of the carry contains "1" and the sticky bit flag (T) is cleared to "0" if that
data does not contain "1". In addition, it is cleared to "0" if the shift count is zero.
46
CHAPTER 2 CPU
● Negative flag (N)
The negative flag (N) is set to "1" when the most significant bit (MSB) of the general-purpose registers
(RL0 toRL3) storing the arithmetic result is "1" and the negative flag (N) is cleared to "0" when the most
significant bit (MSB) of the general purpose registers (RO0 to RL3) storing the arithmetic operation result
is "0".
For details of general-purpose registers, see "2.8 General-purpose Register".
● Zero flag (Z)
The zero flag (Z) is set to "1" when the value of the general-purpose registers (RL0 to RL3) storing the
arithmetic operation result is "0000H" and the zero flag (Z) is cleared to "0" when the value of the generalpurpose registers (RL0 to RL3) storing the arithmetic operation result is not "0000H".
● Overflow flag (V)
The overflow flag (V) is set to "1" when an overflow has occurred as a signed numeric value during
arithmetic operations and the overflow flag (V) is cleared to "0" when no overflow has occurred.
● Carry flag (C)
The carry flag (C) is set to "1" when a carry from the most significant bit or a carry-down to the most
significant bit has occurred during arithmetic operation and the carry flag (C) is cleared to "0" when no
carry or carry-down has occurred.
47
CHAPTER 2 CPU
2.7.5
Register Bank Pointer (PS: RP)
The register bank pointer (RP) is a 5-bit register that indicates the starting address of
the currently used general-purpose register bank.
■ Register Bank Pointer (RP)
Figure 2.7-10 Configuration of Register Bank Pointer (RP)
ILM
RP
CCR
Bit
15 14 13 12 11 10
9
8
PS
ILM2 ILM1 ILM0 B4 B3 B2 B1 B0
7
6
5
4
3
2
1
0
I
S
T
N
Z
V
C
RP initial value
00000B
■ General-purpose Register Area and Register Bank Pointer
The register bank pointer (RP) is a pointer indicating the relationship between the general-purpose registers
of F2MC-16LX and the internal RAM addresses. The relationship between the register bank pointer (RP)
contents and addresses are based on the conversion rules shown in Figure 2.7-11 .
Figure 2.7-11 Physical Address Conversion Rules in General-purpose Register Area
Conversion formula [000180H + (RP)
10H]
At RP=10H
000370 H
Register bank 31
:
:
000280 H
Register bank 16
:
:
000180 H
Register bank 0
• As the register bank pointer (RP) can define a value "00H" to "1FH", the register bank start address can
be set in the range of "000180H" to "00037FH".
• For assembler instructions, an 8-bit immediate value transfer instruction for transferring to the register
bank pointer (RP) can be used. Note that data of the lower 5 bits is valid.
• The register bank pointer (RP) is initialized to "00000B" by a reset.
48
CHAPTER 2 CPU
2.7.6
Interrupt Level Mask Register (PS:ILM)
The interrupt level mask register (ILM) is a 3-bit register indicating the level of the
interrupt accepted by the CPU.
■ Interrupt Level Mask Register (ILM)
For details of interrupt, see "CHAPTER 6 INTERRUPT".
Figure 2.7-12 Composition of Interrupt Level Mask Register (ILM)
RP
ILM
CCR
Bit
15 14 13 12 11 10
PS
ILM2 ILM1 ILM0 B4 B3 B2 B1 B0
9
8
7
6
5
4
3
2
1
0
I
S
T
N
Z
V
C
ILM initial value
000B
The interrupt level mask register (ILM) indicates the current interrupt level.
The interrupt level mask register (ILM), sets an acceptable interrupt level. Interrupts with level values
lower than the interrupt level value set in the interrupt level mask register (ILM) are not accepted.
• The interrupt level mask register (ILM), when reset, has the highest interrupt level, allowing to accept
no interrupts.
• For assembler instructions, an 8-bit immediate value transfer instruction for transferring to the interrupt
level mask register (ILM) can be used. Note that data of the lower 3 bits is valid.
Table 2.7-3 Interrupt Level Mask Register (ILM) and Priority of Interrupt Level
ILM2
ILM1
ILM0
Interrupt level
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
High or Low
High (interrupt disable)
Low
49
CHAPTER 2 CPU
2.7.7
Program Counter (PC)
The program counter (PC) is a 16-bit counter indicating the lower 16 bits at the
instruction address to be executed next by the CPU.
■ Program Counter (PC)
The higher 8 bits of the instruction address to be executed next by the CPU are set in the Program counter
bank register (PCB) and the lower 16 bits are set in the program counter (PC). The instruction address to be
executed next is as shown in Figure 2.7-13 . The contents of the program counter (PC) are also updated by
a conditional branch instruction, subroutine call instruction, interrupt, or reset. In addition, it is also used as
a base pointer for reading out the operand.
For the details of bank registers, see "2.7.9 Bank Register (PCB, DTB, USB, SSB, and ADB)".
Figure 2.7-13 Program Counter (PC)
Upper 8-bit
PCB FEH
Lower 16-bit
PC ABCDH
FEABCD H Instruction executed next
Note:
The program counter (PC) and Program counter bank register (PCB) cannot be rewritten directly by
program (instructions such as MOV PC, #0FFH).
50
CHAPTER 2 CPU
2.7.8
Direct Page Register (DPR)
The direct page register (DPR) is an 8-bit register specifying operand address bits 8 to
15 (addr8 to addr15) when executing an instruction in the abbreviated direct addressing
mode. The bit is initialized to "01H" at a reset.
■ Direct Page Register (DPR)
Figure 2.7-14 Generation of Physical Address in Direct Page Register (DPR)
DTB register
DPR register
AAAAAAAA
BBBBBBBB
Direct address in instruction
CCCCCCCC
MSB
LSB
24-bit
bit 24
bit 16 bit 15
bit 8 bit 7
bit 0
physical address
AAAAAAAA
BBBBBBBB
CCCCCCCC
MSB : Uppermost bit
LSB : Lowest bit
Figure 2.7-15 Setting of Direct Page Register (DPR) and Data Access Example
MOV S:56H, #5AH
Instruction executing result
Upper 8-bit Lower 8-bit
DTB register
12H
DPR register
34H
123458 H
123456 H
MSB : Uppermost bit
LSB : Lowest bit
5AH
123454 H
MSB
LSB
51
CHAPTER 2 CPU
2.7.9
Bank Register (PCB, DTB, USB, SSB, and ADB)
The bank register is a register for specifying the highest 8-bit address of the bank-type
addressing and consists of five registers listed below.
• Program counter bank register (PCB)
• Data bank register (DTB)
• User stack bank register (USB)
• System stack bank register (SSB)
• Additional data bank register (ADB)
These bank registers indicate the memory bank allocated in the program, data, user
stack, system stack, and additional spaces, respectively.
■ Bank Register (PCB, DTB, USB, SSB, and ADB)
● Program counter bank register (PCB)
The PCB is a bank register that specifies the program (PC) space. The PCB is rewritten when executing the
JMPP, CALLP, RETP, or RETI instruction branching to the entire 16M-byte space, when executing a
software interrupt instruction, when a hardware interrupt occurs, or an exception occurs.
● Data bank register (DTB)
It is a bank register which specifies data (DT) space.
● User Stack Bank Register (USB) and System Stack Bank Register (SSB)
They are the bank register that specifies the stack (SP) space. Which of the USB or SSB is defined by the S
flag value in the processor status (PS: CCR). For details, see "2.7.2 Stack Pointer (USP, SSP)".
● Additional data bank register (ADB)
The ADB is a bank register that specifies the additional (AD) space.
● Setting of Each Bank and Data Access
The bank registers are of 8-bit length; the Program counter bank register (PCB) is initialized to "FFH" by
reset and the data bank register (DTB), user stack bank register (USB), system stack bank register (SSB),
and additional data bank register (ADB) are initialized to "00H" by reset. The Program counter bank
register (PCB) is a read-only register. All bank register without Program counter bank register are readable
and writable.
52
CHAPTER 2 CPU
Note:
Note that for the MB90800 series, support is limited to the memory space incorporated in the device.
For details of register operations, see "2.4.2 Bank Addressing".
53
CHAPTER 2 CPU
2.8
General-purpose Register
The general-purpose registers are in the memory block allocated on the RAM at
"000180H" to "00037FH" with each register bank consisting of 16 bits x 8. They can be
used as general-purpose 8-bit registers (byte registers R0 to R7), 16-bit registers (word
registers RW0 to RW7), or 32-bit registers (long-word registers RL0 to RL3).
General-purpose registers allow accessing the RAM with short instructions. The
general-purpose registers blocked in the register banks facilitate register contents
protection and grouping of usage. When the general-purpose registers are used as
long-word registers, they can be also used as linear pointers for directly accessing the
entire space.
■ Configuration of General-purpose Register
On the RAM at "000180H" to "00037FH", there are 32 banks of general-purpose registers and one of the
banks is specified in the register bank pointer (RP). The bank start address set in the register bank pointer
(RP) is as shown in the expression below. 16 bits x 8 is defined as one register bank.
Start address of the general-purpose register=000180H + Register bank pointer (RP) × 10H
For details of the register bank pointer (RP), see "2.7.5 Register Bank Pointer (PS: RP)".
Figure 2.8-1 Allocation and Configuration of General-Purpose Register Banks in Memory Space
Built-in RAM
:
Byte
address
000380 H
Register bank 31
000370 H
Register bank 30
000360 H
:
:
:
0002E0 H
Register bank 21
0002D0 H
Register bank 20
0002C0 H
Register bank 19
0002B0 H
:
:
:
:
:
0001B0 H
Register bank 2
0001A0 H
Register bank 1
000190 H
Register bank 0
000180 H
:
54
RP
14H
Byte
address
02CEH
R6
R7
02CF H RW7
02CCH
R4
R5
02CDH RW6
02CAH
R2
R3
02CBH RW5
02C8 H
02C9 H RW4
02C6 H
R1
R0
RW3
02C4 H
RW2
02C5 H
02C2 H
RW1
02C3 H
02C0 H
RW0
02C1 H
LSB
16 bits
02C7 H
RL3
RL2
RL1
RL0
MSB
Conversion formula [000180H + RP
: Byte register
R0 to R7
RW0 to RW7 : Word register
RL0 to RL3 : Long word register
MSB
: Uppermost bit
LSB
: Lowest bit
10H]
CHAPTER 2 CPU
Note:
The register bank pointer (RP) is initialized to "00H" after a reset.
■ Register Bank
The register bank can be used as a general-purpose register (byte registers R0 to R7, word registers RW0 to
RW7, and long-word registers RL0 to RL3) to perform various operations or to serve as a pointer. The
long-word registers can also be used as liner pointers for directly accessing the entire memory space.
Similar to RAM, the contents of the registers in the register bank are not initialized by reset; the state
before reset remains. However, power becomes irregular when it is on.
Table 2.8-1 Typical Function of the General-purpose Register
Register name
Function
R0 to R7
Used as operands for various instructions
Note:
R0 can also be used as the barrel shift counter or the normalized instruction counter.
RW0 to RW7
Used as pointer
Used as operands for various instructions
Note:
RW0 is used as a counter of the string instruction.
RL0 to RL3
Used as the long pointer
Used as operands for various instructions
55
CHAPTER 2 CPU
2.9
Prefix Code
When a prefix code is set before an instruction, the instruction operation immediately
after the prefix code can be changed. There are the following three kinds of prefix
codes.
• Bank select prefix (PCB, DTB, ADB, and SPB)
• Common register bank prefix (CMR)
• Flag change inhibit prefix (NCC)
■ Prefix Code
● Bank select prefix (PCB, DTB, ADB, and SPB)
When the bank select prefix is set before an instruction, the memory space to be accessed by the instruction
can be changed regardless of the addressing type.
For details, see "2.9.1 Bank Select Prefix (PCB, DTB, ADB, and SPB)".
● Common register bank prefix (CMR)
When the common register bank prefix has been set before an instruction accessing the register bank, the
register access can be changed to the common bank (register bank set when RP = "00H", in "000180H" to
"00018FH") regardless of the value of the register bank pointer (RP).
For details, see "2.9.2 Common Register Bank Prefix (CMR)".
● Flag change inhibit prefix (NCC)
When the flag change inhibit prefix code has been set, prior to the instruction whose flag changes are to be
inhibited, flag changes after the instruction execution do not occur.
For details, see "2.9.3 Flag Change Inhibit Prefix (NCC)".
56
CHAPTER 2 CPU
2.9.1
Bank Select Prefix (PCB, DTB, ADB, and SPB)
The memory space for data accessing is defined for each addressing type; however,
when a bank select prefix is set before an instruction, the memory space to be
accessed can be set regardless of the addressing type.
■ Bank Select Prefix (PCB, DTB, ADB, SPB)
Table 2.9-1 Bank Select Prefix
Bank select prefix
Selected space
PCB
Program space
DTB
Data space
ADB
Additional space
SPB
The user stack space is used when the value of S flag in the condition code register (CCR) is "0",
and the system stack space is used when it is "1".
Note: When the bank select prefix is used, some instructions perform exceptional operation.
Table 2.9-2 Instructions Unaffected by Bank Select Prefix
Instruction types
Instruction
Effect of bank select prefix code
String instruction
MOVS
SCEQ
FILS
MOVSW
SCWEQ
FILSW
Regardless of the prefix presence, the bank register specified
by operand is used.
Stack operation
instruction
PUSHW
POPW
Regardless of the prefix presence, the user stack bank register
(USB) is used if the S flag is "0", and the system stack bank
register (SSB) is used if the S flag is "1".
I/O Access instruction
MOV
MOVW
MOV
MOV
MOVB
SETB
BBC
WBTC
Interrupt return instruction
A,io
A,io
io,A
io,#imm8
A,io:bp
io:bp
io:bp,rel
io,bp
MOVX A,io
MOVW
MOVW
MOVB
CLRB
BBS
WBTS
RETI
io,A
io,#imm16
io:bp,A
io:bp
io:bp,rel
io:bp
Regardless of the prefix presence, the I/O space ("000000H""0000FFH") is accessed.
Regardless of the prefix presence, the system stack bank (SSB)
is used.
Table 2.9-3 Instructions Requiring Precaution When Using Bank Select Prefix
Instruction types
Instruction
Description
Flag change instruction
AND CCR,#imm8
OR CCR,#imm8
The effect of the prefix reaches the following instruction.
ILM setting instruction
MOV ILM,#imm8
The effect of the prefix reaches the following instruction.
PS Return instruction
POPW PS
Do not add the bank select prefix to the PS return
instruction.
57
CHAPTER 2 CPU
2.9.2
Common Register Bank Prefix (CMR)
When the common register bank prefix has been set before an instruction accessing
the register bank, the register access can be changed to the common bank (register
bank set when RP =00H, in "000180H" to "00018FH") regardless of the value of the
register bank pointer (RP).
■ Common Register Bank Prefix (CMR)
To enable easily data exchange between tasks, F2MC-16LX provides a common bank that can be shared
between tasks. The common bank is in "000180H" to "00018FH" house number. However, please note on
using, if the command in Table 2.9-4 should be used.
Table 2.9-4 Instructions Requiring Precaution When Using Common Register Bank Prefix (CMR)
Instruction types
Instruction
String instruction
MOVS
SCEQ
FILS
Flag change instruction
AND CCR, #imm8
OR CCR, #imm8
The effect of the prefix reaches the following instruction.
PS Return instruction
POPW PS
The effect of the prefix reaches the following instruction.
ILM setting instruction
MOV ILM, #imm8
The effect of the prefix reaches the following instruction.
58
MOVSW
SCWEQ
FILSW
Description
Please do not add the CMR prefix to the string
instruction.
CHAPTER 2 CPU
2.9.3
Flag Change Inhibit Prefix (NCC)
When an NCC prefix has been set prior to the instruction whose flag changes are to be
inhibited, flag changes after instruction execution do not occur.
■ Flag Change Inhibit Prefix (NCC)
The flag change inhibit prefix (NCC) code is used to inhibit an unnecessary flag change. The flags whose
changes are inhibited are T, N, Z, V, and C. However, please note on using, if the command in Table 2.9-5
should be used.
For details of T, N, Z, V, and C flags, see "2.7.4 Condition Code Register (PS: CCR).
Table 2.9-5 Instructions Requiring Precaution When Using Flag Change Inhibit Prefix (NCC)
Instruction types
Instruction
MOVSW
SCWEQ
FILSW
Description
String instruction
MOVS
SCEQ
FILS
Flag change instruction
AND CCR, #imm8
OR CCR, #imm8
Regardless of the prefix presence, the condition code
register (CCR) changes in accordance with the
specification of instructions. The effect of the prefix
reaches the following instruction.
PS Return instruction
POPW PS
Regardless of the prefix presence, the condition code
register (CCR) changes in accordance with the
specification of instructions. The effect of the prefix
reaches the following instruction.
ILM setting instruction
MOV ILM, #imm8
The effect of the prefix reaches the following instruction.
Interrupt return instruction
INT #vct8
INT adder16
RETI
Regardless of the prefix presence, the condition code
register (CCR) changes in accordance with the
specification of instructions.
Context
Switch command
JCTX @A
INT9
INTP addr24
Please do not add the NCC prefix to the string
instruction.
Regardless of the prefix presence, the condition code
register (CCR) changes in accordance with the
specification of instructions.
59
CHAPTER 2 CPU
2.9.4
Restrictions on Prefix Code
Use of the prefix codes is subject to the restrictions listed below.
• During execution of a prefix code or interrupt/hold inhibit instruction, the interrupt/
hold request is not accepted.
• When a prefix code is placed before an interrupt/hold instruction, the prefix code
effect is delayed.
• When competing prefix codes are used successively, the last prefix code becomes
valid.
■ Interruption/Holding Control Instruction
Table 2.9-6 Interruption/holding control instruction
Prefix code
The instructions which do not accept
the interrupt and hold requests.
PCB
DTB
ADB
SPB
CMR
NCC
Interruption/holding control instruction
(The command that delays effects)
MOV
OR
AND
POPW
ILM, #imm8
CCR, #imm8
CCR, #imm8
PS
● Control of interruption/holding
During execution of a prefix code or interrupt/hold instruction, an interrupt request or hold request, if
issued, is not accepted as shown in Figure 2.9-1 . If the interrupt/hold request above is not accepted,
interrupt/hold processing is performed only after the first instruction other than prefix code or interrupt/
hold instruction has been executed succeeding the prefix code or interrupt/hold inhibit instruction.
Figure 2.9-1 Control of Interruption/Holding
Interrupt/hold determent instruction
(a)
(a) Normal instruction
Interrupt request generating
60
Interrupt reception
CHAPTER 2 CPU
● Delay of the effect of the prefix code
As shown in Figure 2.9-2 , when a prefix code is set before an interrupt/hold inhibit instruction, the prefix
code effect is valid for the first instruction succeeding the interrupt/hold inhibit instruction.
Figure 2.9-2 Interrupt/hold Inhibit Instruction and Prefix Code
Interrupt/hold determent instruction
MOV A,FFH
NCC
MOV ILM,#imm8
ADD A,01H
CCR : XXX10XXB
CCR : XXX10XXB
CCR is not changed by NCC.
■ Array of Prefix Codes
When competing prefix codes (PCB, ADB, DTB, or SPB) succeeds, the value set in the last PCB becomes
valid.
Figure 2.9-3 Array of Prefix Codes
Prefix code
ADB
DTB
PCB
ADD A,01H
Prefix code make PCB enable.
61
CHAPTER 2 CPU
62
CHAPTER 3
RESET
This chapter explains reset of the MB90800 series.
3.1 Overview of Reset
3.2 Reset Factors and Oscillation Stabilization Wait Times
3.3 External Reset Pin
3.4 Reset Operation
3.5 Reset Factor Bit
3.6 State of Each Pin at Reset
63
CHAPTER 3 RESET
3.1
Overview of Reset
When a reset cause has occurred, the CPU aborts the current processing and enters the
reset clear wait state. After the reset is cleared, processing starts from the address
indicated in the reset vector.
There are the following four kinds of factors of resets.
• generating power-on reset (at power-on)
• Watchdog timer overflow (on using watch-dog timer)
• When the external reset is input from (RST) pin
• When the internal reset signal generation bit (RST) of the low-power consumption
mode control register is set to "0" (software reset)
■ Reset Factor
Table 3.1-1 Reset Factor
Reset
Factor
Machine clock
Watchdog
timer
Oscillation
stabilization waiting
External pin
"L" level to RST terminal setting
input
Main clock (MCLK)
Stops
None
Software
When the internal reset signal
generation bit (RST) of the lowpower consumption mode control
register is set to "0".
Main clock (MCLK)
Stops
None
Watchdog timer
Watchdog timer overflow
Main clock (MCLK)
Stops
None
Power on
When turning on the power
supply
Main clock (MCLK)
Stops
Yes
MCLK: Main clock frequency (oscillation clock divided by 2)
● External reset
The external reset generates a reset when the external reset pin (RST pin) is set to "L" level. The "L" level
input time must be 16 machine cycles (16/φ) more. While operating with the machine clock, the oscillation
does not wait for stabilization even when a reset is generated by setting the external reset pin to "L" level.
Reference:
If the external reset pin is set to "L" level during execution of an instruction (MOV instruction, etc.
executing transfer instruction), the external reset input is enabled after completion of the current
instruction execution. Note that for string instructions (such as MOVS instruction), the external reset
input may be enabled before completion of the transfer with the set counter value.
When "L" level is set in the external reset pin, the port pin enters the reset state regardless of the
instruction execution cycle (Asynchronous when "L" level is set).
64
CHAPTER 3 RESET
● Software reset
The software reset generates a reset of 3 machine cycles (3/φ) when "0" is set in the internal reset signal
generation bit (RST) in the low-power consumption mode control register (LPMCR). Software reset does
not secure the oscillation stabilization wait time.
● Watchdog reset
After starting the watchdog timer, the watchdog reset generates a reset when "0" is not set in the watchdog
control bit (WTE) of the watchdog timer control register (WDTC) within the period of time set with the
interval time set bits (WT1 and WT0) of the watchdog timer control register (WDTC).
● Power on reset
Power-on reset is reset generated at a start of power-supply operating.
The oscillation stabilization wait time is fixed to 217/HCLK (approximately 20.97 ms for oscillation clock
6.25MHz). Reset operation starts after elapsing the oscillation stabilization wait time.
Clock definition
HCLK: Oscillation clock frequency (clock of supplied from oscillation pin)
MCLK: Main clock frequency (oscillation clock divided by 2)
φ : Machine clock frequency (CPU operation clock)
1/φ: machine cycle (CPU operating clock cycle)
For details of clock, see "4.1 Overview of Clock".
65
CHAPTER 3 RESET
3.2
Reset Factors and Oscillation Stabilization Wait Times
F2MC-16LX provides four types of reset causes and the oscillation stabilization wait
time for reset varies by the reset cause.
■ Reset Factors and Oscillation Stabilization Wait Times
Table 3.2-1 lists the reset factors and oscillation stabilization wait times and Table 3.2-2 lists the oscillation
stabilization wait time set in clock selection register (CKSCR).
Table 3.2-1 Reset Factors and Oscillation Stabilization Wait Times
Oscillation stabilization wait time
Numbers in parentheses mean the value at oscillation clock frequency =
6.25MHz.
Reset factor
Power on reset
217/HCLK (Approx. 20.97ms)
Watchdog timer
None (The WS1 and WS0 bits are initialized to "11B".
External reset from RST terminal
None (The WS1 and WS0 bits are initialized to "11B".
Software reset
None (The WS1 and WS0 bits are initialized to "11B".
HCLK: oscillation clock frequency (MHz)
Table 3.2-2 Oscillation Stabilization Wait Time Set in Clock Selection Register (CKSCR)
Oscillation stabilization wait time
Numbers in parentheses mean the value at oscillation clock frequency = 6.25 MHz.
WS1
WS0
0
0
210/HCLK (Approx. 164 μs)
0
1
213/HCLK (Approx. 1.31 ms)
1
0
215/HCLK (Approx. 5.24 ms)
1
1
217/HCLK (Approx. 20.97 ms)
HCLK: oscillation clock frequency (MHz)
Note:
The oscillation clock oscillator requires the oscillation stabilization wait time specific to the oscillator
until it is stabilized at its natural frequency after starting the oscillation. Set the oscillation stabilization
wait time for the oscillator to be used.
■ Oscillation Stabilization Waiting Reset State
Reset operation for power-ON reset or external reset during stop mode is performed after elapsing the
oscillation stabilization wait time generated by the timebase timer. The reset operation is performed after
the external reset is released.
66
CHAPTER 3 RESET
3.3
External Reset Pin
Internal reset is generated by setting an "L" level input at the external reset pin ((RST)
pin). The MB90800 series is reset in synchronization with the CPU operation clock; only
the external pin (I/O port) is reset asynchronously.
■ Block Diagram of External Reset Pin
● Block Diagram of Internal reset pin
Figure 3.3-1 Block Diagram of Internal Reset Pin
Rp
RST
P-ch
Pin
N-ch
CPU operating clock
(PLL multiplier circuit, 2-division of HCLK)
Synchronization
circuit
HCLK : Oscillation clock frequency
Internal reset signal
Input buffer
Note:
Initialization of the internal circuit requires clock. When reset has been input, clock must be supplied
from the oscillation pin.
● Block diagram of internal reset for external pin (I/O port)
Figure 3.3-2 Block Diagram of Internal Reset for External Pin
Rp
RST
P-ch
Pin
N-ch
Reset signal to external pin
HCLK : Oscillation clock frequency
Input buffer
67
CHAPTER 3 RESET
3.4
Reset Operation
When reset has been cleared, the mode data and reset vector set in internal or external
memory according to the mode pin settings are fetched. The CPU operation mode is set
by the mode data register and the address for starting execution after completion of the
reset sequence is set by the reset vector.
■ Overview of Reset Operation
Figure 3.4-1 Reset Operation Flow
Power-on reset stop mode
External reset
Software reset
Watchdog timer reset
During reset
Oscillation stabilization
waiting reset state
Mode data captured
(Setting of bus mode register)
Reset sequence
Reset vector captured
Program operation
Capturing instruction code from
address indicated by reset vector
and executing the instruction
■ Mode Pin
Set how to fetch the mode data and reset vector in mode pins (MD2 to MD0) in advance. When fetching
the mode data and reset vector, execute the reset sequence. For details, see "7.2 Mode Pins (MD2 to
MD0)".
■ Mode Fetch
When reset has been cleared, the CPU fetches the mode data to the mode data register. After fetching the
mode data, the reset vector is fetched in the program counter (PC) and program counter bank register
(PCB).
The bus mode and bus width can be set in the mode data register. In addition, the program start address can
be specified with the reset vector.
For details of mode data fetching, see "CHAPTER 7 SETTING MODE".
68
CHAPTER 3 RESET
Figure 3.4-2 Reset Vector and CPU Mode Data Transfers
2
F MC-16LX CPU core
Memory space
Mode register
FFFFDFH
Mode data
FFFFDEH
Reset vector bit23 to 16
FFFFDD H
Reset vector bit15 to 8
FFFFDCH
Reset vector bit7 to 0
Micro ROM
Reset sequence
PCB
PC
● Mode data register (address "FFFFDFH")
Settings in the mode data register can be modified during execution of the reset sequence. Settings in the
mode data register is activated after fetching the reset vector. The mode data register cannot be rewritten by
setting mode data to "FFFFDFH" using an instruction.
Please refer to "7.3 Mode Data" for details.
● Reset vector (address "FFFFDCH" to "FFFFDEH")
The program start address after reset is released is set. Execute the program from the address set with the
reset vector.
69
CHAPTER 3 RESET
3.5
Reset Factor Bit
To check reset factors, read the value of the watchdog timer control register (WDTC).
■ Reset Factor Bit
The reset cause can be confirmed with the reset cause flag bits (PONR, WRST, ERST, SRST) of the
watchdog timer control register (WDTC). When the reset generation cause need to be determined after
clearing the reset, read the reset cause flag bits (PONR, WRST, ERST, and SRST) of the watchdog timer
control register (WDTC).
The reset cause flag bits (PONR, WRST, ERST, and SRST) are cleared to "0" after reading the watchdog
timer control register (WDTC).
Figure 3.5-1 Block Diagram of Reset Factor Bits
RST pin
Without regular
clear
RST="L"
Power on
Power-on
generation
detection circuit
External reset
request detection
circuit
Watchdog timer
reset generation
detection circuit
Watchdog timer
control register
(WDTC)
RST bit set
LPMCR:RST
bit writing
detection circuit
Clear
S
R
S
F/F
Q
R
R
S
F/F
Q
PONR
S
F/F
Q
ERST
R
F/F
Q
WRST
Delay
circuit
SRST
Watchdog timer
control register
(WDTC) read
Internal data bus
S
R
Q
F/F
70
: Set
: Reset
: Output
: Flip-flop
CHAPTER 3 RESET
■ Correspondence of Reset Factor Bit and Reset Factor
Figure 3.5-2 Configuration of Reset Factor Bit (Watchdog timer control register)
Watchdog reset timer control register (WDTC)
Address
7
bit
0000A8 H
6
5
4
3
2
1
0
PONR
WRSTERST SRST WTE WT1 WT0
R/W
R/W R/W R/W R/W R/W R/W
Initial value
X-XXX111B
Reset factor flag bit
R/W : Readable/Writable
X:
:
Indefinite
Undefined
Table 3.5-1 Correspondence of Reset Factor Bit and Reset Factor
Reset factor
PONR
WRST
ERST
SRST
Power on reset
1
X
X
X
Watchdog timer reset
*
1
*
*
External Reset Pin (RST pin)
*
*
1
*
Software reset (LPMCR:RST)
*
*
*
1
*: The previous state is held.
X: Indefinite
■ Notes on Reset Factor Bit
● At two or more reset factors
When more than one reset cause exists, "1" is set in the related reset cause bits of the watchdog timer
control register (WDTC). For example, when external reset and watchdog timer reset have occurred
simultaneously, "1" is set in the reset cause flag bits (ERST and WRST) of the watchdog timer control
register (WDTC).
● At Power on reset
When power-ON reset has occurred, "1" is set in the reset cause flag bit (PONR) of the watchdog timer
control register (WDTC), but the values of the reset cause flag bits (WRST, ERST, and SRST) are
undefined.
If "1" is set in the reset cause flag bit (PONR), ignore the values of the reset cause flag bits (WRST, ERST,
and SRST).
● Clearing of reset factor bit
The reset cause flag bits (PONR, WRST, ERST, and SRST) are cleared to "0" after reading the watchdog
timer control register (WDTC). Even when reset has occurred, the reset cause flag bit is not cleared to "0"
unless the watchdog timer control register (WDTC) is read.
71
CHAPTER 3 RESET
Note:
If the power is turned on under conditions inhibiting the power-ON reset, the values of the WDTC
register are not assured.
72
CHAPTER 3 RESET
3.6
State of Each Pin at Reset
This section explains the state of each pin at reset.
■ Pin Status during Reset
The states of the terminals during a reset are determined by the mode terminal (MD0 to MD2 = 011B)
settings.
● When internal vector mode is set
All input/output pins are put in high-impedance state and the mode data is read out to the internal ROM.
■ State of Pins after Mode Data Read
The pin state after reading the mode data is determined by the mode data (M1, M0 = 00B).
● When single chip mode is set (M1, M0=00B)
All input/output pins are put in high-impedance state and the mode data is read out to the internal ROM.
Note:
Set the external pin level so that the external circuit does not operate.
73
CHAPTER 3 RESET
74
CHAPTER 4
CLOCK
This chapter explains the clock.
4.1 Overview of Clock
4.2 Block Diagram of Clock Generation Section
4.3 Clock Select Register (CKSCR)
4.4 Clock Mode
4.5 Oscillation Stabilization Wait Time
4.6 Connection of Oscillator and External Clock
75
CHAPTER 4 CLOCK
4.1
Overview of Clock
The clock generator controls operation of the internal clock which is the operation clock
for the CPU and peripheral functions. This internal clock is referred to as machine clock
and its one cycle as machine cycle. In addition, the clock generated by original
oscillation is referred to as oscillation clock and that by internal PLL oscillation as PLL
clock.
■ Overview of Clock
The clock generator contains an oscillation circuit, which generates oscillation clock when an external
oscillator is connected. Clock generated externally can be input and used as the oscillation clock. The
generator, also containing a PLL clock frequency multiplication circuit, can generate four frequency
multiplication clocks of the oscillation clock. The clock generator controls the oscillation stabilization wait
time, controls the PLL clock multiplication, and controls the internal clock operation by clock switching
with the clock selector.
● Oscillation clock (HCLK)
Clock generated by connecting an oscillator to the X0 and X1 pins or clock input from the external.
● Sub clock (SCLK)
Clock generated by connecting an oscillator to the X0A and X1A pins or externally input clock divided by 4.
The sub clock becomes the watch timer input clock and the low-speed machine clock in sub clock mode.
● Main clock (MCLK)
It is a en surroundings clock of the oscillation clock. It is an input clock to the timebase timer and clock
selector.
● PLL clock (PCLK)
Clock generated by multiplying the oscillation clock by the incorporated PLL clock multiplication circuit.
Four kinds of multiplication clocks can be selected.
● Machine clock (φ)
Operation clock for CPU and peripheral functions. One cycle of this clock is used as machine cycle (1/φ).
One can be selected from main clock (oscillation clock divided by 2) and four types of multiplication
clocks.
Note:
The maximum operating frequency for the CPU and peripheral functions is 25MHz. When
multiplication factor exceeding the maximum operating frequency is specified, the device does not
operate correctly.
For example, when oscillating with oscillation clock frequency 25MHz, multiplication by 1 or division
by 2 can be set.
76
CHAPTER 4 CLOCK
4.2
Block Diagram of Clock Generation Section
The clock generator consists of six blocks shown below.
• System Clock generation Circuit
• Sub clock generator circuit
• PLL multiplying circuit
• Clock selector
• Clock select register (CKSCR)
• Oscillation stabilization wait time selector
■ Block Diagram of Clock Generation Section
Figure 4.2-1 shows the block diagram of the clock generator.
Figure 4.2-1 contains the standby control and timebase timer circuits.
Figure 4.2-1 Block Diagram of Clock Generation Section
Low consumption power mode control register (LPMCR)
STP SLP SPL RST TMD CG1
RST
CG0
Reserved
Pin
CPU interval
operating selector
Interrupt
cancellation
Pin high
impedance
control
Internal reset
generation circuit
Internal reset
Interval cycle selection
CPU clock
CPU clock
control circuit
Stop, sleep signal
Stand-by
control circuit
2
Pin high impedance
control circuit
Stop signal
Machine clock
Oscillation stabilization
waiting cancellation
Peripheral clock
control circuit
Oscillation
stabilization
waiting time
selector
2
SCLK
4-division
Sub clock
generation
circuit
2
PLL multiplier circuit
X0A Pin
System clock
generation
circuit
X1A Pin
X0 Pin
Peripheral
clock
SCM MCM WS1 WS0 SCS MCS CS1 CS0
Clock selection register (CKSCR)
2-division
HCLK
1024-division
2-division
4-division
4-division
4-division
2-division
MCLK
Timebase timer
X1 Pin
HCLK : Oscillation clock
MCLK : Main clock
SCLK : Sub clock
to Watchdog timer
77
CHAPTER 4 CLOCK
● System clock generation circuit
The oscillation clock (HCLK) is generated by the oscillator connected externally. It is also possible to input
an external clock.
● Sub clock generator circuit
The sub clock (SCLK) is generated by the oscillator connected externally. It is also possible to input an
external clock.
● PLL multiplying circuit
The oscillation clock is multiplied by PLL oscillation and supplied to the CPU clock selector.
● Clock selector
Select the clock to be supplied out of the main clock and four types of PLL clocks for the CPU and
peripheral function clock control circuits.
● Clock select register (CKSCR)
Switches between the oscillation and PLL clocks, selects the oscillation stabilization wait time, and selects
the PLL clock multiplication factor.
● Oscillation stabilization wait time selector
Circuit for selecting the oscillation stabilization wait time for the oscillation clock when clearing stop mode,
transiting from sub clock to main clock mode, or transiting from sub clock to PLL clock mode. 4-type
timebase timer output can be selected.
78
CHAPTER 4 CLOCK
4.3
Clock Select Register (CKSCR)
The clock selection register (CKSCR) is a register that switches between the main and
PLL clocks, selects the oscillation stabilization wait time, and selects the PLL clock
multiplication factor.
■ Clock Select Register (CKSCR) Configuration
Figure 4.3-1 shows the clock select register (CKSCR) configuration and Table 4.3-1 lists the function
description of bits in clock selection register (CKSCR).
Figure 4.3-1 Clock Select Register (CKSCR) Configuration
Address
0000A1H
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7
(LPMCR)
SCM MCM WS1 WS0 SCS MCS CS1 CS0
R/W R/W
R/W R/W
bit0
Initial value
11111100B
R/W R/W R/W R/W
CS1 CS0
Multiplication rate setting bits
Parenthesized values are examples calculated
at an oscillation clock frequency of 6.25 MHz.
1 x HCLK (6.25MHz)
2 x HCLK (12.5MHz)
3 x HCLK (18.75MHz)
4 x HCLK (25MHz)
MCS
Machine clock setting bit
0 PLL clock setting
1 Main clock setting
Machine clock selection bit (sub)
SCS
0
Sub clock selection*2
1
Main clock selection
0
0
1
1
0
1
0
1
WS1 WS0
0
0
1
1
0
1
0
1
Oscillationstabilization waiting time setting bits
Parenthesized values are examples calculated
at an oscillation clock frequency of 6.25 MHz.
210/HCLK(163.84μs)
213/HCLK(1.31ms)
215/HCLK(5.24ms)
217/HCLK(20.97ms)*1
MCM
Machine clock display bit
Operating in PLL clock
0
1
Operating in main clock
SCM
Machine clock display bit
0
Operating in sub clock*2
1
Operating in main clock
HCLK : Oscillation clock frequency
: Readable/Writable
R/W
: Initial value
*1: This bit becomes 218/HCLK (approx. 41.94ms) at power on reset.
The sub clock cannot use in one system clock.
*2: When "0" is set to the SCS bit, the reset is generated.
79
CHAPTER 4 CLOCK
Note:
The machine clock selection bit is initialized to main clock selection by reset.
Table 4.3-1 Function Description of Bits in Clock Selection Register (CKSCR)
Bit name
Functions
bit15
SCM:
Machine clock
display bit
• This bit indicates whether the main clock or sub clock has been selected as the machine
clock.
• When this bit is "0", it indicates that the sub clock has been selected; when "1", it
indicates the main clock has been selected.
• When SCS is "1" and SCM is "0", it indicates that the main clock oscillation is waiting
for stabilization.
• Writing to this bit has no effect on operation.
bit14
MCM:
Machine clock
display bit
• This bit indicates whether the main clock or PLL-clock has been selected as the machine
clock.
• When this bit is "0", it indicates that the PLL clock has been selected; when "1", it
indicates the main clock has been selected.
• When MCS is "0" and MCM is "1", it indicates that the PLL clock oscillation is waiting
for stabilization.
• Writing to this bit has no effect on operation.
bit13,
bit12
WS1, WS0:
Oscillation
stabilization
waiting time
setting bits
• Selects the oscillation stabilization wait time of the oscillation clock when clearing stop
mode, transiting from sub clock to main clock mode, or transiting from sub clock to PLL
clock mode.
• Initialized to "11B" by every reset cause.
Note:
An appropriate value meeting the characteristic of the oscillator to be used must be set
for the oscillation stabilization wait time. Please refer to"4.2 Block Diagram of Clock
Generation Section". Please set setting"00B" only at the main clock mode. The
oscillation stabilization wait time for PLL clock is fixed to 214/HCLK.
bit11
SCS:
Machine clock
selection bit
• Bit for specifying main or sub clock as the machine clock.
• When this bit is "0", writing "1" causes the main clock oscillation stabilization wait time
to occur, automatically clearing the timebase timer.
• When sub clock is selected, the operation clock is the sub-oscillation clock divided by 4
is used (the machine clock is 8kHz for sub-oscillation clock 32kHz).
• When SCS and MCS are both 0, SCS is preferred, and the sub clock is selected. Initialized
to "1" by every reset cause.
80
CHAPTER 4 CLOCK
Table 4.3-1 Function Description of Bits in Clock Selection Register (CKSCR)
Bit name
Functions
bit10
MCS:
Machine clock
setting bit
• Bit for selecting main or PLL clock as the machine clock.
• When this bit is "0", PLL clock is selected; when this bit is "1", main clock is selected.
• When this bit is "1", writing "0" causes the PLL clock oscillation stabilization wait time
to occur, automatically clearing the timebase timer and also the TBOF bit of the timebase
timer control register (TBTC).
• The PLL clock oscillation stabilization wait time is fixed to 214/HCLK (the oscillation
stabilization wait time is approximately 4.1ms for oscillation clock frequency 4MHz).
• When main clock is selected, the operation clock is the oscillation clock divided by 2 (the
operation clock is 2MHz for oscillation clock frequency 4MHz).
• Initialized to "1" by every reset cause.
Note:
When writing "0" in the MCS bit that is "1", the timebase timer interrupt must be masked
in advance by the TBIE bit of the timebase timer control register (TBTC) or by the
interrupt level mask register (ILM).
bit9,
bit8
CS1, CS0:
Multiplication rate
setting bits
• Bit for selecting the multiply factor for PLL clock.
• The multiplication factor can be selected from among four options.
• Initialized to "00B" by every reset cause.
Note:
When the MCS bit or the MCM bit is"0", writing is controlled. Rewrite the CS1 and CS0
bits after temporarily setting the MCS bit to "1" (main clock mode).
HCLK: Oscillation clock frequency
81
CHAPTER 4 CLOCK
4.4
Clock Mode
There are three clock modes: main clock, PLL clock, and sub clock modes.
■ Main Clock Mode, PLL Clock Mode, Sub Clock Mode
● Main clock mode
The main clock mode uses the oscillation clock divided by 2 as the operation clock for the CPU and
peripheral functions and stops the PLL clock.
● PLL clock mode
The PLL clock mode uses the PLL clock as operation clock for the CPU and peripheral functions. The PLL
clock multiplication factor can be selected by the clock selection register (CKSCR: CS1, CS0).
● Sub clock mode
The sub clock mode uses the sub-oscillation clock divided by 4 as the operation clock for the CPU and
peripheral functions and stops the main clock and the PLL clock.
■ Transition of Clock Mode
By writing to the MCS and SCS bits of the clock selection register (CKSCR), the clock mode transits to
main clock, PLL clock, or sub clock mode.
● Transition from main clock mode to PLL clock mode
When the MCS bit of the clock selection register (CKSCR) is rewritten from "1" to "0" in main clock
mode, main clock is switched to PLL clock after the PLL clock oscillation stabilization wait time.
● Transition from PLL clock mode to main clock mode
When the MCS bit of the clock selection register (CKSCR) is rewritten from "0" to "1" in PLL clock mode, PLL
clock is switched to main clock at the timing (after 1 to 8 PLL clocks) the PLL and main clock edges match.
● Transition from main clock mode to sub clock mode
When the SCS bit of the clock selection register (CKSCR) is rewritten from "1" to "0" in main clock mode,
main clock is switched to sub clock.
● Transition from sub clock mode to main clock mode
When the SCS bit of the clock selection register (CKSCR) is rewritten from "0" to "1" in sub clock mode,
sub clock is switched to main clock after the main clock oscillation stabilization wait time. The oscillation
stabilization wait time is selected with the WS1 and WS0 bits of the clock selection register (CKSCR).
● Transition from PLL clock mode to sub clock mode
When the SCS bit of the clock selection register (CKSCR) is rewritten from "1" to "0" in PLL clock mode,
PLL clock is switched to sub clock.
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CHAPTER 4 CLOCK
● Transition from sub clock mode to PLL clock mode
When the SCS bit of the clock selection register (CKSCR) is rewritten from "0" to "1" in sub clock mode,
sub clock is switched to PLL clock after the main clock oscillation stabilization wait time. The oscillation
stabilization wait time is selected with the WS1 and WS0 bits of the clock selection register (CKSCR).
Note:
Even when the MCS and SCS bits of the clock selection register (CKSCR) are rewritten, machine
clock is not switched immediately. Prior to operating the peripheral functions that depend on the
machine clock, refer to the MCM and SCM bits of the clock selection register (CKSCR) and check
that the machine clock has been switched.
If both the SCS and MCS bits are "0", the higher priority is given to SCS and the sub clock mode is
entered.
■ Selection of PLL Clock Multiplication Rate
One of four types of PLL clock multiplication factors (1 to 4) can be selected by writing "00B" to "11B" in
the CS1 and CS0 bits of the clock selection register (CKSCR).
■ Machine Clock
The PLL clock output from the PLL multiplication circuit, original oscillation clock divided by 2, and suboscillation clock divided by 4 are used as machine clocks. These machine are clocks supplied to the CPU or
resources. One of main clock, PLL clock, and sub clock can be selected by writing to the MCS or SCS bit
of the clock selection register (CKSCR).
Figure 4.4-1 shows the state transition diagram of machine clock selection.
83
CHAPTER 4 CLOCK
Figure 4.4-1 State Transition Diagram of Machine Clock Selection
(8)
Main
MCS =1
MCM=1
SCS =1
SCM =1
(10)
(1)
CS1,CS0=XXB
Main Sub
MCS =1
MCM =1
SCS =0
SCM =1
(9)
CS1,CS0=XXB
(11) Sub Main
(8)
MCS =1
MCM =1
SCS =1
(8)
(6)
SCM =0
Main PLLx (2)
CS1,CS0=XXB
(12) Sub PLL
MCS =0
(3)
(13) MCS =0
MCM=1
(4)
(14) MCM=1
SCS =1
(15) SCS =1
(5)
SCM =1
SCM =0
CS1,CS0=XXB
84
(16)
(10)
Sub
MCS =1
MCM=1
SCS =0
SCM =0
CS1,CS0=XXB
CS1,CS0=XXB
PLL1 Main
(7) MCS =1
MCM=0
SCS =1
SCM =1
CS1,CS0=00B
PLL1 multiplier
MCS =0
MCM=0
(6) SCS =1
(8)
SCM =1
CS1,CS0=00B
PLL1 Sub
MCS =1
(17)
MCM=0
SCS =0
SCM =1
CS1,CS=00B
PLL2 Main
MCS =1
(7) MCM=0
SCS =1
SCM =1
CS1,CS0=01B
PLL2 multiplier
MCS =0
MCM=0
(6) SCS =1
(8)
SCM =1
CS1,CS0=01B
PLL2 Sub
MCS =1
MCM=0
(17)
SCS =0
SCM =1
CS1,CS0=01B
PLL3 Main
(7) MCS =1
MCM=0
SCS =1
SCM =1
CS1,CS0=10B
PLL3 multiplier
MCS =0
MCM=0
(8)
(6) SCS =1
SCM =1
CS1,CS0=10B
PLL3 Sub
MCS =1
(17)
MCM=0
SCS =0
SCM =1
CS1,CS0=10B
PLL4 Main
(7) MCS =1
MCM=0
SCS =1
SCM =1
CS1,CS0=11B
PLL4 multiplier
MCS =0
MCM=0
(6) SCS =1
(8)
SCM =1
CS1,CS0=11B
PLL4 Sub
MCS =1
(17)
MCM=0
SCS =0
SCM =1
CS1,CS0=11B
CHAPTER 4 CLOCK
(1)
MCS bit "0" write
(2)
PLL clock oscillation stabilization waiting time end &CS1,CS0=00B
(3)
PLL clock oscillation stabilization waiting time end &CS1,CS0=01B
(4)
PLL clock oscillation stabilization waiting time end &CS1,CS0=10B
(5)
PLL clock oscillation stabilization waiting time end &CS1,CS0=11B
(6)
MCS bit "1" write (Including Hardware standby, Watchdog reset)
(7)
Synchronous timing of PLL clock and main clock
(8)
SCS bit "0" write
(9)
Sub clock oscillation stabilization waiting time end
(10)
SCS bit "1" write
(11)
Main clock oscillation stabilization waiting time end
(12)
Main clock oscillation stabilization waiting time end &CS1,CS0=00B
(13)
Main clock oscillation stabilization waiting time end &CS1,CS0=01B
(14)
Main clock oscillation stabilization waiting time end &CS1,CS0=10B
(15)
Main clock oscillation stabilization waiting time end &CS1,CS0=11B
(16)
SCS bit "1" write, MCS bit "0" write
(17)
Synchronous timing of PLL clock and sub clock
MCS:
Machine clock selection bit of clock selection register (CKSCR)
MCM:
Machine clock display bit of clock selection register (CKSCR)
SCS:
Machine clock selection bit (sub) of clock selection register (CKSCR)
SCM:
Machine clock display bit (sub) of clock selection register (CKSCR)
CS1,CS0:
Multiplier setting bit of clock selection register (CKSCR)
Note:
The initial value of the machine clock is the main clock (MCS=1 and SCS=1).
When SCS and MCS are both "0", SCS is prioritized, and the sub clock is selected.
For switching from the sub clock mode to PLL clock mode, set the oscillation stabilization wait time
selection bit (WS1 and WS0) of CKSCR register to "01B", "10B", or "11B".
85
CHAPTER 4 CLOCK
4.5
Oscillation Stabilization Wait Time
When setting power ON, clearing stop mode, or switching from sub clock to main or
PLL clock, the oscillation needs to wait for stabilization after starting the oscillation, as
oscillation by the oscillation clock is being suspended. Also when switching from main
to PLL clock, the oscillation must wait for stabilization after starting PLL oscillation.
■ Oscillation Stabilization Wait Time
Generally, ceramic or crystal oscillator requires time of several to tens of milliseconds until the oscillation
is stabilized at the natural frequency (oscillation frequency) after starting the oscillation. Accordingly, CPU
operation is disabled immediately after the oscillation restarts and the clock supply to the CPU is not reenabled until the oscillation stabilization delay time has elapsed. This gives the oscillation time to stabilize.
It is necessary to select a oscillation stabilization wait time appropriate to an oscillator to be used. The
oscillation stabilization wait time can be selected by setting in the clock selection register (CKSCR).
When switching from main to PLL clock, the CPU operates with the main clock during the PLL oscillation
stabilization wait time, and then the clock switches to PLL.
Figure 4.5-1 shows the operation immediately after starting the oscillation.
Figure 4.5-1 Operation Immediately after the Start of Oscillation
Oscillation time
of resonator
Oscillation
stabilization time
X1
Oscillation time
86
Oscillation stabilization
Starting normal operation
or switching to PLL clock
CHAPTER 4 CLOCK
4.6
Connection of Oscillator and External Clock
Each MB90800 series device, containing a system clock generator circuit, generates the
clock with the oscillator connected externally. It is also possible to input an externally
generated clock.
■ Connection of Oscillator and External Clock
● Example of connection of crystal oscillator or ceramic oscillator
Connect the crystal or ceramic oscillator as shown in Figure 4.6-1 .
Figure 4.6-1 Example of Connection of Crystal Oscillator or Ceramic Oscillator
X0 (X0A)
MB90800 series
X1 (X1A)
● Example of connection of external clock
As in the example shown in Figure 4.6-2 , connect the external clock to the X0 (X0A) pin and open the X1
(X1A) pin.
Figure 4.6-2 Example of Connection of External Clock
X0 (X0A)
MB90800 series
Open
X1 (X1A)
87
CHAPTER 4 CLOCK
88
CHAPTER 5
LOW-POWER
CONSUMPTION MODE
This chapter explains the low-power consumption mode.
5.1 Low-power Consumption Mode
5.2 Block Diagram of Low-power Consumption Control Circuit
5.3 Low-power Consumption Mode Control Register (LPMCR)
5.4 CPU Intermittent Operation Mode
5.5 Standby Mode
5.6 State Transition Diagram
5.7 The Pin States in Standby Mode or Reset State
5.8 Precautions when Using Low-power Consumption Mode
89
CHAPTER 5 LOW-POWER CONSUMPTION MODE
5.1
Low-power Consumption Mode
There are CPU operating modes as shown below based on operating clock selection
and clock operation control.
• Clock mode (PLL clock, main clock, or sub clock mode)
• CPU intermittent operation modes (PLL clock, main clock, and sub clock modes)
• Standby mode (sleep, timebase timer, watch, or stop mode)
■ CPU Operation Modes and Current Consumption
Figure 5.1-1 shows the CPU operation modes and current consumption.
Figure 5.1-1 CPU Operation Modes and Current Consumption
Consumption current
Tens of mA
CPU
operating mode
4-multiplier
clock
PLL clock mode
3-multiplier
clock
2-multiplier
clock
1-multiplier
clock
PLL clock interval
operating mode
4-multiplier
clock
3-multiplier
clock
2-multiplier
clock
1-multiplier
clock
Main clock mode (1/2 clock mode)
Main clock interval operating mode
Sub clock mode
Sub clock interval operating mode
Standby mode
Several mA
Sleep mode
Timebase timer mode
Watch mode
Stop mode
Several μA
Low consumption power mode
Note: This figure shows image of each kind of mode, so some part differs from actual current consumption.
90
CHAPTER 5 LOW-POWER CONSUMPTION MODE
■ Clock Mode
● PLL clock mode
In PLL clock mode, the CPU and resources operate on a PLL multiplying clock of oscillation clock
(HCLK).
● Main clock mode
In main clock mode, the CPU and resources operate on a clock with 2-frequency division of oscillation
clock (HCLK). In the main clock mode, PLL multiplication circuit stops.
● Sub clock mode
Mode for operating the CPU and peripheral functions with the sub-oscillation clock. In sub clock mode, the
main clock and PLL multiplication circuit stop working.
Note:
For clock modes, see "5.4 CPU Intermittent Operation Mode".
■ CPU Intermittent Operation Mode
Mode for reducing the power consumption by intermittently operating the CPU while supplying high-speed
clock to the peripheral functions. The CPU intermittent operation mode is a mode for supplying
intermittent clock only to the CPU when it makes access to the registers, built-in memory, peripheral
functions, or external devices.
■ Standby Mode
Standby mode reduces the power consumption by the low-power consumption control circuit which stops
clock supply to the CPU (sleep mode), stops clock supply to the CPU and peripheral functions (timebase
timer mode), or stops the oscillation clock (stop mode).
● PLL sleep mode
PLL sleep mode is mode for stopping the CPU operation clock in PLL clock mode; PLL clock is used for
operation other than the CPU.
● Main sleep mode
Main sleep mode is mode for stopping the CPU operation clock in main clock mode; main clock is used for
operation other than the CPU.
● Sub-sleep mode
Sub-sleep mode is mode for stopping the CPU operation clock in sub clock mode; sub clock is used for
operation other than the CPU.
● Timebase timer mode
Timebase timer mode is mode for stopping operation other than the oscillation clock and timebase timer;
functions other than timebase timer and watch timer stop working.
91
CHAPTER 5 LOW-POWER CONSUMPTION MODE
● Watch mode
It is a mode by which only the watch timer is operated. Only the sub clock operates and the main clock and
PLL multiplication circuit stop working.
● Stop mode
Stop mode is mode for stopping original oscillation; all functions are stopped.
Note:
In stop mode, the oscillation clock stops; this mode allows holding the data with the lowest power
consumption.
92
CHAPTER 5 LOW-POWER CONSUMPTION MODE
5.2
Block Diagram of Low-power Consumption Control Circuit
The low-power consumption control circuit consists of seven blocks listed below.
• CPU intermittent operation selector
• Standby controller circuit
• CPU clock controller circuit
• Peripheral clock controller circuit
• Pin high-impedance controller circuit
• Internal reset generator circuit
• Low-power consumption mode control register (LPMCR)
■ Block Diagram of Low-power Consumption Control Circuit
Figure 5.2-1 shows the block diagram of the low-power consumption control circuit.
Figure 5.2-1 Block Diagram of Low-power Consumption Control Circuit
Low consumption power mode control register (LPMCR)
STP SLP SPL RST TMD CG1 CG0
RST
Reserved
Pin
Pin
high-impedance
control circuit
Pin high-impedance
control
Internal reset
generating
circuit
Internal reset
CPU interval
operating
selector
Interval cycle selection
CPU clock
control circuit
2
Stop, sleep signal
Standby control
circuit
Interrupt
release
CPU clock
Stop signal
Machine clock
Clock generating
block
Peripheral clock
control circuit
Peripheral clock
Release of oscillation stabilization
Oscillation
stabilization
waiting time
selector
Clock selector
2
2
PLL multiplier
circuit
SCM MCM WS1 WS0 SCS MCS CS1 CS0
Clock selection register (CKSCR)
Divided
by 2
X0 Pin
Main clock
X1 Pin
System clock
generating circuit
Divided
by 4
Divided
by 4
Divided
by 8
Timebase timer
Divided
by 4
X0A Pin
X1A Pin
Divided
by 2048
Sub clock
generating circuit
93
CHAPTER 5 LOW-POWER CONSUMPTION MODE
● CPU intermittent operation selector
Selects the number of suspension clocks in CPU intermittent operation mode.
● Standby controller circuit
Controls the CPU clock control circuit and peripheral clock control circuit for changing to low-power
consumption mode or clearing it.
● CPU clock controller circuit
Circuit for controlling the clock supplied to the CPU, peripheral clock control circuit, and peripheral
functions.
● Peripheral clock controller circuit
Circuit for controlling clock supplied to peripheral functions.
● Pin high-impedance controller circuit
Circuit for putting the external pin in high-impedance state in timebase timer mode or stop mode. For a pin
for which a pull-up option has been selected, isolates the pull-up resistor in stop mode.
● Internal reset generator circuit
This circuit generates internal reset signals.
● Low-power consumption mode control register (LPMCR)
Register for transiting to standby mode or clearing it, setting CPU intermittent operation function, etc.
94
CHAPTER 5 LOW-POWER CONSUMPTION MODE
5.3
Low-power Consumption Mode Control Register (LPMCR)
The low-power consumption control register (LPMCR) is a register for changing to lowpower consumption mode or clearing it, and setting the number of CPU clock
suspension cycles in CPU intermittent operation mode, etc.
■ Low-power Consumption Mode Control Register (LPMCR)
Figure 5.3-1 shows the configuration of low-power consumption mode control register (LPMCR) and
Table 5.3-1 lists the function description of bits of low-power consumption mode control register
(LPMCR).
Figure 5.3-1 Configuration of Low-power Consumption Mode Control Register (LPMCR)
Address Bit15 ........ Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0000A0H
(CKSCR)
STP SLP SPL RST TMD CG1 CG0
Reserved
Initial value
00011000B
R/W R/W R/W R/W R/W R/W R/W R/W
Reserved bit
Reserved
Be sure to set 1.
CG1 CG0 CPU operating clock stop cycle number setting bits
0
0
0 cycle (CPU clock=Peripheral clock)
0
1
8 cycles (CPU clock: Peripheral clock=1 : approx. 3 to 4)
1
0
16 cycles (CPU clock: Peripheral clock=1 : approx. 5 to 6)
1
1
32 cycles (CPU clock: Peripheral clock=1 : approx. 9 to 10)
TMD
Watch/timebase timer mode bit
0
Transfer to watch mode or timebase timer mode
1
No effect for operation
Internal reset signal generating bit
RST
0
Generates internal reset signal of 3-machine cycle
1
No effect for operation
Pin state setting bit
(at watch, timebase timer mode or stop mode)
SPL
0
Hold
1
High-impedance
SLP
No effect for operation
1
Transfer to sleep mode
STP
R/W
: Readable/Writable
: Initial value
Sleep mode bit
0
Stop mode bit
0
No effect for operation
1
Transfer to stop mode
95
CHAPTER 5 LOW-POWER CONSUMPTION MODE
Table 5.3-1 Function Description of Bits of Low-power Consumption Mode Control Register (LPMCR)
Bit name
Functions
bit7
STP:
Stop mode bit
• Transition to stop mode
• Transits to stop mode when "1" is written to this bit.
• Operation is not influenced when "0" is written to this bit.
• Cleared to "0" by reset or stop clear.
• When this bit is read, "0" is always read.
bit6
SLP:
Sleep mode bit
• Transition to Sleep Mode
• When the bit is set to "1": The CPU enters the sleep mode.
• Operation is not influenced when "0" is written to this bit.
• Cleared to "0" by reset, sleep clear, or stop clear. Transits to stop mode when "1" is
written to the STP and SLP bits at the same time.
• When this bit is read, "0" is always read.
bit5
SPL:
Pin state setting bit
(at watch, timebase
timer, or stop
mode)
• This bit is enabled only in watch timebase timer, or stop mode.
• When this bit is "0", the external pin level is held.
• When this bit is "1", the external pin is put in high-impedance state.
• The bit is initialized to "0" at a reset.
bit4
RST:
Internal reset signal
generating bit
• When "0" is written to this bit, an internal reset signal of three machine cycles is
generated.
• Operation is not influenced when "1" is written to this bit.
• When this bit is read, "1" is always read.
bit3
TMD:
Watch/timebase
timer mode bit
• This bit set transition to watch mode or timebase timer mode.
• Moves to timebase timer mode when "0" is written to this bit in main clock or PLL clock
mode.
• Moves to timer mode when "0" is written to this bit in sub clock mode.
• Initialized to "1" by reset or interrupt request generation.
• When this bit is read, "1" is always read.
bit2,
bit1
CG1, CG0:
CPU operating
clock stop cycle
number setting bits
• Bit used for setting the number of suspension cycles of the CPU clock for CPU
intermittent operation.
• Stops the CPU clock supply for the specified number of cycles each time the instruction is
executed once.
• Selectable from four types of clocks.
• The bit is initialized to "00B" at a reset.
bit0
Reserved:
Reserved bit
Please write "1" in this bit.
96
CHAPTER 5 LOW-POWER CONSUMPTION MODE
■ Low-power Consumption Mode Control Register
Writing to the low-power consumption mode control register causes transition to the low-power
consumption mode (stop, sleep, timebase timer, or watch mode); for transition to the low-power
consumption mode, use instructions listed in Table 5.3-2 .
The low-power consumption mode transition instruction in Table 5.3-2 must always be followed by an array
of instructions highlighted by a line below.
MOV LPMCR, #H'XX
; the low-power consumption mode transition instruction in Table 5.3-2
NOP
NOP
JMP
$+3
MOV A,#H'10
; jump to next instruction
; any instruction
The devices does not guarantee its operation after returning from the low-power consumption mode if you
place an array of instructions other than the one enclosed in the dotted line. To access the low-power
consumption mode control register (LPMCR) with C language, refer to "■Notes on Accessing the Lowpower Consumption Mode Control Register (LPMCR) to Enter the Standby Mode" in the section "5.8
Precautions when Using Low-power Consumption Mode".
When writing a word data to the low-power consumption mode control register (LPMCR), write at an even
address. Writing at an odd address for transition to the low-power consumption mode may cause operation
errors.
When controlling functions other than those listed in Table 5.3-1 , any instruction may be used.
● Priority level of STP, SLP, and TMD bits
When stop mode request, sleep mode request, and timebase timer mode request are issued at the same time,
the requests are processed according to the priorities shown below.
Request stop mode > Request timebase timer mode > Request sleep mode
Table 5.3-2 List of Instructions Used for Transition to Low-power Consumption Mode
MOV
io, #imm8
MOV
io, A
MOV
@RLi+disp8, A
MOVW io, #imm16
MOVW io, A
MOVW @RLi+disp8, A
SETB io:bp
CLRB io:bp
MOV
MOV
dir, #imm8
dir, A
MOVW dir, #imm16
MOVW dir, A
SETB dir:bp
CLRB dir:bp
MOV
MOV
eam, #imm8
addr16, A
MOVW eam, #imm16
MOVW addr16, A
MOV
MOV
eam, Ri
eam, A
MOVW eam, RWi
MOVW eam, A
SETB addr16:bp
CLRB addr16:bp
97
CHAPTER 5 LOW-POWER CONSUMPTION MODE
5.4
CPU Intermittent Operation Mode
The CPU intermittent operation mode is a mode for reducing the power consumption by
intermittently operating the CPU while operating the external bus and peripheral
functions at high speed.
■ CPU Intermittent Operation Mode
The CPU intermittent operation mode is a mode for stopping the clock supplied to the CPU
predetermined period of time for each instruction execution to delay the internal bus cycle start
accessing the registers, built-in memory (ROM, RAM), I/O, peripheral functions, or external bus.
power consumption processing is activated by reducing the CPU execution speed while supplying
speed clock to the peripheral functions.
for a
when
Lowhigh-
With the low-power consumption mode control register (CG1, CG0 of LPMCR), select the number of
suspension cycles of the clock supplied to the CPU.
The external bus operation itself uses the same clock as the peripheral functions.
The instruction execution time in CPU intermittent operation mode can be calculated by adding to the
ordinary execution time the compensation value obtained by multiplying the instruction execution count for
accessing the registers, built-in memory, built-in peripheral function, and external bus by the number of
suspension cycles. Figure 5.4-1 shows the clock for CPU intermittent operation.
Figure 5.4-1 Clock for CPU Intermittent Operation
Peripheral clock
CPU clock
Temporary stop cycle
1-instruction
cycle
Internal bus activation
98
CHAPTER 5 LOW-POWER CONSUMPTION MODE
5.5
Standby Mode
Standby modes are: sleep mode (PLL sleep, main sleep, sub-sleep), timebase timer
mode, watch mode, and stop mode.
■ Operation State in Standby Mode
Table 5.5-1 lists the operation states in standby mode.
Table 5.5-1 Operation State in Standby Mode
Standby mode
Sleep
mode
Time
base
timer
mode
Watch
mode
Stop
mode
Transition
condition
Main
clock
Sub
clock
Machine
clock
CPU
Peripheral
Operation
Operation
Operation
Stops
Operation
PLL
Sleep mode
SCS= 1
MCS= 0
SLP= 1
Main
Sleep mode
SCS= 1
MCS= 0
SLP= 1
Sub
Sleep mode
SCS= 0
SLP= 1
Stops
Timebase timer
mode (SPL= 0)
SCS= 1
TMD= 0
Operation
Timebase timer
mode (SPL= 1)
SCS= 1
TMD= 0
Watch mode
(SPL= 0)
SCS= 0
TMD= 0
Watch mode
(SPL= 1)
SCS= 0
TMD= 0
Stop mode
STP= 1
Pin
Operation
Setting
disabled
Reset
interrupt
Hold
Stops
*1
Stops
Hi-Z
Stops
Hold
Stops*2
Hi-Z
Stops
Stops
Hold
(SPL= 0)
Stop mode
STP= 1
Hi-Z
(SPL= 1)
*1: Timebase timer and watch timer can be operating.
*2: The watch timer operates.
SPL: Pin state specification bit of low-power consumption mode control register (LPMCR: SPL)
SLP: Sleep bit of Low-power consumption mode control register (LPMCR)
STP: Watch stop bit of Low-power consumption mode control register (LPMCR)
TMD: Watch and timebase timer mode bits of Low-power consumption mode control register (LPMCR)
MCS: Machine clock selection bit of clock selection register (CKSCR)
SCS: Machine clock selection bit (sub-bit) of clock selection register (CKSCR)
Hi-Z: High impedance
99
CHAPTER 5 LOW-POWER CONSUMPTION MODE
5.5.1
Sleep Mode
Sleep mode is mode for stopping the CPU operation clock; operation other than CPU
continues. Specifying transition to sleep mode in the low-power consumption mode
control register (LPMCR) causes transition to PLL sleep mode when PLL clock mode
has been set, to main sleep mode when main clock mode has been set, and to subsleep mode when sub clock mode has been set.
■ Transition to Sleep Mode
When "1" is written to the SLP bit, "1" to the TMD bit, and "0" to the STP bit of the low-power
consumption mode control register (LPMCR), transition to sleep mode occurs. Sleep mode moves to PLL
sleep mode if MCS = 0, SCS = 1 in the clock selection register (CKSCR), moves to main sleep mode if
MCS = 1, SCS = 1, and moves to sub-sleep mode if SCS = 0.
Note:
If "1" is written to the SLP and STP bits at the same time, the STP bit has a priority and transition to
stop mode occurs. If "1" is written to the SLP bit and "0" to the TMD bit at the same time, the TMD bit
has a priority and transition to timebase timer mode or watch mode occurs.
● Data retention function
In sleep mode, the contents of the dedicated registers such as accumulators and the internal RAM are held
unchanged.
● Operation at generating interrupt request
When "1" is written to the SLP bit of the low-power consumption mode control register (LPMCR) after
generation of an interrupt request, transition to sleep mode does not occur. Therefore, the CPU executes the
next instruction when it is in a state accepting no interrupts and branches immediately to the interrupt
processing routine when it is in a state accepting interrupts.
● Pin state
In sleep mode, the preceding state is maintained.
■ Cancellation of Sleep Modes
The low-power consumption control circuit clears sleep mode by reset input or interrupt generation.
● Return by Reset
Initialized to main clock mode by reset.
100
CHAPTER 5 LOW-POWER CONSUMPTION MODE
● Return by interrupt
If there is an interrupt request higher than level 7 from the peripheral circuit and others in the sleep mode,
the sleep mode is canceled. After clearing sleep mode, the action is the same as for ordinary interrupt
processing. When an interrupt is acceptable by settings in the I flag of the condition code register (CCR),
the interrupt level mask register (ILM), and the interrupt control register (ICR), the CPU performs interrupt
processing. When an interrupt is not acceptable, processing from the instruction succeeding the one which
has specified sleep mode continues.
Figure 5.5-1 shows the release of a standby mode by an interrupt.
Figure 5.5-1 Release of a Standby Mode by an Interrupt
Interrupt enable flag setting
of peripheral function
INT generation
(IL 7)
YES
NO
YES
I=0
Not sleep released
Not sleep released
Execution of next instruction
Sleep released
NO
ILM
IL
YES
Execution of next instruction
NO
Execution of interrupt
Note:
When handling an interrupt, the CPU usually services the interrupt after executing the instruction that
follows the one specifying the sleep mode.
Figure 5.5-2 shows the clearing sleep mode (external reset).
Figure 5.5-2 Clearing Sleep Mode (External reset)
RST pin
Sleep mode
Main clock
Oscillation
PLL clock
Oscillation
CPU clock
PLL clock
CPU operation
During stop
Sleep mode released
Reset sequence
Processing
Reset released
101
CHAPTER 5 LOW-POWER CONSUMPTION MODE
5.5.2
Timebase Timer Mode
The timebase timer mode is a mode for stopping operation other than the original
oscillation, timebase timer; and watch timer; all functions other than timebase timer and
watch timer are stopped.
■ Transition to Timebase Timer Mode
When "0" is written to the TMD bit of the low-power consumption mode control register (LPMCR) in PLL
clock or main clock mode (CKSCR: SCS = 1), transition to timebase timer mode occurs.
● Data retention function
In timebase timer mode, the contents of dedicated registers such as accumulators and the internal RAM are
held unchanged.
● Operation at generating interrupt request
When "0" is written to the TMD bit of the low-power consumption mode control register (LPMCR) after
occurrence of an interrupt request, transition to timebase timer mode does not occur.
● Pin state
Whether to hold the preceding state of the external pin in timebase timer mode or put it in high-impedance
state can be controlled with the SPL bit of the low-power consumption mode control register (LPMCR).
■ Cancellation of Timebase Timer Modes
The low-power consumption control circuit clears timebase timer mode when reset is input or an interrupt
occurs.
● Return by Reset
Initialized to main clock mode by reset.
● Return by interrupt
When an interrupt request with interrupt level higher than 7 has been generated from a peripheral circuit,
etc. in timebase timer mode (interrupt control register ICR: IL2, IL1, IL0 are other than "111B"), the lowpower consumption control circuit clears timebase timer mode. After clearing timebase timer mode, the
action is the same as for ordinary interrupt processing. When an interrupt is acceptable according to the I
flag of the condition code register (CCR), the interrupt level mask register (ILM), and the interrupt control
register (ICR), interrupt processing is performed. When an interrupt is not acceptable, processing from the
instruction succeeding the one before entering timebase timer mode continues.
102
CHAPTER 5 LOW-POWER CONSUMPTION MODE
Note:
When handling an interrupt, the CPU usually services the interrupt after executing the instruction that
follows the one specifying the timebase timer mode. When transition to timebase timer mode and
acceptance of an external bus hold request have occurred at the same time, interrupt processing
may start before executing the next instruction.
Figure 5.5-3 shows the clearing timebase timer mode (external reset).
Figure 5.5-3 Clearing Timebase Timer Mode (External reset)
RST pin
Timebase timer
mode
Main clock
Oscillation
PLL clock
Oscillation stabilization wait
Main clock
CPU clock
CPU operation
During stop
Watch mode released
Reset sequence
Oscillation
PLL clock
Processing
Reset released
103
CHAPTER 5 LOW-POWER CONSUMPTION MODE
5.5.3
Watch Mode
The watch mode is a mode for stopping operation of other than sub clock and watch
timer; most of the chip functions are stopped.
■ Transition to Watch Mode
When "0" is written to the TMD bit of the low-power consumption mode control register (LPMCR) in sub
clock mode (CKSCR: SCS = 0), transition to watch mode occurs.
● Data retention function
In watch mode, contents of the dedicated registers such as accumulators and the internal RAM are held
unchanged.
● Operation at generating interrupt request
When "0" is written to the TMD bit of the low-power consumption mode control register (LPMCR) after
generation of an interrupt request, transition to watch mode does not occur.
● Pin state
Whether to hold the preceding state of the external pin in watch mode or put it in high-impedance state can
be controlled with the SPL bit of the low-power consumption mode control register (LPMCR).
■ Cancellation of Watch Mode
The low-power consumption control circuit clears watch mode when reset input or interrupt occurs.
● Return by Reset
When clearing watch mode by a reset cause, transition occurs to oscillation stabilization wait reset state
after clearing watch mode. The reset sequence is executed after the oscillation stabilization wait time.
● Return by interrupt
When an interrupt request with an interrupt level higher than 7 is generated from a peripheral circuit, etc. in
watch mode (interrupt control register ICR: IL2, IL1, IL0 are other than "111B"), the low-power
consumption control circuit clears watch mode and transition to sub clock mode occurs immediately. After
transiting to sub clock mode, the action is the same as for ordinary interrupt processing. When an interrupt
is acceptable by settings in the I flag of the condition code register (CCR), the interrupt level mask register
(ILM), and the interrupt control register (ICR), interrupt processing is carried out. When an interrupt is not
acceptable, processing from the instruction succeeding the one caused to enter watch mode continues.
104
CHAPTER 5 LOW-POWER CONSUMPTION MODE
Note:
When handling an interrupt, the CPU usually services the interrupt after executing the instruction that
follows the one specifying the watch mode.
Figure 5.5-4 shows the cancellation of watch mode (external reset).
Figure 5.5-4 Cancellation of Watch Mode (External reset)
RST pin
Watch clock
Oscillation stabilization wait
Main clock
PLL clock
During stop
Sub clock
Oscillation
Oscillation
Main clock
CPU clock
CPU operation
Watch mode released
During stop
Reset sequence
Processing
Reset released
105
CHAPTER 5 LOW-POWER CONSUMPTION MODE
5.5.4
Stop Mode
Stop mode is mode for stopping original oscillation; all functions are stopped. That
means, data can be held with the lowest power consumption.
■ Transition to Stop Mode
When "1" is written to the STP bit of the low-power consumption mode control register (LPMCR),
transition to stop mode occurs.
● Data retention function
In stop mode, the contents of the dedicated registers such as accumulators and the internal RAM are held
unchanged.
● Operation at generating interrupt request
When "1" is written to the STP bit of the low-power consumption mode control register (LPMCR) after
generation of an interrupt request, transition to stop mode does not occur.
● Pin state setting
Whether to hold the preceding state of the external pin in stop mode or put it in high-impedance state can
be controlled with the SPL bit of the low-power consumption mode control register (LPMCR).
■ Cancellation of Stop Modes
The low-power consumption control circuit clears stop mode when reset input or interrupt occurs. As
oscillation of the operation clock is stopped when returning from stop mode, the low-power consumption
circuit first transits to the oscillation stabilization wait state and then clears stop mode.
● Return by Reset
When clearing stop mode by a reset cause, transition occurs to oscillation stabilization wait reset state after
clearing stop mode. The reset sequence is executed after the oscillation stabilization wait time.
● Return by interrupt
When an interrupt request with an interrupt level higher than 7 is generated from a peripheral circuit, etc. in
stop mode (interrupt control register ICR: IL2, IL1, IL0 are other than "111B"), the low-power consumption
control circuit clears stop mode. After clearing stop mode and after the main clock oscillation stabilization
wait time specified in the WS1 and WS0 bits of the clock selection register (CKSCR), the action is the
same as for ordinary interrupt processing. When an interrupt is acceptable by settings in the I flag of the
condition code register (CCR), the interrupt level mask register (ILM), and the interrupt control register
(ICR), interrupt processing is carried out. When an interrupt is not acceptable, processing from the
instruction succeeding the one caused to enter stop mode continues.
106
CHAPTER 5 LOW-POWER CONSUMPTION MODE
Note:
When handling an interrupt, the CPU usually services the interrupt after executing the instruction that
follows the one specifying the stop mode. When transition to stop mode and acceptance of an
external bus hold request have occurred at the same time, interrupt processing may start before
executing the next instruction.
Figure 5.5-5 shows the cancellation of stop modes (external reset).
Figure 5.5-5 Cancellation of Stop Modes (External Reset)
RST pin
Stop mode
Oscillation clock
Main clock
PLL clock
Oscillation
Oscillation stabilization wait
During stop
CPU clock
CPU operation
Oscillation
Main clock
During stop
Reset sequence Execution of instruction
Reset released
Stop mode released
107
CHAPTER 5 LOW-POWER CONSUMPTION MODE
5.6
State Transition Diagram
Figure 5.6-1 shows the state transition diagram.
■ State Transition Diagram
Figure 5.6-1 State Transition Diagram
External reset,
Watchdog timer reset,
Software reset
Power on
Reset
Power-on reset
SCS = "1"
Oscillation
stabilization
wait end
SCS = 0
Main clock
mode
SLP = 1
Interrupt
Main sleep mode
Interrupt
TMD = 0
Main timebase timer
mode
STP= 1
PLL clock
mode
MCS = "1"
SLP = 1
Interrupt
PLL sleep mode
TMD = 0
Interrupt
PLL timebase timer
mode
Interrupt
Oscillation
stabilization
wait end
Main clock oscillation
stabilization wait
PLL stop mode
Interrupt
Sub clock
mode
SCS = "1"
SLP = 1
Interrupt
Sub sleep mode
TMD = 0
Interrupt
Watch mode
STP = 1
STP = 1
Main stop mode
108
SCS = "0"
MCS = "0"
Oscillation
stabilization
wait end
PLL clock oscillation
stabilization wait
Sub stop mode
Interrupt
Oscillation
stabilization
wait end
Sub clock oscillation
stabilization wait
CHAPTER 5 LOW-POWER CONSUMPTION MODE
■ Low-power Consumption Mode
Table 5.6-1 lists the operation states in low-power consumption mode.
Table 5.6-1 Operation states in Low-power Consumption Mode
Operating state
PLL
Main
clock
Sub
clock
PLL
clock
CPU
Operation
Operation
Operation
Operation
PLL sleep
Peripheral
Operation
Watch
Timebase
timer
Operation
Operation
Stops
PLL timebase timer
Clock
source
PLL
Clock
Stops
PLL stop
Stops
Stops
Stops
Stops
Stops
PLL oscillation
stabilization waiting
Operation
Operation
Operation
Operation
Operation
Main
Operation
Operation
Stops
Operation
Operation
Main sleep
Operation
Operation
Stops
Main timebase timer
Main
Clock
Stops
Main stop
Stops
Stops
Stops
Stops
Main oscillation
stabilization waiting
Operation
Operation
Operation
Operation
Sub
Stops
Operation
Operation
Stops
Sub
Clock
Operation
Main
Clock
Stops
Sub sleep
Operation
Operation
Stops
Watch mode
Stops
Sub-stop
Stops
Stops
Sub oscillation
stabilization waiting
Operation
Operation
Power on reset
Reset
Operation
Operation
Stops
Operation
Stops
Stops
Operation
109
CHAPTER 5 LOW-POWER CONSUMPTION MODE
5.7
The Pin States in Standby Mode or Reset State
The pin states in standby mode or reset state are indicated for each memory access
mode.
■ Pin State in Single-chip Mode
Table 5.7-1 lists the pin states at single chip mode.
Table 5.7-1 Pin status at single chip mode
In standby mode
Pin name
At a reset
In stop mode
At sleep
SPL = 0
P00 to P07
P10 to P17
P20 to P27
P30 to P37
P40 to P47
P50 to P57
P60 to P67
P70 to P76
P80 to P84
P90, P91 *5
P65 to P67
P70
P00 to P07
P10 to P17
P20 to P27
P30 to P37
P50 to P53
P83 to P84
Hold state preserved *2
Hold state preserved *2
SPL = 1
Input cut off *3 /
output Hi-Z
Input disabled *4 /
output Hi-Z
Input enable *1
(External interrupt)
LCD output state maintenance
(at LCDC operation)
*1: Input enabled means that the input function is enabled; it requires selecting the pull-up or pull-down option or external
input. Same as other ports when used as an output port.
*2: Holding the preceding state means holding the state of output immediately before transition to this mode as it is. Note
that input will be disabled when it is in input state. "Holding the state of output immediately before transition to this
mode as it is" means holding the output value of the incorporated peripheral function in operation, if any, or holding the
output value as a port, etc., if any.
*3: In the state of input block, the mask is done as for the input, and "L" level is transmitted internally. Output Hi-Z means
putting the pin in high-impedance state by inhibiting driving of the pin driving transistor.
*4: Input disabled means such state that the value input to the pin is not internally accepted because the operation of the
input gate close to the pin is in enabled state, but the internal circuit is not operating.
*5: P90, P91 exists only in one system clock products.
110
CHAPTER 5 LOW-POWER CONSUMPTION MODE
5.8
Precautions when Using Low-power Consumption Mode
When using low-power consumption mode, five precautions given below should be
considered.
• Transition to Standby Mode and Interrupt
• Cancellation of Standby Mode by Interrupt
• At clearing stop mode
• Oscillation Stabilization Wait Time
• Notes on Accessing the Low-power Consumption Mode Control Register (LPMCR) to
Enter the Standby Mode
■ Transition to Standby Mode and Interrupt
When an interrupt request has been generated to the CPU from a peripheral function, the low-power
consumption mode control register (LPMCR: STP = 1, SLP = 1) or (LPMCR: TMD = 0) is ignored and
transition to standby mode does not occur (transition to standby mode does not occur even after interrupt
processing). In this case, if the interrupt level is higher than 7, whether or not the interrupt request is
accepted by the CPU is not related to this operation. Even in interrupt processing by the CPU, transition to
standby mode is enabled if the interrupt request flag bit has been cleared and there is no other interrupt
requests.
■ Cancellation of Standby Mode by Interrupt
When an interrupt request with an interrupt level higher than 7 has been generated from a peripheral circuit,
etc. in sleep, timebase timer, or stop mode, standby mode is cleared. Whether or not the interrupt request is
accepted by the CPU is not related to this operation.
After clearing standby mode, control branches to the interrupt processing routine for normal interrupt
operation if the priority of the interrupt level setup bits (ICR: IL2, IL1, IL0) for interrupt requests is higher
than the interrupt mask register (ILM) and the interrupt enable flag of the condition code register is enabled
(CCR: I = 1).
When an interrupt is not acceptable, processing from the instruction succeeding the one which has specified
standby mode continues.
When performing interrupt processing, interrupt processing normally starts after executing the instruction
succeeding the one specifying standby mode. Depending on the conditions for transiting to standby mode,
interrupt processing may starts before executing the next instruction.
To prohibit a branch to the interrupt processing routine immediately after return, interrupts must be
prohibited before standby mode is set.
■ At Clearing Stop Mode
Before transiting to stop mode, it can be cleared by input according to the input cause setup for external
interrupts. As an input cause, H level, L level, rising edge, or falling edge may be selected.
111
CHAPTER 5 LOW-POWER CONSUMPTION MODE
■ Oscillation Stabilization Wait Time
● Oscillation Stabilization Wait Time
Because the oscillator for original oscillation is stopped in stop mode, the oscillation stabilization wait time
must be secured. The oscillation stabilization wait time is the time selected with the WS1 and WS0 bits of
the clock selection register (CKSCR). The WS1 and WS0 bits may be set to "00B" only in main clock
mode.
● Oscillation stabilization wait time of PLL clock
When transiting from a state the CPU is operating with main clock and PLL clock is stopped to a state
operating the CPU or peripheral functions with PLL clock, transition occurs to PLL clock oscillation
stabilization wait state and main clock is used for operation while waiting for oscillation stabilization.
The PLL clock oscillation stabilization wait time is fixed to 214/HCLK(HCLK: oscillation clock).
■ Notes on Accessing the Low-power Consumption Mode Control Register (LPMCR) to
Enter the Standby Mode
● To access the low-power consumption mode control register (LPMCR) with assembler language
•
To set the low-power consumption mode control register (LPMCR) to enter the standby mode, use the
instruction listed in Table 5.3-2 .
•
The low-power consumption mode transition instruction in Table 5.3-2 must always be followed by an array
of instructions highlighted by a line below.
MOV LPMCR,#H'XX
NOP
NOP
JMP $+3
MOV A,#H'10
; the low-power consumption mode transition instruction in Table 5.3-2
; jump to next instruction
; any instruction
The devices does not guarantee its operation after returning from the low-power consumption mode if you
place an array of instructions other than the one enclosed in the line.
● To access the low-power consumption mode (LPMCR) with C language
To enter the standby mode using the low-power consumption mode control register (LPMCR), use one of
the following methods (1) to (3) to access the register:
(1) Specify the standby mode transition instruction as a function and insert two _wait_nop() built-in
functions after that instruction. If any interrupt other than the interrupt to return from the standby mode
can occur within the function, optimize the function during compilation to suppress the LINK and
UNLINK instructions from occurring.
Example: Watch mode or timebase timer mode transition function
Void enter_watch(){
IO_LPMCR_byte = 0x10
/* Set LPMCR TMD bit to "0" */
_wait_nop();
_wait_nop();
}
112
CHAPTER 5 LOW-POWER CONSUMPTION MODE
(2) Define the standby mode transition instruction using _asm statements and insert two NOP and JMP
instructions after that instruction.
Example: Transition to sleep mode
_asm(" MOV I: _IO_LPMCR,#H'58"); /* Set LPMCR SLP bit to "1" */
_asm(" NOP");
_asm(" NOP");
_asm(" JMP $+3");
/* Jump to next instruction */
(3) Define the standby mode transition instruction between #pragma asm and #pragma endasm and insert
two NOP and JMP instructions after that instruction.
Example: Transition to stop mode
#pragma asm
MOV I: _IO_LPMCR,#H'98
NOP
NOP
JMP $+3
#pragma endasm
/* Set LPMCR STP bit to "1" */
/* Jump to next instruction */
113
CHAPTER 5 LOW-POWER CONSUMPTION MODE
114
CHAPTER 6
INTERRUPT
This chapter describes interrupts of the MB90800 series
and the functions and operations of Extended Intelligent
I/O Service (EI2OS).
6.1 Overview of Interrupt
6.2 Interrupt Cause and Interrupt Vector
6.3 Interrupt Control Register and Function in Surrounding
6.4 Hardware Interrupt
6.5 Software Interrupt
6.6 Interrupts by Extended Intelligent I/O Service (EI2OS)
6.7 Exception Processing Interrupt
6.8 Stack Operation of Interrupt Processing
6.9 Example of Interrupt Processing Program
115
CHAPTER 6 INTERRUPT
6.1
Overview of Interrupt
The MB90800 series provides the interrupt functions and exception processing listed
below.
• Hardware Interrupt
• Software interrupt
• Interrupts by extended intelligent I/O service (EI2OS)
• Exception processing
■ Type and Function of Interrupt
● Hardware Interrupt
For a peripheral function (resource) interrupt request, moves to the interrupt processing program. For
details, see "6.4 Hardware Interrupt".
● Software interrupt
When a software interrupt instruction (INT instruction) is executed in the program, transition to the
interrupt processing program occurs. For details, see "6.5 Software Interrupt".
● Interrupts by extended intelligent I/O service (EI2OS)
The extended intelligent I/O service (EI2OS) allows data transfer between registers incorporated in the
peripheral functions (resources) and incorporated memory by setting the interrupt control registers (ICR00
to ICR15) and extended intelligent I/O service descriptor (ISD).
Upon completion of the data transfer processing, transition to the interrupt processing program occurs. For
details, see "6.6 Interrupts by Extended Intelligent I/O Service (EI2OS)".
● Exception processing
When an undefined instruction code is executed, exception processing is performed.
When exception processing is performed, control branches to the exception processing routine after saving
the register values currently being processed in the system stack. For details, see "6.7 Exception Processing
Interrupt".
116
CHAPTER 6 INTERRUPT
■ Interrupt Action
Figure 6.1-1 Outline Flow of Interrupt Action
Start
Main program
YES
With valid
hardware interrupt
request
During instruction
of string system
instruction
Interrupt activation/
recovery process
NO
YES
Is EI2OS?
Capture the next
instruction and decode
EI2OS
NO
YES
Is INT instruction?
NO
EI2OS process
Software interrupt/
exception process
Evacuation of dedicated
register to system stack
Hardware interrupt
reception disabled (I=0)
Hardware
interrupt
YES
Is specified
number of times completed,
or is there any end request
from peripheral
function?
Evacuation of dedicated
register to system stack
NO
Renewal of CPU
interrupt process level (ILM)
YES
Is RETI instruction?
NO
Normal instruction
execution
NO
Interrupt recovery
process
Dedicated register
recovery from system
stack to the routine before
calling interrupt routine.
Read interrupt vector,
renewal PC and PCB
and then diverge to
interrupt routine.
Repeat of string
system* instruction has
completed.
YES
Pointer transmission
to next instruction
by PC renewal
*: Interrupt judgement is carried out every 1 step during execution of string system instruction.
117
CHAPTER 6 INTERRUPT
6.2
Interrupt Cause and Interrupt Vector
The MB90800 series provides functions for responding to 256 types of interrupt causes;
256 interrupt vector tables are allocated at the highest address.
For software interrupts, 256 types of interrupt instructions (INT0 to INT255) can be set.
Note that, INT8 and INT10 are shared with reset vector interrupts and exception
processing, respectively. In addition, INT11 to INT42 are shared with peripheral function
(resource) interrupts.
■ Interrupt Vector
The interrupt vector tables to be referred when performing interrupt processing are allocated at the highest
addresses ("FFFC00H" to "FFFFFEH") in memory area. The interrupt vectors share extended intelligent I/O
services, exception processing, hardware interrupts, and software interrupts. Table 6.2-1 shows the interrupt
vector list.
Table 6.2-1 Interrupt Vector List
Software
interrupt
instruction
Vector
address L
Vector
address M
Vector
address H
Mode data
Interrupt
No.
Hardware interrupt
INT0
FFFFFCH
FFFFFDH
FFFFFEH
Unused
#0
None
:
:
:
:
:
:
:
INT7
FFFFE0H
FFFFE1H
FFFFE2H
Unused
#7
None
INT8
FFFFDCH
FFFFDDH
FFFFDEH
FFFFDFH
#8
Reset vectors
INT9
FFFFD8H
FFFFD9H
FFFFDAH
Unused
#9
None
INT10
FFFFD4H
FFFFD5H
FFFFD6H
Unused
#10
<Exception processing>
INT11
FFFFD0H
FFFFD1H
FFFFD2H
Unused
#11
Hardware Interrupt #0
INT12
FFFFCCH
FFFFCDH
FFFFCEH
Unused
#12
Hardware Interrupt #1
INT13
FFFFC8H
FFFFC9H
FFFFCAH
Unused
#13
Hardware Interrupt #2
INT14
FFFFC4H
FFFFC5H
FFFFC6H
Unused
#14
Hardware Interrupt #3
:
:
:
:
:
:
:
INT254
FFFC04H
FFFC05H
FFFC06H
Unused
#254
None
INT255
FFFC00H
FFFC01H
FFFC02H
Unused
#255
None
Note:
Set interrupt vectors that are not defined in software design at exception processing addresses,
118
CHAPTER 6 INTERRUPT
■ Interrupt Factors, Interrupt Vectors, and Interrupt Control Registers
Table 6.2-2 Interrupt Factors, Interrupt Vectors, and Interrupt Control Registers
Interrupt cause
Interrupt control register
EI2OS
Corresponded
Interrupt vector
Number*
Interrupt control
registers
Address
ICR
Address
Reset
#08
08H
FFFFDCH
-
-
INT9 instruction
#09
09H
FFFFD8H
-
-
Exception processing
#10
0AH
FFFFD4H
-
-
DTP/External interrupt ch.0
#11
0BH
FFFFD0H
ICR00
0000B0H
DTP/External interrupt ch.1
#13
0DH
FFFFC8H
ICR01
0000B1H
Serial I/O ch.2
#15
0FH
FFFFC0H
ICR02
0000B2H
DTP/External interrupt ch.2/3
#16
10H
FFFFBCH
Serial I/O ch.3
#17
11H
FFFFB8H
ICR03
0000B3H
16-bit free-run timer
#18
12H
FFFFB4H
Watch timer
#19
13H
FFFFB0H
ICR04
0000B4H
16-bit reload timer ch.2
#21
15H
FFFFA8H
ICR05
0000B5H
16-bit reload timer ch.0
#23
17H
FFFFA0H
ICR06
0000B6H
16-bit reload timer ch.1
#24
18H
FFFF9CH
Input capture ch.0
#25
19H
FFFF98H
ICR07
0000B7H
Input capture ch.1
#26
1AH
FFFF94H
PPG timer ch.0 counter-borrow
#27
1BH
FFFF90H
ICR08
0000B8H
Output compare
#29
1DH
FFFF88H
ICR09
0000B9H
PPG timer ch.1 counter-borrow
#31
1FH
FFFF80H
ICR10
0000BAH
Timebase timer
#33
21H
FFFF78H
ICR11
0000BBH
UART0 reception end
#35
23H
FFFF70H
ICR12
0000BCH
UART0 transmission end
#36
24H
FFFF6CH
A/D converter conversion
complete
#37
25H
FFFF68H
ICR13
0000BDH
I2C interface
#38
26H
FFFF64H
UART1 reception end
#39
27H
FFFF60H
ICR14
0000BEH
UART1 transmission end
#40
28H
FFFF5CH
Flash memory status
#41
29H
FFFF58H
ICR15
0000BFH
Delay interrupt output module
#42
2AH
FFFF54H
Priority
High
Low
: Usable
: Not available
: Interrupt factor corresponds to EI2OS and has EI2OS stop function
: Can be used when interrupt causes that share ICR are not used.
* : When interrupts of the same level are output at the same time, the interrupt with the smallest interrupt vector number has the priority.
119
CHAPTER 6 INTERRUPT
Notes:
• When there are two interrupt causes in the same interrupt control register (ICR) and use of EI2OS
is enabled, EI2OS is started upon detection of one of the interrupt causes. As interrupts other than
the start cause are masked during EI2OS start, masking one of the interrupt requests is
recommended when using EI2OS.
• For a resource that has two interrupt causes in the same interrupt control register (ICR), the
interrupt flag is cleared by an EI2OS interrupt clear signal.
120
CHAPTER 6 INTERRUPT
6.3
Interrupt Control Register and Function in Surrounding
Interrupt control registers (ICR00 to ICR15) are used for all peripheral functions
(resources) that have interrupt functions. The registers control the interrupt and
extended intelligent I/O service (EI2OS).
■ Interrupt Control Register List
Table 6.3-1 Interrupt Control Register List
Address
Registers
Abbreviation
Corresponding resource
0000B0H
Interrupt control registers 00
ICR00
DTP/External interrupt ch.0
0000B1H
Interrupt control registers 01
ICR01
DTP/External interrupt ch.1
0000B2H
Interrupt control registers 02
ICR02
Serial I/O ch.2,
DTP/External interrupt ch.2/3
0000B3H
Interrupt control registers 03
ICR03
Serial I/O ch.3,
16-bit free-run timer
0000B4H
Interrupt control registers 04
ICR04
Watch timer
0000B5H
Interrupt control registers 05
ICR05
16-bit reload timer ch.2
0000B6H
Interrupt control registers 06
ICR06
16-bit reload timer ch.0/ch.1
0000B7H
Interrupt control registers 07
ICR07
Input capture ch.0/ch.1
0000B8H
Interrupt control registers 08
ICR08
PPG timer ch.0 counter-borrow
0000B9H
Interrupt control registers 09
ICR09
Output compare
0000BAH
Interrupt control registers 10
ICR10
PPG timer ch.1 counter-borrow
0000BBH
Interrupt control registers 11
ICR11
Timebase timer
0000BCH
Interrupt control registers 12
ICR12
UART0 reception end
UART0 transmission end
0000BDH
Interrupt control registers 13
ICR13
A/D converters
I2C bus interface
0000BEH
Interrupt control registers 14
ICR14
UART1 reception end
UART1 transmission end
0000BFH
Interrupt control registers 15
ICR15
Flash memory
Delay interrupt generation module
121
CHAPTER 6 INTERRUPT
In the interrupt control register (ICR), four types of settings are allowed.
• Interrupt levels for the peripheral functions (resources) can be set.
• Whether to set the peripheral function (resource) interrupt cause to interrupt processing or extended
intelligent I/O service can be set.
• Descriptor address of the extended intelligent I/O service (EI2OS) can be set.
• Process status of the extended intelligent I/O service (EI2OS) can be displayed.
The interrupt control register (ICR) has different functions for writing and reading.
Note:
When setting the interrupt control register (ICR), accessing with read modify write (RMW)
instructions such as the SETB and CLRB instructions is disabled.
122
CHAPTER 6 INTERRUPT
6.3.1
Interrupt Control Registers (ICR00 to ICR15)
The interrupt control register can set interrupt processing or extended intelligent I/O
service processing when an interrupt request is output. The interrupt control register
has different bit functions for writing and reading.
■ Interrupt Control Registers (ICR00 to ICR15)
Figure 6.3-1 (for writing) Interrupt Control Registers (ICR00 to ICR15)
At writing
ICR00
to
ICR15
0000B0H
to
0000BFH
Bit
7
6
5
3
2
1
0
ICS3 ICS2 ICS1 ICS0
ISE
IL2
IL1
IL0
R/W
R/W
R/W
R/W
R/W
R/W R/W
4
R/W
Initial value
IL2
IL1
IL0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
00000111
Interrupt level setting bit
Interrupt level 0 (strongest)
Interrupt level 7 (without interrupt)
EI2OS enable bit
ISE
0
Activating interrupt sequence at interrupt output
1
Activating EI2OS at interrupt output
ICS3 ICS2 ICS1 ICS0
R/W
: Readable/Writable
: Initial value
B
EI2OS channel setting bit
Channel
Descriptor address
0
0
0
0
0
000100H
0
0
0
1
1
000108H
0
0
1
0
2
000110H
0
0
1
1
3
000118H
0
1
0
0
4
000120H
0
1
0
1
5
000128H
0
1
1
0
6
000130H
0
1
1
1
7
000138H
1
0
0
0
8
000140H
1
0
0
1
9
000148H
1
0
1
0
10
000150H
1
0
1
1
11
000158H
1
1
0
0
12
000160H
1
1
0
1
13
000168H
1
1
1
0
14
000170H
1
1
1
1
15
000178H
123
CHAPTER 6 INTERRUPT
Figure 6.3-2 Interrupt Control Registers (ICR00 to ICR15) (for reading)
At reading
ICR00
to
ICR15
0000B0H
to
0000BFH
Bit
7
6
5
4
3
2
1
0
Initial value
S1
S0
ISE
IL2
IL1
IL0
00000111B
R/W
R/W
R/W
R/W
R/W
R/W
IL2
IL1
IL0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Interrupt level setting bit
Interrupt level 0 (strongest)
Interrupt level 7 (without interrupt)
EI2OS enable bit
ISE
R/W : Readable/Writable
: Undefined bit
: Initial value
124
0
Activating interrupt sequence at interrupt output
1
Activating EI2OS at interrupt output
S1
S0
EI2OS status
0
0
During operating EI2OS or when not activating
0
1
Stop state by count end
1
0
Reserved
1
1
Stop state by request of peripheral functions
CHAPTER 6 INTERRUPT
6.3.2
Interrupt Control Register Functions
Interrupt control registers (ICR00 to ICR15) allow the settings shown below.
• setting of interrupt level
• Extended intelligent I/O Service (EI2OS) enable setting
• Extended intelligent I/O Service (EI2OS) descriptor address setting
• Extended intelligent I/O Service (EI2OS) operation status display
■ Composition of Interrupt Control Register (ICR)
Figure 6.3-3 Composition of Interrupt Control Register (ICR)
At interrupt control register (ICR) writing
Bit 7
6
5
4
ICR00 to ICR15
ICS3 ICS2 ICS1 ICS0
Address:
0000B0H to 0000BFH
R/W R/W R/W R/W
At interrupt control register (ICR) reading
Bit 7
6
5
ICR00 to ICR15
S1
Address:
0000B0H to 0000BFH R/W
R/W
R/W
3
2
1
0
Initial value
ISE
IL2
IL1
IL0
00000111B
R/W
R/W
R/W
R/W
4
3
2
1
0
Initial value
S0
ISE
IL2
IL1
IL0
00000111B
R/W
R/W
R/W
R/W
R/W
R/W : Readable/Writable
Reference:
The EI2OS descriptor address setup bits (ICS3 to ICS0) are set when starting the extended
intelligent I/O service (EI2OS). Set "1" in the EI2OS enable bit (ISE) when starting EI2OS and "0" in
the EI2OS enable bit (ISE) when not starting EI2OS. When not starting EI2OS, settings of the EI2OS
descriptor address bits (ICS3 to ICS0) are not necessary.
■ Interrupt Control Register Functions
● Interrupt levels set bit (IL2 to IL0)
Allows setting the peripheral function (resource) interrupt level. Initialized to level 7 (no interrupts) by
reset (The interruption cannot be generated at level 7).
125
CHAPTER 6 INTERRUPT
Table 6.3-2 Correspondence between Interrupt Level Setup Bits and Interrupt Levels
IL2
IL1
IL0
Interrupt level
0
0
0
0(High)
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
6(Low)
1
1
1
7(No interrupt)
● Extended intelligent I/O Service (EI2OS) enable bit (ISE)
When an interrupt request is output after "1" is set in the EI2OS enable bit (ISE), EI2OS is started. In
addition, when "0" has been set in the EI2OS enable bit (ISE), the interrupt sequence is started. When
EI2OS processing has completed, the EI2OS enable bit (ISE) is cleared to "0". Unless the peripheral
functions (resources) have the EI2OS function, set the EI2OS enable bit (ISE) to "0" by software. EI2OS
permission bit (ISE) is cleared to "0" by reset.
● Extended intelligent I/O Service (EI2OS) channel setting bit (ICS3 to ICS0)
The EI2OS descriptor address setup bits (ICS3 to ICS0) are enabled when setting the descriptor. It set the
descriptor address of the extended intelligent I/O service (EI2OS). Set the EI2OS descriptor address by
setting values in the EI2OS descriptor address setup bits (ICS3 to ICS0). The EI2OS descriptor address
setup bits (ICS3 to ICS0) are initialized to "0000B" by reset.
126
CHAPTER 6 INTERRUPT
Table 6.3-3 Correspondence between EI2OS Channel Setup Bits and Descriptor Addresses
ICS3
ICS2
ICS1
ICS0
Channel to be selected
Descriptor address
0
0
0
0
0
000100H
0
0
0
1
1
000108H
0
0
1
0
2
000110H
0
0
1
1
3
000118H
0
1
0
0
4
000120H
0
1
0
1
5
000128H
0
1
1
0
6
000130H
0
1
1
1
7
000138H
1
0
0
0
8
000140H
1
0
0
1
9
000148H
1
0
1
0
10
000150H
1
0
1
1
11
000158H
1
1
0
0
12
000160H
1
1
0
1
13
000168H
1
1
1
0
14
000170H
1
1
1
1
15
000178H
● Extended intelligent I/O Service (EI2OS) status bits (S1, S0)
The EI2OS status bits (S1, S0) are enabled when reading. When EI2OS is started, the EI2OS status bits (S1,
S0) can be read out to determine whether EI2OS is operating or is stopped. The bit is initialized to "00B" at
a reset.
Table 6.3-4 Relationship Between EI2OS Status Bits and EI2OS Status
S1
S0
0
0
While EI2OS is operating or when EI2OS is not starting
0
1
Stop state by end of counting
1
0
Reserved
1
1
Stop state by request from resource
EI2OS status
127
CHAPTER 6 INTERRUPT
6.4
Hardware Interrupt
By an interrupt request output from the peripheral function (resource), the hardware
interrupt suspends the program processing being performed by the CPU and passes
control to the interrupt processing program set previously. The extended intelligent I/O
service (EI2OS) is treated as hardware interruptions.
■ Hardware Interrupt
● Function of hardware interrupt
The hardware interrupt compares the interrupt level of the interrupt request output from the peripheral
function (resource) with the interrupt level mask register (PS: ILM), referees to the contents of the I flag
(PS: I), and then determines whether or not to accept the interrupt.
When the hardware interrupt is accepted, the direct page register (DPR), accumulator (A), program counter
(PC), processor status register (PS), and bank registers (ADB, DTB, PCB) are saved in the system stack,
the interrupt level set in the ICR registers are stored to the interrupt level mask register (ILM), control
branches to the interrupt vector, and then the interrupt processing program is executed.
● Multiple interrupts
A hardware interrupt can also be started during execution of the interrupt processing program.
● Extended intelligent I/O Service (EI2OS)
EI2OS is a function for transferring data between memory and I/O registers. A hardware interrupt is started
when transfer to the extended intelligent I/O service descriptor has completed. EI2OS is not started in the
multiple. During EI2OS processing, interrupt request or EI2OS request is not accepted. When EI2OS
processing has completed, interrupt request or EI2OS request is accepted.
● External interrupt
An external interrupt is accepted as a hardware interrupt when the interrupt request is detected by the
circuit (DTP/external interrupt circuit) that can output an interrupt request from the external pin.
● Interrupt vector
The interrupt vectors to be referred when executing the interrupt processing are allocated at "FFFC00H" to
"FFFFFFH" of memory.
128
CHAPTER 6 INTERRUPT
Reference:
For allocations of interrupt numbers and interrupt vectors, see "6.2 Interrupt Cause and Interrupt
Vector".
■ Structure Related to Hardware Interrupt
The structure related to hardware interrupts is divided as shown in Table 6.4-1 . When using a hardware
interrupt, the functions given below must be defined within the user program.
Table 6.4-1 Structure Related to Hardware Interrupt
Structure related to
hardware interrupt
Functions
Peripheral (resource)
Interrupt enable bits
Interrupt request flag bit
Peripheral function (resource) interrupt request
control
Interrupt controller
Interrupt control registers (ICR)
Setting interrupt levels and control of EI2OS
CPU
Interrupt enable flag (I)
Judgment control of interruption permission/
interdiction
Interrupt level mask register
(ILM)
Comparison between interrupt request level setup
values and output causes
Microcode
Execution of interruption handler routine
Interrupt vector table
Stores the branch destination address for interrupt
processing
In memory
"FFFC00H" to "FFFFFFH "
■ Hardware Interrupt Inhibit
Acceptance of hardware interrupts is inhibited in the conditions given below.
● Inhibits acceptance of hardware interrupts while writing in peripheral function (resource) control register
Hardware interrupt requests are not accepted while writing in peripheral function (resource) control
register.
Figure 6.4-1 Hardware Interrupt Requests while Writing in Peripheral Function Control Register Area
Writing instruction to peripheral function control register area
MOV A,#08
MOV io, A
Generated interrupt
request here
MOV A, 2000H
Not diverged to
interrupt
Interrupt process
Diverged to
interrupt
129
CHAPTER 6 INTERRUPT
● Inhibits acceptance of hardware interrupts of interrupt suppression instruction
The hardware interrupt inhibit instruction listed in Table 6.4-2 ignores interrupt requests without detecting
presence or absence of hardware interrupt requests. After a instruction other than this type instruction is
executed since of this instruction, the interrupt processing is done, when the hardware interruption request
is generated during executing the hardware interrupt control instruction.
Table 6.4-2 Hardware Interrupt Inhibit Instruction
Prefix code
The instructions which do
not accept the interrupt and
hold requests.
PCB
DTB
ADB
SPB
CMR
NCC
Interruption/holding control instruction
(The command that delays effects)
MOV
OR
AND
POPW
ILM, #imm8
CCR, #imm8
CCR, #imm8
PS
● Inhibits acceptance of hardware interrupts while executing software interrupt
When a software interrupt is started, the I flag is cleared to "0" and, therefore, no hardware interrupt
requests are accepted.
130
CHAPTER 6 INTERRUPT
6.4.1
Operation of Hardware Interrupt
Operation from interrupt request output to interrupt processing completion is
described.
■ Start of Hardware Interrupt
● Peripheral function (resource) operation (interrupt request output)
For a peripheral function (resource) with the hardware interrupt request function, the interrupt request flag
bit indicating presence of an interrupt request and the interrupt enable bit setting interrupt request enable/
disable are defined in the related peripheral function (resource) control register. When the peripheral
function (resource) detects a predefined interrupt cause, "1" is set in the interrupt request flag bit; when the
interrupt output enable bit is set to enable an interrupt request to the CPU, an interrupt request is output to
the interrupt controller.
● Interrupt controller operation (Interrupt request control)
The interrupt controller compares the interrupt request levels (IL) and accepts the interrupt request with the
highest level. When interrupt requests with the same level are output, the interrupt request with the smallest
interrupt number has a priority (see Table 6.2-1 ).
● CPU operation (Interrupt request acceptance and interrupt processing)
The CPU compares the received interrupt level value (ICS: IL2 to IL0) with the interrupt level mask
register value (ILM); if IL2 to IL0 < ILM and an interrupt is enabled (PS: CCR: I = 1), performs the
interrupt processing after completing the instruction currently being executed. In addition, the CPU
performs the interrupt processing when "0" has been set in the EI2OS enable bit (ISE) of the interrupt
control register (ICR) and starts EI2OS and then performs interrupt processing when "1" has been set.
Interrupt processing saves the contents of dedicated registers (12 bytes of A, DPR, ADB, DTB, PCB, PC,
PS) in the system stack (system stack space indicated by SSB and SSP), updates the interrupt vector
program counter value (PCB, PC) and ILM, sets "1" in the stack flag (S), and then enables the system
stack.
■ Return from Hardware Interrupt
When "0" is set in the interrupt request flag bit for the peripheral function (resource) of the interrupt cause
and the RETI instruction is executed by the interrupt processing program, the data saved in the system
stack is returned to the dedicated registers and then control returns to the program processing executed
before interrupt branch.
131
CHAPTER 6 INTERRUPT
■ Operation of Hardware Interrupt
Figure 6.4-2 Operation of Hardware Interrupt
Internal bus
(7)
F2MC-16LX CPU
PS,PC
Micro code
PS
IR
(6)
I
ILM
Check
Comparator
(5)
(4)
(3)
Other peripheral function
Peripheral function generated
interrupt request
(8)
Enable bit
Factor flag
(1)
AND
Level
comparator
Interrupt
level IL
(2)
Interrupt controller
RAM
IL : Interrupt level setting bit of interrupt control register (ICR)
PS : Processor status
I
: Interrupt enable flag
ILM : Interrupt level mask register
IR : Instruction register
(1) The interrupt cause is input inside the peripheral function (resource).
(2) When the interrupt enable bit in the peripheral function (resource) enables an interrupt, an interrupt
request is output from the peripheral function (resource) to the interrupt controller.
(3) When the interrupt controller receives an interrupt request from the peripheral function (resource), it
determines the interrupt priority and transfers the interrupt level (IL) of the interrupt request with the
highest priority to the CPU.
(4) The CPU compares the interrupt level requested from the interrupt controller with the interrupt level
mask register (ILM).
(5) When the comparison result shows that the priority level is higher than the set interrupt processing
level, the contents of the I flag of the condition code register (CCR) are checked.
(6) When the result of checking the I flag of the condition code register shows interrupt enabled (CCR: I =
1), waits completion of the currently executed instruction; upon completion, sets the requested level
(IL2 to IL0) in ILM.
(7) Saves the contents of the dedicated registers in the system stack and branches to the interrupt
processing routine.
(8) When "0" is set in the interrupt request flag bit for the peripheral function (resource) and the RETI
instruction is executed by the program in the interrupt processing routine, the values saved in the
system stack are returned to the dedicated registers and the interrupt processing completes.
132
CHAPTER 6 INTERRUPT
6.4.2
Interrupt Processing
When an interrupt request is output from the peripheral function (resource) and the CPU
has accepted the interrupt request, the interrupt processing is performed upon
completion of the currently executed instruction. The interrupt processing routine is
executed when "0" has been set in the EI2OS enable bit (ISE) of the interrupt control
register (ICR) and the extended intelligent I/O service (EI2OS) is started when "1" has
been set in the EI2OS enable bit (ISE). The software interrupt by an INT instruction
suspends the currently executed instruction, executes the interrupt processing routine
and inhibits the hardware interrupts.
133
CHAPTER 6 INTERRUPT
■ Interrupt Processing
Figure 6.4-3 Flow of Interrupt Processing
Start
Main program
I&IF&IE=1
AND
ILM>IL
During
executing string
system* instruction
NO
YES
Instruction activation/
recovery process
YES
ISE=1
Capture the next
instruction and decode
EI2OS
NO
YES
Is INT instruction?
NO
EI2OS process
Software interrupt/
exception process
Dedicated register
evacuation to system stack
I O
(hardware interrupt disabled)
Hardware
interrupt
Is specified
number of times completed,
or is there any end request
from peripheral
function?
Evacuation of dedicated
register to system stack
NO
YES
ILM IL
(Transfer interrupt level
of received interrupt
request to ILM.)
YES
Is RETI instruction?
NO
Normal instruction
execution
NO
Interrupt recovery
process
Dedicated register
recovery from system
stack to the routine before
calling interrupt routine.
S 1
(Enabled system
stack)
PCB,PC Interrupt vector
(diverged to interrupt
process routine)
Repeat of string
system* instruction has
completed.
YES
Pointer transmission
to next instruction
by PC renewal
*
: Interrupt judgement is carried out every 1 step
S
: Stack flag of condition code register (CCR)
during execution of string system instruction.
PCB : Program counter bank register
I
: Interrupt enable flag of condition code register (CCR)
PC : Program counter
IF : Interrupt request flag of peripheral function
IE : Interrupt enable flag of peripheral function
ILM : Interrupt level mask register (in PS)
ISE : EI2OS enable flag of interrupt control register (ICR)
IL : Interrupt enable level setting bit of interrupt control register (ICR)
134
CHAPTER 6 INTERRUPT
6.4.3
Procedure for Use of Hardware Interrupt
When using hardware interrupts, set the system stack area, peripheral functions
(resources), and interrupt control register (ICR).
■ Procedure for Use of Hardware Interrupt
Figure 6.4-4 Procedure for Use of Hardware Interrupt
Start
(1)
Setting of system stack area
(2)
Initial setting of peripheral function
Interrupt process program
(3)
Setting of ICR in interrupt
controller
(4)
Setting operation start set
interrupt enable bit of
peripheral function enable
(5)
Diverging to stack
process interrupt vector
(7)
Process by
hardware
Setting of ILM and I in PS
(8)
Process for interrupt to
peripheral function
(Execution of interrupt
processing routine)
(9)
Clear of interrupt factor
(10) Interrupt recovery instruction (RETI)
Main program
(6)
Interrupt request generation
Main program
(1) The system stack region is set.
(2) Sets the peripheral function (resource) operation.
(3) Interrupt control register (ICR) is set.
(4) Set the interrupt enable bit for the peripheral functions (resources) so that an interrupt request can be
output.
(5) Sets the interrupt level mask register (ILM) and interrupt enable flag (I) to accept interrupts.
(6) Outputs a hardware interrupt request when an interrupt request from the peripheral functions
(resources) is detected.
(7) The interrupt processing hardware saves the dedicated register values in the system stack and branches
to the interrupt processing program.
(8) The interrupt processing program performs processing for the peripheral functions (resources) in
response to the interrupt processing request output.
(9) Clears the peripheral function (resource) interrupt request.
(10) Executes the interrupt return instruction (RETI instruction) and returns to the program before
branching.
135
CHAPTER 6 INTERRUPT
6.4.4
Multiple Interrupts
The hardware interrupt allows setting multiple interrupts for multiple interrupt requests
from the peripheral functions (resources), but does not allow multiple starts of extended
intelligent I/O service.
■ Multiple Interrupts
● Multiple interrupts operation
When an interrupt request with an interrupt level higher than the interrupt request currently being executed
is output, suspends the current interrupt processing and executes the interrupt request with higher level.
Upon completion of the interrupt processing with the level higher than the currently executed interrupt
request, performs the interrupt processing suspended.
During the interrupt processing, when an interrupt request with a level not higher than the currently
executed interrupt is output, the new interrupt request is suspended until the current interrupt processing
completes unless the I flag of the condition code register (CCR) or the interrupt mask register (ILM) is
changed; upon completion of the current interrupt processing, the suspended interrupt request is executed.
When the condition code register (CCR) I flag is set to interrupt disable (CCR: I = 0) in the interrupt
processing routine or the interrupt level mask register (ILM) is set to interrupt disable (ILM = 000B),
multiple starts of interrupt can be inhibited.
Notes:
• The interrupt level can be set to 0 to 7; when level 7 is set, the CPU accepts no interrupt requests.
• Multiple EI2OS cannot be started. Suspends the interrupt requests output during processing of the
extended intelligent I/O service (EI2OS) and the extended intelligent I/O service requests.
● Example of multiple interrupts
An example of multiple interrupt processing: set the A/D converter interrupt level to 2 and the timer
interrupt level to 1, considering a case when timer interrupts are to be given higher priority than A/D
converter interrupts. When a timer interrupt is output during A/D converter interrupt processing, interrupt
processing is performed as shown in Figure 6.4-5 .
136
CHAPTER 6 INTERRUPT
Figure 6.4-5 Example of Multiple Interrupts
Main program
A/D interrupt process
Interrupt level 2
(ILM= 010B )
Peripheral
initialization
Interrupt level 1
(ILM= 001B )
( 1)
A/D interrupt ( 2)
generation
Timer interrupt process
( 3) Timer interrupt
generation
Interruption
(4) Timer interrupt process
Restart
Main process ( 8)
restart
( 6) A/D interrupt process
(5) Timer interrupt recovery
( 7) A/D interrupt recovery
• At the start of the A/D converter interrupt processing, the interrupt level mask register (ILM) is set to
the same value as the A/D converter interrupt level (ICR: IL2 to IL0) ((2) in the example). When an
interrupt request with level 1 or 0 has occurred, interrupt processing of level 1 or 0 is performed with
higher priority.
• When the interrupt processing has completed and the return instruction (RETI) is executed, the values of
the dedicated registers (A, DPR, ADB, DTB, PCB, PC, PS) saved in the stack register are returned and
the interrupt level mask register (ILM) has the values before the interrupt.
137
CHAPTER 6 INTERRUPT
6.4.5
Hardware Interrupt Processing Time
Between occurrence of a hardware interrupt request and the start of the interrupt
processing routine, time for completing the currently executed instruction and interrupt
handling time are required.
■ Hardware Interrupt Processing Time
Between output of an interrupt request from the peripheral function (resource) and the start of the interrupt
processing routine, time for waiting for a interrupt request sampling and interrupt handling time (time
required for preparing for interrupt processing) are required.
Figure 6.4-6 Interrupt Processing Time
Execution of normal
instruction
Operation of CPU
Interrupt waiting time
Interrupt request
sampling wait time
Interrupt handling
Interrupt process routine
Interrupt handling time
( machine cycle)*
Interrupt request output
*
: Instruction final cycle, sampling interrupt request here
: 1 machine cycle is 1 clock cycle of machine clock ( ).
● Interrupt request sampling delay time
Indicates the time from the interrupt request from the peripheral function (resource) to completion of the
currently executed instruction. The interrupt request checks by sampling whether or not an interrupt request
is output in the last cycle of the instruction being executed. During execution of an instruction, the interrupt
request cannot be recognized and an interrupt request sampling waiting time occurs.
Reference:
The interrupt request sampling waiting time takes the longest value when an interrupt request is
output immediately after starting POPW RW0 ... RW7 instruction (45 machine cycles) with the
longest execution cycles.
● Interrupt handling time (φ Machine cycle)
After accepting an interrupt request, the CPU requires interrupt handling time for saving the dedicated
register values to the system stack and fetching the interrupt vectors. The interrupt handling time can be
calculated by the expression shown below.
For the interruption startup φ =24 + 6 ✕ Z machine cycles
For interrupt return: φ = 11 + 6 ✕ Z machine cycles (RETI instruction)
138
CHAPTER 6 INTERRUPT
The interrupt handling time varies depending on the stack pointer address.
Table 6.4-3 Interrupt Handling Time Compensation Value (Z)
Address which stack pointer indicates
Compensation value (Z)
When an external interruption is 8 bits
+4
When an external interruption is an even number address
+1
When an external interruption is an odd number address
+4
When an internal interruption is an even number address
0
When an internal interruption is an odd number address
+2
Reference:
One machine cycle is equal to one clock cycle of the machine clock (φ).
139
CHAPTER 6 INTERRUPT
6.5
Software Interrupt
When a software interrupt instruction is executed, control is transferred from the main
program to the interrupt processing program. During execution of a software interrupt,
no hardware interrupts are accepted.
■ Start of Software Interrupt
● Start of Software Interrupt
A software interrupt is started by executing the INT instruction. The software interrupt request is output
when an INT instruction is executed; there are no interrupt request flag bits or enable bits like those for
hardware interrupts.
● Hardware interrupt inhibition
As the INT instruction has no interrupt levels, it does not update the interrupt level mask register (ILM).
During the execution of an INT instruction, "0" is set in the I flag of the condition code register (CCR) to
mask hardware interrupts. To enable hardware interrupts during software interrupt processing, set "1" in the
I flag of the condition code register (CCR) with the software interrupt routine.
● Operation of software interrupt
When the CPU fetches an INT instruction, it starts the microcode for software interrupt processing. The
microcode for software interrupt processing saves the registers in the CPU to the system stack, masks
hardware interrupts (CCR: I = 0), and then branches to the related interrupt vector.
Reference:
For allocations of interrupt numbers and interrupt vectors, see "6.2 Interrupt Cause and Interrupt
Vector".
■ Return from Software Interrupt
When the interrupt return instruction (RETI instruction) is executed in the interrupt processing program,
returns the data saved in the system stack to the dedicated registers and returns to the processing being
executed before interrupt branch.
140
CHAPTER 6 INTERRUPT
■ Operation of Software Interrupt
Figure 6.5-1 Operation of Software Interrupt
Internal bus
PS,PC
(1)
(2) Micro code
PS
I
S
IR
Cue
Fetch
RAM
PS
I
S
IR
: Processor status
: Interrupt enable flag
: Stack flag
: Instruction register
(1) Executes the software interrupt instruction (INT instruction).
(2) Saves the dedicated registers to the system stack, masks hardware interrupts, and branches to
the interrupt vector.
Note:
When the program counter bank register (PCB) has been set to "FFH", the CALLV instruction vector
area overlaps with the INT#vct8 instruction table; therefore, design software so that overlapping of
the CALLV instruction and INT#vct8 instruction addresses can be resolved.
141
CHAPTER 6 INTERRUPT
Interrupts by Extended Intelligent I/O Service (EI2OS)
6.6
Functions for transferring data between the peripheral functions (resources) and
memory. When the data transfer ends, hardware is interrupted.
■ Extended Intelligent I/O Service (EI2OS)
The extended intelligent I/O service is a kind of hardware interrupts. Functions for transferring data
between the peripheral functions (resources) and memory. The users write program when starting and
ending EI2OS; no data transfer programs are necessary.
● Advantages of Extended intelligent I/O Service (EI2OS)
Compared with data transfer performed by the interrupt processing routine, there are advantages listed
below.
• Because no descriptions of transfer program are required, the program size can be reduced.
• Because the transfer can be started by an interrupt cause of the peripheral functions (resources), polling
of data transfer causes is not necessary.
• The increment in the forwarding address can be set.
• Increment or no update may be set for I/O register addresses.
● Interrupt by Extended intelligent I/O Service (EI2OS) termination
Upon completion of the data transfer by EI2OS, branches to the interrupt processing routine.
The interrupt processing program can determine the EI2OS end cause by checking the EI2OS status bits
(S1, S0) of the interrupt control register (ICR).
Reference:
The interrupt numbers, interrupt vectors, etc. are fixed for individual peripheral functions. For details,
see "6.2 Interrupt Cause and Interrupt Vector".
● Interrupt control registers (ICR)
Allows setting the EI2OS start and EI2OS channel. Moreover, the EI2OS status of the EI2OS end is
displayed.
● Extended intelligent I/O Service (EI2OS) descriptor (ISD)
The EI2OS descriptor is a register of 8 bytes x 16 channels allocated at "000100H" to "00017FH" on the
RAM for setting transfer mode, peripheral function (resource) addresses, transfer byte count, and transfer
destination address. The channel is set in interrupt control register (ICR).
142
CHAPTER 6 INTERRUPT
Note:
When the extended intelligent I/O service (EI2OS) is operating, execution of the CPU program stops.
■ Operation of Extended Intelligent I/O Service (EI2OS)
Figure 6.6-1 Operation of Extended Intelligent I/O Service (EI2OS)
Memory space
Peripheral function (resource)
by IOA
Resource register
Resource
register
CPU
Interrupt request
(3)
ISD
(5)
(1)
by ICS
(2)
Interrupt control register (ICR)
(3)
Interrupt controller
by BAP
(4)
ISD
IOA
BAP
ICS
DCT
Buffer
by DCT
: EI2OS descriptor
: I/O address pointer
: Buffer address pointer
: EI2OS channel setting bit of interruption control register (ICR)
: Data counter
(1) Outputs an interrupt request from the peripheral functions (resources).
(2) The interrupt controller sets the EI2OS descriptor according to the settings in the interrupt control
register (ICR).
(3) The transfer source, destination, etc. are read from the descriptor.
(4) Data is transferred between the peripheral functions (resources) and memory.
(5) Upon completion of the data transfer, the peripheral function (resource) interrupt flag bit is cleared to
"0".
143
CHAPTER 6 INTERRUPT
6.6.1
Extended Intelligent I/O Service (EI2OS) Descriptor (ISD)
The EI2OS descriptor (ISD) is allocated to the addresses 000100H to 00017FH in the
internal RAM, and consists of 8 bytes x 16 channels.
■ Configuration of Extended Intelligent I/O Service (EI2OS) Descriptor (ISD)
ISD is composed of 8 bytes x 16 channels.
Figure 6.6-2 Configuration of EI2OS Descriptor (ISD)
MSB
LSB
Data counter upper 8 bits (DCTH)
"H"
Data counter lower 8 bits (DCTL)
I/O address pointer upper 8 bits (IOAH)
I/O address pointer lower 8 bits (IOAL)
EI2OS status register (ISCS)
Buffer address pointer upper 8 bits (BAPH)
Buffer address pointer middle 8 bits (BAPM)
ISD head address
(000100H + 8 × ICS)
Buffer address pointer lower 8 bits (BAPL)
MSB : Uppermost bit
LSB : Lowest bit
Table 6.6-1 EI2OS Descriptor (ISD) Area
144
Channel
Descriptor address
0
000100H
1
000108H
2
000110H
3
000118H
4
000120H
5
000128H
6
000130H
7
000138H
8
000140H
9
000148H
10
000150H
11
000158H
12
000160H
13
000168H
14
000170H
15
000178H
"L"
CHAPTER 6 INTERRUPT
Each Register of Extended Intelligent I/O Service (EI2OS)
Descriptor (ISD)
6.6.2
The EI2OS descriptor (ISD) consists of 8 bytes registers.
• Data counter (DCT:2 bytes)
• I/O register address pointer register (IOA:2 bytes)
• EI2OS status register (ISCS:1 byte)
• Buffer address pointer register (BAP:3 bytes)
The initial value of each register is irregular.
■ Data Counter (DCT)
Data counter (DCT) is a register of 16-bit lengths. Specifies the number of bytes to be transferred. Each
time data of one byte is transferred, the counter value is decremented by 1. EI2OS stops when the data
counter value becomes "0000H".
Figure 6.6-3 Configuration of Data Counter (DCT)
DCTL
DCTH
Bit
DCT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Initial value
0
XXXXXXXXXXXXXXXXB
B15 B14 B13 B12 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
R/W : Readable/Writable
X : Indefinite
■ I/O Address Pointer (IOA)
The I/O address pointer (IOA) is a 16-bit register. Sets I/O register lower addresses (A15 to A00) for data
transfer. The higher addresses (A23 to A16) are "00H"; I/O for addresses "0000H" to "FFFFH" can be set.
Figure 6.6-4 Configuration of I/O Address Pointer (IOA)
IOAH
Bit
IOA
15
14
13
12
11
IOAL
10
9
8
7
6
5
4
3
2
1
0
A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00
Initial value
XXXXXXXXXXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
R/W : Readable/Writable
X : Indefinite
■ EI2OS Status Register (ISCS)
The EI2OS status register (ISCS) is 8 bits in length and used for updating/fixing the buffer address pointer
and I/O address pointer, transfer data format (byte/word), and transfer direction.
145
CHAPTER 6 INTERRUPT
Figure 6.6-5 Configuration of Extended intelligent I/O Service (EI2OS) Status Register (ISCS)
7
Bit
6
5
4
3
2
1
0
IF
BW
BF
DIR
SE
R/W
R/W
R/W
R/W
R/W
Reserved Reserved Reserved
R/W
R/W
R/W
Initial value
XXXXXXXXB
EI2OS end control bit
SE
0
1
Not completed by request from peripheral function
Completed by request from peripheral function
Data transfer direction setting bit
DIR
0
I/O address pointer
1
Buffer address pointer
buffer address pointer
I/O address pointer
BF
BAP renewal/fix set bit
0
Buffer address pointer is renewed after data transfer*1.
1
Buffer address pointer is not renewed after data transfer.
BW
Transfer data length set bit
0
Byte
1
Word
IF
IOA renewal/fix set bit
0
I/O address pointer is renewed after data transfer*2.
1
I/O address pointer is not renewed after data transfer.
Reserved bit
Reserved
Be sure to set 0.
R/W : Readable/Writable
X
: Indefinite
*1 : Buffer address pointer is changed only lower 16-bit and enabled increment only.
*2 : Address pointer is enabled increment only.
■ Buffer Address Pointer (BAP)
The buffer address pointer (BAP) is a 24-bit register. Sets the memory address of the data transfer source
by EI2OS operation. As the buffer address pointer (BAP) is provided for each channel of EI2OS, it allows
data transfer between 16M-byte memory addresses and peripheral function (resource) addresses. When "0"
is set in the BAP updating/fixing setup bit (BF) of the EI2OS status register (ISCS), the lower 16 bits
(BAPM, BAPL) are incremented, but the upper 8 bits (BAPH) are not incremented.
Figure 6.6-6 Configuration of Buffer Address Pointer (BAP)
bit23
BAP
R/W
X
to
BAPH
(R/W)
: Readable/Writable
: Undefined
bit16 bit15
to
bit8 bit7
to
BAPM
BAPL
(R/W)
(R/W)
bit0
Initial value
XXXXXXH
Notes:
• The data counter (DCT) allows setting 65,536 (64K bytes) as the maximum transfer count.
• The I/O address pointer (IOA) allows setting the area at "000000H" to "00FFFFH".
• The buffer address pointer (BAP) allows setting the area at "000000H" to "FFFFFFH".
146
CHAPTER 6 INTERRUPT
6.6.3
Operation of Extended Intelligent I/O Service (EI2OS)
When an interrupt request is output from a peripheral function (resource) after setting
the EI2OS start in the interrupt control register (ICR), the CPU performs data transfer
with EI2OS. When the EI2OS processing ends, hardware is interrupted.
■ Operation of Extended Intelligent I/O Service (EI2OS)
Figure 6.6-7 Flowchart of Operation of Extended intelligent I/O Service (EI2OS)
Generating interrupt request
from peripheral function
NO
ISE=1
YES
Interrupt sequence
ISD/ISCS read
End request from
peripheral
function
YES
YES
SE=1
NO
NO
YES
DIR=1
NO
Specified data with IOA
(data transfer)
Specified memory with BAP
Specified data with BAP
(data transfer)
Specified memory with IOA
YES
IF=0
NO
Renewal value is
defined by BW.
IOA renewal
Renewal value is
defined by BW.
BAP renewal
YES
BF=0
NO
DCT decrement
DCT=00B
(-1)
YES
EI2OS end process
NO
Set S1 and S0 to "00B"
Set S1 and S0 to "01B"
Clear of peripheral function
interrupt request
CPU operating recovery
ISD : EI2OS descriptor
ISCS : EI2OS status register
IF
: IOA renewal/fix set bit of EI2OS status register (ISCS)
BW : Transfer data length set bit of EI2OS status register (ISCS)
BF : BAP renewal/fix set bit of EI2OS status register (ISCS)
DIR : Data transfer direct register set bit of
EI2OS status register (ISCS)
SE : EI2OS end control bit of EI2OS status register (ISCS)
Set S1 and S0 to "11B"
Clear ISR to "0"
Interrupt sequence
DCT
IOA
BAP
ISE
S1, S0
: Data counter
: I/O address pointer
: Buffer address pointer
: EI2OS enable bit of interrupt control register (ICR)
: EI2OS status of interrupt control register (ICR)
147
CHAPTER 6 INTERRUPT
6.6.4
Procedure for Use of Extended Intelligent I/O Service
(EI2OS)
For setting the extended intelligent I/O service (EI2OS), use the system stack area,
extended intelligent I/O service (EI2OS) descriptor, peripheral functions (resources), and
interrupt control register (ICR).
■ Procedure for use of Extended Intelligent I/O Service (EI2OS)
Figure 6.6-8 Procedure for Use of Extended intelligent I/O Service (EI2OS)
Process by software
Process by hardware
Start
Initial setting
Setting of system stack area
Setting of EI2OS descriptor
Initial setting of peripheral function
Setting of interrupt control
register (ICR)
Setting of operation start set
interrupt enable bit in
built-in resource
Setting of ILM and I in PS
S1,S0=00B
(Interrupt request) and (ISE=1)
Execution of user program
Data transfer
Judgement of diverging to
interrupt by end request
from countout or resource
YES
(Diverging to interrupt vector)
Resetting of extended
intelligent I/O service
(switching channel, etc.)
Data process during buffer
RETI
ISE : EI2OS enable bit of interrupt control register (ICR)
S1,S0 : EI2OS status of interrupt control register (ICR)
148
S1,S0=01B or
S1,S0=11B
NO
CHAPTER 6 INTERRUPT
6.6.5
Extended Intelligent I/O Service (EI2OS) Processing Time
Time necessary for processing of the extended intelligent I/O service (EI2OS) varies
depending on the settings in the extended intelligent I/O service descriptor (ISD).
• Setting of EI2OS status register (ISCS)
• Address settings indicated in I/O address pointer (IOA)
• Address settings indicated in buffer address pointer (BAP)
• Width of external data bus when external is accessed
• Data length of transfer data
Upon completion of the data transfer with EI2OS, a hardware interrupt is started;
therefore, the interrupt handling time is added.
■ Extended Intelligent I/O Service (EI2OS) Processing Time (time for one transfer)
● At continuing data transfer
The EI2OS processing time for continuation of data transfer is determined according to the settings in the
EI2OS status register (ISCS) as listed in Table 6.6-2 .
Table 6.6-2 Extended Intelligent I/O Service Execution Time
2
EI OS end control bit (SE) setting
Setting of IOA update/fixation and set bit (IF)
BAP address Update/fixed
Register Bits (BF) setting
Terminated by a termination
request from peripheral
functions
Termination request from
peripheral functions is
disregarded
Fixed
Update
Fixed
Update
Fixed
32
34
33
35
Update
34
36
35
37
Unit: One machine cycle is equal to one clock cycle of the machine clock (φ).
The EI2OS processing time for continuation of data transfer must be corrected according to the EI2OS
execution conditions as listed in Table 6.6-3 .
149
CHAPTER 6 INTERRUPT
Table 6.6-3 Compensation Value for Data Transfer at EI2OS Processing Time
Internal access
I/O address pointer
Buffer address pointer
Internal Access
External access
External access
B/Even
Odd
B/Even
8/Odd
0
+2
+1
+4
Odd
+2
+4
+3
+6
B/Even
+1
+3
+2
+5
8/Odd
+4
+6
+5
+8
B/Even
B: Byte data transfer
8: 8-bit word transfer by external bus width
Even: Even address word transfer
Odd: Odd address word transfer
● At completion of counting by data counter (DCT) (for final data transfer)
Upon completion of the data transfer with EI2OS, a hardware interrupt is started; therefore, the interrupt
handling time is added. The EI2OS processing time at the completion of counting is calculated by the
expression shown below. Z in the formula indicates the interpolation value for the interrupt handling time.
EI2OS processing time at count end = EI2OS processing time for data transfer + (21 + 6 × Z) machine cycles
↑
Interrupt handling time
The interrupt handling time varies depending on the address the stack pointer has stored.
Table 6.6-4 Interrupt Handling Time Compensation Value (Z)
Address which stack pointer indicates
Compensation value (Z)
For external 8 bits
+4
For the external even number address
+1
For the external odd number address
+4
For the internal even address
0
For the internal odd address
+2
● For completion by an end request from peripheral function (resource)
When an end request is output from a peripheral function (resource) and data transfer by EI2OS is
terminated halfway (ICR: S1, S0 = 11B), data is not transferred and a hardware interrupt is started. The
EI2OS processing time is calculated by the expression shown below. Z in the expression is the correction
value for the interrupt handling time (see Table 6.6-4 ).
EI2OS processing time at termination before completion = 36 + 6 × Z machine cycles
150
CHAPTER 6 INTERRUPT
Reference:
One machine cycle is equal to one clock cycle of the machine clock (φ).
151
CHAPTER 6 INTERRUPT
6.7
Exception Processing Interrupt
When an instruction not defined for the MB90800 series is executed, exception
processing is performed. Exception processing is similar to an interrupt; occurrence of
an exceptional event between instructions causes the program processing to be
suspended and branches to the exception processing routine.
Exception processing occurs as a result of performing unexpected operations; it may
be used for debugging, executing undefined instructions, or detecting a CPU overrun.
■ Exception Processing
● Operation of exception processing
In the MB90800 series, execution of an instruction not defined in the instruction map causes branching to
the exception processing routine for the software interrupt instruction.
In exception processing, the processing shown below is performed before branching to the interrupt
routine.
• Saves the contents of the dedicated registers (A, DPR, ADB, DTB, PCB, PC, PS) in the system stack.
• Clears the I flag of the condition code register (CCR) to "0" to mask hardware interrupts.
• Sets "1" in the S flag of the condition code register (CCR) to enable the system stack.
The value of the program counter (PC) saved in the system stack stores the program addresses of undefined
instructions. For an instruction code of 2 bytes or more in length, this program address stores the code
recognized to be an undefined instruction. When determining the exceptional cause type is necessary in the
exception processing routine, use the PC value saved in the system stack.
● Return from exception processing
When an RETI instruction is used for return from the exception processing, the PC indicates an undefined
instruction, causing to branch again to the exception processing routine. Make a software reset or input "L"
level (external reset) from the (RST) pin.
152
CHAPTER 6 INTERRUPT
6.8
Stack Operation of Interrupt Processing
When the interrupt is accepted, saves the contents of the dedicated registers in the
system stack before branching to the interrupt processing. After completion of the
interrupt processing, the values saved in the system stack can be returned to the
dedicated registers by executing an interrupt return instruction.
■ Stack Operation at the Start of Interrupt Processing
When the interrupt is accepted, the CPU saves the contents of the dedicated registers in the system stack in
the order shown below.
1. Accumulator (A)
2. Direct page register (DPR)
3. Additional data bank register (ADB)
4. Data bank register (DTB)
5. Program counter bank register (PCB)
6. Program counter (PC)
7. Processor status (PS)
Figure 6.8-1 Stack Operation at the Start of Interrupt Processing
Immediately before
interrupt
SSB
Address
08FFH
08FEH
00H
SSP
08FEH
A
0000H
AH
08FEH
AL
DPR
01H
ADB
00H
DTB
00H
PCB
FFH
PC
803FH
PS
20E0H
08F2H
Immediately after
interrupt
Memory
SSB
XXH
XXH
XXH
XXH
XXH
XXH
XXH
XXH
XXH
XXH
XXH
XXH
SP
"H"
08FFH
08FEH
00H
SSP
08F2H
A
0000H
AH
"L"
Address
08FEH
AL
DPR
01H
ADB
00H
DTB
00H
PCB
FFH
PC
803FH
PS
20E0H
Byte
08F2H
Memory
SP
00H
00H
08H
FEH
01H
00H
00H
FFH
80H
3FH
20H
E0H
Byte
AH
AL
DPR
ADB
DTB
PCB
PC
PS
SP after
renewal
■ Stack Operation when Interrupt Processing Returns
When the interrupt return instruction (RETI instruction) is executed after completion of the interrupt
processing, the values of the dedicated registers (PS, PC, PCB, DTB, ADB, DPR, A) are returned from the
stack in the reversed order for the interrupt processing start and the dedicated registers return to the state
before branching to the interrupt processing.
153
CHAPTER 6 INTERRUPT
■ Stack Area
● Securing stack area
The stack area is also used for saving/returning the program counter (PC) when executing interrupt
processing, subroutine call instruction (CALL), or vector call instruction (CALLV) or for saving/returning
the register values by PUSHW or POPW instruction. The stack region is set on RAM with the data area.
Figure 6.8-2 Stack Area
Vector table
(reset and interrupt
vector call instruction)
FFFFFFH
FFFC00H
ROM area
FF0000H *1
000D00H *2
Built-in RAM area
Stack area
000380H
General purpose
register bank area
000180H
000100H
0000C0H
000000H
Built-in I/O area
*1: Built-in ROM is different depending on products.
*2: Built-in RAM is different depending on products.
Notes:
• When setting an address in the stack pointers (SSP, USP), set an even address. When an odd
address has been set, stack saving/return processing requires additional 1-cycle time.
• Allocate the system stack, user stack, and data areas so that they do not overlap.
● System stack area and user stack area
The system stack area is used for interrupt processing. When the user stack area is used and an interrupt
occurs, it is switched to the system stack. When division of the stack space is not necessary, use the system
stack.
154
CHAPTER 6 INTERRUPT
6.9
Example of Interrupt Processing Program
An example of interrupt processing program is shown below.
■ Example of Interrupt Processing Program
● Processing specification
An example interruption program that uses external interruption 0 (INT0)
● Coding example
DDR1
EQU
000011H
; Port 1 direction register
ENIR
EQU
028H
; DTP/interruption permission register
EIRR
EQU
029H
; Interrupt/DTP flag
ELVR
EQU
02AH
; a register to specify the required level
ICR00
EQU
0B0H
; Interrupt control registers
STACK
SSEG
RW
STACK_T RW
STACK
; Stack
100
1
ENDS
;----------Main Program-----------------------------------------------------CODE
CSEG
;
START:
LOOP:
MOV
RP, #0
; Header bank used for general-purpose registers
MOV
ILM, #07H
; Sets ILM in PS to level 7
MOV
A, #!STACK_T
; Sets system stack
MOV
SSB, A
MOVW A, #STACK_T
; Stack pointer setting.
MOVW SP, A
; In this case, the pointer set to SSP, because S flag = 1.
MOV
DDR1,#00000000B
;P10/INT0 pin for input.
OR
CCR, #40H
; Sets I flag in PS to enable interrupts.
MOV
I:ICR00, #00H
; Sets interrupt level 0 (highest).
MOV
I:ELVR, #00000001B ; make INT0 "H" level
MOV
I:EIRR, #00H
; Clears interrupt cause for INT0.
MOV
I:ENIR, #01H
; INT0 input permitted:
NOP
; Dummy loop
NOP
NOP
NOP
155
CHAPTER 6 INTERRUPT
BRA
LOOP
; Unconditional jump
;----------Interrupt Program-----------------------------------------------------ED_INT1:
MOV
I:EIRR, #00H
; new acceptance of INT0 prohibited
NOP
NOP
NOP
NOP
NOP
NOP
RETI
CODE
; Returns from interrupt.
ENDS
;----------Vector Settings-----------------------------------------------------------VECT
VECT
CSEG
ABS=0FFH
ORG
0FFD0H
DSL
ED_INT1
ORG
0FFDCH
DSL
START
DB
00H
; The vector is set in interruption #11(0BH)
; Reset vector setting
; Single-chip mode setting
ENDS
END
START
■ Example Program of Extended Intelligent I/O Service (EI2OS)
● Processing specification
• EI2OS is started upon detection of the High level of the signal input to the INT0 pin.
• When "H" level is input to INT0 pin, EI2OS is started, which transfers data at port 0 to memory address
"3000H".
• The transfer data byte count is 100; after transferring 100 bytes, outputs an interrupt for EI2OS transfer
completion.
● Coding example
156
DDR1
EQU
000011H
; Port 1 direction register
ENIR
EQU
000028H
; DTP/interruption permission register
EIRR
EQU
000029H
; DTP/interruption factor register
ELVR
EQU
00002AH
; a register to specify the required level
ICR00
EQU
0000B0H
; Interrupt control registers
BAPL
EQU
000100H
; Lower Buffer address pointer lower
BAPM
EQU
000101H
; Buffer address pointer middle
BAPH
EQU
000102H
; Higher Buffer address pointer higher
CHAPTER 6 INTERRUPT
ISCS
EQU
000103H
; EI2OS Status
IOAL
EQU
000104H
; Lower I/O address pointer
IOAH
EQU
000105H
; Higher I/O address pointer
DCTL
EQU
000106H
; Lower data counter
DCTH
EQU
000107H
; Upper data counter
ER0
EQU
EIRR:0
; Defines external interrupt request flag bit.
STACK
SSEG
RW
STACK_T RW
STACK
; Stack
100
1
ENDS
;----------Main Program-----------------------------------------------------CODE
CSEG
START:
AND
CCR,#0BFH
; Clears the I flag in PS to disable interrupts.
MOV
RP,#00
; Sets register bank pointer.
MOV
A,#!STACK_T
; Sets system stack
MOV
SSB,A
MOVW A,#STACK_T
; Stack pointer setting.
MOVW SP,A
; In this case, the pointer set to SSP, because S flag = 1.
MOV
I:DDR1,#00000000B
; Sets the P10/INT0 pin for input.
MOV
BAPL,#00H
; Sets buffer address (003000H)
MOV
BAPM,#30H
MOV
BAPH,#00H
MOV
ISCS,#00010001B
; No I/O address update, byte transfer
; Buffer address updated
; I/O-> Transfer to buffer by peripheral functions
; Yes
MOV
IOAL,#00H
MOV
IOAH,#00H
MOV
DCTL,#64H
MOV
DCTH,#00H
MOV
I:ICR00,#00001000B
; Sets transfer source address (port 0: 000000H)
; Sets transfer byte count (100 bytes)
; EI2OS channel 0, EI2OS enable, interrupt level 0
; (Highest)
MOV
I:ELVR,#00000001B
; make INT0 "H" level
MOV
I:EIRR,#00H
; Clears interrupt cause for INT0.
MOV
I:ENIR,#01H
; Enables INT0 interrupt.
MOV
ILM,#07H
; Sets ILM in PS to level 7
OR
CCR,#40H
; Sets I flag in PS to enable interrupts.
:
157
CHAPTER 6 INTERRUPT
LOOP:
BRA
LOOP
; Infinite loop
;----------Interrupt Program-----------------------------------------------------WARI
CLRB
ER0
; Interrupt/DTP request flag clear
:
user processing
; Confirmation of the cause of the EI2OS completion
:
; Processes data in buffer, resetting EI2OS etc.
RETI
CODE
ENDS
----------Vector Settings------------------------------------------------------------VECT
VECT
CSEG
ABS=0FFH
ORG
0FFD0H
DSL
WARI
ORG
0FFDCH
DSL
START
DB
00H
ENDS
END
158
START
; The vector is set in interruption #11(0BH)
; Reset vector setting
; Single-chip mode setting
CHAPTER 7
SETTING MODE
This chapter describes the MB90800 series operation
mode and memory access mode.
7.1 Overview of Setting Mode
7.2 Mode Pins (MD2 to MD0)
7.3 Mode Data
159
CHAPTER 7 SETTING MODE
7.1
Overview of Setting Mode
Operation mode can be set by setting the mode pin level for reset input and setting
mode data in the mode data register.
■ Setting Mode
Operating mode
Bus mode
RUN mode
Single chip
Flash memory writing mode
■ Operating Mode
For setting operation mode, use the mode pins (MD2 to MD0) and the bus mode setup bits (M1, M0) of the
mode data register. Use the set mode for normal operation start/Flash memory write.
Note:
In the MB90800 series, please set the single chip mode.
When setting single-chip mode, set the MD2 to MD0 pins to "011B" and the bus mode setup bits
(M1, M0) of the mode data register to "00B".
■ Bus Modes
Bus mode varies depending on whether the memory for reading the reset vector is external or internal. Bus
mode can be set by setting the mode setup pins (MD2 to MD0) and setting the bus mode setup bits (M1,
M0) of the mode data register. The bus mode for reading the reset vector and mode data is set by the mode
setup pins (MD2 to MD0). The bus mode is also set by the bus mode setup bits (M1, M0) of the mode data
register.
Reference:
RUN mode means a mode in which the CPU is operating. There are three RUN modes: main clock
mode for operating with the main clock, PLL clock mode for operating with the PLL clock, and lowpower consumption mode. For details, see "CHAPTER 5 LOW-POWER CONSUMPTION MODE".
Note:
In the MB90800 series, please set the single chip mode.
When setting single-chip mode, set the MD2 to MD0 pins to "011B" and the bus mode setup bits
(M1, M0) of the mode data register to "00B".
160
CHAPTER 7 SETTING MODE
7.2
Mode Pins (MD2 to MD0)
Mode pins are three external pins MD2 to MD0 used for setting how to fetch the reset
vector and mode data.
■ Mode Pins (MD2 to MD0)
Use the mode pins to set whether to read the reset vector from external or internal memory. When the reset
vector has been set in external memory, set the external data bus width in the mode data register.
When there is a built-in Flash memory, set Flash memory write mode with the mode pins to allow program
to be written in built-in Flash memory.
Table 7.2-1 Setting of Mode Pins
Mode name
Reset vectors
access area
External data
bus width
MD2
MD1
MD0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
0
1
1
0
Flash memory
Serial write mode *
-
-
-
1
1
1
Flash memory mode
-
-
-
Remark
Setting disabled
Internal vector mode
Internal memory
Mode Data
Register setting
Controlled by mode data
after set sequence
Setting disabled
Set MD2 to MD0: 0 = VSS or 1 = VCC.
*: Flash memory serial writing is not performed by only setting the mode pin. It is necessary to set other parts. For details,
see "CHAPTER 26 CONNECTION EXAMPLES FOR SERIAL WRITING".
Note:
In the MB90800 series, please set the single chip mode.
When setting single-chip mode, set the MD2 to MD0 pins to "011B" and the bus mode setup bits
(M1, M0) of the mode data register to "00B".
161
CHAPTER 7 SETTING MODE
7.3
Mode Data
The mode data register is at address "FFFFDFH" in memory and used for setting the
memory access operation to be performed after the reset sequence.
■ Mode Data
During execution of the reset sequence, the mode data at address "FFFFDFH" is fetched to the mode data
register. The contents of the mode data register can be changed during execution of the reset sequence. It is
not possible to change by the instruction. The mode data settings become effective after the reset sequence.
Figure 7.3-1 Construction of Mode Data
Bit
Mode data register
7
5
6
M1 M0 0
4
0
3
0
2
0
1
0
0
0
Function extended bit (reserved area)
Bus mode setting bit
■ Bus Modes Setting Bit
Bit for setting bus mode to be used after completion of the reset sequence.
Table 7.3-1 Bus Modes Setting Bit and Function
M1
M0
Function
0
0
Single-chip mode
0
1
1
0
1
1
(Setting prohibited)
Note:
In the MB90800 series, please set the single chip mode.
When setting single-chip mode, set the MD2 to MD0 pins to "011B" and the bus mode setup bits
(M1, M0) of the mode data register to "00B".
162
CHAPTER 7 SETTING MODE
Figure 7.3-2 Relation between Access Region and Physical Address
FFFFFFH
ROM
Each product #1
FE0000H
00FFFFH
When setting ROM mirror function
ROM mirror
Each product #2
Each product #3
: No access
RAM
000100H
0000C0H
I/O
: Internal access
000000H
Note: "Each product #x" is address determined depending on each product.
Refer to "2.3 Memory Map" for detail.
■ Mode Pin and Mode Data
Table 7.3-2 Relation between Mode Pin and Mode Data
Mode
MD2
MD1
MD0
M1
M0
Single-chip mode
0
1
1
0
0
Note:
In the MB90800 series, please set the single chip mode.
When setting single-chip mode, set the MD2 to MD0 pins to "011B" and the bus mode setup bits
(M1, M0) of the mode data register to "00B".
163
CHAPTER 7 SETTING MODE
164
CHAPTER 8
I/O PORT
This chapter describes the MB90800 series input/output
port functions and operations.
8.1 Overview of Input/Output Port
8.2 Explanation of Register of Input/Output Port
8.3 Port 0
8.4 Port 1
8.5 Port 2
8.6 Port 3
8.7 Port 4
8.8 Port 5
8.9 Port 6
8.10 Port 7
8.11 Port 8
8.12 Port 9
8.13 Example of Programming Input/Output Port
165
CHAPTER 8 I/O PORT
8.1
Overview of Input/Output Port
There is a maximum of 70 input/output ports (parallel I/O ports), which also work as the
shared resource input/output pins (peripheral function input/output pins).
■ Input/Output Port Function
Input/output ports have port direction register (DDR) and port data register (PDR). The port direction
register (DDR) allows setting port pin input/output in bit units. The port data register (PDR) allows setting
data to be output to port pins. When the input/output port pins have been set as input with the port direction
register (DDR), the port pin level value can be read from the port data register (PDR). When the input/
output port pins have been set as output with the port direction register (DDR), the value of the port data
register (PDR) is output to port pins. The input/output port functions and assigned resources are shown
below.
Table 8.1-1 List of Each Port Function
I/O port
name
Pin name
Input type
CMOS
(hysteresis)
Output
type
CMOS
Function
Port 0
P00 to P07
I/O port
Resource
Port 1
P10 to P17
I/O port
Resource
SEG27
Port 2
P20 to P27
I/O port
P27
Resource
SEG35
Port 3
P30 to P37
I/O port
P37
Resource
Port 4
Port 5
P40 to P47
P50 to P57
P07
P06
P05
P04
P03
P02
P01
P00
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
P17
P16
P15
P14
P13
P12
P11
P10
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
P26
P25
P24
P23
P22
P21
P20
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
P36
P35
P34
P33
P32
P31
P30
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
OCU1
OCU0
IC1
IC0
TMCK
SI3
SC3
SO3
I/O port
P47
P46
P45
P44
P43
P42
Resource
TOT2
TOT1
TOT0
I/O port
P57
P56
P55
P54
P53
P52
P51
P50
Resource
SI1
SO0
SC0
SI0
SEG47
SEG46
SEG45
SEG44
PPG1
TIN2
TIN1
TIN0
-
-
P41
-
P40
-
-
PPG0
Port 6
P60 to P67
I/O port
P67
P66
P65
P64
P63
P62
P61
P60
Resource
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
INT1
INT0
P76
P75*
P74*
P73
P72
P71
P70
SCL
SDA
AN11
AN10
AN9
AN8
SO2
SC2
SI2
SO1
SC1
INT3
INT2
Port 7
Port 8
Port 9
P70 to P76
P80 to P84
P90, P91
*: P75 and P74 is used N-ch open drain
166
I/O port
-
Resource
-
-
I/O port
-
-
-
P84
P83
P82
P81
P80
Resource
-
-
-
COM3
COM2
V2
V1
V0
I/O port
-
-
-
-
-
-
Resource
-
-
-
-
-
-
P91
P90
-
-
CHAPTER 8 I/O PORT
Note:
As ports 6 and 7 are shared with analog input pins; when they are used as input/output ports, set "
00H " in the port 6/port 7 direction registers (DDR6/DDR7), port 6/port 7 data registers (PDR6/
PDR7), and analog input enable registers 0/1 (ADER0/ADER1), respectively. The analog input
enable registers 0 and 1 (ADER0/ADER1) are initialized to "FFH" by reset.
Port 9 exists only in one system clock products.
■ Operations of the Shared Resource Ports Set as Output Port by DDR Register
Figure 8.1-1 Pin States of Shared Resource Ports when Resource Operation is Enabled/Disabled
Enable/disable setting
of resource operation
Port with resource
pin state
Resource operation enable
Depending on resource disable
Resource operation prohibited
Output PDR register value
167
CHAPTER 8 I/O PORT
8.2
Explanation of Register of Input/Output Port
The list of registers related to input/output settings is given below.
■ List of Register of Input/Output Port
Table 8.2-1 Registers of Each Port
Register name
Read/Write
Address
Initial value
Port 0 data register (PDR0)
R/W
000000H
XXXXXXXXB
Port 1 data register (PDR1)
R/W
000001H
XXXXXXXXB
Port 2 data register (PDR2)
R/W
000002H
XXXXXXXXB
Port 3 data register (PDR3)
R/W
000003H
XXXXXXXXB
Port 4 data register (PDR4)
R/W
000004H
XXXXXXXXB
Port 5 data register (PDR5)
R/W
000005H
XXXXXXXXB
Port 6 data register (PDR6)
R/W
000006H
XXXXXXXXB
Port 7 data register (PDR7)
R/W
000007H
- XXXXXXXB
Port 8 data register (PDR8)
R/W
000008H
- - - XXXXXB
Port 9 data register (PDR9)
R/W
000009H
- - - - - - XXB
Port 0 direction register (DDR0)
R/W
000010H
0 0 0 0 0 0 0 0B
Port 1 direction register (DDR1)
R/W
000011H
0 0 0 0 0 0 0 0B
Port 2 direction register (DDR2)
R/W
000012H
0 0 0 0 0 0 0 0B
Port 3 direction register (DDR3)
R/W
000013H
0 0 0 0 0 0 0 0B
Port 4 direction register (DDR4)
R/W
000014H
0 0 0 0 0 0 0 0B
Port 5 direction register (DDR5)
R/W
000015H
0 0 0 0 0 0 0 0B
Port 6 direction register (DDR6)
R/W
000016H
0 0 0 0 0 0 0 0B
Port 7 direction register (DDR7)
R/W
000017H
- 0 0 0 0 0 0 0B
Port 8 direction register (DDR8)
R/W
000018H
- - - 0 0 0 0 0B
Port 9 direction register (DDR9)
R/W
000019H
- - - - - - 0 0B
Analog input enable register 0 (ADER0)
R/W
00001EH
1 1 1 1 1 1 1 1B
Analog input enable register 1 (ADER1)
R/W
00001FH
- - - - 1 1 1 1B
R/W: Readable/Writable
X: Indefinite
-: Undefined
168
CHAPTER 8 I/O PORT
Notes:
• When read modify write (RMW) instruction is executed for the port data register (PDR) in port input
mode, the pin levels are read by READ. Note that the values of bits used as input ports, not bit
operated, of the same series may change.
• When read modify write (RMW) instruction is executed for port data register (PDR) shared with the
resource during resource operation, the level of the pins operating as resources are read by
REDA. Note that the values of bits used as input ports, not bit operated, of the same series may
change.
Table 8.2-2 Object to be Read by Execution of Read Modify Write (RMW) Instruction for PDR Register
At resource operation enable
At resource operation disable
DDR=00H when port input is set
Pin level
Pin level
DDR=FFH when port output is set
Pin level
PDR register value
Enable/disable setting of
resource operation
Port with resource
pin state
Resource operation enable
Depending on resource operation
Read modify write (RMW) instruction
executing timing corresponding
to PDR register
PDR register value
Resource operation disable
Previous data
Input setting (DDR=00H) : Hi-Z
Output setting (DDR=FFH) : Output the changed
PDR value
Read modify write (RMW) instruction execution
Changed by the pin level at executing read modify write (RMW) instruction
169
CHAPTER 8 I/O PORT
8.3
Port 0
Port 0 is a input-output port. This chapter shows configuration of port 0, block diagram
and register of pin.
■ Configuration of Port 0
Port 0 is composed as follows.
• I/O pins/resource I/O pins (P00/SEG12 to P07/SEG19)
• Port 0 data register (PDR0)
• Port 0 direction register (DDR0)
■ A Pin at Port 0
Table 8.3-1 A pin at port 0
Port
name
Port 0
Pin name
Port function
Input/Output port
Resource
function
P00/SEG12
P00
SEG12
P01/SEG13
P01
SEG13
P02/SEG14
P02
SEG14
P03/SEG15
P03
SEG15
P04/SEG16
P04
SEG16
P05/SEG17
P05
SEG17
P06/SEG18
P06
SEG18
P07/SEG19
P07
SEG19
LCD
segment
output
I/O type
Input
CMOS
(hysteresis)
Output
CMOS
Circuit
type
E
Reference:
For the circuit types, see "1.7 I/O Circuit Type".
■ Port 0 Registers
Port 0 register has port 0 data register (PDR0) and port 0 direction register (DDR0). Bits of each register
have one-to-one correspondence with pins of port 0.
Table 8.3-2 Relation between Port 0 Registers and Pins
Port
name
Port 0
170
Bits of related registers and corresponding pins
PDR0, DDR0
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Corresponding pin
P07
P06
P05
P04
P03
P02
P01
P00
CHAPTER 8 I/O PORT
8.3.1
Port 0 Registers (PDR0, DDR0)
The registers for port 0 are explained.
■ Port 0 Register Function
● Port 0 data register (PDR0)
The output value of each terminal of port 0 is set.
● Port 0 direction register (DDR0)
Sets the input/output direction for each pin of port 0.
The pin becomes an output port when "1" is set in the bit corresponding to the pin and becomes an input
port when "0" is set.
Table 8.3-3 Port 0 Register Function
Register
name
Port 0 data
register
(PDR0)
Port 0 data
direction
register
(DDR0)
Bit
value
At read
At write
Address
Input port
Output port
Input port
Output port
0
Pin state is
"L" level
"0" is set to
the bit of the
PDR0
register.
"0" is set to
the bit of the
PDR0
register.
"L" level is
output from
the terminal.
1
Pin state is
"H" level
"1" is set to
the bit of the
PDR0
register.
"1" is set to
the bit of the
PDR0
register.
"H" level is
output from
the terminal.
0
"0" is set to the bit of the
DDR0 register.
Input port
1
"1" is set to the bit of the
DDR0 register.
Output port
Initial value
000000H
XXXXXXXXB
000010H
00000000B
X: Indefinite
171
CHAPTER 8 I/O PORT
8.3.2
Operation of Port 0
This section describes the operation of port 0.
■ Operation of Port 0
● When output port is set by Port 0 direction register (DDR0)
• The value set in the Port 0 data register (PDR0) is output to the port 0 pins.
• When the Port 0 data register (PDR0) is read, the value set in the Port 0 data register (PDR0) is read out.
● When input port is set in Port 0 direction register (DDR0)
• The port 0 pin enters a high impedance state.
• A value set in the Port 0 data register (PDR0) is maintained, but not output to the pins.
• When the Port 0 data register (PDR0) is read, the input level value ("0" for "L" and "1" for "H") is read
out.
Note:
If read modify write (RMW) instructions (such as the bit set instruction) are used to access port 0
data register (PDR0), the bit set to output in port 0 direction register (DDR0) is not affected.
However, the bit set to input in port 0 direct register (DDR0) is written the value of pin input level to
port 0 data register (PDR0), therefore, when changing the bit set to input to output, port 0 data
register (PDR0) should be set to output after setting output value in port 0 data register (PDR0).
● Operation of segment output
When using as a segment output pin, set "1" in the corresponding bit of the LCDC control register.
General-purpose input/output port is disabled and functions as the segment output pin.
● Operation when a reset is performed
• When the CPU is reset, the Port 0 direction register (DDR) value is initialized to "00H" and the port 0
pin is placed in high-impedance state.
• As the Port 0 register (PDR0) is not initialized by reset, to use as an output port, set the output value in
the Port 0 data register (PDR0) and then set the Port 0 direction register (DDR0) for output.
172
CHAPTER 8 I/O PORT
● Operation at stop, timebase timer mode and watch mode
If "1" has been set in the pin state setup bit (SPL) of the low-power consumption mode control register
(LPMCR) when transiting to stop mode, timebase timer mode, or watch mode, the pin is put in highimpedance state regardless of the value of the Port 0 direction register (DDR0). In addition, the input buffer
is also unconditionally blocked to prevent leakage by input open.
When functioning as a segment output pin, the segment output state is maintained.
Table 8.3-4 Port 0 Pin Status
Stop mode,
Timebase timer mode,
Watch mode
(SPL= 0)
Stop mode,
Timebase timer mode,
Watch mode
(SPL= 1, RDRF= 0)
Input/Output port
Input cutoff
level hold
Input cutoff/output Hi-Z
Segment output
Segment output
Segment output
Pin name
Normal
operation
Sleep mode
P00 to P07
Input/Output port
Segment output
SEG12 to SEG19
SPL: Pin state specification bit of low-power consumption mode control register (LPMCR: SPL)
Hi-Z: High impedance
173
CHAPTER 8 I/O PORT
8.4
Port 1
Port 1 is an input-output port. The configuration, block diagram of the pins and
registers for port 1 are shown below.
■ Configuration of Port 1
Port 1 is composed as follows.
• I/O pins/resource I/O pins (P10/SEG20 toP17/SEG27)
• Port 1 data register (PDR1)
• Port 1 direction register (DDR1)
■ A Pin at Port 1
Table 8.4-1 A Pin at Port 1
Port
name
Pin name
Port 1
P10/SEG20
P10
P11/SEG21
P11
P12/SEG22
P12
SEG22
P13/SEG23
P13
SEG23
P14/SEG24
P14
SEG24
P15/SEG25
P15
SEG25
P16/SEG26
P16
SEG26
P17/SEG27
P17
SEG27
Port function
I/O type
Resource function
Input
Input/Output
port
SEG20
SEG21
LCD segment
output
Output
CMOS
(hysteresis)
CMOS
Circuit
type
E
Reference:
For the circuit types, see "1.7 I/O Circuit Type".
■ Port 1 Registers
The registers for port 1 are port 1 data register (PDR1) and port 1 direction register (DDR1). Bits of each
register have one-to-one correspondence with pins of port 1.
Table 8.4-2 The Correspondence between the Registers and Pins of Port 1
Port
name
Port 1
174
Bits of related registers and corresponding pins
PDR1, DDR1
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Corresponding pin
P17
P16
P15
P14
P13
P12
P11
P10
CHAPTER 8 I/O PORT
8.4.1
Registers for Port 1 (PDR1, DDR1)
The registers for port 1 are explained.
■ Function of Registers for Port 1
● Port 1 data register (PDR1)
The output value of each terminal of port 1 is set.
● Port 1 direction register (DDR1)
Sets the input/output direction for each pin of port 1.
The pin becomes an output port when "1" is set in the bit corresponding to the pin and becomes an input
port when "0" is set.
Table 8.4-3 Function of Registers for Port 1
Register
name
Port 1 data
register
(PDR1)
Port 1
direction
register
(DDR1)
At Read
At Write
Bit value
Address
Input port
Output port
Input port
Output port
0
Pin state is
"L" level
"0" is set to
the bit of the
PDR1
register.
"0" is set to
the bit of
the PDR1
register.
"L" level is
output from
the terminal.
1
Pin state is
"H" level.
"1" is set to
the bit of the
PDR1
register.
"1" is set to
the bit of
the PDR1
register.
"H" level is
output from
the terminal.
0
"0" is set to the bit of the
DDR1 register.
Input port
1
"1" is set to the bit of the
DDR1 register.
Output port
Initial value
000001H
XXXXXXXXB
000011H
00000000B
X: Indefinite
175
CHAPTER 8 I/O PORT
8.4.2
Operation of Port 1
The operation of port 1 is explained.
■ Operation of Port 1
● When output port is set by Port 1 direction register (DDR1)
• The value set in the Port 1 data register (PDR1) is output to the port 1 pins.
• When the Port 1 data register (PDR1) is read, the value set in the Port 1 data register (PDR1) is read out.
● When input port is set in Port 1 direction register (DDR1)
• The port 1 pin enters a high impedance state.
• A value set in the Port 1 data register (PDR1) is maintained, but not output to the pins.
• When the Port 1 data register (PDR1) is read, the input level value ("0" for "L" and "1" for "H") is read
out.
Note:
If read modify write (RMW) instructions (such as the bit set instruction) are used to access port 1
data register (PDR1), the bit set to output in port 1 direction register (DDR1) is not affected.
However, the bit set to input in port 1 direct register (DDR1) is written the value of pin input level to
port 1 data register (PDR1), therefore, when changing the bit set to input to output, port 1 data
register (PDR1) should be set to output after setting output value in port 1 data register (PDR1).
● Operation of segment power output
• When using as a segment output pin, set "1" in the corresponding bit of the LCDC control register.
General-purpose input/output port is disabled and functions as the segment output pin.
● Operation when a reset is performed
• When the CPU is reset, the Port 1 direction register (DDR1) value is initialized to "00H" and the port 1
pin is placed in high-impedance state.
• As the Port 1 register (PDR1) is not initialized by reset, to use as an output port, set the output value in
the Port 1 data register (PDR1) and then set the Port 1 direction register (DDR1) for output.
● Operation in stop mode, timebase timer mode or watch mode
If "1" has been set in the pin state setup bit (SPL) of the low-power consumption mode control register
(LPMCR) when transiting to stop mode, timebase timer mode, or watch mode, the pin is put in highimpedance state regardless of the value of the Port 1 direction register (DDR1). In addition, the input buffer
is also unconditionally blocked to prevent leakage by input open.
When functioning as a segment output pin, the segment output state is maintained.
176
CHAPTER 8 I/O PORT
Table 8.4-4 State of Port 1 Pins
Pin name
Normal
operation
Sleep mode
Stop mode,
Timebase timer mode,
Watch mode
(SPL= 0)
Stop mode,
Timebase timer mode,
Watch mode
(SPL= 1)
P10 to P17
Input/Output
port
Input/Output
port
Input cutoff
level hold
Input cutoff/output Hi-Z
SEG20 to
SEG27
Segment
output
Segment
output
Segment output
Segment output
SPL: Pin state specification bit of low-power consumption mode control register (LPMCR: SPL)
Hi-Z: High impedance
177
CHAPTER 8 I/O PORT
8.5
Port 2
Port 2 is an input-output port. The configuration, block diagram of the pins and
registers for port 2 are shown below.
■ Configuration of Port 2
Port 2 is composed as follows.
• I/O pins/resource I/O pins (P20/SEG28 to P27/SEG35)
• Port 2 data register (PDR2)
• Port 2 direction register (DDR2)
■ A Pin at Port 2
Table 8.5-1 A Pin at Port 2
Port
name
Pin name
Port 2
P20/SEG28
P20
P21/SEG29
P21
P22/SEG30
P22
SEG30
P23/SEG31
P23
SEG31
P24/SEG32
P24
SEG32
P25/SEG33
P25
SEG33
P26/SEG34
P26
SEG34
P27/SEG35
P27
SEG35
Port function
I/O type
Resource function
Input
Input/
Output
port
SEG28
SEG29
LCD
segment
output
CMOS
(hysteresis)
Circuit
type
Output
CMOS
E
Reference:
For the circuit types, see "1.7 I/O Circuit Type".
■ Registers for Port 2
The registers for port 2 are port 2 data register (PDR2) and port 2 direction register (DDR2). Bits of each
register have one-to-one correspondence with pins of port 2.
Table 8.5-2 The Correspondence between the Registers and Pins of Port 2.
Port
name
Port 2
178
Bits of related registers and corresponding pins
PDR2, DDR2
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Corresponding pin
P27
P26
P25
P24
P23
P22
P21
P20
CHAPTER 8 I/O PORT
8.5.1
Registers for Port 2 (PDR2, DDR2)
The registers for port 2 are explained.
■ Function of Registers for Port 2
● Port 2 data register (PDR2)
The output value of each terminal of port 2 is set.
● Port 2 direction register (DDR2)
Sets the input/output direction for each pin of port 2.
The pin becomes an output port when "1" is set in the bit corresponding to the pin and becomes an input
port when "0" is set.
Table 8.5-3 Function of Registers for Port 2
At read
Register
name
Port 2 data
register
(PDR2)
Port 2
direction
register
(DDR2)
At write
Address
Bit value
Output
port
Input port
Output port
Input port
0
Pin state is
"L" level
"0" is set to
the bit of
the PDR2
register.
"0" is set to
the bit of
the
PDR2
register.
"L" level is
output
from the
terminal.
1
Pin state is
"H" level
"1" is set to
the bit of
the PDR2
register.
"1" is set to
the bit of
the
PDR2
register.
"H" level is
output
from the
terminal.
0
"0" is set to the bit of the
DDR2 register.
Input port
1
"1" is set to the bit of the
DDR2 register.
Output port
Initial value
000002H
XXXXXXXXB
000012H
00000000B
X: Indefinite
179
CHAPTER 8 I/O PORT
8.5.2
Operation of Port 2
The operation of port 2 is explained.
■ Operation of Port 2
● When output port is set by port 2 direction register (DDR2)
• The value set in the port 2 data register (PDR2) is output to the port 2 pins.
• When the port 2 data register (PDR2) is read, the value set in the port 2 data register (PDR2) is read out.
● When input port is set in port 2 direction register (DDR2)
• The port 2 pin enters a high impedance state.
• A value set in the port 2 data register (PDR2) is maintained, but not output to the pins.
• When the port 2 data register (PDR2) is read, the input level value ("0" for "L" and "1" for "H") is read
out.
Note:
If read modify write (RMW) instructions (such as the bit set instruction) are used to access port 2
data register (PDR2), the bit set to output in port 2 direction register (DDR2) is not affected.
However, the bit set to input in port 2 direct register (DDR2) is written the value of pin input level to
port 2 data register (PDR2), therefore, when changing the bit set to input to output, port 2 data
register (PDR2) should be set to output after setting output value in port 2 data register (PDR2).
● Operation of segment power output
• When using as a segment output pin, set "1" in the corresponding bit of the LCDC control register.
General-purpose input/output port is disabled and functions as the segment output pin.
● Operation when a reset is performed
• When the CPU is reset, the port 2 direction register (DDR2) value is initialized to "00H" and the port 2
pin is placed in high-impedance state.
• As the port 2 register (PDR2) is not initialized by reset, to use as an output port, set the output value in
the port 2 data register (PDR2) and then set the port 2 direction register (DDR2) for output.
● Operation in stop mode, timebase timer mode or watch mode
If "1" has been set in the pin state setup bit (SPL) of the low-power consumption mode control register
(LPMCR) when transiting to stop mode, timebase timer mode, or watch mode, the pin is put in highimpedance state regardless of the value of the port 2 direction register (DDR2). In addition, the input buffer
is also unconditionally blocked to prevent leakage by input open.
When functioning as a segment output pin, the segment output state is maintained.
180
CHAPTER 8 I/O PORT
Table 8.5-4 The State of the Port 2 Pins
Pin name
Normal
operation
Sleep mode
Stop mode,
Timebase timer mode,
Watch mode
(SPL= 0)
Stop mode,
Timebase timer mode,
Watch mode
(SPL= 1)
P20 to P27
Input/Output
port
Input/Output
port
Input cutoff
level hold
Input cutoff/output Hi-Z
SEG28 to
SEG35
Segment
output
Segment
output
Segment output
Segment output
SPL: Pin state specification bit of low-power consumption mode control register (LPMCR: SPL)
Hi-Z: High impedance
181
CHAPTER 8 I/O PORT
8.6
Port 3
Port 3 is an input-output port. The configuration, block diagram of the pins and
registers for port 3 are shown below.
■ Configuration of Port 3
Port 3 is composed as follows.
• I/O pins/resource I/O pins (P30/SEG36/SO3 to P37/SEG43/OCU1)
• Port 3 data register (PDR3)
• Port 3 direction register (DDR3)
■ A Pin at Port 3
Table 8.6-1 A Pin at Port 3
I/O type
Port
name
Port 3
Pin name
Port function
Resource function
Input
P30/SEG36/SO3
P31/SEG37/SC3
P32/SEG38/SI3
P30
P31
P32
P33/SEG39/TMCK P33
P34/SEG40/IC0
P35/SEG41/IC1
P36/SEG42/OCU0
P37/SEG43/OCU1
P34
P35
P36
P37
I/O
port
SEG36
LCD segment output
SO3
Serial I/O ch.3 data output
SEG37
LCD segment output
SC3
Serial I/O ch.3 clock I/O
SEG38
LCD segment output
SI3
Serial I/O ch.3 data input
SEG39
LCD segment output
TMCK
Watch clock output
SEG40
LCD segment output
IC0
Input capture 0 input
SEG41
LCD segment output
IC1
Input capture 1 input
SEG42
LCD segment output
OCU0
Output compare 0 output
SEG43
LCD segment output
OCU1
Output compare 1 output
Reference:
For the circuit types, see "1.7 I/O Circuit Type".
182
Output
CMOS
CMOS
(hysteresis)
Circuit
type
E
CHAPTER 8 I/O PORT
■ Registers for Port 3
The registers for port 3 are port 3 data register (PDR3) and port 3 direct register (DDR3). Bits of each
register have one-to-one correspondence with pins of port 3.
Table 8.6-2 Correspondence between Registers and Pins for Port 3
Port
name
Port 3
Bits of related registers and corresponding pins
PDR3, DDR3
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Corresponding pin
P37
P36
P35
P34
P33
P32
P31
P30
183
CHAPTER 8 I/O PORT
8.6.1
Registers for Port 3 (PDR3, DDR3)
The registers for port 3 are explained.
■ Function of Registers for Port 3
● Port 3 data register (PDR3)
The output value of each terminal of port 3 is set.
● Port 3 direction register (DDR3)
Sets the input/output direction for each pin of port 3.
The pin becomes an output port when "1" is set in the bit corresponding to the pin and becomes an input
port when "0" is set.
Table 8.6-3 Function of Registers for Port 3
Register
name
Input port
184
Input port
Address
Initial value
Output port
"0" is set to
the bit of the
PDR3 register.
"0" is set to
"L" level is
the bit of the
output from
PDR3 register. the terminal.
1
Pin state is
"H" level
"1" is set to
the bit of the
PDR3 register.
"1" is set to
"H" level is
the bit of the
output from
PDR3 register. the terminal.
0
"0" is set to the bit of the
DDR3 register.
1
"1" is set to the bit of the
DDR3 register.
Port 3 data
register
(PDR3)
X: Indefinite
Output port
At write
Pin state is
"L" level
0
Port 3
direction
register
(DDR3)
At read
Bit value
000003H
XXXXXXXXB
000013H
00000000B
Input port
Output port
CHAPTER 8 I/O PORT
8.6.2
Operation of Port 3
The operation of port 3 is explained.
■ Operation of Port 3
● When output port is set by port 3 direction register (DDR3)
• The value set in the port 3 data register (PDR3) is output to the port 3 pins.
• When the port 3 data register (PDR3) is read, the value set in the port 3 data register (PDR3) is read out.
● When input port is set in port 3 direction register (DDR3)
• The port 3 pin enters a high impedance state.
• A value set in the port 3 data register (PDR3) is maintained, but not output to the pins.
• When the port 3 data register (PDR3) is read, the input level value ("0" for "L" and "1" for "H") is read
out.
Note:
If read modify write (RMW) instructions (such as the bit set instruction) are used to access port 3
data register (PDR3), the bit set to output in port 3 direction register (DDR3) is not affected.
However, the bit set to input in port 3 direct register (DDR3) is written the value of pin input level to
port 3 data register (PDR3), therefore, when changing the bit set to input to output, port 3 data
register (PDR3) should be set to output after setting output value in port 3 data register (PDR3).
● Operation of segment output
When using as a segment output pin, set "1" in the corresponding bit of the LCDC control register.
General-purpose input/output port and peripheral input/output pin are disabled and functions as the segment
output pin.
● Operation when a reset is performed
• When the CPU is reset, the port 3 direction register (DDR3) value is initialized to "00H" and the port 3
pin is placed in high-impedance state.
• As the port 3 register (PDR3) is not initialized by reset, to use as an output port, set the output value in
the port 3 data register (PDR3) and then set the port 3 direction register (DDR3) for output.
185
CHAPTER 8 I/O PORT
● Operation in stop mode, timebase timer mode or watch mode
If "1" has been set in the pin state setup bit (SPL) of the low-power consumption mode control register
(LPMCR) when transiting to stop mode, timebase timer mode, or watch mode, the pin is put in highimpedance state regardless of the value of the port 3 direction register (DDR3). In addition, the input buffer
is also unconditionally blocked to prevent leakage by input open.
When functioning as a segment output pin, the segment output state is maintained.
Table 8.6-4 The State of the Port 3 Pins
Sleep mode
Stop mode,
Timebase timer mode,
Watch mode
(SPL= 0)
Stop mode,
Timebase timer mode,
Watch mode
(SPL= 1)
Pin name
Normal
operation
P30 to P37
Input/Output
port
Input/Output
port
Input cutoff
level hold
Input cutoff/output Hi-Z
SEG36 to
SEG43
Segment
output
Segment
output
Segment output
Segment output
SPL: Pin state specification bit of low-power consumption mode control register (LPMCR: SPL)
Hi-Z: High impedance
186
CHAPTER 8 I/O PORT
8.7
Port 4
Port 4 is an input-output port. The configuration, block diagram of the pins and
registers for port 4 are shown below.
■ Configuration of Port 4
Port 4 is composed as follows.
• I/O pins/resource I/O pins (P40/LED0 to P47/LED7/TOT2)
• Port 4 data register (PDR4)
• Port 4 direction register (DDR4)
■ A Pin at Port 4
Table 8.7-1 A Pin at Port 4
Port
name
Port 4
Pin name
I/O type
Port
function
P40/LED0
P40
P41/LED1
P41
P42/LED2
P42
P43/LED3
P43
P44/LED4
P44
P45/LED5/TOT0
Resource function
I/O
port
-
-
P45
TOT0
Reload timer 0 event output
P46/LED6/TOT1
P46
TOT1
Reload timer 1 event output
P47/LED7/TOT2
P47
TOT2
Reload timer 2 event output
Input
Output
CMOS
(hysteresis)
CMOS
Circuit
type
F
Reference:
For the circuit types, see "1.7 I/O Circuit Type".
■ Registers for Port 4
The registers for port 4 are port 4 data register (PDR4) and port 4 direct register (DDR4). Bits of each
register have one-to-one correspondence with pins of port 4.
Table 8.7-2 Correspondence between Registers and Pins for Port 4
Port
name
Port 4
Bits of related registers and corresponding pins
PDR4, DDR4
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Corresponding pin
P47
P46
P45
P44
P43
P42
P41
P40
187
CHAPTER 8 I/O PORT
8.7.1
Registers for Port 4 (PDR4, DDR4)
The registers for port 4 are explained.
■ Function of Registers for Port 4
● Port 4 data register (PDR4)
The output value of each terminal of port 4 is set.
● Port 4 direction register (DDR4)
Sets the input/output direction for each pin of port 4.
The pin becomes an output port when "1" is set in the bit corresponding to the pin and becomes an input
port when "0" is set.
Table 8.7-3 Function of Registers for Port 4
Register
name
At read
Address
Input port
Output port
Input port
Output port
Pin state is
"L" level
"0" is set
to the bit
of the
PDR4
register.
"0" is set
to the bit
of the
PDR4
register.
"L" level
is output
from the
terminal.
1
Pin state is
"H" level
"1" is set
to the bit
of the
PDR4
register.
"1" is set
to the bit
of the
PDR4
register.
0
"0" is set to the bit of the
DDR4 register.
1
"1" is set to the bit of the
DDR4 register.
0
Port 4 data
register
(PDR4)
Port 4
direction
register
(DDR4)
X: Indefinite
188
At write
Bit value
Initial value
000004H
XXXXXXXXB
000014H
00000000B
"H" level
is output
from the
terminal.
Input port
Output port
CHAPTER 8 I/O PORT
8.7.2
Operation of Port 4
The operation of port 4 is explained.
■ Operation of Port 4
● When output port is set by port 4 direction register (DDR4)
• The value set in the port 4 data register (PDR4) is output to the port 4 pins.
• When the port 4 data register (PDR4) is read, the value set in the port 4 data register (PDR4) is read out.
● When input port is set in port 4 direction register (DDR4)
• The port 4 pin enters a high impedance state.
• A value set in the port 4 data register (PDR4) is maintained, but not output to the pins.
• When the port 4 data register (PDR4) is read, the input level value ("0" for "L" and "1" for "H") is read
out.
Note:
If read modify write (RMW) instructions (such as the bit set instruction) are used to access port 4
data register (PDR4), the bit set to output in port 4 direction register (DDR4) is not affected.
However, the bit set to input in port 4 direct register (DDR4) is written the value of pin input level to
port 4 data register (PDR4), therefore, when changing the bit set to input to output, port 4 data
register (PDR4) should be set to output after setting output value in port 4 data register (PDR4).
● Operation of LED output
• When using as an LED output pin, set an output in the port 4 direction register (DDR4).
• The value set in the port 4 data register (PDR4) is output to the port 4 pin to allow LED ON/OFF
control.
● Operation when a reset is performed
• When the CPU is reset, the port 4 direction register (DDR4) value is initialized to "00H" and the port 4
pin is placed in high-impedance state.
• As the port 4 data register (PDR4) is not initialized by reset, to use as an output port, set the output value
in the port 4 data register (PDR4) and then set the port 4 direction register (DDR4) for output.
● Operation in stop mode, timebase timer mode or watch mode
If "1" has been set in the pin state setup bit (SPL) of the low-power consumption mode control register
(LPMCR) when transiting to stop mode, timebase timer mode, or watch mode, the pin is put in highimpedance state regardless of the value of the port 4 direction register (DDR4). In addition, the input buffer
is also unconditionally blocked to prevent leakage by input open.
189
CHAPTER 8 I/O PORT
Table 8.7-4 The state of the port 4 pins
Pin name
P40 to P47
Normal
operation
Input/Output
port
Sleep mode
Stop mode,
Timebase timer mode,
Watch mode
(SPL= 0)
Stop mode,
Timebase timer mode,
Watch mode
(SPL= 1)
Input/Output
port
Input cutoff
level hold
Input cutoff/output Hi-Z
SPL: Pin state specification bit of low-power consumption mode control register (LPMCR: SPL)
Hi-Z: High impedance
190
CHAPTER 8 I/O PORT
8.8
Port 5
Port 5 is an input-output port. The configuration, block diagram of the pins and
registers for port 5 are shown below.
■ Configuration of Port 5
Port 5 is composed as follows.
• I/O pins/resource I/O pins (P50/SEG44/TIN0 to P57/SI1)
• Port 5 data register (PDR5)
• Port 5 direction register (DDR5)
■ A Pin at Port 5
Table 8.8-1 A Pin at Port 5
I/O type
Port
name
Port 5
Pin name
Port function
Resource function
Input
P50/SEG44/TIN0
P51/SEG45/TIN1
P50
P51
P52/ SEG 46/ TIN2 / P52
PPG0
P53/SEG47/PPG1
P53
I/O
port
SEG44
LCD segment output
TIN0
Reload timer 0 event input
SEG45
LCD segment output
TIN1
Reload timer 1 event input
SEG46
LCD segment output
TIN2
Reload timer 2 event input
PPG0
PPG timer 0 output
SEG47
LCD segment output
PPG1
PPG timer 1 output
P54/SI0
P54
SI0
UART ch.0 data input
P55/SC0
P55
SC0
UART ch.0 clock I/O
P56/SO0
P56
SO0
UART ch.0 data output
P57/SI1
P57
SI1
UART ch.1 data input
CMOS
(hysteresis)
Output
CMOS
Circuit
type
E
G
Reference:
For the circuit types, see "1.7 I/O Circuit Type".
191
CHAPTER 8 I/O PORT
■ Registers for Port 5
The registers for port 5 are port 5 data register (PDR5) and port 5 direct register (DDR5). Bits of each
register have one-to-one correspondence with pins of port 5.
Table 8.8-2 Correspondence between Registers and Pins for Port 5
Port
name
Port 5
192
Bits of related registers and corresponding pins
PDR5, DDR5
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Corresponding pin
P57
P56
P55
P54
P53
P52
P51
P50
CHAPTER 8 I/O PORT
8.8.1
port 5 Registers (PDR5, DDR5)
The registers for port 5 are explained.
■ Function of Registers for Port 5
● Port 5 data register (PDR5)
The output value of each terminal of port 5 is set.
● Port 5 direction register (DDR5)
Sets the input/output direction for each pin of port 5.
The pin becomes an output port when "1" is set in the bit corresponding to the pin and becomes an input
port when "0" is set.
Table 8.8-3 Function of Registers for Port 5
Register
name
At read
0
Address
Input port
Output port
Input port
Output port
Pin state is
"L" level
"0" is set
to the bit of
the PDR5
register.
"0" is set
to the bit
of the
PDR5
register.
"L" level
is output
from the
terminal.
"1" is set to
the bit of the
PDR5
register.
"1" is set
to the bit
of the
PDR5
register.
Port 5 data
register
(PDR5)
Port 5
direction
register
(DDR5)
At write
Bit value
1
Pin state is
"H" level
0
"0" is set to the bit of the
DDR5 register.
1
"0" is set to the bit of the
DDR5 register.
Initial value
000005H
XXXXXXXXB
000015H
00000000B
"H" level
is output
from the
terminal.
Input port
Output port
X: Indefinite
193
CHAPTER 8 I/O PORT
8.8.2
Operation of Port 5
The operation of port 5 is explained.
■ Operation of Port 5
● When output port is set by port 5 direction register (DDR5)
• The value set in the port 5 data register (PDR5) is output to the port 5 pins.
• When the port 5 data register (PDR5) is read, the value set in the port 5 data register (PDR5) is read out.
● When input port is set in port 5 direction register (DDR5)
• The port 5 pin enters a high impedance state.
• A value set in the port 5 data register (PDR5) is maintained, but not output to the pins.
• When the port 5 data register (PDR5) is read, the input level value ("0" for "L" and "1" for "H") is read out.
Note:
If read modify write (RMW) instructions (such as the bit set instruction) are used to access port 5
data register (PDR5), the bit set to output in port 5 direction register (DDR5) is not affected.
However, the bit set to input in port 5 direct register (DDR5) is written the value of pin input level to
port 5 data register (PDR5), therefore, when changing the bit set to input to output, port 5 data
register (PDR5) should be set to output after setting output value in port 5 data register (PDR5).
● Operation of segment output
• When using as a segment output pin, set "1" in the corresponding bit of the LCDC control register.
General-purpose input/output port and peripheral input/output pin are disabled and functions as the
segment output pin.
● Operation when a reset is performed
• When the CPU is reset, the port 5 direction register (DDR5) value is initialized to "00H" and the port 5
pin is placed in high-impedance state.
• As the port 5 register (PDR5) is not initialized by reset, to use as an output port, set the output value in
the port 5 data register (PDR5) and then set the port 5 direction register (DDR5) for output.
● Operation in stop mode, timebase timer mode or watch mode
If "1" has been set in the pin state setup bit (SPL) of the low-power consumption mode control register
(LPMCR) when transiting to stop mode, timebase timer mode, or watch mode, the pin is put in highimpedance state regardless of the value of the port 5 direction register (DDR5). In addition, the input buffer
is also unconditionally blocked to prevent leakage by input open.
When functioning as a segment output pin, the segment output state is maintained.
194
CHAPTER 8 I/O PORT
Table 8.8-4 The State of the Port 5 Pins
Pin name
Normal
operation
Sleep mode
Stop mode,
Timebase timer mode,
Watch mode
(SPL= 0)
Stop mode,
Timebase timer mode,
Watch mode
(SPL= 1)
P50 to P57
Input/Output
port
Input/Output
port
Input cutoff
level hold
Input cutoff/output Hi-Z
SEG44 to
SEG47
Segment output
Segment output
Segment output
Segment output
SPL: Pin state specification bit of low-power consumption mode control register (LPMCR: SPL)
Hi-Z: High impedance
195
CHAPTER 8 I/O PORT
8.9
Port 6
Port 6 is an input-output port. The configuration, block diagram of the pins and
registers for port 6 are shown below.
■ Configuration of Port 6
Port 6 is composed as follows.
• I/O pins/resource I/O pins (P60/AN0 to P67/AN7/INT2)
• Port 6 data register (PDR6)
• Port 6 direction register (DDR6)
• Analog input enable register 0 (ADER0)
■ A Pin at Port 6
Table 8.9-1 A Pin at Port 6
I/O type
Port
name
Pin
name
Port 6
P60/AN0
P60
P61/AN1
P61
P62/AN2
Port function
I/O
port
Resource function
AN0
Analog input
AN1
Analog input
P62
AN2
Analog input
P63/AN3
P63
AN3
Analog input
P64/AN4
P64
AN4
Analog input
P65/AN5/
INT0
P65
AN5
Analog input
INT0
DTP/external interrupt input
P66/AN6/
INT1
P66
AN6
Analog input
INT1
DTP/external interrupt input
P67/AN7/
INT2
P67
AN7
Analog input
INT2
DTP/external interrupt input
Input
Output
CMOS
(hysteresis)
CMOS
Circuit
type
I
Reference:
For the circuit types, see "1.7 I/O Circuit Type".
Note:
When using as an input port, set "0" in the corresponding bit of the port 6 direction register (DDR6)
and "0" in the related bit of the analog input enable register 0 (ADER0).
When using as an analog input port, set "0" in the corresponding bit of the port 6 direction register
(DDR6) and "1" in the related bit of the analog input enable register 0 (ADER0).
196
CHAPTER 8 I/O PORT
■ Port 6 Registers
The registers for port 6 are port 6 data register (PDR6) and port 6 direct register (DDR6). Bits of each
register have one-to-one correspondence with pins of port 6.
Table 8.9-2 Relation between Port 6 Registers and Pins
Port
name
Port 6
Bits of related registers and corresponding pins
PDR6, DDR6
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Corresponding pin
P67
P66
P65
P64
P63
P62
P61
P60
197
CHAPTER 8 I/O PORT
8.9.1
Port 6 Registers (PDR6, DDR6)
The registers for port 6 are explained.
■ Port 6 Register Function
● Port 6 data register (PDR6)
The output value of each terminal of port 6 is set.
● Port 6 direction register (DDR6)
Sets the input/output direction for each pin of port 6.
● The pin becomes an output port when "1" is set in the bit corresponding to the pin and becomes an
input port when "0" is set.
● Analog input enable register 0 (ADER0)
Input/output port and A/D converter analog input can be set for each pin. The port is set as A/D converter
analog input when "1" is set in the bit corresponding to the port (pin) and input/output port when "0" is set.
Note:
When an input/output port is set, input of an intermediate-level signal causes input leakage current to
flow; therefore, for A/D converter analog input, be sure to set the corresponding bit of the analog
input enable register 0 (ADER0) to A/D converter analog input.
Reference
By reset, the port 6 direction register (DDR6) is initialized to "00H" and the analog input enable
register 0 (ADER0) is initialized to "FFH" to set the A/D converter analog input.
198
CHAPTER 8 I/O PORT
Table 8.9-3 Port 6 Register Function
Register
name
At write
Bit value
At read
Output port
Pin state is
"L" level
"0" is set
to the bit
of the
PDR6
register.
"0" is set
to the bit
of the
PDR6
register.
"L" level
is output
from the
terminal.
1
Pin state is
"H" level
"1" is set
to the bit
of the
PDR6
register.
"1" is set
to the bit
of the
PDR6
register.
0
"0" is set to the bit of the
DDR6 register.
1
"1" is set to the bit of the
DDR6 register.
Output port
0
"0" is set to the bit of
the ADER0 register.
Input/Output port
1
"1" is set to the bit of the
ADER0 register.
A/D converter analog
input 0 to 7
0
Port 6 data
register
(PDR6)
Port 6
direction
register
(DDR6)
Analog input
enable
register 0
(ADER0)
Address
Input port
Initial value
000006H
XXXXXXXXB
000016H
00000000B
00001EH
11111111B
"H" level
is output
from the
terminal.
Input port
X: Indefinite
199
CHAPTER 8 I/O PORT
8.9.2
Operation of Port 6
The operation of port 6 is explained.
■ Operation of Port 6
● When output port is set in port 6 direction register (DDR6) and analog input enable register 0 (ADER0)
• The value set in the port 6 data register (PDR6) is output to the port 6 pins.
• When the port 6 data register (PDR6) is read, the value set in the port 6 data register (PDR6) is read out.
● When input port is set in port 6 direction register (DDR6) and analog input enable register 0 (ADER0)
• The port 6 pin enters a high impedance state.
• A value set in the port 6 data register (PDR6) is maintained, but not output to the pins.
• When the port 6 data register (PDR6) is read, the input level value ("0" for "L" and "1" for "H") is read out.
Note:
If read modify write (RMW) instructions (such as the bit set instruction) are used to access port 6
data register (PDR6), the bit set to output in port 6 direction register (DDR6) is not affected.
However, the bit set to input in port 6 direct register (DDR6) is written the value of pin input level to
port 6 data register (PDR6), therefore, when changing the bit set to input to output, port 6 data
register (PDR6) should be set to output after setting output value in port 6 data register (PDR6).
● When setting A/D converter analog input
When using as the A/D converter analog input, set "1" in the bit of the analog input enable register 0
(ADER0) corresponding to the A/D converter analog input pin. When A/D converter analog input has been
set, reading the corresponding bit in PDR causes value "0" to be read out.
● Operation when a reset is performed
• By CPU reset, the port 6 direction register (DDR6) is initialized to "00H" and the analog input enable
register 0 (ADER0) is initialized to "FFH" to set the A/D converter analog input. When using as an
input/output port, set "00H" in the analog input enable register 0 (ADER0) to set port input/output mode.
• As the port 6 register (PDR6) is not initialized by reset, to use as an output port, set the output value in
the port 6 data register (PDR6) and then set the port 6 direction register (DDR6) for output.
● Operation in stop mode, timebase timer mode or watch mode
If "1" has been set in the pin state setup bit (SPL) of the low-power consumption mode control register
(LPMCR) when transiting to stop mode, timebase timer mode, or watch mode, the pin is put in highimpedance state regardless of the value of the port 6 direction register (DDR6). In addition, the input buffer
is also unconditionally blocked to prevent leakage by input open.
200
CHAPTER 8 I/O PORT
Table 8.9-4 Port 6 Pin Status
Stop mode,
Timebase timer mode,
Watch mode
(SPL= 0)
Stop mode,
Timebase timer mode,
Watch mode
(SPL= 1)
Pin name
Normal
operation
Sleep
mode
P60 to P67
Input/
Output port
Input/
Output port
A/D
converter
analog
input
Input cutoff
level hold
Input cutoff/output Hi-Z
AN0 to
AN7
A/D
converter
analog
input
INT0 to
INT2
External
Interrupt
request
External
Interrupt
request
Input cutoff/output hold
When external interrupt is enable,
input is enable.
Input cutoff/output Hi-Z
When external interrupt is enable,
input is enable.
SPL: Pin state specification bit of low-power consumption mode control register (LPMCR: SPL)
Hi-Z: High impedance
201
CHAPTER 8 I/O PORT
8.10
Port 7
Port 7 is an input-output port. The configuration, block diagram of the pins and
registers for port 7 are shown below.
■ Configuration of Port 7
Port 7 is composed as follows.
• I/O pins/resource I/O pins (P70/AN8/INT3 to P76)
• Port 7 data register (PDR7)
• Port 7 direction register (DDR7)
• Analog input enable register 1 (ADER1)
■ A Pin at Port 7
Table 8.10-1 A Pin at Port 7
Port
name
Port 7
Pin
name
I/O type
Port function
Resource function
Input
P70/AN8/
INT3
P70
P71/AN9/
SC1
P71
P72/AN10/
SO1
P72
P73/AN11/
SI2
P73
P74/SDA/
SC2
P74
P75/SCL/
SO2
P75
P76
P76
I/O
port
AN8
Analog input
INT3
DTP/external interrupt input
AN9
Analog input
SC1
UART ch.1 clock I/O
AN10
Analog input
SO1
UART ch.1 data output
AN11
Analog input
SI2
Serial I/O ch.2 data input
SDA
I2 C
SC2
Serial I/O ch.2 clock I/O
SCL
I2C
SO2
Serial I/O ch.2 data output
-
Reference
For the circuit types, see "1.7 I/O Circuit Type".
202
-
CMOS
(hysteresis)
Output
Circuit
type
CMOS
I
N-ch
Open
drain
H
CMOS
G
CHAPTER 8 I/O PORT
Note:
When using as an input port, set "0" in the corresponding bit of the port 7 direction register (DDR7)
and "0" in the related bit of the analog input enable register 1 (ADER1).
When using as an analog input port, set "0" in the corresponding bit of the port 7 direction register
(DDR7) and "1" in the related bit of the analog input enable register 1 (ADER1).
■ Port 7 Registers
The registers for port 7 are port 7 data register (PDR7) and port 7 direct register (DDR7). Bits of each
register have one-to-one correspondence with pins of port 7.
Table 8.10-2 Relation between Port 7 Registers and Pins
Port
name
Port 7
Bits of related registers and corresponding pins
PDR7, DDR7
Corresponding pin
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
-
P76
P75
P74
P73
P72
P71
P70
203
CHAPTER 8 I/O PORT
8.10.1
Port 7 Registers (PDR7, DDR7)
The registers for port 7 are explained.
■ Port 7 Register Function
● Port 7 data register (PDR7)
The output value of each terminal of port 7 is set.
● Port 7 direction register (DDR7)
Sets the input/output direction for each pin of port 7.
● The pin becomes an output port when "1" is set in the bit corresponding to the pin and becomes an
input port when "0" is set.
● Analog input enable register 1 (ADER1)
Input/output port and A/D converter analog input can be set for each pin. The port is set as A/D converter
analog input when "1" is set in the bit corresponding to the port (pin) and input/output port when "0" is set.
Note:
When an input/output port is set, input of an intermediate-level signal causes input leakage current to
flow; therefore, for A/D converter analog input, be sure to set the corresponding bit of the analog
input enable register 1 (ADER1) to A/D converter analog input.
Reference
By reset, the port 7 direction register (DDR7) is initialized to "00H" and the analog input enable
register 1 (ADER1) is initialized to "FFH" to set the A/D converter analog input.
204
CHAPTER 8 I/O PORT
Table 8.10-3 Port 7 Register Function
Register
name
At read
0
Address
Input port
Output port
Input port
Output port
Pin state is
"L" level
"0" is set
to the bit of
the PDR7
register.
"0" is set
to the bit
of the
PDR7
register.
"L" level
is output
from the
terminal.
"1" is set
to the bit of
the PDR7
register.
"1" is set
to the bit
of the
PDR7
register.
Port 7 data
register
(PDR7)
Port 7
direction
register
(DDR7)
Analog input
enable
register 1
(ADER1)
At write
Bit value
Initial value
000007H
-XXXXXXXB
000017H
-0000000B
00001FH
----1111B
"H" level
is output
from the
terminal.
1
Pin state is
"H" level
0
"0" is set to the bit of the
DDR7 register.
1
"1" is set to the bit of the
DDR7 register.
Output port
0
"0" is set to the bit of the
ADER1 register.
Input/Output port
1
"1" is set to the bit of the
ADER1 register.
A/D converter analog
input 8 to 11
Input port
X: Indefinite
205
CHAPTER 8 I/O PORT
8.10.2
Operation of Port 7
The operation of port 7 is explained.
■ Operation of Port 7
● When output port is set in port 7 direction register (DDR7) and analog input enable register 1 (ADER1)
• The value set in the port 7 data register (PDR7) is output to the port 7 pins.
• When the port 7 data register (PDR7) is read, the value set in the port 7 data register (PDR7) is read out.
● When input port is set in port 7 direction register (DDR7) and analog input enable register 1 (ADER1)
• The port 7 pin enters a high impedance state.
• A value set in the port 7 data register (PDR7) is maintained, but not output to the pins.
• When the port 7 data register (PDR7) is read, the input level value ("0" for "L" and "1" for "H") is read
out.
Note:
If read modify write (RMW) instructions (such as the bit set instruction) are used to access port 7
data register (PDR7), the bit set to output in port 7 direction register (DDR7) is not affected.
However, the bit set to input in port 7 direct register (DDR7) is written the value of pin input level to
port 7 data register (PDR7), therefore, when changing the bit set to input to output, port 7 data
register (PDR7) should be set to output after setting output value in port 7 data register (PDR7).
● When setting A/D converter analog input
When using as the A/D converter analog input, set "1" in the bit of the analog input enable register 1
(ADER1) corresponding to the A/D converter analog input pin. When A/D converter analog input has been
set, reading the corresponding bit in DDR causes value "0" to be read out.
● Operation when a reset is performed
• By CPU reset, the port 7 direction register (DDR7) is initialized to "00H" and the analog input enable
register 1 (ADER1) is initialized to "FFH" to set the A/D converter analog input. When using P70 to P73
as the input/output ports, set "00H" in the analog input enable register 1 (ADER1) to set port input/
output mode.
• As the port 7 register (PDR7) is not initialized by reset, to use as an output port, set the output value in
the port 7 data register (PDR7) and then set the port 7 direction register (DDR7) for output.
● Operation in stop mode, timebase timer mode or watch mode
If "1" has been set in the pin state setup bit (SPL) of the low-power consumption mode control register
(LPMCR) when transiting to stop mode, timebase timer mode, or watch mode, the pin is put in high-
206
CHAPTER 8 I/O PORT
impedance state regardless of the value of the port 7 direction register (DDR7). In addition, the input buffer
is also unconditionally blocked to prevent leakage by input open.
Table 8.10-4 Port 7 Pin Status
Pin name
Normal
operation
Sleep
mode
P70 to P76
Input/
Output
port
Input/
Output
port
AN8 to
AN11
A/D
converter
analog
input
A/D
converter
analog
input
INT3
External
Interrupt
request
External
Interrupt
request
Stop mode,
Timebase timer mode,
Watch mode
(SPL= 0)
Stop mode,
Timebase timer mode,
Watch mode
(SPL= 1)
Input cutoff
level hold
Input cutoff/
Output Hi-Z
Input cutoff/
Output hold
Input cutoff/
Output Hi-Z
[When external interrupt is enable, input is
enable.]
[When external interrupt is enable, input is
enable.]
SPL: Pin state specification bit of low-power consumption mode control register (LPMCR: SPL)
Hi-Z: High impedance
207
CHAPTER 8 I/O PORT
8.11
Port 8
Port 8 is an input-output port. The configuration, block diagram of the pins and
registers for port 8 are shown below.
■ Configuration of Port 8
Port 8 is composed as follows.
• I/O pins/resource I/O pins (P80/V0 to P84/COM3)
• Port 8 data register (PDR8)
• Port 8 direction register (DDR8)
■ A Pin at Port 8
Table 8.11-1 A Pin at Port 8
I/O type
Port
name
Pin name
Port 8
P80/V0
P80
P81/V1
P81
P82/V2
P82
V2
P83/COM2
P83
COM2
P84/COM3
P84
COM3
Port function
Input
Input/
Output
port
Circuit
type
Resource function
V0
V1
LCD voltage
input
LCD common
power output
CMOS
(hysteresis)
Output
CMOS
J
E
Reference
For the circuit types, see "1.7 I/O Circuit Type".
Note:
When using P80 to P82 as the input/output ports, set "1" in the VS0 bit of the LCDC control register
(LCRH).
When using P83 and P84 as the input/output ports, set "00B" in the CS1:CS0 bits of the LCDC
control register (LCRH).
By CPU reset, the port 8 direction register (DDR8) is initialized to "00H" and pins P80 to P82 are set
as LCD power input.
208
CHAPTER 8 I/O PORT
■ Port 8 Registers
The registers for port 8 are port 8 data register (PDR8) and port 8 direct register (DDR8). Bits of each
register have one-to-one correspondence with pins of port 8.
Table 8.11-2 Relation between Port 8 Registers and Pins
Port
name
Port 8
Bits of related registers and corresponding pins
PDR8, DDR8
-
-
-
bit4
bit3
bit2
bit1
bit0
Corresponding pin
-
-
-
P84
P83
P82
P81
P80
209
CHAPTER 8 I/O PORT
8.11.1
Port 8 Registers (PDR8, DDR8)
The registers for port 8 are explained.
■ Port 8 Register Function
● Port 8 data register (PDR8)
The output value of each terminal of port 8 is set.
● Port 8 direction register (DDR8)
Sets the input/output direction for each pin of port 8.
The pin becomes an output port when "1" is set in the bit corresponding to the pin and becomes an input
port when "0" is set.
Table 8.11-3 Port 8 Register Function
Register
name
At read
0
Address
Input port
Output port
Input port
Output port
Pin state is
"L" level
"0" is set
to the bit of
the PDR8
register.
"0" is set
to the bit
of the
PDR8
register.
"L" level
is output
from the
terminal.
"1" is set
to the bit of
the PDR8
register.
"1" is set
to the bit
of the
PDR8
register.
Port 8 data
register
(PDR8)
Port 8
direction
register
(DDR8)
X: Indefinite
210
At write
Bit value
1
Pin state is
"H" level
0
"0" is set to the bit of the
DDR8 register.
1
"1" is set to the bit of the
DDR8 register.
Initial value
000008H
---XXXXXB
000018H
---00000B
"H" level
is output
from the
terminal.
Input port
Output port
CHAPTER 8 I/O PORT
8.11.2
Operation of Port 8
The operation of port 8 is explained.
■ Operation of Port 8
● When output port is set by port 8 direction register (DDR8)
• The value set in the port 8 data register (PDR8) is output to the port 8 pins.
• When the port 8 data register (PDR8) is read, the value set in the port 8 data register (PDR8) is read out.
● When input port is set in port 8 direction register (DDR8)
• The port 8 pin enters a high impedance state.
• A value set in the port 8 data register (PDR8) is maintained, but not output to the pins.
• When the port 8 data register (PDR8) is read, the input level value ("0" for "L" and "1" for "H") is read
out.
Note:
If read modify write (RMW) instructions (such as the bit set instruction) are used to access port 8
data register (PDR8), the bit set to output in port 8 direction register (DDR8) is not affected.
However, the bit set to input in port 8 direct register (DDR8) is written the value of pin input level to
port 8 data register (PDR8), therefore, when changing the bit set to input to output, port 8 data
register (PDR8) should be set to output after setting output value in port 8 data register (PDR8).
● Operation of LCD power supply input
When using P80 to P82 as the LCD power input pins, set "0" in the VS0 bit of the LCDC control register
(LCRH). The general-purpose input/output port and peripheral input/output pin are disabled and functions
as the common output pin.
● Operation of common power output
When using P83 and P84 as common output, set value other than "00B" in the CS1 and CS0 bits of the
LCDC control register (LCRH). The general-purpose input/output port and peripheral input/output pin are
disabled and functions as the common output pin.
● Operation when a reset is performed
• By CPU reset, the port 8 direction register (DDR8) is initialized to "00H" and pins P80 to P82 are set as
LCD power input.
• Pins P83, P84 enter a high impedance state.
• As the port 8 register (PDR8) is not initialized by reset, to use as an output port, set the output value in
the port 8 data register (PDR8) and then set the port 8 direction register (DDR8) for output.
211
CHAPTER 8 I/O PORT
● Operation in stop mode, timebase timer mode or watch mode
If "1" has been set in the pin state setup bit (SPL) of the low-power consumption mode control register
(LPMCR) when transiting to stop mode, timebase timer mode, or watch mode, the pin is put in highimpedance state regardless of the value of the port 8 direction register (DDR8). In addition, the input buffer
is also unconditionally blocked to prevent leakage by input open.
When functioning as the LCD power input pin, the LCD power input state is maintained.
When functioning as the common output pin, the common output state is maintained.
Table 8.11-4 Port 8 Pin Status
Pin name
Normal
operation
Sleep mode
Stop mode,
Timebase timer mode,
Watch mode
(SPL= 0)
Stop mode,
Timebase timer mode,
Watch mode
(SPL= 1)
P80 to P84
Input/Output
port
Input/Output
port
Input cutoff/level hold
Input cutoff/output Hi-Z
V0 to V2
LCDC voltage
input
LCDC voltage
input
LCDC voltage
input
LCDC voltage
input
COM2, COM3
Common output
Common output
Common output
Common output
SPL: Pin state specification bit of low-power consumption mode control register (LPMCR: SPL)
Hi-Z: High impedance
212
CHAPTER 8 I/O PORT
8.12
Port 9
Port 9 is an input/output port, available only for a one clock system. The configuration,
block diagram of the pins and registers for port 9 are shown below.
■ Configuration of Port 9
Port 9 is composed as follows.
• I/O pins/resource I/O pins (P90, P91)
• Port 9 data register (PDR9)
• Port 9 direction register (DDR9)
■ A Pin at Port 9
Table 8.12-1 A Pin at Port 9
Port
name
Port 9
I/O type
Pin
name
P90
P91
Port function
Resource function
Input
P90
P91
I/O
port
-
Output
CMOS
(hysteresis)
-
CMOS
Circuit
type
G
Reference
For the circuit types, see "1.7 I/O Circuit Type".
■ Port 9 Registers
The registers for port 9 are port 9 data register (PDR9) and port 9 direct register (DDR9). Bits of each
register have one-to-one correspondence with pins of port 9.
Table 8.12-2 Relation between Port 9 Registers and Pins
Port
name
Port 9
Bits of related registers and corresponding pins
PDR9, DDR9
-
-
-
-
-
-
bit1
bit0
Corresponding pin
-
-
-
-
-
-
P91
P90
213
CHAPTER 8 I/O PORT
8.12.1
Port 9 Registers (PDR9, DDR9)
The registers for port 9 are explained.
■ Port 9 Register Function
● Port 9 data register (PDR9)
The output value of each terminal of port 9 is set.
● Port 9 direction register (DDR9)
Sets the input/output direction for each pin of port 9.
The pin becomes an output port when "1" is set in the bit corresponding to the pin and becomes an input
port when "0" is set.
Table 8.12-3 Port 9 Register Function
Register
name
At read
0
Address
Input port
Output port
Pin state is
"L" level
"0" is set to
the bit of the
PDR9
register.
"0" is set
to the bit
of the
PDR9
register.
"1" is set to
the bit of the
PDR9
register.
"1" is set
to the bit
of the
PDR9
register.
Port 9 data
register
(PDR9)
Port 9
direction
register
(DDR9)
X: Indefinite
214
At write
Bit value
1
Pin state is
"H" level
0
"0" is set to the bit of the
DDR9 register.
1
"1" is set to the bit of the
DDR9 register.
Input port
Output port
Initial
value
"L" level is
output from
the terminal.
000009H
------XXB
000019H
------00B
"H" level is
output from
the terminal.
Input port
Output port
CHAPTER 8 I/O PORT
8.12.2
Operation of Port 9
The operation of port 9 is explained.
■ Operation of Port 9
● When output port is set by port 9 direction register (DDR9)
• The value set in the port 9 data register (PDR9) is output to the port 9 pins.
• When the port 9 data register (PDR9) is read, the value set in the port 9 data register (PDR9) is read out.
● When input port is set in port 9 direction register (DDR9)
• The port 9 pin enters a high impedance state.
• A value set in the port 9 data register (PDR9) is maintained, but not output to the pins.
• When the port 9 data register (PDR9) is read, the input level value ("0" for "L" and "1" for "H") is read
out.
Note:
If read modify write (RMW) instructions (such as the bit set instruction) are used to access port 9
data register (PDR9), the bit set to output in port 9 direction register (DDR9) is not affected.
However, the bit set to input in port 9 direct register (DDR9) is written the value of pin input level to
port 9 data register (PDR9), therefore, when changing the bit set to input to output, port 9 data
register (PDR9) should be set to output after setting output value in port 9 data register (PDR9).
● Operation when a reset is performed
• When the CPU is reset, the port 9 direction register (DDR9) value is initialized to "00B" and the port 9
pin is placed in high-impedance state.
• As the port 9 data register (PDR9) is not initialized by reset, to use as an output port, set the output value
in the port 9 data register (PDR9) and then set the port 9 direction register (DDR9) for output.
● Operation in stop mode, timebase timer mode or watch mode
If "1" has been set in the pin state setup bit (SPL) of the low-power consumption mode control register
(LPMCR) when transiting to stop mode, timebase timer mode, or watch mode, the pin is put in highimpedance state regardless of the value of the port 9 direction register (DDR9). In addition, the input buffer
is also unconditionally blocked to prevent leakage by input open.
215
CHAPTER 8 I/O PORT
Table 8.12-4 Port 9 Pin Status
Pin name
P90, P91
Normal
operation
Input/Output
port
Sleep mode
Input/Output
port
Stop mode,
Timebase timer mode,
Watch mode
(SPL= 0)
Stop mode,
Timebase timer mode,
Watch mode
(SPL= 1)
Input cutoff/level hold
Input cutoff/output Hi-Z
SPL: Pin state specification bit of low-power consumption mode control register (LPMCR: SPL)
Hi-Z: High impedance
216
CHAPTER 8 I/O PORT
8.13
Example of Programming Input/Output Port
A program example using input/output ports is given below.
■ Example of Programming Input/Output Port
● Processing specification
• Ports 4 and 5 are used for turning on all of seven segments (eight segments including Dp) of LEDs.
• P50 is related to the anode common pin of LED and pins P40 to P47 are to the segment pins.
MB90800 series
P50
P47
P46
P45
P44
P43
P42
P41
P40
● Coding example
PDR4
EQU
000004H
PDR5
EQU
000005H
DDR4
EQU
000014H
DDR5
EQU
000015H
;----------Main Program-----------------------------------------------------CODE
CSEG
START:
; Initialization
MOV
I:PDR5, #00000000B
; Sets P50 to "L" level,#xxxxxxx0B
MOV
I:DDR5, #11111111B
; Sets port 5 to all-bit output.
MOV
I:PDR4, #11111111B
; Sets "1" in all bits of port 4.
MOV
I:DDR4, #11111111B
; Sets port 4 to all-bit output.
CODE
ENDS
;-------------------------------------------------------------------------------END
START
217
CHAPTER 8 I/O PORT
218
CHAPTER 9
SERIAL I/O
This chapter describes the MB90800 series serial I/O
functions and operations.
9.1 Overview of Serial I/O
9.2 Register of Serial I/O
9.3 Serial I/O Prescaler Register (SDCR0, SDCR1)
9.4 Operation of Serial I/O
219
CHAPTER 9 SERIAL I/O
9.1
Overview of Serial I/O
Serial I/O has a configuration of 8 bits x 2 channels available for data transfer of clock
synchronization mode. The extended I/O serial interface also has two alternatives in
data transfer called LSB first and MSB first.
■ Overview of Serial I/O
There are two serial I/O operation modes described below.
● Internal shift clock mode
Transfers data in synchronization with the internal clock (prescaler).
● External shift clock mode
Transfers data in synchronization with the clock input from the external pin (SC). Transfer operation with
CPU instructions (port reverse instruction execution timing) is also enabled by operating the generalpurpose port sharing the external pin (SC) in this mode.
■ Block Diagram of Serial I/O
Figure 9.1-1 Block Diagram of Serial I/O
Internal data bus
(MSB first) D0 to D7
D7 to D0 (LSB first)
Transfer direction select
SI2, SI3
Read
Write
SDR (serial shift data register)
SO2, SO3
SC2, SC3
Control circuit
Shift clock counter
Internal clock
(Serial I/O prescaler register
(SDCR))
2
1
0
(Serial mode control
SMD2
SMD1
SMD0
SIE
register (SMCS))
SIR BUSY STOP STRT MODE BDS
SOE SCOE
Interrupt
request
Internal data bus
Note:
SMCS0, SDR0, SDCR0 to serial I/O ch.2 (SI2, SO2, SC2), and SMCS1, SDR1, SDCR1 to ch.3 (SI3,
SO3, SC3) will correspond respectively.
220
CHAPTER 9 SERIAL I/O
9.2
Register of Serial I/O
Serial I/O operation can be set by the following registers:
• Serial mode control status register (SMCS0/SMCS1), higher
• Serial mode control status register (SMCS0/SMCS1), lower
• Serial shift data register (SDR0/SDR1)
• Serial I/O prescaler register (SDCR0/SDCR1)
■ Register of Serial I/O
Figure 9.2-1 Register of Serial I/O
bit15
bit8
bit7
bit0
Serial mode control status register (SMCS0, SMCS1)
Serial I/O prescaler register (SDCR0, SDCR1)
Serial shift data register (SDR0, SDR1)
221
CHAPTER 9 SERIAL I/O
9.2.1
Serial Mode Control Status Register (SMCS0, SMCS1)
Serial mode control status register (SMCS0, SMCS1) control transmission mode of
serial I/O.
■ Serial Mode Control Status Register (SMCS0, SMCS1), Higher
Figure 9.2-2 Serial Mode Control Status Register (SMCS), Higher
Address Bit 15
14
13
12
000061H,
SMD2 SMD1SMD0 SIE
000065H
R/W R/W R/W R/W
11
10
9
8
Initial value
SIR BUSY STOP STRT
00000010B
R/W R/W R/W R/W
STRT
Start bit
0
Serial transfer stop
1
Serial transfer activate
Stop bit
STOP
0
Normal operation
1
Transfer stop
Transfer state bit
BUSY
0
Stop or serial data register R/W waiting state
1
Serial transfer state
Serial I/O interrupt request flag bit
SIR
Read
Write
0
No interrupt request
Clear interrupt request
1
Interrupt request
No effection to operation
Serial I/O interrupt request enable bit
SIE
0
Interrupt request disabled
1
Interrupt request enabled
0
0
0
Serial shift clock mode setting bits
φ= 16MHz
φ= 8MHz
A
(div=8)
(div=8)
(div=4)
1.56MHz
1MHz
1MHz
Divided by 2
0
0
1
0.78MHz
1
0
195kHz
500kHz
125kHz
500kHz
12.5kHz
Divided by 4
0
0
1
1
97.5kHz
62.5kHz
62.5kHz
Divided by 16
48.75kHz
31.25kHz
31.25kHz
Divided by 32
SMD2 SMD1SMD0 φ=25MHz
1
0
0
1
0
1
1
0
1
1
1
1
R/W : Readable/Writable
: Initial value
φ
222
: Machine clock frequency
External shift clock mode
Reserved
Reserved
Divided by 8
CHAPTER 9 SERIAL I/O
Table 9.2-1 Function Description of Bits in Serial Mode Control Status Register (SMCS), Higher
Bit name
Functions
bit15
to
bit13
SMD2,
SMD1,
SMD0:
Serial shift
clock mode
setting bits
• The serial shift clock mode is set.
• Determines the shift clock communication rate based on the settings in the SMD2,
SMD1, and SMD0 bits and SDCR.
• Determines the shift clock communication rate based on the settings in the serial shift
clock mode setup bit and SDCR.
• Initialized to "000B" by reset.
• Rewriting under forwarding is prohibited (Do not rewrite).
• As for shift clock, five types of internal shift clocks and external shift clock can be set.
SMD2 to SMD00 = "110B", "111B" is a reserved area and must not be rewritten.
• Shift operation for individual instructions is enabled by setting SCOE = "0" by clock
setting and then operating the port sharing the SC pin.
bit12
SIE:
Serial I/O
interrupt
request enable
bit
• Bit enabling serial I/O interrupt request
• When "1" has been set, an interrupt request is output by setting "1" in the serial I/O
interrupt request flag bit (SIR).
• Initialized to "0" by reset.
bit11
SIR:
Serial I/O
interrupt
request flag
bit
• It is a flag bit of the interrupt request of serial I/O.
• Set to "1" upon completion of the serial data transfer.
• When the serial I/O interrupt request enable bit (SIE) has been set to "1", an interrupt
request is output to the CPU by setting "1".
• When "0" has been set in the MODE bit, the interrupt request is cleared by setting "0"
in the serial I/O interrupt request flag bit (SIR).
• When "1" has been set in the MODE bit, the interrupt request flag bit is cleared to "0"
by SDR register read or write operation.
• When reset occurs or "1" is set in the STOP bit, the interrupt request flag is cleared to
"0", regardless of the MODE bit value.
• When "0" is set, the interrupt request flag bit is cleared to "0".
• If "1" is set, operation is not affected.
• "1" is read when reading.
bit10
BUSY:
Transfer state
bit
• Set to "1" during serial transfer.
• Initialized to "0" by reset.
bit9
STOP:
Stop bit
• The serial transfer is compulsorily interrupted.
• Setting to "1" results in stop state with STOP = "1".
• Initialized to "1" by reset.
bit8
STRT:
Start bit
• The startup of the serial transfer is done.
• When "1" is set in stop state, transfer operation starts.
• When "1" is set during serial transfer operation or serial shift register read/write wait,
the written value is ignored.
• If "0" is set, operation is not affected.
• "0" is read when reading.
223
CHAPTER 9 SERIAL I/O
■ Serial Mode Control Status Register (SMCS0, SMCS1), Lower
Figure 9.2-3 Serial Mode Control Status Register (SMCS), Lower
Address Bit
000060H,
000064H
7
6
5
4
3
2
MODE BDS
R/W
R/W
1
0
Initial value
SOE
SC0E
- - - - 0000B
R/W
R/W
SC0E
0
Shift clock output enable bit
I/O port pin
1
Serial data output
SOE
0
Serial output enable bit
I/O port pin
1
Shift clock output pin
BDS
0
Transfer direction setting bit
LSB first (transfer from lowest bit)
1
MSB first (transfer from uppermost bit)
MODE
R/W
224
: Readable/Writable
: Initial value
Serial mode setting bit
0
Activate at STRT=1
1
Activate at read/write of serial data register (SDR)
CHAPTER 9 SERIAL I/O
Table 9.2-2 Function Description of Bits in Serial Mode Control Status Register, Lower (SMCS)
Bit name
Functions
bit7
to
bit4
-:
Undefined bits
• The value becomes undefined when read operation is performed.
• The set value does not influence the forwarding operation.
bit3
MODE:
Serial mode
register bit
• Sets conditions for starting from stop state.
• When "0" is set, starts with STRT = "1".
• When "1" is set, transfer operation is started by read/write of the serial data register
(SDR).
• Rewriting during forwarding operation is interdiction.
• Initialized to "0" by reset.
• When starting the extended intelligent I/O service, set "1".
bit2
BDS:
Transfer
direction
setting bit
• This bit sets the direction of serial data transfer.
• If "0" is set, data is transferred, starting from the least significant bit (LSB first).
• If "1" is set, data is transferred, starting from the most significant bit (MSB first).
• Set the transfer direction setup bit (BDS) before writing data in the SDR register.
bit1
SOE:
Serial output
enable bit
• Controls the external pins (SO2, 3) for serial I/O.
• When "0" is set, functions as input/output port pin.
• Functions as serial data output pin when "1" is set.
• Initialized to "0" by reset.
bit0
SC0E:
Shift clock
output enable
bit
• Controls output of the input/output external pins (SC2, 3) for shift clock.
• When "0" is set, functions as input/output port pin.
• Functions as serial data output pin when "1" is set.
• When transferring data for each instruction in external shift clock mode, set "0".
• Initialized to "0" by reset.
225
CHAPTER 9 SERIAL I/O
9.2.2
Serial Shift Data Register (SDR0, SDR1)
Serial shift data registers (SDR0, SDR1) are registers for storing serial I/O transfer data.
During transfer operation, do not perform write/read operation on the SDR0 and SDR1
registers.
■ Serial Shift Data Register (SDR0, SDR1)
Figure 9.2-4 Serial Shift Data Register (SDR)
Address Bit
000062H,
000066H
R/W
226
7
6
5
4
3
2
1
0
Initial value
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
: Readable/Writable
CHAPTER 9 SERIAL I/O
9.3
Serial I/O Prescaler Register (SDCR0, SDCR1)
Serial I/O prescaler register (SDCR0, SDCR1) supplies shift clock of serial I/O.
The serial I/O operation clock is obtained by dividing the machine clock. The serial I/O
has been designed so that the predetermined baud rate can be obtained for individual
machine clock of the system by this communication prescaler. These are registers for
controlling SDCR0 and SDCR1 registers and machine clock division.
■ Serial I/O Prescaler Register (SDCR0, SDCR1)
Figure 9.3-1 Serial I/O Prescaler Register (SDCR0, SDCR1)
Address Bit
000063H,
000067H
R/W
15
14
13
12
11
MD
Reserved
R/W
R/W
10
9
8
DIV2 DIV1 DIV0
R/W
R/W
Initial value
0---0000B
R/W
: Readable/Writable
: Undefined bit
Table 9.3-1 Functional Description of Each Bit of the Communication Prescaler Control Register (SDCR)
Bit name
Functions
bit15
MD:
Communication prescaler
operation enable bit
• Bit to enable the operation of the communication prescaler.
• The communication prescaler operates when "1" is set.
• The communication prescaler stops when "0" is set.
bit14
to
bit12
-:
Undefined bits
• The value becomes undefined when read operation is performed.
• The set value does not influence the operation.
bit11
Reserved:
Reserved bit
Be sure to set this bit to "0".
bit10
to
bit8
DIV2 to DIV0:
Division ratio setting bits
• Bit to set the division ratio of the machine lock
• For setting values, see Table 9.3-2 .
227
CHAPTER 9 SERIAL I/O
Table 9.3-2 Communication Prescaler
MD
DIV2
DIV1
DIV0
div
0
-
-
-
Stops
1
0
0
0
1
1
0
0
1
2
1
0
1
0
3
1
0
1
1
4
1
1
0
0
5
1
1
0
1
6
1
1
1
0
7
1
1
1
1
8
Note:
When the division ratio is changed, wait the period of time of machine clock divided by 2 for clock
stabilization before starting communications.
228
CHAPTER 9 SERIAL I/O
9.4
Operation of Serial I/O
Serial I/O consists of the serial mode control status registers (SMCS0, SMCS1) and shift
data registers (SDR0, SDR1). Used for 8-bit serial data input/output.
■ Operation of Serial I/O
When contents of shift data register synchronize with falling of serial shift clock (External clock, internal
clock), serial data I/O is output to serial output pin (SO pin) in bit series. When synchronizing with rising, it
is input from serial input pin (SI pin) to SDR0 and SDR1 register in bit series. The shift direction (MSB or
LSB) can be set in the transfer direction setup bit (BDS) of the serial mode control status register, lower
(SMCS0, SMCS1).
Upon completion of the transfer, transition to stop state or data register R/W standby state occurs
depending on the serial mode setup bit (MODE) of the serial mode control status register, lower (SMCS0,
SMCS1). For transition to transfer state from other states, set the following:
• When returning from stop state, set "0" in the stop bit (STOP) and "0" in the start bit (STRT). STOP and
STRT can be set simultaneously.
• When returning from the serial data register (SDR0, SDR1) R/W standby state, read or write the data
register.
229
CHAPTER 9 SERIAL I/O
9.4.1
Shift Clock
Shift clock has two modes: Internal shift clock mode and external shift clock mode; it is
set by the serial mode control status register (SMCS0, SMCS1). Please switch the mode
with serial I/O stopped. The stop state can be checked by reading the transfer state bit
(BUSY).
■ Internal Shift Clock Mode
Operates with the internal clock and shift clock with duty ratio 50 can be output as synchronous timing
output from the SC pin. Data is forwarded by one bit every a clock. The transfer rate can be defined by the
following formula:
Transfer speed (s)
div × A
Machine clock frequency (Hz)
A is a division ratio indicated with the serial shift clock mode setup bits (SMD0 to SMD2) of the serial
mode control status register (SMCS0, SMCS1) and it is 2, 4, 16, or 32.
The div is set by the divide frequency ratio setting bit (DIV2 to DIV0) of the serial I/O prescaler register
(SDCR0, SDCR1). For details, see Table 9.3-2 .
■ External Shift Clock Mode
In external shift clock mode, one data bit is transferred at each clock, in synchronization with the external
shift clock input from the SC pin. The transfer rate is possible following 1/5 machine cycles or less. For
example, when "1 machine cycle = 0.1μs", up to 2MHz is available.
The settings below enables transfer for each instruction:
• Set external shift clock mode and set "0" in the shift clock output enable bit (SCOE) of the serial mode
control status register (SMCS0, SMCS1).
• Set "1" in the direction register of the port sharing the SC pin to set the port to output mode.
After these settings, set "1" and "0" in the data register (PDR) of the port to fetch the port value output to
the SC pin as the external clock and start the transfer operation. Please start beginning the shift clock from
"H" level.
Note:
During serial I/O operation, writing to the serial mode control status register (SMCS0, SMCS1) and
serial shift data register (SDR0, SDR1) is inhibited.
230
CHAPTER 9 SERIAL I/O
9.4.2
Serial I/O Operation Status
The serial I/O operation states are shown below.
• STOP state
• Stop state
• R/W standby of SDR0 and SDR1 registers
• Transfer State
■ STOP State
In a state obtained by reset or by setting "1" in the stop bit (STOP) of the serial mode control status register
(SMCS0, SMCS1), the shift counter is initialized to SIR = 0. Returning from the stop state is performed by
setting STOP = 0 and STRT = 1 (both can be set at the same time). Because the stop bit (STOP) has
priority over the start bit (STRT), transfer operation is not performed when STOP = 1 and STRT = 1.
■ Stop State
When the serial mode setup bit (MODE) is "0", BUSY = 0 and SIR = 1 are set in the serial mode control
status register (SMCS0, SMCS1) and the counter is initialized and put in stop state upon completion of the
transfer. To return from the HALT state, set STRT to "1", then transfer operation restarts.
■ Serial Data Register Read/Write Standby State
When the serial mode setup bit (MODE) of the serial mode control status register (SMCS0, SMCS1) is "1",
BUSY = "0" and SIR = "1" are set and the SDR0 and SDR1 registers are put in the read/write standby state
upon completion of the serial transfer. When the interrupt enable register is in enabled state, this block
generates an interrupt signal.
When the SDR0 and SDR1 registers are read or written, BUSY = 1 is set and transfer operation is resumed,
returning from the read/write standby state.
■ Transfer State
It is a state to do the serial transfer by "BUSY = 1". Transition to stop state or read/write standby state
occurs depending on the serial mode setup bit (MODE).
Figure 9.4-1 Transfer Diagram of Serial I/O
Reset
Transfer end
STOP=0
STRT=0,BUSY=0
MODE=0
STOP=0
&
STRT=1
MODE=0
&
STOP=0
&
end
Transfer operation
STRT=1,BUSY=1
& STRT=0
STOP
STOP=1
STOP=1
STRT=0,BUSY=0
STOP=1
STOP=0
&
STRT=1
MODE=1& end &STOP=0
R/W & MODE=1 of SDR
Serial data register R/W waiting
STRT=1,BUSY=0
MODE=1
231
CHAPTER 9 SERIAL I/O
Serial data
Figure 9.4-2 Read and Write Conceptual Diagram to Serial Data Register
Data bus
SO0,SO1 Data bus
Read
Write
Read
Write
Interrupt output
SI0,SI1
(2)
Serial I/O interface
(1)
CPU
Interrupt input
Interrupt controller
Data bus
(1) When MODE = 1, the shift lock counter terminates the transfer, SIR = 1 is set, and transition to read/
write standby state occurs. When the serial I/O interrupt enable bit (SIE) is "1", an interrupt signal is
generated. Note that when the transfer is aborted because the serial I/O interrupt enable bit (SIE) is
inactive or "1" is set in the stop bit (STOP), no interrupt signals are generated.
(2) When the serial shift data register (SDR0, SDR1) is read or written, the interrupt request is cleared and
serial transfer starts.
232
CHAPTER 9 SERIAL I/O
9.4.3
Start/Stop Timing of Shift Operation
When starting shift operation, set "0" in the stop bit (STOP) and "1" in the start bit
(STRT) of the serial mode control status register (SMCS0, SMCS1). Shift operation is
stopped at two timings: by STOP = 1 and by transfer completion.
• Stop by STOP = 1 -> Stop with SIR = 0 regardless of the serial mode setup bit (MODE).
• Stop by transfer completion-> Stop with SIR = 1 regardless of the serial mode setup
bit (MODE).
The transfer state setup bit (BUSY) turns to "1" in serial transfer state and to "0" in stop
state or R/W standby state, regardless of the serial mode setup bit (MODE). For
checking the transfer state, read the transfer state setup bit (BUSY).
■ Start/stop Timing of Shift Operation
● Internal shift clock mode (LSB first)
Figure 9.4-3 Timing of Shift Operation (Internal clock)
SC0,SC1
STRT
"1" output
(Transfer start)
(Transfer end)
When MODE=0
BUSY
SO0,SO1
DO0
DO7 (Data retained)
● External shift clock mode (LSB first)
Figure 9.4-4 Timing of Shift Operation (External clock)
SC0,SC1
STRT
(Transfer start)
(Transfer end)
When MODE=0
BUSY
SO0,SO1
DO0
DO7 (Data retained)
233
CHAPTER 9 SERIAL I/O
● For instruction shift in external shift clock mode (LSB first)
PDR register bit
corresponding to SC0,1 pins =0
SC0,SC1
PDR register bit
corresponding to SC0,1 pins =0
PDR register bit corresponding to SC0,1 pins =1 (Transfer end)
STRT
When MODE=0
BUSY
SO0,SO1
DO6
DO7 (Data retained)
● Stop for STOP=1 (LSB first, at internal clock)
SC0,SC1
STRT
"1" output
(Transfer start)
(Transfer stop)
When MODE=0
BUSY
STOP
SO0,SO1
DO3
DO4
DO5 (Data retained)
Attention:DO7 to DO0 show output data.
■ Timing of I/O of Serial data
During serial data transfer, data is output from the serial output pin (SO) at the shift clock falling edge and
data is input from the serial input pin (SI) at the rising or falling edge, whichever set in advance.
Figure 9.4-5 Shift Timing of I/O of Serial Data
LSB first (when BDS bit is "0")
SC0,SC1
SI0,SI1
SI input
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DO3
DO4
DO5
DO6
DO7
DI4
DI3
DI2
DI1
DI0
DO4
DO3
DO2
DO1
DO0
SO output
SO0,SO1
DO0
DO1
DO2
MSB first (when BDS bit is "1")
SC0,SC1
SI0,SI1
SI input
DI7
DI6
DI5
SO output
SO0,SO1
234
DO7
DO6
DO5
CHAPTER 9 SERIAL I/O
9.4.4
Interrupt Function of Serial I/O
Serial I/O can output the interrupt request to CPU. When data transfer is terminated,
serial I/O interrupt request flag bit (SIR) which is interrupt flag is set to "1". When serial
I/O interrupt enable bit (SIE) of serial mode control status register (SMCS0 and SMCS1)
enabling interrupt is "1", interrupt request is output to CPU.
■ Interrupt Function of Serial I/O
Figure 9.4-6 Interruption Signal Output Timing of Serial I/O
SC0,SC1
(Transfer end)
BUSY
Note : When MODE=1
SIE=1
SIR
Read/Write
of SDR
SO0,SO1
DO6
DO7 (data retained)
235
CHAPTER 9 SERIAL I/O
236
CHAPTER 10
TIMEBASE TIMER
This chapter describes the function and operations of
the timebase timer of the MB90800 series.
10.1 Overview of Timebase Timer
10.2 Configuration of Timebase Timer
10.3 Timebase Timer Control Register (TBTC)
10.4 Interrupt of Timebase Timer
10.5 Explanation of Operations of Timebase Timer Functions
10.6 Precautions when Using Timebase Timer
237
CHAPTER 10 TIMEBASE TIMER
10.1
Overview of Timebase Timer
The timebase timer is an 18-bit free-run counter that counts up in synchronization to the
main clock. The timebase timer provides the interval timer function that enables four
types of interval time to be set and the function that supplies clock to the timer for
oscillation stabilization delay time, the watchdog timer and the clock output circuit.
■ Interval Timer Function
The interval timer function outputs an interrupt request at a regular time interval.
• When the interval timer counter of the timebase timer counter overflows, an interrupt request is output.
• The interval time of the interval timer can be set by selecting one from four different types.
Table 10.1-1 Interval Times of Timebase Timer
Main clock cycle
2/HCLK(0.32 μs)
Interval time
212/HCLK (Approx. 0.65ms)
214/HCLK (Approx. 2.62ms)
216/HCLK (Approx. 10.48ms)
219/HCLK (Approx. 83.88ms)
HCLK: Oscillation clock frequency
A value enclosed in parentheses indicates a value for when the oscillation clock frequency is 6.25 MHz.
■ Function of Clock Supply
The clock supply function supplies the operating clock to the timer for oscillation stabilization delay time
and some peripheral functions.
Table 10.1-2 Clock Cycles Supplied from Timebase Timer
Where to supply clock
Oscillation Stabilization
Wait Time
Clock cycle
213/HCLK (Approx. 1.31ms)
Oscillation stabilization wait time for
ceramic oscillators
215/HCLK (Approx. 5.24ms)
Oscillation stabilization wait time for
crystal oscillators
218/HCLK (Approx. 41.94ms)
Watchdog timer
Remark
212/HCLK (Approx. 0.65ms)
Count-up clock of watchdog timer
214/HCLK (Approx. 2.62ms)
216/HCLK (Approx. 10.48ms)
219/HCLK (Approx. 83.88ms)
HCLK: Oscillation clock frequency
A value enclosed in parentheses indicates a value for when the oscillation clock frequency is 6.25 MHz.
238
CHAPTER 10 TIMEBASE TIMER
Reference:
Because oscillation cycles vary immediately after oscillation starts, the oscillation stabilization time is
listed for reference.
239
CHAPTER 10 TIMEBASE TIMER
10.2
Configuration of Timebase Timer
The timebase timer consists of the following blocks:
• Timebase timer counter
• Counter clear circuit
• Interval timer selector
• Timebase timer control register (TBTC)
■ Block Diagram of Timebase Timer
Figure 10.2-1 Block Diagram of Timebase Timer
To watchdog
timer
To PPG timer
Timebase
timer counter
2-division of HCLK
21
22
28
29
210 211 212 213 214 215 216 217 218
OF
OF
OF
Power-on reset
Stop mode start
Hold status start
CKSCR: MCS=1 0*1
CKSCR: SCS=0 1*2
OF
Clock control
block oscillation
stabilization
time selector
Counter clear
control circuit
Interval timer
selector
TBOF
set
TBOF clear
Timebase timer control register
(TBTC)
Time base timer interrupt signal
Reserved
TBIE TBOF TBR TBC1TBC0
: Undefined bit
OF : Over flow
HCLK : Oscillation clock
*1
: Switching machine clock from main clock, or sub clock to PLL clock.
*2
: Switching machine clock from sub clock to main clock.
● Timebase timer counter
18-bit up-counter using the main clock as the count clock
● Counter clear circuit
This circuit clears the timebase timer counter by following;
- Setting "0" to timebase timer initializing bit (TBR) of timebase timer control register (TBTC)
- Power-on resetting
- Transition to stop mode (LPMCR:STP=1)
- Switching the machine clock from main clock to PLL clock (CKSCR:MCS=1 → 0)
240
CHAPTER 10 TIMEBASE TIMER
● Interval timer selector
Select one from four interval timer bit output of the timebase timer counter. An overflow of the selected
interval timer bit will be an interrupt cause.
● Timebase timer control register (TBTC)
Sets interval time, clears the timebase timer counter, controls interrupt requests, and checks the status.
241
CHAPTER 10 TIMEBASE TIMER
10.3
Timebase Timer Control Register (TBTC)
The timebase timer control register (TBTC) sets interval time, clears the timebase timer
counter, controls interrupt requests and checks the status.
■ Timebase Timer Control Register (TBTC)
Figure 10.3-1 Timebase Timer Control Register (TBTC)
Address
0000A9H
Bit
15
14
13
12
11
10
9
8
Initial value
Reserved
TBIE TBOF TBR TBC1 TBC0
R/W
R/W R/W R/W R/W R/W
1 - - 00100 B
Interval time setting bits
TBC1 TBC0
0
0
1
1
0
1
0
1
212/HCLK(approx. 0.65ms)
214/HCLK(approx. 2.62ms)
216/HCLK(approx. 10.48ms)
219/HCLK(approx. 83.88ms)
The value in parenthesis case oscillation
clock frequency is 6.25 MHz.
Timebase timer initialization bit
TBR
0
1
Clear timebase timer and interrupt request
No effect to operation
Interrupt request flag bit
Read
Write
TBOF
0
1
TBIE
0
1
No interrupt request Clear interrupt request
Interrupt request
No effect to operation
Interrupt request enable bit
Interrupt request disable
Interrupt request enable
Reserved
Be sure to set "1".
R/W
: Readable/Writable
: Undefined
: Initial value
HCLK : Oscillation clock frequency
242
Reserved bit
CHAPTER 10 TIMEBASE TIMER
Table 10.3-1 Functional Description of Each Bit in Timebase Timer Control Register (TBTC)
Bit name
Functions
bit15
Reserved:
Reserved bit
Be sure to set this bit to "1".
bit14,
bit13
-:
Undefined bits
• The value becomes undefined when read operation is performed.
• The set value does not influence the operation.
bit12
TBIE:
Interrupt
request enable
bit
• It is a bit by which the interrupt request is permitted.
• If "1" is set, an interrupt request is output to the CPU when the interrupt request flag
bit (TBOF) is set to "1".
bit11
TBOF:
Interrupt
request flag
bit
• It is a flag bit of the interrupt request.
• Set to "1" when the interval timer bit set by the timebase timer counter overflows.
If the interrupt request enable bit (TBIE) is set to "1", an interrupt request is output to
the CPU.
• When "0" is set, the interrupt request flag is cleared to "0".
• If "1" is set, operation is not affected.
Note:
• When setting "0", set the interrupt request enable bit (TBIE) or the interrupt level
mask register (ILM) of the processor status (PS) to "interrupt disable ".
• Cleared to "0" when the timebase timer is cleared or reset by transition to stop mode
or by the timebase timer initialization bit (TBR).
bit10
TBR:
Timebase
timer
initialization
bit
• This bit clears timebase timer counter.
• If "0" is set, the timebase timer counter is cleared to "00000H" and the interrupt
request flag bit (TBOF) is also cleared to "0".
• If "1" is set, operation is not affected.
Reference:
The reading value is one.
bit9,
bit8
TBC1, TBC0:
Interval time
setting bits
• It is a bit by which the cycle of the interval timer is set.
• Specify the bit for the interval timer of the timebase timer counter.
• Selectable from four types of interval time.
243
CHAPTER 10 TIMEBASE TIMER
10.4
Interrupt of Timebase Timer
An interrupt request can be output by an overflow of the interval timer counter selected
by the interval time setting bit. (Interval timer function).
■ Interrupt of Timebase Timer
When the timebase timer counter counts up by the main clock, and the selected interval timer counter
overflows, the interrupt request flag bit (TBOF) is set to "1". When the interrupt request flag bit is set to "1"
in the state the interrupt request enable bit is set to "enable" (TBTC; TBIE = 1), an interrupt request
(interrupt number #34) is output to the CPU and an interrupt processing routine is executed. The interrupt
processing routine is required to set the interrupt request flag bit (TBOF) to "0" and clear the interrupt
request. The interrupt request flag bit (TBOF) is set to "1" when the selected interval timer bit overflows,
regardless of the value of the interrupt request enable bit (TBIE).
Reference:
Extended intelligent I/O service (EI2OS) can not be used in timebase timer.
■ Interrupt of Timebase Timer and EI2OS
Table 10.4-1 Interrupt of Timebase Timer and EI2OS
Interrupt
number
#33(21H)
: Not available
244
Interrupt level setting register
Address in vector table
EI2OS
Register name
Address
Low
High
Bank
ICR11
0000BBH
FFFF78H
FFFF79H
FFFF7AH
CHAPTER 10 TIMEBASE TIMER
10.5
Explanation of Operations of Timebase Timer Functions
Described below are the interval timer function, the timer function for oscillation
stabilization delay time and the clock supply function.
■ Operation of Interval Timer Function (Timebase Timer)
The interval timer function outputs an interrupt request at specified time intervals. Figure 10.5-1 shows the
setting required to operate the timebase timer, as an interval timer.
Figure 10.5-1 Setting of the Timebase Timer
Bit
15
TBTC
Reserved
14
1
13
12
11
10
9
8
TBIE TBOF TBR TBC1 TBC0
0
0
: Used bit
0 : Setting "0"
1 : Setting "1"
: Undefined bit
• The timebase timer counter continues counting up while clock is being oscillated.
• When timebase timer counter is cleared (TBTC:TBR=0), it counts up from "000000000000000000B" and when
the bit set for interval timer causes an overflow, interrupt request flag bit (TBTC: TBOF) is set to "1".
When the interrupt request enable bit is enabled (TBIE = 1) and an overflow occurs, an interval request
is output at intervals specified based on the time when the counter is cleared.
• Actual interval time may be longer than the set time, depending on the clear operation of the timebase
timer counter.
■ Oscillation Stabilization Wait Time
The timebase timer is also used as a timer for the oscillation stabilization delay time of the oscillation clock or a
timer for the oscillation stabilization delay time of PLL clock. The oscillation stabilization delay time is counted
up, starting from a timebase timer counter value of "000000000000000000B" (counter clear). The counting
continues until oscillation stabilization delay time is detected. When returning from timebase timer mode to
PLL clock mode, the timebase timer counter is not cleared so the oscillation stabilization delay time will be
based on the count halfway.
245
CHAPTER 10 TIMEBASE TIMER
Table 10.5-1 Clear Operation of Timebase Timer Counter and Oscillation Stabilization Waiting Time
Operation
Counter
clear
Interrupt request
flag bit (TBOF) clear
Oscillation stabilization wait time
⎯
TBTC: Sets "0" in TBR.
Power on reset
Oscillation stabilization wait time
Watchdog reset
Cancellation of stop modes
Oscillation stabilization won’t time of oscillation
clock (when returning to main clock mode)
Clock mode
Transfer to PLL clock mode
(MCS = 1 → 0)
Oscillation stabilization wait time of PLL clock
Cancellation of timebase timer
modes
Oscillation stabilization wait time of PLL
clock (when returning to PLL clock mode)
Cancellation of sleep modes
⎯
: Clear
: Does not clear
■ Function of Clock Supply
The timebase timer supplies clock to the watchdog timer. Clearing of the timebase timer counter will affect
the operation of the watchdog timer. For details, see "10.6 Precautions when Using Timebase Timer".
■ Operations of Timebase Timer
Operations in the following situations are shown in Figure 10.5-2 .
• A power-on reset occurs.
• When transferring to the sleep mode in operations of the Interval Timer Functions
• When transferring to the stop mode
• A request to clear the timebase timer counter is issued.
When switched to stop mode, the timebase counter is cleared and stops. When recovering from stop mode,
the timebase timer counter counts oscillation stabilization delay time.
246
CHAPTER 10 TIMEBASE TIMER
Figure 10.5-2 Operations of Timebase Timer
Counter value
3FFFFH
Clear by transfer
to stop mode
Oscillation
stabilization
wait overflow
00000H
CPU operation Interval cycle
Counter clear
start
(TBTC: TBC1,TBC0=11B)
(TBTC: TBR=0)
Power-on reset
Clear with interrupt process routine
(option)
TBOF bit
TBIE bit
SLP bit
(LPMCR register)
Sleep
Interval interrupt sleep release
Stop
STP bit
(LPMCR register)
Stop release by external interrupt
The case setting "11B" (219/HCLK) to interval timer setting bit (TBC : TBC1, TBC0) of
timebase timer control register.
: Oscillation stabilization waiting time
HCLK : Oscillation clock frequency
247
CHAPTER 10 TIMEBASE TIMER
10.6
Precautions when Using Timebase Timer
Clearing an interrupt request and the timebase timer counter has the following effects
on the function.
■ Precautions when Using Timebase Timer
● Clearing Interrupt request
When clearing the interrupt request flag bit (TBOF) of the timebase timer control register (TBTC) to "0",
set the interrupt request enable bit (TBIE) or the interrupt level mask register (ILM) for the processor status
(PS) to "interrupt disable ".
● Function affected by clearing of timebase timer counter
• Interval Timer Function (Interval interrupt)
• Watchdog timer
• Watch clock output circuit
● Precaution of function supplied clock from timebase timer counter
In stop mode in which the operating clock stops, the timebase timer counter is cleared and stopped. When
the timebase timer counter is cleared, the clock from the timebase counter is supplied starting from the
initial state, so the "H" level may be shorter or the "L" level may be longer by 1/2 cycle max. Similarly, the
clock for the watchdog timer is supplied starting from the initial state. However, the watchdog timer will
operate at normal cycles because the counter of the watchdog timer is also cleared simultaneously.
● When using the timebase timer, as a timer for oscillation stabilization wait time
Because the oscillation clock has been stopped before power-on and in stop mode, the timebase timer
counter secures the oscillation stabilization wait time of the operating clock, using the clock supplied from
the resonator after it starts operation. In accordance with the resonator type, appropriate oscillation
stabilization wait time should be set.
For details, see "4.5 Oscillation Stabilization Wait Time".
248
CHAPTER 11
WATCHDOG TIMER
This chapter describes the function and operation of the
watchdog timer.
11.1 Overview of Watchdog Timer
11.2 Watchdog Timer Control Register (WDTC)
11.3 Configuration of Watchdog Timer
11.4 Operations of Watchdog Timer
11.5 Precautions when Using Watchdog Timer
11.6 Program Examples of Watchdog Timer
249
CHAPTER 11 WATCHDOG TIMER
11.1
Overview of Watchdog Timer
The watchdog timer is a 2-bit counter operating with an output of the timebase timer or
watch timer and resets the CPU when the counter is not cleared for a preset period of
time.
■ Functions of Watchdog Timer
The watchdog timer is a counter for preventing programs from hanging up. The timer must be cleared at
specified intervals after being activated. If the watchdog timer is not cleared within a certain time due to an
infinite loop of the program, etc., a watchdog reset is generated. The interval time of the watchdog timer
can be set by WT1 and WT0 bits of the watchdog timer control register (WDTC), as shown in Table 11.1-1 .
When the watchdog timer is not cleared, a watchdog reset occurs following the time between the minimum
time interval and the maximum time interval. The counter must be cleared before the time of the minimum
time interval.
Table 11.1-1 Interval Time of Watchdog Timer
Interval time
WT1
WT0
WDCS & SCM
Clock cycle count
Min. *
Max. *
0
0
1
Approx. 2.29 ms
Approx. 2.94ms
214 ± 211 HCLK cycle
0
1
1
Approx. 9.17 ms
Approx. 11.79 ms
216 ± 213 HCLK cycle
1
0
1
Approx. 36.7 ms
Approx. 47.18 ms
218 ± 215 HCLK cycle
1
1
1
Approx. 293.6 ms
Approx. 377.48 ms
221 ± 218 HCLK cycle
0
0
0
Approx. 0.448 s
Approx. 0.576 s
212 ± 29 SCLK cycle
0
1
0
Approx. 3.584 s
Approx. 4.608 s
215 ± 212 SCLK cycle
1
0
0
Approx. 7.168 s
Approx. 9.216 s
216 ± 213 SCLK cycle
1
1
0
Approx. 14.336 s
Approx. 18.432 s
217 ± 214 SCLK cycle
*:
Value for when operating at oscillator clock (HCLK) of 6.25 MHz, sub clock (SCLK) of 32 kHz divided by 4 (= 8
kHz). The maximum and minimum watchdog timer interval time and the number of oscillation clock cycles are
determined by the timing of clear operation. The interval time will be 3.5 to 4.5 times the count clock (timebase
timer-supplied clock) cycle. For the watchdog timer interval time, see "11.4 Operations of Watchdog Timer".
Note:
The watchdog counter is a 2-bit counter that counts carry-up signals from the timebase timer.
Therefore, when the timebase timer is cleared, the time period until the occurrence of a watchdog
timer reset may be longer than the preset period of time.
250
CHAPTER 11 WATCHDOG TIMER
Reference:
When the watchdog timer is activated, it is initialized and set to the stopped state by a reset upon
power-on or by a reset by the watchdog. While the watchdog counter is cleared by a reset by an
external pin, a reset by software, writing to the watchdog control bit (WTE) or changing to sleep
mode, stop mode or watch mode, the watchdog timer is left active.
251
CHAPTER 11 WATCHDOG TIMER
11.2
Watchdog Timer Control Register (WDTC)
The watchdog timer control register (WDTC) displays the factors for activating, clearing,
and resetting the watchdog timer.
■ Watchdog Timer Control Register (WDTC)
Figure 11.2-1 shows the watchdog timer control register (WDTC). Table 11.2-1 lists the function of each
bit of watchdog timer control register (WDTC).
Figure 11.2-1 Watchdog Timer Control Register (WDTC)
Address
0000A8H
bit15
bit8 bit7
(TBTC)
bit6
bit5
bit4
bit3
bit2
bit1
bit0
PONR
WRST ERST SRST WTE WT1 WT0
R/W
R/W R/W R/W R/W R/W R/W
Initial value
X-XXX1111 B
Interval time select bits (operating at HCLK: 6.25 MHz SCLK: 8 kHz)
Interval time
WT1 WT0 WDCS
& SCM
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
0
0
0
0
Min.
Oscillation clock
cycle number
Max.
approx. 2.29 ms approx. 2.94 ms
approx. 9.17 ms approx. 11.79 ms
approx. 36.7 ms approx. 47.18 ms
approx. 293.6 ms approx. 377.48 ms
approx. 0.448s approx. 0.576s
approx. 3.584s approx. 4.608s
approx. 7.168s approx. 9.216s
approx. 14.336s approx. 18.432s
214 ± 211 HCLK cycle
216 ± 213 HCLK cycle
218 ± 215 HCLK cycle
221 ± 218 HCLK cycle
212 ± 29 SCLK cycle
215 ± 212 SCLK cycle
216 ± 213 SCLK cycle
217 ± 214 SCLK cycle
HXLK: Oscillation clock
SCLK: Sub clock (4-division of 32 kHz)
Watchdog control bit
WTE
Activate watchdog timer
(at first writing after reset)
Clear watchdog timer
(at write after 2nd reset)
0
1
No operation
Reset factor bits
PONR WRST ERST SRST
1
R/W : Readable/Writable
X : Undefined
∗
: Undefined bit
∗
∗
∗
X
X
X
1
∗
∗
∗
∗
∗
1
∗
1
Reset factor bit
Power-on
Watchdog timer
External pin (RST="L" input)
RST bit (software reset)
: Retained previous state
: Initial value
The interval time will be 3.5 to 4.5 times the count clock (output value from the timebase timer) cycle. For
details, see "11.4 Operations of Watchdog Timer".
252
CHAPTER 11 WATCHDOG TIMER
Table 11.2-1 Function of Each Bit of Watchdog Timer Control Register (WDTC)
Bit name
Functions
bit7,
bit5,
bit4,
bit3
PONR
WRST
ERST
SRST
Reset factor
bits
• Read-only bits that indicate reset factors. When a reset factor
occurs, the relevant bit is set to "1".
The PONR, WRST, ERST and SRST bits are all cleared to "0"
after the WDTC register is read.
• The contents of the bits other than the PONR bit are not assured at
power-on. Therefore, when the PONR bit is "1", ignore the
contents of the bits other than the PONR bit.
bit6
Undefined
Undefined
• The reading value is irregular.
• Writing does not have the influence in the operation.
bit2
WTE
Watchdog
control bit
• Writing "0" activates the watchdog timer (at the first write after
reset) or clears the 2-bit counter (at the second write after reset).
• There is no influence in the operation in writing "1".
bit1,
bit0
WT1
WT0
Interval time
select bits
• This bit selects an interval time of the watchdog timer.
• The time interval when the watch timer is used as the clock source
to the watchdog timer (watchdog timer clock source select bit
WDCS=0) is different from when the main clock mode or the PLL
clock mode is selected as the clock mode and the WDCS bit in the
watch timer control register (WTC) is set to "1" as shown in Figure
11.2-1 according to the settings of the WTC register.
• Only data is valid after activating watchdog timer. Data written after
the activation of the watchdog timer is ignored.
• The WT1 and WT0 bits are only for writing.
253
CHAPTER 11 WATCHDOG TIMER
11.3
Configuration of Watchdog Timer
The watchdog timer consists of following five kinds of blocks.
• Count clock selector
• Watchdog counter (2-bit counter)
• Watchdog reset generator circuit
• Counter clear control circuit
• Watchdog timer control register (WDTC)
■ Block Diagram of Watchdog Timer
Figure 11.3-1 shows a watchdog timer block diagram.
Figure 11.3-1 Block Diagram of Watchdog Timer
Watchdog timer control register (WDTC)
PONR
Watch mode start
Timebase timer mode start
Sleep mode start
Hold state start
WRST ERST SRST WTE
Watchdog timer
Stop mode start
WT0
WDCS bit of watch timer control register (WTC)
SCM bit of clock selection register (CKSCR)
2
CLR
& activation
Counter
clear control
circuit
WT1
Count
clock
selector
CLR
Overflow
Watchdog reset
generating
circuit
2-bit
counter
Internal reset
generating circuit
CLR
4
Clear
4
(Timebase timer counter)
2-division of HCLK
× 21 × 22
× 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
SCLK
× 21 × 22
× 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
HCLK : Oscillation clock
SCLK : Sub clock
● Count clock selector
Circuit that selects the count clock of the watchdog timer from four types of timebase timer output and four
types of watch timer output. This determines when the watchdog reset is generated.
● Watchdog counter (2-bit counter)
2-bit up-counter that uses timebase timer output as the count clock.
● Watchdog reset generator circuit
Generates a reset signal by an overflow of the watchdog counter.
254
CHAPTER 11 WATCHDOG TIMER
● Counter clear circuit
Clears the watchdog counter and controls operation/stop of the counter.
● Watchdog timer control register (WDTC)
Activates/clears the watchdog timer and holds the reset occurrence factor.
255
CHAPTER 11 WATCHDOG TIMER
11.4
Operations of Watchdog Timer
The watchdog timer generates a watchdog reset upon an overflow of the watchdog
counter.
■ Operations of Watchdog Timer
Figure 11.4-1 shows the setting of watchdog timer.
Figure 11.4-1 Setting of Watchdog Timer
Address
0000A8H
bit15
WDTC
bit8 bit7
(TBTC)
: Used bit
: Unused bit
PONR
bit6
bit5
bit4
bit3
bit2
bit1
bit0
WRST ERST SRST WTE WT1 WT0
0
0 : Setting "0"
● Activating watchdog timer
• The watchdog timer is activated at the first write of "0" to the watchdog control bit (WTE) of the
watchdog timer control register (WDTC) after reset. In this case, specify the interval time at the same
time by the interval time selection bits (WT1, WT0) of the WDTC register.
• Once the watchdog time is activated, it cannot stop until power-on or a watchdog reset occurs.
● Clearing watchdog timer
• The 2-bit counter of the watchdog timer is cleared by the second write of "0" to the WTE bit. If the
counter is not cleared within the interval time, the counter overflows and the watchdog counter is reset.
• The watchdog counter is cleared when a reset operation occurs or when a change to sleep mode, stop
mode or timebase timer mode is made.
• When a change to timebase timer mode or watch mode is made, the watchdog counter is once cleared.
However, be careful that the watchdog counter does not stop after being cleared.
• When watch mode is used (sub clock), do not use the watchdog timer.
● Interval Time of Watchdog Timer
Figure 11.4-2 shows the relationship between clear timing and interval time of watchdog timer. The
interval time varies depending on the timing of clearing the watchdog timer and takes 3.5 to 4.5 times the
count clock cycle.
● Checking reset factors
By checking the reset factor bit (PONR, WRST, ERST, SRST) of the WDTC register after reset, the factor
of the reset can be identified.
256
CHAPTER 11 WATCHDOG TIMER
Figure 11.4-2 Relationship between Clear Timing and Interval Time of Watchdog Timer
[ Watchdog timer block diagram ]
2-bit counter
Clock
selector
a
2-division
circuit
b
2-division
circuit
c
Reset circuit
d
Reset
signal
Count enable and clear
Count enable
output circuit
WTE bit
[ Minimum interval time ] When clear WTE bit immediately before rising of count clock
Count start
Counter clear
Count clock a
The value of 2-division b
The value of 2-division c
Count enable
Reset signal d
7
(Count clock cycle/2)
WTE bit clear
Watchdog reset generating
[ Maximum interval time ] When clear WTE bit immediately before rising of count clock
Counter clear
Count start
Count clock a
The value of 2-division b
The value of 2-division c
Count enable
Reset signal d
9
WTE bit clear
(Count clock cycle/2)
Watchdog reset generating
257
CHAPTER 11 WATCHDOG TIMER
11.5
Precautions when Using Watchdog Timer
Take the following precautions when using the watchdog timer.
■ Precautions when Using Watchdog Timer
● Stopping watchdog timer
Once the watchdog time is activated, it cannot stop until power-on or a watchdog-external reset occurs.
● Interval Time
Because the interval time uses carry-up signals from the timebase timer, as the count clock, clearing the
timebase timer may make the interval time of the watch dog timer longer than the preset period of time.
● Selecting Interval Time
The interval time can be set when activating the watchdog timer. Data written after the activation of the
watchdog timer is ignored.
● Precautions when creating program
When creating a program that clears the watchdog timer repeatedly in the main loop, the main loop
processing time including the interrupt processing must not exceed the minimum interval time of the
watchdog timer.
258
CHAPTER 11 WATCHDOG TIMER
11.6
Program Examples of Watchdog Timer
Program example of watchdog timer is given below:
■ Program Examples of Watchdog Timer
● Processing specification
• The watchdog timer is cleared each time in loop of the main program.
• The processing of the main loop must go round within the minimum interval time.
● Coding example
WDTC
EQU
0000A8H
; Watchdog timer control register
WTE
EQU
WDTC:2
; Watchdog timer control bit
;----------Main program--------------------------------------------------CODE
CSEG
START:
;
:
; Initialize such as a stack pointer (SP).
WDG_START:
MOV
WDTC, #00000011B
; Activating watchdog timer
;221 ± 218 cycles in time of the interval are selected.
;----------Main loop------------------------------------------------------MAIN:
CLRB
;
:
;
User processing
;
:
JMP
I:WTE
; Clearing watchdog timer
It is regularly clearness of two bits.
MAIN
; Interval Time of Watchdog Timer
; Loop in the shortest possible time
CODE
ENDS
;----------Vector Settings--------------------------------------------------------VECT
VECT
CSEG
ABS=0FFH
ORG
0FFDCH
DSL
START
DB
00H
; Reset vector setting
; Single-chip mode setting
ENDS
END
START
259
CHAPTER 11 WATCHDOG TIMER
260
CHAPTER 12
WATCH TIMER
This chapter describes the functions and operations of
the watch timer of the MB90800 series.
12.1 Overview of Watch Timer
12.2 Configuration of Watch Timer
12.3 Watch Timer Control Register (WTC)
12.4 Operation of Watch timer
261
CHAPTER 12 WATCH TIMER
12.1
Overview of Watch Timer
The watch timer is a 15-bit timer using the sub clock. The interval interruption can be
generated. The watch timer can also be used as the clock source of the watchdog timer
by setting.
■ Watch Timer Function
The watch timer consists of a 15-bit timer and a circuit that controls interval interrupt.
The watch timer uses the sub clock, regardless of the values of the PLL clock selection bit (MCS) and sub
clock selection bit (SCS) of the clock selection register (CKSCR).
Table 12.1-1 shows the interval times of watch timer.
Table 12.1-1 Interval Times of Watch Timer
WTC2
WTC1
WTC0
Interval time *
0
0
0
31.25ms
0
0
1
62.5ms
0
1
0
125ms
0
1
1
250ms
1
0
0
500ms
1
0
1
1.000s
1
1
0
2.000s
1
1
1
Setting disabled
*: Four dividing of sub clock 32kHz (=8kHz)
262
CHAPTER 12 WATCH TIMER
12.2
Configuration of Watch Timer
The watch timer is composed of the following four blocks.
• Interval selector
• Clock counter
• Watch timer interruption generation circuit
• Watch timer control register (WTC)
■ Block Diagram of Watch Timer
Figure 12.2-1 Block Diagram of Watch Timer
Watch timer control register (WTC)
WDCS
SCE
WTIE
WTOF
WTR
WTC2
WTC1
WTC0
Clear
28
29
Sub clock
Watch counter
210
Interval selector
211
Interrupt
generation
circuit
Watch timer
interrupt
212
213
210 213 214 215
214
to Watchdog timer
● Watch Counter
A 15-bit up-counter using the sub clock as the clock source.
● Interval selector
A selector that selects one from seven types of interval of the watch timer.
● Interrupt generation circuit
Generates an interval interrupt of the watch timer.
● Watch timer control register (WTC)
Controls the operation of the watch timer and watch timer interrupt and specifies the clock source of the
watchdog timer.
263
CHAPTER 12 WATCH TIMER
12.3
Watch Timer Control Register (WTC)
Watch timer control register (WTC) controls operation of watch timer. It also controls
the interval interrupt time.
■ Watch Timer Control Register (WTC)
Figure 12.3-1 Watch Timer Control Register (WTC)
bit15
Address
0000AAH
bit8
bit7
bit6
WDCS SCE
R/W
R/W
bit5
bit4
WTIE WTOF
R/W
R/W
bit3
WTR
bit2
R/W
R/W
R/W
Watch timer interval selection bits
Interval time
(at Sub clock: 32kHz)
31.25ms
62.5ms
0
0
0
0
1
0
1
0
125ms
0
1
1
1
0
0
1
0
1
1
1
0
250ms
500ms
1.000s
2.000s
1
1
1
0
1
prohibited setting
Watch counter clear bit
Counter of watch timer is cleared all bits to "0".
Nothing. Be sure to read this bit at reading.
0
Watch timer interrupt request flag bit
No generate interrupt request.
1
Generate interrupt request.
WTOF
WTIE
0
1
SCE
Watch timer interval interrupt enable bit
Interrupt disabled
Interrupt enabled
Sub clock oscillation stabilization wait time end bit
0
Oscillation stabilization wait period
1
Oscillation stabilization wait time ends.
WDCS
0
264
R/W
Initial value
10011000B
0
WTR
: Initial value
bit0
WTC2 WTC1 WTC0
WTC2 WTC1 WTC0
R/W : Readable/Writable
bit1
1
Watchdog timer clock source selection bit
Select clock of watch timer.
Select clock of timebase timer.
CHAPTER 12 WATCH TIMER
Table 12.3-1 Function of Watch Timer Control Register (WTC)
Bit name
Functions
bit7
WDCS:
Watchdog timer clock
source selection bit
• This bit selects the clock source of the watchdog timer.
• When set to "0": Selects the clock of watch timer
When set to "1": Selects
• Initialized to "1" by a reset.
bit6
SCE:
Sub clock
oscillation stabilization
wait time end bit
• This bit indicates that the oscillation stabilization wait time of the sub clock has
expired.
• "0" setting of this bit indicates the oscillation stabilization wait period is going on.
• The oscillation stabilization wait time of the sub clock is 214 sub clock cycles.
• Initialized to "0" upon power-on reset and upon stop.
bit5
WTIE:
Watch timer interval
interrupt enable bit
• This bit enables an interval interrupt by the watch timer.
• When this bit is "1", interrupt is enabled. When this bit is "0", interrupt is disabled.
• Initialized to "0" by a reset.
bit4
WTOF:
Watch timer interrupt
request flag bit
• This bit indicates that an interrupt request of the watch timer has occurred.
• Interrupt request is generated when this bit is "1" if the WTIE bit is "1".
• It is set to "1" at every interval set with the WTC2 to WTC0 bits.
• This bit is cleared to "0" by writing "0", transition to stop mode, transition to
hardware standby mode, or a reset.
• Writing "1" in this bit does not have the meaning.
bit3
WTR:
Watch counter clear bit
• This bit clears all bits of the watch timer counter.
• The watch timer counter is cleared to "0" by writing "0" in this bit.
"1" writing in this bit does not have the meaning.
• When this bit is read, "1" is always read.
bit2
to
bit0
WTC2, WTC1, WTC0:
Watch timer interval
selection bits
• It is a bit by which the interval of the watch timer is set.
• Initialized to "00B" by reset.
• When changing this bit, also clear the WTOF bit at the same time.
265
CHAPTER 12 WATCH TIMER
12.4
Operation of Watch timer
The watch timer functions as a clock source for the watch dog timer, a timer for sub
clock oscillation stabilization wait time and an interval timer that generates an interrupt
at regular intervals.
■ Watch Counter
The watch counter is a 15-bit counter that counts sub clock and continues counting while sub clock is input.
● Clearing Watch Counter
The watch counter is cleared upon a power-on reset, change to stop mode and writing "0" to the watch
counter clear bit (WTR) of watch timer control register (WTC).
Note:
When the watch timer counter is cleared, the interrupts of the watchdog timer and interval timer that
use the output of the watch timer are affected.
■ Interruption Function for Interval of Watch Timer
A carry-up signal from the watch counter causes an interrupt to occur at regular intervals.
• Specifying Interval Time
• The (WTC2, WTC1 and WTC0) bits of the WTC register specifies interval time.
• Watch timer interrupt generation
• The watch timer interrupt request flag bit (WTOF) is set for each interval time set by the WTC2, WTC1
and WTC0 bits. In this case, if interrupt is enabled by setting "1" in the watch timer interval interrupt
enable bit (WTIE), a watch timer interrupt is generated.
• The WTOF bit is set, based on the time the watch timer was cleared last.
• Because, in stop mode, the watch timer functions use as a timer for oscillation stabilization wait time,
the WTOF bit is cleared immediately when mode is changed to stop mode.
■ Indicating Function of Clock Source in Watchdog Timer
The clock source of the watchdog timer can be specified by the watchdog timer clock source selection bit
(WDCS) of the WTC register. However, when watch mode is sub clock mode, the counter value of the
watch timer is used, regardless of the value of the WDCS bit.
■ Sub Clock Oscillation Stabilization Wait Time Function
When recovering from power-on reset or stop mode, the watch timer functions as a timer for sub clock
oscillation stabilization wait time. The sub clock oscillation stabilization wait time is fixed to 214 sub clock
cycles.
266
CHAPTER 13
16-BIT RELOAD TIMER
This chapter describes the functions and operations of
the 16-bit reload timer built in the MB90800 series.
13.1 Overview of 16-bit Reload Timer
13.2 Configuration of 16-bit Reload Timer
13.3 Pins of 16-bit Reload Timer
13.4 Registers of 16-bit Reload Timer
13.5 Interrupts of 16-bit Reload Timer
13.6 Explanation of Operation of 16-bit Reload Timer
13.7 16-bit Reload Timer Notes on Use
267
CHAPTER 13 16-BIT RELOAD TIMER
13.1
Overview of 16-bit Reload Timer
The MB90800 series features thee channels of 16-bit reload timer which can set the
following clock modes and the counter operation mode:
Clock Mode
• Internal clock mode: Mode in which countdown is performed in synchronization to
an internal clock
• Event count mode: Mode to count down by external input pulse
Counter Operating mode
• Reload mode: Mode in which the preset count value is reloaded and count is
repeated
• One-shot mode: Mode to stop count by underflow
■ Operation Modes of 16-bit Reload Timer
Table 13.1-1 Operation Modes of 16-bit Reload Timer
Clock Mode
Internal clock mode
Counter Operating mode
Reload mode
One-shot mode
Event count mode
(External Clock Mode)
Reload mode
Operating mode
Software trigger operation external trigger input
External gate input operation
Software trigger operation
One-shot mode
■ Internal Clock Mode
Setting the set count clock bits (CSL1, CSL0) of timer control status register (TMCSR) to "00B", "01B" and
"10B" results in the internal clock mode.
For internal clock mode, the following operation modes can be set.
● Software trigger operation
If the count enable bit (CNTE) of the timer control status register (TMCSR) is set to "1", setting the
software trigger bit (TRG) to "1" triggers the count operation.
● External trigger input
When count enable bit (CNTE) of timer control status register (TMCSR) is set to "1" and valid edge
(setable from rising, falling or both edge) of trigger input which is set previously is input to TIN pin in
operating mode setting bit (MOD2, MOD1 and MOD0), count operation is started.
● External gate input operation
When count enable bit (CNTE) of timer control status register (TMCSR) is set to "1", while valid level
(setable from "H" or "L") of gate input which is set previously in operating mode setting bit (MOD2,
MOD1 and MOD0) is input to TIN pin, count operation is carried out.
268
CHAPTER 13 16-BIT RELOAD TIMER
■ Event Count Mode (External Clock Mode)
Setting the count clock setting bits (CSL1, CSL0) of the timer control status register (TMCSR) to "11B"
results in the event count mode (external clock). If the count enable bit (CNTE) is set to "1", count
operation starts when a valid edge (rise/fall/both) of the trigger input, which is preset by the operating mode
setting bits (MOD2, MOD1, MOD0), is input to the TIN pin. When a constant frequency external clock is
input, the reload timer can also be used as an interval timer.
■ Counter Operation
● Reload mode
Loads the value of the 16-bit reload register (TMRLR) into the 16-bit down-counter upon an underflow of
the 16-bit down-counter ("0000H" -> "FFFFH") to start count operation. Since the reload timer outputs an
interrupt request upon an underflow, it can also be used as an interval timer. The TOT pin can output toggle
waveforms that are reversed whenever an underflow occurs.
Table 13.1-2 Interval Time of 16-bit Reload Timer
Count Clock
Internal count clock
External Count Clock
Count Clock Cycle
Interval Time
21/ φ (0.08 μs)
0.08 μs to 5.24 ms
23/ φ(0.32 μs)
0.32 μs to 20.97 ms
25/ φ (1.28 μs)
1.28 μs to 83.88 ms
23/ φ or more (0.32 μs)
0.32 μs or more
φ : Machine clock frequency
( ) : The inside is machine clock frequency 25MHz.
● One-shot mode
Count operation stops upon an underflow ("0000H" -> "FFFFH") of the 16-bit down-counter.
References:
• 16-bit reload timer 1/2 can be used for UART baud rate creation.
• 16-bit reload timer 1 can be used as an activation trigger of the A/D converter.
269
CHAPTER 13 16-BIT RELOAD TIMER
■ Interrupts of 16-bit Reload Timer and EI2OS
An interrupt request is output upon an underflow ("0000H" -> "FFFFH") of the 16-bit down-counter.
Table 13.1-3 Interrupts of 16-bit Reload Timer and EI2OS
Interrupt control registers
Channel
16-bit reloading
timer 0
Interrupt
number
Register
Name
EI2OS
Address
#23(17H)
ICR06
16-bit reloading
timer 1
#24(18H)
16-bit reloading
timer 2
#21(15H)
ICR05
Address in Vector Table
Low
High
Bank
FFFFA0H
FFFFA1H
FFFFA2H
FFFF9CH
FFFF9DH
FFFF9EH
FFFFA8H
FFFFA9H
FFFFAAH
0000B6H
0000B5H
:Usable when not using interrupt factor which is owned in common with ICR.
270
CHAPTER 13 16-BIT RELOAD TIMER
13.2
Configuration of 16-bit Reload Timer
16-bit reload timer 0 to 2 consist of the following blocks, respectively.
• Count clock generator circuit
• Reload controller circuit
• Output controller circuit
• Operation controller circuit
• 16-bit timer register (TMR)
• 16-bit reload register (TMRLR)
• Timer control status register (TMCSR)
■ Block Diagram of 16-bit Reload Timer
Figure 13.2-1 Block Diagram of 16-bit Reload Timer
Internal data bus
TMRLR
16-bit reload register
Reload signal
TMR
Reload control
circuit
16-bit timer register (down counter) UF
CLK
Count clock generating circuit
Machine
clock
φ
Prescaler 3
Gate
input
Valid
clock
judge
circuit
CLK
Clear
Input
control
circuit
UART*
To A/D converter
Output control circuit
Internal
clock
Pin
Weight signal
Clock
selector
Conversion
Output signal
generating circuit
Pin
EN
External clock
3
2
Select
signal
Function selection
CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE
Operating
control circuit
UF CNTE TRG
Timer control status register (TMCSR)
*: ch1/ch2
Interrupt request
signal
271
CHAPTER 13 16-BIT RELOAD TIMER
● Count clock generator circuit
The machine clock or an external input clock is used as the count clock of the 16-bit reload timer.
● Reload controller circuit
Controls the load operation to the 16-bit down-counter, when activation or an underflow ("0000H" ->
"FFFFH") of the 16-bit down-counter is detected.
● Output controller circuit
Controls the reverse operation of the TOT pin output by an underflow ("0000H" -> "FFFFH") of the 16-bit
down-counter and the enable/disable of the TOT pin output.
● Operation controller circuit
Starting/stopping of 16-bit down counter is controlled.
● 16-bit timer register (TMR)
It is 16-bit down counter. The value of the counter can be read in read operation.
● 16-bit reload register (TMRLR)
The 16-bit reload register (TMRLR) is a register that sets the value to be loaded to the 16-bit down-counter.
Loads the value set in the 16-bit reload register into the 16-bit down-counter for down count operation.
● Timer control status register (TMCSR)
Provides the following functions: set the operating mode of the 16-bit reload timer; set count clock; set
operating conditions: set the enable/disable of the count operation; perform interrupt control; check the
interrupt request status.
272
CHAPTER 13 16-BIT RELOAD TIMER
13.3
Pins of 16-bit Reload Timer
Shown below are the pins of 16-1 bit reload timer and a block diagram of the pin unit.
■ Pins of 16-bit Reload Timer
Pins of 16-bit reload timer is also used for I/O ports.
Table 13.3-1 Pins of 16-bit Reload Timer
Pin name
Pin function
I/O type
P50/TIN0
Port 5 I/O
/Timer input
CMOS output/
SEG output/
CMOS hysteresis input
P45/TOT0
Port 4 I/O
/Timer output
CMOS output/
CMOS hysteresis input
P51/TIN1
Port 5 I/O
/Timer output
CMOS output/
SEG output/
CMOS hysteresis input
P46/TOT1
Port 4 I/O
/Timer output
CMOS output/
CMOS hysteresis input
P52/TIN2
Port 5 I/O
/Timer output
CMOS output/
SEG output/
CMOS hysteresis input
P47/TOT2
Port 4 I/O
/Timer output
CMOS output/
CMOS hysteresis input
Pull-up
selection
Stand-by
control
To the use of the terminal
setting
None
Yes
Set to the input port
(DDR5:bit0 = 0)
Set timer output enable
(TMCSR0: OUTE = 1).
None
Yes
Set to the input port
(DDR5:bit1 = 0)
Set timer output enable
(TMCSR1:OUTE = 1).
None
Yes
Set to the input port
(DDR5:bit2 = 0)
Set timer output enable
(TMCSR2:OUTE = 1).
■ Block Diagram for Pins of 16-bit Reload Timer
Figure 13.3-1 Block Diagram for Pins of 16-bit Reload Timer
Internal data bus
Resource input
PDR read
PDR
I/O judge
circuit
PDR write
DDR
Input buffer
Output buffer
Port pin
Standby control (LPMCR:SPL="1")
I/O control circuit
Resource output
273
CHAPTER 13 16-BIT RELOAD TIMER
13.4
Registers of 16-bit Reload Timer
The list of the register of 16 bit reload timer is shown.
■ List of Register of 16-bit Reload Timer
Figure 13.4-1 List of Register of 16-bit Reload Timer
bit15
bit8
bit7
TMCSR (timer control status register)
TMR/TMRLR (16-bit timer register/16-bit reload register)*
*: This functions as timer register (TMR) at reading and
as 16-bit reload register (TMRLR) at writing.
274
bit0
CHAPTER 13 16-BIT RELOAD TIMER
13.4.1
Timer Control Status Register Higher (TMCSR)
The operating mode of the 16-bit reload timer and the count clock can be set using the
timer control status register (TMCSR).
■ Timer Control Status Register Higher (TMCSR)
Figure 13.4-2 Timer Control Status Register Higher (TMCSR)
Bit
Address
ch.0 000051H
ch.1 000055H
ch.2 000059H
15
14
13
12
11
10
9
8
7
∗
CSL1 CSL0 MOD2 MOD1 MOD0
Initial value
----0000B
R/W R/W R/W R/W R/W
MOD2 MOD1 MOD0
Operation mode setting bits
(at internal clock mode)
Input pin function
0
0
0
0
0
1
0
1
0
0
1
1
1
X
0
1
X
1
MOD2 MOD1 MOD0
R/W
φ
∗
"L" level
Gate input
"H" level
Operation mode setting bits
(at event count mode)
Rising edge
Trigger input
Falling edge
0
X
1
X
1
1
1
Both edge
0
X
0
Falling edge
1
0
0
Rising edge
Trigger input
Valid edge
0
0
Trigger disabled
Input pin function
X
CSL1 CSL0
Valid edge and level
Both edge
Count clock selection bits
Function
Count clock
21/φ (0.08μs)
Internal clock mode
23/φ (0.32μs)
25/φ (1.28μs)
1
0
: Readable/Writable
External
event input
Event
count
mode
1
1
: Undefined bit
: Initial value
: Machine clock, The value in parenthesis is machine clock at 25 MHz operation.
: Refer to "13.4.1 Timer control status register upper (TMCSR)" about MOD0 (bit7).
275
CHAPTER 13 16-BIT RELOAD TIMER
Table 13.4-1 Functional Description of Each Bit of the Timer Control Status Register Higher (TMCSR)
Bit name
Functions
bit15
to
bit12
-:
Undefined bits
• The value becomes undefined when read operation is performed.
• The set value does not influence the operation.
bit11,
bit10
CSL1, CSL0:
Count clock selection
bits
• This bit sets the count clock of the 16-bit reload timer.
• When "00B", "01B" and "10B" is set, internal clock mode is set.
• When "11B" is set, event count mode is set.
MOD2, MOD1,
MOD0:
Operation mode
setting bits
• It is a bit by which the operation mode is set.
< At internal clock mode>
• The MOD2 bit sets the function of the input pin.
• When input pin is set as the trigger input pin by setting "0" to the MOD2 bit and the
preset valid edge is input, the value of the 16-bit reload register (TMRLR) is loaded
into the 16-bit down-counter and starts count operation. The MOD1 and MOD0 bits
specify the direction of the valid edge.
• When the MD2 bit is set to "1", the input pin functions as the gate input and the
count operation continues while the valid level set by the MOD0 bit is input.
• The value set in the MOD1 bit has not effect on the operation.
< At event count mode >
• The value set in the MOD2 bit has not effect on the operation.
• If event count mode is set, the input pin functions as the trigger input and count
operation starts when the valid edge set by the MOD1 and MOD0 bits is input.
bit9
to
bit7
276
CHAPTER 13 16-BIT RELOAD TIMER
13.4.2
Timer Control Status Register Lower (TMCSR)
The timer control status register (TMCSR) provides the following functions: set the
operating conditions of the 16-bit reload timer; set the enable/disable of the count
operation; perform interrupt control; check the interrupt request status.
■ Timer Control Status Register Lower (TMCSR)
Figure 13.4-3 Timer Control Status Register Lower (TMCSR)
Address
Bit
7
6
5
4
3
2
1
0
Initial value
∗
ch.0 000050H
OUTE
OUTL
RELD
INTE
UF
CNTE
00000000B
TRG
MOD0
ch.1 000054H
ch.2 000058H
R/W R/W R/W R/W R/W R/W R/W R/W
TRG
Software trigger bit
0
No effect to operation
1
After data reloaded, count operation starts.
CNTE
Count enable bit
0
Count stop
1
Count enable (activation trigger wait)
Under flow interrupt request flag bit
Write
Read
UF
0
No interrupt request
Clear interrupt request
1
Interrupt request
No effect to operation
INTE
Under flow interrupt request enable bit
0
Interrupt request output disabled
1
Interrupt request output enabled
RELD
Reload enable bit
0
One-shot mode (reload disabled)
1
Reload mode (reload enabled)
Pin output level setting bit
OUTL
At one-shot mode
(RELD=0)
At reload mode
(RELD=1)
0
High rectangular wave during counting Toggle
1
Low rectangular wave during counting
waveform at count start "L"
Toggle waveform at count start "H"
Timer output enable bit
OUTE
0
Pin function
I/O port
Register and pin corresponding to each channel
TMCR
P45, P46, P47
R/W : Readable/Writable
Timer output pin
TOT0, TOT1, TOT2
1
: Initial value
∗ : Refer to "13.4.1 Timer control status register upper (TMCSR)" about MOD0 (bit7).
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CHAPTER 13 16-BIT RELOAD TIMER
Table 13.4-2 Functional Description of Each Bit of the Timer Control Status Register Lower (TMCSR)
Bit name
Functions
bit6
OUTE:
Timer output enable
bit
• This bit enables output to the timer output pin.
• When "0" is set, the pin functions as an I/O port. When "1" is set, it functions as a timer
output pin.
bit5
OUTL:
Pin output level
setting bit
• This bit sets the level of output to the timer output pin.
• The timer output pin outputs a toggle waveform in reload mode and a rectangular
waveform during count operation in one-shot mode.
• The pin output level is reversed for "0" setting and "1" setting.
bit4
RELD:
Reload enable bit
• It is a bit by which the reload operation is permitted.
• When "1" is set, reload mode is set, and the value set in the 16-bit register is loaded into
the 16-bit down-counter upon an underflow of the 16-bit down-counter and count
operation continues.
• When this bit is "0", one-shot mode is set and count operation stops upon an underflow
of the 16-bit down-counter.
bit3
INTE:
Underflow interrupt
request enable bit
• It is a bit by which the interrupt request is permitted.
• When this bit is "1", an interrupt request is output when the underflow interrupt request
flag bit (UF) is set to "1".
bit2
UF:
Underflow interrupt
request flag bit
• It is a flag bit of the interrupt request.
• "1" is set by the underflow of 16 bit down counter.
• When the underflow interrupt request enable bit (INTE) is "1" and this bit is set to "1",
an interrupt request is output.
• When "0" is set, the interrupt request is cleared.
• If "1" is set, operation is not affected.
• Cleared to "0" upon EI2OS activation.
bit1
CNTE:
Count enable bit
• It is a bit by which the count operation is permitted.
• When "1" is set, this bit become activating trigger waiting state. Then, software trigger
bit (TRG) is set "1", or when the valid edge (setable from rising, falling and both edge)
of trigger input which is set in operating mode setting bit (MOD2, MOD1 and MOD0)
is input to TIN pin, count operation is started.
• When "0" is set, the count operation is stopped.
bit0
TRG:
Software trigger bit
• This bit activates the interval timer function or counter function by software.
• When the count enable bit (CNTE) is "1" and this bit is set to "1", the value set in the
16-bit reload resister is loaded into the 16-bit down-counter and count operation starts.
• If "0" is set, operation is not affected.
• These bits indicate "0" when read.
278
CHAPTER 13 16-BIT RELOAD TIMER
13.4.3
16-bit Timer Register (TMR)
The 16-bit timer register (TMR) can read the count value of the 16-bit down-counter.
■ 16-bit Timer Register (TMR)
Figure 13.4-4 16-bit Timer Register (TMR)
Bit
Address
ch.0 000052H
000053H
ch.1 000056H
000057H
ch.2 00005AH
00005BH
15
14
D15 D14
13
12
11
10
D13
D12 D11 D10
9
8
Initial value
D9
D8
XXXXXXXX B
R/W R/W R/W R/W R/W R/W R/W R/W
Bit
7
6
5
4
3
2
1
0
Initial value
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXX B
R/W R/W R/W R/W R/W R/W R/W R/W
R/W : Readable/Writable
X
: Indefinite
It is 16 bit down counter.
When the count enable bit (CNTE) of timer status control register (TMCSR) is set to "1", software trigger
bit (TRG) is set to "1". In the meantime, when the valid edge (setable from rising, falling and both edge) of
trigger input which is set in operating mode setting bit (MOD2, MOD1 and MOD0) is input to TIN pin, the
value set in 16-bit reload register (TMRLR) is loaded to 16-bit down counter and then started down
counter. When counting is in the stop state (TMCSR:CNTE = 0), the value of the 16-bit timer register
(TMR) is held unchanged.
Notes:
• When reading the 16-bit timer register (TMR), be sure to use the word transfer instruction
(MOVW A, 003AH).
• 16-bit timer register (TMR) is a read only register and 16-bit reload register (TMRLR) is a write only
register. However they are assigned to the same address. When setting the value to 16-bit timer
register, 16-bit reload register is set the value without affecting 16-bit timer register.
279
CHAPTER 13 16-BIT RELOAD TIMER
13.4.4
16-bit Reload Register (TMRLR)
The 16-bit reload register (TMRLR) is a register that sets the value to be loaded to the
16-bit down-counter. The value set in the 16-bit reload register is loaded to the 16-bit
down-counter and count operation starts.
■ 16-bit Reload Register (TMRLR)
Figure 13.4-5 16-bit Reload Register (TMRLR)
Bit
Address
ch.0 000052H
000053H
ch.1 000056H
000057H
ch.2 00005AH
00005BH
15
14
D15 D14
13
12
11
10
D13
D12 D11 D10
9
8
Initial value
D9
D8
XXXXXXXX B
R/W R/W R/W R/W R/W R/W R/W R/W
Bit
7
6
5
4
3
2
1
0
Initial value
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXX B
R/W R/W R/W R/W R/W R/W R/W R/W
R/W : Readable/Writable
X
: Indefinite
When setting a value in the 16-bit reload register (TMRLR), be sure to stop count operation
(TMCSR:CNTE = 0), regardless of the operating mode of the 16-bit reload timer. When the count enable
bit (CNTE) of timer status control register (TMCSR) is set to "1", software trigger bit (TRG) is set to "1".
In the meantime, when the valid edge (setable from rising, falling and both edge) of trigger input which is
set in operating mode setting bit (MOD2, MOD1 and MOD0) is input to TIN pin, the value set in 16-bit
reload register (TMRLR) is loaded to 16-bit down counter and then started down counter.
In reload mode, the value in the 16-bit reload register (TMRLR) is loaded to the 16-bit down-counter upon
an underflow ("0000H" -> "FFFFH") of the 16-bit down-counter and counting down continues. In one-shot
mode, the 16-bit down-counter stops upon an underflow of the 16-bit down-counter at "FFFFH".
Notes:
• When setting a value in the 16-bit reload register (TMRLR), be sure to stop count operation
(TMCSR:CNTE = 0).
• Use the word transfer instruction (MOVW 003AH,A) to set the 16-bit reload register (TMRLR).
• 16-bit timer register (TMR) is a read only register and 16-bit reload register (TMRLR) is a write only
register. As they are assigned to the same address, writing value and reading value are different.
The instruction executing the read modify write (RMW) instructions such as INC/DEC instruction,
etc. can not be used.
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CHAPTER 13 16-BIT RELOAD TIMER
13.5
Interrupts of 16-bit Reload Timer
The 16-bit reload timer outputs an interrupt request upon an underflow of the 16-bit
down-counter. The hardware interrupt corresponds to the extended intelligent I/O
service (EI2OS).
■ Interrupts of 16-bit Reload Timer
Table 13.5-1 Interrupt Control Bit of 16-bit Reload Timer and Interrupt Factor
16-bit reload timer 0
16-bit reload timer 1
16-bit reload timer 2
Interrupt request flag bit
TMCSR0:UF
TMCSR1:UF
TMCSR2:UF
Interrupt request enable
bit
TMCSR0:INTE
TMCSR1:INTE
TMCSR2:INTE
Interrupt cause
16 bit down counter
(TMR0) Underflow
16 bit down counter
(TMR1) Underflow
16 bit down counter
(TMR2) Underflow
In the 16-bit reload timer, the underflow interrupt request flag bit (UF) of the timer control status register
(TMCSR) is set to "1" upon an underflow of the 16-bit counter ("0000H" -> "FFFFH"). If the underflow
interrupt request enable bit enables interrupt request (TMCSR:INTE = 1), an interrupt request is output.
■ Interrupts of 16-bit Reload Timer and EI2OS
Table 13.5-2 Interrupts of 16-bit Reload Timer and EI2OS
Interrupt control registers
Interrupt
number
Channel
16-bit reloading
timer 0
Register
name
EI2OS
Address
#23(17H)
ICR06
16-bit reloading
timer 1
#24(18H)
16-bit reloading
timer 2
#21(15H)
ICR05
Address in vector table
Low
High
Bank
FFFFA0H
FFFFA1H
FFFFA2H
FFFF9CH
FFFF9DH
FFFF9EH
FFFFA8H
FFFFA9H
FFFFAAH
0000B6H
0000B5H
:Usable when not using interrupt factor which is owned in common with ICR.
■ EI2OS Function of 16-bit Reload Timer
The 16-bit reload timer can use the extended intelligent I/O service (EI2OS) upon an underflow of the 16bit down-counter ("0000H" -> "FFFFH").
281
CHAPTER 13 16-BIT RELOAD TIMER
13.6
Explanation of Operation of 16-bit Reload Timer
This section explains the setting of the 16-bit reload timer and the operation state of the
counter.
■ Setting of 16-bit Reload Timer
● Setting of internal clock mode
To operate as an interval timer, set as shown in Figure 13.6-1 .
Figure 13.6-1 Setting of Internal Clock Mode
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CSL1 CSL0 MOD2 MOD1 MOD0 OUTEOUTL RELD INTE UF CNTE TRG
TMCSR
1
Other than "11"
Set the initial value of counter (reload value)
TMRLR
: Using bit
1 : Set "1".
● Setting of Internal Clock Mode
To operate as an event counter, set as shown in Figure 13.6-2 .
Figure 13.6-2 Setting of Event Count Mode
Bit
15
TMCSR
14
13
12
11
9
8
7
6
5
4
3
2
1
0
CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE UF CNTE TRG
1
TMRLR
10
1
1
Set the initial value of counter (reload value)
DDR5
: Using bit
1 : Set "1".
: Set "0" to the bit corresponding to using pin.
■ Counter Operation State
The status of the 16-bit down-counter is determined by the value of the count enable bit (CNTE) and the
value of the activation trigger waiting signal value (WAIT) of an internal signal in the timer control status
register (TMCSR). Figure 13.6-3 shows the relationship between the count enable bit (CNTE) value of the
STOP state (halt state), WAIT state (trigger activation wait state) and RUN state (operating state) and the
value of the activation trigger signal (WAIT) of an internal signal.
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CHAPTER 13 16-BIT RELOAD TIMER
Figure 13.6-3 Counter State Transition Diagram
Reset
STOP state CNTE=0,WAIT=1
TIN pin : Input disable
TOT pin : General port
Counter : Hold the value at stop
Undefined immediately
after reset
CNTE=0
CNTE=0
CNTE=1
TRG=0
CNTE=1
TRG=1
WAIT state CNTE=1,WAIT=1
TIN pin : Available only trigger input
TOT pin : Initial value output
UF=1
Counter : Hold value at stop
Undefined until loading immediately RELD=0
after reset
(one-shot mode)
TRG=1
(soft trigger)
RUN state
CNTE=1,WAIT=0
TIN pin : Function as TIN pin
TOT pin : Function as TOT pin
Counter : Operation
UF=1
RELD=1
TRG=1
(Reload mode)
(Soft trigger)
CNTE=1, WAIT=0
LOAD
Load the value of 16-bit reload register
External trigger from TIN pin to down counter.
Load end
: State transfer by hardware
: State transfer by register access
WAIT : Activate trigger waiting signal value of internal signal
TRG : Software trigger bit of timer control status register (TMCSR)
CNTE : Count enable bit of timer control status register (TMCSR)
UF
: Underflow interrupt request flag bit of timer control status register (TMCSR)
RELD : Reload enable bit of timer control status register (TMCSR)
283
CHAPTER 13 16-BIT RELOAD TIMER
13.6.1
Internal Clock Mode (Reload Mode)
Counts down the 16-bit down-counter in synchronization to the internal count clock and
outputs an interrupt request upon an underflow ("0000H" -> "FFFFH"). Also can output
toggle waveforms from the timer output pin.
■ Operation of Internal Clock Mode (Reload Mode)
When the count enable bit (CNTE) of timer status control register (TMCSR) is set to "1", software trigger
bit (TRG) is set to "1". In the meantime, when the valid edge (setable from rising, falling and both edge) of
trigger input which is set in operating mode setting bit (MOD2, MOD1 and MOD0) is input to TIN pin, the
value set in 16-bit reload register (TMRLR) is loaded to 16-bit down counter and then started down
counter. If both the count enable bit (CNTE) and software trigger bit are set to "1" simultaneously, the
counting down starts immediately when count operation is enabled.
Upon an underflow ("0000H" -> "FFFFH") of the 16-bit down-counter, the preset value in the 16-bit reload
register (TMRLR) is loaded to the 16-bit down-counter and courting down continues. When "1" is set to
under flow interrupt request flag bit (UF) of timer control status register (TMCSR) in under flow of 16-bit
dawn counter and under flow interrupt request enable bit (INTE) is set to "1", interrupt request is output to
CPU.
The TOT pin outputs toggle waveforms that are reversed every time an underflow occurs.
● Software trigger operation
If the count enable bit (CNTE) of the timer control status register (TMCSR) is set to "1", count operation
starts when the software trigger bit (TRG) is set to "1".
Figure 13.6-4 Count Operation (Software trigger operation) at Reload Mode
Count clock
Reload
data
Counter
-1
0000H
Reload
data
Data load signal
UF bit
CNTE bit
TRG bit
T*
TOT pin
T : Machine cycle (1 cycle of machine clock)
* : It takes 1T time from trigger input to reload data loading.
284
-1
0000H
Reload
data
-1
0000H
Reload
data
-1
CHAPTER 13 16-BIT RELOAD TIMER
● External trigger input operation
When the count enable bit (CNTE) of timer status control register (TMCSR) is set to "1" and the valid edge
(setable from rising, falling and both edge) of trigger input which is set in operating mode setting bit
(MOD2, MOD1 and MOD0) is input to TIN pin, count operation is started.
Figure 13.6-5 Count Operation (External trigger operation) at Reload Mode
Count clock
Reload
data
Counter
-1
0000H Reload
data
-1
0000H Reload
data
-1
0000H Reload
data
-1
Data load signal
UF bit
CNTE bit
TIN pin
2T to 2.5T
TOT pin
T : Machine cycle (1-cycle of machine clock)
: It takes 2T to 2.5T times from external trigger input to reload data.
Note:
The width of a trigger pulse input to the TIN pin must be above 2/φ (φ: machine clock frequency).
285
CHAPTER 13 16-BIT RELOAD TIMER
● External gate input operation
If the count enable bit (CNTE) of the timer control status register (TMCSR) is set to "1", count operation
starts when the software trigger bit (TRG) is set to "1".
Count operation continues while a valid level ("L" or "H") of the gate input, which is preset by the
operating mode setting bit (MOD2, MOD1, MOD0), is input to the TIN pin.
Figure 13.6-6 Count Operation in Reload Mode (Software trigger, gate input operation)
Count clock
Reload data
Counter
-1
-1
-1
0000H
Reload
data
-1
-1
Data load signal
UF bit
CNTE bit
TRG bit
T*
TIN pin
TOT pin
T : Machine cycle (1 cycle of machine clock)
* : It takes 1T time from trigger input to reload data loading.
Note:
The width of a gate input pulse to the TIN pin must be above 2/φ (φ: machine clock frequency).
286
CHAPTER 13 16-BIT RELOAD TIMER
13.6.2
Internal Clock Mode (One-Shot Mode)
Counts down the 16-bit down-counter in synchronization to the internal count clock and
outputs an interrupt request upon an underflow ("0000H" -> "FFFFH"). Also the TOT pin
can output rectangular waveforms indicating that counting is going on.
■ Internal Clock Mode (One-shot Mode)
When the count enable bit (CNTE) of timer status control register (TMCSR) is set to "1", software trigger
bit (TRG) is set to "1". In the meantime, when the valid edge (setable from rising, falling and both edge) of
trigger input which is set in operating mode setting bit (MOD2, MOD1 and MOD0) is input to TIN pin, the
value set in 16-bit reload register (TMRLR) is loaded to 16-bit down counter and then started down
counter. If both the count enable bit (CNTE) and software trigger bit (TMCSR:TRG) are set to "1"
simultaneously, the counting down starts immediately when count operation is enabled.
Upon an underflow ("0000H" -> "FFFFH") of the 16-bit down-counter, the 16-bit down-counter stops count
operation with "FFFFH".
When under flow interrupt request flag bit (UF) of timer control status register (TMCSR) is set to "1" in
under flow of 16-bit down counter ("0000H" → "FFFFH") and under flow interrupt request enable bit
(INTE) is set to "1", interrupt request is output.
The TOT pin can output rectangular waveforms indicating that counting is going on.
● Software trigger operation
If the count enable bit (CNTE) of the timer control status register (TMCSR) is set to "1", setting the
software trigger bit (TRG) to "1" causes count operation to start.
Figure 13.6-7 Count Operation in One-shot Mode (Software trigger operation)
Count clock
Reload
data
Counter
-1
0000H
FFFFH
Reload
data
-1
0000H
FFFFH
Data load signal
UF bit
CNTE bit
TRG bit
T*
TOT pin
Activate trigger input wait
T : Machine cycle (1 cycle of machine clock)
* : It takes 1T time from trigger input to reload data loading.
287
CHAPTER 13 16-BIT RELOAD TIMER
● External trigger input operation
When the count enable bit (CNTE) of timer status control register (TMCSR) is set to "1" and the valid edge
(setable from rising, falling and both edge) of trigger input which is set in operating mode setting bit
(MOD2, MOD1 and MOD0) is input to TIN pin, count operation is started.
Figure 13.6-8 Count Operation in One-shot Mode (External trigger operation)
Count clock
Reload
data
Counter
-1
0000H
FFFFH
Reload
data
-1
0000H
FFFFH
Data load signal
UF bit
CNTE bit
TIN bit
2T to 2.5T*
TOT pin
Activate trigger input wait
T : Machine cycle (1 cycle of machine clock)
* : It takes 2T to 2.5T time from external trigger input to reload data loading.
Note:
The width of a trigger pulse input to the TIN pin must be above 2/φ (φ: machine clock frequency).
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CHAPTER 13 16-BIT RELOAD TIMER
● External gate input operation
If the count enable bit (CNTE) of timer control status register (TMCSR) is set to "1", setting the software
trigger bit (TRG) to "1" causes count operation to start.
While a valid level ("L" or "H") of the trigger input, which is preset by the operating mode setting bit
(MOD2, MOD1 and MOD0), is input to the TIN pin, count operation continues.
Figure 13.6-9 Count Operation in One-shot Mode (Software trigger gate input operation)
Internal count clock
Reload data
Counter
-1
0000H FFFFH
-1
-1
Reload data
Data load signal
UF bit
CNTE bit
TRG bit
T*
TIN pin
TOT pin
T : Machine cycle (1 cycle of machine clock)
* : It takes 1 machine cycle time from trigger input to reload data loading.
Activate trigger input wait
Note:
The width of a gate input pulse to the TIN pin must be above 2/φ (φ: machine clock frequency).
289
CHAPTER 13 16-BIT RELOAD TIMER
13.6.3
Event Count Mode
The 16-bit down-counter is counted down every time a valid edge of the pulse input to
the TIN pin is detected, and upon an underflow ("0000H" -> "FFFFH"), an interrupt
request is output. Also the TOT pin can output toggle waveforms or rectangular
waveforms.
■ Event Count Mode
When the count enable bit (CNTE) of timer status control register (TMCSR) is set to "1", software trigger
bit (TRG) is set to "1". In the meantime, the value set in 16-bit reload register (TMRLR) is loaded to 16-bit
down counter and carried out down counter every detection of the valid edge (setable from rising, falling
and both edge) of pulse (external count clock) input to TIN pin. If both the count enable bit (CNTE) and
software trigger bit (TRG) are set to "1" simultaneously, counting down starts immediately when count
operation is enabled.
● Reload mode operation
Upon an underflow ("0000H" -> "FFFFH") of the 16-bit down-counter, the preset value in the 16-bit reload
register (TMRLR) is loaded to the 16-bit down-counter and counting down continues.
When under flow interrupt request flag bit (UF) of timer control status register (TMCSR) is set to "1" in
under flow of 16-bit down counter ("0000H" → "FFFFH") and under flow interrupt request enable bit
(INTE) is set to "1", interrupt request is output to CPU.
The TOT pin can output toggle waveforms that are reversed every time an underflow occurs.
Figure 13.6-10 Count Operation (Event count mode) at Reload Mode
TIN pin
Reload
data
Counter
-1
0000H
Reload
data
Data load signal
UF bit
CNTE bit
TRG bit
T*
TOT pin
T : Machine cycle (1 cycle of machine clock)
* : It takes 1T time from trigger input to reload data loading.
290
-1
0000H
Reload
data
-1
0000H
Reload
data
-1
CHAPTER 13 16-BIT RELOAD TIMER
Note:
The "H" width and "L" width of a trigger pulse input to the TIN pin must be above 4/φ (φ: machine
clock frequency).
● One-shot mode operation
Upon an underflow ("0000H" -> "FFFFH") of the 16-bit down-counter, counter stops count operation,
leaving the 16-bit down-counter value "FFFFH".
When under flow interrupt request flag bit (UF) of timer control status register (TMCSR) is set to "1" in
under flow of 16-bit down counter ("0000H" → "FFFFH") and under flow interrupt request enable bit
(INTE) is set to "1", interrupt request is output to CPU.
The TOT pin can output rectangular waveforms indicating that counting is going on.
Figure 13.6-11 Counter Operation (Event count mode) at One-shot Mode
TIN pin
Reload
data
Counter
-1
0000H FFFFH
Reload
data
-1
0000H FFFFH
Data load signal
UF bit
CNTE bit
TRG bit
T*
TOT pin
Activate trigger input wait
T : Machine cycle (1 cycle of machine clock)
* : It takes 1T time from trigger input to reload data loading.
Note:
The "H" width and "L" width of a trigger pulse input to the TIN pin must be above 4/φ (φ: machine
clock frequency).
291
CHAPTER 13 16-BIT RELOAD TIMER
13.7
16-bit Reload Timer Notes on Use
Notes when 16-bit reload timer is used are shown.
■ 16-bit Reload Timer Notes On Use
● Notes on using programs to set
• When setting a value in the 16-bit reload register (TMRLR), be sure to stop count operation
(TMCSR:CNTE = 0). When reading the 16-bit timer register (TMR), be sure to use the word transfer
instruction (MOVW A, 003AH).
• When changing the count clock setting bits (CSL1, CSL0) of the timer control status register (TMCSR),
be sure to stop count operation (TMCSR:CNTE = 0).
● Precautions on interrupt
When the under flow interrupt request flag bit (UF) of the timer control status register (TMCSR) is set to
"1" and the underflow interrupt request enable bit (INTE) is set to "1", return from interrupt processing
does not occur. The underflow interrupt request flag bit (UF) must be cleared to "0".
292
CHAPTER 14
INPUT/OUTPUT TIMER
This chapter explains the movement of the I/O timer.
14.1 Outline of I/O Timer
14.2 Block Diagram of I/O Timer
14.3 List of Register in I/O Timer
14.4 Interruption of I/O Timer
14.5 Operation Explanation of I/O Timer
293
CHAPTER 14 INPUT/OUTPUT TIMER
14.1
Outline of I/O Timer
The I/O timer consists of one 16-bit free-run timer, two input capture units and two
output compare units.
■ Configuration
● 16-bit free-run timer ( 1)
The 16-bit free-run timer consists of a 16-bit up-counter, control register, 16-bit compare clear register, and
prescaler. The output value of the counter is used as the base time (base timer) of the input capture.
The counter operation clock is optional from eight kinds.
Eight types of internal clocks (φ , φ/2, φ/4, φ/8, φ/16, φ/32, φ/64, φ/128)
F: Machine clock frequency
An interrupt can be generated by an overflow of the counter value or a compare match with the compare
clear register (Compare match requires mode setting).
The counter value can be initialized to "0000H" by a reset, soft clear, or a compare match with the compare
clear register.
● Input capture ( 2)
The input capture consists of the capture register and control register corresponding to six external input
pins. It can detect an arbitrary edge of the signal input from each external input pin to generate an interrupt
while holding the 16-bit free-run timer value in the capture register.
• A valid edge of the external input signal can be selected from rise, fall, and both
• Two input captures can operate independently
• An interrupt can be generated by detecting a valid edge of an external input signal
● Output compare ( 2)
The output compare consists of two 16-bit compare registers, compare output latches, and control registers.
A match between the 16-bit free-run timer value and compare register value enables the output level to be
reversed and an interrupt to be generated.
Two compare registers can operate independently. Interrupt flag corresponding to each compare register.
An interrupt can be generated by a comparing match.
294
CHAPTER 14 INPUT/OUTPUT TIMER
14.2
Block Diagram of I/O Timer
This section describes block diagram of I/O timer.
■ Block Diagram
Figure 14.2-1 Block Diagram of I/O Timer
φ
Interrupt
#18
IVF
IVFE
STOP
MODE
SCLR
CLK2
CLK1
Divider
CLK0
Clock
16-bit free-run timer
16 bit
Compare clear register
Compare control
16-bit free-run timer
F2MC-16LX Bus
ICRE
ICLR
MSI2 to MSI0
16-bit free-run timer
16-bit free-run timer
Interrupt
#18
TQ
OTE0
TQ
OTE1
CMO
16-bit free-run timer
IOP1
IOP0
IOE1
IOE0
Interrupt
#25
#26
Edge detection
Capture data register 0
EG11
EG10
EG01
Edge detection
Capture data register 1
ICP0
ICP1
ICE0
IC0
EG00
IC1
ICE1
Interrupt
#25
#26
295
CHAPTER 14 INPUT/OUTPUT TIMER
14.3
List of Register in I/O Timer
The list of the register in the I/O timer is explained.
■ List of Register in 16-bit Free-run Timer
Compare clear
register upper
Address: 00003BH
Compare clear
register lower
Address: 00003AH
Timer data
register upper
Address: 00003DH
Timer data
register lower
Address: 00003CH
Timer control
status register upper
Address: 00003FH
bit15 bit14 bit13 bit12 bit11 bit10
296
bit8
CL15 CL14 CL13 CL12 CL11 CL10 CL09 CL08
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CL07 CL06 CL05 CL04 CL03 CL02 CL01 CL00
R/W
(X)
R/W
(X)
CPCLR
Read/Write
Initial value
R/W
(X)
bit15 bit14 bit13 bit12 bit11 bit10
bit9
bit8
T15
T09
T08
TCDT
Read/Write
Initial value
T12
R/W
(X)
Read/Write
Initial value
R/W
(X)
T13
R/W
(X)
CPCLR
R/W
(X)
T14
R/W
(X)
T11
T10
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
T07
T06
T05
T04
T03
T02
T01
T00
TCDT
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
Read/Write
Initial value
bit9
bit8
bit15 bit14 bit13 bit12 bit11 bit10
ECKE
MSI2 MSI1 MSI0 ICLR ICRE
R/W
(0)
Timer control
status register lower
Address: 00003EH
bit9
bit5
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
bit4
bit3
bit2
bit1
bit0
bit7
bit6
IVF
IVFE STOP MODE SCLR CLK2 CLK1 CLK0
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
TCCSH
Read/Write
Initial value
TCCSL
Read/Write
Initial value
CHAPTER 14 INPUT/OUTPUT TIMER
■ List of Register in Input Capture Part
Input capture
data register upper
Address: ch.0 000045H
Address: ch.1 000047H
bit15 bit14 bit13 bit12 bit11 bit10
Input capture control
status register 0/1
Address: 000048H
bit8
IPCP0, IPCP1
CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08
R
(X)
Input capture
data register lower
Address: ch.0 000044H
Address: ch.1 000046H
bit9
R
(X)
bit7
R
(X)
R
(X)
bit6
bit5
R
(X)
R
(X)
bit4
bit3
R
(X)
bit2
Read/Write
Initial value
R
(X)
bit1
bit0
IPCP0, IPCP1
CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00
R
(X)
R
(X)
R
(X)
R
(X)
R
(X)
R
(X)
R
(X)
R
(X)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
Read/Write
Initial value
ICS01
Read/Write
Initial value
■ List of Registers in Output Compare Unit
Output compare register upper
Address: ch.0 00004BH
Address: ch.1 00004DH
bit15 bit14 bit13 bit12 bit11 bit10
OCCP0, OCCP1
R/W
(X)
bit7
R/W
(X)
bit6
R/W
(X)
bit5
R/W
(X)
bit4
R/W
(X)
bit3
R/W
(X)
bit2
Read/Write
Initial value
R/W
(X)
bit1
bit0
OCCP0, OCCP1
OP07 OP06 OP05 OP04 OP03 OP02 OP01 OP00
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
bit15 bit14 bit13 bit12 bit11 bit10
Output compare control
status register upper
Address: ch.1 00004FH
Read/Write
Initial value
R/W
(X)
bit9
bit8
OCSH
CMOD OTE1 OTE0 OTD1 OTD0
R/W
(0)
bit7
Output compare control
status register lower
Address: ch.1 00004EH
bit8
OP15 OP14 OP13 OP12 OP11 OP10 OP09 OP08
R/W
(X)
Output compare register lower
Address: ch.0 00004AH
Address: ch.1 00004CH
bit9
bit6
bit5
R/W
(0)
bit4
R/W
(0)
bit3
R/W
(0)
bit2
Read/Write
Initial value
R/W
(0)
bit1
bit0
OCSL
IOP1 IOP0 IOE1 IOE0
CST1 CST0
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
Read/Write
Initial value
297
CHAPTER 14 INPUT/OUTPUT TIMER
14.3.1
Explanation of Register of 16-bit Free-run Timer
The 16-bit free-run timer has the following three registers:
• Timer data register (TCDT)
• Compare clear register (CPCLR)
• Timer control status register (TCCSL, TCCSH)
■ Timer Data Register (TCDT)
Timer data
register upper
Address: 00003DH
Timer data
register lower
Address: 00003CH
bit15 bit14 bit13 bit12 bit11 bit10
bit9
bit8
T15
T14
T13
T12
T11
T10
T09
T08
TCDT
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
Read/Write
Initial value
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
T07
T06
T05
T04
T03
T02
T01
T00
TCDT
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
Read/Write
Initial value
Register that can read the count value of the 16-bit free-run timer. The counter value is reset to "0000H"
upon reset. A timer value can be set by writing it into this register. Be sure to write a timer value in the stop
state (STOP = 1). Please access this register the word. The following factors are needed for initialization of
16-bit free-run timer.
• Initialization by Reset
• Initialization by clearness (CLR) of control status register
• Initialization by a match between the compare clear register value and the timer counter value (mode
setting is required)
298
CHAPTER 14 INPUT/OUTPUT TIMER
■ Compare Clear Register (CPCLR)
Compare clear
register upper
Address: 00003BH
Compare clear
register lower
Address: 00003AH
bit15 bit14 bit13 bit12 bit11 bit10
bit9
bit8
CL15 CL14 CL13 CL12 CL11 CL10 CL09 CL08
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CL07 CL06 CL05 CL04 CL03 CL02 CL01 CL00
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
CPCLR
Read/Write
Initial value
CPCLR
Read/Write
Initial value
16-bit compare register that is compared with the 16-bit free-run timer. Since the initial value of the register
is undefined, a value must be set before enabling operation. Please access the register the word. When
MODE bit of timer control status register (TCCS) is set to "1" and 16-bit free-run timer value matches this
register value, 16-bit free-run timer value is cleared to "0000H". When 16-bit free-run timer value matches
this register value, compare clear interrupt flag is set. When compare clear interrupt flag is set to "1" and
interrupt operation is enabled, interrupt request is generated to CPU.
■ Timer Control Status Register (TCCSL, TCCSH)
Timer control
status register upper
Address: 00003FH
Timer control
status register lower
Address: 00003EH
bit15 bit14 bit13 bit12 bit11 bit10
ECKE
bit8
MSI2 MSI1 MSI0 ICLR ICRE
R/W
(0)
bit7
bit9
bit6
bit5
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
bit4
bit3
bit2
bit1
bit0
IVF
IVFE STOP MODE SCLR CLK2 CLK1 CLK0
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
TCCSH
Read/Write
Initial value
TCCSL
Read/Write
Initial value
[bit15] ECKE
Bit to select whether an internal clock or external clock is used as the count clock source of the 16-bit
free-run timer. Since the clock is changed immediately after writing into the ECKE bit, be sure to
change the clock when the output compare and input capture is in the stopped state.
ECKE
Meaning of flag
0
Select the internal clock source (initial value)
1
The clock is input from external terminal (P74).
299
CHAPTER 14 INPUT/OUTPUT TIMER
Note:
If an internal clock is selected, the counter clock must be set by bit2 to bit0 (CLK2 to CLK0). This
count clock becomes a base clock. If clock is input from P74, set DDR5:bit6 = 0.
[bit14, bit13] There are undefined bits (A read operation gives an undefined value. A write operation has no effect on
the operation).
[bit12 to bit10] MSI2 to MSI0
Bit to set the number of times the compare clear interrupt be masked. Consists of a 3-bit reload counter.
The counter value is reloaded every time the counter value becomes "000B". The counter value is also
reloaded when writing data into the register. The number of masking times = the number of setting
times (Example: If interrupt processing is to be performed at the third round after masking twice, the
setting value is "010B"). However, if "000B" is set, an interrupt factor is not masked.
[bit9] ICLR
Interrupt request flag for the compare clear. When the compare clear register value and 16-bit free-run
timer value match, the ICLR bit is set to "1". If the interrupt request enable bit (bit8: ICRE) is set, an
interrupt occurs. The ICLR bit is cleared by writing "0". Writing "1" is meaningless. Read modify write
(RMW) instructions always read "1".
ICLR
Meaning of flag
0
No interrupt request (Initial value)
1
Interrupt request
Note:
After "1" is written, the counter value is not initialized to the following count clock when "0" is written
in this bit.
[bit8] ICRE
This bit is interrupt enable bit of compare clear. When the ICRE bit is "1" and the interrupt flag
(bit9:CLR) is set to "1", an interrupt occurs.
ICRE
300
Meaning of flag
0
Interrupt prohibited (initial value)
1
Interruption permission
CHAPTER 14 INPUT/OUTPUT TIMER
[bit7] IVF
This is interrupt request flag of 16-bit free-run timer. When the 16-bit free-run timer overflows, the IVF
bit is set to "1". If the interrupt request enable bit (bit6: IVFE) is set, an interrupt occurs. The IVF bit is
cleared by writing "1". Writing "1" is meaningless. Read modify write (RMW) instructions always read "1".
IVF
Meaning of flag
0
No Interrupt request (initial value)
1
Interrupt request
[bit6] IVFE
This bit is interrupt enable bit of 16-bit free-run timer. When the IVFE bit is "1" and the interrupt flag
(bit7:IVF) is set to "1", an interrupt occurs.
IVFE
Meaning of flag
0
Interrupt prohibited (initial value)
1
Interruption permission
[bit5] STOP
This bit stop 16-bit free-run timer count. 1 Count stop of timer at the time of writing. "0" The count of
the timer begins at the time of writing.
STOP
Meaning of flag
0
Count enable (operating) (initial value)
1
Count disable (stop)
Note:
When the 16-bit free-run timer stops, the output compare operation also stops.
[bit4] MODE
Initializing condition of 16-bit free-run timer is set. If "0", the counter value can be initialized by a reset
or the clear bit (bit3: SCLR). If "1", the counter value can also be initialized by a match with the value
of the compare clear register, as well as by a reset or the clear bit (bit3:SCLR).
MODE
Meaning of flag
0
Initialization by reset and clear bit (initial value)
1
Initialization by reset, clear bit and compare clear register
Note:
The initialization of the counter value takes place at count value change points.
301
CHAPTER 14 INPUT/OUTPUT TIMER
[bit3] SCLR
Bit to initialize the value of the operating 16-bit free-run timer to "0000H". Initializes the counter to
"0000H" at "1" write operation. Writing "0" is meaningless. The read value is always "0". The
initialization of the counter value takes place at count value change points.
SCLR
Meaning of flag
0
No effect (initial value)
1
The counter value is initialized to "0000H".
Note:
When initializing the counter in the timer stop state, write "0000H" into the data register.
[bit2 to bit0] CLK2 to CLK0
Bit to select the count clock of the 16-bit free-run timer. Since the clock is changed immediately after
writing into the CLK, be sure to change the clock when the output compare and input capture is in the
stopped state.
CLK2
CLK1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
φ = Machine clock
302
CLK0
Count
Clock
φ =25MHz
φ =16MHz
φ = 8MHz
φ = 4MHz
φ = 1MHz
0
1
0
1
0
1
0
1
φ
φ/2
φ/4
φ/8
φ / 16
φ / 32
φ / 64
φ /128
40ns
80ns
160ns
320ns
0.64 μs
1.28 μs
2.56 μs
5.12 μs
62.5ns
125ns
0.25 μs
0.5 μs
1 μs
2 μs
4 μs
8 μs
125ns
0.25 μs
0.5 μs
1 μs
2 μs
4 μs
8 μs
16 μs
0.25 μs
0.5 μs
1 μs
2 μs
4 μs
8 μs
16 μs
32 μs
1 μs
2 μs
4 μs
8 μs
16 μs
32 μs
64 μs
128 μs
CHAPTER 14 INPUT/OUTPUT TIMER
14.3.2
Detailed Description of Input Capture Registers
Input capture data register has tow types of register.
• Input capture data registers (IPCP0, IPCP1)
• Input capture control status register (ICS01)
■ Input Capture Data Registers (IPCP0, IPCP1)
The IPCP register holds the value of the 16-bit free-run timer when a valid edge of the corresponding
external pin input waveform is detected. (Use word access. Write operation is not allowed.)
Input capture
data register upper
Address: ch.0 000045H
Address: ch.1 000047H
bit15 bit14 bit13 bit12 bit11 bit10
bit8
IPCP0, IPCP1
CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08
R
(X)
Input capture
data register lower
Address: ch.0 000044H
Address: ch.1 000046H
bit9
R
(X)
bit7
R
(X)
bit6
R
(X)
bit5
R
(X)
bit4
R
(X)
bit3
R
(X)
bit2
Read/Write
Initial value
R
(X)
bit1
bit0
IPCP0, IPCP1
CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00
R
(X)
R
(X)
R
(X)
R
(X)
R
(X)
R
(X)
R
(X)
R
(X)
Read/Write
Initial value
■ Input Capture Control Status Register (ICS01)
Input capture control
Address: 000048H
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
ICS01
Read/Write
Initial value
[bit7, bit6] ICP1, ICP0
These bits are input capture interrupt flag. The input capture sets the ICP1, ICP0 bits to "1" when it
detects valid edges of external input pins. If the interrupt enable bit (ICE1, ICE0) is set, an interrupt
occurs at detection of a valid edge.
ICP1, ICP0 bits are cleared by written "0". Entering "1" has no effect. The read modify write (RMW)
instructions read "1".
ICP1, ICP0
Meaning of flag
0
There is no effective edge detection (initial value)
1
There is effective edge detection.
ICPn: a number denoted by n corresponds to the channel number of the input capture.
303
CHAPTER 14 INPUT/OUTPUT TIMER
[bit5, bit4] ICE1, ICE0
These bits are input capture interrupt enable bit. If the ICE bit is "1", an input capture interrupt occurs
when the interrupt flag (ICP1, ICP0) is set to "1".
ICE1, ICE0
Meaning of flag
0
Interruption prohibited (initial value)
1
Interruption permission
ICEn: a number denoted by n corresponds to the channel number of the input capture.
[bit3 to bit0] EG11, EG10, EG01, EG00
Bit to select a valid edge polarity of the external input. The input capture operation permission is used
combinedly.
EGn1
EGn0
Edge detection polarity
0
0
No edge detection (stop) (initial value)
0
1
Rising edge detection ↑
1
0
Falling edge detection ↓
1
1
Both edges detection ↑ & ↓
EGn1/EGn0: a number denoted by n corresponds to the channel number of the input capture.
304
CHAPTER 14 INPUT/OUTPUT TIMER
14.3.3
Detailed Description of Output Compare Registers
There are following two types of registers in the output compare unit.
• Output compare register (OCCP0/OCCP1)
• Output compare control status register (OCSL, OCSH)
■ Output Compare Register (OCCP0, OCCP1)
Output compare register upper
Address: ch.0 00004BH
Address: ch.1 00004DH
bit15 bit14 bit13 bit12 bit11 bit10
bit8
OCCP0/OCCP1
OP15 OP14 OP13 OP12 OP11 OP10 OP09 OP08
R/W
(X)
Output compare register lower
Address: ch.0 00004AH
Address: ch.1 00004CH
bit9
R/W
(X)
bit7
R/W
(X)
bit6
R/W
(X)
bit5
R/W
(X)
bit4
R/W
(X)
bit3
R/W
(X)
bit2
Read/Write
Initial value
R/W
(X)
bit1
bit0
OCCP0/OCCP1
OP07 OP06 OP05 OP04 OP03 OP02 OP01 OP00
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
Read/Write
Initial value
16-bit length output compare register, which is compared with the 16-bit free-run timer. As the initial value
of the register is undefined, be sure to set a value before activation. Please access the register the word.
When the register value and 16-bit free-run timer value match, a compare signal is generated and the output
compare interrupt flag is set.
Note:
The output compare register must be updated within the compare interrupt routine or in the compare
disabled state so that a compare match and a write operation will not take place simultaneously.
■ Output Compare Control Status Register (OCSL, OCSH)
bit15 bit14 bit13 bit12 bit11 bit10
Output compare control
status register upper
Address: 00004FH
bit8
OCSH
CMOD OTE1 OTE0 OTD1 OTD0
R/W
(0)
bit7
Output compare control
status register lower
Address: 00004EH
bit9
bit6
bit5
R/W
(0)
bit4
R/W
(0)
bit3
R/W
(0)
bit2
Read/Write
Initial value
R/W
(0)
bit1
bit0
OCSL
IOP1 IOP0 IOE1 IOE0
CST1 CST0
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
Read/Write
Initial value
305
CHAPTER 14 INPUT/OUTPUT TIMER
[bit15 to bit13] There are undefined bits (A read operation gives an undefined value. A write operation has no effect on
the operation).
[bit12] CMOD
If pin output is enabled (OTE1=0 or OTE0=1), pin output level inverse operation mode is switched
when there is a comparing match.
When CMOD = 0 (initial value), the output level of the pin corresponding to the compare register is
reversed.
• OUT0: Reverses the level at a match with the compare register 0.
• OUT1: Reverses the level at a match with the compare registers 0 and 1.
When CMOD = 1, output compare register 0 reverses the output level as when CMOD = 0. However,
the output level of the pin corresponding to the output compare register 1 (OUT1) is reversed both at a
match with output compare register 0 and a match with output compare register 1. When the output
compare registers 0 and 1 have the same value, operation is the same as when one output compare
register only is used.
• OUT0: Reverses the level at a match with the output compare register 0.
• OUT1: When the output compare registers 0 and 1 match, the level is reversed.
[bit11, bit10] OTE1, OTE0
Bit to enable the pin output of the output compare.
OTE1, OTE0
Meaning of flag
0
Operates as a general-purpose port (initial value).
1
Becomes the output compare pin output.
OTE1: Corresponding to output compare 1
OTE0: Corresponding to output compare 0
[bit9, bit8] OTD1, OTD0
Used to change the pin output level when the pin output of the output compare status register is enabled.
The initial value of the compare pin output is "0". To perform a write operation, first, stop the compare
operation. At read operation, the output compare pin output value can be read.
OTD1, OTD0
Meaning of flag
0
Sets the compare pin output to "0" (initial value).
1
Sets the compare pin output to "1".
OTD1: Corresponding to output compare 1
OTD0: Corresponding to output compare 0
306
CHAPTER 14 INPUT/OUTPUT TIMER
[bit7, bit6] IOP1, IOP0
These bits are output compare interrupt flag. When the values of the output compare registers match
that of the 16-bit free-run timer, it is set to "1". Setting the IOP1 and IOP0 bits to "1" when the interrupt
request bit (IOE1, IOE0) is enabled, an output compare interrupt occurs. The IOP1 and IOP0 bits are
cleared by writing "0". Writing "1" is meaningless. The read modify write (RMW) instructions read "1".
IOP1, IOP0
Meaning of flag
0
No output compare match (initial value)
1
Output compare match
IOP1: Corresponding to output compare 1
IOP0: Corresponding to output compare 0
[bit5, bit4] IOE1, IOE0
These bits are output compare interrupt enable bit. Setting the interrupt flag (IOP1, IOP0) to "1" when
the IOE1 or IOE0 bit is "1", an output compare interrupt occurs.
IOE1, IOE0
Meaning of flag
0
Output compare interruption prohibited (initial value)
1
Output compare interruption permission
IOE1: Corresponding to output compare 1
IOE0: Corresponding to output compare 0
[bit3, bit2] Undefined bits
There are undefined bits (A read operation gives an undefined value. A write operation has no effect on
the operation).
[bit1, bit0] CST1, CST0
These bits are synchronizing enable bit with 16-bit free-run timer. The output compare register value
and output data register value must be set before enabling compare operation.
CST1, CST0
Meaning of flag
0
Disabling compare operation (initial value)
1
Enabling Operations
CST1: Corresponding to output compare 1
CST0: Corresponding to output compare 0
Note:
The output compare is synchronized to the 16-bit free-run timer. Therefore, if the 16-bit free-run
timer stops, compare operation also stops.
307
CHAPTER 14 INPUT/OUTPUT TIMER
14.4
Interruption of I/O Timer
The interruption of the following I/O timer is explained.
• Interruption of 16-bit free-run timer
• Interruption of input capture
• Interruption of Output compare
■ Interruption of I/O Timer
● Interruption of 16-bit free-run timer
The 16-bit free-run timer can generate an interrupt request by causing the 16-bit free-run timer itself to
overflow or be cleared.
● Interruption of input capture
The input capture can generate an interrupt request by detecting a valid edge of the external input pin. Also
supports for extended intelligent I/O service (EI2OS).
● Interruption of Output compare
The output compare can generate an interrupt request by a match between the output compare register
value and the 16-bit free-run timer value. Also supports for extended intelligent I/O service (EI2OS).
308
CHAPTER 14 INPUT/OUTPUT TIMER
14.4.1
Interruption of 16-bit Free-run Timer
The 16-bit free-run timer can generate an interrupt request by causing the 16-bit freerun timer itself to overflow or be cleared.
■ Interruption of 16-bit Free-run Timer
The interrupt control bits and interrupt causes of the 16-bit free-run timer are as shown in Table 14.4-1 .
Table 14.4-1 Interrupt Control Bit and Interrupt Factor of 16-bit Free-run Timer
Interrupt
cause
Interrupt flag bit
Interrupt enable bits
16-bit free-run
timer clear
Timer control status register higher (TCCSH)
16-bit free-run
timer
overflow
Timer control status register lower (TCCSL)
Compare clear interrupt
request flag bit
(ICLR)
16-bit free-run timer
interrupt flag bit
(IVF)
Compare clear interrupt
enable bits
(ICRE)
Clear a flag
• Writing "0" into the compare clear interrupt
request flag bit (ICLR)
• Reset
• Writing "0" into the 16-bit free-run timer
interrupt request flag bit (IVF)
• Reset
16-bit free-run timer
interrupt enable bit
(IVFE)
In the 16-bit free-run timer, the interrupt flag bit is set to "1" by an interrupt causes shown in Table 14.4-1 .
In this case, if the interrupt enable bit is set to "1", an interrupt request is output to the interrupt controller.
■ Interruption of 16-bit Free-run Timer and EI2OS
Table 14.4-2 shows interrupt and EI2OS of the 16-bit free-run timer.
Table 14.4-2 Interruption of 16-bit Free-run Timer and EI2OS
Channel
Interrupt
number
Interrupt control
registers
Address in vector table
EI2OS
Register
Name
Address
Low
High
Bank
ICR03
0000B3H
FFFFB4H
FFFFB5H
FFFFB6H
Free-run timer
(overflow)
#18
Free-run timer
(clearness)
: Available
309
CHAPTER 14 INPUT/OUTPUT TIMER
14.4.2
Interruption of Input Capture
The input capture can generate an interrupt request by detecting a valid edge of the
external input pin. Also supports for extended intelligent I/O service (EI2OS).
■ Interruption of Input Capture
The interrupt control bits and interrupt causes of the input capture are as shown in Table 14.4-3 .
Table 14.4-3 Interrupt Control Bits and Interrupt Causes of Input Capture
Interrupt cause
Effective edge of
external input
terminal
Interrupt flag bit
Interrupt enable bits
Clear a flag
Input capture control status register (ICS01)
ICP0
ICE0
ICP1
ICE1
• "0" is written to the ICP0 bit
and the ICP1 bit.
• Reset
In the input capture, the interrupt flag bit is set to "1" by an interrupt causes shown in Table 14.4-3 . In this
case, if the interrupt enable bit is set to "1", an interrupt request is output to the interrupt controller.
■ Interruption of Input Capture and EI2OS
Table 14.4-4 shows interrupt and EI2OS of input capture.
Table 14.4-4 Interruption and EI2OS of Input Capture
Interrupt control registers
Channel
Input
capture 0
Interrupt
number
Register
Name
EI2OS
Address
#25
ICR07
Input
capture 1
#26
Address in Vector Table
Low
High
Bank
FFFF98H
FFFF99H
FFFF9AH
FFFF94H
FFFF95H
FFFF96H
0000B7H
: Can be used when interrupt causes that share input vectors are not used.
■ EI2OS Functions of Input Capture
The input capture has a circuit supporting EI2OS. Therefore, EI2OS can be activated by a valid edge of the
external input pin.
310
CHAPTER 14 INPUT/OUTPUT TIMER
14.4.3
Interruption of Output Compare
The output compare can generate an interrupt request by a match between the compare
register value and the 16-bit free-run timer value. Also supports for extended intelligent
I/O service (EI2OS).
■ Interruption of Output Compare
The interrupt control bits and interrupt causes of the input compare are as shown in Table 14.4-5 .
Table 14.4-5 Interrupt Control Bits and Interrupt Causes of Output Compare
Output compare control status register lower (OCSL)
Interrupt cause
Interrupt flag bits Interrupt enable bits
Match between output compare register
value and 16-bit free-run timer value
IOP0
IOE0
IOP1
IOE1
Clear a flag
• "0" writing into IOP0 and IOP1 bits
• Reset
In the output capture, the interrupt flag bit is set to "1" by an interrupt causes shown in Table 14.4-5 . In
this case, if the interrupt enable bit is set to "1", an interrupt request is output to the interrupt controller.
■ Interrupt and EI2OS of Output Compare
Table 14.4-6 shows interrupt and EI2OS of the output compare.
Table 14.4-6 Interrupt and EI2OS of Output Compare
Interrupt control registers
Channel
Output compare
0,1
Interrupt
number
#29
Address in Vector Table
EI2OS
Register
Name
Address
Low
High
Bank
ICR09
0000B9H
FFFF88H
FFFF89H
FFFF8AH
: Available
■ EI2OS Function of Output Compare
The output compare has a circuit supporting EI2OS. Therefore, EI2OS can be activated by a match between
the output compare register value and 16-bit free-run timer value.
311
CHAPTER 14 INPUT/OUTPUT TIMER
14.5
Operation Explanation of I/O Timer
The movement of the I/O timer is explained.
■ Operation Explanation
● 16-bit free-run timer
The 16-bit free-run timer starts counting at the counter value of "0000H" when a reset has been released.
This counter value is used as the base time of the output compare and input capture.
● Input capture
The input capture generates an interrupt by including the value of the 16-bit free-run timer in the capture
register when it detects a valid edge that is preset.
● Output compare
The output compare compares the preset output compare register value and 16-bit free-run timer value and
when they match, it sets an interrupt flag and generates an interrupt.
312
CHAPTER 14 INPUT/OUTPUT TIMER
14.5.1
16-bit Free-run Timer
The 16-bit free-run timer starts counting at the counter value of "0000H" when a reset
has been released. This counter value is used as the base time of the output compare
and input capture.
■ Explanation of Operation of 16-bit Free-run Timer
The counter value is cleared by the following condition.
• At over flow generating
• At a compare match with the compare clear register value (The mode setting is necessary)
• Writing "1" into the SCLR bit of the TCCS register during operation
• "0000H" writing in TCDT in stop timer
An interrupt can be generated when an overflow occurs or when a match with the compare clear register
value (A compare match interrupt requires mode setting).
Figure 14.5-1 Counter Clear by Overflow
Counter value
FFFF H
BFFF H
7FFF H
3FFF H
0000 H
Time
Reset
Interrupt
Figure 14.5-2 Counter Clear which is Compare Matched with Compare Clear Register Value
Counter value
FFFF H
BFFF H
Match
Match
7FFF H
3FFF H
0000 H
Time
Reset
Output compare
register
BFFF H
Interrupt
313
CHAPTER 14 INPUT/OUTPUT TIMER
● Clear timing of 16-bit free-run timer
The counter is cleared by a reset, software or a match with the compare clear register. Counter clear by a
reset or software takes place as soon as a clear occurs. However, counter clear takes place in
synchronization to count timing.
Figure 14.5-3 Clear timing of Free-run Timer
φ
Compare clear register
N
Compare match
Counter value
N
0000
● Count timing of 16-bit free-run timer
The 16-bit free-run timer is counted up by the input clock (internal or external clock). When an external
clock is selected, this timer is counted up at a rising edge.
Figure 14.5-4 Count Timing of 16-bit Free-run Timer
φ
External clock input
Count clock
Counter value
314
N
N+1
CHAPTER 14 INPUT/OUTPUT TIMER
14.5.2
Input Capture
The input capture generates an interrupt by including the value of the 16-bit free-run
timer in the capture register when it detects a valid edge that is preset.
■ Operation of Input Capture
Figure 14.5-5 Example of Taking Timing of Input Capture
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Reset
IC0
IC1
Example of IC
Undefined
Data register 0
Data register 1
Undefined
Data register example
Undefined
3FFFH
BFFFH
BFFFH
7FFFH
Capture 0 interrupt
Capture 1 interrupt
Example of capture
Interrupt by valid edge again
Capture 0=Rising edge
Interrupt by software
Capture 1=Falling edge
Example of capture=Both edge (as an example)
● Input timing of input capture
Figure 14.5-6 Capture Timing which Input Signal Confronts
φ
Counter value
N
N+1
Input capture input
Valid edge
Capture signal
Capture register
N+1
Interrupt
315
CHAPTER 14 INPUT/OUTPUT TIMER
14.5.3
Output Compare
The output compare compares the preset compare register value and 16-bit free-run
timer value and when they match, it sets an interrupt flag and generates an interrupt.
■ Explanations for Output Compare Operation
Figure 14.5-7 Example of an Operating Waveform when Using Output Compare Registers 0, 1
(Initial value of output is "0")
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
Time
0000H
Reset
Output compare register 0 value
Output compare register 1 value
BFFFH
7FFFH
Compare 0 interrupt
Compare 1 interrupt
Note:
The compare register must be updated within the compare interrupt routine or in the compare
disabled state so that a compare match and a write operation will not take place simultaneously.
● Output compare timing
The output compare can generate a compare match signal, reverse the output and generate an interrupt
when the free-run timer and the preset compare register value match. The output is reversed in
synchronization to count timing of the counter.
Figure 14.5-8 Compare Interrupt Timing
φ
Counter value
Output compare register value
Compare match
Interrupt
316
N
N+1
N
CHAPTER 15
PPG TIMER
This chapter explains the PPG timer.
15.1 Overview of PPG Timer
15.2 Block Diagram of PPG Timer
15.3 Register of PPG Timer
15.4 Explanation of Operation of PPG Timer
15.5 Notes on Use of PPG Timer
15.6 Example of Using PPG Timer
317
CHAPTER 15 PPG TIMER
15.1
Overview of PPG Timer
The PPG timer consists of the prescaler, one 16-bit down-counter, one 16-bit data
register with a cycle setting buffer, and a 16-bit compare register with a duty setting
buffer, and the pin control unit.
The PPG timer can output pulses synchronized to the external or software trigger. The
period and duty of the output pulse can be changed freely by updating two 16-bit
register values.
■ Function of PPG Timer
● PWM Functions
The PPG timer can output pulses programmable by updating the values of the registers described above in
synchronization to the trigger.
Can also be used as a D/A converter by an external circuit.
● One-shot function
By detecting an edge of the trigger input, a single pulse can be output.
● Pin control
The PPG timer controls the following terminals.
• By a duty match, set to "1" (Priority)
• By counter borrow, reset to "0"
• Since output fixed mode is provided, all "L" (or all "H") can easily be output
• The polarity is specifiable
● 16-bit down counter
The counter operation clock can select from eight kinds. There are eight kinds of internal clocks (φ , φ/2,
φ/4, φ/8, φ/16, φ/32, φ/64, φ/128).
φ : Machine clock
The counter value can be initialized to "FFFFH" by a reset or counter borrow.
● Interrupt request
The PPG timer generates an interrupt request when:
• Timer activation
• Counter borrow occurs (cycle match).
• Duty match generating
• Counter borrow (cycle match) or a duty match occurs.
By an external trigger, more than one channel can be activated concurrently. Moreover, the reactivation
under the operation can be set.
318
CHAPTER 15 PPG TIMER
■ Interruption of PPG Timer and EI2OS
Table 15.1-1 shows interrupt and EI2OS of the PPG timer.
Table 15.1-1 Interruption of PPG Timer and EI2OS
Channel
Interrupt
number
Interrupt level setting
register
Address in Vector Table
EI2OS
Register
Name
Address
Low
High
Bank
PPG timer 0
#27(1BH)
ICR08
0000B8H
FFFF90H
FFFF91H
FFFF92H
PPG timer 1
#31(1FH)
ICR10
0000BAH
FFFF80H
FFFF81H
FFFF82H
: Possible to use
319
CHAPTER 15 PPG TIMER
15.2
Block Diagram of PPG Timer
Block diagram of PPG timer is described.
■ Block Diagram of PPG Timer
Figure 15.2-1 shows block diagram of PPG timer.
Figure 15.2-1 Block Diagram of PPG Timer
Prescaler
1/1
PCSR
1/2
PDUT
1/4
1/8
1/16
Load
1/32
CK
1/64
PCNT
16-bit down counter
CMP
1/128
Start
Borrow
PPG mask
Machine clock
φ
S
Q
PPG output
R
reversed bit
Enable
Interrupt
selection
Soft trigger
320
Interrupt
CHAPTER 15 PPG TIMER
15.3
Register of PPG Timer
The list of the register of the PPG timer is described.
■ Register of PPG Timer
Figure 15.3-1 shows the list of the register of the PPG timer.
Figure 15.3-1 The List of the Register of the PPG Timer
PPG control status
register upper
Address: ch.0 000077H
Address: ch.1 00007FH
bit15 bit14 bit13 bit12 bit11 bit10
PPG control status
register lower
Address: ch.0 000076H
Address: ch.1 00007EH
R/W
(0)
bit7
R/W
(0)
bit6
bit5
R/W
(0)
bit4
R/W
(0)
bit3
R/W
(0)
bit2
Read/Write
Initial value
R/W
(X)
bit1
bit0
PCNTL0
PCNTL1
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
Read/Write
Initial value
R/W
(0)
bit9
bit8
PDCRH0
PDCRH1
DC15 DC14 DC13 DC12 DC11 DC10 DC09 DC08
R
(1)
bit7
R
(1)
bit6
R
(1)
bit5
R
(1)
bit4
R
(1)
bit3
R
(1)
bit2
Read/Write
Initial value
R
(1)
bit1
bit0
PDCRL0
PDCRL1
DC07 DC06 DC05 DC04 DC03 DC02 DC01 DC00
R
(1)
R
(1)
R
(1)
R
(1)
R
(1)
R
(1)
R
(1)
R
(1)
bit15 bit14 bit13 bit12 bit11 bit10
bit9
Read/Write
Initial value
bit8
PCSRH0
PCSRH1
CS15 CS14 CS13 CS12 CS11 CS10 CS09 CS08
W
(X)
PPG cycle set register lower
Address: ch.0 000072H
Address: ch.1 00007AH
R/W
(0)
bit15 bit14 bit13 bit12 bit11 bit10
R
(1)
PPG cycle set register upper
Address: ch.0 000073H
Address: ch.1 00007BH
PCNTH0
PCNTH1
IREN IRQF IRS1 IRS0 POEN OSEL
R/W
(0)
PPG down counter
register lower
Address: ch.0 000070H
Address: ch.1 000078H
bit8
CNTE STGR MDSE RTRG CKS2 CKS1 CKS0 PGMS
R/W
(0)
PPG down counter
register upper
Address: ch.0 000071H
Address: ch.1 000079H
bit9
W
(X)
bit7
W
(X)
bit6
W
(X)
bit5
W
(X)
bit4
W
(X)
bit3
W
(X)
bit2
bit1
CS07 CS06 CS05 CS04 CS03 CS02 CS01 CS00
W
(X)
W
(X)
W
(X)
W
(X)
W
(X)
W
(X)
W
(X)
Read/Write
Initial value
W
(X)
W
(X)
bit0
PCSRL0
PCSRL1
Read/Write
Initial value
(Continued)
321
CHAPTER 15 PPG TIMER
(Continued)
PPG duty set register upper
Address: ch.0 000075H
Address: ch.1 00007DH
bit15 bit14 bit13 bit12 bit11 bit10
W
(X)
bit7
W
(X)
bit6
W
(X)
bit5
W
(X)
bit4
W
(X)
bit3
W
(X)
PDUTH0
PDUTH1
bit2
W
(X)
W
(X)
W
(X)
W
(X)
W
(X)
W
(X)
Read/Write
Initial value
W
(X)
bit1
DU07 DU06 DU05 DU04 DU03 DU02 DU01 DU00
W
(X)
322
bit8
DU15 DU14 DU13 DU12 DU11 DU10 DU09 DU08
W
(X)
PPG duty set register lower
Address: ch.0 000074H
Address: ch.1 00007CH
bit9
W
(X)
bit0
PDUTL0
PDUTL1
Read/Write
Initial value
CHAPTER 15 PPG TIMER
15.3.1
Explanation of Register of PPG Timer
In the PPG timer, there are the following four registers.
• PPG control status register (PCNT0, PCNT1)
• PPG down counter register (PDCR0, PDCR1)
• PPG cycle set register (PCSR0, PCSR1)
• PPG duty set register (PDUT0, PDUT1)
■ PPG Control Status Register (PCNT)
Figure 15.3-2 shows the bit configuration of the PPG control status register (PCNT0, PCNT1).
Figure 15.3-2 Bit Configuration of PPG Control Status Register (PCNT0, PCNT1)
bit15 bit14 bit13 bit12 bit11 bit10
PPG control status register upper
Address: ch.0 000077H
Address: ch.1 00007FH
bit9
bit8
CNTE STGR MDSE RTRG CKS2 CKS1 CKS0 PGMS
R/W
(0)
PPG control status register lower
Address: ch.0 000076H
Address: ch.1 00007EH
R/W
(0)
bit7
R/W
(0)
bit6
R/W
(0)
bit5
R/W
(0)
bit4
R/W
(0)
bit3
R/W
(0)
bit2
IREN IRQF IRS1 IRS0 POEN OSEL
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
Read/Write
initial value
R/W
(X)
bit1
R/W
(0)
R/W
(0)
PCNTH0
PCNTH1
bit0
PCNTL0
PCNTL1
Read/Write
initial value
[bit15] CNTE: Timer permission bit
This bit is 16-bit down counter operating enable bit.
CNTE
Timers permission
0
Stop (initial value)
1
Permission
[bit14] STGR: Software trigger bit
The software trigger hangs by writing "1" in this bit.
The reading value of the STGR bit is always "0".
[bit13] MDSE: Mode selection bit
Select either PWM operation that outputs pulses continuously or the one-shot operation that outputs a
single pulse. Rewrite during operation is not allowed.
MDSE
Mode selection
0
PWM operation (initial value)
1
One-shot operation
323
CHAPTER 15 PPG TIMER
[bit12] RTRG: Reactivation permission bit
Bit to enable reactivation by a software trigger. Rewrite during operation is not allowed.
RTRG
Reactivation permission
0
Reactivation interdiction (initial value)
1
Reactivation permission
[bit11 to bit9] CKS2 to CKS0: Counter clock selection bits
The count clock of 16 bit down counter is selected. Rewrite during operation is not allowed.
CKS2
CKS1
CKS0
Cycle
0
0
0
φ (initial value)
0
0
1
φ /2
0
1
0
φ /4
0
1
1
φ /8
1
0
0
φ /16
1
0
1
φ /32
1
0
1
φ /64
1
1
1
φ /128
φ : Machine clock
[bit8] PGMS:PPG power output mask selection bit
By writing "1" into this bit, the PPG output can be set to "0" or "1", regardless of the mode setting,
cycle setting value, and duty setting value.
The table below shows the output level of the PPG timer when "1" is written into PGMS.
Polarity
PPG output
Normal Polarity
"L"
Inversion Polarity
"H"
To output all "H" at normal polarity or all "L" at reversed polarity, write the same value into the cycle
setting register and duty setting register. This enables the reverse of the above mask values to be output.
324
CHAPTER 15 PPG TIMER
[bit7, bit6] It is an undefined bit.
The value written into this bit does not affect operation.
[bit5] IREN: Interrupt request enable bit
This bit is PPG timer interrupt enable bit. When the IREN bit is "1" and the interrupt flag (IRQF of bit4)
is set to "1", an interrupt occurs.
IREN
Interrupt request enable
0
Interrupt disabled (initial value)
1
Interruption permission
[bit4] IRQF: Interruption demand flag
If IREN of bit5 is set to "enabled" and an interrupt selected by IRS1, IRS0 of bit3, bit2, the IRQF bit is
set and an interrupt request to the CPU occurs.
The IRQF bit can be read/written. Clear is performed only when "0" is written. If "1" is tried to be
written, the bit remains unchanged. The value read by read modify write (RMW) instructions is always
"1", regardless of the bit value.
[bit3, bit2] IRS1 and IRS0:Interruption factor selection bit
The factor to set bit4 IRQF is selected.
IRS1
IRS0
Edge selection
0
0
Software trigger or valid trigger input (initial value)
0
1
Counter borrow (cycle match)
1
0
Normal polarity PRG ↑ or reversed polarity PPG ↓ (duty match)
1
1
Counter borrow, normal polarity PPG ↑ or reversed polarity PPG ↓
[bit1] POEN: Output enable bit
Setting to "1" causes the PPG output to be output from the pin.
POEN
PPG output enable
0
General-purpose port (initial value)
1
PPG Output Pin
[bit0] OSEL:PPG power output polarity specification bit
The polarity of the PPG power output is set.
OSEL
PPG power output polarity
0
Normal Polarity (initial value)
1
Reversing polarity
325
CHAPTER 15 PPG TIMER
Combination with bit9 PGMS results in the following.
PGMS
OSEL
PPG output
0
0
Normal Polarity (initial value)
0
1
Reversing polarity
1
0
Output "L" fixation
1
1
Output "H" fixation
Polarity
Reset
Duty match
Normal Polarity
"L" output
Reversing polarity
"H" output
Counter match
■ PPG Down Counter Register (PDCR)
The PDCR register can read the value of 16 bit down counter.
Please access the PDCR register by 16 bit data.
Figure 15.3-3 shows the bit configuration of PPG down counter register (PDCR).
Figure 15.3-3 Bit Configuration of PPG Down Counter Register (PDCR)
PPG down counter register upper
Address: ch.0 000071H
Address: ch.1 000079H
bit15 bit14 bit13 bit12 bit11 bit10
bit9
bit8
PDCRH0
PDCRH1
DC15 DC14 DC13 DC12 DC11 DC10 DC09 DC08
R
(1)
PPG down counter register lower
Address: ch.0 000070H
Address: ch.1 000078H
R
(1)
bit7
R
(1)
bit6
R
(1)
bit5
R
(1)
bit4
R
(1)
bit3
R
(1)
bit2
Read/Write
Initial value
R
(1)
bit1
bit0
DC07 DC06 DC05 DC04 DC03 DC02 DC01 DC00
R
(1)
R
(1)
R
(1)
R
(1)
R
(1)
R
(1)
R
(1)
R
(1)
PDCRL0
PDCRL1
Read/Write
Initial value
■ PPG Cycle Set Register (PCSR)
The PCSR register is a register with a buffer that sets cycle. Transfer from the buffer takes place by a
counter borrow.
When initializing and updating the cycle setting register, be sure to perform a write operation to the duty
setting register after writing to the period setting register.
Please access the PCSR register by 16 bit data.
Figure 15.3-4 shows the bit configuration of the PPG cycle set register (PCSR).
326
CHAPTER 15 PPG TIMER
Figure 15.3-4 Bit Configuration of PPG Cycle Set Register (PCSR)
PPG cycle set register upper
Address: ch.0 000073H
Address: ch.1 00007BH
bit15 bit14 bit13 bit12 bit11 bit10
bit8
PCSRH0
PCSRH1
CS15 CS14 CS13 CS12 CS11 CS10 CS09 CS08
W
(X)
PPG cycle set register lower
Address: ch.0 000072H
Address: ch.1 00007AH
bit9
W
(X)
bit7
W
(X)
bit6
W
(X)
bit5
W
(X)
bit4
W
(X)
bit3
W
(X)
bit2
Read/Write
Initial value
W
(X)
bit1
bit0
PCSRL0
PCSRL1
CS07 CS06 CS05 CS04 CS03 CS02 CS01 CS00
W
(X)
W
(X)
W
(X)
W
(X)
W
(X)
W
(X)
W
(X)
Read/Write
Initial value
W
(X)
■ PPG Duty Set Register (PDUT)
The PDUT register is a register with a buffer that sets duty. Transfer from the buffer takes place by a
counter borrow.
If the cycle setting register and duty setting register are set to the same value, all "H" is output at normal
polarity and all "L" is output at reversed polarity.
Please do not set the value which becomes PCSR<PDUT. The PPG output becomes irregular.
Please access the PDUT register by 16 bit data.
Figure 15.3-5 shows the bit configuration of PPG duty set register (PDUT).
Figure 15.3-5 Bit Configuration of PPG Duty Set Register (PDUT)
PPG duty set register upper
Address: ch.0 000075H
Address: ch.1 00007DH
bit15 bit14 bit13 bit12 bit11 bit10
bit8
PDUTH0
PDUTH1
DU15 DU14 DU13 DU12 DU11 DU10 DU09 DU08
W
(X)
PPG duty set register lower
Address: ch.0 000074H
Address: ch.1 00007CH
bit9
W
(X)
bit7
W
(X)
bit6
W
(X)
bit5
W
(X)
bit4
W
(X)
bit3
W
(X)
bit2
bit1
DU07 DU06 DU05 DU04 DU03 DU02 DU01 DU00
W
(X)
W
(X)
W
(X)
W
(X)
W
(X)
W
(X)
W
(X)
Read/Write
Initial value
W
(X)
W
(X)
bit0
PDUTL0
PDUTL1
Read/Write
Initial value
327
CHAPTER 15 PPG TIMER
15.4
Explanation of Operation of PPG Timer
The movement of the PPG timer is explained.
■ PWM Operation
In PWM operation, pulses can be output continuously after an activation trigger is detected. The cycle of
the output pulse can be controlled by changing the value of PCSR. The duty ratio can be controlled by
changing the value of PDUT.
● For the reactivation interdiction
Figure 15.4-1 Timing of PWM Operation Reactivation Interdiction
Trigger is ignored.
Rising edge detection
Activation
trigger
m
n
0
PPG
(1)
(2)
T: Count clock cycle
m: PCSR value
n: PDUT value
(1) = T(n+1) μs
(2) = T(m+1) μs
● At the reactivation permission
Figure 15.4-2 Timing of PWM Operation Reactivation Permission
Rising edge detection
Reactivate by trigger.
Activation
trigger
m
n
0
PPG
(1)
(2)
(1) = T(n+1) μs
(2) = T(m+1) μs
T: Count clock cycle
m: PCSR value
n: PDUT value
Note:
After writing data into PCSR, be sure to perform a write operation for PDUT.
328
CHAPTER 15 PPG TIMER
■ One-shot Operation
In one-shot mode, a single pulse of any width can be output by a trigger. If reactivation is enabled, the
counter is reloaded when an activation trigger is detected during operation.
● For the reactivation interdiction
Figure 15.4-3 Timing of Single Shot Operation Reactivation Prohibition
Rising edge detection
Trigger is ignored.
Activation
trigger
m
n
0
PPG
(1)
(2)
T: Count clock cycle
m: PCSR value
n: PDUT value
(1) = T(n+1) μs
(2) = T(m+1) μs
● At the reactivation permission
Figure 15.4-4 Timing of Single Shot Operation Reactivation Permission
Rising edge detection
Reactivate by trigger.
Activation
trigger
m
n
0
PPG
(1)
(2)
(1) = T(n+1) μs
(2) = T(m+1) μs
T: Count clock cycle
m: PCSR value
n: PDUT value
329
CHAPTER 15 PPG TIMER
■ Interrupt Factor and Timing
● Interrupt factor and timing
A maximum of 2.5T (T: count clock cycle) is required from the time when an activation trigger is detected
to when the counter value is loaded.
Figure 15.4-5 Interruption Output Factor and Timing
Activation
trigger
Load
max.2.5T
Clock
Count value
XXXXH
0003H
0002H
0001H
0000H
0003H
PPG
Interrupt
Software trigger
Compare match
Borrow
● Example of PWM output all "L" or all "H"
Figure 15.4-6 Example of PWM Output All "L" or All "H"
PPG
Reducing
the duty value
sequentlly
"1" is written to PGMS (mask bit) by the
interrupt causing a borrow. When "0" is
written to PGMS (mask bit) by the interrupt
causing a borrow, the PPG wave can be
outputted without outputting.
PPG
Decreasing
the duty value
sequentlly
330
By the interrupt causing a compare
match, the same value is written to the
duty set register and cycle set register.
CHAPTER 15 PPG TIMER
15.5
Notes on Use of PPG Timer
The notes on use of the PPG timer is explained.
■ Notes on Settings
● After writing data into PPG cycle setting register (PCSR), be sure to perform a write operation to the
PPG duty setting register (PDUT). PCSR register alone cannot be updated. Use word transfer
instructions (such as MOVW A, dir) to access the PCSR and PDUT registers.
● The value written into the PPG duty setting register (PDUT) must be smaller than the one written into
the PPG cycle setting register (PCSR). Otherwise, error might occur during PPG output.
● The CKS2, CKS1 and CKS0 bits of PPG control status register (PCNT) must be updated when PPG is
in the stopped state (PCNT:CNTE = 0).
331
CHAPTER 15 PPG TIMER
15.6
Example of Using PPG Timer
The example of using the PPG timer is explained.
■ Sample Program of PPG Timer
● Overview of Operation
PPG timer 0 outputs 160 kHz and waveform of 60% of duty.
The timer is used in PWM mode to generate interrupts repeatedly.
The timer starts with the software trigger.
EI2OS is not used.
The machine clock uses 16 MHz and the count clock uses 62.5ns.
● Sample program
ICR08 EQU 0000B8H
; Interrupt control register for the 16-bit PPG timer
PCSR0 EQU 000072H
; PPG period setting register
PDUT0 EQU 000074H
; PPG duty setting register
PCNT0 EQU 000070H
; PPG control status register
IRQF EQU PCNT0:4
; Interrupt request flag bit
;-------Main program----------------------------------------------------------CODE
CSEG
START:
;
:
; Assumes that stack pointer (SP) has already been initialized
AND
CCR,#0BFH
; Interrupt disable
MOV
I:ICR08,#00H
; Interrupt level 0 (strongest)
MOVW
I:PCSR0,#0063H
; Sets the period of the PPG output
MOVW
I:PDUT0,#003BH
; Sets the duty ratio of the PPG output
MOVW
I:PCNT0,#01100000000100110B
; Enables PPG output in normal polarity
; Enables 16-bit PPG timer, and 62.5 ns clock
; Software triggers PPG
; Select PWM mode and enable interrupt
; Clears interrupt flag, and starts counter
LOOP:
332
MOV
ILM,#07H
; Sets ILM in PS to level 7
OR
CCR,#40H
; Interrupt enable
MOV
A,#00H
; Endless loop
MOV
A,#01H
;
BRA
LOOP ;
CHAPTER 15 PPG TIMER
;-------Interrupt program------------------------------------------------------WARI:
CLRB
;
:
;
User processing
;
:
I:IRQF
RETI
; Clears interrupt request flag
; Returns from interrupt
CODE ENDS
;-------Vector setting---------------------------------------------------------VECT
CSEG
ABS=0FFH
ORG
0FF90H
DSL
WARI
ORG
0FFDCH
DSL
START
DB
00H
END
START
; Sets vector for interrupt #27 (1BH)
; Sets reset vector
; Sets single-chip mode
VECT ENDS
333
CHAPTER 15 PPG TIMER
334
CHAPTER 16
UART
This chapter describes the functions and the operations
of MB90800 series UART.
16.1 Overview of UART
16.2 Configuration of UART
16.3 UART Pins
16.4 Register of UART
16.5 UART Interrupt
16.6 UART Baud Rate
16.7 Explanation of Operation of UART
16.8 Notes on Using UART
335
CHAPTER 16 UART
16.1
Overview of UART
UART is a general purpose serial data communication interface for synchronous or
asynchronous (start-stop synchronization) communications with external devices. It
supports bi-directional communication (normal mode) and master/slave communication
(multi-processor mode: supported on master side only).
■ UART Function
● UART function
UART is the general purpose serial data communication interface which transmits and receives the serial
data with other CPUs or external devices. See Table 16.1-1 .
Table 16.1-1 UART Function
Functions
Contents
Data buffer
Full-duplicate double-buffer
Transfer mode
• Synchronous to clock (without start/stop bit)
• Asynchronous to clock (start-stop synchronization)
Baud rate
• Baud rate by dedicated baud rate generator
• Baud rate by external clock (clock of SC terminal input)
• Baud rate set by internal clock (clock supplied from the 16-bit reload timer)
• The baud rate can be set according to all eight kinds.
Data length
• 7-bit (Only at an asynchronous normal mode).
• 8-bit
Signal type
NRZ (Non Return to Zero) method
Detection of receive error
• Framing error
• Overrun error
• Parity error (Not detected in multi-processor mode)
Interrupt request
• Receive interrupt (receive, detection of receive error)
• Transfer interrupt (transfer completion)
• Transmission and reception support for extended intelligent I/O service (EI2OS).
Master/slave type
communication function
(multi processor mode)
This function enables communications between 1 (master) and n (slave).
(Only the master side is supported.)
Note:
The UART does not insert start bit nor stop bit in clock synchronized transfer mode. Only data is
forwarded.
336
CHAPTER 16 UART
Table 16.1-2 UART Operation Modes
Data length
Operating mode
No Parity
0
Normal mode
1
Multiprocessor mode
2
Normal mode
With Parity
7 bits or 8 bits
Synchronous
type
Length of
Stop Bit
Asynchronous
8 + 1 *1
-
Asynchronous
1 bit
or
2 bits *2
8
-
Synchronous
None
-: Unavailable
*1: + 1 is an address/data setting bit (A/D) which is used for communication control.
*2: Only one stop bit can be detected when receiving data.
■ Interruption and EI2OS which Relates to UART
Table 16.1-3 Interruption and EI2OS which Relates to UART
Interrupt
cause
UART0
reception
interrupt
Interrupt
number
Interrupt control registers
Vector table address
EI2OS
Register
name
Address
Low
#35(23H)
ICR12
High
Bank
Register
name
FFFF70H
FFFF71H
FFFF72H
0000BCH
UART0
transmission
interrupt
#36(24H)
FFFF6CH
FFFF6DH
FFFF6EH
UART1
reception
interrupt
#39(27H)
FFFF60H
FFFF61H
FFFF62H
FFFF5CH
FFFF5DH
FFFF5EH
ICR14
UART1
transmission
interrupt
#40(28H)
0000BEH
: With a function that stops EI2OS by detecting a UART receive error.
: Usable when not using interrupt factor in common with ICR12 and ICR14
337
CHAPTER 16 UART
16.2
Configuration of UART
UART is composed of the following 11 kinds of blocks.
• Clock selector
• Mode register (SMR0/SMR1)
• Reception control circuit
• Control register (SCR0/SCR1)
• Transmission control circuit • Status register (SSR0/SSR1)
• Reception state judge circuit • Input data register (SIDR0/SIDR1)
• Reception shift register
• Output data register (SODR0/SODR1)
• Transmission shift register
■ UART Block Diagram
Figure 16.2-1 UART Block Diagram
Control bus
Reception
interrupt signal
Dedicated baud
rate generator
16-bit reload
timer 1/2
Transfer clock
Clock
selector
Transfer
interrupt signal
Reception
clock
Pin
Transfer
control
circuit
Reception
control
circuit
Start bit
detection circuit
Transfer start
circuit
Reception bit
counter
Transfer bit
counter
Reception parity
counter
Transfer parity
counter
Shift register
for reception
Shift register
for transfer
Pin
SIDR0/SIDR1
Reception
end
SODR0/SODR1
Pin
Transfer start
Reception state
judge circuit
Reception error
generating signal
for EI2OS
(to CPU)
Internal data bus
SMR0/
SMR1
register
MD1
MD0
CS2
CS1
CS0
SCKE
SOE
338
SCR0/
SCR1
register
PEN
P
SBL
CL
A/D
REC
RXE
TXE
SSR0/
SSR1
register
PE
ORE
FRE
RDRF
TDRE
BDS
RIE
TIE
CHAPTER 16 UART
● Clock selector
Dedicated baud rate generator generates transmission/reception clock from the external input clock (clock
of SC0/SC1 terminal input), and the internal clock (clock supplied by 16-bit reload timer).
● Reception Control Circuit
The reception control circuit is configured with the reception bit counter, start bit detecting circuit, and
reception parity counter. The reception bit counter counts the number of received bits and outputs a
reception interrupt request when the received data reaches to a preset data length. The start bit detecting
circuit detects a start bit from serial input signals. When it detects a start bit, it stores received data by
shifting into the input data register (SIDR0/SIDR1) with the preset transfer speed. The reception parity
counter calculates the parity of the received data if the data is with parity.
● Transmission Control Circuit
The transmission control circuit is configured with the transmission bit counter, transmission start circuit,
and transmission parity counter. The transmission bit counter counts the number of transmitted bits and
outputs a transmission interrupt request when the transmitted data reaches to a preset data length. The
transmission start circuit starts transmission operation when the transmission data is stored in the output
data register (SODR0/SIDR1). The transmission parity counter generates the parity bit of the transmitting
data if the data is with parity.
● Receive shift register
Takes the input data in from SI0/SI1 terminals by shifting bit by bit, and when receiving operation is
completed, starts transferring the received data to the input data register (SIDR0/SIDR1).
● Transmit shift register
The transmitting data set in the output data register (SODR0/SODR1) are transferred to the transmission
shift register and output to SO0, SO1 terminals by shifting bit by bit.
● Mode register (SMR0/SMR1)
Sets the operation mode, sets the baud rate clock, controls the serial clock input-output, and sets the output
permission to the serial data terminal.
● Control register (SCR0/SCR1)
Sets parity/non-parity mode, sets parity, sets stop bit length and/or data length, sets the frame data format in
operation mode 1, clears the receiving error flag bit, and sets permission/prohibition for transmit/receive
operation.
● Status register (SSR0/SSR1)
Checks transmit/receive/error status, sets serial data transfer direction, and sets permission/prohibition for
transmit/receive interrupt request.
● Input data register (SIDR0/SIDR1)
It is a register which stores the received data.
339
CHAPTER 16 UART
● Output data register (SODR0/SODR1)
It is a register which sets the transmitted data. The data that has been set to the output data register is
converted into the serial data and is output.
340
CHAPTER 16 UART
16.3
UART Pins
Block diagram of pins of UART and pin block is shown.
■ UART Pins
UART terminals serve also as input/output ports.
Table 16.3-1 UART Pins
Pin
name
Pin function
I/O type
CMOS
output/
CMOS
hysteria
Input
Pull-up
selection
Stand-by
control
None
Yes
To the use of the terminal setting
P54/
SI0
Input/Output port/
Serial data input
P56/
SO0
Input/Output port/
Serial data output
P55/
SC0
Input/Output port/
Serial clock input/
output
Set to the input port
(DDR5: bit13= 0)
P57/
SI1
Input/Output port/
Serial data input
Set to the input port
(DDR5: bit15= 0)
P72/
AN10/
SO1
Input/Output port/
A/D analog input/
Serial data output
Set to serial data output enable
(SMR1: SOE= 1)
P71/
AN9/
SC1
Input/Output port/
A/D analog input/
Serial clock
input/output
Set to the input port
(DDR7: bit1= 0)
Set to the input port
(DDR5: bit12= 0)
Set to serial data output enable
(SMR0: SOE= 1)
Set to "serial clock output enabled"
(SMR0:SCKE = 1)
Analog input interdiction (ADER1: bit1= 0)
Set to "serial clock output enabled"
(SMR1: SCKE= 1)
■ Block Diagram of UART Pins
Figure 16.3-1 Block Diagram of UART Pins
Internal data bus
Resource input
PDR read
PDR
I/O
judge circuit
PDR write
DDR
Input buffer
Output buffer
Port pin
Standby control (LPMCR: SPL="1")
I/O control circuit
Resource output
341
CHAPTER 16 UART
16.4
Register of UART
The list of the register of UART is shown.
■ List of UART Register
Figure 16.4-1 List of UART Register
bit15
bit8
bit7
bit0
Control register (SCR)
Mode register (SMR)
Status register (SSR)
I/O data register (SIDR/SODR)
Communication prescaler control register (CDCR)
Note:
Register of UART, such as the INC/DEC instruction, which provide the read modify write (RMW)
instruction cannot be used.
342
CHAPTER 16 UART
16.4.1
Control Register (SCR0/SCR1)
The control register (SCR0/SCR1) sets parity/non-parity mode, sets parity, sets stop bit
length and/or data length, sets the frame data format in operation mode 1, clears the
receiving error flag bit, and sets permission/prohibition for transmit/receive operation.
■ Control Register (SCR0/SCR1)
Figure 16.4-2 PWM Control Register (SCR0/SCR1)
Address Bit 15
ch.0 000021H
PEN
ch.1 000029H
R/W
14
13
12
11
10
9
8
Initial value
P
SBL
CL
A/D
REC
RXE
TXE
00000100B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TXE
Transmission operation enable bit
0
Disables transfer operation
1
Enables transfer operation
RXE
Reception operation enable bit
0
Disables reception operation
1
Enables reception operation
REC
Reception error flag clear bit
0
Clears FRE,OR and PE flag to "0".
1
No effect to operation
A/D
Address/Data setting bit
0
Data frame
1
Address frame
CL
Data length setting bit
0
Sets 7 bits
1
Sets 8 bits
SBL
Stop bit length setting bit
0
Sets 1 bit length
1
Sets 2 bits length
Parity setting bit
P
Enable with parity (PEN=1)
0
Even parity
1
Odd parity
PEN
R/W
: Readable/Writable
: Initial value
Parity enable bit
0
No parity
1
Parity
343
CHAPTER 16 UART
Table 16.4-1 Functional Description of Each Bit in Control Register (SCR0/SCR1)
Bit name
344
Functions
bit15
PEN:
Parity enable
bit
It is a bit to set whether or not a parity pit be added to serial data (at send) and detected
(at receive).
Note:
If operation mode 1 or 2 is set, the parity bit cannot be used, so set "0".
bit14
P:
Parity setting
bit
It is a bit by which the odd parity/the even parity is set.
Note:
It is effective only for being the parity (PEN=1).
bit13
SBL:
Stop bit
length setting
bit
It is a bit to set the bit length of the stop bits used for a frame end mark attached to
transmitted data in asynchronous transfer mode.
Note:
At receive, the first bit of the stop bit is detected.
bit12
CL:
Data length
setting bit
It is a bit by which data length of transferred data is set.
Note:
7 bits can be specified only when operating mode is 0 (asynchronous mode). For
operating mode 1 (multiprocessor mode) and operating mode 2 (synchronous) mode, be
sure to set to 8 bits (CL = 1).
bit11
A/D:
Address/Data
setting bit
• It is a bit to set the send/receive data format in multiprocessor mode (operating mode 1).
• When "0" is set, it becomes normal data.
• When "1" is set, it becomes address data.
bit10
REC:
Reception
error flag
clear bit
• It is a bit to clear the receive error flag bits (FRE, ORE, PE) of the status register
(SSR0/SSR1).
• If "0" is set, the receive error flag bit (FRE, ORE, PE) is cleared to "0".
• If "1" is set, the operation is not affected.
Note:
If this bit is set to "0" when the receive interrupt during UART operation is enabled, set
either one of the receive error flag bits (FRE, ORE, PE) to "1".
bit9
RXE:
Reception
operation
enable bit
• It is a bit to control the receive operation of UART.
• If "0" is set, the receive operation is disabled.
• When "1" is set, the reception operation is permitted.
Note:
If receive operation is disabled while data is being received, the receive operation stops
after completing the current receive data operation and after storing the received data in
the input data register (SIDR0/SIDR1).
bit8
TXE:
Transmission
operation
enable bit
• It is a bit to control the send operation of UART.
• If "0" is set, the send operation is disabled.
• When "1" is set, the transmission operation is permitted.
Note:
If send operation is disabled while data is being sent, the send operation stops after the
output data register (SODR0/SODR1) becomes empty.
When setting "0", set it after waiting for longer than the time period of 1/16 of the baud
rate in clock asynchronous transfer mode, and after waiting for the same time period as
the baud rate in clock synchronous transfer mode, after data is written into the output
data register (SODR0/SODR1).
CHAPTER 16 UART
Note:
The command that operates the read modify write (RMW) instruction cannot be used.
345
CHAPTER 16 UART
16.4.2
Mode Register (SMR0/SMR1)
The mode register (SMR0/SMR1) sets the operation mode, sets the baud rate clock,
controls the serial clock input-output, and sets output permission to the serial data
terminal.
■ Mode Register (SMR0/SMR1)
Figure 16.4-3 Mode Register (SMR0/SMR1)
Address Bit
ch.0 000020H
ch.1 000028H
7
6
5
4
3
2
MD1
MD0
CS2
CS1
CS0
R/W
R/W
R/W
R/W
R/W
1
SCKE SOE
R/W
R/W
Regarded as I/O port
1
Regarded as serial data output pin
Serial clock output enable bit (P40/SC0 and P62/SC1 pin)
0
Regarded as I/O port or serial clock I/O pin
1
Regarded as serial clock output pin
Clock setting bits
CS2 to CS0
"000B" to "101B"
Baud rate by dedicated baud rate generator
"110B"
Baud rate by internal clock (16-bit reload timer)
"111B"
Baud rate by external clock (SC0/SC1 pin)
Operating mode setting bits
MD1 MD0
346
00000-00B
0
SCKE
: Readable/Writable
: Undefined
: Initial value
Initial value
Serial data output enable bit (P37/SO0 and P61/SO1 pin)
SOE
R/W
0
Operating mode
0
0
0
Asynchronous (normal mode)
0
1
1
Asynchronous (multi processor mode)
1
0
2
Synchronous (normal mode)
1
1
Setting prohibited
CHAPTER 16 UART
Table 16.4-2 Functional Description of Each Bit of the Mode Register (SMR0/SMR1)
Bit name
Functions
bit7,
bit6
MD1, MD0:
Operation
mode setting
bits
It is a bit by which the operation mode is set.
Note:
Operation mode 1 (multi processor mode) can be only used as a master of master/
slave type communication. Because UART does not feature the address/data
determination function, operation mode 1 cannot be used as the slave.
bit5
to
bit3
CS2 to CS0:
Clock setting
bits
• It is a bit to set the clock source of baud rate.
• If the dedicated baud rate generator is set, the baud rate must also be determined.
• Baud rate can be selected from a total of 8 types of baud rate including dedicated
baud rate generators (6 types), baud rate by an internal clock (1type) and baud rate by
an external clock (1 type).
• Clock input can be set from an external clock (SC0/SC1 pin input), the internal clock
(16-bit reload timer) and the dedicated baud rate generator.
Note:
When using the dedicated baud rate generator at synchronous transfer, do not make
the following setting.
• At CS2 to CS0 = 000B, DIV2 to DIV0 = 000B, 001B, 010B
• At CS2 to CS0 = 001B, DIV2 to DIV0 = 000B
bit2
-:
Undefined bit
• The value becomes undefined when read operation is performed.
• The set value does not influence the operation.
bit1
SCKE:
Serial clock
output enable
bit (P40/SC0,
P62/SC1 pin)
• It is a bit to control the input/output of the serial clock.
• If "0" is set, the SC pin functions as an I/O port or a serial clock input pin.
• If "1" is set, the SC pin functions as a serial clock output pin.
Note:
• If the SC pin is used as the serial clock input (SCKE = 0), set it as an input port. Set
an external clock by the clock setting bit (SMR0/SMR1:CS2 to CS0 = 111B).
• If the SC pin is used as serial clock output (SCKE = 1), set a dedicated baud rate
generator (SMR0/SMR1:CS2 to CS0 = 000B to 101B) or an internal clock (SMR0/
SMR1:CS2 to CS0 = 110B).
Reference:
When being serial clock output (SCKE= 1), this bit functions as serial clock output
pin in spite of the state of I/O port.
bit0
SOE:
Serial data
output enable
bit (P37/SO0,
P61/SO1 pin)
• It is a bit to enable the output of serial data
• When "0" is set, the SO terminal becomes a input-output port.
• If "1" is set, used as a serial data output pin.
Reference:
When being serial data output (SOE= 1), this bit functions as serial data output pin in
spite of the state of I/O port.
Note:
The command that operates the read modify write (RMW) instruction cannot be used.
347
CHAPTER 16 UART
16.4.3
Status Register (SSR0/SSR1)
The status register (SSR0/SSR1) checks transmit/receive/error status, sets the serial
data transfer direction, and sets permission/prohibition for the interrupt operation.
■ Status Register (SSR0/SSR1)
Figure 16.4-4 Status Register (SSR0/SSR1)
Address Bit
ch.0 000023H
ch.1 00002BH
15
14
PE
ORE
R/W
R/W
13
12
10
9
8
Initial value
FRE RDRF TDRE
BDS
RIE
TIE
00001000B
R/W
R/W
R/W
R/W
R/W
11
R/W
TIE
0
Transmission interrupt request enable bit
Disables transfer interrupt request output
1
Enables transfer interrupt request output
RIE
0
Reception interrupt request enable bit
Disables receive interrupt request output
1
Enables receive interrupt request output
BDS
0
Transmission direction setting bit
LSB first (transfer from lowest bit)
1
MSB first (transfer from uppermost bit)
TDRE
0
Transmission data empty flag bit
Transfer data (disable writing of transfer data)
1
No transfer data (enable writing of transfer data)
RDRF
0
Receive data full flag bit
Receives data
1
No reception data
Framing error flag bit
FRE
No framing error
0
1
Framing error
ORE
Overrun error flag bit
0
No overrun
1
Overrun
Parity error flag bit
PE
R/W
348
: Readable/Writable
: Initial value
0
No parity error
1
Parity error
CHAPTER 16 UART
Table 16.4-3 Functional Explanation of Each Bit in Status Register (SSR0/SSR1) (1/2)
Bit name
Functions
bit15
PE:
Parity error
flag bit
• "1" is set when a parity error is detected during receive operation.
• If the receive error flag clear bit (REC) of the control register (SCR0/SCR1) is set to
"0", cleared to "0".
• When "1" is set, a receive interrupt request is output if the receive interrupt request
enable bit (RIE) is set to "1".
• When "1" is set, the data of input data register (SIDR0/SIDR1) becomes invalid.
bit14
ORE:
Overrun error
flag bit
• "1" is set when an overrun error is detected during receive operation.
• If the receive error flag clear bit (REC) of the control register (SCR0/SCR1) is set to
"0", cleared to "0".
• When "1" is set, a receive interrupt request is output if the receive interrupt request
enable bit (RIE) is set to "1".
• When "1" is set, the data of input data register (SIDR0/SIDR1) becomes invalid.
bit13
FRE:
Flaming error
flag bit
• "1" is set when a framing error is detected during receive operation.
• If the receive error flag clear bit (REC) of the control register (SCR0/SCR1) is set to
"0", cleared to "0".
• When "1" is set, a receive interrupt request is output if the receive interrupt request
enable bit (RIE) is set to "1".
• When "1" is set, the data of input data register (SIDR0/SIDR1) becomes invalid.
bit12
RDRF:
Reception
data full flag
bit
• This bit shows status of input data register (SIDR0/SIDR1).
• The data is set to "1" when reception data is stored in the input data register.
• The data is cleared to "0" when reception data is loaded from the input data register.
• When "1" is set, a receive interrupt request is output if the receive interrupt request
enable bit (RIE) is set to "1".
bit11
TDRE:
Transmission
data empty
flag bit
• This bit shows status of output data register (SODR0/SODR1).
• When the transmitting data is written into the output data register (SODR0/SODR1),
the transmission data empty flag bit (TDRE) is cleared to "0".
• "1" is set when data is read into the sending shift register and transmission starts.
• When "1" is set, a send interrupt request is output if the send interrupt request enable
bit (TIE) is set to "1".
Note:
This bit is set "1" in initial state.
bit10
BDS:
Transmission
direction
setting bit
• This bit sets the direction of serial data transfer.
• If "0" is set, data is transferred, starting from the least significant bit (LSB first).
• If "1" is set, data is transferred, starting from the most significant bit (MSB first).
Note:
As the high-order side and low-order side of data is exchanged at read/write operation
for the serial data register, if the transfer direction setting bit (BDS) is changed after
writing data to the output data register (SODR0/SODR1), the written data becomes
invalid.
bit9
RIE:
Reception
interrupt
request enable
bit
• It is a bit to enable receive interrupt requests
• If this bit is set to "1", a receive interrupt request is output when the receive data full
flag bit (RDRF) is "1" or either one of the receive error flag bits (PE, ORE, FRE) is
set to "1".
349
CHAPTER 16 UART
Table 16.4-3 Functional Explanation of Each Bit in Status Register (SSR0/SSR1) (2/2)
Bit name
bit8
TIE:
Transmission
interrupt
request enable
bit
Functions
• It is a bit to enable transmission interrupt requests
• If this bit is set to "1", a transmission interrupt request is output when the data empty
flag bit (TDRE) is set to "1".
Note:
The command that operates the read modify write (RMW) instruction cannot be used.
350
CHAPTER 16 UART
16.4.4
Input Data Register (SIDR0/SIDR1),
Output Data Register (SODR0/SODR1)
The input data register (SIDR0/SIDR1) is the receive only serial data register, and the
output data register (SODR0/SODR1) is the output only serial data register.
■ Input Data Register (SIDR0/SIDR1)
Figure 16.4-5 Input Data Register (SIDR0/SIDR1)
Address Bit
ch.0 000022H
ch.1 00002AH
7
6
5
4
3
2
1
0
Initial value
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W
R/W : Readable/Writable
It is a register which stores the received data. Converts the serial data signals received in SI0/SI1 terminals
in the sift register, and then stores the converted data into the input data register (SIDR0/SIDR1). If the data
length is set to 7-bit in the operation mode 0, then bit7 (D7) will be assumed as an invalid data. When
received data is stored in input data register (SIDR0/SIDR1), received data full flag bit (RDRF) of status
register (SSR0/SSR1) is set to "1". When reception interrupt request output is set enable (SSR0/
SSR1:RIE=1), reception interrupt is output.
The input data register (SIDR0/SIDR1) should be read only when "1" is set to the receiving data full flag
bit (RDRF) of the status register (SSR0/SSR1). The received data full flag bit (RDRF) is cleared to "0"
when the input data register (SIDR0/SIDR1) is read out. If the receiving error occurs (any of SSR0/
SSR1:PE, ORE, FRE is "1"), then the data in the input data register (SIDR0/SIDR1) becomes invalid.
■ Output Data Register (SODR0/SODR1)
Figure 16.4-6 Output Data Register (SODR0/SODR1)
Address Bit
ch.0 000022H
ch.1 00002AH
7
6
5
4
3
2
1
0
Initial value
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W
R/W : Readable/Writable
If the status of the transmission operation is permitted, and when the transmitting data is wrote into the
output data register (SODR0/SODR1), then the transmitting data will be transferred to the transmission sift
register and converted into serial data, and sent out from serial data out terminals (SO0/SO1).If the data
length is set to 7-bit in the operation mode 0, then bit7 (D7) will be assumed as an invalid data.
When the transmitting data is wrote into the output data register, the transmission data empty flag bit
(TDRE) of the status register (SSR0/SSR1) is cleared to "0", and "1" will be set after completion of the
transfer operation to the transmission shift register. If "1" is set to the transmission data empty flag bit
(TDRE), the transmitting data can be written. If the transmission data empty flag bit (TDRE) is set to "1",
and if the transmission interrupt request output is permitted (SSR0/SSR1:TIE= 1), then it outputs the
transmission interrupt. Wait for the transmission interrupt output or until "1" is set to the transmission data
empty flag bit (TDRE) before start writing the next transmitting data.
351
CHAPTER 16 UART
Note:
Output data register (SODR0/SODR1) is a read only register and input data register (SIDR0/SIDR1)
is a write only register. As they are assigned to the same address, writing value and reading value
are different. The instruction executing the read modify write (RMW) instruction such as INC/DEC
instruction, etc. can not be used.
352
CHAPTER 16 UART
16.4.5
Communication Prescaler Control Register (CDCR0/
CDCR1)
The communication pre-scalar control register (CDCR0/CDCR1) controls the machine
clock frequency division.
■ Communication Prescaler Control Register (CDCR0/CDCR1)
The operation clock of UART is generated by dividing the machine clock. It is designed to obtain the
constant baud rate from various machine cycles through the communication pre-scalar control register. The
output of the communication pre-scalar register is also used as the operation clock of the extended I/O
serial interface.
Address Bit
ch.0 000025H
ch.1 00002DH
15
14
MD URST
R/W R/W
13
12
11
Reserved
10
9
8
DIV2 D1V1 D1V0
Initial value
0X--0000B
R/W R/W R/W R/W
R/W : Readable/Writable
: Undefined
Table 16.4-4 Functional Description of Each Bit of the Communication Prescaler Control Register
(CDCR0/CDCR1)
Bit name
Functions
bit15
MD:
Communication prescaler
operation enable bit
• It is a bit to enable the operation of the communication prescaler.
• The communication prescaler operates when "1" is set.
• The communication prescaler stops when "0" is set.
bit14
URST:
UART reset bit
• It is a bit which generates reset for UART.
• When "1" is set, UART is reset.
• When "0" is set, reset of UART is released.
bit13,
bit12
-:
Undefined bits
• The value becomes undefined when read operation is performed.
• The set value does not influence the operation.
bit11
Reserved:
Reserved bit
Be sure to set this bit to "0".
bit10
to
bit8
DIV2 to DIV0:
Division ratio bits
• It is a bit to set the division ratio of the machine lock.
• For setting values, see Table 16.4-5 .
353
CHAPTER 16 UART
Table 16.4-5 Machine Clock Division Ratio
MD
DIV2
DIV1
DIV0
div
0
-
-
-
Stops
1
0
0
0
1
1
0
0
1
2
1
0
1
0
3
1
0
1
1
4
1
1
0
0
5
1
1
0
1
6
1
1
1
0
7
1
1
1
1
8
div: Machine clock division ratio
Notes:
• If frequency division ratio was changed, wait for 2 cycles as the stabilizing time of the clock before
start communication.
The command that operates the read modify write (RMW) instruction cannot be used.
• When using the dedicated baud rate generator at synchronous transfer, do not make the following
setting.
• At CS2 to CS0 = 000B, DIV2 to DIV0 = 000B, 001B, 010B
• At CS2 to CS0 = 001B, DIV2 to DIV0 = 000B
354
CHAPTER 16 UART
16.5
UART Interrupt
UART has the receive interrupt and transmission interrupt, and outputs the interrupt
request using the factors below.
• Outputs the receive interrupt when the receiving data is set to the input data register
(SIDR0/SIDR1), or the receiving error has occurred.
• Outputs the transmission interrupt when the transmitting data is transferred from the
output data register (SODR0/SODR1) to the transmission shift register.
Receive interrupt and transfer interrupt also support for extended intelligent I/O service
(EI2OS).
■ UART Interrupt
Table 16.5-1 Interrupt Control Bit of UART and Interruption Factor
Transmission/
Reception
Reception
Transmission
Interrupt cause
Interrupt
cause
enable
bits
RDRF
Received data is set to input data
register (SIDR0/SIDR1).
SSR0/
SSR1: RIE
ORE
Generating overrun error
FRE
Generating framing error
PE
Generating parity error
TDRE
Output data register
(SODR0/SODR1)
Interrupt
request
flag bit
Operating mode
0
1
2
Interrupt request flag
clear
Reading receive data
Receiving error flag
clear bit
Set (SCR0/SCR1:REC)
to "0".
SSR0/
SSR1: TIE
Writing transmit data
: using bit
: Unused bit
● Receive Interrupt
When either data reception completion, overrun error, framing error or parity error occurs at reception
mode, the reception data full flag bit (RDRF) in status register (SSR0/SSR1) or reception error flag bit
(ORE, FRE, PE) are set to "1" according to the error occurred. When receive interrupt request have been
enabled (SSR0/SSR1: RIE=1), a receive interrupt request is output.
The receiving data full flag bit (RDRF) of the status register (SSR0/SSR1) is cleared to "0" when starts to
read the input data register (SIDR0/SIDR1). The receiving error flag bit (PE, ORE, FRE) of the status
register (SSR0/SSR1) is cleared to "0" if the receiving error flag clear bit (REC) of the control register
(SCR0/SCR1) is set to "0".
355
CHAPTER 16 UART
● Send Interrupt
If the transmitting data is transferred from the output data register (SODR0/SODR1) to the transfer shift
register, then "1" is set to the transmission data empty flag bit (TDRE) of the status register (SSR0/SSR1).
If the send interrupt is permitted (SSR0/SSR1:TIE= 1), then it outputs the transmission interrupt request.
■ Interrupt Related to UART1 and EI2OS
Table 16.5-2 Interrupt Related to UART1 and EI2OS
Interrupt control registers
Interrupt
number
Interrupt cause
UART0 receive
interrupt
Register
name
EI2OS
Address
#35(23H)
ICR12
Vector table address
Low
High
Bank
FFFF70H
FFFF71H
FFFF72H
0000BCH
UART0 send
interrupt
#36(24H)
FFFF6CH
FFFF6DH
FFFF6EH
UART1 receive
interrupt
#39(27H)
FFFF60H
FFFF61H
FFFF62H
FFFF5CH
FFFF5DH
FFFF5EH
ICR14
UART1 send
interrupt
#40(28H)
0000BEH
: With a function that stops EI2OS by detecting a UART receive error.
: Usable when not using interrupt factor in common with ICR12 or ICR14
■ UART EI2OS Function
Because UART has EI2OS-compliant circuit, the reception/send interrupt can individually activate EI2OS.
● At receiving:
EI2OS can be used regardless of other resource status.
● At sending:
Because the interrupt control register (ICR14) shares UART receive interrupt, EI2OS can be activated by
ICR14 when UART receive interrupt is not output.
356
CHAPTER 16 UART
16.5.1
Receive Interrupt Generation and Flag Set Timing
The factors of receiving interrupt are the completion for reception (SSR0/SSR1:RDRF=
1) and the occurrence of receiving error (SSR0/SSR1:one of PE,ORE,FRE= 1)
■ Receive Interrupt Generation and Flag Set Timing
When data is received, it is stored in the input data register (SIDR0/SIDR1) and receive data full flag bit
(RDRF) of status register (SSR0/SSR1) is set to "1" when the stop bit is detected (in operating mode 0 and
1) or when the last bit of receive data(D7) is detected (in operation mode 2). If a receiving error has
occurred, "1" is set to one of the receiving error flag bit (PE, ORE, FRE). In any operation mode, if "1" is
set to one of receiving error flag bit, the value in the input data register (SIDR0/SIDR1) becomes invalid.
● Operation mode 0 (Asynchronous normal mode)
When it detects a stop bit, if "1" is set to the receiving data full flag bit (RDRF) of the status register
(SSR0/SSR1), and if there is any receiving error exists, then "1" is set to either of the receiving error flag
bit (PE, ORE, FRE).
● Operating mode 1 (asynchronous multiprocessor mode)
When it detects a stop bit, if "1" is set to the receiving data full flag bit (RDRF) of the status register
(SSR0/SSR1), and if there is any receiving error exists, then "1" is set to either of the receiving error flag
bit (ORE, FRE). Parity error can not be detected.
● Operation mode 2 (synchronization and normal mode)
When detecting the last bit (D7) of receiving data, if "1" is set to the receiving data full flag bit (RDRF) of
the status register (SSR0/SSR1), and if any error exists, then "1" is set to the receiving error flag bit (ORE).
Parity error and the flaming error cannot be detected.
357
CHAPTER 16 UART
Figure 16.5-1 Reception and Timing of Flag Set
Receive data
(operation mode 0)
ST
D0
D1
D5
D6
D7/P
SP
Receive data
(operation mode 1)
ST
D0
D1
D6
D7
A/D
SP
D0
D1
D4
D5
D6
D7
Receive data
(operation mode 2)
PE, ORE, FRE*
RDRF
Reception interrupt generation
*
: PE flag can not be used in mode 1.
PE and FRE flag can not be used in mode 2.
ST : Start bit
SP : Stop bit
A/D : Address/data setting bit of mode 2 (multi processor mode)
● Timing of receive interruption generation
With a receive interrupt enabled(SSR0/SSR1:RIE=1), when any one of the status register (SSR0/SSR1),
reception data full flag bit (RDRF) or reception error flag bit (PE, ORE, FRE) is set to "1", receive interrupt
request is issued.
358
CHAPTER 16 UART
16.5.2
Timing for the Transmission Interrupt Output and Flag Set
The transmit interrupt is generated when the output data register (SODR0/SODR1) is in
a state where the next transmitted data can be written.
■ Transmit Interrupt Generation and Flag Set Timing
If the data written into the output data register (SODR0/SODR1) has been transferred to the transmission
shift register and the next data write operation is available, then "1" is set to the data empty flag bit (TDRE)
of the status register (SSR0/SSR1). When the transmitting data is written into the output data register
(SODR0/SODR1), the transmission data empty flag bit (TDRE) is cleared to "0".
Figure 16.5-2 Transmission and Timing of Flag Set
[Operation mode 0 and 1]
Transfer interrupt generation
Transfer interrupt generation
SODR write
TDRE
SO0/SO1 output
ST
D0 D1 D2
D3 D4
Transfer interrupt generation
D5 D6
SP
D7 A/D SP
ST D0 D1
D2 D3
Transfer interrupt generation
[Operation mode 2]
SODR write
TDRE
SO0/SO1 output
ST
D0 to D7
SP
A/D
D0
D1 D2 D3
D4 D5
D6 D7
D0
D1 D2
D3 D4 D5
D6 D7
: Start bit
: Data bit
: Stop bit
: Address/data setting bit
● Timing of transmission interrupt request
When the send interrupt is permitted (SSR0/SSR1:TIE= 1) and if "1" is set to the transmission data empty
flab bit (TDRE) of the status register (SSR0/SSR1), then it outputs the transmission interrupt request.
Note:
If the transmission interrupt is permitted (SSR0/SSR1:TIE= 1), the transmission data empty flag bit
(TDRE) of the status register (SSR0/SSR1) is initially set to "1", it outputs the transmission
interruption. Transmission data empty flag bit (TDRE) is read-only, the only way to clear to "0" is
writing the new data into the output data register (SODR0/SODR1). Be careful the timing of
transmitted interrupt enable.
359
CHAPTER 16 UART
16.6
UART Baud Rate
The transmitting/receiving clock of UART can set either of the items below.
• Dedicated baud rate generator
• Internal clock (16 bit reload timer)
• External clock (clock input to SC pin)
■ UART Baud Rate Setting
The selection circuit of the baud rate is shown in Figure 16.6-1 , and can be chosen from one of the three
categories below.
● Setting of baud rate by dedicated baud rate generator
UART stores the dedicated baud rate generator, and can set one of the 6 baud rates using the mode register
(SMR0/SMR1). The machine clock and clock setting bit (CS2 to CS0) of the mode register (SMR0/SMR1)
set asynchronous or synchronous baud rate.
● Setting of baud rate with internal clock
The internal clock supplied by 16-bit reload timer is used as the baud rate directly if it is in the synchronous
mode, or frequency-divided by 16 if it is in the asynchronous mode. The baud rate can be set by setting the
reload timer value.
● Setting of baud rate by external clock
The clock input by UART clock input terminals (SCK) can be used to set the baud rate to the input
frequency if it is in the synchronous mode, or to the clock frequency divided by 16 if it is in the
asynchronous mode.
360
CHAPTER 16 UART
Figure 16.6-1 UART Baud Rate Selector Circuit
SMR0/SMR1: CS2 to CS0
(Clock setting bit)
[Dedicated baud rate generator]
Clock selector
4
0: φ/4
1: φ/5
φ
Prescaler
[Internal timer]
TMCR: CSL1, CSL0
2
Clock selector
φ
In the case of
"000B" to "100B"
Divided circuit
(Synchronous)
Set any division
of 1/2,1/4,1/8
(Asynchronous)
Set internal fixed
division ratio
In the case
of "110B"
UF
Down
counter
1/1 (Synchronous)
1/16 (Asynchronous)
Baud rate
φ/21 φ/23 φ/25
Prescaler
16-bit reload timer
[External clock]
In the case
of "111B"
Pin
1/1 (Synchronous)
1/16 (Asynchronous)
SMR0/SMR1: MD1
(Setting of clock synchronous/asynchronous)
φ: Machine clock frequency
361
CHAPTER 16 UART
16.6.1
Baud Rate by Dedicated Baud Rate Generator
When the output clock of the dedicated baud rate generator was set, the baud rate
which can be set as a transfer clock of UART is shown.
■ Baud Rate by Dedicated Baud Rate Generator
If "000B to 101B" was set to the clock setting bit of the mode register (SMR0/SMR1), the baud rate is
generated by the dedicated baud rate generator.
When the transfer clock is generated by the dedicated baud rate generator, the machine clock first divided
by the machine clock pre-scalar, and then divided by transfer clock frequency divide ratio set in the clock
selector. Although the machine clock frequency divide ratio is common in synchronous/asynchronous
mode, the transfer clock frequency divide ratio differs in synchronous/asynchronous mode, and the
machine clock frequency is set to the value indicated by the clock setting bit (CS2 to CS0) of the mode.
An actual forwarding rate is given by the next expression.
Asynchronous baud rate = φ /(machine clock frequency divide ratio)/(asynchronous transfer clock
frequency divide ratio)
Synchronous baud rate = φ /(machine clock frequency divide ratio)/synchronous transfer clock frequency
divide ratio)
φ : Machine clock frequency
● The frequency divide ratio using pre-scalar (common in synchronous/asynchronous mode)
The machine clock frequency divide ratio is set using the frequency divide ratio setting bit (DIV2 to DIV0)
of the communication pre-scalar control register (CDCR0/CDCR1) shown in Table 16.6-1 .
Table 16.6-1 Division Ratio Setting by the Machine Clock Prescaler
MD
DIV2
DIV1
DIV0
div
0
-
-
-
Stops
1
0
0
0
1
1
0
0
1
2
1
0
1
0
3
1
0
1
1
4
1
1
0
0
5
1
1
0
1
6
1
1
1
0
7
1
1
1
1
8
div: Machine clock division ratio
362
CHAPTER 16 UART
● Ratio of synchronous transmission clock dividing frequency
The synchronous baud rate is set using the clock setting bit (CS2 to CS0) of the mode register (SMR0/
SMR1) shown as Table 16.6-2 .
Table 16.6-2 Setting of Ratio of Synchronous Baud Rate Dividing Frequency
CS2
CS1
CS0
CLK synchronous
Calculation
SC0/SC1
0
0
0
3.125Mbps
(φ / div)/1
(φ / div)/1
0
0
1
1.6Mbps
(φ / div)/2
(φ / div)/2
0
1
0
781.25kbps
(φ / div)/4
(φ / div)/4
0
1
1
390.63kbps
(φ / div)/8
(φ / div)/8
1
0
0
195.34kbps
(φ / div)/16
(φ / div)/16
1
0
1
97.66kbps
(φ / div)/32
(φ / div)/32
Where, φ is machine cycle, calculated at φ = 25MHz, div = 8, div is machine clock frequency divide
ratio. Moreover, CS2 to CS0=000B cannot be set at less than div=8. Please set to become φ /8 or less a
synchronous baud rate.
Notes:
When using the dedicated baud rate generator at synchronous transfer, do not make the following
setting.
• At CS2 to CS0 = 000B, DIV2 to DIV0 = 000B, 001B, 010B
• At CS2 to CS0 = 001B, DIV2 to DIV0 = 000B
● Ratio of asynchronous transmission clock dividing frequency
The asynchronous baud rate is set using the clock setting bit (CS2 to CS0) of the mode register (SMR0/
SMR1) shown as Table 16.6-3 .
Table 16.6-3 Setting of Ratio of Asynchronous Baud Rate Dividing Frequency
Clock Asynchronous
(start-stop synchronization)
CS2
CS1
CS0
0
0
0
120,192bps
(φ / div)/(8 13 2)
(φ / div)/(13 1)
0
0
1
60,096bps
(φ / div)/(8 13 4)
(φ / div)/(13 2)
0
1
0
30,048bps
(φ / div)/(8 13 8)
(φ / div)/(13 4)
0
1
1
15,024bps
(φ / div)/(8 13 16)
(φ / div)/(13 8)
1
0
0
781.25kbps
(φ / div)/(8 2 2)
(φ / div)/2
1
0
1
390.625kbps
(φ / div)/(8 2 4)
(φ / div)/4
Calculation
SC0/SC1
Where, φ is machine cycle, div is machine clock frequency divide ratio, calculated at φ = 25MHz, div = 1.
363
CHAPTER 16 UART
16.6.2
Baud Rate by Internal Timer
Describes the settings and the calculation formula of the baud rate, when the internal
clock supplied by 16-bit reload timer is set as UART transfer clock.
■ Baud Rate by Internal Timer (16-bit Reload Timer)
If the clock setting bit (CS2 to CS0) of the mode register (SMR0/SMR1) is set to "110B", the baud rate will
be set by the internal clock. The baud rate is set using the settings of the pre-scalar frequency divide ratio of
16-bit reload timer and reload value.
Figure 16.6-2 Baud Rate Selection Circuit by Internal Timer (16-bit reload timer)
SMR0/SMR1: CS2 to CS0=110B
(Setting of internal timer)
Clock selector
16-bit reload timer output
(Setting frequency by
division value of prescaler
and reload value)
1/1 (Synchronous)
1/16 (Asynchronous)
Baud rate
SMR0/SMR1: MD1
(Setting of clock synchronous/asynchronous)
● Calculation expression for baud rate
Asynchronous baud rate =(φ / N)/(16 2 (n+1)) bps
Synchronous baud rate =(φ / N)/(2 (n+1)) bps
φ : Machine clock cycle
N: division ratio based on communication prescaler for 16-bit reload timer (21, 23, 25)
n: reload value for 16-bit reload timer (0 to 65,535)
Note:
UART0 is set the baud rate for 16-bit reload timer 1, and UART1 is set the baud rate for 16-bit reload
timer 2.
364
CHAPTER 16 UART
● Example of reload value setting (machine clock:7.3728 MHz)
Table 16.6-4 Baud Rate and Reload Value
Reload Value (n)
Baud rate
Clock Asynchronous
(start-stop synchronization)
Clock synchronous
N=21
(2-frequency division
of machine cycle)
N=23
(8-frequency division
of machine cycle)
N=21
(2-frequency division
of machine cycle)
N=23
(8-frequency division
of machine cycle)
38400
2
-
47
11
19200
5
-
95
23
9600
11
2
191
47
4800
23
5
383
95
2400
47
11
767
191
1200
95
23
1535
383
600
191
47
3071
767
300
383
95
6143
1535
N: division ratio based on communication prescaler for 16-bit reload timer
-: Setting prohibited
Note:
At clock synchronization, the following settings are the prohibitions.
N = 1, n = 0
365
CHAPTER 16 UART
16.6.3
Baud Rate by External Clock
Describes the settings and the calculation formula of the baud rate, when the external
clock is set as UART transfer clock.
■ Baud Rate by External Clock
For setting baud rate of external clock, following condition should be set.
• Set "111B" to the clock setting bit (CS2 to CS0) of the mode register (SMR0/SMR1), and then set the
baud rate using the external clock input.
• Set SC pin as input port.
• Set "0" to the serial clock output permission bit (SCKE) of the mode register (SMR0/SMR1) to make
the terminal as the serial clock input terminal.
As shown in Figure 16.6-3 , set the baud rate based on the external clock input from SC pin. Because the
frequency divide ratio is fixed, the frequency of the external input clock should be changed to the baud rate.
Figure 16.6-3 Baud Rate Selection Circuit by External Clock
SMR0/SMR1: CS2 to CS0=111B
(Setting of external clock)
Clock selector
SC
1/1 (Synchronous)
1/16 (Asynchronous)
Pin
Baud rate
SMR0/SMR1: MD1
(Setting of clock synchronous/asynchronous)
● Calculation expression for baud rate
Asynchronous baud rate = φ/16 bps
Synchronous baud rate = φ' bps
Note: Max φ = 1/2 machine clock
Max φ’ = 1/8 machine clock
366
CHAPTER 16 UART
16.7
Explanation of Operation of UART
UART has the bi-directional serial communication function (operation mode 0, 2) and
the master/slave type communication function (operation mode 1).
■ Operation of UART
● Operating mode
There are 3 type of operation mode (0 to 2) in UART, and they can be set using connection method
between CPUs or data transfer method as shown in Table 16.7-1 .
Table 16.7-1 UART Operation Modes
Data length
Operating mode
No parity
0
Normal mode
1
Multiprocessor mode
2
Normal mode
With parity
7 bits or 8 bits
Synchronous
type
Asynchronous
8 + 1 *1
-
Asynchronous
8
-
Synchronous
Length of
stop bit
1 bit
or
2 bit *2
None
-: Unavailable
*1: + 1 is an address/data setting bit (A/D) which is used for communication control.
*2: Stop bit at reception can detect only one bit.
Note:
The operation mode 1 of UART is used when the master type is chosen in the master/slave type
connection.
● Inter-CPU connection method
Can select either one to one connection (normal mode) or master/slave type connection (multi-processor
mode). Data length, parity/non-parity settings, synchronous/asynchronous methods should be unified
through all the CPUs in both the normal mode and multi-processor mode. The operation mode is set as
follows.
• Both CPUs must select the same method of ether operation mode 0 or 2 in one to one connection. Set
the operation mode to 0 in the asynchronous method, 2 in the synchronous method.
• Use the operation mode 1 in the master/slave type connection. Set the operation mode 1, and use as the
master. Set non-parity in the master/slave type connection.
367
CHAPTER 16 UART
● Synchronous type
The asynchronous method (start-stop synchronization) or the clock synchronous method can be selected by
operation mode.
● Signal type
UART can treat the data of the NRZ (Non Return to Zero) form.
● Enabling Operations
UART has the transmitting operation enable bit (TXE) and the receiving operation enable bit (RXE) in the
control register (SCR0/SCR1) which can control the transmitting and receiving operations. If the operation
is disabled during the operation, the following action will occur.
• If the receiving operation (the data is being input into the reception shift register) is disabled during
receiving action, then it completes receiving data currently working, stores the data in the input data
register (SIDR0/SIDR1), and then, stops the receiving operation.
• If the transmission operation (the data is being output from the transmission shift register) is disabled
during transmitting action, then it stops the transmission operation after the output data register
(SODR0/SODR1) is empty.
• In the operation mode 1 in UART, the 9th bit of the receiving data is ignored.
368
CHAPTER 16 UART
16.7.1
Operation in Asynchronous Mode (Operation Mode 0 or 1)
If UART is used in the operation mode 0 (normal mode) or operation mode 1 (multiprocessor mode), the transfer method will be asynchronous.
■ Operation in Asynchronous Mode
● Transfer/receive data format
The transferring/receiving always starts from the start bit ("L" level). The specified data bit length is
transferring/receiving. And then, The transferring/receiving always ends with the stop bit ("H" level).
• In the operation mode 0, the data length is fixed to 7-bit or 8-bit. The data can be select with/without
parity bit.
• In the operation mode 1, the data length is fixed to 8-bit without parity. The data is added the 9th bit as
the address/data setting bit (SMR0/SMR1:A/D) is added.
Table 16.7-2 shows the transfer/receive data format (operation mode 0 and 1).
Figure 16.7-1 Transfer/Receive Data Format (Operation mode 0 and 1)
[Operating mode 0]
ST
D0
D1
D2
D3
D4
D5
D6
D7
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
No
Parity
Data 8bit
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
ST
D0
D1
D2
D3
D4
D5
D6
SP
SP
ST
D0
D1
D2
D3
D4
D5
D6
SP
SP
SP
With
Parity
SP
No
Parity
Data 7bit
ST
D0
D1
D2
D3
D4
D5
D6
P
SP
ST
D0
D1
D2
D3
D4
D5
D6
P
SP
SP
With
Parity
[Operating mode 1]
ST
D0
D1
D2
D3
D4
D5
D6
D7
A/D
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
A/D
SP
SP
Data 8bit
ST
SP
P
A/D
: Start bit
: Stop bit
: parity bit
: address/data bit
369
CHAPTER 16 UART
● Send Operation
If "1" is set to the transmission data empty flag bit (TDRE) of the status register (SSR0/SSR1), the
transmitting data can be written into the output data register (SODR0/SODR1). If the transmission
operation is enabled (SCR0/SCR1:TXT= 1), the transmission operation will be performed.
After the transmitting data has been transferred to the transmission sift register, and start transmission, "1"
is set to the transmission data empty flag bit (TDRE) of the status register (SSR0/SSR1), and next
transmitting data can be set. If the transmission interrupt request output is enabled (SSR0/SSR1:TIE= 1),
then it outputs the transmission interrupt request to request to set the transmitting data in the output data
register (SODR0/SODR1). The transmission data empty flag bit (TDRE) is cleared to "0" when the
transmitting data is written to the output data register (SODR0/SODR1).
● Receive Operation
If the receiving operation is enabled (SCR0/SCR1:RXE= 1), the receiving operation is always performed.
If a start bit is detected, the receive operation of 1 flame data is performed according to the data format set
in the control register (SCR0/SCR1). At the end of one frame reception, when reception error occurs, after
any one of reception error flag bit (PE, ORE, FRE) in status register (SSR0/SSR1) is set to "1", reception
data full flag bit (RDRF) is set to "1". If the receive interrupt request output is enabled (SSR0/SSR1:RIE=
"1"), then it output the receive interrupt request. Check each of the receiving flag bit (PE, ORE, FRE) of the
status register (SSR0/SSR1). If reception is normally done, then start reading the input data register
(SIDR0/SIDR1), and if there is an error, go to error handling procedure. The receiving data full flag bit
(RDRF) is cleared to "0" when the receiving data is read from the input data register (SIDR0/SIDR1).
● Stop Bit
During transmission, one bit or two bits can be selected. In sink, the first one bit is always distinguished.
● Error detection
• In the Operation mode 0, parity, overrun, and framing error can be detected.
• In the operation mode 1, the overrun errors and the flaming errors can be detected, but the parity errors
can not be detected.
● Parity
The parity can be used for operation mode 0. The parity enable bit (PEN) of the control register (SCR0/
SCR1) can sets the parity/non-parity settings, and the parity setting bit (P) can sets the even parity/odd
parity. The parity cannot be used by operation mode 1.
370
CHAPTER 16 UART
Figure 16.7-2 Transmission Data to which Parity is Effective
SI1
ST
SP
1 0 1 1 0 0 0
SO1
ST
Parity error generating at
reception with even parity
(SCR1: P=0)
SP
Transmission of even parity
(SCR1: P=0)
SP
Transmission of odd parity
(SCR1: P=1)
1 0 1 1 0 0 1
SO1
ST
1 0 1 1 0 0 0
Data
Parity
ST : Start bit
SP : Stop bit
Note: Parity can not be used in operating mode 1 and 2.
371
CHAPTER 16 UART
16.7.2
Operation in Synchronous Mode (Operation mode 2)
The UART uses clock-synchronous transfer method when used in operation mode 2
(normal mode).
■ Operation in Synchronous Mode (Operation mode 2)
● Transfer data format
In the synchronous mode, 8-bit data is transferred in LSB first.
Figure 16.7-3 Transfer Data Format (Operation mode 0 and 2)
Transfer data writing
Mark level
Transfer/reception clock
RXE,TXE
Transfer/reception data
1
LSB
0
1
1
Data
0
0
1
0
MSB
● Clock Supply
In the clock synchronous (I/O extended serial) method, the numbers of the clocks equal to the number of
the sending/receiving bit are required.
• If the internal clock has been set, the data receiving synchronous clock is generated when the data is
sent.
• If the external clock has been set, check the existence of the data (SSR0/SSR1: TDRE=0) in the output
data register (SODR0/SODR1) in the sender UART, then externally supply the clock for a duration
exactly corresponding to one byte. Make sure the mark level must be "H" before and after transmission
operations.
● Error detection
Overrun error can be detected, while parity and framing errors cannot be detected.
372
CHAPTER 16 UART
● Initialization
Describes the setting value of each control register when using the synchronous mode.
Mode register (SMR0/SMR1)
MD1, MD0
; Set "10B"
CS2, CS1, CS0
; Specifies the clock inputs of the clock selector
SCKE
; Dedicated baud rate generator or internal clock
Sets "1"
For the clock output, the external clock (clock input)
Set "0"
SOE
; "1" is set when transmitting.
"0" is set when receiving.
Control register (SCR0/SCR1)
PEN
; Set "0"
P, SBL, A/D
; No meaning
CL
; "1" (8-bit data) is set.
REC
; Set "0" (for the initialization, clear all of the error flag)
RXE, TXE
; "1" is set in either.
Status register (SSR0/SSR1)
RIE
; When the interruption is used, "1" is set.
When the interruption is not used, "0" is set.
TIE
; When the interruption is used, "1" is set.
When the interruption is not used, "0" is set.
● Starting communications
When send data is written to the output data register (SODR0/SODR1), communication starts. Note that the
transmitting data must be wrote into the output data register (SODR0/SODR1) before start communicating,
even if it is receiving operation.
● Terminating communications
When the transmission/reception operations of 1 frame data are completed, "1" is set to the receiving data
full flag bit (RDRF) of the status register (SSR0/SSR1). At receiving operation, check the over run error
flag bit (ORE) and determine whether the communication has been performed normally.
373
CHAPTER 16 UART
16.7.3
Bidirectional Communication Function (Normal mode)
In the operation mode 0, 2, one to one connection, serial bi-directional communication
can be performed. The communication clock mode becomes asynchronous for the
operation mode 0, synchronous for the operation mode 2.
■ Bidirectional Communication Function
To operate UART in the normal mode (operation mode 0, 2), the settings described in Figure 16.7-4 must
be set.
Figure 16.7-4 UART1 Operation Mode 0 Setting
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
PEN P SBL CL A/D REC RXE TXE MD1 MD0 CS2 CS1 CS0
SCR1,SMR1
Mode 0
Mode 2
SSR1,
SIDR1/SODR1
Mode 0
Mode 2
0
1
0
0
PE ORE FRE RDRF TDRE BDS RIE TIE
0
1
1
0
SCKE SOE
0
0
Set the conversion data (at writing)/
Hold the reception data (at reading)
DDR
:
:
1 :
0 :
:
Used bit
Unused bit
Set "1".
Set "0".
Set "0" when using pin input
● Inter-CPU connection
As shown in Figure 16.7-5 , connect 2 CPUs each other.
Figure 16.7-5 Example of Bidirectional Communication Connect for UART1
SO
SO
SI
SC
CPU-1
374
SI
Output
Input
SC
CPU-2
CHAPTER 16 UART
● Communication procedure
The communication starts from the sender when the sending data is ready for communication. When the
receiver receives the transmitting data, it periodically returns the ANS (returns per 1 byte in this example).
Figure 16.7-6 Flowchart for Bidirectional Communication
(Transmission side)
(Reception side)
Start
Start
Operation mode setting
(Either 0 or 2)
Operation mode setting
(Match with transmission side)
Set 1-byte data to SODR
and communicate
Data transfer
NO
Reception data is
existence.
YES
NO
Reception data is
existence.
Reception data read
abd process
YES
Data transfer
Reception data read
and process
(ANS)
1-byte data transfer
375
CHAPTER 16 UART
16.7.4
Master/Slave Mode Communication Function
(Multi-processor mode)
The UART allows master/slave communications between multiple CPUs in the operation
mode 1. UART is available as master.
■ Master/Slave Mode Communication Function
To operate UART in the multi-processor mode (operation mode 1), the settings described in Figure 16.7-7
must be set.
Figure 16.7-7 UART1 Operation Mode 1 Setting
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
PEN P SBL CL A/D REC RXE TXE MD1 MD0 CS2 CS1 CS0
SCR1,SMR1
0
SSR1,
SIDR1/SODR1
1
0
PE ORE FRE RDRF TDRE BDS RIE TIE
0
1
2
1
0
SCKE SOE
0
Set the transfer data (at writing)/
Hold the reception data (at reading)
DDR
:
:
1 :
0 :
:
Used bit
Unused bit
Set "1".
Set "0".
Set "0" when using pin input
● Inter-CPU connection
Communication system is configured by connecting a master CPU and plural slave CPU to two common
communication lines as shown in Figure 16.7-8 . UART1 is available as master CPU.
Figure 16.7-8 Connection Example for UART1 Master-slave Communications
SO
SI
Master CPU
SO
SI
Slave CPU #0
376
SO
SI
Slave CPU #1
CHAPTER 16 UART
● Function setting
In the master/slave type communication, set the operation mode and the data transfer method as described
in Table 16.7-2 .
Table 16.7-2 Setting of Master/Slave Mode Communication Function
Operating mode
Master CPU
Address transmission/
reception
Data
Parity
Synchronous
type
A/D= 1
+
8-bit address
Not provided
Asynchronous
Slave CPU
Operation
mode 1
Stop bit
1 bit
or
2 bit
Data transmission/
reception
A/D = 0
+
8-bit data
377
CHAPTER 16 UART
● Communication procedure
The communication starts when the master CPU transmits the address data. The address data is the data
which assume A/D bit as "1", and addresses the communicating slave CPU. Each slave CPU checks the
address data using program, and if the address data matches with the address assigned to the slave CPU, it
starts the communication (normal data) with the master CPU.
Figure 16.7-9 Flowchart for Master/Slave Communications
(Master CPU)
Start
Regarded operation
mode as "1"
Input SIN pin to serial
data input
Set 1-byte data (address
data) selecting slave CPU
to D0 to D7 and transmit
(A/D=1)
Set "0" to A/D
Enable reception operation
Slave CPU and
communication
Communication end?
NO
YES
Other
slave CPU and
communication
NO
YES
Disable reception operation
End
378
CHAPTER 16 UART
16.8
Notes on Using UART
Notes when UART is used are shown.
■ Notes on Using UART
● Enabling Operations
UART has the transmission operation enable bit (TXE) and the reception operation enable bit (RXE) in the
control register. Because the initial value of the transmission/reception operation enable bit (TXE, RXE)
are defaulted to "0" and operations are disabled, set "1" to enable the transmission/reception operation
before start transferring the data. If required, the transfer operation can be stopped by disabling the
transmission/reception operation.
● Setting of communication mode
Please make setting the communicate mode under suspension. If the communication mode is set during the
transmission/reception operation, there is no guarantee of the data which has been transmitted/received.
● Synchronous mode
UART clock synchronous mode (operation mode 2) adopt the clock control (I/O extended serial) method,
and the start bit and the stop bit are not added to the data.
● Transmission interrupt enable timing
When transmit data is transferred from the serial output data register (SODR1) to the transmit shift register,
the transmit data empty flag bit (bit11: TDRE) in the serial status register (SSR1) is set to "1".If a transmit
interrupt is enabled (bit8: TIE = 1), a transmit interrupt is requested.
As the initial value is set to "1" (without transfer data, transfer data writing enable) in transmit data empty
flag bit (TDRE) of status register (SSR0/SSR1), immediately after enabling transfer interrupt request
output (SSR0/SSR1:TIE="1"), transfer interrupt is output. The transmitting data must be ready before you
set "1" to the transmission interrupt request enable bit (TIE).
● Reception of operation mode 1 (multi processor mode)
In UART operation mode 1 (multi-processor mode), the receiving operation in 9-bit receiving can not be
performed.
● Clock setting in clock synchronous mode
When using the dedicated baud rate generator in clock synchronous mode, do not make the following
setting.
• CS2 to CS0 = 000B
• CS2 to CS0 = 001B, DIV2 to DIV0 = 000B
379
CHAPTER 16 UART
380
CHAPTER 17
DTP/EXTERNAL INTERRUPT
CIRCUIT
This chapter describes the functions and the operations
of the MB90800 series DTP/External interrupt circuit.
17.1 Overview of DTP/External Interrupt Circuit
17.2 Configuration of DTP/External Interrupt Circuit
17.3 Pins of External DTP/Interrupt Circuit
17.4 Register for DTP/External Interrupt Circuit
17.5 Operation of DTP/External Interrupt Circuit
17.6 Notes on Using DTP/External Interrupt Circuit
381
CHAPTER 17 DTP/EXTERNAL INTERRUPT CIRCUIT
17.1
Overview of DTP/External Interrupt Circuit
DTP (data Transfer Peripheral)/External interrupt circuit detects the interrupt request
input from the external interrupt input terminal, and outputs the interrupt request.
■ DTP/External Interrupt Function
The function of DTP/External interrupt circuit outputs the interrupt request when it detects the edge signal
or level signal input into the external interrupt input terminal.
If CPU accept the interrupt request, and if the extended intelligent I/O service (EI2OS)) is enabled,
branches to the interrupt handling routine after completing the automatic data transfer (DTP function)
performed by EI2OS. And if EI2OS is disabled, it branches to the interrupt handling routine without
activating the automatic data transfer (DTP function) performed by EI2OS.
Table 17.1-1 Overview of DTP/External Interrupt
Interrupt function
DTP function
Input Pin
4 Channel (P65/INT0, P66/INT1, P67/INT2, P70/INT3)
Interrupt cause
The detection level or the type of the edge for each terminals can be set in the request level setting
register (ELVR).
Input of "H" level or "L" level
Rising edge, or falling edge
Interrupt number
#11(0BH), #13(0DH), #16(10H)
Interrupt control
Enabling/Disabling the interrupt request output using the DTP/interrupt enable register (ENIR)
Interrupt flag
Holding the interrupt causes using the DTP/interrupt cause register (EIRR)
Processing setting
The EI2OS is disabled.
(ICR:ISE= 0)
The EI2OS is enabled.
(ICR:ISE= 1)
Processing
Branched to the interrupt handling routine
After an automatic data transfer by EI2OS
Branched to the interrupt handling routine
ICR: Interrupt control register
382
CHAPTER 17 DTP/EXTERNAL INTERRUPT CIRCUIT
■ DTP/External Interrupt Circuit and EI2OS
Table 17.1-2 DTP/External Interrupt Circuit and EI2OS
Channel
Interrupt
number
Interrupt control registers
Vector table address
EI2OS
Register Name
Address
Low
High
Bank
INT0
#11(0BH)
ICR00
0000B0H
FFFFD0H
FFFFD1H
FFFFD2H
INT1
#13(0DH)
ICR01
0000B1H
FFFFC8H
FFFFC9H
FFFFCAH
#16(10H)
ICR02
0000B2H
FFFFBCH
FFFFBDH
FFFFBEH
INT2
INT3
: Possible to use
383
CHAPTER 17 DTP/EXTERNAL INTERRUPT CIRCUIT
17.2
Configuration of DTP/External Interrupt Circuit
DTP/External interrupt circuit is configured of the blocks described below.
• DTP/External interruption input detector circuit
• DTP/External interruption factor register (EIRR)
• DTP/External interruption permission register (ENIR)
• Request level set register (ELVR)
■ Block Diagram of the DTP/External Interrupt Circuit
Figure 17.2-1 Block Diagram of the DTP/External Interrupt Circuit
Request level setting register (ELVR)
LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0
Selector
DTP/external
interruption
input detector
circuit
Pin
INT0
Selector
Pin
INT1
Internal data bus
Selector
Pin
INT2
Pin
Selector
INT3
DTP/external interruption factor
register (EIRR)
ER3
ER2
ER1
ER0
Interrupt request
DTP/external interruption
permission register (ENIR)
EN3
384
EN2
EN1
EN0
CHAPTER 17 DTP/EXTERNAL INTERRUPT CIRCUIT
● DTP/external interrupt input detection circuit
If an input signal into the external interrupt input terminal matches to the edge level set in the request level
setting register (ELVR), the DTP/External interrupt factor flag bit (EIRR:ER3 to ER0) is set to "1".
● A register to specify the required level (ELVR)
For each of the external interrupt input terminal, set the detecting condition of the interrupt request (level or
edge).
● DTP/External interruption factor register (EIRR)
Holding or clearing the interrupt cause.
● DTP/External interruption permission register (ENIR)
Set the Enabling/Disabling of the interrupt request for each external interrupt input terminal.
385
CHAPTER 17 DTP/EXTERNAL INTERRUPT CIRCUIT
17.3
Pins of External DTP/Interrupt Circuit
Describes the terminal of the DTP/External interrupt circuit and block diagram of the
terminal part.
■ Pins of DTP/External Interrupt Circuit
DTP/External interrupt circuit serves as both input and output ports.
Table 17.3-1 Pins of DTP/External Interrupt Circuit
Pin name
P65/AN5/
INT0
Pin function
I/O type
Port 6 I/O /
A/D analog input/
External interrupt
Input
CMOS output/
CMOS
hysteresis input
Pull-up
resistance
Stand-by
control
None
None
To the use of the terminal setting
Set to the input port
(DDR6:bit5= 0)
Analog input interdiction
(ADER0: bit5= 0)
P66/AN6/
INT1
Set to the input port
(DDR6:bit6= 0)
Analog input interdiction
(ADER0: bit6= 0)
P67/AN7/
INT2
Set to the input port
(DDR6:bit7= 0)
Analog input interdiction
(ADER0: bit7= 0)
P70/AN8/
INT3
Port 7 I/O /
A/D analog input/
External interrupt
Input
Set to the input port
(DDR7:bit0= 0)
Analog input interdiction
(ADER1: bit0= 0)
■ The Block Diagram of the DTP/External Interrupt Circuit Terminal Part
Internal data bus
Figure 17.3-1 The Block Diagram of the DTP/External Interrupt Circuit Terminal Part
PDR read
PDR
PDR write
DDR
386
I/O judge
circuit
Input buffer
Output buffer
Standby control (LPMCR: SPL=1)
Port pin
CHAPTER 17 DTP/EXTERNAL INTERRUPT CIRCUIT
17.4
Register for DTP/External Interrupt Circuit
Figure 17.4-1 shows Register list of DTP/external interrupt circuit.
■ Register for DTP/External Interrupt Circuit
Figure 17.4-1 Register List of DTP/External Interrupt Circuit
bit15
bit8 bit7
DTP/interrupt factor register (EIRR)
bit0
DTP/interrupt enable register (ENIR)
Request level setting register (ELVR)
387
CHAPTER 17 DTP/EXTERNAL INTERRUPT CIRCUIT
17.4.1
DTP/External Interruption Factor Register (EIRR)
DTP/Interrupt factor register (EIRR) holds and clears the interrupt cause.
■ DTP/External Interruption Factor Register (EIRR)
Figure 17.4-2 DTP/External interruption Factor Register (EIRR)
Address Bit
15
14
000031H
R/W
X
388
: Readable/Writable
: Indefinite
: Undefined
13
12
11
10
9
8
ER3 ER2
ER1 ER0
R/W R/W
R/W R/W
ER3
to
ER0
0
1
Initial value
----XXXXB
External interrupt request flag bit
Read
Write
No interrupt request
Clear interrupt request
Interrupt request
No effect to operation
CHAPTER 17 DTP/EXTERNAL INTERRUPT CIRCUIT
Table 17.4-1 Functional Explanation of Each Bit of the DTP/Interrupt Factor Register (EIRR)
Bit name
Functions
bit15
to
bit12
Undefined bits
This setting becomes invalid.
bit11
ER3:
External interrupt request flag
bit
• It is a flag bit of the interrupt request.
• "1" is set to the external interrupt input terminal (INT0) if the level
that was set in the external interrupt request detecting condition
setting bit (LB0, LA0) of the request level setting register (ELVR)
or the edge signal are detected.
• When "1" has been set to the external interrupt request permission
bit (EN3) of the DTP/External interrupt permission register (ENIR),
and if "1" is set, it outputs the interrupt request to CPU.
• When "0" is set, the interrupt request is cleared.
• If "1" is set, the operation is not affected.
bit10
ER2:
External interrupt request flag
bit
• It is a flag bit of the interrupt request.
• "1" is set to the external interrupt input terminal (INT2) if the level
that was set in the external interrupt request detecting condition
setting bit (LB2, LA2) of the request level setting register (ELVR)
or the edge signal are detected.
• When "1" has been set to the external interrupt request permission
bit (EN2) of the DTP/External interrupt permission register (ENIR),
and if "1" is set, it outputs the interrupt request to CPU.
• When "0" is set, the interrupt request is cleared.
• If "1" is set, the operation is not affected.
bit9
ER1:
External interrupt request flag
bit
• It is a flag bit of the interrupt request.
• "1" is set to the external interrupt input terminal (INT1) if the level
that was set in the external interrupt request detecting condition
setting bit (LB1, LA1) of the request level setting register (ELVR)
or the edge signal are detected.
• When "1" has been set to the external interrupt request permission
bit (EN1) of the DTP/External interrupt permission register (ENIR),
and if "1" is set, it outputs the interrupt request to CPU.
• When "0" is set, the interrupt request is cleared.
• If "1" is set, the operation is not affected.
bit8
ER0:
External interrupt request flag
bit
• It is a flag bit of the interrupt request.
• "1" is set to the external interrupt input terminal (INT1) if the level
that was set in the external interrupt request detecting condition
setting bit (LB0, LA0) of the request level setting register (ELVR) or
the edge signal are detected.
• When "1" has been set to the external interrupt request permission
bit (EN0) of the DTP/External interrupt permission register (ENIR),
and if "1" is set, it outputs the interrupt request to CPU.
• When "0" is set, the interrupt request is cleared.
• If "1" is set, the operation is not affected.
389
CHAPTER 17 DTP/EXTERNAL INTERRUPT CIRCUIT
Reference:
If the extended intelligent I/O service (EI2OS) has been activated as the DTP function, at the time of
one data transfer is completed, the corresponding external request flag bit (ER3 to ER0) is cleared to
"0".
Notes:
• If you set the external interrupt request flag bit (ER3 to ER0) to "0", you must also set the "0" to
the bit which was read as "1" by the software. If you want to set "0" to the external interrupt
request flag bit (ER3 to ER0), but it has been set to "1" by the hardware, the interrupt operation
may not work correctly because of clearing the external interrupt request flag bit (ER3 to ER0) to
"0".
• The value of the DTP/external interrupt factor bit (EIRR: ER) is valid only when the corresponding
DTP/external interrupt enable bit (ENIR: EN) is set to "1".
For the state which the DTP/external interrupt is not enabled (ENIR:EN=0), the DTP/external
interrupt factor bit may be set regardless of the presence or absence of the DTP/external interrupt
factor.
• Be sure to clear the DTP/external interrupt factor bit (EIRR: ER) immediately before the DTP/
external interrupt is enabled (ENIR: EN=1).
390
CHAPTER 17 DTP/EXTERNAL INTERRUPT CIRCUIT
17.4.2
DTP/External Interruption Permission Register (ENIR)
DTP/External interruption permission register (ENIR) sets Enable/Disable for the
external interrupt request for each external interrupt terminal.
■ DTP/External Interruption Permission Register (ENIR)
Figure 17.4-3 DTP/External interruption Permission Register (ENIR)
Address Bit
7
6
5
4
3
2
1
0
Initial value
EN3 EN2 EN1 EN0
000030H
----0000B
R/W R/W R/W R/W
R/W
: Readable/Writable
: Initial value
: Undefined bit
EN3
to
EN0
0
Disable interrupt request
1
Enable interrupt request
External interrupt request enable bit
Table 17.4-2 Functional Explanation of the Each Bit of DTP/Interrupt Permission Register (ENIR)
Bit name
Function
bit7
to
bit4
Undefined bits
Τhis setting becomes invalid.
bit3
EN3:
External interrupt request
enable bit
• It is a bit by which the interrupt request is permitted.
• When "1" has been set, and if "1" is set to the external interrupt
request flag bit (ER3) of the DTP/Interrupt factor register (EIRR), it
outputs the interrupt request to CPU.
bit2
EN2:
External interrupt request
enable bit
• It is a bit by which the interrupt request is permitted.
• When "1" has been set, and if "1" is set to the external interrupt
request flag bit (ER2) of the DTP/Interrupt factor register (EIRR), it
outputs the interrupt request to CPU.
bit1
EN1:
External interrupt request
enable bit
• It is a bit by which the interrupt request is permitted.
• When "1" has been set, and if "1" is set to the external interrupt
request flag bit (ER1) of the DTP/Interrupt factor register (EIRR), it
outputs the interrupt request to CPU.
bit0
EN0:
External interrupt request
enable bit
• It is a bit by which the interrupt request is permitted.
• When "1" has been set, and if "1" is set to the external interrupt
request flag bit (ER0) of the DTP/Interrupt factor register (EIRR), it
outputs the interrupt request to CPU.
391
CHAPTER 17 DTP/EXTERNAL INTERRUPT CIRCUIT
Note:
Be sure to clear the DTP/external interrupt factor bit (EIRR: ER) immediately before the DTP/external
interrupt is enabled (ENIR: EN=1).
Reference:
If you use the shared input/output port as an external interrupt input terminal, set the bit of the port
direction register (DDR), corresponding to the external interrupt input terminal, to "0", and use the
terminal as an input port.
Regardless of the status of the external interrupt request enable bit (ENIR:EN3 to EN0), the status of
the external interrupt input terminal can read directly using the port data register (PDR). Regardless
of the value in the external interrupt request enable bit (ENIR:EN3 to EN0), "1" is set to the external
interrupt request flag bit (ER3 to ER0) of the DTP/Interrupt cause register (EIRR) when it detects the
DTP/External interrupt request signal.
Table 17.4-3 Associating the DTP/Interrupt Control Register (EIRR, ENIR) and Each Channel
DTP/External interrupt pin
Interrupt number
INT3
INT2
392
#16(10H)
External interrupt request
flag bit
External interrupt request
enable bit
ER3
EN3
ER2
EN2
INT1
#13(0DH)
ER1
EN1
INT0
#11(0BH)
ER0
EN0
CHAPTER 17 DTP/EXTERNAL INTERRUPT CIRCUIT
17.4.3
Request Level Setting Register (ELVR)
The request level setting register (ELVR) sets the detect condition of the interrupt
request (level or edge) for each of the external interrupt input terminal.
■ Request Level Setting Register (ELVR)
Figure 17.4-4 Request Level Setting Register (ELVR)
7
Address Bit
000032H
LB3
6
LA3
5
4
LB2
3
LA2
LB1
R/W R/W R/W R/W
R/W
: Readable/Writable
: Initial value
2
LA1
1
LB0
0
Initial value
LA0
00000000B
R/W R/W R/W R/W
LB3
to
LB0
0
LA3
to
LA0
0
"L" level detection
0
1
"H" level detection
1
0
Rising edge detection
1
1
Falling edge detection
External interrupt request detection
condition setting bit
Table 17.4-4 Functional Explanation of Each Bit of the Request Level Setting Register (ELVR)
Bit name
Functions
bit7,
bit6
LB3, LA3:
External interrupt request
detecting condition setting bit
It is the bit which sets the interrupt request detecting condition (level or edge)
from the signals input into the external interrupt input terminal (INT3).
bit5,
bit4
LB2, LA2:
External interrupt request
detecting condition setting bit
It is the bit which sets the interrupt request detecting condition (level or edge)
from the signals input into the external interrupt input terminal (INT2).
bit3,
bit2
LB1, LA1:
External interrupt request
detecting condition setting bit
It is the bit which sets the interrupt request detecting condition (level or edge)
from the signals input into the external interrupt input terminal (INT1).
bit1,
bit0
LB0, LA0:
External interrupt request
detecting condition setting bit
It is the bit which sets the interrupt request detecting condition (level or edge)
from the signals input into the external interrupt input terminal (INT0).
Reference:
If the detect signal which has been set in the request level setting register (ELVR) is input into the
external interrupt input terminal, "1" is set to the external interrupt request flag bit (EIRR:ER3 to ER0)
of corresponding terminal regardless of the setting of the DTP/Interrupt enable register bits
(EIRR;ER3 to ER0).
393
CHAPTER 17 DTP/EXTERNAL INTERRUPT CIRCUIT
Table 17.4-5 Associating the Request Level Setting Register (ELVR) and Each Channel
DTP/External interrupt
Interrupt number
LB3, LA3
INT3
INT2
394
Bit name
#16(10H)
LB2, LA2
INT1
#13(0DH)
LB1, LA1
INT0
#11(0BH)
LB0, LA0
CHAPTER 17 DTP/EXTERNAL INTERRUPT CIRCUIT
17.5
Operation of DTP/External Interrupt Circuit
DTP/External interrupt circuit has the external interrupt function and DTP function. The
setting and operation of each function are explained.
■ DTP/External Interrupt Setting
To operate DTP/External interrupt circuit, you need setting described in Figure 17.5-1 .
Figure 17.5-1 DTP/External Interrupt Circuit
Bit
ICR
EIRR/
ENIR
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ICS3ICS2 ICS1ICS0 ISE IL2 IL1 IL0 ICS3ICS2 ICS1ICS0 ISE IL2 IL1 IL0
0
0
At external interrupt
1
1
At DTP
ER3ER2 ER1ER0
ELVR
EN3EN2 EN1EN0
LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0
P70 P67 P66 P65
DDR
: Used bit
: Set "1" to the bit corresponding to using pin
: Set "0" to the bit corresponding to using pin
0 : Set "0"
1 : Set "1"
The register of the DTP/External interrupt circuit should be set using the procedure described below in
order to avoid the incorrect output of the interrupt request when setting the register.
1. The general-purpose I/O port that shared with the pin used as an external interruption input is set to the
input port.
2. Set "00H" to the DTP/Interrupt enable register (ENIR) to prohibit the interrupt request.
3. Set the interrupt detect condition to the external interrupt request detect condition setting bit (LB3 to
LB0, LA3 to LA0) corresponds to the external interrupt input terminal of the request level setting
register (ELVR).
4. Clear the interrupt request by setting "0" to the external interrupt request flag bit (ER3 to ER0)
corresponds to the external interrupt input terminal of the DTP/interrupt factor register (EIRR).
5. Enables the interrupt request by setting "1" to the external interrupt request enable bit (EN3 to EN0)
corresponds to the external interrupt input terminal of the DTP/Interrupt permission register (ENIR).
● Switch of external interruption function and DTP function
Selects the external interrupt function or the DTP function, using the EI2OS enable bit (ISE) of the interrupt
control register (ICR) corresponding to the interrupt cause to be used. If "1" has been set to the EI2OS
enable bit (ISE), the extended intelligent I/O service (EI2OS) is permitted and operates as the ETP function.
And if "0" has been set to the EI2OS enable bit (ISE), the EI2OS is prohibited and operates as the external
interrupt function.
395
CHAPTER 17 DTP/EXTERNAL INTERRUPT CIRCUIT
■ DTP/External Interrupt Operation
Table 17.5-1 The Control Bit of the DTP/External Interrupt Circuit and the Interrupt
Causes
DTP/External interrupt circuit
Interrupt request flag bit
EIRR:ER3 to ER0
Interrupt request enable bit
ENIR:EN3 to EN0
Interrupt cause
Input of valid edge/level to INT3 to INT0 pins
TP/Interrupt circuit first sets the request level setting register (ELVR), DTP/interrupt cause register (EIRR),
and DTP/Interrupt enable register (ENIR), then issues the interrupt request to the interrupt controller when
it detects a signal set in the request level setting register (ELVR). If "0" has been set to the EI2OS enable bit
(ICR:ISE) of the interrupt control register, interrupt handling is processed, and if "1" has been set instead,
then the extended intelligent I/O service (DTP handling) is processed before the interrupt is handled.
Figure 17.5-2 Operation of DTP/External Interrupt Circuit
DTP/external interrupt circuit
Other
request Interrupt controller
ELVR
ICR YY
EIRR
CMP
ICR XX
ENIR
CPU
IL
CMP
ILM
Interrupt process
micro program
Factor
DTP process routine
(EI2OS activation)
DTP/external interrupt
request output
Memory
Peripheral data transfer
Descriptor renewal
Interrupt controller
reception judge
Descriptor
data counter
CPU interrupt
reception judge
0
=0
Interrupt process routine
Reset or stop
Recovery from DTP process
Interrupt process
micro program activation
ICR: ISE
CPU process recovery
1
0
Activate external interrupt routine
Process and interrupt flag clear
Recovery from external interrupt
396
CHAPTER 17 DTP/EXTERNAL INTERRUPT CIRCUIT
17.5.1
External Interrupt Function
DTP/External interrupt circuit has the external interrupt function which issues an
interrupt request triggered by the input signal of the external interrupt input terminal.
■ External Interrupt Function
If a signal with a level set in the request level setting register (ELVR) is input into the external interrupt
input terminals, "1" will be set to the external interrupt request flag bit (ER3 to ER0) of the DTP/Interrupt
cause register (EIRR), corresponding to the DTP/interrupt request terminals.
When "1" has been set to the external interrupt request permission bit (EN3 to EN0) of the DTP/Interrupt
permission register (ENIR), corresponding to the external interrupt input terminals, an interrupt request is
issued to the interrupt controller, if "1" is set to the external interrupt request flag bit (ER3 to ER0).
Interrupt controller judges interrupt level (ICR: IL2 to IL0) of interrupt request from peripheral (resource)
and the priority order by simultaneous output of interrupt and CPU judges whether receiving interrupt
request by interrupt level mask register (PS: ILM) and interrupt enable flag (PS: CCR: 1). If CPU accepts
the interrupt request, it performs the interrupt process, and will be branched to the interrupt handling
routine. In the interrupt handling program, clear the interrupt request by setting "0" to corresponding
external interrupt request flag bit (ER3 to ER0), and return from the interrupt using interrupt return
instruction.
Note:
If the interrupt handler is activated, make sure to set "0" to the external interrupt request flag bit
(EIRR:EN3 to EN0) which activated the program. If "1" is set to the external interrupt request flag bit
(EIRR:EN3 to EN0), it can not be return from the interrupt.
397
CHAPTER 17 DTP/EXTERNAL INTERRUPT CIRCUIT
17.5.2
DTP Function
DTP/External interrupt circuit has the DTP (Data Transfer Peripheral) function which
detects the data transfer request signals input into the external interrupt input terminal
from externally connected peripheral devices and activate the extended I/O service.
■ Operating Explanation of DTP Function
DTP function detects the data transfer request signals input into the external interrupt input terminal from
externally connected peripheral devices and performs the automatic transfer of the data between memory
and the peripheral devices.
External function activates the intelligent I/O service. Although it functions similarly to the external
interrupt function until the CPU accept the interrupt request, it activates the EI2OS and starts transferring
the data with the interrupt request, if the operation of EI2OS is enabled (ICR:ISE= 1). When the data
transfer is completed, it updates the descriptor and other elements, clears the external interrupt request flag
bit (EIRR:ER3 to ER0) to "0", and operates as the external interrupt function again. When the transfer by
EI2OS finishes completely, it will be branched to the interrupt process routine which the vector address of
the external interrupt points to. For the externally connected peripheral equipment, cancel the factor input
of the data transfer request signal (DTP factor) within 3 machine cycles after the first transfer started.
Figure 17.5-3 Example of Interface with External Peripheral Equipment
"H" level request (ELVR: LB0,LA0=01B)
Input to INT0 pin
(DTP factor)
CPU internal operation
(micro program)
Descriptor
select and read
Address bus pin
Descriptor
renewal
Read address
Write address
Read data
Data bus pin
Write data
Read signal
Write signal
*1
Peripheral
equipment
of external
connection
Register
Data transfer
request
Internal data bus
Read operation*1
DTP factor*2
Interrupt
INT DTP/external request
interrupt circuit
Write operation*3
CPU
(EI2OS)
*1: 3-machine cycle
*2: After transfer starts, withdraw within 3-machine cycle.
*3: When extended intelligent I/O service is "peripheral memory transfer"
398
Internal
memory
CHAPTER 17 DTP/EXTERNAL INTERRUPT CIRCUIT
17.6
Notes on Using DTP/External Interrupt Circuit
Shows the cautions relevant to the input signal of the DTP/External interrupt circuit,
releasing the standby mode, and the interrupt.
■ Notes on Using DTP/External Interrupt Circuit
● Condition of external-connected peripheral device when DTP function is used
The externally connected peripheral device which can support the DTP functions must be able to clear the
data transfer request automatically upon the transfer completion. If the externally connected peripheral
device continue outputting the transfer request more than 3 cycles after the CPU has started data transfer,
the DTP/External interrupt circuit re-starts the data transfer operation, assuming next transfer request has
occurred.
● External interrupt input polarity
• If the request level setting register (ELVR) is set as the edge detect, input pulse must maintain the level
for minimum 3 machine cycles or more from the input level cross point, in order for the input to be
detected as the edge interrupt.
• When a level causing an interrupt factor is input with level detection set in the detection level setting
register, the DTP/external interrupt request flag bit (EIRR: ER) in the DTP/external interrupt factor
register is set to "1" and the factor is held as shown in Figure 17.6-1 .
• Interrupt is enabled
If the request level setting register (ELVR) is set as the level detect, when a level causing an interrupt
request is input, "1" is set to factor flip-flop of internal DTP/interrupt factor register (EIRR) as shown in
Figure 17.6-1 and it retain to hold the factor. Therefore, even after withdrawing interrupt factor, request
to interrupt controller is left output. To cancel the request to the interrupt controller, set the external
interrupt request flag bit (EIRR: ER3 to ER0) to "0" and clear the interrupt cause flip flop to "0" as
shown in Figure 17.6-2 .
Figure 17.6-1 Clearness of Factor Holding Circuit when Level is Set
DTP/external
interrupt factor
DTP/external
interrupt input
detection circuit
Factor flip-flop
(EIRRregister)
Enable gate
To interrupt
controller
(interrupt request)
Maintained to hold the factor except for clear
399
CHAPTER 17 DTP/EXTERNAL INTERRUPT CIRCUIT
Figure 17.6-2 DTP/External Interrupt Causes and Interrupt Requests in Case of Interrupt-request-out
Enabled.
DTP/external interrupt factor
(at "H" level detection)
Withdrawal of interrupt factor
interrupt request to
interrupt controller
Invalidated by clear of factor flip-flop
● Precautions on interrupts
When it was branched to the interrupt handling routine by the external interrupt, it can not return from the
interrupt handling program if status of the external interrupt request flag bit (EIIR:ER3 to ER0) is "1" and
the external interrupt request enable bits (ENIR;EN3 to EN0) are "1". Be sure to clear the external interrupt
request flag bit (EIRR:ER3 to ER0) to "0" in the interrupt handling program (If the DTP function is used,
the external interrupt request flag bit (EIRR:ER3 to ER0) is clears to "0" by EI2OS).
In the level detect mode, if the level signal of the interrupt request is held on the external interrupt input pin
(INT3 to INT0), "1" will be set to the external interrupt request flag bit (EIRR: ER3 to ER0) again even if
you set "0" to the external interrupt request flag bits (EIR;ER3 to ER0) and therefore, you cannot return
from the interrupt. To return from the interrupt, disable the interrupt request or clear the interrupt request
level signal.
400
CHAPTER 18
I2C INTERFACE
This chapter describes the functions and the operations
of the MB90800 series I2C interface.
18.1 I2C Interface Outline
18.2 Block Diagram and Unit Configuration of I2C Interface
18.3 I2C Interface Register
18.4 I2C Interface Operation
401
CHAPTER 18 I2C INTERFACE
18.1
I2C Interface Outline
I2C interface is the serial input-output port that support Inter IC BUS and functions as
the master/slave device on the I2C bus. It has the features below.
■ Features of I2C Interface
MB90800 series have 1 channel of the built-in I2C interface.
The feature in the I2C interface is shown as follows.
• Master/slave transmission/reception
• Arbitration function
• Clock synchronous
• Slave address/General call address detection function
• Transfer direction detection function
• Repeat generating and detecting function of the start conditions
• Bus error detection function
• The transfer rate can be supported to 100Kbps
402
CHAPTER 18 I2C INTERFACE
18.2
Block Diagram and Unit Configuration of I2C Interface
Figure 18.2-1 shows the block diagram of I2C interface, and Figure 18.2-2 shows the unit
configuration of I2C interface.
■ Block Diagram of I2C Interface
Figure 18.2-1 Block Diagram of I2C Interface
ICCR
I2C enable
EN
Clock division 1
5 6 7 8
ICCR
CS4
Machine clock
Clock selection 1
CS3
Clock division 2
2 4 8 16 32 64 128 256
CS2
CS1
CS0
Clock selection 2
Internal data bus
Shift clock
generation
Shift clock
edge change timing
IBSR
Bus busy
BB
RSC
Sync
Repeat start
Last Bit
LRB
Start/stop condition
detection
Transmit/
receive
TRX
Error
FBT
First Byte
AL
Arbitration lost detection
IBCR
BER
SCL
BEIE
Interrupt request
INTE
IRQ
SDA
INT
IBCR
SCC
MSS
ACK
GCAA
End
Start
Master
ACK enable
Start/stop condition
generation
GC-ACK enable
IDAR
IBSR
AAS
GCA
Slave
Global call
Slave address
comparison
IADR
403
CHAPTER 18 I2C INTERFACE
■ Unit Configuration of I2C Interface
Figure 18.2-2 Unit Configuration of I2C Interface
SCL
R
SDA
R
N-ch
I2C interface
N-ch
404
External fixed
I2C interface
CHAPTER 18 I2C INTERFACE
I2C Interface Register
18.3
I2C interface supports following 5 types of registers.
• I2C status register (IBSR)
• I2C control register (IBCR)
• I2C clock control register (ICCR)
• I2C address register (IADR)
• I2C data register (IDAR)
■ I2C Interface Register
Figure 18.3-1 I2C Interface Register
bit15
bit8
bit7
bit0
I2C status register (IBSR)
I2C control register (IBCR)
I2C clock control register (ICCR)
I2C address register (IADR)
I2C data register (IDAR)
405
CHAPTER 18 I2C INTERFACE
18.3.1
I2C Status Register (IBSR)
I2C status register (IBSR) supports the following functions.
• Repeat detection of the start condition • Slave addressing detection
• arbitration lost detection
• General call address detection
• Acknowledge storing
• Data transfer
• Byte 1 detection
■ I2C Status Register (IBSR)
Figure 18.3-2 I2C Status Register (IBSR)
Address Bit
7
6
5
4
3
2
1
0
Initial value
00006AH
BB
RSC
AL
LRB
TRX
AAS
GCA
FBT
00000000B
R
R
R
R
R
R
R
R
FBT
0
First byte detection bit
Reception data is other than first byte.
1
Reception data is first byte.
GCA
0
General call address detection bit
General call address is not received at slave.
1
General call address is received at slave.
AAS
0
Slave addressing detection bit
Addressing is not carried out at slave.
1
Addressing is carried out at slave.
TRX
0
Transfer state bit
Reception state
1
Transfer state
LRB
0
Acknowledge storing bit
The reception is confirmed.
1
The reception is not confirmed.
AL
0
Arbitration lost detection bit
Arbitration lost is not detected.
Arbitration lost is generated during
1
master transfer or set "1" to MSS bit
when other system is using the bus
RSC
No repeat start condition detection
1
Repeat start condition detection
BB
R
: Read only
: Initial value
406
Repeat start condition detection bit
0
Bus state bit
0
Detect stop condition
1
Detect start condition (at using bus)
CHAPTER 18 I2C INTERFACE
Table 18.3-1 Functional Explanation of Each Bit I2C Status Register (IBSR)
Bit name
Functions
bit7
BB:
Bus state bit
• The state of the I2C bus is shown.
• When the stop condition is detected, "0" is read.
• When the start condition is detected, "1" is read.
bit6
RSC:
Repeat start condition
detection bit.
• The start condition is repeatedly detected.
• While the bus is in use, "1" is read if the start condition is detected again.
• If "0" is set to the INT bit and it is not addressed in the slave mode, it will be cleared
to "0" by detecting the start condition in bus stop state or detecting stop condition.
bit5
AL:
Arbitration lost
detection bit
• The arbitration lost is detected.
• If the arbitration lost occurred during master transmission mode, or if "1" is set to
MSS bit while other system is using the bus, then "1" is read.
• If "0" is set to the INT bit, it is cleared to "0".
bit4
LRB:
Acknowledge storing
bit
• Stores the acknowledge from the receiver.
"0": the reception is confirmed.
"1": the reception is not confirmed.
• It is cleared by detecting of the start condition or stop condition.
bit3
TRX:
Transfer state bit
• Transmitting and receiving the data transfer is shown.
•"0" is read to receiving state.
•"1" is read to send state.
bit2
AAS:
Slave addressing
detection bit
• Addressing is detected.
• When addressing is done at the slave, "1" is read.
• It is cleared to "0" by detecting of the start condition or stop condition.
bit1
GCA:
General call address
detection bit
• General call address (00H) is detected.
• When you receive the General call address, "1" is read.
• It is cleared to "0" by detecting of the start condition or stop condition.
bit0
FBT:
First byte detection bit
• The first byte is detected.
• When receiving data is the first byte (address data), then "1" is read.
• Even if "1" is set by detecting the start condition, it will be cleared to "0" if "0" has
been set to the INT bit or not addressed in the slave mode.
407
CHAPTER 18 I2C INTERFACE
18.3.2
I2C Control Register (IBCR)
I2C control register supports the following functions.
• Interrupt request/Interrupt enable
• Start condition generation
• Master/slave setting
• Acknowledge generation enable
■ I2C Control Register (IBCR)
Figure 18.3-3 I2C Control Register (IBCR)
Address Bit 15
00006BH
14
13
12
11
10
9
8
BER BEIE SCC MSS ACK GCAA INTE INT
R/W R/W R/W R/W
R/W R/W R/W R/W
INT
0
1
Transfer end interrupt request flag bit
Read
Disable interrupt request
1
Enable interrupt request
No effect to operation
Acknowledge generation enable bit
0
Not generating acknowledge
1
Generating acknowledge
ACK
Clear interrupt request.
Interrupt request enable bit
0
GCAA
Acknowledge generation enable bit
0
Not generating acknowledge
1
Generating acknowledge
Master/slave setting bit
MSS
0
Generating stop condition and being transfer end slave mode
1
Becoming as master mode, generating start condition and starting address data transfer
Start condition generation bit
SCC
0
1
Noeffect to operation
Start condition is generated again at master transfer and
address data transfer is restarted.
Bus error interrupt enable bit
BEIE
0
Bus error interrupt request disabled
1
Bus error interrupt request enabled
BER
408
Write
Transfer is not finished.
Set as other table condition
after transfer end.
INTE
R/W : Readable/Writable
: Initial value
Initial value
00000000B
Bus error interrupt request flag bit
Read
Write
0
Interrupt request
Clear interrupt request
1
No interrupt request
No effect to operation
CHAPTER 18 I2C INTERFACE
Table 18.3-2 Functional Explanation of the Each Bit in I2C Control Register (IBCR)
Bit name
Functions
bit15
BER:
Bus error interrupt
request flag bit
• It is a flag bit of the interrupt request of the bus error.
• If "1" has been set to the bus error interrupt request enable bit (BEIE), and when "1" is
set, then it output the interrupt request.
• If "1" is set, then the EN bit of the ICCR register will be cleared, the I2C interface will
become hold state, and the data transfer will be discontinued.
• When "0" is set, the interrupt request is cleared.
• If "1" is set, the operation is not affected.
bit14
BEIE:
Bus error interrupt
enable bit
• It is a interrupt enable bits.
• If "1" has been set, and when "1" is set to the interrupt request flag bit of the bus error
(BER), then it generates the interrupt.
bit13
SCC:
Start condition
generation bit
• It is a start condition generation bit.
• If "1" is set, it generates the start condition again at the master transfer, and starts the
address data transfer.
• If it is read, it reads "0".
bit12
MSS:
Master/slave setting
bit
• Master/slave setting is executed.
• If "0" is set, then it generates the stop condition, and will operate in the slave mode
upon the completion of transfer.
• If "1" is set, it operates in the master mode and generates the start condition, and starts
the address data transfer.
• If the arbitration lost has occurred during the master sending, it will be cleared to "0"
and will switch to the slave mode.
bit11
ACK:
Acknowledge
generation
enable bit
• It is the acknowledge generation enable bit when the data is received.
• If "1" is set, the acknowledge will be generated.
• It becomes invalid when the address data is received in the slave mode.
bit10
GCAA:
Acknowledge
generation enable
bit
• This bit is acknowledge generation enable bit on receiving general call address.
If "1" is set, the acknowledge will be generated.
• If "1" is set, the acknowledge will be generated.
bit9
INTE:
Interrupt request
enable bit
• It is a interrupt enable bits.
• When "1" has been set, and if "1" is set to the transfer ending interrupt request flag bit
(INT), then the interruption is generated.
bit8
INT:
Transfer end
interrupt request
flag bit
• It is a interrupt request flag bit.
• When "1" is set, the SCL line is kept at the "L" level.
• If "0" is set, it clears the interrupt request, releases the SCL lines, and transfers the next
bite.
• When the start condition or the stop condition is generated in the master mode, it will be
reset to "0".
409
CHAPTER 18 I2C INTERFACE
■ Attention of Competition of SCC, MSS, and INT Bits
By simultaneously writing to the SCC, MSS, and INT bits, the contention occurs among the next bite
transfer, start condition generation, and stop condition generation. The priority at this time is as follows.
1) The next byte transfer and stop condition generation
If "0" is set both to INT bit and MSS bit, the "0" setting of the MSS bit is given priority and generates
the stop condition.
2) The next byte transfer and start condition generation
If "0" is set both to INT bit and "1" to SCC bit, the "1" setting of the SCC bit is given priority and
generates the start condition.
3) Start condition generation and stop condition generation
Prohibit the simultaneous setting of "1" to SCC bit and "0" to MSS bit.
Notes:
The transmission of the general call address is prohibited in following condition because the
address cannot be received as slave.
Condition that (1) other LSI that becomes master mode besides this LSI exists on the bus, (2) this
LSI transmits the general call address as a master, and (3) the arbitration lost is generated since
the second byte.
If the instruction that generates the start condition is executed on the timing in Figure 18.3-4 and
Figure 18.3-5 ("1" is set to the MSS bit), the interrupt (INT bit = 1) by the arbitration lost detection
(AL bit = 1) is not generated.
Condition 1 that interrupt (INT bit = 1) by AL bit = 1 detection is not generated.
Condition that the instruction fort generating the start condition is executed ("1" is set to the MSS
bit of the IBCR register), when the SDA pin level or the SCL pin level is "L" at the undetected status
for start condition (BB bit = 0).
Figure 18.3-4 Diagram of Timing at which an Interrupt upon Detection of "AL bit=1" does not Occur
SCL pin or SDA pin at "L" level
SCL pin
"L"
SDA pin
"L"
I2C operation enable status (EN bit = 1)
"1"
Master mode setting (MSS bit = 1)
Arbitration lost detection (AL bit = 1)
Bus busy (BB bit)
Interrupt (INT bit)
410
"0"
"0"
CHAPTER 18 I2C INTERFACE
• Condition 2 in which an interrupt (INT bit=1) upon detection of "AL bit=1" does not occur
When an instruction which generates a start condition by enabling I2C operation (EN bit=1) is
executed (set "1" to MSS bit in IBCR register) with the I2C bus occupied by another master.
This is because, as shown in Figure 18.3-5 , when the other master on the I2C bus starts
communication with I2C disabled (EN bit=0), the I2C bus enters the occupied state with no start
condition detected (BB bit =0).
Figure 18.3-5 Diagram of Timing at which an Interrupt upon Detection of "AL bit=1" does not Occur
Start Condition
The INT bit interrupt does not
occur in the ninth clock cycle.
Stop Condition
SCL pin
SDA pin
SLAVE ADDRESS
ACK
DAT
ACK
EN bit
MSS bit
AL bit
BB bit
"0"
INT bit
"0"
If a symptom as described above can occur, follow the procedure below for software processing.
1. Execute the instruction that generates a start condition (set the MSS bit to "1").
2. Use, for example, the timer function to wait for the time for three-bit data transmission at the I2C
transfer frequency set in the ICCR register.*
Example: Time for three-bit data transmission at an I2C transfer frequency
of 100 kHz = {1/(100x103)}x30=30 μs
*: When the arbitration lost is detected, the MSS bit is set to "1" and then the AL bit is set to "1"
without fail after the time for three-bit data transmission at the I2C transfer frequency.
3. Check the AL and BB bits in the IBSR register and, if the AL and BB bits are "1" and "0",
respectively, set the EN bit in the ICCR register to "0" to initialize I2C. When the AL and BB bits
are not so, perform normal processing.
411
CHAPTER 18 I2C INTERFACE
A sample flow is given below.
Master mode setting
Set MSS bit in bus control register (IBCR) to "1".
Wait for the time for three-bit data transmission at the I2C
transfer frequency set in the clock control register (ICCR)*
NO
BB bit=0 and AL bit=1
YES
Setting EN bit to "0" and initializing of I2C
To normal process
*: When the arbitration lost is detected, the MSS bit is set to "1" and then the AL bit is set to "1"
without fail after the time for three-bit data transmission at the I2C transfer frequency.
Example of occurrence for an interrupt (INT bit=1) upon detection of "AL bit=1"
When an instruction which generates a start condition is executed (setting the MSS bit to "1") with
"bus busy" detected (BB bit=1) and arbitration is lost, the INT bit interrupt occurs upon detection of
"AL bit=1".
Figure 18.3-6 Diagram of Timing at which an Interrupt upon Detection of "AL bit=1" Occurs
Start Condition
Interrupt in the ninth clock cycle
SCL pin
SDA pin
SLAVE ADDRESS
ACK
DAT
EN bit
MSS bit
AL bit
Clearing the AL bit by software
BB bit
INT bit
412
Releasing the SCL by clearing
the INT bit by software
CHAPTER 18 I2C INTERFACE
18.3.3
I2C Clock Control Register (ICCR)
I2C clock control register (ICCR) supports the following functions.
• I2C interface operation enable
• Serial Clock frequency setting
■ I2C Clock Control Register (ICCR)
Figure 18.3-7 I2C Clock Control Register (ICCR)
Address Bit
7
6
00006CH
5
EN
4
3
2
1
0
CS4 CS3 CS2 CS1 CS0
Initial value
--0XXXXXB
R/W R/W R/W R/W R/W R/W
EN
I2C interface operating enable bit
0
Operation prohibition
1
Operation acceptance
R/W : Read/write
X : Indefinite
: Initial value
Table 18.3-3 Functional Explanation of Each Bit in the I2C Clock Control Register (ICCR)
Bit name
USART functions
bit7,
bit6
-:
Undefined bits
• The value becomes undefined when read operation is performed.
• The set value does not influence the operation.
bit5
EN:
I2C interface
operating enable
bit
• It is I2C interface operation permission bit.
• If "0" has been set, then each bit in the I2C bus status register (IBSR) and I2C bus control
register (IBCR) (except for BER, BETE bits) is cleared.
• If "1" is set to the BER bit, then it is cleared to "0".
bit4
to
bit0
CS4 to CS0:
Serial clock
frequency setting
bits
• It is the bit which sets the serial clock frequency.
• The frequency fsck in the shift clock is set as shown in the next formula.
φ
φsck =
m×n+4
φ :machine clock
• See Table 18.3-5 for the setting values of the serial clock frequency.
413
CHAPTER 18 I2C INTERFACE
Table 18.3-4 Serial Clock Frequency Setting (CS4, CS3)
m
CS4
CS3
5
0
0
6
0
1
7
1
0
8
1
1
Table 18.3-5 Serial Clock Frequency Setting (CS2 to CS0)
n
CS2
CS1
CS0
4
0
0
0
8
0
0
1
16
0
1
0
32
0
1
1
64
1
0
0
128
1
0
1
256
1
1
0
512
1
1
1
For example, when φ=25 MHz, and if M=5 and n=32 are selected, the serial clock frequency will become
152.43 kHz.
Notes:
• The cycle + 4 is minimum overhead for checking that the output level of SCL pin has changed.
When the delay of SCL pin rising is large or when the slave device pulls out the clock, the value
will become larger than this.
The output of I2C peripheral port pins changes as follow by setting I2C operation enable bit (EN
bit).
• When EN bit=1 (operation enabled), I2C output signal is output to SDA/P74, SCL/P75 pin in spite
of the setting value of DDR7:bit12, DDR7:bit13.
• When EN bit=0 (operation disabled), for DDR7: bit12=1 and DDR7: bit13=1 (output setting), the
setting value of P74 an P75 in the PDR7 register is output to SDA/P74 and SCL/P75 pins.
• During the operation of I2C, if read modify write (RMW) instructions is executed to the port data
register (PDR7), which is the same type register as I2C, then the pin levels are read the bit12 and
bit13 of the PDR7 in READ cycle. Therefore, note that the values in the bit12 and bit13 of PDR7
may be changed by P75/SCL and P74/SDA pin levels.
414
CHAPTER 18 I2C INTERFACE
Figure 18.3-8 Change Timing of Port of I2C Using Combinedly
I2C operating enable/disable
I2C operating enable: EN bit = 1
SCL/P75
I2C operating disable EN bit=0
DDR9: when bit 9=0: Hi-Z for input set
DDR9: when bit 9=1: Output changed value of PDR
SDA/P74
DDR9: when bit 8=0: Hi-Z for input set
DDR9: when bit 8=1: Output changed value of PDR
Read modify write (RMW) instruction execution
timing for PDR register
PDR register value
Previous data
Read modify write (RMW) instruction execution
changing by the pin level at read modify write (RMW) instruction execution
415
CHAPTER 18 I2C INTERFACE
18.3.4
I2C Address Register (IADR)
I2C address register (IADR) indicates the slave address.
■ I2C Address Register (IADR)
Figure 18.3-9 I2C Address Register (IADR)
Address Bit
15
00006DH
14
13
12
11
10
9
8
Initial value
A6
A5
A4
A3
A2
A1
A0
-XXXXXXXB
R/W R/W R/W R/W R/W R/W R/W
R/W: Readable/Writable
X : Indefinite
: Undefined bit
It is a register which specifies the slave address. In the slave, the address data is compared to the IADR
register after reception of the address, and if they match, then it will send the acknowledge to the master.
416
CHAPTER 18 I2C INTERFACE
18.3.5
I2C Data Register (IDAR)
I2C data register (IDAR) is used for the serial transfer.
■ I2C Data Register (IDAR)
Figure 18.3-10 I2C Data Register (IDAR)
Address Bit
7
6
5
4
3
2
1
0
Initial value
00006EH
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXB
R/W R/W R/W R/W R/W
R/W R/W R/W
R/W : Readable/Writable
X : Indefinite
It is the data register used for the serial transfer, and transferred from MSB. During the data receiving
(TRX= 0), the data output value become "1".
The writing side of the I2C data register is double-buffered, and if the bus is in use (BB= 1), the write data
will be loaded into the serial transfer register when each byte is transferred. Because it reads the serial
transfer register directly during reading, the receiving data become valid only when the INT bit has been
set.
417
CHAPTER 18 I2C INTERFACE
18.4
I2C Interface Operation
I2C bus performs communication as bi-directional bus line using one serial data line
(SDA) and one serial clock line (SCL). SDA and SCL can be used as the open drain
input-output pins (SDA and SCL) in I2C interface. As a result, the wired logic is enabled.
And the input voltage can be up to 5 V (Typ).
■ Start Condition
If the MSS bit is set to "1" with the bus released (BB= 0, MSS= 1), then the I2C interface starts operation in
the master mode, and concurrently generates the start condition. In the master mode, the start condition can
be generated again by setting the SCC bit to "1" even when the bus line is occupied (BB= 1).
Following 2 conditions generate the start condition.
• When you set the MSS bit in "1" with the bus not used (MSS= 0, BB= 0, INT= 0, AL= 0)
• For the bus master, by setting the SCC bit to "1" in the state of interrupt (MSS= 1, BB= 1, INT =1,
AL= 0)
During the bus is in use by other system (idling state), if the MSS bit is set to "1", the AL bit will be set to
"1". If the MSS bit and SCC bit are both set to "1" using the method other than the above-mentioned
conditions, then the setting value will be ignored.
■ Stop Condition
For the master mode (MSS= 1), if the MSS bit is set to "0", then the stop condition will be generated and
transit to the slave mode.
The condition to generate the stop condition is as follows.
If the state is the interrupt for the bus master (MSS= 1, INT= 1, INT = 1, AL= 0), then MSS bit will be set
to "0".
If the MSS bit is set to "0" in the cases other than these above, then the setting value will be ignored.
■ Addressing
In the master mode, BB= 1 and TRX= 1 will be set after the start condition generation, and it outputs the
IDAR register contents from the MSB. If it receives the acknowledge from the slave After sending the
address data, it reverse the bit0 of the sending data (after sending: IDAR, bit0) and stores them into the
TRX bit.
In the slave mode, BB= 1 and TRX= 0 will be set or cleared after the start condition generation, and the
sending data from the master can be received into the IDAR register. After receiving the address data,
IDAR register will be compared to IADR register. If the register values match, then AAS will be set to "1"
and send the acknowledge to the master. Then, bit0 of the receiving data (After receiving: IDAR, bit0) will
be stored into the TRX bit.
418
CHAPTER 18 I2C INTERFACE
■ Arbitration
If other master are sending the data simultaneously in the master sending mode, the arbitration will occur.
If own data is "1" and the data on the SDA line is "L level", then it regard itself losing arbitration and set
the AL bit to "1". And if it tries to generate the start condition during the bus state is in use, then the AL bit
is also set to "1".
If the AL bit is set to "1", then MSS and TRX becomes MSS= 0 and TRX= 0, and it will operate in the
slave receiving mode.
■ Acknowledge
The receiver send the acknowledge to the sender. During the data receiving, ACK bit sets the acknowledge
setting. During the data sending, the acknowledge from the receiver is stored in the LRB bit.
In the slave sending mode, if the sender does not receive the acknowledge from the master receiver, then
TRX becomes TRX= 0 and the mode becomes the slave receive mode. Then, the master will be able to
generate the stop condition when the slave releases the SCL line.
■ Bus Error
If the following conditions exist, it will be considered as bus error, and the I2C interface will be in the
stopped state.
• By detecting the basic defining violation on the I2C bus during the data sending (Including ACK bit)
• When you detect the stop condition detection for the master
• By detecting the basic defining violation on the I2C bus during the bus is in the idling state
■ Execution of the Start Condition Generation Instruction under at SDA="L" and
SCL="L"
If the start condition generation instruction is executed (write "1" to MSS bit) under SDA="L" and
SCL="L", then the status become BB=0 and AL=1. In this case, the transfer ending interrupt request flag
(INT bit) is not set because the transfer has not been completed. Therefore, detection of this state should be
performed by monitoring the BB bit and AL bit by program.
419
CHAPTER 18 I2C INTERFACE
Figure 18.4-1 Change Timings of Each Flag when Executing the Start Condition Generation
Instruction under SDA="L" and SCL="L"
SCL
"L"
"L"
SDA
Start condition
Arbitration
Interruption
Bus busy
420
Set "1" to MSS bit
Set AL bit to IBSR
INT bit of IBCR
"L"
BB bit of IBSR
"L"
CHAPTER 18 I2C INTERFACE
18.4.1
I2C Interface Transfer Flow
Figure 18.4-2 describes the one byte transfer flow from the master to the slave, and
Figure 18.4-3 describes the one byte transfer flow from the slave to the master.
■ I2C Interface Transfer Flow
Figure 18.4-2 One Byte Transfer Flow From The Master to the Slave
Master
Slave
Start
DAR: Write
MSS: "1" write
Start condition
BB set, TRX set
BB set, TRX set
Address data transfer
AAS set
Acknowledge
LBR reset
INT set,TRX set
DAR: Write
INT: "0" write
Interrupt
INT set,TRX set
ACK: "1" write
INT: "0" write
Data transfer
Acknowledge
LBR rest
INT set
Interrupt
MSS: "0" write
INT reset
BB reset,TRX reset
Stio condition
INT set
DAR: Read
INT: "0" write
BB reset,TRX reset
AAS reset
End
421
CHAPTER 18 I2C INTERFACE
Figure 18.4-3 One Byte Transfer Flow from Slave to Master
Master
Slave
Start
DAR: Write
MSS: "1" write
Start condition
BB set,TRX set
BB set,TRX set
Address data transfer
AAS reset
Acknowledge
LBR reset
INT set,TRX reset
Interrupt
INT: "0" write
INT set,TRX set
DAR: Write
INT: "0" write
Data transfer
Negative acknowledge
INT set
DAR: Read
LBR set,TRX set
INT set
Interrupt
INT: "0" write
MSS: "0" write
INT reset
BB reset,TRX reset
Stio condition
End
422
BB reset,TRX reset
AAS reset
CHAPTER 18 I2C INTERFACE
18.4.2
Mode Flow of I2C Interface
Figure 18.4-4 shows the I2C mode flow.
■ Mode Flow of I2C Interface
Figure 18.4-4 I2C Mode Flow
Slave reception mode
STC
NO
YES
TRX,AAS,LRB:reset
FBT:set
STC&BB=1
YES
RSC:set
NO
BB:set
8-bit reception
RSC,FBT:reset
Address comparison
Match
AAS: set
INT:set
Confirmation
corresponding output
SCL line
Hold to "L"
NO
TRX=1
Slave reception mode
YES
SPC
Slave transfer mode
NO
YES
AAS,LRB,BB,RSC:
reset
INT:0write
FBT:reset
SCL line open
Transfer/reception
YES
Confirmation
corresponding is
existence.
NO
TRX:reset
423
CHAPTER 18 I2C INTERFACE
Operation Flow of I2C Interface
18.4.3
Figure 18.4-5 shows the I2C master sending-receiving program flow (interruption use)
and Figure 18.4-6 shows the I2C slave program flow (interruption use).
■ Operation Flow of I2C Interface
Figure 18.4-5 I2C Master Sending-Receiving Program Flow Chart (interruption use)
Main routine
Interrupt routine
Start
Start
Set slave address
Is bus error
generated?
I2C operating enabled
YES
NO
Is AL
generated?
Set of transfering byte number
with data writing at a time
Slave address set transfer
(data direction bit=0)
Slave address set
reception
(data direction bit=1)
YES
BBbit=1?
2
YES
BBbit=1?
Data direction bit
TRXbit=1?
Constant time WAIT
Constant time WAIT
NO
3
RETI
To interrupt routine
of slave program
1
NO
BBbit=0 and
AL bit=1?
Rest transfer
byte number=0?
NO
YES
Rest reception
byte number=?
YES
Decrement of transfer byte number
I2C operating disabled
YES
1
Rest reception
byte number=1?
YES
NO
Acknowledge generation enabled
Acknowledge generation enabled
Set of transfer data
End interrupt factor clear
LOOP
RETI
Is
reception of
first byte?
YES
NO
Decrement of reception byte number
Storing reception data to RAM
End interrupt factor clear
RETI
424
1
NO
YES
NO
I2C operating disabled
I2C initialized setting
3
Acknowledge generating enabled
NO
NO
YES
3
YES
Slave address transfer
Start condition generating
LOOP
RETI
I2C operating enabled
Is master?
Is ACK
returned?
Slave address transfer
Start condition generating
NO
Bus error interrupt
factor clear
YES
NO
BBbit=0 and
AL bit=1?
STOP condition generation
YES
NO
Master reception
Set of transfering byte number
with writing at a time
YES
2
NO
Is master
reception operation?
Master transfer
1
CHAPTER 18 I2C INTERFACE
Figure 18.4-6 I2C Slave Program Flow Chart (interruption use)
Main routine
Interrupt routine
Start
Start
Set slave address
I2C operating enabled
Set to slave mode
Is bus error
generated?
YES
2
NO
1
2
Transfer end interrupt
factor clear
Bus error interrupt
factor clear
RETI
I2C operating enabled
I2C initialized setting
NO
Is addressing?
1
RETI
LOOP
YES
Data
direction bit
TRX bit=1?
Is
reception dat
address?
NO
YES
Is ACK
returned?
YES
Transfer data set
Transfer end interrupt
factor clear
NO
1
YES
NO
Storing reception
data to RAM
Transfer end interrupt
factor clear
RETI
RETI
425
CHAPTER 18 I2C INTERFACE
426
CHAPTER 19
8/10-BIT A/D CONVERTER
This chapter describes the functions and the operations
of the MB90800 series 8/10 bit A/D converter.
19.1 Overview of 8/10-bit A/D Converter
19.2 Configuration of 8/10-bit A/D Converter
19.3 Pins of 8/10-bit A/D Converter
19.4 Register of 8/10-bit A/D Converter
19.5 Interrupt of 8/10-bit A/D Converter
19.6 Explanation of Operation of 8/10-bit A/D Converter
427
CHAPTER 19 8/10-BIT A/D CONVERTER
19.1
Overview of 8/10-bit A/D Converter
The 8/10 bit A/D converter supports the function that converts the analog input voltage
into the value of 10 bit or 8 bit using sequential compare conversion method.
■ Function of 8/10-bit A/D Converter
Function of 8/10-bit A/D Converter
• The conversion time is 3.1 ms minimum (including the sampling time).
• Sampling time is 2.0 ms minimum.
• The conversion method used is the RC sequential compare conversion method with sample hold circuit.
• The resolution of ten bits or eight bits can be set.
• The input signal is setable from 12 channels analog input pins using the program.
• EI2OS can be activated by outputting the interrupt request when the A/D conversion completes.
• If the A/D conversion is performed under the condition of the interrupt enable, the converting data will
be protected.
• The activation factor of the conversion can be set from software and the 16-bit reload timer 1 output
(rising edge).
Conversion mode has four kinds of type as shown in Table 19.1-1 .
Table 19.1-1 Conversion Modes of 8/10-bit A/D Converter
Conversion mode
Single conversion operation
Scanning conversion operation
Single-shot conversion mode 1
Single-shot conversion mode 2
End after set channel (one channel) is
converted once
Ends after converting the continuous multiple
channels (can be set up to 12 channels) one time
Continuous conversion mode
Repeatedly converts a channel which
had been set (one channel)
Repeatedly converts the continuous multiple
channels (can be set up to 12 channels)
Pause-conversion mode
Suspend after converting a channel
which had been set (one channel),
and wait for the next activation
Suspend after converting the continuous
multiple channels (can be set up to 12 channels),
and wait for the next activation
■ 8/10-bit A/D Converter Interrupt and EI2OS
Table 19.1-2 8/10-bit A/D Converter Interrupt and EI2OS
Interrupt
number
Interrupt control registers
EI2OS
Register name
Address
Low
High
Bank
ICR13
0000BDH
FFFF68H
FFFF69H
FFFF6AH
#37(25H)
: Possible to use
428
Vector table address
CHAPTER 19 8/10-BIT A/D CONVERTER
19.2
Configuration of 8/10-bit A/D Converter
The 8/10-bit A/D converter consists of following blocks.
• A/D Control status register 0/1(ADCS0/ADCS1)
• A/D data register (ADCR0/ADCR1)
• Clock selector (input clock selector for activation of A/D conversion)
• Decoder
• Analog channel selector
• Sample hold circuit
• D/A converter
• Comparator
• Control circuit
■ Block Diagram of 8/10-bit A/D Converter
Figure 19.2-1 Block Diagram of 8/10-bit A/D Converter
Interrupt request signal #37 (25H)*
A/D conversion
Rechannel register 0/1 BUSY INT INTE PAUS STS1 STS0 STRT served
MD1 MD0 ANS3ANS2 ANS1ANS0 ANE3ANE2 ANE1 ANE0
(ADCS0/ADCS1)
8
2
Clock selector
Decoder
Internal data bus
16-bit reload timer 1 output
φ
Comparator
Sample hold
circuit
P73/AN11
to
P60/AN0
A/D data register
(ADCR0/ADCR1)
Analog
channel
selector
S10 ST1 ST0 CT1 CT0
AVR
AVcc
AVss
Control circuit
2
D/A converter
2
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
φ : Machine cycle
* : Interrupt signal
429
CHAPTER 19 8/10-BIT A/D CONVERTER
● A/D control status register 0/1(ADCS0/ADCS1)
A/D control status register 0 (ADCS0) has functions that sets the A/D conversion mode and the start/end
channels of the A/D conversion.
A/D control status register 1 (ADCS1) has functions that set the A/D conversion activation factor and
enable/disable of the interrupt request, and confirms the interrupt request state and the hold/operation of A/D
conversion.
● A/D data register (ADCR0/ADCR1)
The register which stores the A/D conversion result, also supports the functions that sets the resolution,
sampling time or compare time of the of the A/D conversion.
● Clock selector
It is the selector which sets the A/D conversion activation clock. In activation clock. 16-bit reload timer 1
output can set.
● Decoder
This circuit sets the analog input pins to be used, based on the setting values of the A/D conversion end
channel setting bit (ANE0 to ANE3) and A/D conversion start channel setting bit (ANS0 to ANS3) of A/D
control status register (ADCS0).
● Analog channel selector
This circuit sets the pins to be used, out of the 12 channel analog input pins.
● Sample hold circuit
This circuit holds the input voltages from the pins selected by the analog channel selector. The input
voltage after the A/D conversion was activated, A/D conversion is not affected by the input voltage variety
during A/D conversion process (compare process).
● D/A converter
It generates the reference voltage to be compared with the input voltage kept.
● Comparator
Compare the input voltage sample-held with the output voltage of the D/A converter to determine higher or
lower.
● Control circuit
The signal from the comparator (higher or lower) determines the A/D conversion value. When the A/D
conversion is finished, it stores the result of conversion to the A/D data register (ADCR0/ADCR1) and
outputs the interrupt request.
430
CHAPTER 19 8/10-BIT A/D CONVERTER
19.3
Pins of 8/10-bit A/D Converter
Pins of 8/10-bit A/D converter and block diagram of pins are shown.
■ Pins of 8/10-bit A/D Converter
The A/D converter pins are shared with input and output ports.
Table 19.3-1 Pins of 8/10-bit A/D Converter
Functions
Pin name
Channel 0
P60/AN0
Channel 1
P61/AN1
Channel 2
P62/AN2
Channel 3
P63/AN3
Channel 4
P64/AN4
Channel 5
P65/AN5/
INT0
Channel 6
P66/AN6/
INT1
Channel 7
P67/AN7/
INT2
Channel 8
P70/AN8/
INT3
Channel 9
P71/AN9/
SC1
Channel 10
P72/AN10/
SO1
Channel 11
P73/AN11/
SI2
Pull-up
setting
Stand-by
control
To the use of the
terminal setting
Pin function
I/O type
Port 6
Input/Output/
Analog input
CMOS output/
CMOS hysteresis
input
or
Analog input
None
None
Input setting of port 6
(DDR6:bit0 to bit7= 0)
Set to analog input
(ADER0: bit0 to bit7= 1)
Port 7
Input/Output/
Analog input
CMOS output/
CMOS hysteresis
input
or
Analog input
None
None
Input setting of port 7
(DDR7:bit0 to bit3= 0)
Set to analog input
(ADER1: bit0 to bit3= 1)
431
CHAPTER 19 8/10-BIT A/D CONVERTER
■ Block Diagram of Pins of 8/10-bit A/D Converter
Figure 19.3-1 Block Diagram of P60/AN0 to P73/AN11 Pins
A/D converter
analog input signal
Internal data bus
ADER
PDR read
PDR
I/O judge
circuit
PDR write
DDR
Input buffer
Output buffer
Port pin
Standby control (LPMCR:SPL=1)
Standby control : Stop mode and LPMCR:SPL="1"
Notes:
• For pins used as input ports, set "0" to corresponding bit (bit7 to bit0) of the port direction register
(DDR6, DDR7), and set "0" to corresponding bit (bit11 to bit0) of the analog input enable register
(ADER0, ADER1).
• For pins used as analog input pin, set "1" to corresponding bit (bit11 to bit0) of the analog input
enable register (ADER0, ADER1). The read value of the port data registers (PDR6, PDR7) are
"00H" respectively.
432
CHAPTER 19 8/10-BIT A/D CONVERTER
19.4
Register of 8/10-bit A/D Converter
Register list of 8/10-bit A/D converter is shown.
■ Register List of 8/10-bit A/D Converter
Figure 19.4-1 Register List of 8/10-bit A/D Converter
bit15
bit8
bit7
bit0
A/D control status register 1(ADCS1)
A/D control status register 0(ADCS0)
A/D data register (ADCR1)
A/D data register (ADCR0)
A/D conversion channel setting
register (ADMR)
433
CHAPTER 19 8/10-BIT A/D CONVERTER
19.4.1
A/D Control Status Register 1(ADCS1)
A/D control status register 1 (ADCS1) has functions that set the A/D conversion
activation factor and enable/disable of the interrupt request, and confirms the interrupt
request state and the hold/operation of A/D conversion.
■ A/D Control Status Register 1(ADCS1)
Figure 19.4-2 A/D Control Status Register 1(ADCS1)
Address Bit
000035H
15
14
13
12
11
10
9
8
BUSY INT INTE PAUS STS1 STS0 STRT
R/W R/W R/W R/W R/W R/W
Reserved
W
Initial value
00000000B
R/W
Reserved bit
Reserved
Be sure to set "0".
STRT
A/D conversion activating bit
(only available at software activating (ADC2: EXT=0)
0
Not activating A/D conversion function
1
Activating A/D conversion function
STS1 STS0
0
0
1
0
1
0
1
1
PAUS
Temporary stop flag bit
(only available at using of EI2OS)
During A/D conversion operation
During temporary stop of A/D conversion operation
Interrupt request enable bit
0
Prohibition of interrupt request output
1
Acceptance of interrupt request output
Interrupt request flag bit
Read
Write
0
A/D conversion has not completed.
Clear interrupt request.
1
A/D conversion has completed.
No effect to operation
BUSY
434
Activation of 16-bit reload timer
or software
1
INT
: Readable/Writable
: Write only
: Initial value
Activation of software
0
INTE
R/W
W
A/D activating factor setting bits
Converting bit
Read
Write
0
During A/D conversion stop
A/D conversion forcibly stop
1
During A/D conversion operating No effect to operation
CHAPTER 19 8/10-BIT A/D CONVERTER
Table 19.4-1 Function Description of Each Bit of A/D Control Status Register 1 (ADCS1)
Bit name
Functions
bit15
BUSY:
Converting bit
• This bit is A/D converter operating status bit.
• "0" setting indicates that it is suspending the A/D conversion.
• "1" setting indicates that it is operating the A/D conversion.
• If "0" is set, then it terminates the A/D conversion operation.
• If "1" is set, the operation is not affected.
Note:
Do not set the termination and activation (BUSY=0, STRT=1) of the A/D conversion
operation at the same time.
bit14
INT:
Interrupt request
flag bit
• It is a flag bit of the interrupt request.
• "1" will be set when A/D conversion result is stored into the A/D data register (ADCR0/
ADCR1).
• It outputs the interrupt request by setting "1", if "1" has been set to the interrupt request
permit bit (INTE).
• When "0" is set, the interrupt request is cleared.
• If "1" is set, operation is not affected.
• It will be clear to "0" if EI2OS is used.
Note:
To clear the interrupt request, stop the A/D conversion.
bit13
INTE:
Interrupt request
enable bit
• It is a bit by which the interrupt request is permitted.
• It outputs the interrupt request by setting "1", if "1" has been set to the interrupt request flag
bit (INT).
• Please set "1" when you use EI2OS.
bit12
PAUS:
Temporary stop
flag bit
• "1" will be set when the A/D conversion operation is suspended.
• If EI2OS is used in the continuous conversion mode, and the transfer of the previous data to
the memory is not finished, "1" is set although the A/D conversion had been completed,
and A/D conversion operation is suspended. In this case, the converting data is not stored
to A/D data register (ADCR0/ADCR1).
• When the transfer of the previous data to the memory completes, it is cleared to "0", and the
A/D conversion operation is restarted.
Note:
It is valid when using EI2OS.
bit11,
bit10
STS1, STS0:
A/D activating
factor setting bits
• This bit sets the activation factor of the A/D conversion.
• when the activation factors are multiplexed, It is activated by the first activation factor.
Note:
Because the activation factor is changed immediately at the setting, be sure to switch them
in the state without the objective activation factor if it is set during the A/D conversion
operation.
bit9
STRT:
A/D conversion
activating bit
• This bit activates the A/D conversion operation.
• The analog to digital conversion starts when "1" is set.
• During the suspend conversion mode, the restart operation by STRT bit is not performed.
Note:
Do not perform the termination and activation (BUSY=0, STRT=1) of the A/D conversion
operation at the same time.
bit8
Reserved:
Reserved bit
Be sure to set this bit to "0".
435
CHAPTER 19 8/10-BIT A/D CONVERTER
19.4.2
A/D Control Status Register 0(ADCS0)
A/D control status register 0 (ADCS0) has functions that sets the A/D conversion mode
and the start/end channels of the A/D conversion.
■ A/D Control Status Register 0(ADCS0)
Figure 19.4-3 A/D Control Status Register 0(ADCS0)
Address Bit
000034H
7
6
5
4
MD1 MD0
3
2
1
0
Initial value
00------B
R/W R/W
MD1 MD0
R/W
436
A/D conversion mode setting bits
0
0
Single-shot conversion mode 1 (Enable restart in operating)
0
1
Single-shot conversion mode 2 (disable restart in operating)
1
0
Continuous conversion mode (disable restart in operating)
1
1
Stop conversion mode (disable restart in operating)
: Readable/Writable
: Undefined bit
: Initial value
CHAPTER 19 8/10-BIT A/D CONVERTER
Table 19.4-2 Function Description of Each Bit of A/D Control Status Register 0(ADCS0)
Bit name
bit7,
bit6
MD1, MD0:
A/D
conversion
mode setting
bits
Functions
• This bit sets the mode of the A/D conversion.
• The single conversion mode 1, single conversion mode 2, continuous conversion mode, and
suspend conversion mode can be set.
• Single conversion mode 1: It ends after the A/D conversion from the channel set in the A/D
conversion start channel setting bit (ANS3 to ANS0) to the
channels set in the A/D conversion end channel setting bit (ANE3
to ANE0). It is possible to reactivate while operating.
• Single conversion mode 2: It ends after the A/D conversion from the channel set in the A/D
conversion start channel setting bit (ANS3 to ANS0) to the
channels set in the A/D conversion end channel setting bit (ANE3
to ANE0). It is not possible to reactivate while operating.
• Continuous conversion mode: It repeats the A/D conversion in the range from the channel set
in the A/D conversion start channel setting bit (ANS3 to
ANS0) to the channels set in the A/D conversion end channel
setting bit (ANE3 to ANE0) until terminated by the conversion
busy bit (BUSY). It is not possible to reactivate while
operating.
• Stop conversion mode: While A/D conversion from the channel set in A/D conversion start
channel setting bit (ANS3 to ANS0) to the channel set in A/D
conversion end channel setting bit (ANE3 to ANE0) is temporary
stopped every one channel, it repeats until forcibly stop in converting
bit (BUSY). It is not possible to reactivate while operating. The
restart during the suspend is differently triggered depending on the
activation factor set by the A/D activation factor setting bit (STS1,
STS0).
Note:
Restart disable for each of the single mode, continuous mode, and suspend conversion mode
are applied to detection of the 16-bit free run timer 0 and 16-bit reload timer 1, and activation
of all the software.
437
CHAPTER 19 8/10-BIT A/D CONVERTER
19.4.3
A/D Data Register (ADCR0/ADCR1)
A/D data register (ADCR0/ADCR1) is the register that stores the A/D conversion result. It
also has functions that set the resolution of A/D conversion, the sampling time and
compare time in A/D conversion process
■ A/D Data Register (ADCR0/ADCR1)
Figure 19.4-4 A/D Data Register (ADCR0/ADCR1)
Address
000037H
000036H
Bit
15
14
13
12
11
10
S10 ST1ST0 CT1CT0
W
W W
W
W
9
8
7
6
5
4
3
2
1
0
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
R
R
R
R
R
R
R
D9 to D0
R
R
Initial value
00101-XXB (upper)
XXXXXXXXB (lower)
R
A/D data bits
Store the conversion data
CT1 CT0
0
44 machine cycle (at [email protected])
0
1
66 machine cycle (at [email protected])
1
0
88 machine cycle (at [email protected])
1
1
176 machine cycle (at [email protected])
ST1 ST0
φ
438
: Read only
: Write only
: Undefined
: Unused bit
: Initial value
: Machine clock frequency
Sampling time setting bits
0
0
20 machine cycle (at [email protected])
0
1
32 machine cycle (at [email protected])
1
0
48 machine cycle (at [email protected])
1
1
128 machine cycle (at [email protected])
S10
R
W
X
Compare time setting bits
0
A/D conversion resolution setting bit
0
10-bit resolution mode (D9 to D0)
1
8-bit resolution mode (D7 to D0)
CHAPTER 19 8/10-BIT A/D CONVERTER
Table 19.4-3 Functional Explanation of Each Bit in the A/D Data Register (ADCR0/ADCR1)
Bit name
Functions
bit15
S10:
A/D
conversion
resolution
setting bit
• This bit sets the resolution of the A/D conversion.
• When "0" is set, ten bit resolution is set.
• When "1" is set, eight bit resolution is set.
Notes:
• The A/D data bit used are different depends on the resolution.
• In 10-bit resolution mode, the D9 to D0 bits are used.
• In 8-bit resolution mode, the D7 to D0 bits are used.
bit14,
bit13
ST1, ST0:
Sampling time
setting bits
• This bit sets the sampling time of the A/D conversion.
• When the A/D conversion is activated, it captures analog data input for a duration set in the
sampling time setting bit (ST1, ST0).
Notes:
• If "00B" is going to be set, make sure the machine clock frequency should be less than 8
MHz.
• If "00B" is set with a machine clock frequency more than 16MHz, the analogue conversion
value might not be obtained.
bit12,
bit11
CT1, CT0:
Compare time
setting bits
• This bit sets the compare time during A/D conversion.
• After capturing analog input (sampling time passed) and the time set by compare time
setting bit (CT1, CT0), A/D conversion result is decided then storing to A/D data bit (D9 to
D0) and A/D data bit (D7 to D0) in 10-bit and 8-bit resolution mode respectively.
Notes:
• If "00B" is going to be set, make sure the machine clock frequency should be less than 8
MHz.
• If "00B" is set with a machine clock frequency more than 16MHz, the analogue conversion
value might not be obtained.
bit10
-:
Undefined
bit
• The value becomes undefined when read operation is performed.
• The set value does not influence the operation.
bit9
to
bit0
D9 to D0:
A/D data bits
• This bit stores the A/D conversion result. It is rewritten at the end of each A/D conversion.
• The final conversion value is stored usually.
• The initial value is irregular.
Notes:
• It supports the A/D conversion data protect function (see "19.6 Explanation of Operation of
8/10-bit A/D Converter" for more details).
• Do not write data to the A/D data bit during A/D conversion.
Notes:
• If the A/D conversion resolution setting bit (S10) is going to be updated, be sure to stop the A/D
conversion operation before A/D conversion start operation. If it is updated after A/D conversion
operation was started, the contents of A/D data register (ADCR/ADCR1) will be unstable.
• If 10-bit resolution mode has been set, and when the A/D data register (ADCR0/ADCR1) is going
to be read, be sure to use the word transfer instruction (such as MOVM A, 002EH)
439
CHAPTER 19 8/10-BIT A/D CONVERTER
19.4.4
Analog to Digital Conversion Channel Set Register (ADMR)
Analog to digital conversion channel set register (ADMR) has the function which set the
A/D conversion channel.
■ Analog to Digital Conversion Channel Set Register (ADMR)
Figure 19.4-5 Analog to Digital Conversion Channel Set Register (ADMR)
Address Bit
000039H
15
14
13
12
11
10
9
8
Initial value
ANS3 ANS2 ANS1 ANS0 ANE3 ANE2 ANE1 ANE0
0000000B
R/W R/W R/W R/W R/W R/W R/W R/W
ANE3 ANE2 ANE1 ANE0 A/D conversion complete channel setting bits
AN0
0
0
0
0
AN1
0
0
0
1
AN2
0
0
1
0
AN3
0
0
1
1
AN4
0
1
0
0
AN5
0
1
0
1
AN6
0
1
1
0
AN7
0
1
1
1
AN8
1
0
0
0
AN9
1
0
0
1
AN10
1
0
1
0
AN11
1
0
1
1
1
1
0
0
1
1
0
1
Setting disabled
1
1
1
0
1
1
1
1
A/D conversion start channel setting bits
ANS3 ANS2 ANS1 ANS0 During
stop
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
R/W : Readable/Writable
: Initial value
440
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
Read in
conversion
Read in temporary
stop with stop
conversion mode
Channel
number in
converting
Channel
number
converted
immediately
before
Setting disabled
CHAPTER 19 8/10-BIT A/D CONVERTER
Table 19.4-4 Analog to Digital Conversion Channel Set Register (ADMR)
Bit name
Functions
bit7
to
bit4
ANS3, ANS2,
ANS1, ANS0:
A/D conversion start
channel setting bits
• This bit sets the start channel of the A/D conversion and indicates the channel
numbers during conversion operation.
• If the A/D conversion is activated, the A/D conversion starts from the channel which
sets in the A/D conversion start channel setting bit (ANS3 to ANS0).
• The converting channel number is read during A/D conversion. The channel number
most recently converted is read during suspend in the stop conversion mode.
bit3
to
bit0
ANE3, ANE2,
ANE1, ANE0:
A/D conversion
complete channel
setting bits
• This bit sets the end channel of the A/D conversion.
• If the A/D conversion is activated, A/D conversion will be performed until it reaches
to the channel set in the A/D conversion end channel setting bit (ANE3 to ANE0).
• If you set the channel same as the one which sets in the A/D conversion start channel
setting bit (ANS3 to ANS0), the channel which has been set will be A/D converted.
• In the case of setting sequent conversion mode or stop conversion mode, when A/D
conversion is completed until the channel which sets in A/D conversion end channel
setting bit (ANE3 to ANE0), it returns to the start channel which sets in A/D
conversion start channel setting bit (ANS3 to ANS0) and repeats A/D conversion.
• Do not set the value to the start channel larger than the end channel setting.
Note:
Please do not set the A/D conversion mode setting bit (MD1, MD0) and the A/D
conversion end channel selection bit (ANE3, ANE2, ANE1, and ANE0) by the read
modify write (RMW) instruction after setting the start channel to the A/D conversion
start channel selection bit (ANS3, ANS2, ANS1, ANS0).
The last conversion channel is read from the ANS3, ANS2, ANS1, and ANS0 bits
until the A/D conversion operating starts.
Therefore, when MD1, MD0 bits and ANE3, ANE2, ANE1, and ANE0 bits are set by
the read modify write (RMW) instruction after setting the starting channel to ANS3,
ANS2, ANS1, and ANS0 bits, the value of the ANE3, ANE2, ANE1, and ANE0 bits
may be over-write.
Notes:
• Do not use the values between "1100B" to " 1111B" for the start and end channel settings.
• Do not set the value to the start channel larger than the end channel setting.
441
CHAPTER 19 8/10-BIT A/D CONVERTER
19.5
Interrupt of 8/10-bit A/D Converter
The 8/10-bit A/D converter outputs the interrupt request to CPU when the data is set to
the A/D data register. Also supports for extended intelligent I/O service (EI2OS).
■ Interrupt of 8/10-bit A/D Converter
Table 19.5-1 Interrupt Control Bit and Interrupt Cause of 8/10-bit A/D Converter
8/10-bit A/D converter
Interrupt request flag bit
ADCS1: INT= 1
Interrupt request enable bit
ADCS1: INTE= 1
Interrupt cause
Storing to A/D data register of A/D conversion result.
After A/D conversion is activated when A/D conversion result is stored to A/D data register (ADCR0/
ADCR1), interrupt request flag bit (INT) of A/D control status register (ADCS1) is set to "1". Furthermore,
if interrupt request enable bit (INTE) is set to "1" previously, interrupt request to CPU is output.
■ 8/10-bit A/D Converter Interrupt and EI2OS
Table 19.5-2 8/10-bit A/D Converter Interrupt and EI2OS
Interrupt
number
#37(25H)
Interrupt control registers
Vector table address
EI2OS
Register Name
Address
Low
High
Bank
ICR13
0000BDH
FFFF68H
FFFF69H
FFFF6AH
: Available
■ EI2OS Function of 8/10-bit A/D Converter
The 10 bit A/D converter can transfer the result of A/D conversion to the memory using EI2OS function.
When using EI2OS function, converting data protect function works and the value of A/D data register is
transferred to memory. It is available to prevent from lack of data that A/D conversion is temporary
stopped until interrupt request flag bit (INT) of A/D control status register 1 (ADCS1) is cleared to "0".
442
CHAPTER 19 8/10-BIT A/D CONVERTER
19.6
Explanation of Operation of 8/10-bit A/D Converter
The 8/10-bit A/D converter can be set in 4 types of modes, the single conversion mode
1, single conversion mode 2, continuous conversion mode, and suspend conversion
mode. The operation explanation of each mode is done.
■ Operation of Single Conversion Mode
In single conversion mode, it sequentially converts the analog input which have been set by the ANS bit
and ANE bit, and when it reaches to the end channel set in ANE bit, it stops the A/D conversion. If the start
channel and end channel is the same (ANS=ANE), only one channel specified in the ANS bit will be
converted. To operate in the single conversion mode, you must make setting according to Figure 19.6-1 .
Figure 19.6-1 Setting in Single Conversion Mode
Bit
ADCS0/ADCS1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ReBUSY INT INTE PAUSSTS1STS0 STRTserved MD1 MD0
0
ADCR0/ADCR1 S10 ST1 ST0 CT1 CT0
ADMR
ANS3 ANS2 ANS1 ANS0 ANE3 ANE2 ANE1 ANE0
Store the conversion data
: Used bit
0 : Set "0".
Example of Conversion Order in Single Conversion Mode shows in the following.
When ANS=000B, ANE=011B:AN0 → AN1 → AN2 → AN3 → End
When ANS=110B, ANE=010B:AN6 → AN7 → AN0 → AN1 → AN2 → End
When ANS=011B, ANE=011B:AN3 → End
■ Operation of Continuous Conversion Mode
In the case of setting sequent conversion mode or stop conversion mode, when A/D conversion is
completed until the channel which sets in A/D conversion end channel setting bit (ANE3 to ANE0), it
returns to the start channel which sets in A/D conversion start channel setting bit (ANS3 to ANS0) and
repeats A/D conversion. In sequent conversion mode, when A/D converting the analog input from the start
channel sets in A/D conversion start channel setting bit (ANS3 to ANS0) of A/D control status register 0
(ADCS0) to the end channel which sets in A/D conversion end channel setting bit (ANE3 to ANE0), it
returns the analog input which sets in A/D conversion start channel setting bit (ANS3 to ANS0) and repeats
the A/D conversion.
If the start channel and end channel is the same, it repeats the A/D conversion of the channel which has
been set in the A/D conversion start channel setting bit (ANS3 to ANS0).
The A/D conversion will not be stopped unless the conversion busy bit (BUSY) of the A/D control status
register 1 (ADCS1) is set to "0". Moreover, it is not possible to reactivate while operating. To operate in the
continuous conversion mode, you must make setting accordant to Figure 19.6-2 .
443
CHAPTER 19 8/10-BIT A/D CONVERTER
Figure 19.6-2 Setting in Continuous Conversion Mode
Bit
15
14
13
12
11
10
9
ADCS0/ADCS1 BUSY INT INTE PAUS STS1 STS0 STRT
8
Reserved
0
ADCR0/ADCR1 S10 ST1 ST0 CT1 CT0
ADMR
7
6
5
4
3
2
1
0
MD1 MD0
1
0
Store the conversion data
: Used bit
: Set "1" to the bit corresponding to using pin
: Set "1"
: Set "0"
ANS3 ANS2 ANS1 ANS0 ANE3 ANE2 ANE1 ANE0
Example of Conversion Order in Continuous Conversion Mode shows in the following.
When ANS=000B, ANE=011B:AN0 → AN1 → AN2 → AN3 → AN0 → Repeat
When ANS=110B, ANE=010B:AN6 → AN7 → AN0 → AN1 → AN2 → AN6 → Repeat
When ANS=011B, ANE=011B:AN3 → AN3 → Repeat
■ Operation of Pause-conversion Mode
In the stop conversion mode, while A/D conversion from the start channel set in A/D conversion start
channel setting bit (ANS3 to ANS0) to the channel set in A/D conversion end channel setting bit (ANE3 to
ANE0) is temporary stopped every one channel, after conversion, it returns analog input set in A/D
conversion start channel setting bit (ANS3 to ANS0) and repeats A/D conversion and temporary stop.
If the start channel and end channel is the same, it repeats the A/D conversion of the channel which has
been set in the A/D conversion start channel setting bit (ANS3 to ANS0).
If the suspend mode is set, the restart of the A/D conversion varies depend on the activation factor set in the
A/D activation factor setting bit (STS1, STS0) of the A/D control status register 1 (ADCS1).
The A/D conversion will not be stopped unless the conversion busy bit (BUSY) of the A/D control status
register 1 (ADCS1) is set to "0". Moreover, it is not possible to reactivate while operating. To operate in the
suspend conversion mode, you must make setting according to Figure 19.6-3 .
Figure 19.6-3 Setting in Pause-conversion Mode
Bit
15
14
13
12
11
10
9
ADCS0/ADCS1 BUSY INT INTE PAUS STS1 STS0 STRT
8
Reserved
0
ADCR0/ADCR1 S10 ST1 ST0 CT1 CT0
ADMR ANS3 ANS2 ANS1 ANS0 ANE3 ANE2 ANE1 ANE0
7
6
5
4
3
2
1
0
MD1 MD0
1
1
Store the conversion data
: Used bit
: Set "1" to the bit corresponding to using pin.
1 : Set "1".
0 : Set "0"
Example of Conversion Order in Pause-conversion Mode shows in the following.
When ANS=000B, ANE=011B:AN0 → suspend → AN1 → suspend → AN2 →
suspend → AN3 → suspend → AN0 → repeat
When ANS=110B, ANE=001B:AN6 → suspend → AN7 → suspend → AN0 →
suspend → AN1 → suspend → AN6 → repeat
When ANS=011B, ANE=011B:AN3 → suspend → AN3 → suspend → Repetition
444
CHAPTER 19 8/10-BIT A/D CONVERTER
Conversion Using EI2OS
19.6.1
The 8/10-bit A/D converter allows the transfer of A/D conversion result to memory using
the EI2OS.
■ Conversion Using EI2OS
Figure 19.6-4 Example of Operation Flow Chart when EI2OS is Used
A/D conversion activation
Sample hold
EI2OS activation
Conversion
Data transfer
Conversion completion
Is
specified number of
times finished?*
YES
Interrupt process
NO
Interrupt output
Interrupt clear
*: It is determined by setting of EI2OS.
If EI2OS is used, more than one data can be transferred to the memory without data loss by the converted
data protection function even if it is in continuous conversion mode.
445
CHAPTER 19 8/10-BIT A/D CONVERTER
19.6.2
A/D-converted Data Protection Function
If A/D conversion is performed under the interrupt enabled status, the function of
converted data protection works.
■ A/D-converted Data Protection Function
Because the 8/10 bit A/D converter has only one data register for storing the converted data, the data which
has been stored in the data register is overwritten at the conversion end if the A/D conversion is performed.
In continuous conversion mode, if the converted data has not been transferred to the memory in time, the
part of stored data may be lost.
To prevent the data loss, the data protection function works as follows, when the interrupt request enable
(ADCS1: INTE= 1).
● Data protection function when EI2OS is not used
When the converted data is stored in the A/D data register (ADCR0/ADCR1), "1" is set to the interrupt
request flag bit (INT) in the A/D control status register 1 (ADCS1) and suspend the A/D conversion. In the
process of interrupt routine, if the interrupt request flag bit (INT) is cleared to "0" after the data in A/D data
register (ADCR0/ADCR1) has been transferred to the memory or other devices, the A/D conversion is
restarted.
● Data protection function when EI2OS is used
When using EI2OS in sequent conversion mode, if previous data is not completed to transfer to memory
although A/D conversion completed, "1" is set in suspended flag bit (PAUS) of A/D control status register
1 (ADCS1), A/D conversion operation is temporary stopped and conversion data is not stored in A/D data
register (ADCR0/ADCR1). When the transfer of previous data to the memory is completed, the suspend
flag bit (PAUS) is cleared to "0", and the A/D conversion operation will be restarted.
446
CHAPTER 19 8/10-BIT A/D CONVERTER
Figure 19.6-5 Data Protection Function Flow when EI2OS is Used
EI2OS setting
A/D continuous conversion
activation
1 time conversion completed
Store in data register
EI2OS activation
2 times conversion completed
EI2OS completion
NO
A/D temporary stop
YES
Store in data register
3 times conversion
EI2OS activation
Continued
All conversion finished
Continued
Store in data register
EI2OS activation
Interrupt process routine
A/D initialization or stop
Completion
Note: Flow at A/D converter operating stop is omitted.
Notes:
• The conversion data protection function works if the interrupt is enabled (ADCS1: INTE= 1).
• When EI2OS is used and A/D conversion is suspended, if the interrupt is prohibited, then A/D
conversion operation starts and newly converted data may be written before the previous data has
been transferred.
• If reactivation is performed under suspension, the waiting data will be destroyed.
447
CHAPTER 19 8/10-BIT A/D CONVERTER
448
CHAPTER 20
LCD CONTROLLER/DRIVER
In this chapter, the functions and operation of the LCD
controller/driver are explained.
20.1 Outline of LCD Controller/Driver
20.2 Composition of LCD Controller/Driver
20.3 Terminal of LCD Controller/Driver
20.4 Register of LCD Controller/Driver
20.5 Display RAM of LCD Controller/Driver
20.6 Operation Explanation of LCD Controller/Driver
449
CHAPTER 20 LCD CONTROLLER/DRIVER
20.1
Outline of LCD Controller/Driver
LCD controller/driver which is built-in 24 8 bits display data memory controls the LCD
display by 4 common outputs and 48 segment outputs. Three duty outputs can be
selected to directly drive the LCD panel (liquid crystal display).
■ Function of LCD Controller/Driver
The LCD controller/driver has a function for directly displaying the contents of the display data memory
(display RAM) on the LCD panel (liquid crystal display) by the segment and common outputs.
● Contains an LCD driving voltage split resistor. Moreover, the external division resistance can be
connected.
● A maximum of four common output lines (COM0 to COM3) and 48 segment output lines (SEG0 to
SEG47) are available.
● Contains 24-byte display data memory (display RAM).
● For the duty, 1/2, 1/3, or 1/4 can be selected (restricted by bias setting).
● The LCD can directly be driven.
Indicates combinations of bias duties available.
Table 20.1-1 Combination Table of Bias Duty
Bias
1/2 duty
1/3 duty
1/4 duty
1/2 biases
1/3 bias setting
: mode
: Disable
The SEG12 to SEG47 pins cannot be used as segment outputs when LCRH/LCRR has been set for generalpurpose ports.
450
CHAPTER 20 LCD CONTROLLER/DRIVER
20.2
Composition of LCD Controller/Driver
The LCD controller/driver consists of eight blocks listed below and can be functionally
divided into the controller unit used for generating segment and common signals and
the driver unit used for driving the LCD.
• LCDC
control register (LCRL/LCRH)
• LCDC range register (LCRR)
• Display RAM
• Prescaler
• Timing controller
• Circuit of making to exchange
• Common driver
• Segment driver
• Division resistance
451
CHAPTER 20 LCD CONTROLLER/DRIVER
■ Composition of LCD Controller/Driver
Figure 20.2-1 Block Diagram of LCD Controller/Driver
LCDC range register
(LCRR)
V0 V1 V2 V3
LCDC control register L
(LCRL)
4
Timing
controller
Sub clock
(32 kHz)
Circuit of making
to exchange
Internal data bus
Prescaler
48
Display RAM
24 x 8 bits
Common driver
Main clock
COM0
COM1
COM2
COM3
Segment driver
Division resistance
SEG0
SEG1
SEG2
SEG3
SEG4
to
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
LCDC control register H
(LCRH)
Controller
Driver
• LCDC control register lower (LCRL)
Controls the LCD driving power, selects display/non-display blanking, selects display mode, and selects
the LCD clock cycle.
• LCDC control register higher (LCRH)
Register for switching segment output, V pin, COM pin, and general-purpose port.
• LCDC range register (LCRR)
Switch the segment output and general-purpose port and selects the LCD driving voltage division
resistor. The internal division resistance has two kinds.
• Display RAM
24 × 8 bits RAM for segment output signal generation. The contents of this RAM are automatically
read out in synchronization with the common signal selection timings. And the contents output from the
segment output pins at the same time as rewriting to the display RAM.
• Prescaler
Generates frame frequency according to the settings selected from four frequencies.
452
CHAPTER 20 LCD CONTROLLER/DRIVER
• Timing controller
Controls the common and segment signals based on the frame frequency and LCRL register settings.
• Circuit of making to exchange
Generates AC waveform for LCD driving from the timing controller signals.
• Common driver
This is the LCD common terminal driver.
• Segment driver
This is the LCD segment terminal driver.
• Division resistance
Resistor for generating divided LCD driving voltage. Selectable with LCDC control register lower part
(LCRL: VSEL). In addition, two division resistors are mounted; they can be selected by the LCDC
resistor register (LCRR: LCR). The division resistance can put the outside.
■ Power-supply Voltage of LCD Controller/Driver
Set the LCD driver power voltage by using the incorporated division resistor or connecting the division
resistor to the V0 to V3 pins.
453
CHAPTER 20 LCD CONTROLLER/DRIVER
20.2.1
Internal Division Register of LCD Controller/Driver
The LCD driver power voltage is generated by the external division resistor connected
to the V0 to V3 pins or the internal division resistor. The internal division resistor can be
selected from two types of resistors.
■ Internal Division Register of LCD Controller/Driver
LCD controller driver is built-in internal division resister. In addition, the external division resistor can be
connected to the LCD driving power pins (V0 to V3).
The internal and external division resistors are selected by the driving power control bit (LCRL: VSEL) of
the LCD control register. When the VSEL bit is set to "1", the internal division resistor is supplied the
power. When using the internal split resistor without connecting external division resistor, set the VSEL bit
to "1".
When connecting the external division resistor, set the VSEL bit to "0" to isolate the internal resistor.
The internal division resistor (R) can be selected from approximately 100 k Ω/ approximately 12.5 kΩ
(approximately 200 kΩ/ approximately 25 kΩ between VCC and V3) by the LCDC resistor register (LCRR:
LCR).
The LCD controller enable is made inactive when LCD operation is stopped (LCRL: MS1, MS0 = 00B).
The internal division resistor equivalent circuit is shown in Figure 20.2-2 .
Figure 20.2-2 Equivalent Circuit in the Internal Division Resistor
VCC
2R
P-ch
N-ch
V3
V3
R
P-ch
N-ch
P-ch
V2
V2
VSHT
SW
N-ch
R
P-ch
N-ch
P-ch
V1
V1
P-ch
R
P-ch
N-ch
V0
V0
LCD controller
enable
VSEL
VS0
V0 to V3: Voltage value of V0 to V3 pin
454
N-ch
N-ch
N-ch
CHAPTER 20 LCD CONTROLLER/DRIVER
■ Use of Internal Division Resistance
Even when the internal division resistor is used, connect an external resistor to between VCC and V3.
The state when using the internal division resistor is shown in Figure 20.2-3 .
When setting 1/2 bias, the V2 and V1 pins are short-circuited by the internal switch (control signal: VSHT).
When using the external division resistor with 1/2 bias setting, the switch is set OFF; therefore, shortcircuit it with an external resistor.
Figure 20.2-3 State when Using the Internal Division Resistor
VCC
VCC
VR
V3
2R
V2
R
V1
R
V0
R
2R
V2
V2
R
V1
V1
R
V0
V0
R
V3
LCD controller
enable
VR
V3
V3
LCD controller
enable
Q1
1/2 bias
V2
V1
V0
Q1
1/3 bias
V0 to V3: Voltage value of V0 to V3 pin
■ Terminal V Switch
When using the internal division resistor, three ports V2 to V0 can be switched to ports by the LCDC
control register higher part (LCRH: VS0).
■ Intensity Control when Internal Division Resistance is Used
If the intensity is not raised by using the internal division resistor, connect the VR (variable resistor) to the
external (between the VCC and V3 pins) and adjust the V3 voltage.
Figure 20.2-4 Intensity Adjustment when Using the Internal Division Resistor
VCC
VR
V3
2R
V2
R
V1
R
V0
R
LCD controller
enable
V3
V2
V1
V0
Q1
Adjusting the brightness
V0 to V3: Voltage value of V0 to V3 pin
455
CHAPTER 20 LCD CONTROLLER/DRIVER
20.2.2
External Division Register of LCD Controller/Driver
The external division resistor can be connected to the LCD driving power pins (V0 to
V3). The external division resistor connections and LCD driving voltages related to the
bias type are shown in Figure 20.2-5 and Table 20.2-1 .
■ External Division Register of LCD Controller/Driver
Figure 20.2-5 Connection Example of External Division Resistor
VCC
VCC
VR
V3
R
V2
VR
V3
R
V2
VLCD
R
V1
VLCD
V1
R
V0
R
V0
V0=VSS
V0=VSS
1/2 bias
1/3 bias
Table 20.2-1 Setting of LCD Drive Voltage
V3
V2
V1
V0
1/2 biases
VLCD
1/2VLCD
1/2VLCD
VSS
1/3 bias setting
VLCD
2/3VLCD
1/3VLCD
VSS
V0 to V3: Voltage of the V0 to V3 terminals
VLCD: LCD operating voltage
456
CHAPTER 20 LCD CONTROLLER/DRIVER
■ Use of External Division Resistance
As the V0 pin is internally connected to VSS (GND) through a transistor, current flowing to the resistor at
LCD controller stop can be blocked by connecting the division resistor VSS side to only the V0 pin when
using the external division resistor.
The state when using the external division resistor is shown in Figure 20.2-6 .
Figure 20.2-6 State when Using the External Division Resistor
VCC
V3
V2
V1
V0
LCD controller
enable
2R
V3
R
V2
R
V1
R
V0
VR
RX
RX
RX
V0=VSS
Q1
• To connect the external resistor without being influenced by the internal division resistor, the internal
division resistor must be entirely isolated by writing "0" in the driving voltage control bit (LCRL:
VSEL) of the LCD control register. When using the external division resistor, be sure to set the V pin
switching bit (LCRH: VS0) to "0".
• When a value other than "00B" is written to the display mode selection bit (LCRL: MS1, MS0) of the
LCD control register with the internal division resistor isolated, the LCDC enable transistor (Q1) turns
ON causing current to flow in the external division resistor.
• When "00B" is written to the display mode selection bit (MS1, MS0), the LCDC enable transistor (Q1)
turns OFF causing no current to flow in the external division resistor.
RX to be connected to the external varies by LCD; therefore, select an appropriate value.
457
CHAPTER 20 LCD CONTROLLER/DRIVER
20.3
Terminal of LCD Controller/Driver
Terminals while relates to LCD controller/driver and block diagrams of terminals are
shown.
■ Terminal of LCD Controller/Driver
The pins related to the LCD controller/driver are four common output pins (COM0 to COM3), 48 segment
output pins (SEG0 to SEG47), and 4 LCD driving power pins (V0 to V3).
Table 20.3-1 LCD Controller/Driver Pin Functions (1/2)
Pin name
Functions
SEG0 to SEG11
It is a terminal only for the LCD segment output.
P00/SEG12 to P07/
SEG19
Serves functions as the general-purpose input/output port and LCD segment output pin.
The functions are switched by the settings in the LCRR register.
P10/SEG20 to P17/
SEG27
Serves functions as the general-purpose input/output port and LCD segment output pin.
The functions are switched by the settings in the LCRR register.
P20/SEG28 to P23/
SEG31
Serves functions as the general-purpose input/output port and LCD segment output pin.
The functions are switched by the settings in the LCRR register.
P24/SEG32 to P27/
SEG35
Serves functions as the general-purpose input/output port and LCD segment output pin.
The functions are switched by the settings in the LCRH register.
P30/SEG36/SO3
Serves functions as the general-purpose input/output port, LCD segment output pin, and serial I/O
data output pin.
The functions are switched by the settings in the LCRH register.
P31/SEG37/SC3
Serves functions as the general-purpose input/output port, LCD segment output pin, and serial
clock input/output pin.
The functions are switched by the settings in the LCRH register.
P32/SEG38/SI3
Serves functions as the general-purpose input/output port, LCD segment output pin, and serial I/O
data input pin.
The functions are switched by the settings in the LCRH register.
P33/SEG39/TMCK
Serves functions as the general-purpose input/output port, LCD segment output pin, and timer
clock output pin.
The functions are switched by the settings in the LCRH register.
P34/SEG40/IC0,
P35/SEG41/IC1
Serves functions as the general-purpose input/output port, LCD segment output pin, and input
capture external trigger input pin.
The functions are switched by the settings in the LCRH register.
P36/SEG42/OCU0,
P37/SEG43/OCU1
Serves functions as the general-purpose input/output port, LCD segment output pin, and output
compare output pin.
The functions are switched by the settings in the LCRH register.
458
CHAPTER 20 LCD CONTROLLER/DRIVER
Table 20.3-1 LCD Controller/Driver Pin Functions (2/2)
Pin name
Functions
P50/SEG44/TIN0,
P51/SEG45/TIN1
Serves functions as the general-purpose input/output port, LCD segment output pin, and reload
timer external clock input pin.
The functions are switched by the settings in the LCRH register.
P52/SEG46/TIN2/
PPG0
Serves functions as the general-purpose input/output port, LCD segment output pin, reload timer
external clock input pin, and PPG timer output pin.
The functions are switched by the settings in the LCRH register.
P53/SEG47/PPG1
Serves functions as the general-purpose input/output port, LCD segment output pin, and PPG
timer output pin.
The functions are switched by the settings in the LCRH register.
COM0, COM1
It is a terminal only for LCD common output.
P83/COM2,
P84/COM3
Serves functions as the general-purpose input/output port and COM output pin. The functions are
switched by the settings in the LCRH register.
V3
Dedicated pin for LCD driver power supply.
V2/P82 to V0/P80
Serves functions as the LCD driver power pin and general-purpose input/output port. The
functions are switched by the settings in the LCRH register.
■ Block Diagram of Pins Related to LCD Controller/Driver
Figure 20.3-1 Block Diagram of Pins Related to LCD Controller/Driver
Internal data bus
Port data register (PDR)
PDR read
Output latch
PDR write
Pin
Port data direction register (PDR)
DDR
DDR write
DDR read
Pin: P00/SEG12 to P07/SEG19
P10/SEG20 to P17/SEG27
P20/SEG28 to P27/SEG35
P83/COM2, P84/COM3
Standby control (SPL = 1)
LCD output
LCD output enable
459
CHAPTER 20 LCD CONTROLLER/DRIVER
Figure 20.3-2 Block Diagram of Pins Related to LCD Controller/Driver
Resource output
Resource input
Resource output enable
Port data register (PDR)
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (PDR)
DDR
DDR write
DDR read
Pin:
Standby control (SPL = 1)
P30/SEG36/SO3, P31/SEG37/SC3
P32/SEG38/SI3, P33/SEG39/TMCK
P34/SEG40/IC0, P35/SEG41/IC1
P36/SEG42/OCU0, P37/SEG43/OCU1
P50/SEG44/TIN0, P51/SEG45/TIN1
P52/SEG46/TIN2/PPG0
P53/SEG47/PPG1
LCD output
LCD output enable
Figure 20.3-3 Block Diagram of Pins Related to LCD Controller/Driver
LCRH
VS
Internal data bus
Port data register (PDR)
LCD input (V0 to V3)
PDR read
Output latch
PDR write
Pin
Port data direction register (PDR)
DDR
DDR write
DDR read
Pin: V2/P82 to V0/P80
460
Standby control (SPL = 1)
CHAPTER 20 LCD CONTROLLER/DRIVER
20.4
Register of LCD Controller/Driver
Registers related to LCD controller/driver are shown.
■ Registers Related to LCD Controller/Driver
Figure 20.4-1 Registers Related to LCD Controller/Driver
LCRL(LCDC control register lower)
bit4
bit3
bit2
bit1
bit0 Initial value
BK
MS1
MS0
FP1
FP0
R/W
R/W
R/W
R/W
R/W
bit15 bit14 bit13 bit12 bit11 bit10
bit9
bit8 Initial value
SS4
VS0
CS1
CS0
SS3
SS2
SS1
SS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit6
bit5
bit4
bit3
bit2
bit1
bit0 Initial value
SE4
SE3
SE2
SE1
SE0
LCR
R/W
R/W
R/W
R/W
R/W
R/W
bit7
Address
00005CH
bit6
bit5
CSS LCEN VSEL
R/W
R/W
R/W
00010000B
LCRH(LCDC control register upper)
Address
00005DH
00000000B
LCRR(LCDC range register)
bit7
Address
00005EH
Reserved Reserved
R/W
R/W
00000000B
R/W : Readable/Writable
461
CHAPTER 20 LCD CONTROLLER/DRIVER
20.4.1
LCDC Control Register Lower (LCRL)
The LCDC control register lower part (LCRL) is a register used for driving power
control, display blanking, and display mode selection.
■ LCDC Control Register Lower (LCRL)
Figure 20.4-2 LCDC Control Register Lower (LCRL)
bit5
bit4
bit3
bit0
Initial value
00005CH CSS LCEN VSEL
BK
MS1 MS0 FP1 FP0
00010000B
Address
bit7
bit6
R/W R/W R/W
bit2
bit1
R/W R/W R/W R/W R/W
FP1 FP0
0
0
1
1
0
1
0
1
Frame cycle selection bits
CSS=0
CSS=1
13
Fc/2 xN
Fc/25xN
14
Fc/2 xN
Fc/26xN
15
Fc/2 xN
Fc/27xN
Fc/216xN
Fc/28xN
N: Time-division count
Fc: Oscillation
MS1 MS0
0
0
1
1
BK
0
1
VSEL
0
1
LCEN
R/W
: Readable/Writable
: Initial value
462
0
1
0
1
Display mode selection bits
LCD operation stop
1/2 duty output mode (Time-division count N=2)
1/3 duty output mode (Time-division count N=3)
1/4 duty output mode (Time-division count N=4)
Display blanking selection bit
Display
Display blanking
LCD driving power control bit
External division resistor used
Internal division resistor used
At timebase timer mode/operation enable bit
at clock mode
0
Timebase timer/watch mode operation stopped.
1
Timebase timer/watch mode operation not stopped.
Be sure to set the clock selection bit (CSS) to "1"
at watch mode.
CSS
0 Main clock
1 Sub clock
Clock selection bit
CHAPTER 20 LCD CONTROLLER/DRIVER
Table 20.4-1 Function Description of Bits in LCDC Control Register Lower Part (LCRL)
Bit name
Functions
bit7
CSS:
Clock
selection bit
This bit is clock selection bit for prescaler.
0: selecting main clock
1: selecting sub clock
bit6
LCEN:
At timebase
timer mode/
Operation
enable bit at
watch mode
Operation enable bit for timebase timer mode/watch mode.
In the timebase timer mode/watch mode, the LCD display stops when this bit is "0" and operates
when this bit is "1".
In the watch mode, be sure to set "1" in the clock selection bit (CSS) to select the sub clock.
bit5
VSEL:
LCD driving
power control
bit
Bit for selecting whether or not to supply power to the internal division resistor.
The internal division resistor is blocked when the VSEL bit is "0" and in conduction state when
the VSEL bit is "1". When connecting the external division resistor, set the VSEL bit to "0".
bit4
BK:
Display
blanking
selection bit
Show/Hide LCD is selected.
For display unit blanking (non-display, BK = 1), the segment output is unselected waveform
(waveform not in the display conditions).
bit3,
bit2
MS1, MS0:
Display mode
selection bits
Select one of three output waveform duties.
The common pin to be used is determined depending on the selected duty output mode.
When these bits are "0s", the LCD controller/driver stops the display operation.
Note:
When the selected frame cycle generation clock is to be stopped for transition to the stop mode,
etc., stop the display operation in advance.
bit1,
bit0
FP1, FP0:
Frame cycle
selection bits
Select one of four LCD display frame cycles.
Note:
According to the LCD module to be used, calculate the optimum frame frequency and set the
registers.
The frame frequency is influenced by the original oscillation frequency.
463
CHAPTER 20 LCD CONTROLLER/DRIVER
20.4.2
LCDC Control Register Higher (LCRH)
The LCDC control register higher (LCRL) is a register used for switching segment
output (SEG32 to SEG47), V pin inputs (V0 to V2), COM pin outputs (COM2 and COM3),
and general-purpose ports.
■ LCDC Control Register Higher (LCRH)
Figure 20.4-3 LCDC Control Register Higher (LCRH)
Address
00005DH
bit15 bit14 bit13 bit12 bit11 bit10 bit9
bit8
Initial value
SS3 SS2 SS1 SS0
00000000B
SS4 VS0 CS1
CS0
R/W R/W R/W
R/W R/W R/W R/W R/W
SEG32 to SEG47 output switching bits
SS4 SS3 SS2 SS1 SS0
0
X
X
X
X
1
0
0
0
0
1
0
0
0
1
0
0
1
1
0
0
1
0
1
0
1
: Initial value
464
General-purpose port
P24 to P27,P30 to P37,P50 to P53
SEG32
P25 to P27,P30 to P37,P50 to P53
1
SEG32, SEG33
P26,P27,P30 to P37,P50 to P53
0
SEG32 to SEG34
P27,P30 to P37,P50 to P53
1
1
SEG32 to SEG35
P30 to P37,P50 to P53
1
0
0
SEG32 to SEG36
P31 to P37,P50 to P53
1
0
1
SEG32 to SEG37
P32 to P37,P50 to P53
0
1
1
0
SEG32 to SEG38
P33 to P37,P50 to P53
1
0
1
1
1
SEG32 to SEG39
P34 to P37,P50 to P53
1
1
0
0
0
SEG32 to SEG40
P35 to P37,P50 to P53
1
1
0
0
1
SEG32 to SEG41
P36,P37,P50 to P53
1
1
0
1
0
SEG32 to SEG42
P37,P50 to P53
1
1
0
1
1
SEG32 to SEG43
P50 to P53
1
1
1
0
0
SEG32 to SEG44
P51 to P53
1
1
1
0
1
SEG32 to SEG45
P52,P53
1
1
1
1
0
SEG32 to SEG46
P53
1
1
1
1
1
SEG32 to SEG47
VS0
0
1
R/W : Readable/Writable
Segment
output
V pin switching bit
V0 to V2
P80 to P82
COM pin switching bits
CS1CS0
0 0 COM0, COM1
0 1 COM0 to COM2
1 X COM0 to COM3
CHAPTER 20 LCD CONTROLLER/DRIVER
Table 20.4-2 Function Description of Bits in LCDC Control Register Higher Part (LCRH)
Bit name
Functions
bit15
SS4:
SEG32 to SEG47
output switching
bit
Select whether to use P24 to P27, P30 to P37, P50 to P53/SEG32 to SEG47 pins as segment
outputs or general-purpose ports.
bit14
VS0:
V pin switching
bit
Select whether to use P80 to P82/V0 to V2 pins as V0 to V2 or general-purpose ports.
Note:
When using the V pin as a general-purpose port, be sure to enable the internal division
resistor. Set the LCD driving power control bit (VSEL) to "1" in advance.
bit13,
bit12
CS1, CS0:
COM pin
switching bits
Select whether to use P83/COM2, P84 to COM3 pins as COM or general-purpose ports.
bit11
to
bit8
SS3 to SS0:
SEG32 to SEG47
output switching
bits
Switch whether to use P47/SEG21, P90/SEG22, P91/SEG23 pins as segment outputs or as
general purpose I/O ports.
465
CHAPTER 20 LCD CONTROLLER/DRIVER
20.4.3
LCDC Range Register (LCRR)
The LCDC range register (LCRR) is a register used for switching the segment outputs
(SEG12 to SEG31) and general-purpose ports and selecting the internal division resistor
for LCD driving voltage generation.
■ LCDC Range Register (LCRR)
Figure 20.4-4 LCDC Range Register (LCRR)
Address
00005EH
bit7
bit6
bit5
bit4
bit3
bit0
Initial value
Reserved
Reserved
bit2
bit1
SE4
SE3
SE2 SE1 SE0 LCR
00000000B
R/W R/W R/W
R/W
R/W R/W R/W R/W
0
Internal divided resistor selection bit
Internal division resistor is selected approx. 100kΩ
(approx. 200kΩbetween Vcc and V3).
1
External division resistor is selected approx. 12.5kΩ
(approx. 25kΩ between Vcc and V3).
LCR
SE4 SE3 SE2 SE1SE0
0
0
0
0
P00 to P07,P10 to P17,P20 to P23
0
0
0
0
1
SEG12 to SEG15 P04 to P07,P10 to P17,P20 to P23
0
0
0
1
1
SEG12 to SEG19
P10 to P17,P20 to P23
0
0
1
1
1
SEG12 to SEG23
P14 to P17,P20 to P23
0
1
1
1
1
SEG12 to SEG27
P20 to P23
1
1
1
1
1
SEG12 to SEG31
0
466
General-purpose port
Segment output
0
Reserved
R/W : Readable/Writable
: Initial value
SEG12 to SEG31 output switching bits
Reserved bits
Be sure to set this bit to "0".
CHAPTER 20 LCD CONTROLLER/DRIVER
Table 20.4-3 Function Description of Bits in LCD Control Register Higher Part (LCRH)
Bit name
Functions
bit7,
bit6
Reserved:
Reserved bits
Reserved bit.
Be sure to set this bit to "0".
bit5
to
bit1
SE4 to SE0:
SEG12 to SEG31 output
switching bits
Select whether to use P00/SEG12 to P07/SEG19, P10/SEG20 to P17/SEG27, P20/
SEG28 to P23/SEG31 pins as segment outputs or general-purpose ports.
bit0
LCR:
Internal divided register
selection bit
Select LCD driving power generation or internal division register.
467
CHAPTER 20 LCD CONTROLLER/DRIVER
20.5
Display RAM of LCD Controller/Driver
The display RAM is 24 x 8 bits display data memory for generating segment output
signals.
■ Display RAM and Output Terminal
The contents of this RAM are automatically read out in synchronization with the common signal selection
timings and output from the segment output pins.
This is converted to the selected voltage (LCD display) and output when the bit contents are "1s" and
converted to the unselected voltage (LCD non-display) and output when the bit contents are "0s ".
As the LCD display operation is performed asynchronously of the CPU operations, the display RAM can
be read or written at any timings.
Of the SEG0 to SEG47 pins, the pins not specified as segment outputs in the LCRH register can be used as
general-purpose ports and the related RAM can be used as ordinary RAM.
The relationship between the duty/common outputs and display RAM are shown in Table 20.5-2 .
The correspondence between the display RAM and common/segment output pins are shown in Figure 20.5-1 .
Figure 20.5-1 Correspondence between Display RAM and Common/segment Output Pins (1/2)
Address
bit3
bit2
bit1
bit0
SEG0
7900H
bit7
bit6
bit5
bit4
SEG1
bit11
bit10
bit9
bit8
SEG2
bit15
bit14
bit13
bit12
SEG3
bit3
bit2
bit1
bit0
SEG4
bit7
bit6
bit5
bit4
SEG5
bit11
bit10
bit9
bit8
SEG6
bit15
bit14
bit13
bit12
SEG7
bit3
bit2
bit1
bit0
SEG8
bit7
bit6
bit5
bit4
SEG9
bit11
bit10
bit9
bit8
SEG10
bit15
bit14
bit13
bit12
SEG11
bit3
bit2
bit1
bit0
SEG12
bit7
bit6
bit5
bit4
SEG13
bit11
bit10
bit9
bit8
SEG14
bit15
bit14
bit13
bit12
SEG15
7901H
7902H
7903H
7904H
7905H
7906H
7907H
468
CHAPTER 20 LCD CONTROLLER/DRIVER
Figure 20.5-1 Correspondence between Display RAM and Common/segment Output Pins (2/2)
7908H
7909H
790AH
790BH
790CH
790DH
790EH
790FH
7910H
7911H
7912H
7913H
7914H
7915H
7916H
7917H
bit3
bit2
bit1
bit0
SEG16
bit7
bit6
bit5
bit4
SEG17
bit11
bit10
bit9
bit8
SEG18
bit15
bit14
bit13
bit12
SEG19
bit3
bit2
bit1
bit0
SEG20
bit7
bit6
bit5
bit4
SEG21
bit11
bit10
bit9
bit8
SEG22
bit15
bit14
bit13
bit12
SEG23
bit3
bit2
bit1
bit0
SEG24
bit7
bit6
bit5
bit4
SEG25
bit11
bit10
bit9
bit8
SEG26
bit15
bit14
bit13
bit12
SEG27
bit3
bit2
bit1
bit0
SEG28
bit7
bit6
bit5
bit4
SEG29
bit11
bit10
bit9
bit8
SEG30
bit15
bit14
bit13
bit12
SEG31
bit3
bit2
bit1
bit0
SEG32
bit7
bit6
bit5
bit4
SEG33
bit11
bit10
bit9
bit8
SEG34
bit15
bit14
bit13
bit12
SEG35
bit3
bit2
bit1
bit0
SEG36
bit7
bit6
bit5
bit4
SEG37
bit11
bit10
bit9
bit8
SEG38
bit15
bit14
bit13
bit12
SEG39
bit3
bit2
bit1
bit0
SEG40
bit7
bit6
bit5
bit4
SEG41
bit11
bit10
bit9
bit8
SEG42
bit15
bit14
bit13
bit12
SEG43
bit3
bit2
bit1
bit0
SEG44
bit7
bit6
bit5
bit4
SEG45
bit11
bit10
bit9
bit8
SEG46
bit15
bit14
bit13
bit12
SEG47
COM3
COM2
COM1
COM0
469
CHAPTER 20 LCD CONTROLLER/DRIVER
Table 20.5-1 Relationship between Common/Segments and Display RAM, and Dual-purpose Pins
LCRH/LCRR register
SS4 to SS0, SE4 to SE0 bit
value
Segment used
RAM area used
as display
General-purpose port terminal
which can be used
SE4 to SE0
SS4 to SS0
00000B
0XXXXB
SEG0 to SEG11 (12 pins)
7900H to 7905H
P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P50 to P53
00001B
0XXXXB
SEG0 to SEG15 (16 pins)
7900H to 7907H
P04 to P07, P10 to P17, P20 to P27,
P30 to P37, P50 to P53
00011B
0XXXXB
SEG0 to SEG19 (20 pins
7900H to 7909H
P10 to P17, P20 to P27, P30 to P37,
P50 to P53
00111B
0XXXXB
SEG0 to SEG23 (24 pins)
7900H to 790BH
P14 to P17, P20 to P27, P30 to P37,
P50 to P53
01111B
0XXXXB
SEG0 to SEG27 (28 pins)
7900H to 790DH
P20 to P27, P30 to P37, P50 to P53
11111B
0XXXXB
SEG0 to SEG31 (32 pins)
7900H to 790FH
P24 to P27, P30 to P37, P50 to P53
11111B
10000B
SEG0 to SEG32 (33 pins)
7900H to 7910H
P25 to P27, P30 to P37, P50 to P53
11111B
10001B
SEG0 to SEG33 (34 pins)
7900H to 7910H
P26, P27, P30 to P37, P50 to P53
11111B
10010B
SEG0 to SEG34 (35 pins)
7900H to 7911H
P27, P30 to P37, P50 to P53
11111B
10011B
SEG0 to SEG35 (36 pins)
7900H to 7911H
P30 to P37, P50 to P53
11111B
10100B
SEG0 to SEG36 (37 pins)
7900H to 7912H
P31 to P37, P50 to P53
11111B
10101B
SEG0 to SEG37 (38 pins)
7900H to 7912H
P32 to P37, P50 to P53
11111B
10110B
SEG0 to SEG38 (39 pins)
7900H to 7913H
P33 to P37, P50 to P53
11111B
10111B
SEG0 to SEG39 (40 pins)
7900H to 7913H
P34 to P37, P50 to P53
11111B
11000B
SEG0 to SEG40 (41 pins)
7900H to 7914H
P35 to P37, P50 to P53
11111B
11001B
SEG0 to SEG41 (42 pins)
7900H to 7914H
P36, P37, P50 to P53
11111B
11010B
SEG0 to SEG42 (43 pins)
7900H to 7915H
P37, P50 to P53
11111B
11011B
SEG0 to SEG43 (44 pins)
7900H to 7915H
P50 to P53
11111B
11100B
SEG0 to SEG44 (45 pins)
7900H to 7916H
P51 to P53
11111B
11101B
SEG0 to SEG45 (46 pins)
7900H to 7916H
P52, P53
11111B
11110B
SEG0 to SEG46 (47 pins)
7900H to 7917H
P53
11111B
11111B
SEG0 to SEG47 (48 pins)
7900H to 7917H
None
Reference:
RAM region not used as display can be used as usual RAM.
However, only byte access is possible.
470
CHAPTER 20 LCD CONTROLLER/DRIVER
Table 20.5-2 Relationship between Duty/common Outputs And Display RAM Bits Used
Bit of each display data used
Duty
set value
Common power output
for using
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
-
-
-
1/2
COM0, COM1(2 pins)
-
1/3
COM0 to COM2(3 pins)
-
1/4
COM0 to COM3(4 pins)
-
: Used
-: Unused
471
CHAPTER 20 LCD CONTROLLER/DRIVER
20.6
Operation Explanation of LCD Controller/Driver
The LCD controller/driver performs controlling and driving necessary for LCD display.
■ Operation Explanation of LCD Controller/Driver
The following setting is necessary to display LCD.
Figure 20.6-1 Setting of Controller LCD/Driver
bit7
LCRL
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CSS LCEN VSEL
BK
MS1 MS0 FP1 FP0
other than "00B"
bit15 bit14 bit13 bit12 bit11 bit10 bit9
LCRH
SS4 VS0 CS1
bit7
bit6
LCRR
0
Display RAM
7900H to 7917H
bit8
CS0
SS3 SS2 SS1 SS0
bit5
bit4
bit3
SE4
SE3
SE2 SE1 SE0 LCR
bit2
bit1
bit0
0
Display data
: Used bit
0 : Set to "0"
When above settings have been made and the selected frame cycle generation clock is oscillating, the LCD
panel driving waveform is output to the common and segment output pins (COM0 to COM3 and SEG0 to
SEG47) according to the contents of the display RAM.
The frame cycle generation clock can be switched even while the LCD display is operating. The display
may blink when switching the clock. To avoid blinking, switch the clock after temporarily stopping the
display by blanking (LCRL: BK = 1) etc.
The display drive output is a 2-frame alternating waveform selected by bias and duty settings.
For 1/2 duty, COM2 and COM3 pins output waveform of unselected level. Likewise, for 1/3 duty, the
COM3 pin outputs waveform of unselected level.
When the LCD display operation is stopped (LCRL: MS1, MS0 = 00B) or during reset operation, the
common and segment output pins are both in the "L" level.
Note:
When the selected frame cycle generation clock is stopped during LCD display operation, the
alternating circuit stops and, consequently, direct current is applied to the liquid crystal elements.
In this case, the LCD display operation must be stopped in advance. The condition for stopping
the original oscillation clock is based on the standby mode selection.
472
CHAPTER 20 LCD CONTROLLER/DRIVER
■ Drive Waveform for the LCD
Due to the characteristics of the LCD, DC driving of the LCD causes the crystal display elements to be
deteriorated due to chemical changes. Therefore, the LCD controller/driver contains an alternating circuit
and drives the LCD by the 2-frame alternating waveform. There are three output waveforms types listed
below.
1/2 biases 1/2-duty output corrugated sheet
1/3 biases 1/3-duty output corrugated sheet
1/3 biases 1/4-duty output corrugated sheet
473
CHAPTER 20 LCD CONTROLLER/DRIVER
20.6.1
Output Waveform at LCD Controller/Driver Operation
(1/2 duty)
The display drive output is a 2-frame alternating waveform of the multiplex driving type.
For 1/2 duty, only COM0 and COM1 are used for display. Neither COM2 nor COM3 are
used.
■ 1/2 Biases 1/2-duty Power Output Corrugated Sheet
For display, the crystal elements that have the maximum potential difference between the common and
segment outputs are set ON.
The output waveform when the display RAM contents are the same as Table 20.6-1 is shown in Figure
20.6-2 .
Table 20.6-1 Example of Content of Display RAM
Content of display RAM
Segment
COM3
COM2
COM1
COM0
SEGn
-
-
0
0
SEGn+1
-
-
0
1
-: Unused
474
CHAPTER 20 LCD CONTROLLER/DRIVER
Figure 20.6-2 1/2 bias, 1/2 Duty Output Waveform Example
COM0
V3
V2=V1
V0=Vss
COM1
V3
V2=V1
V0=Vss
COM2
V3
V2=V1
V0=Vss
COM3
V3
V2=V1
V0=Vss
SEGn
V3
V2=V1
V0=Vss
SEGn+1
V3
V2=V1
V0=Vss
Potential difference between
COM0 and SEGn
V3(ON)
V2
V0=Vss
-V2
-V3(ON)
Potential difference between
COM1 and SEGn
V3(ON)
V2
V0=Vss
-V2
-V3(ON)
Potential difference between
COM0 and SEGn+1
V3(ON)
V2
V0=Vss
-V2
-V3(ON)
Potential difference between
COM1 and SEGn+1
V3(ON)
V2
V0=Vss
-V2
-V3(ON)
1 frame
1 interval
V0 to V3: Voltage value between the pins for V0 to V3.
475
CHAPTER 20 LCD CONTROLLER/DRIVER
■ LCD Panel Connection Example and Display Data Example (1/2 duty driving type)
Figure 20.6-3 Example of Display Data of LCD Panel
Example) Displaying "5"
SEGn
SEGn + 3
COM1
SEGn + 1
SEGn + 2
COMO
Address COM3 COM2 COM1 COM0
Address COM3 COM2 COM1 COM0
n
H
n+1H
7900H
bit3
bit2
bit1 *1
bit0 *0 SEGn
bit7
bit6
bit5 *3
bit4 *2 SEGn + 1
bit3
bit2
bit1 *5
bit0 *4 SEGn + 2
bit7
bit6
bit5 *7
bit4 *6 SEGn + 3
*0 to *7: Indicates the correspondence with the display RAM.
Bit2, bit3, bit6, and bit7 are not used.
7901H
1
1
SEG0
1
0
SEG1
1
0
SEG2
0
1
SEG3
0: OFF
1: ON
7905H
7904H
7903H
7902H
7901H
1
1
1
1
1
0
1
1
0
1
1
0
1
0
1
1
1
1
0
0
1
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
1
0
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
0
1
SEG11
SEG10
1
1
SEG9
SEG8
1
1
SEG7
SEG6
0
0
SEG5
SEG4
1
1
SEG3
SEG2
1
SEG1
0
SEG0
COM1
1
0
1
1
1
0
0
0
0
0
1
0
0
1
0
1
1
1
1
1
COM2
[Display RAM]
[LCD panel]
476
7900H
1
1
0
1
1
COM0
1
[Segment No.] COM3
[Address]
Example of data corresponding
for 0 to 9
LCD
display bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
CHAPTER 20 LCD CONTROLLER/DRIVER
20.6.2
Output Waveform at LCD Controller/Driver Operation
(1/3 duty)
For 1/3 duty, COM0, COM1, and COM2 are used for display. Neither COM2 nor COM3 is
not used.
■ 1/3 Biases 1/3-duty Output Corrugated Sheet
For display, the crystal elements that have the maximum potential difference between the common and
segment outputs are set ON.
The output waveform when the display RAM contents are the same as Table 20.6-2 is shown in Figure
20.6-4 .
Table 20.6-2 Example of Content of Display RAM
Content of display RAM
Segment
COM3
COM2
COM1
COM0
SEGn
-
1
0
0
SEGn+1
-
1
0
1
-: Unused
477
CHAPTER 20 LCD CONTROLLER/DRIVER
Figure 20.6-4 1/3 Bias, 1/3 Duty Output Waveform Example
COM0
V3
V2
V1
V0=Vss
COM1
V3
V2
V1
V0=Vss
COM2
V3
V2
V1
V0=Vss
V3
V2
V1
V0=Vss
V3
V2
V1
V0=Vss
V3
V2
V1
V0=Vss
COM3
SEGn
SEGn+1
V3(ON)
V2
V1
V0=Vss
-V1
-V2
-V3(ON)
Potential difference between
COM0 and SEGn
V3(ON)
V2
V1
V0=Vss
-V1
-V2
-V3(ON)
Potential difference between
COM1 and SEGn
V3(ON)
V2
V1
V0=Vss
-V1
-V2
-V3(ON)
Potential difference between
COM2 and SEGn
Potential difference between
COM0 and SEGn+1
V3(ON)
V2
V1
V0=Vss
-V1
-V2
-V3(ON)
Potential difference between
COM1 and SEGn+1
V3(ON)
V2
V1
V0=Vss
-V1
-V2
-V3(ON)
Potential difference between
COM2 and SEGn+1
V3(ON)
V2
V1
V0=Vss
-V1
-V2
-V3(ON)
1 frame
1 interval
V0 to V3: Voltage value between the pins for V0 to V3.
478
CHAPTER 20 LCD CONTROLLER/DRIVER
■ LCD Panel Connection Example and Display Data Example (1/3 duty driving type)
Figure 20.6-5 Example of Display Data of LCD Panel
Example) Displaying "5"
COMO
SEGn
COM1
COM2
SEGn + 1
SEGn + 2 Address COM3 COM2 COM1 COM0
7900H
0
0
1
SEG0
Address COM3 COM2 COM1 COM0
n
H
n+1H
bit3
bit2 *2
bit1 *1
bit0 *0 SEGn
bit7
bit6 *5
bit5 *4
bit4 *3 SEGn + 1
bit3
bit2 *8
bit1 *7
bit0 *6 SEGn + 2
7901H
7902H
0
SEG1
0
1
0
SEG2
0
0
1
SEG3
1
1
1
SEG4
0
1
0
SEG5
From bit0
From bit4
0: OFF
1: ON
7904H
1
1
SEG8
0
7903H
1
1
SEG7
1
0
0
SEG6
1
7902H
1
1
SEG5
1
0
0
SEG4
0
7901H
0
0
SEG3
0
1
1
SEG2
1
1
1
SEG1
0
0
1
1
7900H
Example of display data for 0 to 9
LCD
display bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
SEG0
COM1
COM2
[Segment No.] COM3
1
[LCD panel]
[Display RAM]
COM0
[Address]
*0 to *8: Indicates the correspondence with the display RAM.
Bit3, bit7, and *bit2 are not used.
1
Data when starting from bit 4
Data when starting from bit 0
As 2 digits are indicated by 3 bytes in 1/3 duty
operation, two types of data assignment are
allowed: from bit 0/byte 1 and from bit 4/byte 2.
479
CHAPTER 20 LCD CONTROLLER/DRIVER
20.6.3
Output Waveform at LCD Controller/Driver Operation
(1/4 duty)
For 1/4 duty, all of COM0, COM1, COM2, and COM3 are used for display.
■ 1/3 Biases 1/4-duty Output Corrugated Sheet
For display, the crystal elements that have the maximum potential difference between the common and
segment outputs are set ON.
The output waveform when the display RAM contents are the same as Table 20.6-3 is shown in Figure
20.6-6 .
Table 20.6-3 Example of Content of Display RAM
Content of display RAM
Segment
480
COM3
COM2
COM1
COM0
SEGn
0
1
0
0
SEGn+1
0
1
0
1
CHAPTER 20 LCD CONTROLLER/DRIVER
Figure 20.6-6 1/3 Bias, 1/4 Duty Output Waveform Example
V3
V2
V1
V0=Vss
V3
V2
V1
V0=Vss
V3
V2
V1
V0=Vss
COM0
COM1
COM2
V3
V2
V1
V0=Vss
V3
V2
V1
V0=Vss
V3
V2
V1
V0=Vss
COM3
SEGn
SEGn+1
V3(ON)
V2
V1
V0=Vss
-V1
-V2
-V3(ON)
Potential difference between
COM0 and SEGn
Potential difference between
COM1 and SEGn
V3(ON)
V2
V1
V0=Vss
-V1
-V2
-V3(ON)
Potential difference between
COM2 and SEGn
V3(ON)
V2
V1
V0=Vss
-V1
-V2
-V3(ON)
Potential difference between
COM3 and SEGn
V3(ON)
V2
V1
V0=Vss
-V1
-V2
-V3(ON)
Potential difference between
COM0 and SEGn+1
V3(ON)
V2
V1
V0=Vss
-V1
-V2
-V3(ON)
V3(ON)
V2
V1
V0=Vss
-V1
-V2
-V3(ON)
Potential difference between
COM1 and SEGn+1
V3(ON)
V2
V1
V0=Vss
-V1
-V2
-V3(ON)
Potential difference between
COM2 and SEGn+1
V3(ON)
V2
V1
V0=Vss
-V1
-V2
-V3(ON)
Potential difference between
COM3 and SEGn+1
1 frame
1 interval
V0 to V3: Voltage value between the pins for V0 to V3.
481
CHAPTER 20 LCD CONTROLLER/DRIVER
■ LCD Panel Connection Example and Display Data Example (1/4 duty driving type)
Figure 20.6-7 Example of Display Data of LCD Panel
Example) Displaying "5"
COM3 SEGn
COM0
COM1
SEGn + 1
COM2
Address COM3 COM2 COM1 COM0
Address COM3 COM2 COM1 COM0
n
H
bit3
*3
bit2
bit7 *7
*2
*1
bit1
bit6 *6
bit0
bit5 *5
*0
7900H
SEGn
7903H
7902H
7901H
7900H
[Address]
COM0
COM1
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
0: OFF
1: ON
Example of display data for 0 to 9
LCD
display bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
COM2
[Segment No.] COM3
[Display RAM]
[LCD panel]
482
SEG1
bit4 *4 SEGn + 1
*0 to *7: Indicates the correspondence with the display RAM.
SEG0
CHAPTER 21
WATCH CLOCK OUTPUT
This chapter describes the MB90800 series watch clock
output functions and operations.
21.1 Outline of Watch Clock Output
21.2 Configuration of Watch Clock Output Circuit
21.3 Watch Clock Output Control Register (TMCS)
483
CHAPTER 21 WATCH CLOCK OUTPUT
21.1
Outline of Watch Clock Output
The watch clock output circuit divides the oscillation clock by the timebase timer and
generates and outputs the set division clock.
Select from 32/64/128/256 division of the oscillation clock.
■ Watch Clock Output Circuit
The watch clock output circuit is inactive in reset or stop mode. It is active in PLL clock mode, main clock
mode, sleep mode, or sub-clock mode.
Table 21.1-1 Watch Clock Output Enable Mode
PLL clock mode
Main clock mode
Sleep mode
Sub-clock mode
Stop mode
Reset
Operating State
Note:
When the timebase timer is cleared while using the watch clock output circuit, the clock is not
correctly output.
For the timebase timer clear conditions, see "CHAPTER 10 TIMEBASE TIMER".
484
CHAPTER 21 WATCH CLOCK OUTPUT
21.2
Configuration of Watch Clock Output Circuit
The watch clock output circuit consists of the blocks listed below.
• Watch clock select circuit
• Watch clock output control register (TMCS)
■ Block Diagram of the Watch Clock Output Circuit
Figure 21.2-1 Block Diagram of Watch Clock Output Circuit
Watch clock selection circuit
X0
Selector
Watch clock output
Oscillation circuit
X1
Timebase timer
2-division circuit
485
CHAPTER 21 WATCH CLOCK OUTPUT
21.3
Watch Clock Output Control Register (TMCS)
The watch clock output control register (TMCS) is a register used for setting the watch
clock division ratio.
■ Watch Clock Output Control Register (TMCS)
Figure 21.3-1 Watch Clock Output Control Register (TMCS)
15
Address Bit
14
0000AFH
TS1
TS0
0
0
1
1
0
1
0
1
TEN
12
11
10
9
8
Initial value
TEN
TS1
TS0
XXXXX000B
R/W
R/W
R/W
Watch clock division ratio
setting bits
Divided by 32
Divided by 64
Divided by 128
Divided by 256
Output cycle at
HCLK=6.25MHz
Watch clock output enable bit
0
Output disabled
1
Output enabled
R/W : Readable/Writable
: Unused bit
: Initial value
HCLK : Oscillation clock frequency
486
13
5.12us
10.24us
20.48us
40.96us
CHAPTER 21 WATCH CLOCK OUTPUT
Table 21.3-1 Function Description of Each Bit in Watch Clock Output Control Register
(TMCS)
Bit name
Functions
bit15
to
bit11
-:
Undefined
bits
• When reading, this bit is undefined.
• The value to be set affects to operation.
bit10
TEN:
Watch clock
output enable
bit
Watch clock output enable bit. When using this function, be sure to
specify a port with ADER0 and specify the port as output setting in
DDR.
bit9,
bit8
TS1, TS0:
Watch clock
divide ratio
setting bits
By setting TS1 and TS0 and specifying the port as output, the watch
clock can be output.
Note:
The first cycle waveform with TEN output enabled is started asynchronously with the timebase timer;
consequently, it may differ from the output waveform actually set.
Watch clock output control register (TMCS) which the command that operates the read modify write
(RMW) instruction cannot be used.
487
CHAPTER 21 WATCH CLOCK OUTPUT
488
CHAPTER 22
DELAYED INTERRUPT
GENERATION MODULE
This chapter describes the MB90800 series delayed
interrupt generation module functions and operations.
22.1 Overview of Delayed Interrupt Generation Module
22.2 Delay Interruption Factor Generation/release Register (DIRR)
22.3 Operation of Delayed Interrupt Generation Module
22.4 Notes on Use of Delay Interruption Generation Module
489
CHAPTER 22 DELAYED INTERRUPT GENERATION MODULE
22.1
Overview of Delayed Interrupt Generation Module
The delayed interrupt generation module outputs an interrupt request for task
switching. When the delayed interrupt generation module is used, software is allowed to
output and clear task switching interrupts request for the MB90800 series CPU.
■ Block Diagram of Delayed Interrupt Generation Module
Internal data bus
Figure 22.1-1 Block Diagram of Delayed Interrupt Generation Module
490
Delay interrupt factor generation/release decoder
Factor latch
CHAPTER 22 DELAYED INTERRUPT GENERATION MODULE
22.2
Delay Interruption Factor Generation/release Register
(DIRR)
Delay interruption factor generation/release register (DIRR) is explained.
■ Delay Interruption Factor Generation/Release Register (DIRR)
Figure 22.2-1 Delay Interruption Factor Generation/release Register (DIRR)
Address
15
Bit
14
13
12
11
10
9
00009FH
8
RO
Initial value
- - - - - - - 0B
R/W
R/W : Readable/Writable
: Unused bit
Table 22.2-1 Function Description of Each Bit in Delayed Interrupt Cause/Release Register (DIRR)
Bit name
Functions
bit15
to
bit9
-:
Undefined bits
• When reading, this bit is undefined.
• The value to be set affects to operation.
bit8
R0:
Delayed interrupt
request output bit
• Sets generation/release of a delayed interrupt request.
• When "1" is set, outputs a delayed interrupt request.
• When "0" is set, the delay interrupt request is cleared.
• When reset is set, set to the interrupt cause release state (cleared to "0").
491
CHAPTER 22 DELAYED INTERRUPT GENERATION MODULE
22.3
Operation of Delayed Interrupt Generation Module
When "1" is set in the delayed interrupt request output bit (R0) of the delayed interrupt
cause/release register (DIRR) by software, a delayed interrupt request is output to the
interrupt controller.
■ Operation of Delayed Interrupt Generation Module
When "1" is set in the delayed interrupt request output bit (R0) of the delayed interrupt cause/release
register (DIRR) by software, an interrupt request is output to the interrupt controller. When outstanding
interrupt request other than delayed interrupts has a priority level lower than the delayed interrupt or there
are no interrupt requests other than the delayed interrupt, the interrupt controller outputs an interrupt
request to the CPU. CPU compares interrupt level mask register (ILM) in processor status register (PS)
with interrupt request level. When interrupt request level is stronger than interrupt level mask register
(ILM), hardware interrupt processing micro program is activated after completion of executing instruction
and delay interrupt processing routine is carried on. When "0" is set in the delayed interrupt request output
bit (R0) of the delayed interrupt cause/release register (DIRR) by the interrupt processing routine, the
delayed interrupt request cause is cleared and the task is switched.
Figure 22.3-1 Operation of Delayed Interrupt Generation Module
Delay interrupt
generating module
Interrupt controller
write
Other request
IL
ICRyy
CMP
DIRR
ICRxx
CMP
ILM
INTA
DIRR
IL
ILM
CMP
ICR
492
: Delay interrupt factor generating/release register
: Interrupt level setting bit of interrupt control register (ICR)
: Interrupt level mask register in PS
: Comparator
: Interrupt control register
CHAPTER 22 DELAYED INTERRUPT GENERATION MODULE
22.4
Notes on Use of Delay Interruption Generation Module
The precautions for using the delayed interrupt generation module are listed below.
■ Delay Interruption Generation Module Notes on Use
● Delayed interrupt request
When "0" has not been set in the delayed interrupt request output bit (R0) of the delayed interrupt
generation cause/release register (DIRR) after completion of the interrupt processing by the interrupt
processing routine or during execution of the interrupt processing routine, return from the interrupt
processing is disabled.
493
CHAPTER 22 DELAYED INTERRUPT GENERATION MODULE
494
CHAPTER 23
ADDRESS MATCH
DETECTING FUNCTION
This chapter describes the MB90800 series address
match detecting functions and operations.
23.1 Overview of Address Match Detection Function
23.2 Address Match Detection Function
23.3 Operation Explanation of Address Match Detection Function
23.4 Example of Using Address Match Detection Function
495
CHAPTER 23 ADDRESS MATCH DETECTING FUNCTION
23.1
Overview of Address Match Detection Function
When the program address matches the value set in the address match detection
register, the instruction code to be fetched by the CPU is replaced by the INT9
instruction code. By performing processing by the INT#9 interrupt routine, the program
patch function is enabled.
■ Block Diagram of Address Match Detection Function
Internal data bus
Address latch
496
Address detection register
Enable bit
Detection bit
Reset
Set
Comparator
Figure 23.1-1 Block Diagram of Address Match Detection Function
MB90800
series
CPU core
CHAPTER 23 ADDRESS MATCH DETECTING FUNCTION
23.2
Address Match Detection Function
Register list of address match detection function is shown.
■ Register List of Address Match Detection Function
Figure 23.2-1 Register List of Address Match Detection Function
bit23
bit0
PADR0 (Program address detection register upper/middle/lower)
PADR1 (Program address detection register upper/middle/lower)
PACSR (program address
detection control status register)
497
CHAPTER 23 ADDRESS MATCH DETECTING FUNCTION
23.2.1
Program Address Detection Register (PADR0/PADR1)
The program address detection register (PADR0/PADR1) is a register for setting the
address to be compared.
■ Program Address Detection Register (PADR0/PADR1)
Figure 23.2-2 Program Address Detection Register (PADR0/PADR1)
bit23
PADR0
Address
001FF0H
to
001FF2H
bit16 bit15
Upper
Middle
R/W
R/W
bit23
PADR1
Address
001FF3H
to
001FF5H
bit8 bit7
bit16 bit15
bit0
Lower
Initial value
XXXXXXH
R/W
bit8 bit7
bit0
Upper
Middle
Lower
R/W
R/W
R/W
XXXXXXH
R/W : Readable/Writable
X : Undefined
When "1" has been set in the corresponding interrupt enable bit of the program address detection control
status register (PACSR), the program address is compared with the value set in the program address
detection register (PADR0/PADR1). When the program address value (PC value) matches with the value of
the program address detection register (PADR0/PADR1), "1" is set in the interrupt flag bit and an INT9
instruction is output. When "0" has been set in the interrupt enable bit, no INT9 instruction will be output.
The correspondence with the program address detection control status register (PACSR) is as shown below.
498
Address detection register
Interrupt request enable bit
Interrupt request flag bit
PADR0
AD0E
AD0D
PADR1
AD1E
AD1D
CHAPTER 23 ADDRESS MATCH DETECTING FUNCTION
23.2.2
Program Address Detection Control Status Register
(PACSR)
The program address detection control status register (PACSR) controls interrupts
within the address match detection function.
■ Program Address Detection Control Status Register (PACSR)
Figure 23.2-3 Program Address Detection Control Status Register (PACSR)
Address Bit
00009EH
7
6
5
4
Reserved Reserved Reserved Reserved
3
2
1
0
AD1E AD1D AD0E AD0D
R/W
R/W
R/W
Initial value
00000000H
R/W
R/W : Readable/Writable
: Unused bit
Table 23.2-1 Function Description: Program Address Detection Control Status Register (PACSR)
Bit name
Functions
bit7
to
bit4
Reserved:
Reserved bits
Be sure to set this bit to "0".
bit3
AD1E:
PADR1 interrupt
request enable bit
It is a bit by which the interruption of PADR1 is permitted.
When "1" is set, program address detection register (PADR1) is compared to program
address. If program address detection register (PADR1) matches up to program address, "1"
is set to interrupt flag bit of PADR1 (AD1D) and an INT9 instruction is output.
bit2
AD1D:
PADR1 interrupt
request flag bit
It is a flag bit of the interrupt request of PADR1.
When the value of program address detection register (PADR1) and program address
match, "1" is set.
When "1" is set while "1" is set in the request enable bit (AD1E) of PAD0, an INT9
instruction is output.
When "0" is set, cleared to "0".
If "1" is set, the operation is not affected.
bit1
AD0E:
PADR0 interrupt
request enable bit
It is a bit by which the interruption of PADR0 is permitted.
When "1" is set, program address detection register (PADR0) is compared to program
address. If program address detection register (PADR0) matches up to program address, "1"
is set to interrupt flag bit of PADR0 (AD0D) and an INT9 instruction is output.
bit0
AD0D:
PADR0 interrupt
request flag bit
It is a flag bit of the interrupt request of PADR0.
When program address detection register (PADR1) and the comparison of program address
match, "1" is set.
When "1" is set while "1" is set in the request enable bit of PAD0 (AD0E), an INT9
instruction is output.
When "0" is set, cleared to "0".
If "1" is set, the operation is not affected.
499
CHAPTER 23 ADDRESS MATCH DETECTING FUNCTION
23.3
Operation Explanation of Address Match Detection
Function
Operation of Address Match Detection Function is explained.
■ Operation of Address Match Detection Function
If the program address matches the value set in the address detection register, the instruction code to be
fetched by the CPU is replaced by the INT9 instruction code ("01H"); therefore, when the CPU executes the
instruction at the set program address, it executes the INT9 instruction. By performing processing by the
INT#9 interrupt routine, the program patch function is enabled.
There are two program address detection registers (PADR0/PADR1), each register with the interrupt enable
bit (AD1E, AD0E) and interrupt flag bit (AD1D, AD0D). When interrupt enable bit (AD1E, AD0E) is set
to "1", the value set in address detection register is compare to program address. When matching, "1" is set
in interrupt flag bit (AD1D, AD0D) and instruction code read to CPU is replaced to INT9 instruction. The
interrupt flag bit (AD1D, AD0D) is cleared to "0" by setting "0".
Note:
When the program address other than the first byte of the instruction is set in the address detection
register, the address matching detection function does not operate correctly. When changing the
address detection register, set "0" in the interrupt enable bit in advance. Setting the address
detection register while the interrupt enable bit is "1" may cause address detection to be caused in
error while setting.
500
CHAPTER 23 ADDRESS MATCH DETECTING FUNCTION
23.4
Example of Using Address Match Detection Function
Example of using Address Match Detection Function is shown.
■ System Configuration Diagram
Figure 23.4-1 Example of System Configuration
MCU
MB90800
Series
E2PROM
SIN
■ E2PROM Memory Map
Table 23.4-1 E2PROM Memory Map
Address
Explanation
0000H
Patch program No.0 byte number
(There is no program mistake in case of 0.)
0001H
Program address No.0 bit7 to bit0
0002H
Program address No.0 bit15 to bit8
0003H
Program address No.0 bit24 to bit16
0004H
Patch program No.1 byte number
(There is no program mistake in case of 0.)
0005H
Program address No.1 bit7 to bit0
0006H
Program address No.1 bit15 to bit8
0007H
Program address No.1 bit24 to bit16
0010H to
Main body of patch program No.0
■ The Initial State
All bits of E2PROM are "0".
501
CHAPTER 23 ADDRESS MATCH DETECTING FUNCTION
■ INT9 Interrupts
The interrupt routine references the interrupt flag bit (AD1D, AD0D) of the program address detection
control status register (PACSR) to identify the address detection cause that has generated the interrupt
request and then branches to the program that has output the interrupt request.After branching to the
program, information stacked by interrupt is made invalid and the interrupt flag bit (AD1D, AD0D) is
cleared to "0".
Figure 23.4-2 Program Patch Processing Example
FFFFFFH
3
Abnormal program
1
PC= Generated address
ROM
External E2PROM
Register set for
program patch
The number of program byte
Interrupt generating address
Corrected program
Data transmission by using of UART
RAM
2
Corrected program
000000H
502
CHAPTER 23 ADDRESS MATCH DETECTING FUNCTION
Figure 23.4-3 Program Patch Processing Flow
Reset
INT9
Read "0000H" of E2PROM
"0000H"="00H"
"0000H" (E2PROM)
To patch program
JPM 000400H
"0000H"="00H"
Read address
"0001H" to "0003H" (E2PROM)
MOV
PADR0 (MCU)
Patch program execution
"000400H" to "000480H"
Read patch program
"0010H" to "0090H"(E2PROM)
MOV
"000400H" to "000480H"(MCU)
Patch program finish
JMP FF0050H
Enable patch process
MOV PACSR,#02H
Normal program execution
NO
PC=PADR0
YES
INT9
E2PROM
FFFFFFH
ROM
FFFFH
0090H
0010H
0003H
0002H
0001H
0000H
FF8050H
Abnormal program
FF8000H
FF0000H
Patch program
001100H
RAM area
Program address lower: 50H
Program address middle: 80H
Program address lower: FFH
Number of patch program byte: 80H
Stack area
RAM
000480H
000400H
000100H
Patch program
RAM/register area
I/O area
000000H
503
CHAPTER 23 ADDRESS MATCH DETECTING FUNCTION
504
CHAPTER 24
ROM MIRROR FUNCTION
SELECTION MODULE
This chapter describes the MB90800 series ROM mirror
function selection module.
24.1 Overview of ROM Mirror Function Selection Module
24.2 ROM Mirror Function Select Register (ROMM)
505
CHAPTER 24 ROM MIRROR FUNCTION SELECTION MODULE
24.1
Overview of ROM Mirror Function Selection Module
The ROM mirror function selection module can reference the ROM data in bank FF from
bank 00 by setting the register of the ROM function selection module.
Use of the ROM mirror function enables accessing from the target area ("FF8000H" to
"FFFFFFH") to the I/O or RAM area without crossing the bank.
■ Block Diagram of ROM Mirror Function Selection Module
Figure 24.1-1 Block Diagram of ROM Mirror Function Selection Module
Internal data bus
ROM mirror function select register
Address
Address area
FF bank
00 bank
Data
ROM
506
CHAPTER 24 ROM MIRROR FUNCTION SELECTION MODULE
24.2
ROM Mirror Function Select Register (ROMM)
Register of ROM mirror function selection module is explained.
■ ROM Mirror Function Select Register (ROMM)
Figure 24.2-1 ROM Mirroring Function Select Register (ROMM)
Address
Bit
15
14
13
12
11
10
9
00006FH
8
MI
Initial value
XXXXXXX1B
W
W : Write only
X : Undefined
: Unused bit
Note:
When accessing addresses "008000H" to "00FFFFH", do not set the ROM mirror function selection
register.
Table 24.2-1 Functions of ROM Mirror Function Selection Register (ROMM)
Bit name
Functions
bit15
to
bit9
-:
Undefined bits
When read the value, is undefined.
The set value does not influence the operation.
bit8
MI:
ROM mirror function
setting bit
It is a bit by which ROM mirror function is set.
When "1" is set, the ROM data in bank FF can be read out from bank 00.
When "0" is set, the ROM data in bank FF cannot be read out from bank 00.
Note:
As the ROM mirror function references addresses "008000H" to "00FFFFH" from addresses
"FF8000H" to "FFFFFFH", addresses "FF0000H" to "FF7FFFH" cannot be referenced by setting the
ROM mirror function.
MB90803/S
MB90F803/S
MB90F809/S
MB90F804-101/102
MB90V800-101/201
Address 1
FE0000H
FD0000H
FC0000H
FC0000H
Address 2
001100H
F002900H
004100H
007100H
507
CHAPTER 24 ROM MIRROR FUNCTION SELECTION MODULE
Figure 24.2-2 Memory Space
Address
FFFFFFH
FF4000H
ROM area
010000H
004000H
ROM mirror area
ROM area
Address 1
Address 2
000100H
0000C0H
000000H
508
Reference
enable
RAM area
Internal area
I/O area
I/O area
External area
The case of MI=1
The case of MI=0
RAM area
CHAPTER 25
2M-BIT FLASH MEMORY
This chapter describes the MB90800 series 2M-bit Flash
memory functions and operations.
25.1 Overview of 2M-bit Flash Memory
25.2 Registers and Sector Configuration of Flash Memory
25.3 Flash Memory Control Status Register (FMCS)
25.4 Flash Memory Automatic Algorithm Start-up Method
25.5 Details of Programming/Erasing Flash Memory
509
CHAPTER 25 2M-BIT FLASH MEMORY
25.1
Overview of 2M-bit Flash Memory
The 2M-bit Flash memory is allocated in banks "FCH" to "FFH" on the CPU memory
map, allowing read and program accesses from the CPU, similarly to mask ROM, by the
Flash memory interface circuit functions. Flash memory write/erase can be carried out
by an instruction operation from the CPU through the Flash memory interface circuit. It
enables rewriting the mounted on-line Flash memory under control of the CPU, allowing
efficient program and/or data modification.
■ Method of Data Writing/deletion to Flash memory
There are three ways of programming and erasing Flash memory as follows:
• Parallel Writer (MODEL 1890A manufactured by MINATO ELECTRONICS INC.)
• Serial-only Writer (AF220 manufactured by Yokogawa Digital Computer Corporation)
• Programming and erasing by executing program
This section explains "Programming and erasing by executing program ".
■ Features of 2M-bit Flash Memory
• 256K word × 8/128K word × 16 bits
• (64K × 32K × 2 +8K × 2 +1K) Sector configuration
• Uses automatic program algorithm (Embedded Algorithm: the same manner as MBM29F400TA
• Erase pause/restart function
• Detects completion of writing/erasing by CPU interrupts
• Compatible with the JEDEC standard command
• Sector erase function (any combination of sectors)
• 10,000 times of writing/deletion guarantee
■ How to Program and Erase Flash memory
Programming and erasing Flash memory cannot be performed at one time. Flash memory write/erase
operation is enabled by temporarily copying the program in the Flash memory to RAM and then executing
the copied program in the RAM.
For details, see "25.5.2 Writing Data to Flash Memory".
510
CHAPTER 25 2M-BIT FLASH MEMORY
25.2
Registers and Sector Configuration of Flash Memory
Figure 25.2-1 shows the Flash memory control status register (FMCS).
■ Register of Flash Memory
● Flash memory control status register (FMCS)
Figure 25.2-1 Flash memory control status register (FMCS)
Address Bit
0000AEH
7
6
5
INTE RDYINT WE
R/W
R/W
R/W
4
RDY
3
2
1
0
Reserved Reserved Reserved Reserved
R
W
R/W
W
Initial value
00000000B
R/W
R/W : Readable/Writable
R : Read only
W : Write only
■ Sector Configuration
Figure 25.2-2 shows the sector configuration of 2M-bit Flash memory. The upper and lower addresses of
each sector are given in the figure.
Figure 25.2-2 Sector Configuration of 2M-bit Flash Memory
CPU address
Flash memory
High
FFFFFFH
Low
High
FFC000H
FFBFFFH
Low
High
FFA000H
FF9FFFH
Low
High
FF8000H
FF7FFFH
Low
High
FF0000H
FEFFFFH
Low
High
FE0000H
FDFFFFH
Low
High
FD0000H
FCFFFFH
Low
FC0000H
SA6 (16Kbyte)
SA5 (8Kbyte)
SA4 (8Kbyte)
SA3 (32Kbyte)
SA2 (64Kbyte)
SA1 (64Kbyte)
SA0 (64Kbyte)
511
CHAPTER 25 2M-BIT FLASH MEMORY
25.3
Flash Memory Control Status Register (FMCS)
The Flash memory control status register (FMCS) functions are described below.
■ Flash Memory Control Status Register (FMCS)
Figure 25.3-1 Flash Memory Control Status Register (FMCS)
Address Bit
0000AEH
7
6
5
4
INTE RDYINT
WE
RDY
R/W
R/W
R
R/W
3
2
1
0
Reserved Reserved Reserved Reserved
W
R/W
W
Initial value
00000000B
R/W
Reserved bits
Reserved
Be sure to set "0".
RDY
Write/Erase operation executing
1
Write/Erase operation completed (write/erase operation enabled)
WE
Write/Erase operation disabled
1
Write/Erase operation enabled
Write/Erase operations completed flag bit
0
Write/Erase operation executing
1
Write/Erase operation completed (interrupt request generated)
INTE
512
Write/Erase operations enable bit
0
RDYINT
R/W : Readable/Writable
R : Read only
W : Write only
: Initial value
Write/Erase status bit
0
Interrupt request enable bit
0
Disable interrupt at write/erase completion
1
Enable interrupt at write/erase completion
CHAPTER 25 2M-BIT FLASH MEMORY
Table 25.3-1 Function Description of Bits in the Flash Memory Control Status Register (FMCS)
Bit name
Functions
bit7
INTE:
Interrupt
request enable
bit
• Bit used to enable an interrupt request output to the CPU upon completion of the Flash
memory write/erase operation.
• When "1" is set, setting "1" in the RDYINT bit causes an interrupt request to be output.
• When "0" is set, setting "1" in the RDYINT bit does not cause an interrupt request to be
output.
bit6
RDYINT:
Write/Erase
operations
completed flag
bit
• Upon completion of the Flash memory write/erase operation, "1" is set, enabling Flash
memory write/erase operations.
• Cleared to "0" by setting "0", disabling Flash memory write/erase operations.
• If "1" is set, operation is not affected.
For details, see "25.4 Flash Memory Automatic Algorithm Start-up Method". At the end
timing, "1" is also set.
• When using the read modify write (RMW) instruction, "1" is always read out.
bit5
WE:
Write/Erase
operations
enable bit
• When "1" is set, write/erase to Flash memory is enabled after execution of write/erase
command sequence (For details, see "25.4 Flash Memory Automatic Algorithm Start-up
Method").
• When "0" is set, write/erase signal is not generated by executing the FF bank write/erase
command sequence.
• The initial value is "0", disabling the operation. Before starting the Flash memory write/erase
command, be sure to set "1" to enable the operation.
Note:
When performing no write/erase operation, set "0".
bit4
RDY:
Write/Erase
status bit
• While this is cleared to "0", Flash memory write/erase operation is disabled.
• Even while this is cleared to "0", a read/reset command such as sector erase pause is
accepted.
• When writing/the deletion operation is ended, "1" is set.
bit3
to
bit0
Reserved:
Reserved bits
Be sure to set this bit to "0".
513
CHAPTER 25 2M-BIT FLASH MEMORY
Note:
As operating end flag bit (RDYINT) and write/erase status bit (RDY) do not change simultaneously,
the program should be made so that write/erase end is judged by either of operating end flag bit
(RDYINT) or write/erase status bit (RDY).
Automatic algorithm
completion timing
RDYINT bit
RDY bit
1 machine cycle
514
CHAPTER 25 2M-BIT FLASH MEMORY
25.4
Flash Memory Automatic Algorithm Start-up Method
There are four types of commands that start the Flash memory automatic algorithm:
read/reset, write, chip erase, and sector erase. The sector erase command can control
suspension and restart.
■ Command Sequence Table
Table 25.4-1 lists the command sequence table. Though all data written in the command register is one
byte long, set the word access mode. In the word access mode, the higher byte is ignored.
Table 25.4-1 Command Sequence Table
Command
sequence
Bus
First bus cycle
write
access Address
Data
2nd bus cycle
3rd bus cycle
4th bus cycle
5th bus cycle
The 6th bus cycle
Address
Data
Address
Data
Address
Data
Address
Data
Address
Data
-
-
-
-
-
-
-
-
-
-
1
FxXXXXH XXF0H
4
FxAAAAH XXAAH Fx5554H XX55H FxAAAAH XXF0H RA
RD
-
-
-
-
Write program 4
FxAAAAH XXAAH Fx5554H XX55H FxAAAAH XXA0H PA (even)
PD (word)
-
-
-
-
Chip erase
6
FxAAAAH XXAAH Fx5554H XX55H FxAAAAH XX80H FxAAAAH XXAAH
Fx5554H XX55H FxAAAAH XX10H
Sector erase
6
FxAAAAH XXAAH Fx5554H XX55H FxAAAAH XX80H FxAAAAH XXAAH
Fx5554H XX55H SA (even) XX30H
Read/Reset*
Sector Erasing being Suspended
By input of address FXXXXXH data (XXB0H), current sector erasing pauses.
Sector Erase Restart
By input of address FXXXXXH data (XX30H), current sector erasing pauses and then restarts.
*: The two types of read/reset commands can reset the Flash memory to read mode.
Notes:
• Address Fx in the table means the FC to FF. When operating the address, set a value of the bank
to be addressed.
• Addresses in the table are the values in the CPU memory map. X is an any value.
• RA: Read address
• PA writing address, The even number address is specifiable.
• SA: Sector address. For details, see "25.2 Registers and Sector Configuration of Flash Memory".
The even number address is specifiable.
• RD: Read data
• PD: The writing data and the word data are specifiable.
515
CHAPTER 25 2M-BIT FLASH MEMORY
25.5
Details of Programming/Erasing Flash Memory
The procedure for setting a command that starts the automatic algorithm and
performing read/reset, write, chip erase, sector erase, sector erase suspension, or
sector erase restart operation on the Flash memory is described below.
■ Details of Programming/Erasing Flash Memory
When operation of read/rest, writing, chip erase, sector erase, sector erase temporary stop and erase restart
writes to command sequence, automatic algorithm can be activated (For detail, see "23.4 Example of
Using Address Match Detection Function"). Please continue writing from CPU to the Flash memory.
Returns to the read/reset state upon normal completion.
Details of the read/reset, write, chip erase, sector erase, sector erase suspension, and sector erase restart
operations are described in below.
• Make the read/reset state
• Write the data
• All data erasing (chip all erase)
• Any data erasing (sector erase)
• Sector erasing suspension
• Sector erasing resumption
516
CHAPTER 25 2M-BIT FLASH MEMORY
25.5.1
Read/Reset State in Flash Memory
The procedure for executing a read/reset command and making the Flash memory to
read/reset state is described.
■ Read/Reset State in Flash Memory
Read/reset command of command sequence list (see Table 25.4-1 ) is sequentially transferred from CPU to
Flash memory in order to make to read/reset state.
The read/reset command has two command sequences, leading to the same results.
The read/reset state is the initial state of the Flash memory; that is, the Flash memory is always in the read/
reset state immediately after power ON or after normal completion of a command. The read/reset state is
the state waiting for command input.
In the read/reset state, a read access to Flash memory enables data to be read. As with mask ROM, program
access from the CPU is enabled. A read access to Flash memory does not require the read/reset command.
If the command is not terminated normally, use the read/reset command to initialize the automatic
algorithm.
517
CHAPTER 25 2M-BIT FLASH MEMORY
25.5.2
Writing Data to Flash Memory
The procedure for executing a write command and writing data in the Flash memory is
described below. Figure 25.5-1 shows an example of Flash memory writing.
■ Writing Data in Flash Memory
Writing command of command sequence list (see Table 25.4-1 ) is sequentially transferred from CPU to
Flash memory in order to activate the data write automatic algorithm in Flash memory. When data write at
the target address has completed after four cycles, the automatic algorithm is started for automatic writing.
■ How to Specify Address
Writing may be done regardless of the address sequence, even beyond the sector boundaries, but data
written by one write command is one word.
■ Notes on Data Programming
Bit data 0 cannot be returned to bit data 1 by writing. When bit data "1" is written to bit data "0", the data
polling algorithm and toggle operation do not complete, the Flash memory element is assumed to be faulty,
and "1" is assumed to be written in the bit data. When data is read while read/reset, the bit data is "0". To
return the bit data from "0" to "1", perform erase operation.
All commands are ignored during automatic programming. When a hardware reset is started during writing,
data at the write address is not assured.
518
CHAPTER 25 2M-BIT FLASH MEMORY
Figure 25.5-1 Procedure Example for Writing to Flash Memory
Start writing
FMCS: WE (bit5)
Flash memory writing enable
Writing command sequence
1 FXAAAAH XXAAH
2 FX5554H XX55H
3 FXAAAAH XXA0H
4 Writing address writing data
Next address
Writing/delete operating
completion flag bit
0
"0" output is long.
RDYINT
1
NO
Writing error
Last address
YES
FMCS: WE (bit5)
Flash memory write disable
Start writing
519
CHAPTER 25 2M-BIT FLASH MEMORY
25.5.3
Erasing All Data from Flash Memory (Chip Erase)
The procedure for executing a chip erase command and erasing entire Flash memory
data is described below.
■ Erasing Data from Flash Memory (Chip Erase)
Chip erase command of command sequence list (see Table 25.4-1 ) is transferred from CPU to Flash
memory in order to erase all the data from Flash memory.
The chip erase command starts the chip erase operation upon completion of the writing in the 6th cycle.
Chip erase does not require writing in the Flash memory in advance. During automatic erase function
processing, the Flash memory writes "0" for verification before erasing all bit data.
520
CHAPTER 25 2M-BIT FLASH MEMORY
25.5.4
Erasing Any Data in Flash Memory (Sector Erasing)
The procedure for executing a sector erase command and erasing any Flash memory
data (sector erase) is described. Erasing in sector units is enabled and multiple sectors
can be specified at the same time. An example of procedure for Flash memory sector
erase is shown in Figure 25.5-2 .
■ Erasing Any Data in Flash Memory (Sector Erasing)
Sector erase command of command sequence list (see Table 25.4-1 ) is transferred from CPU to Flash
memory in order to erase any sector in Flash memory.
■ How to Specify Sector
The sector erase command starts 50 μs sector erase wait by writing a sector erase code ("30H") at an
arbitrary even address accessible in the target sector in the 6th cycle. To erase multiple sectors,
successively write the erase code ("30H") at the target addresses to be erased.
■ Notes on Specifying Multiple Sectors
Erasing starts upon completion of the 50μs sector erase wait period after writing the last sector erase code.
That is, when erasing more than one sector simultaneously, the address of erase sector and the sector code
(command sequence 6th cycle) must be input within 50 μs. For 50 μs or more, it is not accepted.
521
CHAPTER 25 2M-BIT FLASH MEMORY
Figure 25.5-2 Example of Sector Erasing Procedure
Start deletion
FMCS: WE (bit5)
Flash memory deletion enable
Deletion command sequence
1 FXAAAAH XXAAH
2 FX5554H XX55H
3 FXAAAAH XX80H
4 FXAAAAH XXAAH
5 FX5554H XX55H
6 Erase sector code input (30H)
NO
Writing/delete operating
completion flag bit
0
RDYINT
"0" output is long.
Next address
1
NO
Writing error
Last sector
YES
FMCS: WE (bit5)
Flash memory deletion disable
Start deletion
522
CHAPTER 25 2M-BIT FLASH MEMORY
25.5.5
The Flash Memory Sector Erase Suspension
The procedure for setting a sector erase suspension command and suspending the
Flash memory sector erase is described below. Data can be read from the sector not
being deleted.
■ Sector Erasing Suspension
Sector erase temporary stop command of command sequence list (see Table 25.4-1 ) is transferred from
CPU to Flash memory in order to temporary stop the sector in Flash memory.
The sector erase suspension command can suspend erasing during sector erase and read data from a sector
not being erased. In the sector erase suspension state, reading is enabled, but writing is disabled. The sector
erase suspension command is enabled only during sector erasing including the erase wait time and it is
ignored during chip erase or write operation.
The sector erase suspension command is executed by writing a erase suspension stop code ("B0H"). The
address sets the arbitrary address in the Flash memory. During erase suspension, a erase suspension
command, if executed, is ignored.
When a sector erase suspension command is input during the sector erase wait period, the sector erase
waiting ends, erase operation is aborted, and erase stop state is set. When an erase suspension command is
input during sector erase operation after the sector erase wait period, the erase suspension state is set after a
maximum of 20 μs.
Before issuing a sector erase temporary stop command, wait for 20 μs after issuing the sector erase
command or sector erase resume command.
523
CHAPTER 25 2M-BIT FLASH MEMORY
25.5.6
The Flash Memory Sector Erase Resumption
The procedure for setting the sector erase restart command and restarting the
suspended Flash memory sector erase operation is described below.
■ The Flash Memory Sector Erase Resumption
Sector erase restart command of command sequence list (see Table 25.4-1 ) is transferred from CPU to
Flash memory in order to restart the temporary stopped sector erase in Flash memory.
The sector erase resume command resumes sector erasing suspended by the sector erase suspend command.
The sector erase resume command can be executed by writing of erase restart code ("30H"). The address
sets the arbitrary address in the Flash memory.
Execution of the sector erase restart command during sector erase is ignored.
524
CHAPTER 26
CONNECTION EXAMPLES
FOR SERIAL WRITING
This chapter describes a connection example for serial
write using the AF220 Flash microcontroller programmer
manufactured by Yokogawa Digital Computer
Corporation.
26.1 The Basic Component of Serial Writing Connection
26.2 Example of Connecting Serial Writing (User power supply used)
525
CHAPTER 26 CONNECTION EXAMPLES FOR SERIAL WRITING
26.1
The Basic Component of Serial Writing Connection
The MB90F80x supports the serial on-board programming of Flash ROM (Fujitsu
standard). The MB90F80x specification is explained as follows.
■ The Basic Component of Serial Writing Connection
For FUJITSU Standard serial on-board writing, use AF220 Flash Microcontroller Programmer
manufactured by Yokogawa Digital Computer Corporation.
Host interface cable (AZ201)
General purpose common cable (AZ210)
AF220
RS232C
Flash microcomputer CLK synchronous serial
programer
+
MB90F80x
user system
Memory card
Operation enable with stand alone
Note:
For the AF220 Flash microcontroller programmer functions and operations and the common
connection cable (AZ210) and connectors, contact Yokogawa Digital Computer Corporation.
526
CHAPTER 26 CONNECTION EXAMPLES FOR SERIAL WRITING
Table 26.1-1 Pins Used for Fujitsu Standard Serial On-board Programming
Pin
Function
Functional description
MD2, MD1,
MD0
Mode Pin
Switches to write mode from the Flash microcontroller programmer.
X0, X1
Oscillation pins
As the CPU internal operation clock is set to the PLL single clock mode, the internal
operation clock is set to the oscillation clock frequency. The oscillation clock used
for serial on-board rewriting is 1MHz to 25MHz.
P65, P66
Writing program
start pin
Input a Low level to P65 and high level to P66.
However, P66 cannot be used in MB90F803/S.
RST
Reset pin
SI0
Serial data input
pin
SO0
Serial data output
pin
SC0
Serial clock input
pin
VCC
Supply voltage
pin
When supplying the write voltage (3V + /-10) from the user system, connection with
the Flash microcontroller programmer is not necessary.
When connecting, do not short-circuit with the user power supply.
VSS
GND pin
Share GND with the Flash microcontroller programmer.
UART is used as CLK synchronous mode.
-
When using the P65, SI0, SO0, or SC0 pin in the user system, the control circuit shown in Figure 26.1-1 is
necessary. Isolate the user circuit during serial on-board writing, with the (/TICS) signal of the Flash
microcontroller programmer.
Figure 26.1-1 Control Circuit
MB90F80x
write control pin
AF220 write control pin
10kΩ
AF220
/TICS pin
User circuit
See Sections "26.2 Example of Connecting Serial Writing (User power supply used)" for the four serial
writing connection examples given below.
• Example of connecting cereal writing (User Power Supply Used)
• Serial write connection example (supplying power from writer)
• Example of Minimum Connection to Flash Microcontroller Programmer (User Power Supply Used)
• Example of a minimum connection with Flash microcontroller programmer (supplying power from
writer)
527
CHAPTER 26 CONNECTION EXAMPLES FOR SERIAL WRITING
Table 26.1-2 System Configuration of the Flash Microcontroller Programmer (Made by Yokogawa Digital
Computer Corporation)
Model
Function
AF220
Advanced Flash microcontroller programmer
AF200 ACP
AC adaptor (center) + (option)
AZ201
Host interface cable (RS232C cable for PCAT)
AZ210
Standard target probe (a) length: 1 m
FF001
Control module for Fujitsu F2MC-16LX Flash microcontroller control module
FF001 P2
2MB PC Card (option)
FF001 P4
4MB PC Card (option)
Contact to: Yokogawa Digital Computer Corporation
Tel.:+81-042-333-6224
528
CHAPTER 26 CONNECTION EXAMPLES FOR SERIAL WRITING
26.2
Example of Connecting Serial Writing (User power supply
used)
Four kinds of example of connecting cereal writing is shown.
• Example of connecting cereal writing (User Power Supply Used)
• Serial write connection example (supplying power from writer)
• Example of Minimum Connection to Flash Microcontroller Programmer (User Power
Supply Used)
• Example of a minimum connection with Flash microcontroller programmer (supplying
power from writer)
■ Example of Connecting Serial Writing (User power supply used)
Figure 26.2-1 shows the MB90F80x serial writing connection example (using user power supply). Set the
mode pins to single-chip mode (MD0 = 1, MD1 = 1, MD2 = 0).
529
CHAPTER 26 CONNECTION EXAMPLES FOR SERIAL WRITING
Figure 26.2-1 MB90F80x Serial Writing Connection Example (Using user power supply)
User system
AF220
Flash microcomputer
Connector
programer
DX10-28S
TAUX3
MB90F80x
(19)
MD2
10kΩ
10kΩ
MD1
10kΩ
TMODE
MD0
X0
(12)
1MHz to
16MHz
TAUX
(23)
/TICS
(10)
X1
P65
10kΩ
User
circuit
10kΩ
/TRES
(5)
RST
10kΩ
User
circuit
TTXD
TRXD
TCK
(13)
(27)
(6)
TVcc
(2)
GND
(1,7,
8,14,
15,21,
22,28)
P66
(Cannot be used in MB90F803/S.)
SI0
SO0
SC0
Vcc
User power
supply
Vss
14 pin
3, 4, 9, 11, 16, 17, 18, 20, 24, 25 and 26
pins are OPEN.
1 pin
DX10-28S
28 pin
15 pin
DX10-28S : Write angle type
Pin assignment of connector
(produced by Hirose Electronics)
530
CHAPTER 26 CONNECTION EXAMPLES FOR SERIAL WRITING
• When using the P65, SI0, SO0, or SC0 pin in the user system, the control circuit shown below is
necessary. Isolate the user circuit during serial writing, with the (/TICS) signal of the Flash
microcontroller programmer.
Figure 26.2-2 Control circuit
MB90F80x
write control pin
AF220 write control pin
10kΩ
AF220
/TICS pin
User circuit
• When connecting AF220, set the user circuit power OFF in advance.
531
CHAPTER 26 CONNECTION EXAMPLES FOR SERIAL WRITING
■ Serial Write Connection Example (Supplying power from writer)
Figure 26.2-3 shows the MB90F80x serial writing connection example (using writer power supply). Set the
mode pins to single-chip mode (MD0 = 1, MD1 = 1, MD2 = 0).
Figure 26.2-3 MB90F80x Serial Writing Connection Example (Using writer power supply)
User system
AF220
Flash microcomputer
Connector
programer
DX10-28S
TAUX3
MB90F80x
(19)
MD2
10kΩ
10kΩ
MD1
10kΩ
TMODE
MD0
X0
(12)
1MHz to
16MHz
TAUX
(23)
/TICS
(10)
X1
P65
10kΩ
User
circuit
10kΩ
/TRES
(5)
RST
User
circuit
TTXD
TRXD
TCK
TVcc
Vcc
TVPP1
GND
10kΩ
(13)
(27)
(6)
(16)
(1,7,
8,14,
15,21,
22,28)
P66
(Cannot be used in MB90F803/S.)
SI0
SO0
SC0
User power
supply
Vcc
Vss
14 pin
4, 9, 11, 17, 18, 20, 24, 25 and 26
pins are OPEN.
1 pin
DX10-28S
28 pin
15 pin
DX10-28S : Write angle type
Pin assignment of connector
(produced by Hirose Electronics)
532
CHAPTER 26 CONNECTION EXAMPLES FOR SERIAL WRITING
• When using the P65, SI0, SO0, or SC0 pin in the user system, the control circuit shown below is
necessary. Isolate the user circuit during serial writing, with the (/TICS) signal of the Flash
microcontroller programmer.
Figure 26.2-4 Control Circuit
MB90F80x
write control pin
AF220 write control pin
10kΩ
AF220
/TICS pin
User circuit
• When connecting AF220, set the user circuit power OFF in advance.
• If the power for write is supplied from AF220/AF210/AF120/AF110, do not make a short circuit with
the user power.
533
CHAPTER 26 CONNECTION EXAMPLES FOR SERIAL WRITING
■ Example of Minimum Connection to Flash Microcontroller Programmer (User Power
Supply Used)
Figure 26.2-5 shows the example of minimum connection to Flash microcontroller programmer (when
using user power).
When the pins are set as shown in Figure 26.2-5 for Flash memory writing, connections of MD2, MD1,
MD0, P65, and P66 to the Flash microcontroller programmer are not necessary.
Figure 26.2-5 Example of Minimum Connection to Flash Microcontroller Programmer (when using user power)
AF220
Flash microcomputer
programer
User system
Set "1" to MD2
at serial rewriting.
MB90F80x
10kΩ
MD2
Set "1" to MD1
at serial rewriting.
10kΩ
10kΩ
MD1
10kΩ
10kΩ
MD0
Set "0" to MD0
at serial rewriting.
10kΩ
X0
1MHz to
16MHz
10kΩ
Set "0" to P65
at serial rewriting.
P65
10kΩ
User circuit
P66
Set "1" to P66
(Cannot be used in MB90F803/S.)
at serial rewriting.
User
circuit
Connector
DX10-28S
/TRES
TTXD
TRXD
TCK
TVcc
GND
X1
10kΩ
(5)
RST
(13)
SI0
SO0
SC0
Vcc
(27)
(6)
(2)
(1,7,
8,14,
15,21,
22,28)
User power supply
Vss
14 pin
3, 4, 9, 11, 12, 16, 17, 18, 19, 20, 23,
24, 25 and 26 pins are OPEN.
DX10-28S : Write angle type
1 pin
DX10-28S
15 pin
28 pin
Pin assignment of connector
(produced by Hirose Electronics)
• When connecting AF220, set the user circuit power OFF in advance.
534
CHAPTER 26 CONNECTION EXAMPLES FOR SERIAL WRITING
■ Example of a Minimum Connection with Flash Microcontroller Programmer (Supplying
Power from Writer)
Figure 26.2-6 shows the example of minimum Connection with Flash microcontroller programmer
(supplying power from writer).
When the pins are set as shown in Figure 26.2-6 for Flash memory writing, connections of MD2, MD1,
MD0, P65, and P66 to the Flash microcontroller programmer are not necessary.
Figure 26.2-6 Example of Minimum Connection with Flash Microcontroller Programmer
(Supplying power from writer)
AF220
Flash microcomputer
programer
User system
Set "1" to MD2
at serial rewriting.
MB90F80x
10kΩ
MD2
Set "1" to MD1
at serial rewriting.
10kΩ
10kΩ
10kΩ
10kΩ
MD1
MD0
Set "0" to MD0
at serial rewriting.
10kΩ
X0
1MHz to
16MHz
10kΩ
Set "0" to P65
at serial rewriting.
P65
10kΩ
User circuit
P66
Set "1" to P66
(Cannot be used in MB90F803/S.)
at serial rewriting.
User circuit
Connector
DX10-28S
/TRES
TTXD
TRXD
TCK
TTXD
TRXD
TVcc
GND
X1
10kΩ
(5)
(13)
(27)
(6)
RST
SI0
SO0
SC0
(2)
(3)
(16)
Vcc
(1,7,
8,14,
15,21,
22,28)
User power supply
Vss
14 pin
4, 9, 10, 11, 12, 17, 18, 19, 20, 23,
24, 25 and 26 pins are OPEN.
DX10-28S : Write angle type
1 pin
DX10-28S
15 pin
28 pin
Pin assignment of connector
(produced by Hirose Electronics)
535
CHAPTER 26 CONNECTION EXAMPLES FOR SERIAL WRITING
• When connecting AF220, set the user circuit power OFF in advance.
• If the power for write is supplied from AF220/AF210/AF120/AF110, do not make a short circuit with
the user power.
536
APPENDIX
The appendix describes the memory map and the
instructions used in the F2MC-16LX.
APPENDIX A I/O Map
APPENDIX B Instructions
537
APPENDIX
APPENDIX A I/O Map
Table A-1 shows the addresses allocated to the registers used by the internal peripheral
functions on the MB90800 series.
■ I/O Map
Table A-1 I/O Map (1/8)
Address
Register
abbreviation
Register name
Initial value
Resource
name
Read/
Write
000000H
PDR0
Port 0 data register
XXXXXXXXB
Port 0
R/W
000001H
PDR1
Port 1 data register
XXXXXXXXB
Port 1
R/W
000002H
PDR2
Port 2 data register
XXXXXXXXB
Port 2
R/W
000003H
PDR3
Port 3 data register
XXXXXXXXB
Port 3
R/W
000004H
PDR4
Port 4 data register
XXXXXXXXB
Port 4
R/W
000005H
PDR5
Port 5 data register
XXXXXXXXB
Port 5
R/W
000006H
PDR6
Port 6 data register
XXXXXXXXB
Port 6
R/W
000007H
PDR7
Port 7 data register
-XXXXXXXB
Port 7
R/W
000008H
PDR8
Port 8 data register
---XXXXXB
Port 8
R/W
000009H
PDR9
Port 9 data register
------XXB
Port 9
R/W
00000AH
00000BH
00000CH
The use of the USBP terminal is prohibited.
00000DH
00000EH
00000FH
000010H
DDR0
Port 0 direction register
00000000B
Port 0
R/W
000011H
DDR1
Port 1 direction register
00000000B
Port 1
R/W
000012H
DDR2
Port 2 direction register
00000000B
Port 2
R/W
000013H
DDR3
Port 3 direction register
00000000B
Port 3
R/W
000014H
DDR4
Port 4 direction register
00000000B
Port 4
R/W
000015H
DDR5
Port 5 direction register
00000000B
Port 5
R/W
000016H
DDR6
Port 6 direction register
00000000B
Port 6
R/W
000017H
DDR7
Port 7 direction register
-0000000B
Port 7
R/W
000018H
DDR8
Port 8 direction register
---00000B
Port 8
R/W
000019H
DDR9
Port 9 direction register
------00B
Port 9
R/W
538
APPENDIX A I/O Map
Table A-1 I/O Map (2/8)
Address
Register
abbreviation
Register name
Initial value
Resource
name
Read/
Write
00001AH
00001BH
The use of the USBP terminal is prohibited.
00001CH
00001DH
00001EH
ADER0
Analog input enable 0
11111111B
Port 6, A/D
R/W
00001FH
ADER1
Analog input enable 1
----1111B
Port 7, A/D
R/W
000020H
SMR0
Mode register ch.0
00000-00B
UART0
R/W
000021H
SCR0
Control register ch.0
00000100B
R/W
000022H
SIDR0/
SODR0
Input/output data register ch.0
XXXXXXXXB
R/W
000023H
SSR0
Status register ch.0
00001000B
R/W
000024H
The use of the USBP terminal is prohibited.
000025H
CDCR0
000026H
Communication prescaler control
register ch.0
00--0000B
Prescaler 0
R/W
UART1
R/W
The use of the USBP terminal is prohibited.
000027H
000028H
SMR1
Mode register ch.1
00000-00B
000029H
SCR1
Control register ch.1
00000100B
R/W
00002AH
SIDR1/
SODR1
Input/output data register ch.1
XXXXXXXXB
R/W
00002BH
SSR1
Status register ch.1
00001000B
R/W
00002CH
The use of the USBP terminal is prohibited.
00002DH
CDCR1
00002EH
Communication prescaler control
register ch.1
00--0000B
Prescaler 1
R/W
External
interrupt
R/W
The use of the USBP terminal is prohibited.
00002FH
000030H
ENIR
DTP/interruption permission register
----0000B
000031H
EIRR
DTP/interruption factor register
----XXXXB
000032H
ELVRL
Request level setting resister
00000000B
000033H
The use of the USBP terminal is prohibited.
000034H
ADCS0
A/D control status register o
00------B
000035H
ADCS1
A/D control status register 1
00000000B
R/W, W
000036H
ADCR0
A/D data register (Low)
XXXXXXXXB
R
000037H
ADCR1
A/D data register (High)
00101-XXB
R, W
000038H
The use of the USBP terminal is prohibited.
000039H
ADMR
A/D conversion channel set register
00000000B
R/W
R/W
A/D converter
A/D converter
R/W
R/W
539
APPENDIX
Table A-1 I/O Map (3/8)
Address
00003AH
Register
abbreviation
CPCLR
Register name
Compare clear register
00003BH
00003CH
Initial value
XXXXXXXXB
XXXXXXXXB
TCDT
Timer Data Register
00003DH
Resource
name
16-bit free run
timer
00000000B
Read/
Write
R/W
R/W
00000000B
00003EH
TCCSL
Timer control status register lower
00000000B
R/W
00003FH
TCCSH
Timer control status register higher
0--00000B
R/W
000040H
000041H
The use of the USBP terminal is prohibited.
000042H
000043H
000044H
IPCP0
Input capture data register 0
000045H
000046H
XXXXXXXXB
IPCP1
Input capture data register 1
000047H
000048H
ICS01
Input capture control status 0/1
OCCP0
Output compare register 0
XXXXXXXXB
00000000B
XXXXXXXXB
XXXXXXXXB
OCCP1
Output compare register 1
00004DH
XXXXXXXXB
XXXXXXXXB
00004EH
OCSL
Output compare control status
register lower
0000--00B
00004FH
OCSH
Output compare control status
register higher
---00000B
000050H
TMCSR0L
Timer control status register 0 lower
00000000B
000051H
TMCSR0H
Timer control status register 0
higher
----0000B
000052H
TMR0/
TMRLR0
Timer register 0/reload register 0
XXXXXXXXB
000054H
TMCSR1L
Timer control status register 1 lower
00000000B
000055H
TMCSR1H
Timer control status register 1
higher
----0000B
000056H
TMR1/
TMRLR1
Timer register 1/reload register 1
XXXXXXXXB
000053H
000057H
540
R
R/W
The use of the USBP terminal is prohibited.
00004BH
00004CH
Input
Capture 0/1
XXXXXXXXB
000049H
00004AH
XXXXXXXXB
Output
Compare 0
R/W
Output
Compare 1
R/W
Output
Compare 0/1
R/W
R/W
16-bit reload
timer 0
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
16-bit reload
timer 1
R/W
R/W
R/W
APPENDIX A I/O Map
Table A-1 I/O Map (4/8)
Address
Register
abbreviation
Register name
Initial value
000058H
TMCSR2L
Timer control status register 2 lower
00000000B
000059H
TMCSR2H
Timer control status register 2
higher
----0000B
00005AH
TMR2/
TMRLR2
Timer Register 1/
Reload Register 2
XXXXXXXXB
00005CH
LCRL
LCDC control register lower
00010000B
00005DH
LCRH
LCDC control register higher
00000000B
00005EH
LCRR
LCDC range register
00000000B
00005BH
00005FH
000060H
Resource
name
16-bit reload
timer 2
Read/
Write
R/W
R/W
R/W
XXXXXXXXB
LCD
controller/
driver
R/W
R/W
R/W
The use of the USBP terminal is prohibited.
SMCS0
000061H
Serial mode control status register
(ch.0)
----0000B
00000010B
SIO
(Extended
serial I/O)
R/W
000062H
SDR0
Serial data register (ch.0)
XXXXXXXXB
000063H
SDCR0
Serial I/O prescaler register (ch.0)
0---0000B
Prescaler (SIO)
R/W
000064H
SMCS1
Serial mode control status register
(ch.1)
----0000B
SIO
(Extended
serial I/O)
R/W
000065H
00000010B
000066H
SDR1
Serial shift data register (ch.1)
XXXXXXXXB
000067H
SDCR1
Serial I/O prescaler register (ch.1)
0---0000B
000068H
R/W
R/W
Prescaler (SIO)
R/W
I2C
R
The use of the USBP terminal is prohibited.
000069H
00006AH
IBSR
I2C status register
00000000B
00006BH
IBCR
I2C control register
00000000B
R/W
00006CH
ICCR
I2C clock select register
--0XXXXXB
R/W
00006DH
IADR
I2C address register
-XXXXXXXB
R/W
00006EH
IDAR
I2C data register
XXXXXXXXB
R/W
00006FH
ROMM
ROM mirror function select register
XXXXXXX1B
ROM mirror
W
000070H
PDCRL0
PPG0 down counter register
11111111B
16-bit PPG0
R
000071H
PDCRH0
000072H
PCSRL0
000073H
PCSRH0
000074H
PDUTL0
000075H
PDUTH0
000076H
PCNTL0
000077H
PCNTH0
11111111B
PPG0 cycle set register
XXXXXXXXB
W
XXXXXXXXB
PPG0 duty set register
XXXXXXXXB
W
XXXXXXXXB
PPG0 Control status register
--000000B
R/W
0000000XB
541
APPENDIX
Table A-1 I/O Map (5/8)
Address
Register
abbreviation
000078H
PDCRL1
000079H
PDCRH1
00007AH
PCSRL1
00007BH
PCSRH1
00007CH
PDUTL1
00007DH
PDUTH1
00007EH
PCNTL1
00007FH
PCNTH1
Register name
PPG1 down counter register
Initial value
11111111B
PPG1 cycle set register
XXXXXXXXB
PPG1 duty set register
XXXXXXXXB
W
W
XXXXXXXXB
PPG1 Control status register
--000000B
0000000XB
000082H
000083H
000084H
000085H
000086H
000087H
000088H
000089H
00008AH
(Reserved area)
00008BH
00008CH
00008DH
00008EH
00008FH
000090H
000091H
000092H
000093H
000094H
000095H
542
R
XXXXXXXXB
000081H
000097H
16-bit PPG1
Read/
Write
11111111B
000080H
000096H
Resource
name
The use of the USBP terminal is prohibited.
(Reserved area)
R/W
APPENDIX A I/O Map
Table A-1 I/O Map (6/8)
Address
Register
abbreviation
Register name
Initial value
Resource
name
Read/
Write
000098H
000099H
00009AH
The use of the USBP terminal is prohibited.
00009BH
00009CH
00009DH
00009EH
PACSR
Program address detection control
status register
00000000B
Address match
detecting
function
R/W
00009FH
DIRR
Delay interruption factor generation/
release register
-------0B
Delayed
interrupt
R/W
0000A0H
LPMCR
Low-power Consumption Mode
register
00011000B
R/W
0000A1H
CKSCR
Clock selection register
11111100B
Low-power
consumption
control circuit
R/W
0000A2H
0000A3H
0000A4H
The use of the USBP terminal is prohibited.
0000A5H
0000A6H
0000A7H
0000A8H
WDTC
Watchdog timer control register
X-XXX111B
Watchdog
Timers
R, W
0000A9H
TBTC
Timebase timer control register
1--00100B
Timebase
timer
R/W
0000AAH
WTC
Watch timer control register
10011000B
Watch timer
(Sub clock)
R/W
0000ABH
0000ACH
The use of the USBP terminal is prohibited.
0000ADH
0000AEH
FMCS
Flash control register
00000000B
Flash I/F
R/W
0000AFH
TMCS
Timer clock output control register
XXXXX000B
Clock division
for watch
R/W
543
APPENDIX
Table A-1 I/O Map (7/8)
Address
Register
abbreviation
Register name
Initial value
Resource
name
Read/
Write
0000B0H
ICR00
Interrupt control registers 00
00000111B
R/W
0000B1H
ICR01
Interrupt control registers 01
00000111B
R/W
0000B2H
ICR02
Interrupt control registers 02
00000111B
R/W
0000B3H
ICR03
Interrupt control registers 03
00000111B
R/W
0000B4H
ICR04
Interrupt control registers 04
00000111B
R/W
0000B5H
ICR05
Interrupt control registers 05
00000111B
R/W
0000B6H
ICR06
Interrupt control registers 06
00000111B
R/W
0000B7H
ICR07
Interrupt control registers 07
00000111B
0000B8H
ICR08
Interrupt control registers 08
00000111B
0000B9H
ICR09
Interrupt control registers 09
00000111B
R/W
0000BAH
ICR10
Interrupt control registers 10
00000111B
R/W
0000BBH
ICR11
Interrupt control registers 11
00000111B
R/W
0000BCH
ICR12
Interrupt control registers 12
00000111B
R/W
0000BDH
ICR13
Interrupt control registers 13
00000111B
R/W
0000BEH
ICR14
Interrupt control registers 14
00000111B
R/W
0000BFH
ICR15
Interrupt control registers 15
00000111B
R/W
XXXXXXXXB
R/W
XXXXXXXXB
R/W
001FF0H
001FF1H
PADR0
Program address detection register 0
001FF2H
XXXXXXXXB
001FF3H
XXXXXXXXB
001FF4H
001FF5H
544
PADR1
Program address detection register 1
Interrupt
controller
Address match
detecting
function
R/W
R/W
R/W
R/W
XXXXXXXXB
R/W
XXXXXXXXB
R/W
APPENDIX A I/O Map
Table A-1 I/O Map (8/8)
Address
Register
abbreviation
Register name
Initial value
Resource
name
Read/
Write
VRAM
LCD Display RAM
XXXXXXXXB
LCD
controller/
driver
R/W
007900H
007901H
007902H
007903H
007904H
007905H
007906H
007907H
007908H
007909H
00790AH
00790BH
00790CH
00790DH
00790EH
00790FH
007910H
007911H
007912H
007913H
007914H
007915H
007916H
007917H
● Explanation on read/write
R/W: Readable/Writable
R: Read
W: Write
● Explanation of initial values
0: The initial value is "0".
1: The initial value is "1".
X: The initial value is irregular.
545
APPENDIX
APPENDIX B Instructions
APPENDIX B describes the instructions used by the F2MC-16LX.
B.1 Instruction Types
B.2 Addressing
B.3 Direct Addressing
B.4 Indirect Addressing
B.5 Execution Cycle Count
B.6 Effective address field
B.7 How to Read the Instruction List
B.8 F2MC-16LX Instruction List
B.9 Instruction Map
Code: CM44-00202-3E
546
APPENDIX B Instructions
B.1
Instruction Types
The F2MC-16LX supports 351 types of instructions. Addressing is enabled by using an
effective address field of each instruction or using the instruction code itself.
■ Instruction Types
The F2MC-16LX supports the following 351 types of instructions:
•
41 transfer instructions (byte)
•
38 transfer instructions (word or long word)
•
42 addition/subtraction instructions (byte, word, or long word)
•
12 increment/decrement instructions (byte, word, or long word)
•
11 comparison instructions (byte, word, or long word)
•
11 unsigned multiplication/division instructions (word or long word)
•
11 signed multiplication/division instructions (word or long word)
•
39 logic instructions (byte or word)
•
6 logic instructions (long word)
•
6 sign inversion instructions (byte or word)
•
1 normalization instruction (long word)
•
18 shift instructions (byte, word, or long word)
•
50 branch instructions
•
6 accumulator operation instructions (byte or word)
•
28 other control instructions (byte, word, or long word)
•
21 bit operation instructions
•
10 string instructions
547
APPENDIX
B.2
Addressing
With the F2MC-16LX, the address format is determined by the instruction effective
address field or the instruction code itself (implied). When the address format is
determined by the instruction code itself, specify an address in accordance with the
instruction code used. Some instructions permit the user to select several types of
addressing.
■ Addressing
The F2MC-16LX supports the following 23 types of addressing:
548
•
Immediate (#imm)
•
Register direct
•
Direct branch address (addr16)
•
Physical direct branch address (addr24)
•
I/O direct (io)
•
Abbreviated direct address (dir)
•
Direct address (addr16)
•
I/O direct bit address (io:bp)
•
Abbreviated direct bit address (dir:bp)
•
Direct bit address (addr16:bp)
•
Vector address (#vct)
•
Register indirect (@RWj j = 0 to 3)
•
Register indirect with post increment (@RWj+ j = 0 to 3)
•
Register indirect with displacement (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3)
•
Long register indirect with displacement (@RLi + disp8 i = 0 to 3)
•
Program counter indirect with displacement (@PC + disp16)
•
Register indirect with base index (@RW0 + RW7, @RW1 + RW7)
•
Program counter relative branch address (rel)
•
Register list (rlst)
•
Accumulator indirect (@A)
•
Accumulator indirect branch address (@A)
•
Indirectly-specified branch address (@ear)
•
Indirectly-specified branch address (@eam)
APPENDIX B Instructions
■ Effective Address Field
Table B.2-1 lists the address formats specified by the effective address field.
Table B.2-1 Effective Address Field
Code
Representation
00
R0
RW0
RL0
01
R1
RW1
(RL0)
02
R2
RW2
RL1
03
R3
RW3
(RL1)
04
R4
RW4
RL2
05
R5
RW5
(RL2)
06
R6
RW6
RL3
07
R7
RW7
(RL3)
08
@RW0
09
@RW1
Address format
Default bank
Register direct: Individual parts correspond to the
byte, word, and long word types in order from the
left.
None
DTB
DTB
Register indirect
0A
@RW2
ADB
0B
@RW3
SPB
0C
@RW0+
DTB
0D
@RW1+
DTB
Register indirect with post increment
0E
@RW2+
ADB
0F
@RW3+
SPB
10
@RW0+disp8
DTB
11
@RW1+disp8
DTB
Register indirect with 8-bit displacement
12
@RW2+disp8
ADB
13
@RW3+disp8
SPB
14
@RW4+disp8
DTB
15
@RW5+disp8
DTB
Register indirect with 8-bit displacement
16
@RW6+disp8
ADB
17
@RW7+disp8
SPB
18
@RW0+disp16
DTB
19
@RW1+disp16
DTB
Register indirect with 16-bit displacement
1A
@RW2+disp16
ADB
1B
@RW3+disp16
SPB
1C
@RW0+RW7
Register indirect with index
DTB
1D
@RW1+RW7
Register indirect with index
DTB
1E
@PC+disp16
PC indirect with 16-bit displacement
PCB
1F
addr16
Direct address
DTB
549
APPENDIX
B.3
Direct Addressing
An operand value, register, or address is specified explicitly in direct addressing mode.
■ Direct Addressing
● Immediate addressing (#imm)
Specify an operand value explicitly (#imm4/ #imm8/ #imm16/ #imm32).
Figure B.3-1 Example of Immediate Addressing (#imm)
MOVW A, #01212H (This instruction stores the operand value in A.)
Before execution
A 2233
4455
After execution
A 4455
1 2 1 2 (Some instructions transfer AL to AH.)
● Register direct addressing
Specify a register explicitly as an operand. Table B.3-1 lists the registers that can be specified. Figure B.3-2
shows an example of register direct addressing.
Table B.3-1 Direct Addressing Registers
General-purpose register
Special-purpose register
Byte
R0, R1, R2, R3, R4, R5, R6, R7
Word
RW0, RW1, RW2, RW3, RW4, RW5, RW6,
RW7
Long word
RL0, RL1, RL2, RL3
Accumulator
A, AL
Pointer
SP *
Bank
PCB, DTB, USB, SSB, ADB
Page
DPR
Control
PS, CCR, RP, ILM
*: One of the user stack pointer (USP) and system stack pointer (SSP) is selected and used depending on
the value of the S flag bit in the condition code register (CCR). For branch instructions, the program
counter (PC) is not specified in an instruction operand but is specified implicitly.
550
APPENDIX B Instructions
Figure B.3-2 Example of Register Direct Addressing
MOV R0, A (This instruction transfers the eight low-order bits of A to the generalpurpose register R0.)
Before execution
A 0716
2534
Memory space
R0
After execution
A 0716
2564
??
Memory space
R0
34
● Direct branch addressing (addr16)
Specify an offset explicitly for the branch destination address. The size of the offset is 16 bits, which
indicates the branch destination in the logical address space. Direct branch addressing is used for an
unconditional branch, subroutine call, or software interrupt instruction. Bit23 to bit16 of the address are
specified by the program counter bank register (PCB).
Figure B.3-3 Example of Direct Branch Addressing (addr16)
JMP 3B20H (This instruction causes an unconditional branch by direct branch
addressing in a bank.)
Before execution
After execution
PC 3 C 2 0
PC 3 B 2 0
PCB 4 F
PCB 4 F
Memory space
4F3B20H
Next instruction
4F3C20H
62
4F3C21H
20
4F3C22H
3B
JMP 3B20H
551
APPENDIX
● Physical direct branch addressing (addr24)
Specify an offset explicitly for the branch destination address. The size of the offset is 24 bits. Physical
direct branch addressing is used for unconditional branch, subroutine call, or software interrupt instruction.
Figure B.3-4 Example of Direct Branch Addressing (addr24)
JMPP 333B20H (This instruction causes an unconditional branch by direct branch 24-bit
addressing.)
Before execution
After execution
PC 3 C 2 0
PC 3 B 2 0
PCB 4 F
PCB 3 3
Memory space
333B20H
Next instruction
4F3C20H
63
4F3C21H
20
4F3C22H
3B
4F3C23H
33
JMPP 333B20H
● I/O direct addressing (io)
Specify an 8-bit offset explicitly for the memory address in an operand. The I/O address space in the
physical address space from 000000H to 0000FFH is accessed regardless of the data bank register (DTB)
and direct page register (DPR). A bank select prefix for bank addressing is invalid if specified before an
instruction using I/O direct addressing.
Figure B.3-5 Example of I/O Direct Addressing (io)
MOVW A, I:0C0H (This instruction reads data by I/O direct addressing and stores it in A.)
Before execution
After execution
A 0716
2534
Memory space
0000C0H
EE
0000C1H
FF
A 2534 FFEE
Note : "I:" is Addressing Specifier that shows the I/O Direct Addressing.
552
APPENDIX B Instructions
● Abbreviated direct addressing (dir)
Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are
specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register
(DTB).
Figure B.3-6 Example of Abbreviated Direct Addressing (dir)
MOV S:20H, A (This instruction writes the contents of the eight low-order bits of A in
abbreviated direct addressing mode.)
Before execution
A 4455
DPR 6 6
After execution
A 4455
DPR 6 6
1212
DTB 7 7
Memory space
776620H
1212
DTB 7 7
??
Memory space
776620H
12
Note : "S:" is Addressing Specifier that shows the Abbreviated Direct Addressing.
● Direct addressing (addr16)
Specify the 16 low-order bits of a memory address explicitly in an operand. Address bits 16 to 23 are
specified by the data bank register (DTB). A prefix instruction for access space addressing is invalid for
this mode of addressing.
Figure B.3-7 Example of Direct Addressing (addr16)
MOVW A, 3B20H (This instruction reads data by direct addressing and stores it in A.)
Before execution
After execution
A 2020
A AABB
AABB
0123
DTB 5 5
Memory space
553B21H
01
553B20H
23
DTB 5 5
553
APPENDIX
● I/O direct bit addressing (io:bp)
Specify bits in physical addresses 000000H to 0000FFH explicitly. Bit positions are indicated by ":bp",
where the larger number indicates the most significant bit (MSB) and the lower number indicates the least
significant bit (LSB).
Figure B.3-8 Example of I/O Direct Bit Addressing (io:bp)
SETB I:0C1H:0 (This instruction sets bits by I/O direct bit addressing.)
Memory space
Before execution
0000C1H
00
Memory space
After execution
0000C1H
01
Note : "I:" is Addressing Specifier that shows the I/O Direct Addressing.
● Abbreviated direct bit addressing (dir:bp)
Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are
specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register
(DTB). Bit positions are indicated by ":bp", where the larger number indicates the most significant bit
(MSB) and the lower number indicates the least significant bit (LSB).
Figure B.3-9 Example of Abbreviated Direct Bit Addressing (dir:bp)
SETB S:10H:0 (This instruction sets bits by abbreviated direct bit addressing.)
Memory space
Before execution
DTB 5 5
DPR 6 6
556610H
00
Memory space
After execution
DTB 5 5
DPR 6 6
01
556610H
Note : "S:" is Addressing Specifier that shows the Abbreviated Direct Addressing.
● Direct bit addressing (addr16:bp)
Specify arbitrary bits in 64 kilobytes explicitly. Address bits 16 to 23 are specified by the data bank register
(DTB). Bit positions are indicated by ":bp", where the larger number indicates the most significant bit
(MSB) and the lower number indicates the least significant bit (LSB).
Figure B.3-10 Example of Direct Bit Addressing (addr16:bp)
SETB 2222H : 0 (This instruction sets bits by direct bit addressing.)
Memory space
Before execution
DTB 5 5
552222H
00
Memory space
After execution
554
DTB 5 5
552222H
01
APPENDIX B Instructions
● Vector Addressing (#vct)
Specify vector data in an operand to indicate the branch destination address. There are two sizes for vector
numbers: 4 bits and 8 bits. Vector addressing is used for a subroutine call or software interrupt instruction.
Figure B.3-11 Example of Vector Addressing (#vct)
CALLV #15 (This instruction causes a branch to the address indicated by the interrupt
vector specified in an operand.)
Before execution
PC 0 0 0 0
Memory space
PCB F F
After execution
FFC000H
EF
FFFFE0H
00
FFFFE1H
D0
CALLV #15
PC D 0 0 0
PCB F F
Table B.3-2 CALLV Vector List
Instruction
Vector address L
Vector address H
CALLV #0
XXFFFEH
XXFFFFH
CALLV #1
XXFFFCH
XXFFFDH
CALLV #2
XXFFFAH
XXFFFBH
CALLV #3
XXFFF8H
XXFFF9H
CALLV #4
XXFFF6H
XXFFF7H
CALLV #5
XXFFF4H
XXFFF5H
CALLV #6
XXFFF2H
XXFFF3H
CALLV #7
XXFFF0H
XXFFF1H
CALLV #8
XXFFEEH
XXFFEFH
CALLV #9
XXFFECH
XXFFEDH
CALLV #10
XXFFEAH
XXFFEBH
CALLV #11
XXFFE8H
XXFFE9H
CALLV #12
XXFFE6H
XXFFE7H
CALLV #13
XXFFE4H
XXFFE5H
CALLV #14
XXFFE2H
XXFFE3H
CALLV #15
XXFFE0H
XXFFE1H
Note: A PCB register value is set in XX.
Note:
When the program counter bank register (PCB) is FFH, the vector area overlaps the vector area of
INT #vct8 (#0 to #7). Use vector addressing carefully (see Table B.3-2).
555
APPENDIX
B.4
Indirect Addressing
In indirect addressing mode, an address is specified indirectly by the address data of an
operand.
■ Indirect Addressing
● Register indirect addressing (@RWj j = 0 to 3)
Memory is accessed using the contents of general-purpose register RWj as an address. Address bits 16 to
23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system stack bank register
(SSB) or user stack bank register (USB) when RW3 is used, or additional data bank register (ADB) when
RW2 is used.
Figure B.4-1 Example of Register Indirect Addressing (@RWj j = 0 to 3)
MOVW A, @RW1 (This instruction reads data by register indirect addressing and stores
it in A.)
Before execution
A 0716
2534
Memory space
RW1 D 3 0 F
After execution
DTB 7 8
78D30FH
EE
78D310H
FF
A 2534 FFEE
RW1 D 3 0 F
DTB 7 8
● Register indirect addressing with post increment (@RWj+ j = 0 to 3)
Memory is accessed using the contents of general-purpose register RWj as an address. After operand
operation, RWj is incremented by the operand size (1 for a byte, 2 for a word, or 4 for a long word).
Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system
stack bank register (SSB) or user stack bank register (USB) when RW3 is used, or additional data bank
register (ADB) when RW2 is used.
If the post increment results in the address of the register that specifies the increment, the incremented
value is referenced after that. In this case, if the next instruction is a write instruction, priority is given to
writing by an instruction and, therefore, the register that would be incremented becomes write data.
556
APPENDIX B Instructions
Figure B.4-2 Example of Register Indirect Addressing with Post Increment (@RWj+ j = 0 to 3)
MOVW A, @RW1+ (This instruction reads data by register indirect addressing with post
increment and stores it in A.)
Before execution
A 0716
2534
Memory space
RW1 D 3 0 F
After execution
DTB 7 8
78D30FH
EE
78D310H
FF
A 2534 FFEE
RW1 D 3 1 1
DTB 7 8
● Register indirect addressing with offset (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3)
Memory is accessed using the address obtained by adding an offset to the contents of general-purpose
register RWj. Two types of offset, byte and word offsets, are used. They are added as signed numeric
values. Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0, RW1, RW4, or
RW5 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 or RW7 is
used, or additional data bank register (ADB) when RW2 or RW6 is used.
Figure B.4-3 Example of Register Indirect Addressing with Offset
(@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3)
MOVW A, @RW1+10H (This instruction reads data by register indirect addressing with
an offset and stores it in A.)
Before execution
A 0716
2534
(+10H)
RW1 D 3 0 F
After execution
DTB 7 8
Memory space
78D31FH
EE
78D320H
FF
A 2534 FFEE
RW1 D 3 0 F
DTB 7 8
557
APPENDIX
● Long register indirect addressing with offset (@RLi + disp8 i = 0 to 3)
Memory is accessed using the address that is the 24 low-order bits obtained by adding an offset to the
contents of general-purpose register RLi. The offset is 8-bits long and is added as a signed numeric value.
Figure B.4-4 Example of Long Register Indirect Addressing with Offset (@RLi + disp8 i = 0 to 3)
MOVW A, @RL2+25H (This instruction reads data by long register indirect addressing with
an offset and stores it in A.)
Before execution
A 0716
2534
(+25H)
RL2 F 3 8 2
After execution
4B02
Memory space
824B27H
EE
824B28H
FF
A 2534 FFEE
RL2 F 3 8 2
4B02
● Program counter indirect addressing with offset (@PC + disp16)
Memory is accessed using the address indicated by (instruction address + 4 + disp16). The offset is one
word long. Address bits 16 to 23 are specified by the program counter bank register (PCB). Note that the
operand address of each of the following instructions is not deemed to be (next instruction address +
disp16):
•
DBNZ eam, rel
•
DWBNZ eam, rel
•
CBNE eam, #imm8, rel
•
CWBNE eam, #imm16, rel
•
MOV eam, #imm8
•
MOVW eam, #imm16
Figure B.4-5 Example of Program Counter Indirect Addressing with Offset (@PC + disp16)
MOVW A, @PC+20H (This instruction reads data by program counter indirect
addressing with an offset and stores it in A.)
Before execution
A 0716
2534
Memory space
PCB C 5 PC 4 5 5 6
After execution
A 2534
FFEE
PCB C 5 PC 4 5 5 A
558
+4
C54556H
73
C54557H
9E
C54558H
20
C54559H
00
C5455AH
.
.
.
+20H
C5457AH
EE
C5457BH
FF
MOVW
A, @PC+20H
APPENDIX B Instructions
● Register indirect addressing with base index (@RW0 + RW7, @RW1 + RW7)
Memory is accessed using the address determined by adding RW0 or RW1 to the contents of generalpurpose register RW7. Address bits 16 to 23 are indicated by the data bank register (DTB).
Figure B.4-6 Example of Register Indirect Addressing with Base Index (@RW0 + RW7, @RW1 + RW7)
MOVW A, @RW1+RW7 (This instruction reads data by register indirect addressing with
a base index and stores it in A.)
Before execution
A 0716
RW1 D 3 0 F
WR7 0 1 0 1
After execution
A 2534
RW1 D 3 0 F
2534
+
DTB 7 8
Memory space
78D410H
EE
78D411H
FF
FFEE
DTB 7 8
WR7 0 1 0 1
559
APPENDIX
● Program counter relative branch addressing (rel)
The address of the branch destination is a value determined by adding an 8-bit offset to the program
counter (PC) value. If the result of addition exceeds 16 bits, bank register incrementing or decrementing is
not performed and the excess part is ignored, and therefore the address is contained within a 64-kilobyte
bank. This addressing is used for both conditional and unconditional branch instructions. Address bits 16 to
23 are indicated by the program counter bank register (PCB).
Figure B.4-7 Example of Program Counter Relative Branch Addressing (rel)
BRA 3C32H (This instruction causes an unconditional relative branch.)
Before execution
After execution
PC 3 C 2 0
PC 3 C 3 2
PCB 4 F
PCB 4 F
Memory space
4F3C32H
Next instruction
4F3C21H
10
4F3C20H
60
BRA 3C32H
● Register list (rlst)
Specify a register to be pushed onto or popped from a stack.
Figure B.4-8 Configuration of the Register List
MSB
LSB
RW7 RW6 RW5 RW4 RW3 RW2 RW1 RW0
A register is selected when the corresponding bit is 1 and deselected when the bit is 0.
560
APPENDIX B Instructions
Figure B.4-9 Example of Register List (rlst)
POPW RW0, RW4 (This instruction transfers memory data indicated by the SP to
multiple word registers indicated by the register list.)
SP
34FA
SP
34FE
RW0
×× ××
RW0
02 01
RW1
×× ××
RW1
×× ××
RW2
×× ××
RW2
×× ××
RW3
×× ××
RW3
×× ××
RW4
×× ××
RW4
04 03
RW5
×× ××
RW5
×× ××
RW6
×× ××
RW6
×× ××
RW7
×× ××
RW7
×× ××
Memory space
SP
Memory space
01
34FAH
01
34FAH
02
34FBH
02
34FBH
03
34FCH
03
34FCH
04
34FDH
04
34FDH
34FEH
SP
Before execution
34FEH
After execution
● Accumulator indirect addressing (@A)
Memory is accessed using the address indicated by the contents of the low-order bytes (16 bits) of the
accumulator (AL). Address bits 16 to 23 are specified by a mnemonic in the data bank register (DTB).
Figure B.4-10 Example of Accumulator Indirect Addressing (@A)
MOVW A, @A (This instruction reads data by accumulator indirect addressing and stores it in A.)
Before execution
A
0716
2534
DTB B B
After execution
A
0716
Memory space
BB2534H
EE
BB2535H
FF
FFEE
DTB B B
561
APPENDIX
● Accumulator indirect branch addressing (@A)
The address of the branch destination is the content (16 bits) of the low-order bytes (AL) of the
accumulator. It indicates the branch destination in the bank address space. Address bits 16 to 23 are
specified by the program counter bank register (PCB). For the Jump Context (JCTX) instruction, however,
address bits 16 to 23 are specified by the data bank register (DTB). This addressing is used for
unconditional branch instructions.
Figure B.4-11 Example of Accumulator Indirect Branch Addressing (@A)
JMP @A (This instruction causes an unconditional branch by accumulator indirect
branch addressing.)
Before execution
PC 3 C 2 0
A 6677
After execution
PC 3 B 2 0
A 6677
PCB 4 F
3B20
Memory space
4F3B20H
Next instruction
4F3C20H
61
JMP @A
PCB 4 F
3B20
● Indirect specification branch addressing (@ear)
The address of the branch destination is the word data at the address indicated by ear.
Figure B.4-12 Example of Indirect Specification Branch Addressing (@ear)
JMP @@RW0 (This instruction causes an unconditional branch by register indirect
addressing.)
Before execution
After execution
562
PC 3 C 2 0
PCB 4 F
RW0 7 F 4 8
DTB 2 1
PC 3 B 2 0
PCB 4 F
RW0 7 F 4 8
DTB 2 1
Memory space
217F48H
20
217F49H
3B
4F3B20H
Next instruction
4F3C20H
73
4F3C21H
08
JMP @@RW0
APPENDIX B Instructions
● Indirect specification branch addressing (@eam)
The address of the branch destination is the word data at the address indicated by eam.
Figure B.4-13 Example of Indirect Specification Branch Addressing (@eam)
JMP @RW0 (This instruction causes an unconditional branch by register indirect
addressing.)
Before execution
PC 3 C 2 0
PCB 4 F
RW0 3 B 2 0
After execution
PC 3 B 2 0
PCB 4 F
Memory space
4F3B20H
Next instruction
4F3C20H
73
4F3C21H
00
JMP @RW0
RW0 3 B 2 0
563
APPENDIX
B.5
Execution Cycle Count
The number of cycles required for instruction execution (execution cycle count) is
obtained by adding the number of cycles required for each instruction, "correction
value" determined by the condition, and the number of cycles for instruction fetch.
■ Execution Cycle Count
The number of cycles required for instruction execution (execution cycle count) is obtained by adding the
number of cycles required for each instruction, "correction value" determined by the condition, and the
number of cycles for instruction fetch. In the mode of fetching an instruction from memory such as internal
ROM connected to a 16-bit bus, the program fetches the instruction being executed in word increments.
Therefore, intervening in data access increases the execution cycle count.
Similarly, in the mode of fetching an instruction from memory connected to an 8-bit external bus, the
program fetches every byte of an instruction being executed. Therefore, intervening in data access increases
the execution cycle count. In CPU intermittent operation mode, access to a general-purpose register,
internal ROM, internal RAM, internal I/O, or external data bus causes the clock to the CPU to halt for the
cycle count specified by the CG0 and CG1 bits of the low power consumption mode control register.
Therefore, for the cycle count required for instruction execution in CPU intermittent operation mode, add
the "access count x cycle count for the halt" as a correction value to the normal execution count.
564
APPENDIX B Instructions
■ Calculating the Execution Cycle Count
Table B.5-1 lists execution cycle counts and Table B.5-2 and Table B.5-3 summarize correction value data.
Table B.5-1 Execution Cycle Counts in Each Addressing Mode
(a) *
Code
Operand
00
|
07
Ri
Rwi
RLi
08
|
0B
Execution cycle count in
each addressing mode
Register access count in
each addressing mode
See the instruction list.
See the instruction list.
@RWj
2
1
0C
|
0F
@RWj+
4
2
10
|
17
@RWi+disp8
2
1
18
|
1B
@RWi+disp16
2
1
1C
1D
1E
1F
@RW0+RW7
@RW1+RW7
@PC+disp16
addr16
4
4
2
1
2
2
0
0
*: (a) is used for ~ (cycle count) and B (correction value) in "B.8 F2MC-16LX Instruction List".
565
APPENDIX
Table B.5-2 Cycle Count Correction Values for Counting Execution Cycles
(b) byte *
Operand
(c) word *
(d) long *
Cycle
count
Access
count
Cycle
count
Access
count
Cycle
count
Access
count
Internal register
+0
1
+0
1
+0
2
Internal memory
Even address
+0
1
+0
1
+0
2
Internal memory
Odd address
+0
1
+2
2
+4
4
External data bus
16-bit even address
+1
1
+1
1
+2
2
External data bus
16-bit odd address
+1
1
+4
2
+8
4
External data bus
8-bits
+1
1
+4
2
+8
4
*: (b), (c), and (d) are used for ~ (cycle count) and B (correction value) in "B.8 F2MC-16LX Instruction
List".
Note:
When an external data bus is used, the cycle counts during which an instruction is made to wait by
ready input or automatic ready must also be added.
Table B.5-3 Cycle Count Correction Values for Counting Instruction Fetch Cycles
Instruction
Byte boundary
Word boundary
Internal memory
-
+2
External data bus 16-bits
-
+3
External data bus 8-bits
+3
-
Notes:
• When an external data bus is used, the cycle counts during which an instruction is made to wait
by ready input or automatic ready must also be added.
• Actually, instruction execution is not delayed by every instruction fetch. Therefore, use the
correction values to calculate the worst case.
566
APPENDIX B Instructions
B.6
Effective address field
Table B.6-1 shows the effective address field.
■ Effective Address Field
Table B.6-1 Effective Address Field
Code
Representation
00
01
02
03
04
05
06
07
08
09
0A
R0
R1
R2
R3
R4
R5
R6
R7
@RW0
@RW1
@RW2
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
0B
0C
0D
0E
0F
10
11
12
13
14
15
@RW3
@RW0+
@RW1+
@RW2+
@RW3+
@RW0+disp8
@RW1+disp8
@RW2+disp8
@RW3+disp8
@RW4+disp8
@RW5+disp8
16
17
18
19
1A
1B
1C
1D
1E
1F
@RW6+disp8
@RW7+disp8
@RW0+disp16
@RW1+disp16
@RW2+disp16
@RW3+disp16
@RW0+RW7
@RW1+RW7
@PC+disp16
addr16
RL0
(RL0)
RL1
(RL1)
RL2
(RL2)
RL3
(RL3)
Address format
Byte count of
extended
address part *
Register direct: Individual parts correspond to
the byte, word, and long word types in order
from the left.
-
Register indirect
0
Register indirect with post increment
0
Register indirect with 8-bit displacement
1
Register indirect with 16-bit displacement
2
Register indirect with index
Register indirect with index
PC indirect with 16-bit displacement
Direct address
0
0
2
2
*1: Each byte count of the extended address part applies to + in the # (byte count) column in "B.8 F2MC-16LX
Instruction List".
567
APPENDIX
B.7
How to Read the Instruction List
Table B.7-1 describes the items used in "B.8 F2MC-16LX Instruction List", and Table
B.7-2 describes the symbols used in the same list.
■ Description of Instruction Presentation Items and Symbols
Table B.7-1 Description of Items in the Instruction List (1/2)
Item
Mnemonic
Uppercase, symbol: Represented as is in the assembler.
Lowercase: Rewritten in the assembler.
Number of following lowercase: Indicates bit length in the instruction.
#
Indicates the number of bytes.
~
Indicates the number of cycles.
See Table B.2-1 for the alphabetical letters in items.
RG
B
Operation
568
Description
Indicates the number of times a register access is performed during instruction
execution.
The number is used to calculate the correction value for CPU intermittent
operation.
Indicates the correction value used to calculate the actual number of cycles during
instruction execution.
The actual number of cycles during instruction execution can be determined by
adding the value in the ~ column to this value.
Indicates the instruction operation.
LH
Indicates the special operation for bit15 to bit08 of the accumulator.
Z: Transfers 0.
X: Transfers after sign extension.
-: No transfer
AH
Indicates the special operation for the 16 high-order bits of the accumulator.
*: Transfers from AL to AH.
-: No transfer
Z: Transfers 00 to AH.
X: Transfers 00H or FFH to AH after AL sign extension.
APPENDIX B Instructions
Table B.7-1 Description of Items in the Instruction List (1/2)
Item
Description
I
Each indicates the state of each flag: I (interrupt enable), S (stack), T (sticky bit), N
(negative), Z (zero), V (overflow), C (carry).
*: Changes upon instruction execution.
-: No change
S: Set upon instruction execution.
R: Reset upon instruction execution.
S
T
N
Z
V
C
RMW
Indicates whether the instruction is a Read Modify Write instruction (reading data
from memory by the I instruction and writing the result to memory).
*: Read Modify Write instruction
-: Not Read Modify Write instruction
Note:
Cannot be used for an address that has different meanings between read and
write operations.
Table B.7-2 Explanation on Symbols in the Instruction List (1/2)
Symbol
A
Explanation
The bit length used varies depending on the 32-bit accumulator instruction.
Byte: Low-order 8 bits of byte AL
Word: 16 bits of word AL
Long word: 32 bits of AL and AH
AH
16 high-order bits of A
AL
16 low-order bits of A
SP
Stack pointer (USP or SSP)
PC
Program counter
PCB
Program counter bank register
DTB
Data bank register
ADB
Additional data bank register
SSB
System stack bank register
USB
User stack bank register
SPB
Current stack bank register (SSB or USB)
DPR
Direct page register
brg1
DTB, ADB, SSB, USB, DPR, PCB, SPB
brg2
DTB, ADB, SSB, USB, DPR, SPB
569
APPENDIX
Table B.7-2 Explanation on Symbols in the Instruction List (1/2)
Symbol
Ri
R0, R1, R2, R3, R4, R5, R6, R7
RWi
RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7
RWj
RW0, RW1, RW2, RW3
RLi
RL0, RL1, RL2, RL3
dir
Abbreviated direct addressing
addr16
Direct addressing
addr24
Physical direct addressing
ad24 0-15
Bit0 to bit15 of addr24
ad24 16-23
Bit16 to bit23 of addr24
io
I/O area (000000H to 0000FFH)
#imm4
4-bit immediate data
#imm8
8-bit immediate data
#imm16
16-bit immediate data
#imm32
32-bit immediate data
ext (imm8)
16-bit data obtained by sign extension of 8-bit immediate data
disp8
8-bit displacement
disp16
16-bit displacement
bp
570
Explanation
Bit offset
vct4
Vector number (0 to 15)
vct8
Vector number (0 to 255)
( )b
Bit address
rel
PC relative branch
ear
Effective addressing (code 00H to 07H)
eam
Effective addressing (code 08H to 1FH)
rlst
Register list
APPENDIX B Instructions
B.8
F2MC-16LX Instruction List
Table B.8-1 to Table B.8-18 list the instructions used by the F2MC-16LX.
■ F2MC-16LX Instruction List
Table B.8-1 41 Transfer Instructions (Byte)
Mnemonic
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVN
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
XCH
XCH
XCH
XCH
A,dir
A,addr16
A,Ri
A,ear
A,eam
A,io
A,#imm8
A,@A
A,@RLi+disp8
A,#imm4
A,dir
A,addr16
A,Ri
A,ear
A,eam
A,io
A,#imm8
A,@A
A,@RWi+disp8
A,@RLi+disp8
dir,A
addr16,A
Ri,A
ear,A
eam,A
io,A
@RLi+disp8,A
Ri,ear
Ri,eam
ear,Ri
eam,Ri
Ri,#imm8
io,#imm8
dir,#imm8
ear,#imm8
eam,#imm8
@AL,AH
A,ear
A,eam
Ri,ear
Ri,eam
#
~
RG
B
2
3
1
2
2+
2
2
2
3
1
2
3
2
2
2+
2
2
2
2
3
2
3
1
2
2+
2
3
2
2+
2
2+
2
3
3
3
3+
2
2
2+
2
2+
3
4
2
2
3 + (a)
3
2
3
10
1
3
4
2
2
3 + (a)
3
2
3
5
10
3
4
2
2
3 + (a)
3
10
3
4 + (a)
4
5 + (a)
2
5
5
2
4 + (a)
3
4
5 + (a)
7
9 + (a)
0
0
1
1
0
0
0
0
2
0
0
0
1
1
0
0
0
0
1
2
0
0
1
1
0
0
2
2
1
2
1
1
0
0
1
0
0
2
0
4
2
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
0
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
(b)
(b)
(b)
0
0
(b)
(b)
(b)
0
(b)
0
(b)
0
(b)
(b)
0
(b)
(b)
0
2 × (b)
0
2 × (b)
Operation
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
byte (A) ← ((RLi)+disp8)
byte (A) ← imm4
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
byte (A) ← ((RWi)+disp8)
byte (A) ← ((RLi)+disp8)
byte (dir) ← (A)
byte (addr16) ← (A)
byte (Ri) ← (A)
byte (ear) ← (A)
byte (eam) ← (A)
byte (io) ← (A)
byte ((RLi)+disp8) ← (A)
byte (Ri) ← (ear)
byte (Ri) ← (eam)
byte (ear) ← (Ri)
byte (eam) ← (Ri)
byte (Ri) ← imm8
byte (io) ← imm8
byte (dir) ← imm8
byte (ear) ← imm8
byte (eam) ← imm8
byte ((A)) ← (AH)
byte (A) ↔ (ear)
byte (A) ↔ (eam)
byte (Ri) ↔ (ear)
byte (Ri) ↔ (eam)
LH
AH
I
S
T
N
Z
V
C
RMW
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
X
X
X
X
X
X
X
X
X
X
Z
Z
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
-
*
*
*
*
*
*
*
*
*
R
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
-
Note:
See Table B.5-1 and Table B.5-2 for information on (a) and (b) in the table.
571
APPENDIX
Table B.8-2 38 Transfer Instructions (Word, Long Word)
Mnemonic
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
XCHW
XCHW
XCHW
XCHW
MOVL
MOVL
MOVL
MOVL
MOVL
A,dir
A,addr16
A,SP
A,RWi
A,ear
A,eam
A,io
A,@A
A,#imm16
A,@RWi+disp8
A,@RLi+disp8
dir,A
addr16,A
SP,A
RWi,A
ear,A
eam,A
io,A
@RWi+disp8,A
@RLi+disp8,A
RWi,ear
RWi,eam
ear,RWi
eam,RWi
RWi,#imm16
io,#imm16
ear,#imm16
eam,#imm16
@AL,AH
A,ear
A,eam
RWi, ear
RWi, eam
A,ear
A,eam
A,#imm32
ear,A
eam,A
#
~
RG
B
2
3
1
1
2
2+
2
2
3
2
3
2
3
1
1
2
2+
2
2
3
2
2+
2
2+
3
4
4
4+
2
2
2+
2
2+
2
2+
5
2
2+
3
4
1
2
2
3 + (a)
3
3
2
5
10
3
4
1
2
2
3 + (a)
3
5
10
3
4 + (a)
4
5 + (a)
2
5
2
4 + (a)
3
4
5 + (a)
7
9 + (a)
4
5 + (a)
3
4
5 + (a)
0
0
0
1
1
0
0
0
0
1
2
0
0
0
1
1
0
0
1
2
2
1
2
1
1
0
1
0
0
2
0
4
2
2
0
0
2
0
(c)
(c)
0
0
0
(c)
(c)
(c)
0
(c)
(c)
(c)
(c)
0
0
0
(c)
(c)
(c)
(c)
0
(c)
0
(c)
0
(c)
0
(c)
(c)
0
2 × (c)
0
2 × (c)
0
(d)
0
0
(d)
Operation
word (A) ← (dir)
word (A) ← (addr16)
word (A) ← (SP)
word (A) ← (RWi)
word (A) ← (ear)
word (A) ← (eam)
word (A) ← (io)
word (A) ← ((A))
word (A) ← imm16
word (A) ← ((RWi)+disp8)
word (A) ← ((RLi)+disp8)
word (dir) ← (A)
word (addr16) ← (A)
word (SP) ← (A)
word (RWi) ← (A)
word (ear) ← (A)
word (eam) ← (A)
word (io) ← (A)
word ((RWi)+disp8) ← (A)
word ((RLi)+disp8) ← (A)
word (RWi) ← (ear)
word (RWi) ← (eam)
word (ear) ← (RWi)
word (eam) ← (RWi)
word (RWi) ← imm16
word (io) ← imm16
word (ear) ← imm16
word (eam) ← imm16
word ((A)) ← (AH)
word (A) ↔ (ear)
word (A) ↔ (eam)
word (RWi) ↔ (ear)
word (RWi) ↔ (eam)
long (A) ← (ear)
long (A) ← (eam)
long (A) ← imm32
long (ear) ← (A)
long(eam) ← (A)
LH
AH
I
S
T
N
Z
V
C
RMW
-
*
*
*
*
*
*
*
*
*
*
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
Note:
See Table B.5-1 and Table B.5-2 for information on (a), (c), and (d) in the table.
572
APPENDIX B Instructions
Table B.8-3 42 Addition/Subtraction Instructions (Byte, Word, Long Word)
Mnemonic
#
~
RG
B
ADD
ADD
ADD
ADD
ADD
ADD
ADDC
ADDC
ADDC
ADDDC
A,#imm8
A,dir
A,ear
A,eam
ear,A
eam,A
A
A,ear
A,eam
A
2
2
2
2+
2
2+
1
2
2+
1
2
5
3
4 + (a)
3
5 + (a)
2
3
4 + (a)
3
0
0
1
0
2
0
0
1
0
0
0
(b)
0
(b)
0
2 × (b)
0
0
(b)
0
SUB
SUB
SUB
SUB
SUB
SUB
SUBC
SUBC
SUBC
SUBDC
A,#imm8
A,dir
A,ear
A,eam
ear,A
eam,A
A
A,ear
A,eam
A
2
2
2
2+
2
2+
1
2
2+
1
2
5
3
4 + (a)
3
5 + (a)
2
3
4 + (a)
3
0
0
1
0
2
0
0
1
0
0
0
(b)
0
(b)
0
2 × (b)
0
0
(b)
0
ADDW
ADDW
ADDW
ADDW
ADDW
ADDW
ADDCW
ADDCW
SUBW
SUBW
SUBW
SUBW
SUBW
SUBW
SUBCW
SUBCW
ADDL
ADDL
ADDL
SUBL
SUBL
SUBL
A
A,ear
A,eam
A,#imm16
ear,A
eam,A
A,ear
A,eam
A
A,ear
A,eam
A,#imm16
ear,A
eam,A
A,ear
A,eam
A,ear
A,eam
A,#imm32
A,ear
A,eam
A,#imm32
1
2
2+
3
2
2+
2
2+
1
2
2+
3
2
2+
2
2+
2
2+
5
2
2+
5
2
3
4+(a)
2
3
5+(a)
3
4+(a)
2
3
4+(a)
2
3
5+(a)
3
4+(a)
6
7+(a)
4
6
7+(a)
4
0
1
0
0
2
0
1
0
0
1
0
0
2
0
1
0
2
0
0
2
0
0
0
0
(c)
0
0
2 × (c)
0
(c)
0
0
(c)
0
0
2 × (c)
0
(c)
0
(d)
0
0
(d)
0
Operation
byte (A) ← (A) + imm8
byte (A) ← (A) + (dir)
byte (A) ← (A) + (ear)
byte (A) ← (A) + (eam)
byte (ear) ← (ear) + (A)
byte (eam) ← (eam) + (A)
byte (A) ← (AH) + (AL) + (C)
byte (A) ← (A) + (ear)+ (C)
byte (A) ← (A) + (eam)+ (C)
byte (A) ← (AH) + (AL) + (C)
(decimal)
byte (A) ← (A) - imm8
byte (A) ← (A) - (dir)
byte (A) ← (A) - (ear)
byte (A) ← (A) - (eam)
byte (ear) ← (ear) - (A)
byte (eam) ← (eam) - (A)
byte (A) ← (AH) - (AL) - (C)
byte (A) ← (A) - (ear) - (C)
byte (A) ← (A) - (eam) - (C)
byte (A) ← (AH) - (AL) - (C)
(decimal)
word (A) ← (AH) + (AL)
word (A) ← (A) + (ear)
word (A) ← (A) + (eam)
word (A) ← (A) + imm16
word (ear) ← (ear) + (A)
word (eam) ← (eam) + (A)
word (A) ← (A) + (ear) + (C)
word (A) ← (A) + (eam) + (C)
word (A) ← (AH) - (AL)
word (A) ← (A) - (ear)
word (A) ← (A) - (eam)
word (A) ← (A) - imm16
word (ear) ← (ear) - (A)
word (eam) ← (eam) - (A)
word (A) ← (A) - (ear) - (C)
word (A) ← (A) - (eam) - (C)
long (A) ← (A) + (ear)
long (A) ← (A) + (eam)
long (A) ← (A) + imm32
long (A) ← (A) - (ear)
long (A) ← (A) - (eam)
long (A) ← (A) - imm32
LH
AH
I
S
T
N
Z
V
C
RMW
Z
Z
Z
Z
Z
Z
Z
Z
Z
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
Z
Z
Z
Z
Z
Z
Z
Z
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.
573
APPENDIX
Table B.8-4 12 Increment/decrement Instructions (Byte, Word, Long Word)
Mnemonic
#
~
RG
B
INC
ear
2
3
2
0
INC
eam
2+
5+(a)
0
2 × (b)
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
byte (ear) ← (ear) + 1
-
-
-
-
-
*
*
*
-
-
byte (eam) ← (eam) + 1
-
-
-
-
-
*
*
*
-
*
DEC
ear
2
3
2
0
byte (ear) ← (ear) - 1
-
-
-
-
-
*
*
*
-
-
DEC
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← (eam) - 1
-
-
-
-
-
*
*
*
-
*
INCW
ear
2
3
2
0
word (ear) ← (ear) + 1
-
-
-
-
-
*
*
*
-
-
INCW
eam
2+
5+(a)
0
2 × (c)
word (eam) ← (eam) + 1
-
-
-
-
-
*
*
*
-
*
DECW
ear
2
3
2
0
DECW
eam
2+
5+(a)
0
2 × (c)
INCL
ear
2
7
4
0
INCL
eam
2+
9+(a)
0
2 × (d)
DECL
ear
2
7
4
0
DECL
eam
2+
9+(a)
0
2 × (d)
word (ear) ← (ear) - 1
-
-
-
-
-
*
*
*
-
-
word (eam) ← (eam) - 1
-
-
-
-
-
*
*
*
-
*
long (ear) ← (ear) + 1
-
-
-
-
-
*
*
*
-
-
long (eam) ← (eam) + 1
-
-
-
-
-
*
*
*
-
*
long (ear) ← (ear) - 1
-
-
-
-
-
*
*
*
-
-
long (eam) ← (eam) - 1
-
-
-
-
-
*
*
*
-
*
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.
Table B.8-5 11 Compare Instructions (Byte, Word, Long Word)
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
RMW
CMP
Mnemonic
A
1
1
0
0
byte (AH) - (AL)
Operation
-
-
-
-
-
*
*
*
*
-
CMP
A,ear
2
2
1
0
byte (A) - (ear)
-
-
-
-
-
*
*
*
*
-
CMP
A,eam
2+
3+(a)
0
(b)
byte (A) - (eam)
-
-
-
-
-
*
*
*
*
-
CMP
A,#imm8
2
2
0
0
byte (A) - imm8
-
-
-
-
-
*
*
*
*
-
CMPW
A
1
1
0
0
word (AH) - (AL)
-
-
-
-
-
*
*
*
*
-
CMPW
A,ear
2
2
1
0
word (A) - (ear)
-
-
-
-
-
*
*
*
*
-
CMPW
A,eam
2+
3+(a)
0
(c)
word (A) - (eam)
-
-
-
-
-
*
*
*
*
-
CMPW
A,#imm16
3
2
0
0
word (A) - imm16
-
-
-
-
-
*
*
*
*
-
CMPL
A,ear
2
6
2
0
long (A) - (ear)
-
-
-
-
-
*
*
*
*
-
CMPL
A,eam
2+
7+(a)
0
(d)
long (A) - (eam)
-
-
-
-
-
*
*
*
*
-
CMPL
A,#imm32
5
3
0
0
long (A) - imm32
-
-
-
-
-
*
*
*
*
-
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.
574
APPENDIX B Instructions
Table B.8-6 11 Unsigned Multiplication/Division Instructions (Word, Long Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
DIVU
A
1
*1
0
0
word (AH) / byte (AL)
quotient → byte (AL) remainder → byte (AH)
-
-
-
-
-
-
-
*
*
-
DIVU
A,ear
2
*2
1
0
word (A) / byte (ear)
quotient → byte (A) remainder → byte (ear)
-
-
-
-
-
-
-
*
*
-
DIVU
A,eam
2+
*3
0
*6
word (A) / byte (eam)
quotient → byte (A) remainder → byte (eam)
-
-
-
-
-
-
-
*
*
-
DIVUW
A,ear
2
*4
1
0
long (A) / word (ear)
quotient → word (A) remainder → word (ear)
-
-
-
-
-
-
-
*
*
-
DIVUW
A,eam
2+
*5
0
*7
long (A) / word (eam)
quotient → word (A) remainder → word (eam)
-
-
-
-
-
-
-
*
*
-
MULU
A
1
*8
0
0
byte (AH) * byte (AL) → word (A)
-
-
-
-
-
-
-
-
-
MULU
A,ear
2
*9
1
0
byte (A) * byte (ear) → word (A)
-
-
-
-
-
-
-
-
-
-
MULU
A,eam
2+
*10
0
(b)
byte (A) * byte (eam) → word (A)
-
-
-
-
-
-
-
-
-
-
MULUW
A
1
*11
0
0
word (AH) * word (AL) → Long (A)
-
-
-
-
-
-
-
-
-
MULUW
A,ear
2
*12
1
0
word (A) * word (ear) → Long (A)
-
-
-
-
-
-
-
-
-
-
MULUW
A,eam
2+
*13
0
(c)
word (A) * word (eam) → Long (A)
-
-
-
-
-
-
-
-
-
-
*1: 3: Division by 0 7: Overflow 15: Normal
*2: 4: Division by 0 8: Overflow 16: Normal
*3: 6+(a): Division by 0 9+(a): Overflow 19+(a): Normal
*4: 4: Division by 0 7: Overflow 22: Normal
*5: 6+(a): Division by 0 8+(a): Overflow 26+(a): Normal
*6: (b): Division by 0 or overflow 2 × (b): Normal
*7: (c): Division by 0 or overflow 2 × (c): Normal
*8: 3: Byte (AH) is 0. 7: Byte (AH) is not 0.
*9: 4: Byte (ear) is 0. 8: Byte (ear) is not 0.
*10: 5+(a): Byte (eam) is 0, 9+(a): Byte (eam) is not 0.
*11: 3: Word (AH) is 0. 11: Word (AH) is not 0.
*12: 4: Word (ear) is 0. 12: Word (ear) is not 0.
*13: 5+(a): Word (eam) is 0. 13+(a): Word (eam) is not 0.
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (c) in the table.
575
APPENDIX
Table B.8-7 11 Signed Multiplication/Division Instructions (Word, Long Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
DIV
A
2
*1
0
0
word (AH) / byte (AL)
quotient → byte (AL) remainder → byte (AH)
Z
-
-
-
-
-
-
*
*
-
DIV
A,ear
2
*2
1
0
word (A) / byte (ear)
quotient → byte (A) remainder → byte (ear)
Z
-
-
-
-
-
-
*
*
-
DIV
A,eam
2+
*3
0
*6
word (A) / byte (eam)
quotient → byte (A) remainder → byte (eam)
Z
-
-
-
-
-
-
*
*
-
DIVW
A,ear
2
*4
1
0
long (A) / word (ear)
quotient → word (A) remainder → word (ear)
-
-
-
-
-
-
-
*
*
-
DIVW
A,eam
2+
*5
0
*7
long (A) / word (eam)
quotient → word (A) remainder → word (eam)
-
-
-
-
-
-
-
*
*
-
MUL
A
2
*8
0
0
byte (AH) * byte (AL) → word (A)
-
-
-
-
-
-
-
-
-
-
MUL
A,ear
2
*9
1
0
byte (A) * byte (ear) → word (A)
-
-
-
-
-
-
-
-
-
-
byte (A) * byte (eam) → word (A)
-
-
-
-
-
-
-
-
-
-
word (AH) * word (AL) → Long (A)
-
-
-
-
-
-
-
-
-
-
0
word (A) * word (ear) → Long (A)
-
-
-
-
-
-
-
-
-
-
(c)
word (A) * word (eam) → Long (A)
-
-
-
-
-
-
-
-
-
-
MUL
A,eam
2+
*10
0
(b)
MULW
A
2
*11
0
0
MULW
A,ear
2
*12
1
MULW
A,eam
2+
*13
0
*1:
*2:
*3:
*4:
3: Division by 0, 8 or 18: Overflow, 18: Normal
4: Division by 0, 11 or 22: Overflow, 23: Normal
5+(a): Division by 0, 12+(a) or 23+(a): Overflow, 24+(a): Normal
When dividend is positive; 4: Division by 0, 12 or 30: Overflow, 31: Normal
When dividend is negative; 4: Division by 0, 12 or 31: Overflow, 32: Normal
*5: When dividend is positive; 5+(a): Division by 0, 12+(a) or 31+(a): Overflow, 32+(a): Normal
When dividend is negative; 5+(a): Division by 0, 12+(a) or 32+(a): Overflow, 33+(a): Normal
*6: (b): Division by 0 or overflow, 2 × (b): Normal
*7: (c): Division by 0 or overflow, 2 × (c): Normal
*8: 3: Byte (AH) is 0, 12: result is positive, 13: result is negative
*9: 4: Byte (ear) is 0, 13: result is positive, 14: result is negative
*10: 5+(a): Byte (eam) is 0, 14+(a): result is positive, 15+(a): result is negative
*11: 3: Word (AH) is 0, 16: result is positive, 19: result is negative
*12: 4: Word (ear) is 0, 17: result is positive, 20: result is negative
*13: 5+(a): Word (eam) is 0, 18+(a): result is positive, 21+(a): result is negative
Notes:
• The execution cycle count found when an overflow occurs in a DIV or DIVW instruction may be a
pre-operation count or a post-operation count depending on the detection timing.
• When an overflow occurs with DIV or DIVW instruction, the contents of the AL are destroyed.
• See Table B.5-1 and Table B.5-2 for information on (a) to (c) in the table.
576
APPENDIX B Instructions
Table B.8-8 39 Logic 1 Instructions (Byte, Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
-
AND
A,#imm8
2
2
0
0
byte (A) ← (A) and imm8
-
-
-
-
-
*
*
R
-
AND
A,ear
2
3
1
0
byte (A) ← (A) and (ear)
-
-
-
-
-
*
*
R
-
-
AND
A,eam
2+
4+(a)
0
(b)
byte (A) ← (A) and (eam)
-
-
-
-
-
*
*
R
-
-
byte (ear) ← (ear) and (A)
-
-
-
-
-
*
*
R
-
-
byte (eam) ← (eam) and (A)
-
-
-
-
-
*
*
R
-
*
AND
ear,A
2
3
2
0
AND
eam,A
2+
5+(a)
0
2 × (b)
OR
A,#imm8
2
2
0
0
byte (A) ← (A) or imm8
-
-
-
-
-
*
*
R
-
-
OR
A,ear
2
3
1
0
byte (A) ← (A) or (ear)
-
-
-
-
-
*
*
R
-
-
OR
A,eam
2+
4+(a)
0
(b)
byte (A) ← (A) or (eam)
-
-
-
-
-
*
*
R
-
-
OR
ear,A
2
3
2
0
byte (ear) ← (ear) or (A)
-
-
-
-
-
*
*
R
-
-
OR
eam,A
2+
5+(a)
0
2 × (b)
byte (eam) ← (eam) or (A)
-
-
-
-
-
*
*
R
-
*
XOR
A,#imm8
2
2
0
0
byte (A) ← (A) xor imm8
-
-
-
-
-
*
*
R
-
-
XOR
A,ear
2
3
1
0
byte (A) ← (A) xor (ear)
-
-
-
-
-
*
*
R
-
-
XOR
A,eam
2+
4+(a)
0
(b)
byte (A) ← (A) xor (eam)
-
-
-
-
-
*
*
R
-
-
XOR
ear,A
2
3
2
0
byte (ear) ← (ear) xor (A)
-
-
-
-
-
*
*
R
-
-
XOR
eam,A
2+
5+(a)
0
2 × (b)
byte (eam) ← (eam) xor (A)
-
-
-
-
-
*
*
R
-
*
NOT
A
1
2
0
0
byte (A) ← not (A)
-
-
-
-
-
*
*
R
-
-
NOT
ear
2
3
2
0
byte (ear) ← not (ear)
-
-
-
-
-
*
*
R
-
-
NOT
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← not (eam)
-
-
-
-
-
*
*
R
-
*
ANDW
A
1
2
0
0
word (A) ← (AH) and (A)
-
-
-
-
-
*
*
R
-
-
ANDW
A,#imm16
3
2
0
0
word (A) ← (A) and imm16
-
-
-
-
-
*
*
R
-
-
ANDW
A,ear
2
3
1
0
word (A) ← (A) and (ear)
-
-
-
-
-
*
*
R
-
-
ANDW
A,eam
2+
4+(a)
0
(c)
word (A) ← (A) and (eam)
-
-
-
-
-
*
*
R
-
-
word (ear) ← (ear) and (A)
-
-
-
-
-
*
*
R
-
-
word (eam) ← (eam) and (A)
-
-
-
-
-
*
*
R
-
*
0
word (A) ← (AH) or (A)
-
-
-
-
-
*
*
R
-
-
0
word (A) ← (A) or imm16
-
-
-
-
-
*
*
R
-
-
1
0
word (A) ← (A) or (ear)
-
-
-
-
-
*
*
R
-
-
4+(a)
0
(c)
word (A) ← (A) or (eam)
-
-
-
-
-
*
*
R
-
-
2
3
2
0
word (ear) ← (ear) or (A)
-
-
-
-
-
*
*
R
-
-
eam,A
2+
5+(a)
0
2 × (c)
word (eam) ← (eam) or (A)
-
-
-
-
-
*
*
R
-
*
XORW
A
1
2
0
0
word (A) ← (AH) xor (A)
-
-
-
-
-
*
*
R
-
-
XORW
A,#imm16
3
2
0
0
word (A) ← (A) xor imm16
-
-
-
-
-
*
*
R
-
-
XORW
A,ear
2
3
1
0
word (A) ← (A) xor (ear)
-
-
-
-
-
*
*
R
-
-
ANDW
ear,A
2
3
2
0
ANDW
eam,A
2+
5+(a)
0
2 × (c)
ORW
A
1
2
0
ORW
A,#imm16
3
2
0
ORW
A,ear
2
3
ORW
A,eam
2+
ORW
ear,A
ORW
XORW
A,eam
2+
4+(a)
0
(c)
word (A) ← (A) xor (eam)
-
-
-
-
-
*
*
R
-
XORW
ear,A
2
3
2
0
word (ear) ← (ear) xor (A)
-
-
-
-
-
*
*
R
-
-
XORW
eam,A
2+
5+(a)
0
2 × (c)
word (eam) ← (eam) xor (A)
-
-
-
-
-
*
*
R
-
*
NOTW
A
1
2
0
0
word (A) ← not (A)
-
-
-
-
-
*
*
R
-
-
NOTW
ear
2
3
2
0
word (ear) ← not (ear)
-
-
-
-
-
*
*
R
-
-
NOTW
eam
2+
5+(a)
0
2 × (c)
word (eam) ← not (eam)
-
-
-
-
-
*
*
R
-
*
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (c) in the table.
577
APPENDIX
Table B.8-9 6 Logic 2 Instructions (Long Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
ANDL
A,ear
2
6
2
0
long (A) ← (A) and (ear)
-
-
-
-
-
*
*
R
-
-
ANDL
A,eam
2+
7+(a)
0
(d)
long (A) ← (A) and (eam)
-
-
-
-
-
*
*
R
-
-
ORL
A,ear
2
6
2
0
long (A) ← (A) or (ear)
-
-
-
-
-
*
*
R
-
-
ORL
A,eam
2+
7+(a)
0
(d)
long (A) ← (A) or (eam)
-
-
-
-
-
*
*
R
-
-
XORL
A,ear
2
6
2
0
long (A) ← (A) xor (ear)
-
-
-
-
-
*
*
R
-
-
XORL
A,eam
2+
7+(a)
0
(d)
long (A) ← (A) xor (eam)
-
-
-
-
-
*
*
R
-
-
Note:
See Table B.5-1 and Table B.5-2 for information on (a) and (d) in the table.
Table B.8-10 6 Sign Inversion Instructions (Byte, Word)
Mnemonic
NEG
A
#
~
RG
B
1
2
0
0
byte (A) ← 0 - (A)
byte (ear) ← 0 - (ear)
-
-
-
-
-
*
*
*
*
-
byte (eam) ← 0 - (eam)
-
-
-
-
-
*
*
*
*
*
word (A) ← 0 - (A)
-
-
-
-
-
*
*
*
*
-
NEG
ear
2
3
2
0
NEG
eam
2+
5+(a)
0
2 × (b)
NEGW
A
1
2
0
0
NEGW
ear
2
3
2
0
NEGW
eam
2+
5+(a)
0
2 × (c)
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
X
-
-
-
-
*
*
*
*
-
word (ear) ← 0 - (ear)
-
-
-
-
-
*
*
*
*
-
word (eam) ← 0 - (eam)
-
-
-
-
-
*
*
*
*
*
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (c) in the table.
Table B.8-11 1 Normalization Instruction (Long Word)
Mnemonic
NRML
A,R0
#
~
RG
B
2
*1
1
0
Operation
long (A) ← Shift left to the position where '1' is set
for the first time.
byte (R0) ← Shift count at that time
*1: 4 when all accumulators have a value of 0; otherwise, 6+(R0)
578
LH
AH
I
S
T
N
Z
V
C
RMW
-
-
-
-
-
-
*
-
-
-
APPENDIX B Instructions
Table B.8-12 18 Shift Instructions (Byte, Word, Long Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
RORC
A
2
2
0
0
byte (A) ← Right rotation with carry
-
-
-
-
-
*
*
-
*
-
ROLC
A
2
2
0
0
byte (A) ← Right rotation with carry
-
-
-
-
-
*
*
-
*
-
RORC
ear
2
3
2
0
byte (ear) ← Right rotation with carry
-
-
-
-
-
*
*
-
*
-
RORC
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← Right rotation with carry
-
-
-
-
-
*
*
-
*
*
ROLC
ear
2
3
2
0
byte (ear) ← Left rotation with carry
-
-
-
-
-
*
*
-
*
-
ROLC
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← Left rotation with carry
-
-
-
-
-
*
*
-
*
*
ASR
A,R0
2
*1
1
0
byte (A) ← Arithmetic right shift (A, 1 bit)
-
-
-
-
*
*
*
-
*
-
LSR
A,R0
2
*1
1
0
byte (A) ← Logical right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSL
A,R0
2
*1
1
0
byte (A) ← Logical left barrel shift (A, R0)
-
-
-
-
-
*
*
-
*
-
ASRW
A
1
2
0
0
word (A) ← Arithmetic right shift (A, 1 bit)
-
-
-
-
*
*
*
-
*
-
LSRW
A/SHRW A
1
2
0
0
word (A) ← Logical right shift (A, 1 bit)
-
-
-
-
*
R
*
-
*
-
LSLW
A/SHLW A
1
2
0
0
word (A) ← Logical left shift (A, 1 bit)
-
-
-
-
-
*
*
-
*
-
ASRW
A,R0
2
*1
1
0
word (A) ← Arithmetic right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSRW
A,R0
2
*1
1
0
word (A) ← Logical right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSLW
A,R0
2
*1
1
0
word (A) ← Logical left barrel shift (A, R0)
-
-
-
-
-
*
*
-
*
-
ASRL
A,R0
2
*2
1
0
long (A) ← Arithmetic right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSRL
A,R0
2
*2
1
0
long (A) ← Logical right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSLL
A,R0
2
*2
1
0
long (A) ← Logical left barrel shift (A, R0)
-
-
-
-
-
*
*
-
*
-
*1: 6 when R0 is 0; otherwise, 5 + (R0)
*2: 6 when R0 is 0; otherwise, 6 + (R0)
Note:
See Table B.5-1 and Table B.5-2 for information on (a) and (b) in the table.
579
APPENDIX
Table B.8-13 31 Branch 1 Instructions
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
BZ/BEQ
rel
2
*1
0
0
Branch on (Z) = 1
-
-
-
-
-
-
-
-
-
-
BNZ/
BNE
rel
2
*1
0
0
Branch on (Z) = 0
-
-
-
-
-
-
-
-
-
-
BC/BLO
rel
2
*1
0
0
Branch on (C) = 1
-
-
-
-
-
-
-
-
-
-
BNC/
BHS
rel
2
*1
0
0
Branch on (C) = 0
-
-
-
-
-
-
-
-
-
-
BN
rel
2
*1
0
0
Branch on (N) = 1
-
-
-
-
-
-
-
-
-
-
BP
rel
2
*1
0
0
Branch on (N) = 0
-
-
-
-
-
-
-
-
-
-
BV
rel
2
*1
0
0
Branch on (V) = 1
-
-
-
-
-
-
-
-
-
-
BNV
rel
2
*1
0
0
Branch on (V) = 0
-
-
-
-
-
-
-
-
-
-
BT
rel
2
*1
0
0
Branch on (T) = 1
-
-
-
-
-
-
-
-
-
-
BNT
rel
2
*1
0
0
Branch on (T) = 0
-
-
-
-
-
-
-
-
-
-
BLT
rel
2
*1
0
0
Branch on (V) xor (N) = 1
-
-
-
-
-
-
-
-
-
-
BGE
rel
2
*1
0
0
Branch on (V) xor (N) = 0
-
-
-
-
-
-
-
-
-
-
BLE
rel
2
*1
0
0
Branch on ((V) xor (N)) or (Z) = 1
-
-
-
-
-
-
-
-
-
-
BGT
rel
2
*1
0
0
Branch on ((V) xor (N)) or (Z) = 0
-
-
-
-
-
-
-
-
-
-
BLS
rel
2
*1
0
0
Branch on (C) or (Z) = 1
-
-
-
-
-
-
-
-
-
-
BHI
rel
2
*1
0
0
Branch on (C) or (Z) = 0
-
-
-
-
-
-
-
-
-
-
BRA
rel
2
*1
0
0
Unconditional branch
-
-
-
-
-
-
-
-
-
-
JMP
@A
1
2
0
0
word (PC) ← (A)
-
-
-
-
-
-
-
-
-
-
JMP
addr16
3
3
0
0
word (PC) ← addr16
-
-
-
-
-
-
-
-
-
-
JMP
@ear
2
3
1
0
word (PC) ← (ear)
-
-
-
-
-
-
-
-
-
JMP
@eam
2+
4+(a)
0
(c)
word (PC) ← (eam)
-
-
-
-
-
-
-
-
-
-
JMPP
@ear *3
2
5
2
0
word (PC) ← (ear), (PCB) ← (ear+2)
-
-
-
-
-
-
-
-
-
-
JMPP
@eam *3
2+
6+(a)
0
(d)
JMPP
addr24
4
4
0
0
word (PC) ← (eam), (PCB) ← (eam+2)
-
-
-
-
-
-
-
-
-
-
word (PC) ← ad24 0-15, (PCB) ← ad24 16-23
-
-
-
-
-
-
-
-
-
-
CALL
@ear *4
2
6
1
(c)
word (PC) ← (ear)
-
-
-
-
-
-
-
-
-
-
CALL
@eam *4
2+
7+(a)
0
2 × (c)
word (PC) ← (eam)
-
-
-
-
-
-
-
-
-
-
CALL
addr16 *5
3
6
0
(c)
word (PC) ← addr16
-
-
-
-
-
-
-
-
-
-
CALLV
#vct4 *5
1
7
0
2 × (c)
Vector call instruction
-
-
-
-
-
-
-
-
-
-
CALLP
@ear *6
2
10
2
2 × (c)
word (PC) ← (ear), (PCB) ← (ear+2)
-
-
-
-
-
-
-
-
-
-
CALLP
@eam *6
2+
11+(a)
0
*2
CALLP
addr24 *7
4
10
0
2 × (c)
word (PC) ← (eam), (PCB) ← (eam+2)
-
-
-
-
-
-
-
-
-
-
word (PC) ← ad24 0-15, (PCB) ← ad24 16-23
-
-
-
-
-
-
-
-
-
-
*1: 4 when a branch is made; otherwise, 3
*2: 3 × (c) + (b)
*3: Read (word) of branch destination address
*4: W: Save to stack (word) R: Read (word) of branch destination address
*5: Save to stack (word)
*6: W: Save to stack (long word), R: Read (long word) of branch destination address
*7: Save to stack (long word)
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.
580
APPENDIX B Instructions
Table B.8-14 19 Branch 2 Instructions
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S T N Z V C
RMW
CBNE
A,#imm8,rel
3
*1
0
0
Branch on byte (A) not equal to imm8
-
-
-
-
-
*
*
*
*
-
CWBNE
A,#imm16,rel
4
*1
0
0
Branch on word (A) not equal to imm16
-
-
-
-
-
*
*
*
*
-
CBNE
ear,#imm8,rel
4
*2
1
0
Branch on byte (ear) not equal to imm8
-
-
-
-
-
*
*
*
*
-
CBNE
eam,#imm8,rel *9
4+
*3
0
(b)
Branch on byte (eam) not equal to imm8
-
-
-
-
-
*
*
*
*
-
CWBNE
ear,#imm16,rel
5
*4
1
0
Branch on word (ear) not equal to imm16
-
-
-
-
-
*
*
*
*
-
CWBNE
eam,#imm16,rel*9
5+
*3
0
(c)
Branch on word (eam) not equal to imm16
-
-
-
-
-
*
*
*
*
-
DBNZ
ear,rel
3
*5
2
0
byte (ear) ← (ear) - 1, Branch on (ear) not equal to 0
-
-
-
-
-
*
*
*
-
*
DBNZ
eam,rel
3+
*6
2
DWBNZ
ear,rel
3
*5
2
DWBNZ
eam,rel
3+
*6
2
2 × (b) byte (eam) ← (eam) - 1, Branch on (eam) not equal to 0
-
-
-
-
-
*
*
*
-
-
-
-
-
-
*
*
*
-
-
2 × (c) word (eam) ← (eam) - 1, Branch on (eam) not equal to 0
-
-
-
-
-
*
*
*
-
*
0
word (ear) ← (ear) - 1, Branch on (ear) not equal to 0
INT
#vct8
2
20
0
8 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
INT
addr16
3
16
0
6 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
INTP
addr24
4
17
0
6 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
1
20
0
8 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
INT9
RETI
LINK
#imm8
UNLINK
1
*8
0
*7
Return from interrupt
-
-
*
*
*
*
*
*
*
-
2
6
0
(c)
Saves the old frame pointer in the stack upon entering the
function, then sets the new frame pointer and reserves the
local pointer area.
-
-
-
-
-
-
-
-
-
-
1
5
0
(c)
Recovers the old frame pointer from the stack upon exiting
the function.
-
-
-
-
-
-
-
-
-
-
RET
*10
1
4
0
(c)
Return from subroutine
-
-
-
-
-
-
-
-
-
-
RETP
*11
1
6
0
(d)
Return from subroutine
-
-
-
-
-
-
-
-
-
-
*1: 5 when a branch is made; otherwise, 4
*2: 13 when a branch is made; otherwise, 12
*3: 7+(a) when a branch is made; otherwise, 6+(a)
*4: 8 when a branch is made; otherwise, 7
*5: 7 when a branch is made; otherwise, 6
*6: 8+(a) when a branch is made; otherwise, 7+(a)
*7: 3 × (b) + 2 × (c) when jumping to the next interruption request; 6 × (c) when returning from the current interruption
*8: 15 when jumping to the next interruption request; 17 when returning from the current interruption
*9: Do not use RWj+ addressing mode with a CBNE or CWBNE instruction.
*10: Return from stack (word)
*11: Return from stack (long word)
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.
581
APPENDIX
Table B.8-15 28 Other Control Instructions (Byte, Word, Long Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
PUSHW
A
1
4
0
(c)
word (SP) ← (SP) - 2, ((SP)) ← (A)
-
-
-
-
-
-
-
-
-
-
PUSHW
AH
1
4
0
(c)
word (SP) ← (SP) - 2, ((SP)) ← (AH)
-
-
-
-
-
-
-
-
-
-
PUSHW
PS
1
4
0
(c)
word (SP) ← (SP) - 2, ((SP)) ← (PS)
-
-
-
-
-
-
-
-
-
-
PUSHW
rlst
2
*3
*5
*4
(SP) ← (SP) - 2n, ((SP)) ← (rlst)
-
-
-
-
-
-
-
-
-
-
POPW
A
1
3
0
(c)
word (A) ← ((SP)), (SP) ← (SP) + 2
-
*
-
-
-
-
-
-
-
-
POPW
AH
1
3
0
(c)
word (AH) ← ((SP)), (SP) ← (SP) + 2
-
-
-
-
-
-
-
-
-
-
POPW
PS
1
4
0
(c)
word (PS) ← ((SP)), (SP) ← (SP) + 2
-
-
*
*
*
*
*
*
*
-
POPW
rlst
2
*2
*5
*4
(rlst) ← ((SP)), (SP) ← (SP) + 2n
-
-
-
-
-
-
-
-
-
-
JCTX
@A
1
14
0
6 × (c)
Context switch instruction
-
-
*
*
*
*
*
*
*
-
AND
CCR,#imm8
2
3
0
0
byte (CCR) ← (CCR) and imm8
-
-
*
*
*
*
*
*
*
-
OR
CCR,#imm8
2
3
0
0
byte (CCR) ← (CCR) or imm8
-
-
*
*
*
*
*
*
*
-
MOV
RP,#imm8
2
2
0
0
byte (RP) ← imm8
-
-
-
-
-
-
-
-
-
-
MOV
ILM,#imm8
2
2
0
0
byte (ILM) ← imm8
-
-
-
-
-
-
-
-
-
-
MOVEA
RWi,ear
2
3
1
0
word (RWi) ← ear
-
-
-
-
-
-
-
-
-
-
MOVEA
RWi,eam
2+
2+(a)
1
0
word (RWi) ← eam
-
-
-
-
-
-
-
-
-
-
MOVEA
A,ear
2
1
0
0
word (A) ← ear
-
*
-
-
-
-
-
-
-
-
MOVEA
A,eam
2+
1+(a)
0
0
word (A) ← eam
-
*
-
-
-
-
-
-
-
-
ADDSP
#imm8
2
3
0
0
word (SP) ← (SP) + ext(imm8)
-
-
-
-
-
-
-
-
-
-
ADDSP
#imm16
3
3
0
0
word (SP) ← (SP) + imm16
-
-
-
-
-
-
-
-
-
-
MOV
A,brg1
2
*1
0
0
byte (A) ← (brg1)
Z
*
-
-
-
*
*
-
-
-
MOV
brg2,A
-
2
1
0
0
byte (brg2) ← (A)
-
-
-
-
-
*
*
-
-
NOP
1
1
0
0
No operation
-
-
-
-
-
-
-
-
-
-
ADB
1
1
0
0
Prefix code for AD space access
-
-
-
-
-
-
-
-
-
-
DTB
1
1
0
0
Prefix code for DT space access
-
-
-
-
-
-
-
-
-
-
PCB
1
1
0
0
Prefix code for PC space access
-
-
-
-
-
-
-
-
-
-
SPB
1
1
0
0
Prefix code for SP space access
-
-
-
-
-
-
-
-
-
-
NCC
1
1
0
0
Prefix code for flag no-change
-
-
-
-
-
-
-
-
-
-
CMR
1
1
0
0
Prefix code for common register bank
-
-
-
-
-
-
-
-
-
-
*1: PCB, ADB, SSB, USB, SPB: 1, DTB, DPR: 2
*2: 7 + 3 × (POP count) + 2 × (POP last register number), 7 when RLST = 0 (no transfer register)
*3: 29 + 3 × (PUSH count) - 3 × (PUSH last register number), 8 when RLST = 0 (no transfer register)
*4: (POP count) × (c) or (PUSH count) × (c)
*5: (POP count) or (PUSH count)
Note:
See Table B.5-1 and Table B.5-2 for information on (a) and (c) in the table.
582
APPENDIX B Instructions
Table B.8-16 21 Bit Operand Instructions
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
MOVB
A,dir:bp
3
5
0
(b)
byte (A) ← (dir:bp)b
Z
*
-
-
-
*
*
-
-
-
MOVB
A,addr16:bp
4
5
0
(b)
byte (A) ← (addr16:bp)b
Z
*
-
-
-
*
*
-
-
-
MOVB
A,io:bp
3
4
0
(b)
byte (A) ← (io:bp)b
Z
*
-
-
-
*
*
-
-
-
MOVB
dir:bp,A
3
7
0
2 × (b)
bit (dir:bp)b ← (A)
-
-
-
-
-
*
*
-
-
*
MOVB
addr16:bp,A
4
7
0
2 × (b)
bit (addr16:bp)b ← (A)
-
-
-
-
-
*
*
-
-
*
MOVB
io:bp,A
3
6
0
2 × (b)
bit (io:bp)b ← (A)
-
-
-
-
-
*
*
-
-
*
SETB
dir:bp
3
7
0
2 × (b)
bit (dir:bp)b ← 1
-
-
-
-
-
-
-
-
-
*
SETB
addr16:bp
4
7
0
2 × (b)
bit (addr16:bp)b ← 1
-
-
-
-
-
-
-
-
-
*
SETB
io:bp
3
7
0
2 × (b)
bit (io:bp)b ← 1
-
-
-
-
-
-
-
-
-
*
*
CLRB
dir:bp
3
7
0
2 × (b)
bit (dir:bp)b ← 0
-
-
-
-
-
-
-
-
-
CLRB
addr16:bp
4
7
0
2 × (b)
bit (addr16:bp)b ← 0
-
-
-
-
-
-
-
-
-
*
CLRB
io:bp
3
7
0
2 × (b)
bit (io:bp)b ← 0
-
-
-
-
-
-
-
-
-
*
BBC
dir:bp,rel
4
*1
0
(b)
Branch on (dir:bp) b = 0
-
-
-
-
-
-
*
-
-
-
BBC
addr16:bp,rel
5
*1
0
(b)
Branch on (addr16:bp) b = 0
-
-
-
-
-
-
*
-
-
-
BBC
io:bp,rel
4
*2
0
(b)
Branch on (io:bp) b = 0
-
-
-
-
-
-
*
-
-
-
BBS
dir:bp,rel
4
*1
0
(b)
Branch on (dir:bp) b = 1
-
-
-
-
-
-
*
-
-
-
BBS
addr16:bp,rel
5
*1
0
(b)
Branch on (addr16:bp) b = 1
-
-
-
-
-
-
*
-
-
-
BBS
io:bp,rel
4
*2
0
(b)
SBBS
addr16:bp,rel
5
*3
0
2 × (b)
Branch on (io:bp) b = 1
-
-
-
-
-
-
*
-
-
-
Branch on (addr16:bp) b = 1,
bit (addr16:bp) b ← 1
-
-
-
-
-
-
*
-
-
*
WBTS
io:bp
3
*4
0
WBTC
io:bp
3
*4
0
*5
Waits until (io:bp) b = 1
-
-
-
-
-
-
-
-
-
-
*5
Waits until (io:bp) b = 0
-
-
-
-
-
-
-
-
-
-
RMW
*1: 8 when a branch is made; otherwise, 7
*2: 7 when a branch is made; otherwise, 6
*3: 10 when the condition is met; otherwise, 9
*4: Undefined count
*5: Until the condition is met
Note:
See Table B.5-1 and Table B.5-2 for information on (b) in the table.
Table B.8-17 6 Accumulator Operation Instructions (Byte, Word)
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
SWAP
Mnemonic
1
3
0
0
byte (A)0-7 ↔ (A)8-15
Operation
-
-
-
-
-
-
-
-
-
-
SWAPW
1
2
0
0
word (AH) ↔ (AL)
-
*
-
-
-
-
-
-
-
-
EXT
1
1
0
0
Byte sign extension
X
-
-
-
-
*
*
-
-
-
EXTW
1
2
0
0
Word sign extension
-
X
-
-
-
*
*
-
-
-
ZEXT
1
1
0
0
Byte zero extension
Z
-
-
-
-
R
*
-
-
-
ZEXTW
1
1
0
0
Word zero extension
-
Z
-
-
-
R
*
-
-
-
583
APPENDIX
Table B.8-18 10 String Instructions
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
-
MOVS / MOVSI
2
*2
*5
*3
byte transfer @AH+ ← @AL+, counter = RW0
-
-
-
-
-
-
-
-
-
MOVSD
2
*2
*5
*3
byte transfer @AH- ← @AL-, counter = RW0
-
-
-
-
-
-
-
-
-
-
SCEQ / SCEQI
2
*1
*8
*4
byte search @AH+ ← AL, counter = RW0
-
-
-
-
-
*
*
*
*
-
SCEQD
2
*1
*8
*4
byte search @AH- ← AL, counter = RW0
-
-
-
-
-
*
*
*
*
FILS / FILSI
2
6m+6
*8
*3
byte fill @AH+ ← AL, counter = RW0
-
-
-
-
-
*
*
-
-
-
MOVSW / MOVSWI
2
*2
*5
*6
word transfer @AH+ ← @AL+, counter = RW0
-
-
-
-
-
-
-
-
-
-
MOVSWD
2
*2
*5
*6
word transfer @AH- ← @AL-, counter = RW0
-
-
-
-
-
-
-
-
-
-
SCWEQ / SCWEQI
2
*1
*8
*7
word search @AH+ - AL, counter = RW0
-
-
-
-
-
*
*
*
*
-
SCWEQD
2
*1
*8
*7
word search @AH- - AL, counter = RW0
-
-
-
-
-
*
*
*
*
-
FILSW / FILSWI
2
6m+6
*8
*6
word fill @AH+ ← AL, counter = RW0
-
-
-
-
-
*
*
-
-
-
*1: 5 when RW0 is 0, 4 + 7 × (RW0) when the counter expires, or 7n + 5 when a match occurs
*2: 5 when RW0 is 0; otherwise, 4 + 8 × (RW0)
*3: (b) × (RW0) + (b) × (RW0) When the source and destination access different areas, calculate the (b) item individually.
*4: (b) × n
*5: 2 × (b) × (RW0)
*6: (c) × (RW0) + (c) × (RW0) When the source and destination access different areas, calculate the (c) item individually.
*7: (c) × n
*8: (b) × (RW0)
Note:
m: RW0 value (counter value), n: Loop count
See Table B.5-1 and Table B.5-2 for information on (b) and (c) in the table.
584
APPENDIX B Instructions
B.9
Instruction Map
Each F2MC-16LX instruction code consists of 1 or 2 bytes. Therefore, the instruction
map consists of multiple pages. Table B.9-2 to Table B.9-21 summarize the F2MC-16LX
instruction map.
■ Structure of Instruction Map
Figure B.9-1 Structure of Instruction Map
Basic page map
Bit operation
instructions
Character string
operation
instructions
2-byte
instructions
: Byte 1
ea instructions × 9 : Byte 2
An instruction such as the NOP instruction that ends in one byte is completed within the basic page. An
instruction such as the MOVS instruction that requires two bytes recognizes the existence of byte 2 when it
references byte 1, and can check the following one byte by referencing the map for byte 2. Figure B.9-2
shows the correspondence between an actual instruction code and instruction map.
585
APPENDIX
Figure B.9-2 Correspondence between Actual Instruction Code and Instruction Map
Some instructions do
not contain byte 2.
Instruction
code
Length varies
depending on the
instruction.
Byte 1
Byte 2
Operand
Operand
...
[Basic page map]
XY
+Z
[Extended page map]*
UV
+W
*: The extended page map is a generic name of maps for bit operation instructions, character
string operation instructions, 2-byte instructions, and ea instructions. Actually, there are
multiple extended page maps for each type of instructions.
An example of an instruction code is shown in Table B.9-1.
Table B.9-1 Example of an Instruction Code
Byte 1
(from basic page map)
Byte 2
(from extended page map)
NOP
00 +0=00
-
AND A, #8
30 +4=34
-
MOV A, ADB
60 +F=6F
00 +0=00
CBNE @RW2+d8, #8, rel
70 +0=70
F0 +2=F2
Instruction
586
+F
+E
+D
+C
+B
+A
+9
+8
+7
+6
+5
+4
+3
+2
+1
+0
A
ZEXT
SWAP
ADDSP
DTB
ADB
SPB
#8
A, #8
dir, A
A, dir
io, A
A, io
JMP
BRA
60
MULU
DIVU
ea
@A instruction 2
A
MOVW
MOVX
RET
SP, A A, addr16
A0
B0
C0
ea
instruction 8
D0
E0
F0
rel
LSRW
ASRW
LSLW
SWAPW
ZEXTW
XORW
ORW
ANDW
ORW
PUSHW
POPW
A, #16
AH
AH
MOVW
ea, RWi
Bit operation MOV
A instruction
ea, Ri
MOVW
RWi, ea
PUSHW
POPW
2-byte
XCHW
A
rlst
rlst instruction
RWi, ea
Character
XORW
PUSHW
POPW
XCH
operation
A
A, #16
PS
PS string
Ri, ea
instruction
A
ANDW
PUSHW
POPW
A
A, #16
A
CMPW
MOVL
MOVW
RETI
A, #16
A, #32 addr16, A
ADDSP
MULUW
NOTW
A
#16
A
A
A
EXTW
A
BHI
BLS
BGT
BLE
rel
rel
rel
rel
rel
BGE
CMPL
CMPW
A, #32
NEGW
A
rel
BLT
rel
rel
rel
rel
rel
MOV
MOV
CBNE A, CWBNE A, MOVW
MOVW
INTP
MOV
RP, #8
ILM, #8
#8, rel
#16, rel
A, #16 A,addr16
addr24
Ri, ea
BT
BNV
BV
BP
BN
BNC/BHS
rel
BC/BLO
BNZ/BNE
rel
rel
ADDW
MOVW
MOVW
INT
ea
MOVW
MOVW
MOVW
MOVW A, MOVW
A, #16
A, dir
A, io
#vct8 instruction 9
A, RWi
RWi, A RWi, #16 @RWi+d8 @RWi+d8, A
NOT
ea
instruction 7
MOVX
MOVX
CALLP
ea
A, dir
A, io
addr24 instruction 6
MOVW
MOVW
RETP
A, #8
A, SP
io, #16
A, #8
90
BNT
SUBL
SUBW
A, #32
A
A
A
XOR
OR
OR
CCR, #8
80
ea
MOV
MOV
MOV
MOVX
MOVX A, MOVN
CALL
BZ/BEQ
rel instruction 1
A, Ri
Ri, A
Ri, #8
A, Ri @RWi+d8
A, #4
#vct4
rel
70
MOV
JMP
ea
A, addr16
addr16 instruction 3
MOV
MOV
50
MOVX
MOV
JMPP
ea
A, #8
A, #8 addr16, A
addr24 instruction 4
MOV
MOV
MOV
40
SUBW
MOVW
MOVW
INT
MOVEA
A
A, #16
dir, A
io, A
addr16
RWi, ea
UNLINK
A
CMP
A
A, #8
A, #8
SUBC
SUB
ADD
30
AND
AND
MOV
MOV
CALL
ea
CCR, #8
A, #8
dir, #8
io, #8
addr16 instruction 5
CMP
A
A, dir
A, dir
ADDC
SUB
ADD
20
LINK
ADDL
ADDW
#imm8
A, #32
EXT
@A
PCB
A
JCTX
SUBDC
ADDDC
NEG
NCC
INT9
A
CMR
10
NOP
00
APPENDIX B Instructions
Table B.9-2 Basic Page Map
587
588
+F
+E
+D
+C
+B
+A
+9
+8
+7
+6
+5
+4
+3
+2
+1
+0
10
MOVB
io:bp, A
20
30
CLRB
io:bp
40
50
SETB
io:bp
60
70
BBC
io;bp, rel
80
90
BBS
io:bp, rel
A0
B0
MOVB
MOVB A, MOVB
MOVB
CLRB
CLRB
SETB
SETB
BBC
BBC
BBS
BBS
A, dir:bp addr16:bp
dir:bp, A addr16:bp,A
dir:bp addr16:bp
dir:bp addr16:bp dir:bp, rel addr16:bp,rel dir:bp, rel addr16:bp,rel
MOVB
A, io:bp
00
WBTS
io:bp
C0
D0
WBTC
io:bp
E0
SBBS
addr16:bp
F0
APPENDIX
Table B.9-3 Bit Operation Instruction Map (First Byte = 6CH)
MOVSI
MOVSD
PCB, PCB
PCB, DTB
PCB, ADB
PCB, SPB
DTB, PCB
DTB, DTB
DTB, ADB
DTB, SPB
ADB, PCB
ADB, DTB
ADB, ADB
ADB, SPB
SPB, PCB
SPB, DTB
SPB, ADB
SPB, SPB
+1
+2
+3
+4
+5
+6
+7
+8
+9
+A
+B
+C
+D
+E
+F
10
+0
00
MOVSWI
20
MOVSWD
30
40
50
60
70
90
A0
B0
C0
SPB
ADB
DTB
SPB
ADB
DTB
SPB
ADB
DTB
SPB
ADB
DTB
SPB
ADB
DTB
SCEQI
SCEQD
SCWEQI SCWEQD FILSI
PCB
PCB
PCB
PCB
PCB
80
D0
SPB
ADB
DTB
FILSWI
PCB
E0
F0
APPENDIX B Instructions
Table B.9-4 Character String Operation Instruction Map (First Byte = 6EH)
589
590
LSLW
LSLL
LSL
MOVW
MOVW
A, R0
A, R0
A, R0 @RL2+d8, A A, @RL2+d8
MOVW
MOVW
NRML
A, @A @AL, AH
A, R0
ASRW
ASRL
ASR
MOVW
MOVW
A, R0
A, R0
A, R0 @RL3+d8, A A, @RL3+d8
LSRW
LSRL
LSR
A, R0
A, R0
A, R0
+D
+E
+F
MOVW
MOVW
@RL1+d8, A A, @RL1+d8
MOVW
MOVW
@RL0+d8, A A, @RL0+d8
+C
+B
+A
+9
+8
A
MOV
MOV
MOVX
MOV
MOV
A, PCB
A, @A A, @RL3+d8 @RL3+d8, A A, @RL3+d8
+6
ROLC
MOV
MOV
A, @A @AL, AH
+5
A
MOV
MOV
MOVX
MOV
MOV
A, DPR
DPR, A A, @RL2+d8 @RL2+d8, A A, @RL2+d8
+4
ROLC
MOV
MOV
A, USB
USB, A
+3
+7
MOV
MOV
MOVX
MOV
MOV
A, SSB
SSB, A A, @RL1+d8 @RL1+d8, A A, @RL1+d8
+2
40
MOV
MOV
A, ADB
ADB, A
30
+1
20
MOV
MOV
MOVX
MOV
MOV
A, DTB
DTB, A A, @RL0+d8 @RL0+d8, A A, @RL0+d8
10
+0
00
50
60
DIV
MULW
MUL
70
A
A
A
80
90
A0
B0
C0
D0
E0
F0
APPENDIX
Table B.9-5 2-byte Instruction Map (First Byte = 6FH)
50
90
B0
D0
@RW1, @RW1+d16 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A,
#16, rel
#16, rel A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
@RW2, @RW2+d16 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A,
#16, rel
#16, rel A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
@RW3, @RW3+d16 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A,
#16, rel
#16, rel A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
SUBL
SUBL A,
A, RL2 @RW5+d8
SUBL
SUBL A,
A, RL3 @RW6+d8
SUBL
SUBL A,
A, RL3 @RW7+d8
ADDL
ADDL A,
A, RL2 @RW5+d8
ADDL
ADDL A,
A, RL3 @RW6+d8
ADDL
ADDL A,
A, RL3 @RW7+d8
ADDL
ADDL A, SUBL
SUBL A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
ADDL
ADDL A, SUBL
SUBL A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
ADDL
ADDL A, SUBL
SUBL A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
ADDL
ADDL A, SUBL
SUBL A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
ADDL
ADDL A, SUBL
SUBL A, Use
@RW0+RW7 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A, Use
@RW0+RW7,
A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 prohibited
#16, rel A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 prohibited
#8, rel
ADDL
ADDL A, SUBL
SUBL A, Use
@RW1+RW7 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A, Use
@RW1+RW7,
A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 prohibited
#16, rel A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 prohibited
#8, rel
ADDL
ADDL A,
A,@RW2+ @PC+d16
ADDL
ADDL A, SUBL
SUBL A, Use
A,@RW3+
addr16 A,@RW3+
addr16 prohibited
+5
+6
+7
+8
+9
+A
+B
+C
+D
+E
+F
SUBL
SUBL A,
A,@RW2+ @PC+d16
@RW0, @RW0+d16 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A,
#16, rel
#16, rel A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
SUBL
SUBL A,
A, RL2 @RW4+d8
Use
prohibited
ANDL
ANDL A,
A,@RW2+ @PC+d16
ANDL
ANDL A,
A, RL3 @RW7+d8
ANDL
ANDL A,
A, RL3 @RW6+d8
ANDL
ANDL A,
A, RL2 @RW5+d8
ANDL
ANDL A,
A, RL2 @RW4+d8
ORL
ORL A,
A,@RW2+ @PC+d16
ORL
ORL A,
A, RL3 @RW7+d8
ORL
ORL A,
A, RL3 @RW6+d8
ORL
ORL A,
A, RL2 @RW5+d8
ORL
ORL A,
A, RL2 @RW4+d8
XORL
XORL A,
A,@RW2+ @PC+d16
XORL
XORL A,
A, RL3 @RW7+d8
XORL
XORL A,
A, RL3 @RW6+d8
XORL
XORL A,
A, RL2 @RW5+d8
XORL
XORL A,
A, RL2 @RW4+d8
XORL
XORL A,
A, RL1 @RW3+d8
addr16,
#8, rel
Use
@PC+d16,
prohibited
#8, rel
@RW3, @RW3+d16,
#8, rel
#8, rel
@RW2, @RW2+d16,
#8, rel
#8, rel
@RW1, @RW1+d16,
#8, rel
#8, rel
@RW0, @RW0+d16,
#8, rel
#8, rel
R7, @RW7+d8,
#8, rel
#8, rel
R6, @RW6+d8,
#8, rel
#8, rel
R5, @RW5+d8,
#8, rel
#8, rel
R4, @RW4+d8,
#8, rel
#8, rel
R3, @RW3+d8,
#8, rel
#8, rel
addr16, CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A, Use
#16, rel A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 prohibited
@PC+d16, CMPL
CMPL A,
#16, rel A,@RW2+ @PC+d16
RW7, @RW7+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL3 @RW7+d8
RW6, @RW6+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL3 @RW6+d8
RW5, @RW5+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL2 @RW5+d8
RW4, @RW4+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL2 @RW4+d8
ORL
ORL A,
A, RL1 @RW3+d8
R2, @RW2+d8,
#8, rel
#8, rel
R1, @RW1+d8,
#8, rel
#8, rel
ADDL
ADDL A,
A, RL2 @RW4+d8
ANDL
ANDL A,
A, RL1 @RW3+d8
XORL
XORL A,
A, RL1 @RW2+d8
XORL
XORL A,
A, RL0 @RW1+d8
+4
RW3, @RW3+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL1 @RW3+d8
ORL
ORL A,
A, RL1 @RW2+d8
ORL
ORL A,
A, RL0 @RW1+d8
SUBL
SUBL A,
A, RL1 @RW3+d8
ANDL
ANDL A,
A, RL1 @RW2+d8
ANDL
ANDL A,
A, RL0 @RW1+d8
ADDL
ADDL A,
A, RL1 @RW3+d8
RW2, @RW2+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL1 @RW2+d8
RW1, @RW1+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL0 @RW1+d8
+3
CBNE ↓
F0
R0, @RW0+d8,
#8, rel
#8, rel
CBNE ↓
E0
SUBL
SUBL A,
A, RL1 @RW2+d8
XORL
XORL A,
A, RL0 @RW0+d8
C0
ADDL
ADDL A,
A, RL1 @RW2+d8
ORL
ORL A,
A, RL0 @RW0+d8
A0
+2
ANDL
ANDL A,
A, RL0 @RW0+d8
80
SUBL
SUBL A,
A, RL0 @RW1+d8
70
ADDL
ADDL A,
A, RL0 @RW1+d8
60
RW0, @RW0+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL0 @RW0+d8
CWBNE ↓ CWBNE ↓
40
+1
30
+0
20
SUBL
SUBL A,
A, RL0 @RW0+d8
10
ADDL
ADDL A,
A, RL0 @RW0+d8
00
APPENDIX B Instructions
Table B.9-6 ea Instruction 1 (First Byte = 70H)
591
592
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL3 @@RW7+d8
@RL3 @@RW7+d8
RL3 @RW7+d8
RL3 @RW7+d8
A, RL3 @RW7+d8
RL3, A @RW7+d8,A
R7, #8 @RW7+d8,#8
A, RW7 @RW7+d8
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW0 @RW0+d16 @@RW0 @RW0+d16
@RW0 @RW0+d16
@RW0 @RW0+d16 A,@RW0 @RW0+d16 @RW0,A @RW0+d16,A @RW0, #8 @RW0+d16,#8
A,@RW0 @RW0+d16
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW1 @RW1+d16 @@RW1 @RW1+d16
@RW1 @RW1+d16
@RW1 @RW1+d16 A,@RW1 @RW1+d16 @RW1,A @RW1+d16,A @RW1, #8 @RW1+d16,#8
A,@RW1 @RW1+d16
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW2 @RW2+d16 @@RW2 @RW2+d16
@RW2 @RW2+d16
@RW2 @RW2+d16 A,@RW2 @RW2+d16 @RW2,A @RW2+d16,A @RW2, #8 @RW2+d16,#8
A,@RW2 @RW2+d16
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW3 @RW3+d16 @@RW3 @RW3+d16
@RW3 @RW3+d16
@RW3 @RW3+d16 A,@RW3 @RW3+d16 @RW3,A @RW3+d16,A @RW3, #8 @RW3+d16,#8
A,@RW3 @RW3+d16
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW0+ @RW0+RW7 @@RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 @RW0+,A @RW0+RW7,A @RW0+, #8 @RW0+RW7,#8 A,@RW0+ @RW0+RW7
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW1+ @RW1+RW7 @@RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 @RW1+,A @RW1+RW7,A @RW1+, #8 @RW1+RW7,#8 A,@RW1+ @RW1+RW7
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW2+ @@PC+d16 @@RW2+ @@PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16 A,@RW2+ @PC+d16 @RW2+,A @PC+d16, A @RW2+, #8 @PC+d16, #8 A,@RW2+ @PC+d16
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW3+ @addr16 @@RW3+ @addr16 @RW3+
addr16 @RW3+
addr16 A,@RW3+
addr16 @RW3+,A
addr16, A @RW3+, #8
addr16, #8 A,@RW3+
addr16
+8
+9
+A
+B
+C
+D
+E
+F
F0
+7
E0
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL3 @@RW6+d8
@RL3 @@RW6+d8
RL3 @RW6+d8
RL3 @RW6+d8
A, RL3 @RW6+d8
RL3, A @RW6+d8,A
R6, #8 @RW6+d8,#8
A, RW6 @RW6+d8
D0
+6
C0
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL2 @@RW5+d8
@RL2 @@RW5+d8
RL2 @RW5+d8
RL2 @RW5+d8
A, RL2 @RW5+d8
RL2, A @RW5+d8,A
R5, #8 @RW5+d8,#8
A, RW5 @RW5+d8
B0
+5
A0
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL2 @@RW4+d8
@RL2 @@RW4+d8
RL2 @RW4+d8
RL2 @RW4+d8
A, RL2 @RW4+d8
RL2, A @RW4+d8,A
R4, #8 @RW4+d8,#8
A, RW4 @RW4+d8
90
+4
80
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL1 @@RW3+d8
@RL1 @@RW3+d8
RL1 @RW3+d8
RL1 @RW3+d8
A, RL1 @RW3+d8
RL1, A @RW3+d8,A
R3, #8 @RW3+d8,#8
A, RW3 @RW3+d8
70
+3
60
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL1 @@RW2+d8
@RL1 @@RW2+d8
RL1 @RW2+d8
RL1 @RW2+d8
A, RL1 @RW2+d8
RL1, A @RW2+d8,A
R2, #8 @RW2+d8,#8
A, RW2 @RW2+d8
50
+2
40
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL0 @@RW1+d8
@RL0 @@RW1+d8
RL0 @RW1+d8
RL0 @RW1+d8
A, RL0 @RW1+d8
RL0, A @RW1+d8,A
R1, #8 @RW1+d8,#8
A, RW1 @RW1+d8
30
+1
20
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL0 @@RW0+d8
@RL0 @@RW0+d8
RL0 @RW0+d8
RL0 @RW0+d8
A, RL0 @RW0+d8
RL0, A @RW0+d8,A
R0, #8 @RW0+d8,#8
A, RW0 @RW0+d8
10
+0
00
APPENDIX
Table B.9-7 ea Instruction 2 (First Byte = 71H)
D0
E0
F0
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV A,
MOV
MOV
MOVX
MOVX A,
XCH
XCH A,
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV A,
MOV
MOV
MOVX
MOVX A,
XCH
XCH A,
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16 A,@RW2+ @PC+d16 @RW2+, A @PC+d16, A A,@RW2+ @PC+d16 A,@RW2+ @PC+d16
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW3+
addr16 @RW3+
addr16 @RW3+
addr16 @RW3+
addr16 A,@RW3+
addr16 @RW3+, A
addr16, A A,@RW3+
addr16 A,@RW3+
addr16
+D
+E
+F
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R7 @RW7+d8
A, R7 @RW7+d8
R7, A @RW7+d8,A
A, R7 @RW7+d8
A, R7 @RW7+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R6 @RW6+d8
A, R6 @RW6+d8
R6, A @RW6+d8,A
A, R6 @RW6+d8
A, R6 @RW6+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R5 @RW5+d8
A, R5 @RW5+d8
R5, A @RW5+d8,A
A, R5 @RW5+d8
A, R5 @RW5+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R4 @RW4+d8
A, R4 @RW4+d8
R4, A @RW4+d8,A
A, R4 @RW4+d8
A, R4 @RW4+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R3 @RW3+d8
A, R3 @RW3+d8
R3, A @RW3+d8,A
A, R3 @RW3+d8
A, R3 @RW3+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R2 @RW2+d8
A, R2 @RW2+d8
R2, A @RW2+d8,A
A, R2 @RW2+d8
A, R2 @RW2+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R1 @RW1+d8
A, R1 @RW1+d8
R1, A @RW1+d8,A
A, R1 @RW1+d8
A, R1 @RW1+d8
+C
INC
DEC
R7 @RW7+d8
C0
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW3 @RW3+d16
@RW3 @RW3+d16
@RW3 @RW3+d16
@RW3 @RW3+d16 A,@RW3 @RW3+d16 @RW3, A @RW3+d16,A
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
ROLC
RORC
RORC
INC
R7 @RW7+d8
R7 @RW7+d8
ROLC
INC
DEC
R6 @RW6+d8
B0
+B
ROLC
RORC
RORC
INC
R6 @RW6+d8
R6 @RW6+d8
ROLC
INC
DEC
R5 @RW5+d8
A0
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW2 @RW2+d16
@RW2 @RW2+d16
@RW2 @RW2+d16
@RW2 @RW2+d16 A,@RW2 @RW2+d16 @RW2, A @RW2+d16,A
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
ROLC
RORC
RORC
INC
R5 @RW5+d8
R5 @RW5+d8
ROLC
INC
DEC
R4 @RW4+d8
90
+A
ROLC
RORC
RORC
INC
R4 @RW4+d8
R4 @RW4+d8
ROLC
INC
DEC
R3 @RW3+d8
INC
DEC
R2 @RW2+d8
INC
DEC
R1 @RW1+d8
80
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R0 @RW0+d8
A, R0 @RW0+d8
R0, A @RW0+d8,A
A, R0 @RW0+d8
A, R0 @RW0+d8
70
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW1 @RW1+d16
@RW1 @RW1+d16
@RW1 @RW1+d16
@RW1 @RW1+d16 A,@RW1 @RW1+d16 @RW1, A @RW1+d16,A
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
ROLC
RORC
RORC
INC
R3 @RW3+d8
R3 @RW3+d8
ROLC
60
INC
DEC
R0 @RW0+d8
50
+9
ROLC
RORC
RORC
INC
R2 @RW2+d8
R2 @RW2+d8
ROLC
40
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW0 @RW0+d16
@RW0 @RW0+d16
@RW0 @RW0+d16
@RW0 @RW0+d16 A,@RW0 @RW0+d16 @RW0, A @RW0+d16,A
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
ROLC
RORC
RORC
INC
R1 @RW1+d8
R1 @RW1+d8
ROLC
30
ROLC
RORC
RORC
INC
R0 @RW0+d8
R0 @RW0+d8
20
ROLC
10
+8
+7
+6
+5
+4
+3
+2
+1
+0
00
APPENDIX B Instructions
Table B.9-8 ea Instruction 3 (First Byte = 72H)
593
594
JMP
JMP @
CALL
CALL @
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW3 @RW3+d16 @@RW3 @RW3+d16 @RW3 @RW3+d16
@RW3 @RW3+d16 A,@RW3 @RW3+d16 @RW3, A @RW3+d16,A @RW3, #16 @RW3+d16,#16 A,@RW3 @RW3+d16
+B
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@RW2+ @PC+d16 A,@RW2+ @PC+d16 @RW2+, A @PC+d16, A @RW2+, #16 @PC+d16, #16 A,@RW2+ @PC+d16
JMP
JMP
CALL
CALL
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW3+ @addr16 @@RW3+ @addr16 @RW3+
addr16 @RW3+
addr16 A,@RW3+
addr16 @RW3+, A
addr16, A @RW3+, #16
addr16, #16 A,@RW3+
addr16
INCW
+F
INCW
JMP
JMP
CALL
CALL
INCW
INCW
@@RW2+ @@PC+d16 @@RW2+ @@PC+d16 @RW2+ @PC+d16
CALL @
+E
CALL
DECW
DECW
MOVW
MOVW A,
MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A @RW1+, #16 @RW1+RW7,#16 A,@RW1+ @RW1+RW7
XCHW
XCHW A,
A, RW7 @RW7+d8
XCHW
XCHW A,
A, RW6 @RW6+d8
XCHW
XCHW A,
A, RW5 @RW5+d8
+D @@RW1+ @RW1+RW7 @@RW1+ @RW1+RW7 @RW1+ @RW1+RW7
INCW
MOVW
MOVW
RW7, #16 @RW7+d8,#16
MOVW
MOVW
RW6, #16 @RW6+d8,#16
MOVW
MOVW
RW5, #16 @RW5+d8,#16
XCHW
XCHW A,
A, RW4 @RW4+d8
DECW
DECW
MOVW
MOVW A,
MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A @RW0+, #16 @RW0+RW7,#16 A,@RW0+ @RW0+RW7
INCW
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW7 @RW7+d8
RW7 @RW7+d8
A, RW7 @RW7+d8
RW7, A @RW7+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW6 @RW6+d8
RW6 @RW6+d8
A, RW6 @RW6+d8
RW6, A @RW6+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW5 @RW5+d8
RW5 @RW5+d8
A, RW5 @RW5+d8
RW5, A @RW5+d8,A
MOVW
MOVW
RW4, #16 @RW4+d8,#16
+C @@RW0+ @RW0+RW7 @@RW0+ @RW0+RW7 @RW0+ @RW0+RW7
JMP @
JMP
JMP @
CALL
CALL @
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW2 @RW2+d16 @@RW2 @RW2+d16 @RW2 @RW2+d16
@RW2 @RW2+d16 A,@RW2 @RW2+d16 @RW2, A @RW2+d16,A @RW2, #16 @RW2+d16,#16 A,@RW2 @RW2+d16
+A
JMP
JMP
JMP @
CALL
CALL @
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW1 @RW1+d16 @@RW1 @RW1+d16 @RW1 @RW1+d16
@RW1 @RW1+d16 A,@RW1 @RW1+d16 @RW1, A @RW1+d16,A @RW1, #16 @RW1+d16,#16 A,@RW1 @RW1+d16
+9
CALL @
JMP
JMP @
CALL
CALL @
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW0 @RW0+d16 @@RW0 @RW0+d16 @RW0 @RW0+d16
@RW0 @RW0+d16 A,@RW0 @RW0+d16 @RW0,A @RW0+d16,A @RW0, #16 @RW0+d16,#16 A,@RW0 @RW0+d16
+8
CALL
CALL
CALL
@RW7 @@RW7+d8
JMP
JMP
@RW7 @@RW7+d8
+7
JMP @
CALL
CALL
@RW6 @@RW6+d8
JMP
JMP
@RW6 @@RW6+d8
+6
JMP
CALL
CALL
@RW5 @@RW5+d8
JMP
JMP
@RW5 @@RW5+d8
+5
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW4 @RW4+d8
RW4 @RW4+d8
A, RW4 @RW4+d8
RW4, A @RW4+d8,A
XCHW
XCHW A,
A, RW3 @RW3+d8
XCHW
XCHW A,
A, RW2 @RW2+d8
XCHW
XCHW A,
A, RW1 @RW1+d8
CALL
CALL
@RW4 @@RW4+d8
MOVW
MOVW
RW3, #16 @RW3+d8,#16
MOVW
MOVW
RW2, #16 @RW2+d8,#16
MOVW
MOVW
RW1, #16 @RW1+d8,#16
JMP
JMP
@RW4 @@RW4+d8
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW3 @RW3+d8
RW3 @RW3+d8
A, RW3 @RW3+d8
RW3, A @RW3+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW2 @RW2+d8
RW2 @RW2+d8
A, RW2 @RW2+d8
RW2, A @RW2+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW1 @RW1+d8
RW1 @RW1+d8
A, RW1 @RW1+d8
RW1, A @RW1+d8,A
+4
F0
XCHW
XCHW A,
A, RW0 @RW0+d8
E0
CALL
CALL
@RW3 @@RW3+d8
D0
MOVW
MOVW
RW0, #16 @RW0+d8,#16
C0
JMP
JMP
@RW3 @@RW3+d8
B0
+3
A0
CALL
CALL
@RW2 @@RW2+d8
90
JMP
JMP
@RW2 @@RW2+d8
80
+2
70
CALL
CALL
@RW1 @@RW1+d8
60
JMP
JMP
@RW1 @@RW1+d8
50
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW0 @RW0+d8
RW0 @RW0+d8
A, RW0 @RW0+d8
RW0, A @RW0+d8,A
40
+1
30
CALL
CALL
@RW0 @@RW0+d8
20
JMP
JMP
@RW0 @@RW0+d8
10
+0
00
APPENDIX
Table B.9-9 ea Instruction 4 (First Byte = 73H)
ADD
A, SUB
SUB
SUB
ADDC
A, ADDC
A,
ADDC
ADDC A,
A, CMP
CMP
CMP
CMP
A,
A,
A, AND
AND
AND
AND
AND
AND
A,
A,
DBNZ @PC
A, OR
OR
A, XOR
XOR
A, DBNZ
+d16, rel
A,@RW2+ @PC+d16, A,@RW2+ @PC+d16 @RW2+, rel
+F A,@RW3+
ADD
ADD
SUB
SUB
ADDC
ADDC
CMP
CMP
AND
AND
OR
OR
XOR
XOR
DBNZ
DBNZ
A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 A,@RW3+
A, addr16 A,@RW3+ A, addr16 @RW3+, rel addr16, rel
+E A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16
ADD
SUB
CMP
DBNZ @RW1
XOR
XOR A,
DBNZ
+RW7, rel
A,@RW1+ @RW1+RW7 @RW1+, rel
A,
CMP
OR
OR
A,
A,@RW1+ @RW1+RW7
ADD
ADD
ADDC A,
+D A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
ADDC
XOR
XOR A,
DBNZ
DBNZ @RW0
+RW7, rel
A,@RW0+ @RW0+RW7 @RW0+, rel
A,
OR
OR
A,
A,@RW0+ @RW0+RW7
SUB
+C A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
SUB
DBNZ @RW3
XOR
XOR
A, DBNZ
@RW3, rel
+d16, rel
A,@RW3 @RW3+d16
ADD
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
+B
A,
DBNZ @RW2
XOR
XOR
A, DBNZ
@RW2, rel
+d16, rel
A,@RW2 @RW2+d16
ADD
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
+A
ADD
DBNZ @RW1
XOR
XOR
A, DBNZ
@RW1, rel
+d16, rel
A,@RW1 @RW1+d16
ADD
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
+9
ADD
DBNZ @RW0
XOR
XOR
A, DBNZ
@RW0, rel
+d16, rel
A,@RW0 @RW0+d16
ADD
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @RW7
+d8, rel
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
R7, rel
ADD
F0
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @RW6
+d8, rel
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
R6, rel
E0
ADD
D0
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @RW5
+d8, rel
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
R5, rel
C0
ADD
B0
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @RW4
+d8, rel
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
R4, rel
A0
ADD
90
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @RW3
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
R3, rel +d8, rel
80
ADD
70
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @RW2
+d8, rel
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
R2, rel
60
ADD
50
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @RW1
+d8, rel
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
R1, rel
40
ADD
30
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @RW0
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
R0, rel +d8, rel
20
ADD
10
+8
+7
+6
+5
+4
+3
+2
+1
+0
00
APPENDIX B Instructions
Table B.9-10 ea Instruction 5 (First Byte = 74H)
595
596
NOT
NOT
R2 @RW2+d8
SUB
SUB
SUB
SUB
ADD
SUB
SUB
@RW1+RW7,A @RW1+, A @RW1+RW7,A
ADD @R
@RW0+RW7,A @RW0+, A @RW0+RW7,A
ADD @R
+F
ADD
ADD
@RW3+, A addr16, A
SUB
SUB
@RW3+, A addr16, A
+E @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A
ADD
+D @RW1+, A
ADD
+C @RW0+, A
ADD
NOT
NOT
@RW1+ @RW1+RW7
NOT
NOT
@RW0+ @RW0+RW7
SUBC
SUBC A, NEG
NEG
AND
AND
A,@RW3+
addr16 @RW3+
addr16 @RW3+, A addr16, A
OR
OR
@RW3+, A addr16, A
XOR
XOR
@RW3+, A addr16, A
NOT
NOT
@RW3+
addr16
SUBC
SUBC A, NEG
NEG
AND
AND
OR
OR
XOR
XOR
NOT
NOT
A,@RW2+ @PC+d16
@RW2+ @PC+d16 @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A @RW2+ @PC+d16
SUBC
SUBC A,
NEG
NEG
AND
AND
OR
OR
XOR
XOR
A,@RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A
SUBC
SUBC A,
NEG
NEG
AND
AND
OR
OR
XOR
XOR
A,@RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A
NOT
NOT
@RW3 @RW3+d16
ADD
ADD @R
SUB
SUB
SUBC
SUBC A, NEG
NEG
AND
AND
OR
OR
XOR
XOR
@RW3, A @RW3+d16,A @RW3, A @RW3+d16,A A, @RW3 @RW3+d16
@RW3 @RW3+d16 @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A
+B
XOR
NOT
NOT
R7, A @RW7+d8, A
R7 @RW7+d8
XOR
NOT
NOT
R6, A @RW6+d8, A
R6 @RW6+d8
XOR
NOT
NOT
R5, A @RW5+d8, A
R5 @RW5+d8
XOR
NOT
NOT
R4, A @RW4+d8, A
R4 @RW4+d8
XOR
NOT
NOT
R3, A @RW3+d8, A
R3 @RW3+d8
XOR
R2, A @RW2+d8,A
XOR
NOT
NOT
R1, A @RW1+d8, A
R1 @RW1+d8
NOT
NOT
@RW2 @RW2+d16
XOR
F0
ADD
ADD @R
SUB
SUB
SUBC
SUBC A, NEG
NEG
AND
AND
OR
OR
XOR
XOR
@RW2, A @RW2+d16,A @RW2, A @RW2+d16,A A, @RW2 @RW2+d16
@RW2 @RW2+d16 @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A
NEG
AND
AND
OR
OR
R7 @RW7+d8
R7, A @RW7+d8, A
R7, A @RW7+d8, A
XOR
XOR
XOR
XOR
XOR
XOR
E0
XOR
NOT
NOT
R0, A @RW0+d8, A
R0 @RW0+d8
D0
+A
ADD
SUB
SUB
SUBC
SUBC A, NEG
R7, A @RW7+d8, A
R7, A @RW7+d8, A
A, R7 @RW7+d8
ADD
NEG
AND
AND
OR
OR
R6 @RW6+d8
R6, A @RW6+d8, A
R6, A @RW6+d8, A
NEG
AND
AND
OR
OR
R5 @RW5+d8
R5, A @RW5+d8, A
R5, A @RW5+d8, A
NEG
AND
AND
OR
OR
R4 @RW4+d8
R4, A @RW4+d8, A
R4, A @RW4+d8, A
NEG
AND
AND
OR
OR
R3 @RW3+d8
R3, A @RW3+d8, A
R3, A @RW3+d8, A
NEG
AND
AND
OR
OR
R2 @RW2+d8
R2, A @RW2+d8,A
R2, A @RW2+d8,A
NEG
AND
AND
OR
OR
R1 @RW1+d8
R1, A @RW1+d8, A
R1, A @RW1+d8, A
XOR
C0
NOT
NOT
@RW1 @RW1+d16
ADD
SUB
SUB
SUBC
SUBC A, NEG
R6, A @RW6+d8, A
R6, A @RW6+d8, A
A, R6 @RW6+d8
ADD
B0
ADD
ADD @R
SUB
SUB
SUBC
SUBC A, NEG
NEG
AND
AND
OR
OR
XOR
XOR
@RW1, A @RW1+d16,A @RW1, A @RW1+d16,A A, @RW1 @RW1+d16
@RW1 @RW1+d16 @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A
ADD
SUB
SUB
SUBC
SUBC A, NEG
R5, A @RW5+d8, A
R5, A @RW5+d8, A
A, R5 @RW5+d8
ADD
A0
+9
ADD
SUB
SUB
SUBC
SUBC A, NEG
R4, A @RW4+d8, A
R4, A @RW4+d8, A
A, R4 @RW4+d8
ADD
90
NOT
NOT
@RW0 @RW0+d16
ADD
SUB
SUB
SUBC
SUBC A, NEG
R3, A @RW3+d8, A
R3, A @RW3+d8, A
A, R3 @RW3+d8
ADD
80
NEG
AND
AND
OR
OR
R0 @RW0+d8
R0, A @RW0+d8, A
R0, A @RW0+d8, A
70
ADD
ADD
SUB
SUB
SUBC
SUBC A, NEG
NEG
AND
AND
OR
OR
XOR
XOR
@RW0, A @RW0+d16,A @RW0, A @RW0+d16,A A, @RW0 @RW0+d16
@RW0 @RW0+d16 @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A
ADD
SUB
SUB
SUBC
SUBC A, NEG
R2, A @RW2+d8,A
R2, A @RW2+d8,A
A, R2 @RW2+d8
60
ADD
50
ADD
SUB
SUB
SUBC
SUBC A, NEG
R1, A @RW1+d8, A
R1, A @RW1+d8, A
A, R1 @RW1+d8
40
ADD
30
ADD
SUB
SUB
SUBC
SUBC A, NEG
R0, A @RW0+d8, A
R0, A @RW0+d8, A
A, R0 @RW0+d8
20
ADD
10
+8
+7
+6
+5
+4
+3
+2
+1
+0
00
APPENDIX
Table B.9-11 ea Instruction 6 (First Byte = 75H)
ADDW A, SUBW
ADDW
ADDCW
CMPW
ADDCW A, CMPW
ADDCW A,
ANDW
CMPW A, ANDW
CMPW A,
ORW
ORW
ANDW A, ORW
ANDW A,
ANDW A,
ORW
ORW
ORW
A,
A,
A, XORW
DWBNZ @PC
XORW A, DWBNZ
@RW2+, rel
+d16,rel
+F A,@RW3+
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
addr16 A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 @RW3+, rel addr16, rel
+E A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16, A,@RW2+ @PC+d16
SUBW A, ADDCW
SUBW A,
ANDW
XORW
XORW A,
DWBNZ
DWBNZ @RW1
+RW7,rel
A,@RW1+ @RW1+RW7 @RW1+, rel
SUBW
ADDW A,
ADDW
CMPW A,
+D A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
CMPW
XORW
XORW A,
DWBNZ
DWBNZ @RW0
+RW7,rel
A,@RW0+ @RW0+RW7 @RW0+, rel
ADDCW A,
+C A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
ADDCW
XORW
XORW A, DWBNZ
DWBNZ @RW3
+d16,rel
A,@RW3 @RW3+d16 @RW3, rel
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
+B
SUBW A,
XORW
XORW A, DWBNZ
DWBNZ @RW2
+d16,rel
A,@RW2 @RW2+d16 @RW2, rel
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
+A
SUBW
XORW
XORW A, DWBNZ
DWBNZ @RW1
+d16,rel
A,@RW1 @RW1+d16 @RW1, rel
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
+9
ADDW A,
XORW
XORW A, DWBNZ
DWBNZ @RW0
+d16,rel
A,@RW0 @RW0+d16 @RW0, rel
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
+8
ADDW
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ @RW7
+d8,rel
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
RW7, rel
F0
+7
E0
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ @RW6
+d8,rel
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
RW6, rel
D0
+6
C0
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ @RW5
+d8,rel
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
RW5, rel
B0
+5
A0
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ @RW4
+d8,rel
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
RW4, rel
90
+4
80
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ @RW3
+d8,rel
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
RW3, rel
70
+3
60
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ @RW2
+d8,rel
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
RW2, rel
50
+2
40
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ @RW1
+d8,rel
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
RW1, rel
30
+1
20
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ @RW0
+d8,rel
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
RW0, rel
10
+0
00
APPENDIX B Instructions
Table B.9-12 ea Instruction 7 (First Byte = 76H)
597
598
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW3 @RW3+d16 @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A
@RW3 @RW3+d16
SUBW
SUBW
@RW3+, A addr16, A
ADDW
ADDW
@RW3+, A addr16, A
+F
SUBCW
SUBCW A, NEGW
NEGW
ANDW
ANDW
A,@RW3+
addr16 @RW3+
addr16 @RW3+, A addr16, A
ORW
ORW
@RW3+, A addr16, A
XORW
XORW
@RW3+, A addr16, A
NOTW
NOTW
@RW3+
addr16
SUBCW
SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
A,@RW2+ @PC+d16
@RW2+ @PC+d16 @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A
@RW2+ @PC+d16
SUBW
SUBW
@RW2+, A @PC+d16,A
ADDW
ADDW
@RW2+, A @PC+d16,A
+E
SUBCW A,
ADDW
ADDW
SUBW
SUBW
SUBCW
SUBCW A,
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A A,@RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A @RW1+ @RW1+RW7
SUBCW
+D
SUBW
SUBCW A,
ADDW
ADDW
SUBW
SUBW
SUBCW
SUBCW A,
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A A,@RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A @RW0+ @RW0+RW7
SUBW
SUBCW
+C
ADDW
ADDW
SUBW
SUBCW A,
+B @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A A, @RW3 @RW3+d16
SUBW
SUBCW
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW2 @RW2+d16 @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A
@RW2 @RW2+d16
ADDW
ADDW
SUBW
+A @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A A, @RW2 @RW2+d16
SUBW
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW1 @RW1+d16 @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A
@RW1 @RW1+d16
ADDW
ADDW
SUBCW A,
+9 @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A A, @RW1 @RW1+d16
SUBCW
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW0 @RW0+d16 @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A
@RW0 @RW0+d16
SUBW
NOTW
NOTW
RW7 @RW7+d8
NOTW
NOTW
RW6 @RW6+d8
NOTW
NOTW
RW5 @RW5+d8
+8 @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A A, @RW0 @RW0+d16
SUBW
XORW
XORW
RW7, A @RW7+d8, A
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW7, A @RW7+d8, A
RW7, A @RW7+d8, A
A, RW7 @RW7+d8
RW7 @RW7+d8
RW7, A @RW7+d8, A
RW7, A @RW7+d8, A
+7
ADDW
XORW
XORW
RW6, A @RW6+d8, A
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW6, A @RW6+d8, A
RW6, A @RW6+d8, A
A, RW6 @RW6+d8
RW6 @RW6+d8
RW6, A @RW6+d8, A
RW6, A @RW6+d8, A
+6
ADDW
XORW
XORW
RW5, A @RW5+d8, A
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW5, A @RW5+d8, A
RW5, A @RW5+d8, A
A, RW5 @RW5+d8
RW5 @RW5+d8
RW5, A @RW5+d8, A
RW5, A @RW5+d8, A
+5
NOTW
NOTW
RW4 @RW4+d8
XORW
XORW
RW4, A @RW4+d8, A
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW4, A @RW4+d8, A
RW4, A @RW4+d8, A
A, RW4 @RW4+d8
RW4 @RW4+d8
RW4, A @RW4+d8, A
RW4, A @RW4+d8, A
+4
F0
NOTW
NOTW
RW0 @RW0+d8
E0
NOTW
NOTW
RW3 @RW3+d8
D0
XORW
XORW
RW3, A @RW3+d8, A
C0
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW3, A @RW3+d8, A
RW3, A @RW3+d8, A
A, RW3 @RW3+d8
RW3 @RW3+d8
RW3, A @RW3+d8, A
RW3, A @RW3+d8, A
B0
+3
A0
NOTW
NOTW
RW2 @RW2+d8
90
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
RW2, A @RW2+d8,A
RW2, A @RW2+d8,A
A, RW2 @RW2+d8
RW2 @RW2+d8
RW2, A @RW2+d8,A
RW2, A @RW2+d8,A
RW2, A @RW2+d8,A
80
+2
70
NOTW
NOTW
RW1 @RW1+d8
60
XORW
XORW
RW1, A @RW1+d8, A
50
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW1, A @RW1+d8, A
RW1, A @RW1+d8, A
A, RW1 @RW1+d8
RW1 @RW1+d8
RW1, A @RW1+d8, A
RW1, A @RW1+d8, A
40
+1
30
XORW
XORW
RW0, A @RW0+d8, A
20
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW0, A @RW0+d8, A
RW0, A @RW0+d8, A
A, RW0 @RW0+d8
RW0 @RW0+d8
RW0, A @RW0+d8, A
RW0, A @RW0+d8, A
10
+0
00
APPENDIX
Table B.9-13 ea Instruction 8 (First Byte = 77H)
DIV
DIV
A, DIVW
DIVW A,
A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
DIV
DIV
A, DIVW
DIVW A,
A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A,
A, @RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A,
A, @RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A,
A, @RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
MULU
MULU A, MULUW MULUW A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
MULU
MULU A, MULUW MULUW A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
MULU
MULU A, MULUW MULUW A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
MULU
MULU A, MULUW
MULUW A, MUL
MUL A,
MULW
MULW A,
DIVU
DIVU A,
DIVUW
DIVUW A,
A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
MULU
MULU A, MULUW
MULUW A, MUL
MUL A,
MULW
MULW A,
DIVU
DIVU A,
DIVUW
DIVUW A,
A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
MULU
MULU A, MULUW
MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16
A,@RW2+ @PC+d16
A,@RW2+ @PC+d16
+9
+A
+B
+C
+D
+E
+F A, @RW3+
MULU
DIV
DIV
A, DIVW
DIVW A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A,
A, @RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
MULU
MULU A, MULUW MULUW A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
+8
MULU A, MULUW
MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
addr16 A,@RW3+ addr16
A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
A, DIVW
DIVW A,
addr16 A,@RW3+
addr16
DIV
DIV
A, DIVW
DIVW A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
DIV
DIV
A, DIVW
DIVW A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
DIV
DIV
A, DIVW
DIVW A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R7 @RW7+d8
A, RW7 @RW7+d8
A, R7 @RW7+d8
A, RW7 @RW7+d8
A, R7 @RW7+d8
A, RW7 @RW7+d8
A, R7 @RW7+d8
A, RW7 @RW7+d8
F0
+7
E0
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R6 @RW6+d8
A, RW6 @RW6+d8
A, R6 @RW6+d8
A, RW6 @RW6+d8
A, R6 @RW6+d8
A, RW6 @RW6+d8
A, R6 @RW6+d8
A, RW6 @RW6+d8
D0
+6
C0
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R5 @RW5+d8
A, RW5 @RW5+d8
A, R5 @RW5+d8
A, RW5 @RW5+d8
A, R5 @RW5+d8
A, RW5 @RW5+d8
A, R5 @RW5+d8
A, RW5 @RW5+d8
B0
+5
A0
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R4 @RW4+d8
A, RW4 @RW4+d8
A, R4 @RW4+d8
A, RW4 @RW4+d8
A, R4 @RW4+d8
A, RW4 @RW4+d8
A, R4 @RW4+d8
A, RW4 @RW4+d8
90
+4
80
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R3 @RW3+d8
A, RW3 @RW3+d8
A, R3 @RW3+d8
A, RW3 @RW3+d8
A, R3 @RW3+d8
A, RW3 @RW3+d8
A, R3 @RW3+d8
A, RW3 @RW3+d8
70
+3
60
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R2 @RW2+d8
A, RW2 @RW2+d8
A, R2 @RW2+d8
A, RW2 @RW2+d8
A, R2 @RW2+d8
A, RW2 @RW2+d8
A, R2 @RW2+d8
A, RW2 @RW2+d8
50
+2
40
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R1 @RW1+d8
A, RW1 @RW1+d8
A, R1 @RW1+d8
A, RW1 @RW1+d8
A, R1 @RW1+d8
A, RW1 @RW1+d8
A, R1 @RW1+d8
A, RW1 @RW1+d8
30
+1
20
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R0 @RW0+d8
A, RW0 @RW0+d8
A, R0 @RW0+d8
A, RW0 @RW0+d8
A, R0 @RW0+d8
A, RW0 @RW0+d8
A, R0 @RW0+d8
A, RW0 @RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-14 ea Instruction 9 (First Byte = 78H)
599
600
MOVEA RW0, MOVEA
MOVEA RW1, MOVEA
MOVEA RW2, MOVEA
MOVEA RW3, MOVEA
MOVEA RW4, MOVEA
MOVEA RW5, MOVEA
MOVEA RW6, MOVEA
MOVEA RW7,
RW1,@RW0 @RW0+d16
RW2,@RW0 @RW0+d16
RW3,@RW0 @RW0+d16
RW4,@RW0 @RW0+d16
RW5,@RW0 @RW0+d16
RW6,@RW0 @RW0+d16
RW7,@RW0
@RW0+d16
MOVEA RW0, MOVEA
MOVEA RW1, MOVEA
MOVEA RW2, MOVEA
MOVEA RW3, MOVEA
MOVEA RW4, MOVEA
MOVEA RW5, MOVEA
MOVEA RW6, MOVEA
MOVEA RW7,
RW1,@RW1 @RW1+d16
RW2,@RW1 @RW1+d16
RW3,@RW1 @RW1+d16
RW4,@RW1 @RW1+d16
RW5,@RW1 @RW1+d16
RW6,@RW1 @RW1+d16
RW7,@RW1
@RW1+d16
MOVEA RW0, MOVEA
MOVEA RW1, MOVEA
MOVEA RW2, MOVEA
MOVEA RW3, MOVEA
MOVEA RW4, MOVEA
MOVEA RW5, MOVEA
MOVEA RW6, MOVEA
MOVEA RW7,
RW1,@RW2 @RW2+d16
RW2,@RW2 @RW2+d16
RW3,@RW2 @RW2+d16
RW4,@RW2 @RW2+d16
RW5,@RW2 @RW2+d16
RW6,@RW2 @RW2+d16
RW7,@RW2
@RW2+d16
MOVEA RW0, MOVEA
MOVEA RW1, MOVEA
MOVEA RW2, MOVEA
MOVEA RW3, MOVEA
MOVEA RW4, MOVEA
MOVEA RW5, MOVEA
MOVEA RW6, MOVEA
MOVEA RW7,
RW1,@RW3 @RW3+d16
RW2,@RW3 @RW3+d16
RW3,@RW3 @RW3+d16
RW4,@RW3 @RW3+d16
RW5,@RW3 @RW3+d16
RW6,@RW3 @RW3+d16
RW7,@RW3
@RW3+d16
MOVEA RW0, MOVEA
MOVEA RW1, MOVEA
MOVEA RW2, MOVEA
MOVEA RW3, MOVEA
MOVEA RW4, MOVEA
MOVEA RW5, MOVEA
MOVEA RW6, MOVEA
MOVEA RW7,
RW1,@RW0+ @RW0+RW7 RW2,@RW0+ @RW0+RW7 RW3,@RW0+ @RW0+RW7 RW4,@RW0+ @RW0+RW7 RW5,@RW0+ @RW0+RW7 RW6,@RW0+ @RW0+RW7 RW7,@RW0+ @RW0+RW7
MOVEA RW0, MOVEA
MOVEA RW1, MOVEA
MOVEA RW2, MOVEA
MOVEA RW3, MOVEA
MOVEA RW4, MOVEA
MOVEA RW5, MOVEA
MOVEA RW6, MOVEA
MOVEA RW7,
RW1,@RW1+ @RW1+RW7 RW2,@RW1+ @RW1+RW7 RW3,@RW1+ @RW1+RW7 RW4,@RW1+ @RW1+RW7 RW5,@RW1+ @RW1+RW7 RW6,@RW1+ @RW1+RW7 RW7,@RW1+ @RW1+RW7
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
RW0,@RW3+ RW0, addr16 RW1,@RW3+ RW1, addr16 RW2,@RW3+ RW2, addr16 RW3,@RW3+ RW3, addr16 RW4,@RW3+ RW4, addr16 RW5,@RW3+ RW5, addr16
+F
MOVEA
MOVEA
MOVEA
MOVEA
RW6,@RW3+ RW6, addr16 [email protected]+ RW7, addr16
MOVEA
MOVEA RW0, MOVEA
MOVEA RW1, MOVEA
MOVEA RW2, MOVEA
MOVEA RW3, MOVEA
MOVEA RW4, MOVEA
MOVEA RW5, MOVEA
MOVEA RW6, MOVEA
MOVEA RW7,
RW0,@RW2+ @PC+d16
RW1,@RW2+ @PC+d16
RW2,@RW2+ @PC+d16
RW3,@RW2+ @PC+d16
RW4,@RW2+ @PC+d16
RW5,@RW2+ @PC+d16
RW6,@RW2+ @PC+d16
RW7,@RW2+
@PC+d16
+E
+D RW0,@RW1+ @RW1+RW7
+C RW0,@RW0+ @RW0+RW7
+B RW0,@RW3 @RW3+d16
+A RW0,@RW2 @RW2+d16
+9 RW0,@RW1 @RW1+d16
+8 RW0,@RW0 @RW0+d16
MOVEA
MOVEA
MOVEA RW0, MOVEA
MOVEA RW1, MOVEA
MOVEA RW2, MOVEA
MOVEA RW3, MOVEA
MOVEA RW4, MOVEA
MOVEA RW5, MOVEA
MOVEA RW6, MOVEA
MOVEA RW7,
RW0,RW7 @RW7+d8
RW1,RW7 @RW7+d8
RW2,RW7 @RW7+d8
RW3,RW7 @RW7+d8
RW4,RW7 @RW7+d8
RW5,RW7 @RW7+d8
RW6,RW7 @RW7+d8
RW7,RW7
@RW7+d8
F0
+7
E0
MOVEA
MOVEA RW0, MOVEA
MOVEA RW1, MOVEA
MOVEA RW2, MOVEA
MOVEA RW3, MOVEA
MOVEA RW4, MOVEA
MOVEA RW5, MOVEA
MOVEA RW6, MOVEA
MOVEA RW7,
RW0,RW6 @RW6+d8
RW1,RW6 @RW6+d8
RW2,RW6 @RW6+d8
RW3,RW6 @RW6+d8
RW4,RW6 @RW6+d8
RW5,RW6 @RW6+d8
RW6,RW6 @RW6+d8
RW7,RW6
@RW6+d8
D0
+6
C0
MOVEA
MOVEA RW0, MOVEA
MOVEA RW1, MOVEA
MOVEA RW2, MOVEA
MOVEA RW3, MOVEA
MOVEA RW4, MOVEA
MOVEA RW5, MOVEA
MOVEA RW6, MOVEA
MOVEA RW7,
RW0,RW5 @RW5+d8
RW1,RW5 @RW5+d8
RW2,RW5 @RW5+d8
RW3,RW5 @RW5+d8
RW4,RW5 @RW5+d8
RW5,RW5 @RW5+d8
RW6,RW5 @RW5+d8
RW7,RW5
@RW5+d8
B0
+5
A0
MOVEA
MOVEA RW0, MOVEA
MOVEA RW1, MOVEA
MOVEA RW2, MOVEA
MOVEA RW3, MOVEA
MOVEA RW4, MOVEA
MOVEA RW5, MOVEA
MOVEA RW6, MOVEA
MOVEA RW7,
RW0,RW4 @RW4+d8
RW1,RW4 @RW4+d8
RW2,RW4 @RW4+d8
RW3,RW4 @RW4+d8
RW4,RW4 @RW4+d8
RW5,RW4 @RW4+d8
RW6,RW4 @RW4+d8
RW7,RW4
@RW4+d8
90
+4
80
MOVEA
MOVEA RW0, MOVEA
MOVEA RW1, MOVEA
MOVEA RW2, MOVEA
MOVEA RW3, MOVEA
MOVEA RW4, MOVEA
MOVEA RW5, MOVEA
MOVEA RW6, MOVEA
MOVEA RW7,
RW0,RW3 @RW3+d8
RW1,RW3 @RW3+d8
RW2,RW3 @RW3+d8
RW3,RW3 @RW3+d8
RW4,RW3 @RW3+d8
RW5,RW3 @RW3+d8
RW6,RW3 @RW3+d8
RW7,RW3
@RW3+d8
70
+3
60
MOVEA
MOVEA RW0, MOVEA
MOVEA RW1, MOVEA
MOVEA RW2, MOVEA
MOVEA RW3, MOVEA
MOVEA RW4, MOVEA
MOVEA RW5, MOVEA
MOVEA RW6, MOVEA
MOVEA RW7,
RW0,RW2 @RW2+d8
RW1,RW2 @RW2+d8
RW2,RW2 @RW2+d8
RW3,RW2 @RW2+d8
RW4,RW2 @RW2+d8
RW5,RW2 @RW2+d8
RW6,RW2 @RW2+d8
RW7,RW2
@RW2+d8
50
+2
40
MOVEA
MOVEA RW0, MOVEA
MOVEA RW1, MOVEA
MOVEA RW2, MOVEA
MOVEA RW3, MOVEA
MOVEA RW4, MOVEA
MOVEA RW5, MOVEA
MOVEA RW6, MOVEA
MOVEA RW7,
RW0,RW1 @RW1+d8
RW1,RW1 @RW1+d8
RW2,RW1 @RW1+d8
RW3,RW1 @RW1+d8
RW4,RW1 @RW1+d8
RW5,RW1 @RW1+d8
RW6,RW1 @RW1+d8
RW7,RW1
@RW1+d8
30
+1
20
MOVEA
MOVEA RW0, MOVEA
MOVEA RW1, MOVEA
MOVEA RW2, MOVEA
MOVEA RW3, MOVEA
MOVEA RW4, MOVEA
MOVEA RW5, MOVEA
MOVEA RW6, MOVEA
MOVEA RW7,
RW0,RW0 @RW0+d8
RW1,RW0 @RW0+d8
RW2,RW0 @RW0+d8
RW3,RW0 @RW0+d8
RW4,RW0 @RW0+d8
RW5,RW0 @RW0+d8
RW6,RW0 @RW0+d8
RW7,RW0
@RW0+d8
10
+0
00
APPENDIX
Table B.9-15 MOVEA RWi, ea Instruction (First Byte = 79H)
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R7 @RW7+d8
R1, R7 @RW7+d8
R2, R7 @RW7+d8
R3, R7 @RW7+d8
R4, R7 @RW7+d8
R5, R7 @RW7+d8
R6, R7 @RW7+d8
R7, R7 @RW7+d8
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0,@RW0 @RW0+d16 R1,@RW0 @RW0+d16 R2,@RW0 @RW0+d16 R3,@RW0 @RW0+d16 R4,@RW0 @RW0+d16 R5,@RW0 @RW0+d16 R6,@RW0 @RW0+d16 R7,@RW0 @RW0+d16
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0,@RW1 @RW1+d16 R1,@RW1 @RW1+d16 R2,@RW1 @RW1+d16 R3,@RW1 @RW1+d16 R4,@RW1 @RW1+d16 R5,@RW1 @RW1+d16 R6,@RW1 @RW1+d16 R7,@RW1 @RW1+d16
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0,@RW2 @RW2+d16 R1,@RW2 @RW2+d16 R2,@RW2 @RW2+d16 R3,@RW2 @RW2+d16 R4,@RW2 @RW2+d16 R5,@RW2 @RW2+d16 R6,@RW2 @RW2+d16 R7,@RW2 @RW2+d16
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0,@RW3 @RW3+d16 R1,@RW3 @RW3+d16 R2,@RW3 @RW3+d16 R3,@RW3 @RW3+d16 R4,@RW3 @RW3+d16 R5,@RW3 @RW3+d16 R6,@RW3 @RW3+d16 R7,@RW3 @RW3+d16
MOV R0, MOV R0,
MOV R1, MOV R1,
MOV R2, MOV R2,
MOV R3, MOV R3,
MOV R4, MOV R4,
MOV R5, MOV R5,
MOV R6, MOV R6,
MOV R7, MOV R7,
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
MOV R0, MOV R0,
MOV R1, MOV R1,
MOV R2, MOV R2,
MOV R3, MOV R3,
MOV R4, MOV R4,
MOV R5, MOV R5,
MOV R6, MOV R6,
MOV R7, MOV R7,
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
MOV R0, MOV R0, MOV R1, MOV R1, MOV R2, MOV R2, MOV R3, MOV R3, MOV R4, MOV R4, MOV R5, MOV R5, MOV R6, MOV R6, MOV R7, MOV R7,
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
MOV R0, MOV R0, MOV R1, MOV R1, MOV R2, MOV R2, MOV R3, MOV R3, MOV R4, MOV R4, MOV R5, MOV R5, MOV R6, MOV R6, MOV R7, MOV R7,
@RW3+
addr16 @RW3+
addr16
@RW3+
addr16 @RW3+
addr16 @RW3+
addr16 @RW3+
addr16 @RW3+
addr16
@RW3+
addr16
+8
+9
+A
+B
+C
+D
+E
+F
F0
+7
E0
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R6 @RW6+d8
R1, R6 @RW6+d8
R2, R6 @RW6+d8
R3, R6 @RW6+d8
R4, R6 @RW6+d8
R5, R6 @RW6+d8
R6, R6 @RW6+d8
R7, R6 @RW6+d8
D0
+6
C0
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R5 @RW5+d8
R1, R5 @RW5+d8
R2, R5 @RW5+d8
R3, R5 @RW5+d8
R4, R5 @RW5+d8
R5, R5 @RW5+d8
R6, R5 @RW5+d8
R7, R5 @RW5+d8
B0
+5
A0
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R4 @RW4+d8
R1, R4 @RW4+d8
R2, R4 @RW4+d8
R3, R4 @RW4+d8
R4, R4 @RW4+d8
R5, R4 @RW4+d8
R6, R4 @RW4+d8
R7, R4 @RW4+d8
90
+4
80
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R3 @RW3+d8
R1, R3 @RW3+d8
R2, R3 @RW3+d8
R3, R3 @RW3+d8
R4, R3 @RW3+d8
R5, R3 @RW3+d8
R6, R3 @RW3+d8
R7, R3 @RW3+d8
70
+3
60
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R2 @RW2+d8
R1, R2 @RW2+d8
R2, R2 @RW2+d8
R3, R2 @RW2+d8
R4, R2 @RW2+d8
R5, R2 @RW2+d8
R6, R2 @RW2+d8
R7, R2 @RW2+d8
50
+2
40
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R1 @RW1+d8
R1, R1 @RW1+d8
R2, R1 @RW1+d8
R3, R1 @RW1+d8
R4, R1 @RW1+d8
R5, R1 @RW1+d8
R6, R1 @RW1+d8
R7, R1 @RW1+d8
30
+1
20
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R0 @RW0+d8
R1, R0 @RW0+d8
R2, R0 @RW0+d8
R3, R0 @RW0+d8
R4, R0 @RW0+d8
R5, R0 @RW0+d8
R6, R0 @RW0+d8
R7, R0 @RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-16 MOV Ri, ea Instruction (First Byte = 7AH)
601
602
MOVW
MOVW RW5,
RW5,@RW3 @RW3+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW0,@RW1 @RW1+d16 RW1,@RW1 @RW1+d16 RW2,@RW1 @RW1+d16 RW3,@RW1 @RW1+d16 RW4,@RW1 @RW1+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW0,@RW2 @RW2+d16 RW1,@RW2 @RW2+d16 RW2,@RW2 @RW2+d16 RW3,@RW2 @RW2+d16 RW4,@RW2 @RW2+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW0,@RW3 @RW3+d16 RW1,@RW3 @RW3+d16 RW2,@RW3 @RW3+d16 RW3,@RW3 @RW3+d16 RW4,@RW3 @RW3+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4, MOVW
MOVW RW5, MOVW
MOVW RW6, MOVW
MOVW RW7,
RW0,@RW0+ @RW0+RW7 RW1,@RW0+ @RW0+RW7 RW2,@RW0+ @RW0+RW7 RW3,@RW0+ @RW0+RW7 RW4,@RW0+ @RW0+RW7 RW5,@RW0+ @RW0+RW7 RW6,@RW0+ @RW0+RW7 RW7,@RW0+ @RW0+RW7
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, @RW2+ @PC+d16
RW2, @RW2+ @PC+d16
RW3, @RW2+ @PC+d16
RW4, @RW2+ @PC+d16
MOVW
MOVW
RW1, @RW3+ RW1, addr16
MOVW
RW0, @RW1+
MOVW
MOVW
RW0, @RW2+ @PC+d16
MOVW
MOVW
RW0, @RW3+ RW0, addr16
+9
+A
+B
+C
+D
+E
+F
MOVW
MOVW
RW2, @RW3+ RW2, addr16
MOVW
MOVW
RW3, @RW3+ RW3, addr16
MOVW
MOVW
RW5, @RW3+ RW5, addr16
MOVW
MOVW
RW5, @RW2+ @PC+d16
MOVW
MOVW
RW6, @RW3+ RW6, addr16
MOVW
MOVW RW6,
RW6, @RW2+ @PC+d16
MOVW
MOVW
RW7, @RW3+ RW7, addr16
MOVW
MOVW RW7,
RW7, @RW2+ @PC+d16
MOVW RW7,
@RW1+RW7
MOVW
MOVW RW7,
RW7,@RW3 @RW3+d16
MOVW
MOVW RW7,
RW7,@RW2 @RW2+d16
MOVW
MOVW RW7,
RW7,@RW1 @RW1+d16
MOVW
MOVW RW7,
RW7,@RW0 @RW0+d16
MOVW
MOVW RW7,
RW7, RW7 @RW7+d8
MOVW
MOVW RW7,
RW7, RW6 @RW6+d8
MOVW
MOVW RW7,
RW7, RW5 @RW5+d8
MOVW
MOVW RW7,
RW7, RW4 @RW4+d8
MOVW RW6, MOVW
@RW1+RW7 RW7, @RW1+
MOVW
MOVW RW6,
RW6,@RW3 @RW3+d16
MOVW
MOVW RW6,
RW6,@RW2 @RW2+d16
MOVW
MOVW RW6,
RW6,@RW1 @RW1+d16
MOVW
MOVW RW6,
RW6,@RW0 @RW0+d16
MOVW
MOVW RW6,
RW6, RW7 @RW7+d8
MOVW
MOVW RW6,
RW6, RW6 @RW6+d8
MOVW
MOVW RW6,
RW6, RW5 @RW5+d8
MOVW
MOVW RW6,
RW6, RW4 @RW4+d8
MOVW
MOVW
@RW1+RW7 RW6, @RW1+
MOVW
MOVW RW5,
RW5, RW6 @RW6+d8
MOVW
MOVW RW5,
RW5, RW5 @RW5+d8
MOVW RW4, MOVW
@RW1+RW7 RW5, @RW1+
MOVW
MOVW
RW4, @RW3+ RW4, addr16
MOVW RW3, MOVW
@RW1+RW7 RW4, @RW1+
MOVW
MOVW RW5,
RW5,@RW2 @RW2+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW0,@RW0 @RW0+d16 RW1,@RW0 @RW0+d16 RW2,@RW0 @RW0+d16 RW3,@RW0 @RW0+d16 RW4,@RW0 @RW0+d16
+8
MOVW RW2, MOVW
@RW1+RW7 RW3, @RW1+
MOVW
MOVW RW5,
RW5,@RW1 @RW1+d16
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW7 @RW7+d8
RW2, RW7 @RW7+d8
RW3, RW7 @RW7+d8
RW4, RW7 @RW7+d8
MOVW
MOVW
RW0, RW7 @RW7+d8
+7
MOVW RW1, MOVW
@RW1+RW7 RW2, @RW1+
MOVW
MOVW RW5,
RW5,@RW0 @RW0+d16
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW6 @RW6+d8
RW2, RW6 @RW6+d8
RW3, RW6 @RW6+d8
RW4, RW6 @RW6+d8
MOVW
MOVW
RW0, RW6 @RW6+d8
+6
MOVW
MOVW
@RW1+RW7 RW1, @RW1+
MOVW
MOVW RW5,
RW5, RW7 @RW7+d8
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW5 @RW5+d8
RW2, RW5 @RW5+d8
RW3, RW5 @RW5+d8
RW4, RW5 @RW5+d8
MOVW
MOVW
RW0, RW5 @RW5+d8
+5
MOVW
MOVW RW5,
RW5, RW4 @RW4+d8
MOVW
MOVW RW7,
RW7, RW3 @RW3+d8
MOVW
MOVW RW7,
RW7, RW2 @RW2+d8
MOVW
MOVW RW7,
RW7, RW1 @RW1+d8
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW4 @RW4+d8
RW2, RW4 @RW4+d8
RW3, RW4 @RW4+d8
RW4, RW4 @RW4+d8
MOVW
MOVW RW6,
RW6, RW3 @RW3+d8
MOVW
MOVW RW6,
RW6, RW2 @RW2+d8
MOVW
MOVW RW6,
RW6, RW1 @RW1+d8
MOVW
MOVW
RW0, RW4 @RW4+d8
MOVW
MOVW RW5,
RW5, RW3 @RW3+d8
MOVW
MOVW RW5,
RW5, RW2 @RW2+d8
MOVW
MOVW RW5,
RW5, RW1 @RW1+d8
+4
F0
MOVW
MOVW RW7,
RW7, RW0 @RW0+d8
E0
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW3 @RW3+d8
RW2, RW3 @RW3+d8
RW3, RW3 @RW3+d8
RW4, RW3 @RW3+d8
D0
MOVW
MOVW RW6,
RW6, RW0 @RW0+d8
C0
MOVW
MOVW
RW0, RW3 @RW3+d8
B0
MOVW
MOVW RW5,
RW5, RW0 @RW0+d8
A0
+3
90
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW2 @RW2+d8
RW2, RW2 @RW2+d8
RW3, RW2 @RW2+d8
RW4, RW2 @RW2+d8
80
MOVW
MOVW
RW0, RW2 @RW2+d8
70
+2
60
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW1 @RW1+d8
RW2, RW1 @RW1+d8
RW3, RW1 @RW1+d8
RW4, RW1 @RW1+d8
50
MOVW
MOVW
RW0, RW1 @RW1+d8
40
+1
30
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW0 @RW0+d8
RW2, RW0 @RW0+d8
RW3, RW0 @RW0+d8
RW4, RW0 @RW0+d8
20
MOVW
MOVW
RW0, RW0 @RW0+d8
10
+0
00
APPENDIX
Table B.9-17 MOVW RWi, ea Instruction (First Byte = 7BH)
+F
+E
+D
+C
+B
+A
+9
+8
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R1 addr16, R1
MOV
MOV
@RW3+, R0 addr16, R0
MOV
MOV
MOV
@RW2+, R1 @PC+d16, R1
@RW2+, R0 @PC+d16, R0
MOV
MOV
MOV
MOV
MOV
@RW0+, R1 @RW0+RW7, R1
MOV
@RW3, R1 @RW3+d16, R1
MOV
@RW2, R1 @RW2+d16, R1
MOV
@RW1, R1 @RW1+d16, R1
MOV
@RW1+, R1 @RW1+RW7, R1
MOV
MOV
@RW0, R1 @RW0+d16, R1
MOV
@RW1+, R0 @RW1+RW7, R0
MOV
@RW0+, R0 @RW0+RW7, R0
MOV
@RW3, R0 @RW3+d16, R0
MOV
@RW2, R0 @RW2+d16, R0
MOV
@RW1, R0 @RW1+d16, R0
MOV
@RW0, R0 @RW0+d16, R0
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R2 addr16, R2
MOV
@RW2+, R2 @PC+d16, R2
MOV
@RW1+, R2 @RW1+RW7, R2
MOV
@RW0+, R2 @RW0+RW7, R2
MOV
@RW3, R2 @RW3+d16, R2
MOV
@RW2, R2 @RW2+d16, R2
MOV
@RW1, R2 @RW1+d16, R2
MOV
@RW0, R2 @RW0+d16, R2
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R3 addr16, R3
MOV
@RW2+, R3 @PC+d16, R3
MOV
@RW1+, R3 @RW1+RW7, R3
MOV
@RW0+, R3 @RW0+RW7, R3
MOV
@RW3, R3 @RW3+d16, R3
MOV
@RW2, R3 @RW2+d16, R3
MOV
@RW1, R3 @RW1+d16, R3
MOV
@RW0, R3 @RW0+d16, R3
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R4 addr16, R4
MOV
@RW2+, R4 @PC+d16, R4
MOV
@RW1+, R4 @RW1+RW7, R4
MOV
@RW0+, R4 @RW0+RW7, R4
MOV
@RW3, R4 @RW3+d16, R4
MOV
@RW2, R4 @RW2+d16, R4
MOV
@RW1, R4 @RW1+d16, R4
MOV
@RW0, R4 @RW0+d16, R4
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R5 addr16, R5
MOV
@RW2+, R5 @PC+d16, R5
MOV
@RW1+, R5 @RW1+RW7, R5
MOV
@RW0+, R5 @RW0+RW7, R5
MOV
@RW3, R5 @RW3+d16, R5
MOV
@RW2, R5 @RW2+d16, R5
MOV
@RW1, R5 @RW1+d16, R5
MOV
@RW0, R5 @RW0+d16, R5
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R6 addr16, R6
MOV
@RW2+, R6 @PC+d16, R6
MOV
@RW1+, R6 @RW1+RW7, R6
MOV
@RW0+, R6 @RW0+RW7, R6
MOV
@RW3, R6 @RW3+d16, R6
MOV
@RW2, R6 @RW2+d16, R6
MOV
@RW1, R6 @RW1+d16, R6
MOV
@RW0, R6 @RW0+d16,
R6
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R7 addr16, R7
MOV
@RW2+, R7 @PC+d16, R7
MOV
@RW1+, R7 @RW1+RW7, R7
MOV
@RW0+, R7 @RW0+RW7, R7
MOV
@RW3, R7 @RW3+d16, R7
MOV
@RW2, R7 @RW2+d16, R7
MOV
@RW1, R7 @RW1+d16, R7
MOV
@RW0, R7 @RW0+d16, R7
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R7, R0 @RW7+d8, R0
R7, R1 @RW7+d8, R1
R7, R2 @RW7+d8, R2
R7, R3 @RW7+d8, R3
R7, R4 @RW7+d8, R4
R7, R5 @RW7+d8, R5
R7, R6 @RW7+d8, R6
R7, R7 @RW7+d8, R7
F0
+7
E0
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R6, R0 @RW6+d8, R0
R6, R1 @RW6+d8, R1
R6, R2 @RW6+d8, R2
R6, R3 @RW6+d8, R3
R6, R4 @RW6+d8, R4
R6, R5 @RW6+d8, R5
R6, R6 @RW6+d8, R6
R6, R7 @RW6+d8, R7
D0
+6
C0
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R5, R0 @RW5+d8, R0
R5, R1 @RW5+d8, R1
R5, R2 @RW5+d8, R2
R5, R3 @RW5+d8, R3
R5, R4 @RW5+d8, R4
R5, R5 @RW5+d8, R5
R5, R6 @RW5+d8, R6
R5, R7 @RW5+d8, R7
B0
+5
A0
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R4, R0 @RW4+d8, R0
R4, R1 @RW4+d8, R1
R4, R2 @RW4+d8, R2
R4, R3 @RW4+d8, R3
R4, R4 @RW4+d8, R4
R4, R5 @RW4+d8, R5
R4, R6 @RW4+d8, R6
R4, R7 @RW4+d8, R7
90
+4
80
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R3, R0 @RW3+d8, R0
R3, R1 @RW3+d8, R1
R3, R2 @RW3+d8, R2
R3, R3 @RW3+d8, R3
R3, R4 @RW3+d8, R4
R3, R5 @RW3+d8, R5
R3, R6 @RW3+d8, R6
R3, R7 @RW3+d8, R7
70
+3
60
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R2, R0 @RW2+d8, R0
R2, R1 @RW2+d8, R1
R2, R2 @RW2+d8, R2
R2, R3 @RW2+d8, R3
R2, R4 @RW2+d8, R4
R2, R5 @RW2+d8, R5
R2, R6 @RW2+d8, R6
R2, R7 @RW2+d8, R7
50
+2
40
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R1, R0 @RW1+d8, R0
R1, R1 @RW1+d8, R1
R1, R2 @RW1+d8, R2
R1, R3 @RW1+d8, R3
R1, R4 @RW1+d8, R4
R1, R5 @RW1+d8, R5
R1, R6 @RW1+d8, R6
R1, R7 @RW1+d8, R7
30
+1
20
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R0, R0 @RW0+d8, R0
R0, R1 @RW0+d8, R1
R0, R2 @RW0+d8, R2
R0, R3 @RW0+d8, R3
R0, R4 @RW0+d8, R4
R0, R5 @RW0+d8, R5
R0, R6 @RW0+d8, R6
R0, R7 @RW0+d8, R7
10
+0
00
APPENDIX B Instructions
Table B.9-18 MOV ea, Ri Instruction (First Byte = 7CH)
603
604
MOVW
[email protected]
@RW2, RW1 +d16, RW1
MOVW
[email protected]
@RW3, RW1 +d16, RW1
MOVW
[email protected]
@RW0+, RW1 +RW7,RW1
MOVW
[email protected]
@RW1+,RW1 +RW7,RW1
MOVW
[email protected]
@RW2+,RW1 +d16, RW1
MOVW
MOVW
@RW3+,RW1 addr16, RW1
MOVW
[email protected]
@RW2, RW0 +d16, RW0
MOVW
[email protected]
@RW3, RW0 +d16, RW0
MOVW
[email protected]
@RW0+,RW0 +RW7,RW0
MOVW
[email protected]
@RW1+,RW0 +RW7,RW0
MOVW
[email protected]
@RW2+,RW0 +d16, RW0
MOVW
MOVW
@RW3+,RW0 addr16, RW0
+B
+C
+D
+E
+F
MOVW
MOVW
@RW3+,RW2 addr16, RW2
MOVW
[email protected]
@RW2+,RW2 +d16, RW2
MOVW
[email protected]
@RW1+,RW2 +RW7,RW2
MOVW
[email protected]
@RW0+,RW2 +RW7,RW2
MOVW
[email protected]
@RW3, RW2 +d16, RW2
MOVW
[email protected]
@RW2, RW2 +d16, RW2
MOVW
MOVW
@RW3+,RW3 addr16, RW3
MOVW
[email protected]
@RW2+,RW3 +d16, RW3
MOVW
[email protected]
@RW1+,RW3 -+RW7,RW3
MOVW
[email protected]
@RW0+,RW3 +RW7,RW3
MOVW
[email protected]
@RW3, RW3 +d16, RW3
MOVW
[email protected]
@RW2, RW3 +d16, RW3
MOVW
[email protected]
@RW1, RW3 +d16, RW3
MOVW
MOVW
@RW3+,RW4 addr16, RW4
MOVW
[email protected]
@RW2+,RW4 +d16, RW4
MOVW
[email protected]
@RW1+,RW4 +RW7,RW4
MOVW
[email protected]
@RW0+,RW4 +RW7,RW4
MOVW
[email protected]
@RW3, RW4 +d16, RW4
MOVW
[email protected]
@RW2, RW4 +d16, RW4
MOVW
[email protected]
@RW1, RW4 +d16, RW4
MOVW
MOVW
@RW3+,RW5 addr16, RW5
MOVW
[email protected]
@RW2+,RW5 +d16, RW5
MOVW
[email protected]
@RW1+,RW5 +RW7,RW5
MOVW
[email protected]
@RW0+,RW5 +RW7,RW5
MOVW
[email protected]
@RW3, RW5 +d16, RW5
MOVW
[email protected]
@RW2, RW5 +d16, RW5
MOVW
[email protected]
@RW1, RW5 +d16, RW5
MOVW
MOVW
@RW3+,RW6 addr16, RW6
MOVW
MOVW @PC
@RW2+,RW6 +d16, RW6
MOVW
[email protected]
@RW1+,RW6 +RW7,RW6
MOVW
[email protected]
@RW0+,RW6 +RW7,RW6
MOVW
[email protected]
@RW3, RW6 +d16, RW6
MOVW
[email protected]
@RW2, RW6 +d16, RW6
MOVW
[email protected]
@RW1, RW6 +d16, RW6
MOVW
MOVW
@RW3+,RW7 addr16, RW7
MOVW
[email protected]
@RW2+,RW7 +d16, RW7
MOVW
[email protected]
@RW1+,RW7 +RW7,RW7
MOVW
[email protected]
@RW0+,RW7 +RW7,RW7
MOVW
[email protected]
@RW3, RW7 +d16, RW7
MOVW
[email protected]
@RW2, RW7 +d16, RW7
MOVW
[email protected]
@RW1, RW7 +d16, RW7
MOVW
[email protected]
@RW0, RW7 +d16, RW7
+A
MOVW
[email protected]
@RW1, RW2 +d16, RW2
MOVW
[email protected]
@RW0, RW6 +d16, RW6
MOVW
[email protected]
@RW1, RW1 +d16, RW1
MOVW
[email protected]
@RW0, RW5 +d16, RW5
MOVW
[email protected]
@RW1, RW0 +d16, RW0
MOVW
[email protected]
@RW0, RW4 +d16, RW4
+9
MOVW
[email protected]
@RW0, RW3 +d16, RW3
MOVW
[email protected]
@RW0, RW1 +d16, RW1
MOVW
[email protected]
@RW0, RW0 +d16, RW0
+8
MOVW
[email protected]
@RW0, RW2 +d16, RW2
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW7, RW0 @RW7+d8, RW0
RW7, RW1 @RW7+d8, RW1 RW7, RW2 @RW7+d8, RW2 RW7, RW3 @RW7+d8, RW3 RW7, RW4 @RW7+d8, RW4 RW7, RW5 @RW7+d8, RW5 RW7, RW6 @RW7+d8, RW6 RW7, RW7 @RW7+d8, RW7
F0
+7
E0
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW6, RW0 @RW6+d8, RW0
RW6, RW1 @RW6+d8, RW1 RW6, RW2 @RW6+d8, RW2 RW6, RW3 @RW6+d8, RW3 RW6, RW4 @RW6+d8, RW4 RW6, RW5 @RW6+d8, RW5 RW6, RW6 @RW6+d8, RW6 RW6, RW7 @RW6+d8, RW7
D0
+6
C0
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW5, RW0 @RW5+d8, RW0
RW5, RW1 @RW5+d8, RW1 RW5, RW2 @RW5+d8, RW2 RW5, RW3 @RW5+d8, RW3 RW5, RW4 @RW5+d8, RW4 RW5, RW5 @RW5+d8, RW5 RW5, RW6 @RW5+d8, RW6 RW5, RW7 @RW5+d8, RW7
B0
+5
A0
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW4, RW0 @RW4+d8, RW0
RW4, RW1 @RW4+d8, RW1 RW4, RW2 @RW4+d8, RW2 RW4, RW3 @RW4+d8, RW3 RW4, RW4 @RW4+d8, RW4 RW4, RW5 @RW4+d8, RW5 RW4, RW6 @RW4+d8, RW6 RW4, RW7 @RW4+d8, RW7
90
+4
80
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW3, RW0 @RW3+d8, RW0
RW3, RW1 @RW3+d8, RW1 RW3, RW2 @RW3+d8, RW2 RW3, RW3 @RW3+d8, RW3 RW3, RW4 @RW3+d8, RW4 RW3, RW5 @RW3+d8, RW5 RW3, RW6 @RW3+d8, RW6 RW3, RW7 @RW3+d8, RW7
70
+3
60
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW2, RW0 @RW2+d8, RW0
RW2, RW1 @RW2+d8, RW1 RW2, RW2 @RW2+d8, RW2 RW2, RW3 @RW2+d8, RW3 RW2, RW4 @RW2+d8, RW4 RW2, RW5 @RW2+d8, RW5 RW2, RW6 @RW2+d8, RW6 RW2, RW7 @RW2+d8, RW7
50
+2
40
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW1, RW0 @RW1+d8, RW0
RW1, RW1 @RW1+d8, RW1 RW1, RW2 @RW1+d8, RW2 RW1, RW3 @RW1+d8, RW3 RW1, RW4 @RW1+d8, RW4 RW1, RW5 @RW1+d8, RW5 RW1, RW6 @RW1+d8, RW6 RW1, RW7 @RW1+d8, RW7
30
+1
20
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW0, RW0 @RW0+d8, RW0
RW0, RW1 @RW0+d8, RW1 RW0, RW2 @RW0+d8, RW2 RW0, RW3 @RW0+d8, RW3 RW0, RW4 @RW0+d8, RW4 RW0, RW5 @RW0+d8, RW5 RW0, RW6 @RW0+d8, RW6 RW0, RW7 @RW0+d8, RW7
10
+0
00
APPENDIX
Table B.9-19 MOVW ea, Rwi Instruction (First Byte = 7DH)
XCH
XCH
XCH
XCH
R1,
XCH
XCH
R2,
XCH
XCH
R3,
XCH
XCH
R4,
XCH
XCH
R5,
XCH
XCH
R6,
XCH
XCH
R7,
XCH
XCH
R1,
XCH
XCH
R2,
XCH
XCH
R3,
XCH
XCH
R4,
XCH
XCH
R5,
XCH
XCH
R6,
XCH
XCH
R7,
XCH
XCH
XCH
XCH
XCH
R1, XCH
XCH
R2, XCH
XCH
R3, XCH
XCH
R4, XCH
XCH
R5, XCH
XCH
R6, XCH
XCH
R7,
+F R0,@RW3+ R0, addr16
XCH
XCH
R1,@RW3+ R1, addr16
XCH
XCH
R2,@RW3+ R2, addr16
XCH
XCH
R3,@RW3+ R3, addr16
XCH
XCH
R4,@RW3+ R4, addr16
XCH
XCH
R5,@RW3+ R5, addr16
XCH
XCH
R6,@RW3+ R6, addr16
XCH
XCH
R7,@RW3+ R7, addr16
+E R0,@RW2+ @PC+d16 R1,@RW2+ @PC+d16 R2,@RW2+ @PC+d16 R3,@RW2+ @PC+d16 R4,@RW2+ @PC+d16 R5,@RW2+ @PC+d16 R6,@RW2+ @PC+d16 R7,@RW2+ @PC+d16
R0, XCH
XCH R0,
XCH
XCH R1,
XCH
XCH R2,
XCH
XCH R3,
XCH
XCH R4,
XCH
XCH R5,
XCH
XCH R6,
XCH
XCH R7,
@RW1+RW7 R1,@RW1+ @RW1+RW7 R2,@RW1+ @RW1+RW7 R3,@RW1+ @RW1+RW7 R4,@RW1+ @RW1+RW7 R5,@RW1+ @RW1+RW7 R6,@RW1+ @RW1+RW7 R7,@RW1+ @RW1+RW7
+D R0,@RW1+
XCH
XCH R0,
XCH
XCH R1,
XCH
XCH R2,
XCH
XCH R3,
XCH
XCH R4,
XCH
XCH R5,
XCH
XCH R6,
XCH
XCH R7,
@RW0+RW7 R1,@RW0+ @RW0+RW7 R2,@RW0+ @RW0+RW7 R3,@RW0+ @RW0+RW7 R4,@RW0+ @RW0+RW7 R5,@RW0+ @RW0+RW7 R6,@RW0+ @RW0+RW7 R7,@RW0+ @RW0+RW7
XCH
+C R0,@RW0+
+B R0,@RW3 @RW3+d16 R1,@RW3 @RW3+d16 R2,@RW3 @RW3+d16 R3,@RW3 @RW3+d16 R4,@RW3 @RW3+d16 R5,@RW3 @RW3+d16 R6,@RW3 @RW3+d16 R7,@RW3 @RW3+d16
R0,
+A R0,@RW2 @RW2+d16 R1,@RW2 @RW2+d16 R2,@RW2 @RW2+d16 R3,@RW2 @RW2+d16 R4,@RW2 @RW2+d16 R5,@RW2 @RW2+d16 R6,@RW2 @RW2+d16 R7,@RW2 @RW2+d16
R0,
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0,@RW1 @RW1+d16 R1,@RW1 @RW1+d16 R2,@RW1 @RW1+d16 R3,@RW1 @RW1+d16 R4,@RW1 @RW1+d16 R5,@RW1 @RW1+d16 R6,@RW1 @RW1+d16 R7,@RW1 @RW1+d16
+9
XCH
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0,@RW0 @RW0+d16 R1,@RW0 @RW0+d16 R2,@RW0 @RW0+d16 R3,@RW0 @RW0+d16 R4,@RW0 @RW0+d16 R5,@RW0 @RW0+d16 R6,@RW0 @RW0+d16 R7,@RW0 @RW0+d16
+8
XCH
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R7 @RW7+d8
R1, R7 @RW7+d8
R2, R7 @RW7+d8
R3, R7 @RW7+d8
R4, R7 @RW7+d8
R5, R7 @RW7+d8
R6, R7 @RW7+d8
R7, R7 @RW7+d8
F0
+7
E0
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R6 @RW6+d8
R1, R6 @RW6+d8
R2, R6 @RW6+d8
R3, R6 @RW6+d8
R4, R6 @RW6+d8
R5, R6 @RW6+d8
R6, R6 @RW6+d8
R7, R6 @RW6+d8
D0
+6
C0
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R5 @RW5+d8
R1, R5 @RW5+d8
R2, R5 @RW5+d8
R3, R5 @RW5+d8
R4, R5 @RW5+d8
R5, R5 @RW5+d8
R6, R5 @RW5+d8
R7, R5 @RW5+d8
B0
+5
A0
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R4 @RW4+d8
R1, R4 @RW4+d8
R2, R4 @RW4+d8
R3, R4 @RW4+d8
R4, R4 @RW4+d8
R5, R4 @RW4+d8
R6, R4 @RW4+d8
R7, R4 @RW4+d8
90
+4
80
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R3 @RW3+d8
R1, R3 @RW3+d8
R2, R3 @RW3+d8
R3, R3 @RW3+d8
R4, R3 @RW3+d8
R5, R3 @RW3+d8
R6, R3 @RW3+d8
R7, R3 @RW3+d8
70
+3
60
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R2 @RW2+d8
R1, R2 @RW2+d8
R2, R2 @RW2+d8
R3, R2 @RW2+d8
R4, R2 @RW2+d8
R5, R2 @RW2+d8
R6, R2 @RW2+d8
R7, R2 @RW2+d8
50
+2
40
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R1 @RW1+d8
R1, R1 @RW1+d8
R2, R1 @RW1+d8
R3, R1 @RW1+d8
R4, R1 @RW1+d8
R5, R1 @RW1+d8
R6, R1 @RW1+d8
R7, R1 @RW1+d8
30
+1
20
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R0 @RW0+d8
R1, R0 @RW0+d8
R2, R0 @RW0+d8
R3, R0 @RW0+d8
R4, R0 @RW0+d8
R5, R0 @RW0+d8
R6, R0 @RW0+d8
R7, R0 @RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-20 XCH Ri, ea Instruction (First Byte = 7EH)
605
606
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW2+ @PC+d16
RW1,@RW2+ @PC+d16
RW2,@RW2+ @PC+d16
RW3,@RW2+ @PC+d16
RW4,@RW2+ @PC+d16
RW5,@RW2+ @PC+d16
RW6,@RW2+ @PC+d16
RW7,@RW2+ @PC+d16
XCHW
XCHW
RW0,@RW3+ RW0, addr16
+E
+F
XCHW
XCHW
RW7,@RW3+ RW7, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW1+ @RW1+RW7 RW1,@RW1+ @RW1+RW7 RW2,@RW1+ @RW1+RW7 RW3,@RW1+ @RW1+RW7 RW4,@RW1+ @RW1+RW7 RW5,@RW1+ @RW1+RW7 RW6,@RW1+ @RW1+RW7 RW7,@RW1+ @RW1+RW7
+D
XCHW
XCHW
RW6,@RW3+ RW6, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW0+ @RW0+RW7 RW1,@RW0+ @RW0+RW7 RW2,@RW0+ @RW0+RW7 RW3,@RW0+ @RW0+RW7 RW4,@RW0+ @RW0+RW7 RW5,@RW0+ @RW0+RW7 RW6,@RW0+ @RW0+RW7 RW7,@RW0+ @RW0+RW7
+C
XCHW
XCHW
RW5,@RW3+ RW5, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW3 @RW3+d16
RW1,@RW3 @RW3+d16
RW2,@RW3 @RW3+d16
RW3,@RW3 @RW3+d16
RW4,@RW3 @RW3+d16
RW5,@RW3 @RW3+d16
RW6,@RW3 @RW3+d16
RW7,@RW3 @RW3+d16
+B
XCHW
XCHW
RW4,@RW3+ RW4, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW2 @RW2+d16
RW1,@RW2 @RW2+d16
RW2,@RW2 @RW2+d16
RW3,@RW2 @RW2+d16
RW4,@RW2 @RW2+d16
RW5,@RW2 @RW2+d16
RW6,@RW2 @RW2+d16
RW7,@RW2 @RW2+d16
+A
XCHW
XCHW
RW3,@RW3+ RW3, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW1 @RW1+d16
RW1,@RW1 @RW1+d16
RW2,@RW1 @RW1+d16
RW3,@RW1 @RW1+d16
RW4,@RW1 @RW1+d16
RW5,@RW1 @RW1+d16
RW6,@RW1 @RW1+d16
RW7,@RW1 @RW1+d16
+9
XCHW
XCHW
RW2,@RW3+ RW2, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW0 @RW0+d16
RW1,@RW0 @RW0+d16
RW2,@RW0 @RW0+d16
RW3,@RW0 @RW0+d16
RW4,@RW0 @RW0+d16
RW5,@RW0 @RW0+d16
RW6,@RW0 @RW0+d16
RW7,@RW0 @RW0+d16
+8
XCHW
XCHW
RW1,@RW3+ RW1, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW7 @RW7+d8
RW1, RW7 @RW7+d8
RW2, RW7 @RW7+d8
RW3, RW7 @RW7+d8
RW4, RW7 @RW7+d8
RW5, RW7 @RW7+d8
RW6, RW7 @RW7+d8
RW7, RW7 @RW7+d8
F0
+7
E0
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW6 @RW6+d8
RW1, RW6 @RW6+d8
RW2, RW6 @RW6+d8
RW3, RW6 @RW6+d8
RW4, RW6 @RW6+d8
RW5, RW6 @RW6+d8
RW6, RW6 @RW6+d8
RW7, RW6 @RW6+d8
D0
+6
C0
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW5 @RW5+d8
RW1, RW5 @RW5+d8
RW2, RW5 @RW5+d8
RW3, RW5 @RW5+d8
RW4, RW5 @RW5+d8
RW5, RW5 @RW5+d8
RW6, RW5 @RW5+d8
RW7, RW5 @RW5+d8
B0
+5
A0
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW4 @RW4+d8
RW1, RW4 @RW4+d8
RW2, RW4 @RW4+d8
RW3, RW4 @RW4+d8
RW4, RW4 @RW4+d8
RW5, RW4 @RW4+d8
RW6, RW4 @RW4+d8
RW7, RW4 @RW4+d8
90
+4
80
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW3 @RW3+d8
RW1, RW3 @RW3+d8
RW2, RW3 @RW3+d8
RW3, RW3 @RW3+d8
RW4, RW3 @RW3+d8
RW5, RW3 @RW3+d8
RW6, RW3 @RW3+d8
RW7, RW3 @RW3+d8
70
+3
60
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW2 @RW2+d8
RW1, RW2 @RW2+d8
RW2, RW2 @RW2+d8
RW3, RW2 @RW2+d8
RW4, RW2 @RW2+d8
RW5, RW2 @RW2+d8
RW6, RW2 @RW2+d8
RW7, RW2 @RW2+d8
50
+2
40
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW1 @RW1+d8
RW1, RW1 @RW1+d8
RW2, RW1 @RW1+d8
RW3, RW1 @RW1+d8
RW4, RW1 @RW1+d8
RW5, RW1 @RW1+d8
RW6, RW1 @RW1+d8
RW7, RW1 @RW1+d8
30
+1
20
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW0 @RW0+d8
RW1, RW0 @RW0+d8
RW2, RW0 @RW0+d8
RW3, RW0 @RW0+d8
RW4, RW0 @RW0+d8
RW5, RW0 @RW0+d8
RW6, RW0 @RW0+d8
RW7, RW0 @RW0+d8
10
+0
00
APPENDIX
Table B.9-21 XCHW RWi, ea Instruction (First Byte = 7FH)
INDEX
INDEX
The index follows on the next page.
This is listed in alphabetic order.
607
INDEX
Index
Numerics
A
1/2 Biases
1/2 Biases 1/2-duty Power Output Corrugated Sheet
.......................................................... 474
1/2-duty Power Output
1/2 Biases 1/2-duty Power Output Corrugated Sheet
.......................................................... 474
1/3 Biases
1/3 Biases 1/3-duty Output Corrugated Sheet ...... 477
1/3 Biases 1/4-duty Output Corrugated Sheet ...... 480
16-bit Free-run Timer
Explanation of Operation of 16-bit Free-run Timer
.......................................................... 313
Interruption of 16-bit Free-run Timer ................. 309
Interruption of 16-bit Free-run Timer and EI2OS. 309
List of Register in 16-bit Free-run Timer ............ 296
16-bit Reload Register
16-bit Reload Register (TMRLR)....................... 280
16-bit Reload Timer
16-bit Reload Timer Notes On Use .................... 292
Baud Rate by Internal Timer (16-bit Reload Timer)
.......................................................... 364
Block Diagram for Pins of 16-bit Reload Timer .. 273
Block Diagram of 16-bit Reload Timer............... 271
EI2OS Function of 16-bit Reload Timer.............. 281
Interrupts of 16-bit Reload Timer....................... 281
Interrupts of 16-bit Reload Timer and EI2OS ...... 281
List of Register of 16-bit Reload Timer .............. 274
Operation Modes of 16-bit Reload Timer............ 268
Pins of 16-bit Reload Timer .............................. 273
Setting of 16-bit Reload Timer .......................... 282
16-bit Timer Register
16-bit Timer Register (TMR)............................. 279
24-bit Operand
Linear Addressing by Specifying 24-bit Operand .. 32
2M-bit Flash Memory
Features of 2M-bit Flash Memory ...................... 510
8/10-bit A/D Converter
8/10-bit A/D Converter Interrupt and EI2OS ....... 442
Block Diagram of 8/10-bit A/D Converter .......... 429
Block Diagram of Pins of 8/10-bit A/D Converter432
EI2OS Function of 8/10-bit A/D Converter ......... 442
Function of 8/10-bit A/D Converter ................... 428
Interrupt of 8/10-bit A/D Converter.................... 442
Pins of 8/10-bit A/D Converter .......................... 431
Register List of 8/10-bit A/D Converter.............. 433
A
608
Accumulator (A)................................................ 40
A/D Control Status Register
A/D Control Status Register 0(ADCS0) ............. 436
A/D Control Status Register 1(ADCS1) ............. 434
A/D Converter
Block Diagram of 8/10-bit A/D Converter.......... 429
Block Diagram of Pins of 8/10-bit A/D Converter432
Function of 8/10-bit A/D Converter ................... 428
Pin handling when no A/D Converter is Used ....... 22
Pins of 8/10-bit A/D Converter.......................... 431
Procedure of A/D Converter/Analog Input Power-on
........................................................... 21
Register List of 8/10-bit A/D Converter ............. 433
A/D Data Register
A/D Data Register (ADCR0/ADCR1)................ 438
A/D-converted Data
A/D-converted Data Protection Function............ 446
Access Space
Bank Registers and Access Space ........................ 33
Accumulator
Accumulator (A)................................................ 40
Acknowledge
Acknowledge .................................................. 419
ADB
Bank Register
(PCB, DTB, USB, SSB, and ADB)......... 52
Bank Select Prefix (PCB, DTB, ADB, SPB)......... 57
ADCR
A/D Data Register (ADCR0/ADCR1)................ 438
ADCS
A/D Control Status Register 0(ADCS0) ............. 436
A/D Control Status Register 1(ADCS1) ............. 434
Address Match Detection
Block Diagram of Address Match Detection Function
......................................................... 496
Operation of Address Match Detection Function. 500
Register List of Address Match Detection Function
......................................................... 497
Addressing
Addressing .............................................. 418, 548
Addressing by Indirect-specifying
32-bit Register ...................................... 32
Bank Addressing and Default Space .................... 34
Direct Addressing ............................................ 550
Indirect Addressing .......................................... 556
Linear Addressing and Bank Addressing .............. 31
Linear Addressing by Specifying 24-bit Operand .. 32
INDEX
ADMR
Analog to Digital Conversion Channel Set Register
(ADMR) ............................................ 440
Analog Input
Procedure of A/D Converter/Analog Input Power-on
............................................................ 21
Analog to Digital Conversion Channel Set Register
Analog to Digital Conversion Channel Set Register
(ADMR) ............................................ 440
Any Data
Erasing Any Data in Flash Memory (Sector Erasing)
.......................................................... 521
Arbitration
Arbitration....................................................... 419
Asynchronous Mode
Operation in Asynchronous Mode ..................... 369
B
Bank Addressing
Bank Addressing and Default Space .................... 34
Linear Addressing and Bank Addressing .............. 31
Bank Register
Bank Register
(PCB, DTB, USB, SSB, and ADB) ......... 52
Bank Registers and Access Space ........................ 33
Bank Select Prefix
Bank Select Prefix (PCB, DTB, ADB, SPB) ......... 57
BAP
Buffer Address Pointer (BAP) ........................... 146
Baud Rate
Baud Rate by Dedicated Baud Rate Generator .... 362
Baud Rate by External Clock ............................ 366
Baud Rate by Internal Timer (16-bit Reload Timer)
.......................................................... 364
UART Baud Rate Setting.................................. 360
Bidirectional Communication
Bidirectional Communication Function .............. 374
Block Diagram
Block Diagram ............................................ 7, 295
Block Diagram for Pins of 16-bit Reload Timer .. 273
Block Diagram of 16-bit Reload Timer .............. 271
Block Diagram of 8/10-bit A/D Converter .......... 429
Block Diagram of Address Match Detection Function
.......................................................... 496
Block Diagram of Clock Generation Section ........ 77
Block Diagram of Delayed Interrupt Generation
Module .............................................. 490
Block Diagram of External Reset Pin ................... 67
Block Diagram of I2C Interface ......................... 403
Block Diagram of Low-power Consumption Control
Circuit.................................................. 93
Block Diagram of Pins of 8/10-bit A/D Converter432
Block Diagram of Pins Related to LCD Controller/
Driver ................................................ 459
Block Diagram of PPG Timer ............................320
Block Diagram of ROM Mirror Function Selection
Module ...............................................506
Block Diagram of Serial I/O ..............................220
Block Diagram of the DTP/External Interrupt Circuit
..........................................................384
Block Diagram of the Timer Clock Output Circuit
..........................................................485
Block Diagram of Timebase Timer.....................240
Block Diagram of UART Pins ...........................341
Block Diagram of Watch Timer .........................263
Block Diagram of Watchdog Timer....................254
The Block Diagram of the DTP/External Interrupt
Circuit Terminal Part ...........................386
UART Block Diagram ......................................338
Buffer Address Pointer
Buffer Address Pointer (BAP) ...........................146
Bus Error
Bus Error .........................................................419
Bus Modes
Bus Modes .......................................................160
Bus Modes Setting Bit
Bus Modes Setting Bit ......................................162
C
Calculating
Calculating the Execution Cycle Count...............565
CCR
Configuration of Condition Code Register
(CCR)...................................................46
CDCR
Communication Prescaler Control Register (CDCR0/
CDCR1) .............................................353
Chip Erase
Erasing Data from Flash Memory (Chip Erase) ...520
CKSCR
Clock Select Register (CKSCR) Configuration......79
Clock
Overview of Clock..............................................76
Clock Generation
Block Diagram of Clock Generation Section .........77
Clock Mode
Clock Mode .......................................................91
Event Count Mode (External Clock Mode)..........269
External Shift Clock Mode ................................230
Internal Clock Mode .........................................268
Internal Shift Clock Mode .................................230
Transition of Clock Mode....................................82
Clock Select Register
Clock Select Register (CKSCR) Configuration......79
Clock Source
Indicating Function of Clock Source in Watchdog
Timer .................................................266
609
INDEX
Clock Supply
Clock Supply Map.............................................. 23
Function of Clock Supply.......................... 238, 246
CMR
Common Register Bank Prefix (CMR) ................. 58
Command Sequence
Command Sequence Table ................................ 515
Common Register Bank Prefix
Common Register Bank Prefix (CMR) ................. 58
Communication
Bidirectional Communication Function .............. 374
Master/Slave Mode Communication Function..... 376
Communication Prescaler Control Register
Communication Prescaler Control Register (CDCR0/
CDCR1) ............................................. 353
Compare Clear Register
Compare Clear Register (CPCLR) ..................... 299
Condition Code Register
Configuration of Condition Code Register
(CCR) .................................................. 46
Configuration
Configuration................................................... 294
Connection Example
LCD Panel Connection Example and Display Data
Example (1/2 duty driving type) ........... 476
Serial Write Connection Example (Supplying power
from writer) ........................................ 532
Consumption
CPU Operation Modes and Current Consumption.. 90
Continuous Conversion Mode
Operation of Continuous Conversion Mode ........ 443
Control Register
Control Register (SCR0/SCR1) ......................... 343
Conversion
Conversion Using EI2OS .................................. 445
Conversion Mode
Operation of Continuous Conversion Mode ........ 443
Operation of Single Conversion Mode................ 443
Counter
Counter Operation State.................................... 282
Counter Operation
Counter Operation ............................................ 269
CPCLR
Compare Clear Register (CPCLR) ..................... 299
CPU
CPU.................................................................. 26
CPU Intermittent Operation Mode ................. 91, 98
CPU Operation Modes and Current Consumption.. 90
Crystal Oscillator
Crystal Oscillator Circuit .................................... 21
Current Consumption
CPU Operation Modes and Current Consumption.. 90
610
D
Data Counter
Data Counter (DCT)......................................... 145
DCT
Data Counter (DCT)......................................... 145
DDR
Operations of the Shared Resource Ports Set as Output
Port by DDR Register.......................... 167
Dedicated Baud Rate
Baud Rate by Dedicated Baud Rate Generator .... 362
Dedicated Registers
Configuration of Dedicated Registers................... 38
Dedicated Registers and
General-purpose Register....................... 37
Default Space
Bank Addressing and Default Space .................... 34
Delay Interruption
Delay Interruption Generation Module Notes on Use
......................................................... 493
Delay Interruption Factor Generation/Release
Register
Delay Interruption Factor Generation/Release
Register (DIRR).................................. 491
Delayed Interrupt Generation Module
Block Diagram of Delayed Interrupt Generation
Module .............................................. 490
Operation of Delayed Interrupt Generation Module
......................................................... 492
Description
Description of Instruction Presentation Items and
Symbols ............................................. 568
Descriptor
Configuration of Extended Intelligent I/O Service
(EI2OS) Descriptor (ISD) .................... 144
Direct Addressing
Direct Addressing ............................................ 550
Direct Page Register
Direct Page Register (DPR) ................................ 51
DIRR
Delay Interruption Factor Generation/Release
Register (DIRR).................................. 491
Display Data Example
LCD Panel Connection Example and Display Data
Example (1/4 duty driving type) ........... 482
Display RAM
Display RAM and Output Terminal ................... 468
DPR
Direct Page Register (DPR) ................................ 51
Drive Waveform
Drive Waveform for the LCD ........................... 473
DTB
Bank Register (PCB, DTB, USB, SSB,
and ADB)............................................. 52
INDEX
Bank Select Prefix (PCB, DTB, ADB, SPB) ......... 57
DTP
Block Diagram of the DTP/External Interrupt Circuit
.......................................................... 384
DTP/External Interrupt Circuit and EI2OS.......... 383
DTP/External Interrupt Function ....................... 382
DTP/External Interrupt Operation...................... 396
DTP/External Interrupt Setting .......................... 395
Notes on Using DTP/External Interrupt Circuit ... 399
Operating Explanation of DTP Function............. 398
Pins of DTP/External Interrupt Circuit ............... 386
Register for DTP/External Interrupt Circuit ........ 387
The Block Diagram of the DTP/External Interrupt
Circuit Terminal Part........................... 386
DTP/External Interruption Factor Register
DTP/External Interruption Factor Register (EIRR)
.......................................................... 388
DTP/External Interruption Permission Register
DTP/External Interruption Permission Register
(ENIR)............................................... 391
duty
LCD Panel Connection Example and Display Data
Example (1/2 duty driving type) ........... 476
E
E2PROM
E2PROM Memory Map .................................... 501
Effective Address Field
Effective Address Field ............................ 549, 567
EI2OS
8/10-bit A/D Converter Interrupt and EI2OS ....... 442
Configuration of Extended Intelligent I/O Service
(EI2OS) Descriptor (ISD)..................... 144
Conversion Using EI2OS .................................. 445
DTP/External Interrupt Circuit and EI2OS.......... 383
EI2OS Function of 16-bit Reload Timer ............. 281
EI2OS Function of 8/10-bit A/D Converter......... 442
EI2OS Function of Output Compare................... 311
EI2OS Functions of Input Capture ..................... 310
Example Program of Extended Intelligent I/O Service
(EI2OS).............................................. 156
Extended Intelligent I/O Service (EI2OS) ........... 142
Extended Intelligent I/O Service (EI2OS) Processing
Time (time for one transfer) ................. 149
Interrupt and EI2OS of Output Compare............. 311
Interrupt of Timebase Timer and EI2OS ............. 244
Interrupt Related to UART1 and EI2OS ............. 356
Interruption and EI2OS which Relates to
UART................................................ 337
Interruption of 16-bit Free-run Timer and
EI2OS ................................................ 309
Interruption of Input Capture and EI2OS ............ 310
Interruption of PPG Timer and EI2OS................ 319
Interrupts of 16-bit Reload Timer and EI2OS ...... 281
Operation of Extended Intelligent I/O Service
(EI2OS) ......................................143, 147
Procedure for use of Extended Intelligent I/O Service
(EI2OS) ..............................................148
UART EI2OS Function .....................................356
EI2OS Status Register
EI2OS Status Register (ISCS) ............................145
EIRR
DTP/External Interruption Factor Register (EIRR)
..........................................................388
ELVR
Request Level Setting Register (ELVR)..............393
ENIR
DTP/External Interruption Permission Register
(ENIR) ...............................................391
Erase
The Flash Memory Sector Erase Resumption ......524
Erasing
Sector Erasing Suspension.................................523
Erasing Any Data
Erasing Any Data in Flash Memory (Sector Erasing)
..........................................................521
Erasing Data
Erasing Data from Flash Memory (Chip Erase) ...520
Event Count
Event Count Mode............................................290
Event Count Mode (External Clock Mode)..........269
Example Program
Example Program of Extended Intelligent I/O Service
(EI2OS) ..............................................156
Exception Processing
Exception Processing ........................................152
Execution Cycle Count
Calculating the Execution Cycle Count...............565
Execution Cycle Count......................................564
Extended Intelligent I/O
Extended Intelligent I/O Service (EI2OS)............142
Extended Intelligent I/O Service (EI2OS) Processing
Time (time for one transfer) ..................149
Extended Intelligent I/O Service
Configuration of Extended Intelligent I/O Service
(EI2OS) Descriptor (ISD) .....................144
Example Program of Extended Intelligent I/O Service
(EI2OS) ..............................................156
Operation of Extended Intelligent I/O Service
(EI2OS) ......................................143, 147
Procedure for use of Extended Intelligent I/O Service
(EI2OS) ..............................................148
External Clock
Baud Rate by External Clock .............................366
Connection of Oscillator and External Clock .........87
External Clock Mode
Event Count Mode (External Clock Mode)..........269
611
INDEX
External Division Register
External Division Register of LCD Controller/Driver
.......................................................... 456
External Interrupt
Block Diagram of the DTP/External Interrupt Circuit
.......................................................... 384
DTP/External Interrupt Circuit and EI2OS .......... 383
DTP/External Interrupt Function........................ 382
DTP/External Interrupt Operation ...................... 396
DTP/External Interrupt Setting .......................... 395
External Interrupt Function ............................... 397
Notes on Using DTP/External Interrupt Circuit ... 399
Pins of DTP/External Interrupt Circuit ............... 386
Register for DTP/External Interrupt Circuit ........ 387
The Block Diagram of the DTP/External Interrupt
Circuit Terminal Part ........................... 386
External Reset
Block Diagram of External Reset Pin ................... 67
External Shift Clock Mode
External Shift Clock Mode ................................ 230
F
F2MC-16LX Instruction List
F2MC-16LX Instruction List............................. 571
Fetch
Mode Fetch........................................................ 68
Flag Change Inhibit Prefix
Flag Change Inhibit Prefix (NCC)........................ 59
Flag Set Timing
Receive Interrupt Generation and Flag Set Timing
.......................................................... 357
Transmit Interrupt Generation and Flag Set Timing
.......................................................... 359
Flash Memory
Details of Programming/Erasing Flash Memory .. 516
Erasing Any Data in Flash Memory (Sector Erasing)
.......................................................... 521
Erasing Data from Flash Memory (Chip Erase) ... 520
Features of 2M-bit Flash Memory ...................... 510
Read/Reset State in Flash Memory..................... 517
Register of Flash Memory ................................. 511
Writing Data in Flash Memory .......................... 518
Flash Memory Control Status Register
Flash Memory Control Status Register
(FMCS) .............................................. 512
Flash Microcontroller Programmer
Example of Minimum Connection to Flash
Microcontroller Programmer (User Power
Supply Used) ...................................... 534
FMCS
Flash Memory Control Status Register (FMCS) .. 512
FPT-100P-M06
FPT-100P-M06 Package Dimensions ..................... 8
612
Free-run Timer
Explanation of Operation of 16-bit Free-run Timer
......................................................... 313
Interruption of 16-bit Free-run Timer ................. 309
Interruption of 16-bit Free-run Timer and
EI2OS ................................................ 309
List of Register in 16-bit Free-run Timer ............ 296
G
General-purpose Register
Configuration of General-purpose Register........... 54
Dedicated Registers and General-purpose
Register ............................................... 37
General-purpose Register Area and Register Bank
Pointer ................................................. 48
H
Hardware Interrupt
Hardware Interrupt........................................... 128
Hardware Interrupt Inhibit ................................ 129
Hardware Interrupt Processing Time.................. 138
Operation of Hardware Interrupt........................ 132
Procedure for Use of Hardware Interrupt............ 135
Return from Hardware Interrupt ........................ 131
Start of Hardware Interrupt ............................... 131
Structure Related to Hardware Interrupt ............. 129
Holding Control
Interruption/Holding Control Instruction .............. 60
I
I/O
I/O Area............................................................ 28
I/O Address Pointer
I/O Address Pointer (IOA) ................................ 145
I/O Circuit
I/O Circuit Type ................................................ 16
I/O Map
I/O Map .......................................................... 538
I/O Timer
Interruption of I/O Timer .................................. 308
I 2C
Block Diagram of I2C Interface......................... 403
Features of I2C Interface................................... 402
I2C Interface Register....................................... 405
I2C Interface Transfer Flow .............................. 421
Mode Flow of I2C Interface .............................. 423
Operation Flow of I2C Interface ........................ 424
Unit Configuration of I2C Interface ................... 404
I2C Address Register
I2C Address Register (IADR)............................ 416
2
I C Clock Control Register
I2C Clock Control Register (ICCR) ................... 413
INDEX
I2C Control Register
I2C Control Register (IBCR) ............................. 408
I2C Data Register
I2C Data Register (IDAR)................................. 417
2
I C Status Register
I2C Status Register (IBSR)................................ 406
IADR
I2C Address Register (IADR)............................ 416
IBCR
I2C Control Register (IBCR) ............................. 408
IBSR
I2C Status Register (IBSR)................................ 406
ICCR
I2C Clock Control Register (ICCR).................... 413
ICR
Composition of Interrupt Control Register
(ICR) ................................................. 125
Interrupt Control Registers (ICR00 to ICR15)..... 123
ICS
Input Capture Control Status Register (ICS01).... 303
IDAR
I2C Data Register (IDAR)................................. 417
ILM
Interrupt Level Mask Register (ILM) ................... 49
Indirect
Addressing by Indirect-specifying
32-bit Register ...................................... 32
Indirect Addressing
Indirect Addressing .......................................... 556
Initial State
The Initial State ............................................... 501
Input Capture
EI2OS Functions of Input Capture ..................... 310
Interruption of Input Capture............................. 310
Interruption of Input Capture and EI2OS ............ 310
List of Register in Input Capture Part ................. 297
Operation of Input Capture ............................... 315
Input Capture Control Status Register
Input Capture Control Status Register (ICS01).... 303
Input Capture Data Registers
Input Capture Data Registers (IPCP0, IPCP1)..... 303
Input Data Register
Input Data Register (SIDR0/SIDR1) .................. 351
Input/Output Port
Example of Programming Input/Output Port....... 217
Input/Output Port Function ............................... 166
List of Register of Input/Output Port .................. 168
Instruction
Description of Instruction Presentation Items and
Symbols ............................................. 568
Execution of the Start Condition Generation
Instruction under at SDA= "L"
and SCL="L"...................................... 419
F2MC-16LX Instruction List............................. 571
Instruction Types ..............................................547
Interruption/Holding Control Instruction...............60
Structure of Instruction Map ..............................585
Instruction Presentation Items and Symbols
Description of Instruction Presentation Items and
Symbols..............................................568
INT
Attention of Competition of SCC, MSS,
and INT Bits .......................................410
INT9
INT9 Interrupts ................................................502
Intensity Control
Intensity Control when Internal Division Resistance is
Used...................................................455
Intermittent Operation Mode
CPU Intermittent Operation Mode..................91, 98
Internal Clock
Internal Clock Mode .........................................268
Internal Clock Mode (One-shot Mode) ...............287
Operation of Internal Clock Mode (Reload Mode)
..........................................................284
Internal Division Register
Internal Division Register of LCD Controller/Driver
..........................................................454
Internal Division Resistance
Intensity Control when Internal Division Resistance is
Used...................................................455
Use of Internal Division Resistance ....................455
Internal Shift Clock Mode
Internal Shift Clock Mode .................................230
Internal Timer
Baud Rate by Internal Timer
(16-bit Reload Timer) ..........................364
Interrupt
8/10-bit A/D Converter Interrupt and EI2OS .......442
Cancellation of Standby Mode by Interrupt .........111
Hardware Interrupt ...........................................128
Hardware Interrupt Inhibit .................................129
Hardware Interrupt Processing Time...................138
INT9 Interrupts ................................................502
Interrupt Action ................................................117
Interrupt and EI2OS of Output Compare .............311
Interrupt Function of Serial I/O ..........................235
Interrupt of 8/10-bit A/D Converter ....................442
Interrupt of Timebase Timer ..............................244
Interrupt of Timebase Timer and EI2OS..............244
Interrupt Processing ..........................................134
Interrupt Related to UART1 and EI2OS ..............356
Interrupt Vector ................................................118
Interrupts of 16-bit Reload Timer .......................281
Interrupts of 16-bit Reload Timer and EI2OS.......281
Multiple Interrupts............................................136
Operation of Hardware Interrupt ........................132
Operation of Software Interrupt .........................141
Procedure for Use of Hardware Interrupt.............135
613
INDEX
Return from Hardware Interrupt......................... 131
Return from Software Interrupt.......................... 140
Start of Hardware Interrupt................................ 131
Start of Software Interrupt................................. 140
Structure Related to Hardware Interrupt ............. 129
Transition to Standby Mode and Interrupt........... 111
Transmit Interrupt Generation and Flag Set Timing
.......................................................... 359
Type and Function of Interrupt .......................... 116
UART Interrupt................................................ 355
Interrupt Control Register
Composition of Interrupt Control Register
(ICR) ................................................. 125
Interrupt Control Register Functions .................. 125
Interrupt Control Register List ........................... 121
Interrupt Control Registers (ICR00 to ICR15) ..... 123
Interrupt Factors, Interrupt Vectors, and Interrupt
Control Registers................................. 119
Interrupt Factors
Interrupt Factors, Interrupt Vectors, and Interrupt
Control Registers................................. 119
Interrupt Level Mask Register
Interrupt Level Mask Register (ILM) ................... 49
Interrupt Processing
Example of Interrupt Processing Program ........... 155
Stack Operation at the Start of Interrupt Processing
.......................................................... 153
Stack Operation when Interrupt Processing Returns
.......................................................... 153
Interrupt Vector
Interrupt Factors, Interrupt Vectors, and Interrupt
Control Registers................................. 119
Interrupt Vector................................................ 118
Interruption
Interruption and EI2OS which Relates
to UART ............................................ 337
Interruption Function for Interval of Watch Timer
.......................................................... 266
Interruption of I/O Timer .................................. 308
Interruption of Input Capture ............................. 310
Interruption of Input Capture and EI2OS............. 310
Interruption of Output Compare......................... 311
Interruption/Holding Control Instruction .............. 60
Interval Timer
Interval Timer Function .................................... 238
Operation of Interval Timer Function (Timebase
Timer) ................................................ 245
IOA
I/O Address Pointer (IOA) ................................ 145
IPCP
Input Capture Data Registers (IPCP0, IPCP1) ..... 303
ISCS
EI2OS Status Register (ISCS) ............................ 145
614
ISD
Configuration of Extended Intelligent I/O Service
(EI2OS) Descriptor (ISD) .................... 144
L
Latch-up
Observing the Maximum Rated Voltage (Prevention
of Latch-up) ......................................... 20
LCD
About the Terminal Processing of Using LCD ...... 22
Drive Waveform for the LCD ........................... 473
LCD Controller/Driver
Block Diagram of Pins Related to LCD Controller/
Driver ................................................ 459
Composition of LCD Controller/Driver.............. 452
External Division Register of
LCD Controller/Driver ........................ 456
Function of LCD Controller/Driver.................... 450
Internal Division Register of
LCD Controller/Driver ........................ 454
Operation Explanation of
LCD Controller/Driver ........................ 472
Power-supply Voltage of
LCD Controller/Driver ........................ 453
Registers Related to LCD Controller/Driver ....... 461
Terminal of LCD Controller/Driver ................... 458
LCDC Control Register
LCDC Control Register Higher (LCRH) ............ 464
LCDC Control Register Lower (LCRL) ............. 462
LCDC Range Register
LCDC Range Register (LCRR) ......................... 466
LCD Panel
LCD Panel Connection Example and Display Data
Example (1/2 duty driving type) ........... 476
LCD Panel Connection
LCD Panel Connection Example and Display Data
Example (1/4 duty driving type) ........... 482
LCRH
LCDC Control Register Higher (LCRH) ............ 464
LCRL
LCDC Control Register Lower (LCRL) ............. 462
LCRR
LCDC Range Register (LCRR) ......................... 466
Linear Addressing
Linear Addressing and Bank Addressing .............. 31
Linear Addressing by Specifying
24-bit Operand...................................... 32
Low-power Consumption
Block Diagram of Low-power Consumption Control
Circuit ................................................. 93
Operating State of
Low-power Consumption Mode ............. 24
INDEX
Low-power Consumption Mode Control Register
Low-power Consumption Mode Control Register
(LPMCR) ............................................. 95
Notes on Accessing the Low-power Consumption
Mode Control Register (LPMCR) to Enter
the Standby Mode ............................... 112
LPMCR
Low-power Consumption Mode Control Register
(LPMCR) ............................................. 95
Notes on Accessing the Low-power Consumption
Mode Control Register (LPMCR) to Enter
the Standby Mode ............................... 112
M
Machine Clock
Machine Clock .................................................. 83
Main Clock
Main Clock Mode, PLL Clock Mode, Sub Clock
Mode ................................................... 82
Master/Slave Mode
Master/Slave Mode Communication Function .... 376
Maximum Rated Voltage
Observing the Maximum Rated Voltage (Prevention
of Latch-up) ......................................... 20
MB90800 Series
Feature of MB90800 Series................................... 2
Function (resource) Around Internal of MB90800
Series..................................................... 3
MD
Mode Pins (MD2 to MD0) ................................ 161
Memory Map
E2PROM Memory Map .................................... 501
Memory Map..................................................... 29
Memory Space
Memory Space................................................... 27
Minimum Connection
Example of Minimum Connection to Flash
Microcontroller Programmer (User Power
Supply Used) ...................................... 534
Mode Data
Mode Data ...................................................... 162
Mode Pin and Mode Data ................................. 163
State of Pins after Mode Data Read...................... 73
Mode Fetch
Mode Fetch ....................................................... 68
Mode Flow
Mode Flow of I2C Interface .............................. 423
Mode Pin
Mode Pin .......................................................... 68
Mode Pin and Mode Data ................................. 163
Mode Pins (MD2 to MD0) ................................ 161
Mode Register
Mode Register (SMR0/SMR1) .......................... 346
MSS
Attention of Competition of SCC, MSS,
and INT Bits .......................................410
Multi-byte Data
Access to Multi-byte Data ...................................36
Store of Multi-byte Data in RAM .........................35
Multi-byte Length
Storage of Multi-byte Length Operand..................35
Multiple Interrupts
Multiple Interrupts............................................136
Multiple Sectors
Notes on Specifying Multiple Sectors .................521
Multiplication Rate
Selection of PLL Clock Multiplication Rate ..........83
N
NCC
Flag Change Inhibit Prefix (NCC) ........................59
O
OCCP
Output Compare Register (OCCP0, OCCP1).......305
OCSH
Output Compare Control Status Register (OCSL,
OCSH) ...............................................305
OCSL
Output Compare Control Status Register (OCSL,
OCSH) ...............................................305
One-shot Mode
Internal Clock Mode (One-shot Mode) ...............287
Operating Mode
Operating Mode ...............................................160
Operating State
Operating State of Low-power Consumption Mode24
Operation Flow
Operation Flow of I2C Interface .........................424
Operation Mode
CPU Intermittent Operation Mode..................91, 98
CPU Operation Modes and
Current Consumption .............................90
Operation in Synchronous Mode
(Operation mode 2)..............................372
Operation Modes of 16-bit Reload Timer ............268
Operation State
Counter Operation State ....................................282
Operation State in Standby Mode .........................99
Oscillation Stabilization Wait Time
Oscillation Stabilization Wait Time ..............86, 245
Reset Factors and Oscillation Stabilization Wait
Times ...................................................66
Sub Clock Oscillation Stabilization Wait Time
Function .............................................266
615
INDEX
Oscillation Stabilization Waiting
Oscillation Stabilization Waiting Reset State ........ 66
Oscillator
Connection of Oscillator and External Clock......... 87
Output Compare
EI2OS Function of Output Compare................... 311
Explanations for Output Compare Operation....... 316
Interruption of Output Compare......................... 311
List of Registers in Output Compare Unit ........... 297
Output Compare Control Status Register
Output Compare Control Status Register (OCSL,
OCSH) ............................................... 305
Output Compare Register
Output Compare Register (OCCP0, OCCP1) ...... 305
Output Data Register
Output Data Register (SODR0/SODR1) ............. 351
Output Port
Operations of the Shared Resource Ports Set as Output
Port by DDR Register .......................... 167
P
Package Dimensions
FPT-100P-M06 Package Dimensions ..................... 8
PACSR
Program Address Detection Control Status Register
(PACSR) ............................................ 499
PADR
Program Address Detection Register (PADR0/
PADR1) ............................................. 498
Pause-conversion Mode
Operation of Pause-conversion Mode ................. 444
PC
Program Counter (PC) ........................................ 50
PCB
Bank Register
(PCB, DTB, USB, SSB, and ADB) ......... 52
Bank Select Prefix (PCB, DTB, ADB, SPB) ......... 57
PCNT
PPG Control Status Register (PCNT) ................. 323
PCSR
PPG Cycle Set Register (PCSR) ........................ 326
PDCR
PPG Down Counter Register (PDCR) ................ 326
PDUT
PPG Duty Set Register (PDUT) ......................... 327
Pin
A Pin at Port 0 ................................................. 170
A Pin at Port 1 ................................................. 174
A Pin at Port 2 ................................................. 178
A Pin at Port 3 ................................................. 182
A Pin at Port 4 ................................................. 187
A Pin at Port 5 ................................................. 191
A Pin at Port 6 ................................................. 196
616
A Pin at Port 7 ................................................. 202
A Pin at Port 8 ................................................. 208
A Pin at Port 9 ................................................. 213
Pin Assignment
Pin Assignment.................................................... 9
Pin Functional
Pin Functional Description.................................. 10
Pin handling
Pin handling when no A/D Converter is Used ....... 22
PLL Clock
Main Clock Mode, PLL Clock Mode, Sub Clock
Mode ................................................... 82
Selection of PLL Clock Multiplication Rate ......... 83
Port 0
A Pin at Port 0 ................................................. 170
Configuration of Port 0..................................... 170
Operation of Port 0........................................... 172
Port 0 Register Function ................................... 171
Port 0 Registers
Port 0 Registers ............................................... 170
Port 1
A Pin at Port 1 ................................................. 174
Configuration of Port 1..................................... 174
Function of Registers for Port 1......................... 175
Operation of Port 1........................................... 176
Port 1 Registers
Port 1 Registers ............................................... 174
Port 2
A Pin at Port 2 ................................................. 178
Configuration of Port 2..................................... 178
Function of Registers for Port 2......................... 179
Operation of Port 2........................................... 180
Registers for Port 2 .......................................... 178
Port 3
A Pin at Port 3 ................................................. 182
Configuration of Port 3..................................... 182
Function of Registers for Port 3......................... 184
Operation of Port 3........................................... 185
Registers for Port 3 .......................................... 183
Port 4
A Pin at Port 4 ................................................. 187
Configuration of Port 4..................................... 187
Function of Registers for Port 4......................... 188
Operation of Port 4........................................... 189
Registers for Port 4 .......................................... 187
Port 5
A Pin at Port 5 ................................................. 191
Configuration of Port 5..................................... 191
Function of Registers for Port 5......................... 193
Operation of Port 5........................................... 194
Registers for Port 5 .......................................... 192
Port 6
A Pin at Port 6 ................................................. 196
Configuration of Port 6..................................... 196
Operation of Port 6........................................... 200
INDEX
Port 6 Register Function ................................... 198
Port 7
A Pin at Port 7 ................................................. 202
Configuration of Port 7..................................... 202
Operation of Port 7........................................... 206
Port 7 Register Function ................................... 204
Port 7 Registers
Port 7 Registers................................................ 203
Port 8
A Pin at Port 8 ................................................. 208
Configuration of Port 8..................................... 208
Operation of Port 8........................................... 211
Port 8 Register Function ................................... 210
Port 8 Registers
Port 8 Registers................................................ 209
Port 9
A Pin at Port 9 ................................................. 213
Configuration of Port 9..................................... 213
Operation of Port 9........................................... 215
Port 9 Register Function ................................... 214
Port 9 Registers
Port 9 Registers................................................ 213
Power pins
About Power pins............................................... 21
Power-supply Voltage
Power-supply Voltage of
LCD Controller/Driver ........................ 453
PPG Control Status Register
PPG Control Status Register (PCNT) ................. 323
PPG Cycle Set Register
PPG Cycle Set Register (PCSR) ........................ 326
PPG Down Counter Register
PPG Down Counter Register (PDCR) ................ 326
PPG Duty Set Register
PPG Duty Set Register (PDUT)......................... 327
PPG Timer
Block Diagram of PPG Timer ........................... 320
Function of PPG Timer..................................... 318
Interruption of PPG Timer and EI2OS................ 319
Register of PPG Timer ..................................... 321
Sample Program of PPG Timer ......................... 332
Prefix
Common Register Bank Prefix (CMR)................. 58
Flag Change Inhibit Prefix (NCC) ....................... 59
Prefix Code
Array of Prefix Codes......................................... 61
Prefix Code ....................................................... 56
Processing Time
Extended Intelligent I/O Service (EI2OS) Processing
Time (time for one transfer) ................. 149
Processor Status
Configuration of Processor Status (PS)................. 45
Product Lineup
Product Lineup .................................................... 5
Program Address Detection Control Status Register
Program Address Detection Control Status Register
(PACSR) ............................................499
Program Address Detection Register
Program Address Detection Register (PADR0/
PADR1)..............................................498
Program Counter
Program Counter (PC).........................................50
Program Examples
Program Examples of Watchdog Timer ..............259
Programming
Example of Programming Input/Output Port .......217
Notes on Data Programming ..............................518
Programming/Erasing
Details of Programming/Erasing Flash Memory ..516
Protection
A/D-converted Data Protection Function.............446
PS
Configuration of Processor Status (PS) .................45
PWM
PWM Operation ...............................................328
R
RAM
Display RAM and Output Terminal....................468
RAM Area .........................................................28
Store of Multi-byte Data in RAM .........................35
Read/Reset State
Read/Reset State in Flash Memory .....................517
Receive Interrupt Generation
Receive Interrupt Generation and Flag Set Timing
..........................................................357
Register Bank
Register Bank.....................................................55
Register Bank Pointer
General-purpose Register Area and Register Bank
Pointer..................................................48
Register Bank Pointer (RP)..................................48
Reload Mode
Operation of Internal Clock Mode
(Reload Mode) ....................................284
Reload Timer
16-bit Reload Timer Notes On Use.....................292
Baud Rate by Internal Timer
(16-bit Reload Timer) ..........................364
Block Diagram for Pins of
16-bit Reload Timer.............................273
Block Diagram of 16-bit Reload Timer ...............271
EI2OS Function of 16-bit Reload Timer..............281
Interrupts of 16-bit Reload Timer .......................281
Interrupts of 16-bit Reload Timer and EI2OS.......281
List of Register of 16-bit Reload Timer...............274
Operation Modes of 16-bit Reload Timer ............268
Pins of 16-bit Reload Timer...............................273
617
INDEX
Setting of 16-bit Reload Timer .......................... 282
Request Level Setting Register
Request Level Setting Register (ELVR) ............. 393
Reset
Notes on Reset Factor Bit.................................... 71
Oscillation Stabilization Waiting Reset State ........ 66
Overview of Reset Operation............................... 68
Pin Status during Reset ....................................... 73
Reset Factor....................................................... 64
Reset Factor Bit ................................................. 70
Reset Factors and Oscillation Stabilization Wait
Times................................................... 66
ROM
ROM Area......................................................... 28
ROM Mirror
Block Diagram of ROM Mirror Function Selection
Module............................................... 506
ROM Mirror Function Select Register
ROM Mirror Function Select Register
(ROMM) ............................................ 507
ROMM
ROM Mirror Function Select Register
(ROMM) ............................................ 507
RP
Register Bank Pointer (RP) ................................. 48
S
Sample Program
Sample Program of PPG Timer.......................... 332
SCC
Attention of Competition of SCC, MSS,
and INT Bits ....................................... 410
SCL
Execution of the Start Condition Generation
Instruction under at SDA= "L"
and SCL="L" ...................................... 419
SCR
Control Register (SCR0/SCR1) ......................... 343
SDA
Execution of the Start Condition Generation
Instruction under at SDA= "L"
and SCL="L" ...................................... 419
SDCR
Serial I/O Prescaler Register
(SDCR0, SDCR1) ............................... 227
SDR
Serial Shift Data Register (SDR0, SDR1) ........... 226
Sector
How to Specify Sector ...................................... 521
Notes on Specifying Multiple Sectors................. 521
The Flash Memory Sector Erase Resumption ...... 524
Sector Configuration
Sector Configuration......................................... 511
618
Sector Erasing
Erasing Any Data in Flash Memory
(Sector Erasing) .................................. 521
Sector Erasing Suspension ................................ 523
Serial data
Timing of I/O of Serial data .............................. 234
Serial Data Register
Serial Data Register Read/Write Standby State ... 231
Serial I/O
Block Diagram of Serial I/O ............................. 220
Interrupt Function of Serial I/O ......................... 235
Operation of Serial I/O ..................................... 229
Overview of Serial I/O ..................................... 220
Register of Serial I/O........................................ 221
Serial I/O Prescaler Register
Serial I/O Prescaler Register
(SDCR0, SDCR1) ............................... 227
Serial Mode Control Status Register
Serial Mode Control Status Register (SMCS0,
SMCS1), Higher ................................. 222
Serial Mode Control Status Register (SMCS0,
SMCS1), Lower.................................. 224
Serial Shift Data Register
Serial Shift Data Register (SDR0, SDR1) ........... 226
Serial Writing
Example of Connecting Serial Writing (User power
supply used) ....................................... 529
Serial Writing Connection
The Basic Component of
Serial Writing Connection.................... 526
Setting Mode
Setting Mode ................................................... 160
Shift Clock Mode
External Shift Clock Mode................................ 230
Internal Shift Clock Mode................................. 230
Shift Operation
Start/stop Timing of Shift Operation .................. 233
SIDR
Input Data Register (SIDR0/SIDR1) .................. 351
Single Conversion Mode
Operation of Single Conversion Mode ............... 443
Single-chip Mode
Pin State in Single-chip Mode ........................... 110
Sleep Mode
Cancellation of Sleep Modes............................. 100
Transition to Sleep Mode.................................. 100
SMCS
Serial Mode Control Status Register (SMCS0,
SMCS1), Higher ................................. 222
Serial Mode Control Status Register (SMCS0,
SMCS1), Lower.................................. 224
SMR
Mode Register (SMR0/SMR1) .......................... 346
INDEX
SODR
Output Data Register (SODR0/SODR1) ............. 351
Software Interrupt
Operation of Software Interrupt ......................... 141
Return from Software Interrupt ......................... 140
Start of Software Interrupt ................................ 140
SPB
Bank Select Prefix (PCB, DTB, ADB, SPB) ......... 57
SSB
Bank Register (PCB, DTB, USB, SSB,
and ADB)............................................. 52
SSP
System Stack Pointer (SSP) ................................ 44
SSR
Status Register (SSR0/SSR1) ............................ 348
Stabilization
Stabilization of Supply Voltage ........................... 20
Stack
Setting of Stack.................................................. 43
Stack Area....................................................... 154
Stack Operation at the Start of
Interrupt Processing ............................ 153
Stack Operation when Interrupt
Processing Returns .............................. 153
Standby Mode
Cancellation of Standby Mode by Interrupt ........ 111
Notes on Accessing the Low-power Consumption
Mode Control Register (LPMCR) to Enter
the Standby Mode ............................... 112
Operation State in Standby Mode ........................ 99
Standby Mode ................................................... 91
Transition to Standby Mode and Interrupt .......... 111
Standby State
Serial Data Register Read/Write Standby State ... 231
Start Condition
Execution of the Start Condition Generation
Instruction under at SDA= "L"
and SCL="L"...................................... 419
Start Condition ................................................ 418
Start/stop Timing
Start/stop Timing of Shift Operation .................. 233
State Transition Diagram
State Transition Diagram .................................. 108
Status Register
Status Register (SSR0/SSR1) ............................ 348
Stop Condition
Stop Condition................................................. 418
Stop Mode
At Clearing Stop Mode..................................... 111
Cancellation of Stop Modes .............................. 106
Transition to Stop Mode ................................... 106
Stop State
STOP State...................................................... 231
Stop State........................................................ 231
Structure
Structure of Instruction Map ..............................585
Sub Clock
Main Clock Mode, PLL Clock Mode, Sub Clock
Mode....................................................82
Sub Clock Oscillation Stabilization Wait Time
Function .............................................266
Supply Map
Clock Supply Map ..............................................23
Supply Voltage
Stabilization of Supply Voltage............................20
Supplying power
Serial Write Connection Example (Supplying power
from writer).........................................532
Synchronous Mode
Operation in Synchronous Mode
(Operation mode 2)..............................372
System Configuration
System Configuration Diagram ..........................501
System Stack Pointer
System Stack Pointer (SSP) .................................44
T
TBTC
Timebase Timer Control Register (TBTC) ..........242
TCCSH
Timer Control Status Register
(TCCSL, TCCSH) ...............................299
TCCSL
Timer Control Status Register
(TCCSL, TCCSH) ...............................299
TCDT
Timer Data Register (TCDT) .............................298
Terminal
About the Terminal Processing of Using LCD.......22
Processing of Unused Input Terminal ...................20
Timebase Timer
Block Diagram of Timebase Timer.....................240
Interrupt of Timebase Timer ..............................244
Interrupt of Timebase Timer and EI2OS..............244
Operation of Interval Timer Function (Timebase
Timer) ................................................245
Operations of Timebase Timer ...........................246
Precautions when Using Timebase Timer............248
Timebase Timer Control Register
Timebase Timer Control Register (TBTC) ..........242
Timebase Timer Mode
Cancellation of Timebase Timer Modes..............102
Transition to Timebase Timer Mode...................102
Timer Clock
Block Diagram of the Timer Clock Output Circuit
..........................................................485
Timer Clock Output Circuit ...............................484
619
INDEX
Timer Clock Output Control Register
Timer Clock Output Control Register
(TMCS).............................................. 486
Timer Control Status Register
Timer Control Status Register
(TCCSL, TCCSH) ............................... 299
Timer Control Status Register Higher
(TMCSR) ........................................... 275
Timer Control Status Register Lower
(TMCSR) ........................................... 277
Timer Data Register
Timer Data Register (TCDT)............................. 298
TMCS
Timer Clock Output Control Register (TMCS).... 486
TMCSR
Timer Control Status Register Higher
(TMCSR) ........................................... 275
Timer Control Status Register Lower
(TMCSR) ........................................... 277
TMR
16-bit Timer Register (TMR)............................. 279
TMRLR
16-bit Reload Register (TMRLR)....................... 280
transfer
Extended Intelligent I/O Service (EI2OS) Processing
Time (time for one transfer) ................. 149
Transfer Flow
I2C Interface Transfer Flow............................... 421
Transfer State
Transfer State................................................... 231
Transition Diagram
State Transition Diagram .................................. 108
Transmit Interrupt
Transmit Interrupt Generation and
Flag Set Timing .................................. 359
U
UART
Block Diagram of UART Pins ........................... 341
Interrupt Related to UART1 and EI2OS.............. 356
Interruption and EI2OS which
Relates to UART ................................. 337
List of UART Register...................................... 342
Notes on Using UART...................................... 379
Operation of UART.......................................... 367
UART Baud Rate Setting .................................. 360
UART Block Diagram ...................................... 338
UART EI2OS Function ..................................... 356
UART Function ............................................... 336
620
UART Interrupt ............................................... 355
UART Pins...................................................... 341
Unused Input Terminal
Processing of Unused Input Terminal .................. 20
USB
Bank Register
(PCB, DTB, USB, SSB, and ADB)......... 52
User Power
Example of Minimum Connection to Flash
Microcontroller Programmer (User Power
Supply Used)...................................... 534
User power supply
Example of Connecting Serial Writing (User power
supply used) ....................................... 529
User Stack Pointer
User Stack Pointer (USP).................................... 44
USP
User Stack Pointer (USP).................................... 44
W
Watch Counter
Watch Counter................................................. 266
Watch Mode
Cancellation of Watch Mode............................. 104
Transition to Watch Mode ................................ 104
Watch Timer
Block Diagram of Watch Timer ........................ 263
Interruption Function for Interval of
Watch Timer ...................................... 266
Watch Timer Function...................................... 262
Watch Timer Control Register
Watch Timer Control Register (WTC) ............... 264
Watchdog Timer
Block Diagram of Watchdog Timer ................... 254
Functions of Watchdog Timer ........................... 250
Indicating Function of Clock Source in Watchdog
Timer................................................. 266
Operations of Watchdog Timer ......................... 256
Precautions when Using Watchdog Timer .......... 258
Program Examples of Watchdog Timer.............. 259
Watchdog Timer Control Register
Watchdog Timer Control Register (WDTC) ....... 252
WDTC
Watchdog Timer Control Register (WDTC) ....... 252
Writing Data
Writing Data in Flash Memory.......................... 518
WTC
Watch Timer Control Register (WTC) ............... 264
CM44-10128-5E
FUJITSU MICROELECTRONICS • CONTROLLER MANUAL
F2MC-16LX
16-BIT MICROCONTROLLER
MB90800 Series
HARDWARE MANUAL
February 2010 the fifth edition
Published
FUJITSU MICROELECTRONICS LIMITED
Edited
Sales Promotion Dept.
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