2.4 MB

The following document contains information on Cypress products.
MB9A310K Series
32-bit ARM® Cortex®-M3 based Microcontroller
MB9AF311K, MB9AF312K
Data Sheet (Full Production)
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Spansion Inc. deems the products to have been in sufficient production
volume such that subsequent versions of this document are not expected to change. However,
typographical or specification corrections, or modifications to the valid combinations offered may occur.
Publication Number MB9A310K-DS706-00029
CONFIDENTIAL
Revision 2.0
Issue Date February 20, 2015
D a t a S h e e t
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers
of product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to
verify that they have the latest information before finalizing their design. The following descriptions of
Spansion data sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue.
Spansion Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion
Inc. The information is intended to help you evaluate this product. Do not design in this product
without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on
this proposed product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a
commitment to production has taken place. This designation covers several aspects of the product life
cycle, including product qualification, initial production, and the subsequent phases in the manufacturing
process that occur before full production is achieved. Changes to the technical specifications presented
in a Preliminary document should be expected while keeping these aspects of production under
consideration. Spansion places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification
has been completed, and that initial production has begun. Due to the phases of the
manufacturing process that require maintaining efficiency and quality, this document may be
revised by subsequent versions or modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
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disclaimer on the first page refers the reader to the notice on this page.
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When a product has been in production for a period of time such that no changes or only nominal
changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes
may include those affecting the number of ordering part numbers available, such as the addition or
deletion of a speed option, temperature range, package type, or VIO range. Changes may also include
those needed to clarify a description or to correct a typographical error or incorrect specification.
Spansion Inc. applies the following conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production
volume such that subsequent versions of this document are not expected to change. However,
typographical or specification corrections, or modifications to the valid combinations offered may
occur.”
Questions regarding these document designations may be directed to your local sales office.
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CONFIDENTIAL
MB9A310K-DS706-00029-2v0-E, February 20, 2015
MB9A310K Series
32-bit ARM® Cortex®-M3 based Microcontroller
MB9AF311K, MB9AF312K
Data Sheet (Full Production)
 Description
The MB9A310K Series are a highly integrated 32-bit microcontrollers dedicated for embedded controllers
with high-performance and low cost.
These series are based on the ARM Cortex-M3 Processor with on-chip Flash memory and SRAM, and has
peripheral functions such as Motor Control Timers, ADCs and Communication Interfaces (USB, UART,
CSIO, I2C, LIN).
The products which are described in this data sheet are placed into TYPE5 product categories in "FM3
Famliy PERIPHERAL MANUAL".
Note: ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries.
Publication Number MB9A310K-DS706-00029
Revision 2.0
Issue Date February 20, 2015
This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient
production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the
valid combinations offered may occur.
CONFIDENTIAL
D a t a S h e e t

Features
 32-bit ARM Cortex-M3 Core
 Processor version: r2p1
 Up to 40MHz Frequency Operation
 Integrated Nested Vectored Interrupt Controller (NVIC) : 1 NMI (non-maskable interrupt) and 48
peripheral interrupts and 16 priority levels
 24-bit System timer (Sys Tick) : System timer for OS task management
 On-chip Memories
[Flash memory]
This Series are based on two independent on-chip Flash memories.
 MainFlash
 Up to 128Kbyte
 Read cycle : 0 wait-cycle
 Security function for code protection
 WorkFlash
 32Kbyte
 Read cycle : 0 wait-cycle
 Security function is shared with code protection
[SRAM]
This Series contain a total of up to 16Kbyte on-chip SRAM. This is composed of two independent SRAM
(SRAM0, SRAM1) . SRAM0 is connected to I-code bus and D-code bus of Cortex-M3 core. SRAM1 is
connected to System bus.
 SRAM0 : 8 Kbyte
 SRAM1 : 8 Kbyte
 USB Interface
USB interface is composed of Function and Host.
PLL for USB is built-in, USB clock can be generated by multiplication of Main clock.
[USB function]
 USB2.0 Full-Speed supported
 Max 6 EndPoint supported
 EndPoint 0 is control transfer
 EndPoint 1, 2 can be selected Bulk-transfer, Interrupt-transfer or Isochronous-transfer
 EndPoint 3 to 5 can be selected Bulk-transfer or Interrupt-transfer
 EndPoint 1 to 5 is comprised Double Buffer
 The size of each EndPoint is as follows.
 EndPoint 0, 2 to 5:64 bytes
 EndPoint 1: 256 bytes
[USB host]
 USB2.0 Full/Low-speed supported
 Bulk-transfer, interrupt-transfer and Isochronous-transfer support
 USB Device connected/dis-connected automatically detect
 IN/OUT token handshake packet automatically
 Max 256-byte packet-length supported
 Wake-up function supported
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D a t a S h e e t
 Multi-function Serial Interface (Max 4channels)
 2 channels with 16-steps × 9-bits FIFO (ch.0, ch.1), 2 channels without FIFO (ch.3, ch.5)
 Operation mode is selectable from the followings for each channel.
(In ch.5, only UART and LIN are available.)
 UART
 CSIO
 LIN
 I2C
[UART]
 Full-duplex double buffer
 Selection with or without parity supported
 Built-in dedicated baud rate generator
 External clock available as a serial clock
 Hardware Flow control : Automatically control the transmission by CTS/RTS (only ch.4)
 Various error detect functions available (parity errors, framing errors, and overrun errors)
[CSIO]
 Full-duplex double buffer
 Built-in dedicated baud rate generator
 Overrun error detect function available
[LIN]
 LIN protocol Rev.2.1 supported
 Full-duplex double buffer
 Master/Slave mode supported
 LIN break field generate (can be changed 13 to 16-bit length)
 LIN break delimiter generate (can be changed 1 to 4-bit length)
 Various error detect functions available (parity errors, framing errors, and overrun errors)
2
[I C]
Standard mode (Max 100kbps) / Fast-mode (Max 400kbps) supported
 DMA Controller (4channels)
DMA Controller has an independent bus for CPU, so CPU and DMA Controller can process simultaneously.







8 independently configured and operated channels
Transfer can be started by software or request from the built-in peripherals
Transfer address area: 32-bit (4Gbyte)
Transfer mode: Block transfer/Burst transfer/Demand transfer
Transfer data type: byte/half-word/word
Transfer block count: 1 to 16
Number of transfers: 1 to 65536
 A/D Converter (Max 8channels)
[12-bit A/D Converter]
 Successive Approximation Register type
 Built-in 2unit
 Conversion time: [email protected]
 Priority conversion available (priority at 2levels)
 Scanning conversion mode
 Built-in FIFO for conversion data storage
(for SCAN conversion: 16steps, for Priority conversion: 4steps)
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CONFIDENTIAL
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D a t a S h e e t
 Base Timer (Max 8channels)
Operation mode is selectable from the followings for each channel.




16-bit PWM timer
16-bit PPG timer
16/32-bit reload timer
16/32-bit PWC timer
 General Purpose I/O Port
This series can use its pins as General Purpose I/O ports when they are not used for external bus or
peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function
can be allocated.





Capable of pull-up control per pin
Capable of reading pin level directly
Built-in the port relocate function
Up 36 fast General Purpose I/O Ports
Some pin is 5V tolerant I/O.
See "PIN DESCRIPTION" to confirm the corresponding pins.
 Multi-function Timer
The Multi-function timer is composed of the following blocks.






16-bit free-run timer × 3ch.
Input capture × 4ch.
Output compare × 6ch.
A/D activating compare × 3ch.
Waveform generator × 3ch.
16-bit PPG timer × 3ch.
The following function can be used to achieve the motor control.






PWM signal output function
DC chopper waveform output function
Dead time function
Input capture function
A/D convertor activate function
DTIF (Motor emergency stop) interrupt function
 Real-time clock (RTC)
The Real-time clock can count Year/Month/Day/Hour/Minute/Second/A day of the week from 01 to 99.
 Interrupt function with specifying date and time (Year/Month/Day/Hour/Minute/Second/A day of the
week.) is available. This function is also available by specifying only Year, Month, Day, Hour or Minute.
 Timer interrupt function after set time or each set time.
 Capable of rewriting the time with continuing the time count.
 Leap year automatic count is available.
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CONFIDENTIAL
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D a t a S h e e t
 Quadrature Position/Revolution Counter (QPRC)
The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position
encoder. Moreover, it is possible to use up/down counter.




The detection edge of the three external event input pins AIN, BIN and ZIN is configurable.
16-bit position counter
16-bit revolution counter
Two 16-bit compare registers
 Dual Timer (32/16-bit Down Counter)
The Dual Timer consists of two programmable 32/16-bit down counters.
Operation mode is selectable from the followings for each channel.
 Free-running
 Periodic (=Reload)
 One-shot
 Watch Counter
The Watch counter is used for wake up from Low Power Consumption mode.
 Interval timer: up to 64s (Max) @ Sub Clock : 32.768kHz
 External Interrupt Controller Unit
 Up to 6 external interrupt input pin
 Include one non-maskable interrupt (NMI)
 Watchdog Timer (2channels)
A watchdog timer can generate interrupts or a reset when a time-out value is reached.
This series consists of two different watchdogs, a "Hardware" watchdog and a "Software" watchdog.
"Hardware" watchdog timer is clocked by low-speed internal CR oscillator. Therefore, ”Hardware"
watchdog is active in any power saving mode except RTC and STOP and Deep stand-by RTC and Deep
stand-by STOP.
 CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator helps a verify data transmission or storage integrity.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
 CCITT CRC16 Generator Polynomial: 0x1021
 IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
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CONFIDENTIAL
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D a t a S h e e t
 Clock and Reset
[Clocks]
Five clock sources (2 external oscillators, 2 internal CR oscillator, and Main PLL) that are dynamically
selectable.





Main Clock
: 4MHz to 48MHz
Sub Clock
: 32.768kHz
High-speed internal CR Clock
: 4MHz
Low-speed internal CR Clock
: 100kHz
Main PLL Clock
[Resets]
 Reset requests from INITX pin
 Power on reset
 Software reset
 Watchdog timers reset
 Low-voltage detector reset
 Clock supervisor reset
 Clock Super Visor (CSV)
Clocks generated by internal CR oscillators are used to supervise abnormality of the external clocks.
 External OSC clock failure (clock stop) is detected, reset is asserted.
 External OSC frequency anomaly is detected, interrupt or reset is asserted.
 Low-Voltage Detector (LVD)
This Series include 2-stage monitoring of voltage on the VCC pins. When the voltage falls below the
voltage has been set, Low-Voltage Detector generates an interrupt or reset.
 LVD1: error reporting via interrupt
 LVD2: auto-reset operation
 Low Power Consumption Mode
Six Low Power Consumption modes supported.






SLEEP
TIMER
RTC
STOP
Deep stand-by RTC
Deep stand-by STOP
 Debug
Serial Wire JTAG Debug Port (SWJ-DP)
 Power Supply
 Wide range voltage
: VCC
= 2.7V to 5.5V
 Power supply for USB I/O : USBVCC0 = 3.0V to 3.6V (when USB is used)
= 2.7V to 5.5V (when GPIO is used)
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CONFIDENTIAL
MB9A310K-DS706-00029-2v0-E, February 20, 2015
D a t a S h e e t
 Product Lineup
 Memory size
Product name
MainFlash
On-chip
Flash memory
WorkFlash
SRAM0
On-chip SRAM SRAM1
Total
MB9AF311K
64 Kbyte
32 Kbyte
8 Kbyte
8 Kbyte
16 Kbyte
MB9AF312K
128 Kbyte
32 Kbyte
8 Kbyte
8 Kbyte
16 Kbyte
 Function
MB9AF311K
MB9AF312K
Product name
Pin count
CPU
Freq.
Power supply voltage range
USB2.0 (Function/Host)
DMAC
Multi-function Serial Interface
(UART/CSIO/LIN/I2C)
48/52
Cortex-M3
40 MHz
2.7V to 5.5V
(USBVCC:3.0V to 3.6V)
1ch. (Max)
4ch. (Max)
4ch. (Max)
with 16-steps × 9-bits FIFO : ch.0, ch.1
without FIFO : ch.3, ch.5 (In ch.5, only UART and LIN are available.)
Base Timer
8ch. (Max)
(PWC/ Reload timer/PWM/PPG)
A/D
activation
3ch.
compare
Input
4ch.
capture
Free-run
MF3ch.
1 unit (Max)
Timer timer
Output
6ch.
compare
Waveform
3ch.
generator
PPG
3ch.
QPRC
1ch. (Max)
Dual Timer
1 unit
Real-time clock
1 unit
Watch Counter
1 unit
CRC Accelerator
Yes
Watchdog timer
1ch. (SW) + 1ch. (HW)
External Interrupts
6 pins (Max) + NMI × 1
General Purpose I/O ports
36 pins (Max)
12-bit A/D converter
8ch. (2 units)
CSV (Clock Super Visor)
Yes
LVD (Low-Voltage Detector)
2ch.
High-speed
4 MHz
Built-in
OSC
Low-speed
100 kHz
Debug Function
SWJ-DP
Note: All signals of the peripheral function in each product cannot be allocated by limiting the pins of package.
It is necessary to use the port relocate function of the General I/O port according to your function use.
See "Electrical Characteristics 4.AC Characteristics (3)Built-in CR Oscillation Characteristics" for
accuracy of built-in CR.
February 20, 2015, MB9A310K-DS706-00029-2v0-E
CONFIDENTIAL
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D a t a S h e e t
 Packages
Product name
Package
MB9AF311K
MB9AF312K



LQFP: FPT-48P-M49 (0.5mm pitch)
QFN: LCC-48P-M73 (0.5mm pitch)
LQFP: FPT-52P-M02 (0.65mm pitch)
: Supported
Note : See "Package Dimensions" for detailed information on each package.
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CONFIDENTIAL
MB9A310K-DS706-00029-2v0-E, February 20, 2015
D a t a S h e e t
 Pin Assignment
 FPT-48P-M49
VSS
P81/UDP0
P80/UDM0
USBVCC
P60/SIN5_0/TIOA2_2/INT15_1/IC00_0/WKUP3
P61/SOT5_0/TIOB2_2/UHCONX/DTTI0X_2
P0F/NMIX/CROUT_1/RTCCO_0/SUBOUT_0/WKUP0
P04/TDO/SWO
P03/TMS/SWDIO
P02/TDI
P01/TCK/SWCLK
P00/TRSTX
48
47
46
45
44
43
42
41
40
39
38
37
(TOP VIEW)
VCC
1
36
P21/SIN0_0/INT06_1/WKUP2
P50/INT00_0/AIN0_2/SIN3_1
2
35
P22/AN07/SOT0_0/TIOB7_1
P51/INT01_0/BIN0_2/SOT3_1
3
34
P23/AN06/SCK0_0/TIOA7_1
P52/INT02_0/ZIN0_2/SCK3_1
4
33
AVSS
P39/DTTI0X_0/ADTG_2
5
32
AVRH
P3A/RTO00_0/TIOA0_1/RTCCO_2/SUBOUT_2
6
31
AVCC
P3B/RTO01_0/TIOA1_1
7
30
P15/AN05/SOT0_1/IC03_2
P3C/RTO02_0/TIOA2_1
8
29
P14/AN04/SIN0_1/INT03_1/IC02_2
P3D/RTO03_0/TIOA3_1
9
28
P13/AN03/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1
P3E/RTO04_0/TIOA4_1
10
27
P12/AN02/SOT1_1/IC00_2
P3F/RTO05_0/TIOA5_1
11
26
P11/AN01/SIN1_1/INT02_1/FRCK0_2/IC02_0/WKUP1
VSS
12
25
P10/AN00
13
14
15
16
17
18
19
20
21
22
23
24
C
VCC
P46/X0A
P47/X1A
INITX
P49/TIOB0_0
P4A/TIOB1_0
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
LQFP - 48
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
February 20, 2015, MB9A310K-DS706-00029-2v0-E
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D a t a S h e e t
 LCC-48P-M73
VSS
P81/UDP0
P80/UDM0
USBVCC
P60/SIN5_0/TIOA2_2/INT15_1/IC00_0/WKUP3
P61/SOT5_0/TIOB2_2/UHCONX/DTTI0X_2
P0F/NMIX/CROUT_1/RTCCO_0/SUBOUT_0/WKUP0
P04/TDO/SWO
P03/TMS/SWDIO
P02/TDI
P01/TCK/SWCLK
P00/TRSTX
48
47
46
45
44
43
42
41
40
39
38
37
(TOP VIEW)
VCC
1
36
P21/SIN0_0/INT06_1/WKUP2
P50/INT00_0/AIN0_2/SIN3_1
2
35
P22/AN07/SOT0_0/TIOB7_1
P51/INT01_0/BIN0_2/SOT3_1
3
34
P23/AN06/SCK0_0/TIOA7_1
P52/INT02_0/ZIN0_2/SCK3_1
4
33
AVSS
P39/DTTI0X_0/ADTG_2
5
32
AVRH
P3A/RTO00_0/TIOA0_1/RTCCO_2/SUBOUT_2
6
31
AVCC
P3B/RTO01_0/TIOA1_1
7
30
P15/AN05/SOT0_1/IC03_2
P3C/RTO02_0/TIOA2_1
8
29
P14/AN04/SIN0_1/INT03_1/IC02_2
P3D/RTO03_0/TIOA3_1
9
28
P13/AN03/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1
P3E/RTO04_0/TIOA4_1
10
27
P12/AN02/SOT1_1/IC00_2
P3F/RTO05_0/TIOA5_1
11
26
P11/AN01/SIN1_1/INT02_1/FRCK0_2/IC02_0/WKUP1
VSS
12
25
P10/AN00
13
14
15
16
17
18
19
20
21
22
23
24
C
VCC
P46/X0A
P47/X1A
INITX
P49/TIOB0_0
P4A/TIOB1_0
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
QFN - 48
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
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MB9A310K-DS706-00029-2v0-E, February 20, 2015
D a t a S h e e t
 FPT-52P-M02
VSS
P81/UDP0
P80/UDM0
USBVCC
P60/SIN5_0/TIOA2_2/INT15_1/IC00_0/WKUP3
P61/SOT5_0/TIOB2_2/UHCONX/DTTI0X_2
P0F/NMIX/CROUT_1/RTCCO_0/SUBOUT_0/WKUP0
P04/TDO/SWO
P03/TMS/SWDIO
P02/TDI
P01/TCK/SWCLK
P00/TRSTX
NC
52
51
50
49
48
47
46
45
44
43
42
41
40
(TOP VIEW)
VCC
1
39
P21/SIN0_0/INT06_1/WKUP2
P50/INT00_0/AIN0_2/SIN3_1
2
38
P22/AN07/SOT0_0/TIOB7_1
P51/INT01_0/BIN0_2/SOT3_1
3
37
P23/AN06/SCK0_0/TIOA7_1
P52/INT02_0/ZIN0_2/SCK3_1
4
36
NC
NC
5
35
AVSS
P39/DTTI0X_0/ADTG_2
6
34
AVRH
P3A/RTO00_0/TIOA0_1/RTCCO_2/SUBOUT_2
7
33
AVCC
P3B/RTO01_0/TIOA1_1
8
32
P15/AN05/SOT0_1/IC03_2
P3C/RTO02_0/TIOA2_1
9
31
P14/AN04/SIN0_1/INT03_1/IC02_2
P3D/RTO03_0/TIOA3_1
10
30
P13/AN03/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1
P3E/RTO04_0/TIOA4_1
11
29
P12/AN02/SOT1_1/IC00_2
P3F/RTO05_0/TIOA5_1
12
28
P11/AN01/SIN1_1/INT02_1/FRCK0_2/IC02_0/WKUP1
VSS
13
27
P10/AN00
14
15
16
17
18
19
20
21
22
23
24
25
26
C
VCC
P46/X0A
P47/X1A
INITX
P49/TIOB0_0
P4A/TIOB1_0
NC
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
LQFP - 52
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
February 20, 2015, MB9A310K-DS706-00029-2v0-E
CONFIDENTIAL
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D a t a S h e e t
 List of Pin Functions
 List of pin numbers
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Pin No
LQFP-48
LQFP-52
QFN-48
1
1
2
2
3
3
4
4
-
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
12
CONFIDENTIAL
Pin Name
VCC
P50
INT00_0
AIN0_2
SIN3_1
P51
INT01_0
BIN0_2
SOT3_1
P52
INT02_0
ZIN0_2
SCK3_1
NC
P39
DTTI0X_0
ADTG_2
P3A
RTO00_0
TIOA0_1
RTCCO_2
SUBOUT_2
P3B
RTO01_0
TIOA1_1
P3C
RTO02_0
TIOA2_1
P3D
RTO03_0
TIOA3_1
P3E
RTO04_0
TIOA4_1
P3F
RTO05_0
TIOA5_1
VSS
I/O circuit
type
Pin state
type
-
I*
H
I*
H
I*
H
E
I
G
I
G
I
G
I
G
I
G
I
G
I
-
MB9A310K-DS706-00029-2v0-E, February 20, 2015
D a t a S h e e t
Pin No
LQFP-48
LQFP-52
QFN-48
13
14
14
15
15
16
16
17
17
18
18
19
19
20
-
21
20
22
21
23
22
24
23
25
24
26
25
27
26
28
27
29
28
30
29
31
February 20, 2015, MB9A310K-DS706-00029-2v0-E
CONFIDENTIAL
Pin Name
C
VCC
P46
X0A
P47
X1A
INITX
P49
TIOB0_0
P4A
TIOB1_0
NC
PE0
MD1
MD0
PE2
X0
PE3
X1
VSS
P10
AN00
P11
AN01
SIN1_1
INT02_1
FRCK0_2
IC02_0
WKUP1
P12
AN02
SOT1_1
IC00_2
P13
AN03
SCK1_1
IC01_2
RTCCO_1
SUBOUT_1
P14
AN04
SIN0_1
INT03_1
IC02_2
I/O circuit
type
Pin state
type
-
D
M
D
N
B
C
E
I
E
I
-
C
P
J
D
A
A
A
B
-
F
K
F
F
F
K
F
K
F
L
13
D a t a S h e e t
Pin No
LQFP-48
LQFP-52
QFN-48
30
32
31
32
33
-
33
34
35
36
34
37
35
38
36
39
-
40
37
41
38
42
39
43
40
44
41
45
42
46
43
47
14
CONFIDENTIAL
Pin Name
P15
AN05
SOT0_1
IC03_2
AVCC
AVRH
AVSS
NC
P23
AN06
SCK0_0
TIOA7_1
P22
AN07
SOT0_0
TIOB7_1
P21
SIN0_0
INT06_1
WKUP2
NC
P00
TRSTX
P01
TCK
SWCLK
P02
TDI
P03
TMS
SWDIO
P04
TDO
SWO
P0F
NMIX
CROUT_1
RTCCO_0
SUBOUT_0
WKUP0
P61
SOT5_0
TIOB2_2
UHCONX
DTTI0X_2
I/O circuit
type
Pin state
type
F
K
-
F
K
F
K
E
G
E
E
E
E
E
E
E
E
E
E
E
J
E
I
MB9A310K-DS706-00029-2v0-E, February 20, 2015
D a t a S h e e t
Pin No
LQFP-48
LQFP-52
QFN-48
44
48
45
49
46
50
47
51
48
* : 5V tolerant I/O
52
February 20, 2015, MB9A310K-DS706-00029-2v0-E
CONFIDENTIAL
Pin Name
P60
SIN5_0
TIOA2_2
INT15_1
IC00_0
WKUP3
USBVCC
P80
UDM0
P81
UDP0
VSS
I/O circuit
type
Pin state
type
I*
G
H
O
H
O
-
15
D a t a S h e e t
 List of pin functions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Pin No
Module
Pin name
ADC
ADTG_2
AN00
AN01
AN02
AN03
AN04
AN05
AN06
AN07
TIOA0_1
TIOB0_0
TIOA1_1
TIOB1_0
TIOA2_1
TIOA2_2
TIOB2_2
A/D converter external trigger input pin
Base timer ch.2 TIOB pin
LQFP-48
QFN-48
5
25
26
27
28
29
30
34
35
6
18
7
19
8
44
43
TIOA3_1
Base timer ch.3 TIOA pin
9
10
TIOA4_1
Base timer ch.4 TIOA pin
10
11
TIOA5_1
Base timer ch.5 TIOA pin
11
12
TIOA7_1
TIOB7_1
SWCLK
Base timer ch.7 TIOA pin
Base timer ch.7 TIOB pin
Serial wire debug interface clock input pin
Serial wire debug interface data input/output
pin
Serial wire viewer output pin
J-TAG test clock input pin
J-TAG test data input pin
J-TAG debug data output pin
J-TAG test mode state input/output pin
J-TAG test reset Input pin
External interrupt request 00 input pin
External interrupt request 01 input pin
34
35
38
37
38
42
40
44
41
38
39
41
40
37
2
3
4
26
29
36
44
42
45
42
43
45
44
41
2
3
4
28
31
39
48
46
Base Timer
0
Base Timer
1
Base Timer
2
Base Timer
3
Base Timer
4
Base Timer
5
Base Timer
7
Debugger
SWDIO
External
Interrupt
16
CONFIDENTIAL
SWO
TCK
TDI
TDO
TMS
TRSTX
INT00_0
INT01_0
INT02_0
INT02_1
INT03_1
INT06_1
INT15_1
NMIX
Function
A/D converter analog input pin.
ANxx describes ADC ch.xx.
Base timer ch.0 TIOA pin
Base timer ch.0 TIOB pin
Base timer ch.1 TIOA pin
Base timer ch.1 TIOB pin
Base timer ch.2 TIOA pin
External interrupt request 02 input pin
External interrupt request 03 input pin
External interrupt request 06 input pin
External interrupt request 15 input pin
Non-Maskable Interrupt input pin
LQFP-52
6
27
28
29
30
31
32
37
38
7
19
8
20
9
48
47
MB9A310K-DS706-00029-2v0-E, February 20, 2015
D a t a S h e e t
Pin No
Module
Pin name
GPIO
P00
P01
P02
P03
P04
P0F
P10
P11
P12
P13
P14
P15
P21
P22
P23
P39
P3A
P3B
P3C
P3D
P3E
P3F
P46
P47
P49
P4A
P50
P51
P52
P60
P61
P80
P81
PE0
PE2
PE3
Function
General-purpose I/O port 0
General-purpose I/O port 1
General-purpose I/O port 2
General-purpose I/O port 3
General-purpose I/O port 4
General-purpose I/O port 5
General-purpose I/O port 6
General-purpose I/O port 8
General-purpose I/O port E
February 20, 2015, MB9A310K-DS706-00029-2v0-E
CONFIDENTIAL
LQFP-48
QFN-48
37
38
39
40
41
42
25
26
27
28
29
30
36
35
34
5
6
7
8
9
10
11
15
16
18
19
2
3
4
44
43
46
47
20
22
23
LQFP-52
41
42
43
44
45
46
27
28
29
30
31
32
39
38
37
6
7
8
9
10
11
12
16
17
19
20
2
3
4
48
47
50
51
22
24
25
17
D a t a S h e e t
Pin No.
Module
Pin name
Multifunction
Serial
0
SIN0_0
SIN0_1
SOT0_0
(SDA0_0)
SOT0_1
(SDA0_1)
SCK0_0
(SCL0_0)
Multifunction
Serial
1
SIN1_1
SOT1_1
(SDA1_1)
SCK1_1
(SCL1_1)
18
CONFIDENTIAL
Function
Multi-function serial interface ch.0 input
pin
Multi-function serial interface ch.0 output
pin.
This pin operates as SOT0 when it is used
in a UART/CSIO/LIN (operation modes
0 to 3) and as SDA0 when it is used in an
I2C (operation mode 4).
Multi-function serial interface ch.0 clock
I/O pin.
This pin operates as SCK0 when it is used
in a CSIO (operation modes 2) and as
SCL0 when it is used in an I2C (operation
mode 4).
Multi-function serial interface ch.1 input
pin
Multi-function serial interface ch.1 output
pin.
This pin operates as SOT1 when it is used
in a UART/CSIO/LIN (operation modes
0 to 3) and as SDA1 when it is used in an
I2C (operation mode 4).
Multi-function serial interface ch.1 clock
I/O pin.
This pin operates as SCK1 when it is used
in a CSIO (operation modes 2) and as
SCL1 when it is used in an I2C (operation
mode 4).
LQFP-48
QFN-48
36
29
LQFP-52
39
31
35
38
30
32
34
37
26
28
27
29
28
30
MB9A310K-DS706-00029-2v0-E, February 20, 2015
D a t a S h e e t
Pin No.
Module
Multifunction
Serial
3
Pin name
SIN3_1
SOT3_1
(SDA3_1)
SCK3_1
(SCL3_1)
Multifunction
Serial
5
SIN5_0
SOT5_0
February 20, 2015, MB9A310K-DS706-00029-2v0-E
CONFIDENTIAL
Function
Multi-function serial interface ch.3 input
pin
Multi-function serial interface ch.3 output
pin.
This pin operates as SOT3 when it is used
in a UART/CSIO/LIN (operation modes
0 to 3) and as SDA3 when it is used in an
I2C (operation mode 4).
Multi-function serial interface ch.3 clock
I/O pin.
This pin operates as SCK3 when it is used
in a CSIO (operation modes 2) and as
SCL3 when it is used in an I2C (operation
mode 4).
Multi-function serial interface ch.5 input
pin
Multi-function serial interface ch.5 output
pin.
This pin operates as SOT5 when it is used
in a UART/LIN (operation modes 0, 1, 3).
LQFP-48
QFN-48
LQFP-52
2
2
3
3
4
4
44
48
43
47
19
D a t a S h e e t
Pin No
Module
Pin name
Multifunction
Timer
0
DTTI0X_0
DTTI0X_2
FRCK0_2
IC00_0
IC00_2
IC01_2
IC02_0
IC02_2
IC03_2
RTO00_0
(PPG00_0)
RTO01_0
(PPG00_0)
RTO02_0
(PPG02_0)
RTO03_0
(PPG02_0)
RTO04_0
(PPG04_0)
RTO05_0
(PPG04_0)
20
CONFIDENTIAL
Function
LQFP-48
QFN-48
LQFP-52
Input signal controlling wave form
generator outputs RTO00 to RTO05 of
multi-function timer 0.
16-bit free-run timer ch.0 external clock
input pin
5
6
43
47
26
28
16-bit input capture ch.0 input pin of
multi-function timer 0.
ICxx describes channel number.
44
27
28
26
29
30
48
29
30
28
31
32
6
7
7
8
8
9
9
10
10
11
11
12
Wave form generator output pin of
multi-function timer 0.
This pin operates as PPG00 when it is
used in PPG0 output modes.
Wave form generator output pin of
multi-function timer 0.
This pin operates as PPG00 when it is
used in PPG0 output modes.
Wave form generator output pin of
multi-function timer 0.
This pin operates as PPG02 when it is
used in PPG0 output modes.
Wave form generator output pin of
multi-function timer 0.
This pin operates as PPG02 when it is
used in PPG0 output modes.
Wave form generator output pin of
multi-function timer 0.
This pin operates as PPG04 when it is
used in PPG0 output modes.
Wave form generator output pin of
multi-function timer 0.
This pin operates as PPG04 when it is
used in PPG0 output modes.
MB9A310K-DS706-00029-2v0-E, February 20, 2015
D a t a S h e e t
Pin No
Module
Pin name
Quadrature
Position/
Revolution
Counter
0
AIN0_2
Real-time
clock
RTCCO_0
Function
LQFP-48
QFN-48
LQFP-52
QPRC ch.0 AIN input pin
2
2
BIN0_2
QPRC ch.0 BIN input pin
3
3
ZIN0_2
QPRC ch.0 ZIN input pin
4
4
42
46
28
30
6
7
42
46
28
30
6
7
RTCCO_1
0.5 seconds pulse output pin of Real-time
clock
RTCCO_2
SUBOUT_0
SUBOUT_1
Sub clock output pin
SUBOUT_2
Low Power
Consumption
Mode
USB
WKUP0
Deep stand-by mode return signal input
pin 0
42
46
WKUP1
Deep stand-by mode return signal input
pin 1
26
28
WKUP2
Deep stand-by mode return signal input
pin 2
36
39
WKUP3
Deep stand-by mode return signal input
pin 3
44
48
UDM0
USB ch.0 function/host D – pin
46
50
UDP0
USB ch.0 function/host D + pin
47
51
UHCONX
USB external pull-up control pin
43
47
February 20, 2015, MB9A310K-DS706-00029-2v0-E
CONFIDENTIAL
21
D a t a S h e e t
Pin No
Module
RESET
Pin name
INITX
Mode
MD0
MD1
POWER
GND
CLOCK
VCC
VCC
USBVCC
VSS
VSS
VSS
X0
X0A
X1
X1A
CROUT_1
Analog
POWER
Analog
GND
C pin
NC pin
LQFP-52
17
18
21
23
20
22
1
14
45
12
24
48
22
15
23
16
1
15
49
13
26
52
24
16
25
17
42
46
A/D converter analog power pin
31
33
AVRH
A/D converter analog reference voltage
input pin
32
34
AVSS
A/D converter GND pin
33
35
Power stabilization capacity pin
13
14
-
5
-
21
-
36
-
40
C
NC
NC
NC
CONFIDENTIAL
External Reset Input pin.
A reset is valid when INITX="L".
Mode 0 pin.
During normal operation, MD0="L" must
be input. During serial programming to
Flash memory, MD0="H" must be input.
Mode 1 pin.
During serial programming to Flash
memory, MD1="L" must be input.
Power supply Pin
Power supply Pin
3.3V Power supply port for USB I/O
GND Pin
GND Pin
GND Pin
Main clock (oscillation) input pin
Sub clock (oscillation) input pin
Main clock (oscillation) I/O pin
Sub clock (oscillation) I/O pin
Built-in high-speed CR-osc clock output
port
LQFP-48
QFN-48
AVCC
NC
22
Function
NC pin.
NC pin should be kept open.
NC pin.
NC pin should be kept open.
NC pin.
NC pin should be kept open.
NC pin.
NC pin should be kept open.
MB9A310K-DS706-00029-2v0-E, February 20, 2015
D a t a S h e e t
 I/O Circuit Type
Type
Circuit
Remarks
A
It is possible to select the main
oscillation / GPIO function
Pull-up
resistor
P-ch
P-ch
Digital output
X1
N-ch
Digital output
R
Pull-up resistor control
Digital input
Standby mode Control
When the main oscillation is
selected.
 Oscillation feedback
resistor
: Approximately 1MΩ
 With Standby mode control
When the GPIO is selected.
 CMOS level output.
 CMOS level hysteresis
input
 With pull-up resistor
control
 With standby mode control
 Pull-up resistor
: Approximately 50kΩ
 IOH= -4mA, IOL= 4mA
Clock input
Feedback
resistor
Standby mode Control
Digital input
Standby mode Control
Pull-up
resistor
R
P-ch
P-ch
Digital output
N-ch
Digital output
X0
Pull-up resistor control
 CMOS level hysteresis
input
 Pull-up resistor
: Approximately 50kΩ
B
Pull-up resistor
Digital input
February 20, 2015, MB9A310K-DS706-00029-2v0-E
CONFIDENTIAL
23
D a t a S h e e t
Type
Circuit
Remarks
 Open drain output
 CMOS level hysteresis
input
C
Digital input
Digital output
N-ch
D
It is possible to select the sub
oscillation / GPIO function
Pull-up
When the sub oscillation is
selected.
 Oscillation feedback
resistor
: Approximately 5MΩ
 With Standby mode control
resistor
P-ch
P-ch
Digital output
X1A
N-ch
Digital output
R
Pull-up resistor control
Digital input
Standby mode Control
Clock input
When the GPIO is selected.
 CMOS level output.
 CMOS level hysteresis
input
 With pull-up resistor
control
 With standby mode control
 Pull-up resistor
: Approximately 50kΩ
 IOH= -4mA, IOL= 4mA
Feedback
resistor
Standby mode Control
Digital input
Standby mode Control
Pull-up
resistor
R
P-ch
P-ch
Digital output
N-ch
Digital output
X0A
Pull-up resistor control
24
CONFIDENTIAL
MB9A310K-DS706-00029-2v0-E, February 20, 2015
D a t a S h e e t
Type
Circuit
Remarks
E
P-ch
P-ch
N-ch
Digital output
Digital output
R
 CMOS level output
 CMOS level hysteresis
input
 With pull-up resistor
control
 With standby mode control
 Pull-up resistor
: Approximately 50kΩ
 IOH= -4mA, IOL= 4mA
 When this pin is used as an
I2C pin, the digital output
P-ch transistor is always off
 +B input is available
Pull-up resistor control
Digital input
Standby mode Control
F
P-ch
P-ch
N-ch
R
Digital output
Digital output
Pull-up resistor control
 CMOS level output
 CMOS level hysteresis
input
 With input control
 Analog input
 With pull-up resistor
control
 With standby mode control
 Pull-up resistor
: Approximately 50kΩ
 IOH= -4mA, IOL= 4mA
 When this pin is used as an
I2C pin, the digital output
P-ch transistor is always off
 +B input is available
Digital input
Standby mode Control
Analog input
Input control
February 20, 2015, MB9A310K-DS706-00029-2v0-E
CONFIDENTIAL
25
D a t a S h e e t
Type
Circuit
Remarks
 CMOS level output
 CMOS level hysteresis
input
 With pull-up resistor
control
 With standby mode control
 Pull-up resistor
: Approximately 50kΩ
 IOH= -12mA, IOL= 12mA
 +B input is available
G
P-ch
P-ch
Digital output
N-ch
Digital output
R
Pull-up resistor control
Digital input
Standby mode Control
H
It is possible to select the
USB I/O / GPIO function.
GPIO Digital output
GPIO Digital input/output direction
GPIO Digital input
GPIO Digital input circuit control
When the USB I/O is selected.
 Full-speed, Low-speed
control
UDP output
UDP/P81
USB Full-speed/Low-speed control
UDP input
Differential
UDM/P80
Differential input
USB/GPIO select
UDM input
When the GPIO is selected.
 CMOS level output
 CMOS level hysteresis
input
 With standby mode control
IOH = -20.5mA,
IOL = 18.5mA
UDM output
USB Digital input/output direction
GPIO Digital input
GPIO Digital input/output direction
GPIO Digital input
GPIO Digital input circuit control
26
CONFIDENTIAL
MB9A310K-DS706-00029-2v0-E, February 20, 2015
D a t a S h e e t
Type
Circuit
Remarks
I
P-ch
P-ch
N-ch
Digital output
Digital output
R
 CMOS level output
 CMOS level hysteresis
input
 5V tolerant
 With pull-up resistor
control
 With standby mode control
 Pull-up resistor
: Approximately 50kΩ
 IOH= -4mA, IOL= 4mA
 Available to control of PZR
registers.
Pull-up resistor control
Digital input
Standby mode Control
J
CMOS level hysteresis input
Mode input
February 20, 2015, MB9A310K-DS706-00029-2v0-E
CONFIDENTIAL
27
D a t a S h e e t
 Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly
affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This
page describes precautions that must be observed to minimize the chance of failure and to obtain higher
reliability from your Spansion semiconductor devices.
1. Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
 Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.
 Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the
device's electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these
ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data
sheet. Users considering application outside the listed conditions are advised to contact their sales
representative beforehand.
 Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power
supply and input/output functions.
(1) Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause
deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to
prevent such overvoltage or over-current conditions at the design stage.
(2) Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can
cause large current flows. Such conditions if present for extended periods of time can damage the
device.
Therefore, avoid this type of connection.
(3) Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation.
Such pins should be connected through an appropriate resistance to a power supply pin or ground pin.
 Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When
subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may
be formed, causing large current levels in excess of several hundred mA to flow continuously at the power
supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but
can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the
following:
(1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should
include attention to abnormal noise, surge levels, etc.
(2) Be sure that abnormal current flows do not occur during the power-on sequence.
Code: DS00-00004-3E
28
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MB9A310K-DS706-00029-2v0-E, February 20, 2015
D a t a S h e e t
 Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from
electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards
in the design of products.
 Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury,
damage or loss from such failures by incorporating safety design measures into your facility and equipment
such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions.
 Precautions Related to Usage of Devices
Spansion semiconductor devices are intended for use in standard applications (computers, office automation
and other office equipment, industrial, communications, and measurement equipment, personal or
household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or
abnormal operation may directly affect human lives or cause physical injury or property damage, or where
extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea
floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult
with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
2. Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance
during soldering, you should only mount under Spansion's recommended conditions. For detailed
information about mount conditions, contact your sales representative.
 Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct
soldering on the board, or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the
board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the
soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for
storage temperature. Mounting processes should conform to Spansion recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can
lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment
of socket contacts and IC leads be verified before mounting.
 Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are
more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in
increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Spansion recommends the solder reflow method, and has
established a ranking of mounting conditions for each product. Users are advised to mount packages in
accordance with Spansion ranking of recommended conditions.
February 20, 2015, MB9A310K-DS706-00029-2v0-E
CONFIDENTIAL
29
D a t a S h e e t
 Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic
soldering, junction strength may be reduced under some conditions of use.
 Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions
will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed
moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent,
do the following:
(1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product.
Store products in locations where temperature changes are slight.
(2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at
temperatures between 5°C and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
(3) When necessary, Spansion packages semiconductor devices in highly moisture-resistant aluminum
laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags
for storage.
(4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
 Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Spansion
recommended conditions for baking.
Condition: 125°C/24 h
 Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take
the following precautions:
(1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus
for ion generation may be needed to remove electricity.
(2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
(3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high
resistance (on the level of 1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to
minimize shock loads is recommended.
(4) Ground all fixtures and instruments, or protect with anti-static measures.
(5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board
assemblies.
30
CONFIDENTIAL
MB9A310K-DS706-00029-2v0-E, February 20, 2015
D a t a S h e e t
3. Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described
above.
For reliable performance, do the following:
(1) Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high
humidity levels are anticipated, consider anti-humidity processing.
(2) Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal
operation. In such cases, use anti-static measures or processing to prevent discharges.
(3) Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will
adversely affect the device. If you use devices in such conditions, consider ways to prevent such
exposure or to protect the devices.
(4) Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation.
Users should provide shielding as appropriate.
(5) Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible
substances. If devices begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Spansion products in other special environmental conditions should
consult with sales representatives.
Please check the latest handling precautions at the following URL.
http://www.spansion.com/fjdocuments/fj/datasheet/e-ds/DS00-00004.pdf
February 20, 2015, MB9A310K-DS706-00029-2v0-E
CONFIDENTIAL
31
D a t a S h e e t
 Handling Devices
 Power supply pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected
within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be
connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels,
to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the
total output current rating.
Moreover, connect the current supply source with each Power supply pins and GND pins of this device at
low impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a
bypass capacitor between each Power supply pins and GND pins, between AVCC pin and AVSS pin near
this device.
 Stabilizing power supply voltage
A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is
within the recommended operating conditions of the VCC power supply voltage. As a rule, with voltage
stabilization, suppress the voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at
the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC value in the recommended
operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a momentary
fluctuation on switching the power supply.
 Crystal oscillator circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit
board so that X0/X1, X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor
to ground are located as close to the device as possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins
are surrounded by ground plane as this is expected to produce stable operation.
Evaluate oscillation of your using crystal oscillator by your mount board.
 Using an external clock
When using an external clock, the clock signal should be input to the X0, X0A pin only and the X1, X1A
pin should be kept open.
 Example of Using an External Clock
Device
X0(X0A)
Open
X1(X1A)
2
 Handling when using Multi-function serial pin as I C pin
If it is using Multi-function serial pin as I2C pins, P-ch transistor of digital output is always disable.
However, I2C pins need to keep the electrical characteristic like other pins and not to connect to external I2C
bus system with power OFF.
32
CONFIDENTIAL
MB9A310K-DS706-00029-2v0-E, February 20, 2015
D a t a S h e e t
 C pin
This series contains the regulator. Be sure to connect a smoothing capacitor (C S) for the regulator between
the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency
characteristics as a smoothing capacitor.
However, some laminated ceramic capacitors have the characteristics of capacitance variation due to
thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the
specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor.
A smoothing capacitor of about 4.7μF would be recommended for this series.
C
Device
CS
VSS
GND
 Mode pins (MD0)
Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the
pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS pins
is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for
switching the pin level and rewriting the Flash memory data. It is because of preventing the device
erroneously switching to test mode due to noise.
 NC pins
NC pin should be kept open.
 Notes on power-on
Turn power on/off in the following order or at the same time.
If not using the A/D converter, connect AVCC =VCC and AVSS = VSS.
Turning on :VCC → USBVCC
VCC → AVCC → AVRH
Turning off : USBVCC → VCC
AVRH → AVCC → VCC
 Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider the case of receiving wrong data due to noise, perform error detection such as by applying a
checksum of data at the end. If an error is detected, retransmit the data.
February 20, 2015, MB9A310K-DS706-00029-2v0-E
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33
D a t a S h e e t
 Differences in features among the products with different memory sizes and between Flash
products and MASK products
The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and
oscillation characteristics among the products with different memory sizes and between Flash products and
MASK products are different because chip layout and memory structures are different.
If you are switching to use a different product of the same series, please make sure to evaluate the electric
characteristics.
 Pull-Up function of 5V tolerant I/O
Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5V tolerant I/O.
34
CONFIDENTIAL
MB9A310K-DS706-00029-2v0-E, February 20, 2015
D a t a S h e e t
 Block Diagram
MB9AF311K, F312K
TRSTX,TCK,
TDI,TMS
TDO
SRAM0
8 Kbyte
SWJ-DP
ROM
Table
SRAM1
8 Kbyte
Multi-layer AHB (Max 42 MHz)
Cortex-M3 Core I
@40 MHz(Max)
D
NVIC
Sys
AHB-APB Bridge:
APB0(Max 42 MHz)
Dual-Timer
Watchdog Timer
(Software)
Clock Reset
Generator
INITX
Watchdog Timer
(Hardware)
MainFlash I/F
Security
MainFlash
64 Kbyte/
128 Kbyte
WorkFlash I/F
WorkFlash
32 Kbyte
USB2.0 PHY
(Host/
Func)
USBVCC
UDP0,UDM0
UHCONX
DMAC
4ch.
CSV
X0
X1
X0A
Main
Osc
Sub
Osc
PLL
AHB-AHB
Bridge
CLK
Source Clock
CR
4MHz
CR
100kHz
CROUT
AVCC,
AVSS,
AVRH
12-bit A/D Converter
USB Clock Ctrl
Unit 0
Power-On
Reset
AN[07:00]
Unit 1
LVD Ctrl
ADTG_2
AIN0
BIN0
ZIN0
QPRC
1ch.
A/D Activation Compare
3ch.
IC0x
FRCKx
16-bit Input Capture
4ch.
16-bit Free-Run Timer
3ch.
16-bit Output Compare
6ch.
DTTI0X
RTOx
Waveform Generator
3ch.
16-bit PPG
3ch.
Multi-Function Timer
Deep Standby Ctrl
AHB-APB Bridge : APB2 (Max 42 MHz)
TIOBx
LVD
Regulator
Base Timer
16-bit 8ch./
32-bit 4ch.
AHB-APB Bridge : APB1 (Max 42 MHz)
TIOAx
PLL
C
WKUP[3:0]
RTCCO,
SUBOUT
Real-Time Clock
IRQ-Monitor
CRC
Accelerator
Watch Counter
External Interrupt
Controller
6-pin + NMI
INTx
NMIX
MODE-Ctrl
GPIO
Multi-Function Serial I/F
4ch.
(with FIFO ch.0 - ch.1)
MD[1:0]
PIN-Function-Ctrl
P0x,
P1x,
.
.
.
PFx
SCKx
SINx
SOTx
 Memory Size
See "Memory size" in "Product Lineup" to confirm the memory size.
February 20, 2015, MB9A310K-DS706-00029-2v0-E
CONFIDENTIAL
35
D a t a S h e e t
 Memory Map
 Memory Map (1)
Peripherals Area
0x41FF_FFFF
Reserved
0xFFFF_FFFF
0x4006_1000
Reserved
DMAC
Reserved
0xE010_0000
0xE000_0000
0x4006_0000
Cortex-M3 Private
Peripherals
0x4005_0000
USB ch.0
0x4004_0000
Reserved
Reserved
0x7000_0000
0x6000_0000
External Device
Area
Reserved
0x4400_0000
0x4200_0000
0x4000_0000
32Mbyte
Bit band alias
Peripherals
0x4003_C000
0x4003_B000
RTC
0x4003_A000
Watch Counter
0x4003_9000
CRC
0x4003_8000
MFS
0x4003_6000
Reserved
USB Clock Ctrl
0x4003_5000
LVD/DS mode
0x4003_4000
Reserved
0x4003_7000
0x4003_3000
GPIO
0x4003_2000
Reserved
0x4003_1000
Int-Req. Read
0x4003_0000
0x4002_F000
Reserved
0x4002_E000
32Mbyte
Bit band alias
0x4002_8000
0x2400_0000
0x2200_0000
EXTI
Reserved
CR Trim
Reserved
0x4002_7000
A/DC
0x200E_1000
Reserved
0x4002_6000
QPRC
0x200E_0000
WorkFlash I/F
0x4002_5000
Base Timer
0x200C_0000
WorkFlash
0x4002_4000
PPG
0x2008_0000
Reserved
0x2000_0000
SRAM1
See the next page
"Memory Map (2)" for
0x1FFF_0000
SRAM0
the memory size
details.
0x0010_2000
Reserved
0x4002_1000
0x4002_0000
0x0010_0000
Reserved
0x4001_6000
Security/CR Trim
0x4001_5000
0x4001_3000
MainFlash
0x0000_0000
Reserved
SW WDT
0x4001_1000
HW WDT
0x4001_0000
Clock/Reset
0x4000_0000
CONFIDENTIAL
Reserved
Dual Timer
0x4001_2000
0x4000_1000
36
MFT unit0
Reserved
MainFlash I/F
MB9A310K-DS706-00029-2v0-E, February 20, 2015
D a t a S h e e t

Memory Map (2)
MB9AF311K
MB9AF312K
0x200E_0000
0x200E_0000
Reserved
Reserved
0x200C_8000
SA0-3 (8KBx4)
0x200C_0000
0x200C_0000
Reserved
Reserved
0x2000_2000
0x2000_2000
SRAM1
8Kbyte
SRAM1
8Kbyte
0x2000_0000
0x2000_0000
0x1FFF_E000
WorkFlash
32Kbyte
SA0-3 (8KBx4)
WorkFlash
32Kbyte
0x200C_8000
SRAM0
8Kbyte
0x1FFF_E000
SRAM0
8Kbyte
Reserved
Reserved
0x0010_2000
0x0010_2000
0x0010_1000
CR trimming
0x0010_1000
CR trimming
0x0010_0000
Security
0x0010_0000
Security
Reserved
Reserved
0x0002_0000
SA4-7 (8KBx4)
0x0001_0000
SA8-9 (16KBx2)
0x0000_0000
MainFlash
64Kbyte
0x0000_0000
MainFlash
128Kbyte
SA8-9 (48KBx2)
SA4-7 (8KBx4)
* : See "MB9A310K/110K Series Flash programming Manual" for sector structure of Flash.
February 20, 2015, MB9A310K-DS706-00029-2v0-E
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37
D a t a S h e e t
 Peripheral Address Map
Start address
End address
0x4000_0000
0x4000_0FFF
0x4000_1000
0x4000_FFFF
0x4001_0000
0x4001_0FFF
Clock/Reset Control
0x4001_1000
0x4001_1FFF
Hardware Watchdog timer
0x4001_2000
0x4001_2FFF
0x4001_3000
0x4001_4FFF
0x4001_5000
0x4001_5FFF
Dual-Timer
0x4001_6000
0x4001_FFFF
Reserved
0x4002_0000
0x4002_0FFF
Multi-function timer unit0
0x4002_1000
0x4002_3FFF
Reserved
0x4002_4000
0x4002_4FFF
PPG
0x4002_5000
0x4002_5FFF
Base Timer
0x4002_6000
0x4002_6FFF
0x4002_7000
0x4002_7FFF
A/D Converter
0x4002_8000
0x4002_DFFF
Reserved
0x4002_E000
0x4002_EFFF
Internal CR trimming
0x4002_F000
0x4002_FFFF
Reserved
0x4003_0000
0x4003_0FFF
External Interrupt Controller
0x4003_1000
0x4003_1FFF
Interrupt Request Batch-Read Function
0x4003_2000
0x4003_2FFF
Reserved
0x4003_3000
0x4003_3FFF
GPIO
0x4003_4000
0x4003_4FFF
Reserved
0x4003_5000
0x4003_57FF
Low-Voltage Detector
0x4003_5800
0x4003_5FFF
0x4003_6000
0x4003_6FFF
0x4003_7000
0x4003_7FFF
Reserved
0x4003_8000
0x4003_8FFF
Multi-function serial Interface
0x4003_9000
0x4003_9FFF
CRC
0x4003_A000
0x4003_AFFF
Watch Counter
0x4003_B000
0x4003_BFFF
Real-time clock
0x4003_C000
0x4003_FFFF
Reserved
0x4004_0000
0x4004_FFFF
USB ch.0
0x4005_0000
0x4005_FFFF
0x4006_0000
0x4006_0FFF
0x4006_1000
0x41FF_FFFF
Reserved
0x200E_0000
0x200E_FFFF
WorkFlash I/F register
38
CONFIDENTIAL
Bus
AHB
APB0
APB1
APB2
Peripherals
MainFlash I/F register
Reserved
Software Watchdog timer
Reserved
Quadrature Position/Revolution Counter
Deep stand-by mode Controller
USB clock generator
Reserved
AHB
DMAC register
MB9A310K-DS706-00029-2v0-E, February 20, 2015
D a t a S h e e t
 Pin Status in Each CPU State
The terms used for pin status have the following meanings.
 INITX=0
This is the period when the INITX pin is the "L" level.
 INITX=1
This is the period when the INITX pin is the "H" level.
 SPL=0
This is the status that standby pin level setting bit (SPL) in standby mode control register (STB_CTL) is
set to "0".
 SPL=1
This is the status that standby pin level setting bit (SPL) in standby mode control register (STB_CTL) is
set to "1".
 Input enabled
Indicates that the input function can be used.
 Internal input fixed at "0"
This is the status that the input function cannot be used. Internal input is fixed at "L".
 Hi-Z
Indicates that the output drive transistor is disabled and the pin is put in the Hi-Z state.
 Setting disabled
Indicates that the setting is disabled.
 Maintain previous state
Maintains the state that was immediately prior to entering the current mode.
If a built-in peripheral function is operating, the output follows the peripheral function.
If the pin is being used as a port, that output is maintained.
 Analog input is enabled
Indicates that the analog input is enabled.
 GPIO selected
In Deep stand-by mode, pins switch to the general-purpose I/O port.
February 20, 2015, MB9A310K-DS706-00029-2v0-E
CONFIDENTIAL
39
D a t a S h e e t
Pin status type
 List of Pin Status
Function
group
Power-on
reset or
Device Run mode
INITX input
low-voltage
internal
or sleep
state
detection
reset state mode state
state
Power
supply
unstable
-
Power
supply
stable
INITX = 0 INITX = 1 INITX = 1
Power supply stable
Timer mode,
RTC mode, or
sleep mode state
Deep stand-by RTC Return from
mode or Deep
Deep
stand-by STOP mode stand-by
state
mode state
Power supply stable
Power supply stable
INITX = 1
SPL = 0
SPL = 1
INITX = 1
SPL = 0
SPL = 1
Power
supply
stable
INITX = 1
-
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state
Main crystal
oscillator input
pin
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state
Main crystal
oscillator output
pin
Hi-Z/
Internal
input
fixed at
"0"/
or Input
enable
C
INITX
input pin
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
D
Mode
input pin
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
JTAG
selected
Hi-Z
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state
A
B
Hi-Z /
Hi-Z /
Internal
Internal
input fixed input fixed
at "0"
at "0"
Maintain
previous
state
E
GPIO
selected
40
CONFIDENTIAL
Maintain
Maintain
Maintain
Maintain
Maintain
previous
previous
previous
previous
previous
state /When state /When state /When state /When state /When
Maintain
oscillation oscillation oscillation oscillation oscillation
previous
stop*1,Hi-Z/ stop*1,Hi-Z/ stop*1,Hi-Z/ stop*1,Hi-Z/ stop*1,Hi-Z//
state
Internal
Internal
Internal
Internal
Internal
input fixed input fixed input fixed input fixed input fixed
at "0"
at "0"
at "0"
at "0"
at "0"
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
MB9A310K-DS706-00029-2v0-E, February 20, 2015
Pin status type
D a t a S h e e t
Function
group
Power-on
reset or
Device Run mode
INITX input
low-voltage
internal
or sleep
state
detection
reset state mode state
state
Power
supply
unstable
-
WKUP
enabled
Analog input
selected
Setting
disabled
Hi-Z
F
Power
supply
stable
INITX = 0 INITX = 1 INITX = 1
Power supply stable
Setting
disabled
Setting
disabled
Maintain
previous
state
Timer mode,
RTC mode, or
sleep mode state
Power supply stable
Power supply stable
INITX = 1
SPL = 0
SPL = 1
INITX = 1
SPL = 0
SPL = 1
Maintain
previous
state
WKUP
input
enabled
Maintain
previous
state
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
GPIO
selected
G
WKUP
enabled
Setting
disabled
Setting
disabled
Setting
disabled
External
interrupt
enabled selected
Setting
disabled
Setting
disabled
Setting
disabled
Resource other
than above
selected
Hi-Z
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Setting
disabled
Setting
disabled
Setting
disabled
GPIO
selected
External
interrupt
enabled selected
H
Resource other
than above
selected
Hi-Z
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Hi-Z
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
GPIO
selected
resource
selected
I
GPIO
selected
February 20, 2015, MB9A310K-DS706-00029-2v0-E
CONFIDENTIAL
Maintain
previous
state
Hi-Z /
WKUP
input
enabled
Power
supply
stable
INITX = 1
GPIO
selected
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
input fixed input fixed input fixed input fixed input fixed input fixed input fixed
input fixed
at "0" /
at "0" /
at "0" /
at "0" /
at "0" /
at "0" /
at "0" /
at "0" /
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog input
input
input
input
input
input
input
input
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
External
interrupt
enabled selected
Resource other
than above
selected
Deep stand-by RTC Return from
mode or Deep
Deep
stand-by STOP mode stand-by
state
mode state
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
GPIO
selected
Maintain
previous
state
WKUP
input
enabled
GPIO
selected
Maintain
previous
state
GPIO
selected
Maintain
previous
state
GPIO
selected
Maintain
previous
state
Hi-Z /
Internal
input fixed
at "0"
Hi-Z /
WKUP
input
enabled
Hi-Z /
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
GPIO
selected
Maintain
previous
state
GPIO
selected
GPIO
selected
Maintain
previous
state
GPIO
selected
Maintain
previous
state
GPIO
selected
Maintain
previous
state
41
Pin status type
D a t a S h e e t
Function
group
Power
supply
unstable
-
NMIX
selected
J
Power-on
reset or
Device Run mode
INITX input
low-voltage
internal
or sleep
state
detection
reset state mode state
state
Resource other
than above
selected
Setting
disabled
Hi-Z
GPIO
selected
Analog input
selected
Hi-Z
K
Resource other
than above
selected
GPIO
selected
Analog input
selected
L
Setting
disabled
Hi-Z
Power
supply
stable
INITX = 0 INITX = 1 INITX = 1
Power supply stable
Setting
disabled
Hi-Z /
Input
enabled
Timer mode,
RTC mode, or
sleep mode state
Power supply stable
Power supply stable
INITX = 1
SPL = 0
SPL = 1
INITX = 1
SPL = 0
SPL = 1
Maintain
previous
state
Setting
disabled
Hi-Z /
Input
enabled
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input fixed
at "0"
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input fixed
at "0"
Hi-Z /
WKUP
input
enabled
GPIO
selected
Maintain
previous
state
GPIO
selected
Maintain
previous
state
Hi-Z /
Internal
input fixed
at "0"
GPIO
selected
Maintain
previous
state
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
input fixed input fixed input fixed input fixed input fixed input fixed input fixed
input fixed
at "0" /
at "0" /
at "0" /
at "0" /
at "0" /
at "0" /
at "0" /
at "0" /
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog input
input
input
input
input
input
input
input
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
Maintain
previous
state
Setting
disabled
WKUP
input
enabled
Power
supply
stable
INITX = 1
-
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
input fixed input fixed input fixed input fixed input fixed input fixed input fixed
input fixed
at "0" /
at "0" /
at "0" /
at "0" /
at "0" /
at "0" /
at "0" /
at "0" /
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog input
input
input
input
input
input
input
input
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
External
interrupt
enabled selected
Resource other
than above
selected
Deep stand-by RTC Return from
mode or Deep
Deep
stand-by STOP mode stand-by
state
mode state
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
GPIO
selected
Hi-Z /
Internal
input fixed
at "0"
GPIO
selected
Maintain
previous
state
Hi-Z /
Internal
input fixed
at "0"
GPIO
selected
Maintain
previous
state
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state
Sub crystal
oscillator input
pin
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
M
42
CONFIDENTIAL
MB9A310K-DS706-00029-2v0-E, February 20, 2015
Pin status type
D a t a S h e e t
Function
group
Power-on
reset or
Device Run mode
INITX input
low-voltage
internal
or sleep
state
detection
reset state mode state
state
Power
supply
unstable
-
GPIO
selected
Setting
disabled
Sub crystal
oscillator output
pin
Hi-Z/
Internal
input
fixed at
"0"/
or Input
enable
N
GPIO
selected
Hi-Z
Power
supply
stable
INITX = 0 INITX = 1 INITX = 1
Power supply stable
Setting
disabled
Setting
disabled
Hi-Z /
Hi-Z /
Internal
Internal
input fixed input fixed
at "0"
at "0"
Hi-Z /
Input
enabled
Maintain
previous
state
Timer mode,
RTC mode, or
sleep mode state
Deep stand-by RTC Return from
mode or Deep
Deep
stand-by STOP mode stand-by
state
mode state
Power supply stable
Power supply stable
INITX = 1
SPL = 0
SPL = 1
INITX = 1
SPL = 0
SPL = 1
Maintain
previous
state
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state
Hi-Z /
Internal
input fixed
at "0"
Power
supply
stable
INITX = 1
Maintain
previous
state
Maintain
Maintain
Maintain
Maintain
Maintain
previous
previous
previous
previous
previous
state /When state /When state /When state /When state /When
Maintain
oscillation oscillation oscillation oscillation oscillation
previous
stop*2,Hi-Z/ stop*2,Hi-Z/ stop*2,Hi-Z/ stop*2,Hi-Z/ stop*2,Hi-Z/
state
Internal
Internal
Internal
Internal
Internal
input fixed input fixed input fixed input fixed input fixed
at "0"
at "0"
at "0"
at "0"
at "0"
Hi-Z /
Input
enabled
Maintain
previous
state
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Hi-Z /
Input enabled
Maintain
previous
state
USB I/O pin
Setting
disabled
Setting
disabled
Setting
disabled
Hi-Z at
Hi-Z at
transmis- transmission / Input sion/ Input
Maintain
enabled/ enabled/
previous
Internal Internal
state
input fixed input fixed
at "0" at at "0" at
reception reception
Mode
input pin
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Input
enabled
Maintain
previous
state
Hi-Z /
Input
enabled
Maintain
previous
state
O
P
*1 : Oscillation is stopped at Sub timer mode, Low-speed CR timer mode, RTC mode, STOP mode, Deep
stand-by RTC mode, and Deep stand-by STOP mode.
*2 : Oscillation is stopped at STOP mode and Deep stand-by STOP mode.
February 20, 2015, MB9A310K-DS706-00029-2v0-E
CONFIDENTIAL
43
D a t a S h e e t
Electrical Characteristics
1.
Absolute Maximum Ratings
Parameter
Power supply voltage *1, *2
Power supply voltage (for USB) *1, *3
Analog power supply voltage *1, *4
Analog reference voltage *1, *4
Symbol
Min
Max
Unit
Remarks
Vss + 6.5
V
Vss + 6.5
V
Vss + 6.5
V
Vss + 6.5
V
Vcc + 0.5
Except for USB
Vss - 0.5
V
(≤6.5V)
pin
USBVcc0 + 0.5
Input voltage
VI
Vss - 0.5
V
USB pin
(≤6.5V)
Vss - 0.5
Vss + 6.5
V
5V tolerant
AVcc + 0.5
Analog pin input voltage
VIA
Vss - 0.5
V
(≤6.5V)
Vcc + 0.5
Output voltage
VO
Vss - 0.5
V
(≤6.5V)
Clamp maximum current
ICLAMP
-2
+2
mA *8
Clamp total maximum current
Σ[ICLAMP]
+20
mA *8
10
mA 4mA type
5
"L" level maximum output current *
IOL
20
mA 12mA type
39
mA P80, P81
4
mA 4mA type
"L" level average output current *6
IOLAV
12
mA 12mA type
18.5
mA P80, P81
"L" level total maximum output current
∑IOL
100
mA
"L" level total average output current *7
∑IOLAV
50
mA
- 10
mA 4mA type
"H" level maximum output current *5
IOH
- 20
mA 12mA type
- 39
mA P80, P81
-4
mA 4mA type
"H" level average output current *6
IOHAV
- 12
mA 12mA type
- 20.5
mA P80, P81
"H" level total maximum output current
∑IOH
- 100
mA
"H" level total average output current *7
∑IOHAV
- 50
mA
Power consumption
PD
300
mW
Storage temperature
TSTG
- 55
+ 150
°C
*1 : These parameters are based on the condition that V SS = AVSS = 0.0V.
*2 : Vcc must not drop below VSS - 0.5V.
*3 : USBVcc must not drop below VSS - 0.5V.
*4 : Ensure that the voltage does not to exceed Vcc + 0.5 V, for example, when the power is turned on.
*5 : The maximum output current is the peak value for a single pin.
*6 : The average output is the average current for a single pin over a period of 100 ms.
*7 : The total average output current is the average current for all pins over a period of 100 ms.
44
CONFIDENTIAL
Vcc
USBVcc
AVcc
AVRH
Rating
Vss - 0.5
Vss - 0.5
Vss - 0.5
Vss - 0.5
MB9A310K-DS706-00029-2v0-E, February 20, 2015
D a t a S h e e t
*8 :








See "List of Pin Functions" and "I/O Circuit Type" about +B input available pin.
Use within recommended operating conditions.
Use at DC voltage (current) the +B input.
The +B signal should always be applied a limiting resistance placed between the +B
signal and the device.
The value of the limiting resistance should be set so that when the +B signal is
applied the input current to the device pin does not exceed rated values, either
instantaneously or for prolonged periods.
Note that when the device drive current is low, such as in the low-power
consumpsion modes, the +B input potential may pass through the protective diode
and increase the potential at the VCC and AVCC pin, and this may affect other
devices.
Note that if a +B signal is input when the device power supply is off (not fixed at 0V),
the power supply is provided from the pins, so that incomplete operation may result.
The following is a recommended circuit example (I/O equivalent circuit).
Protection Diode
VCC
VCC
Limiting
resistor
P-ch
Digital output
+B input (0V to 16V)
N-ch
Digital input
R
AVCC
Analog input
<WARNING>
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
February 20, 2015, MB9A310K-DS706-00029-2v0-E
CONFIDENTIAL
45
D a t a S h e e t
2.
Recommended Operating Conditions
(Vss = AVss = 0.0V)
Parameter
Power supply voltage
Power supply voltage for USB
Symbol
Vcc
USBVcc
Conditions
-
Value
Min
Max
4
2.7*
5.5
3.0
3.6
(≤Vcc)
-
AVcc
AVRH
-
2.7
2.7
5.5
(≤Vcc)
5.5
AVcc
CS
-
1
10
2.7
Analog power supply voltage
Analog reference voltage
Smoothing capacitor
Unit
Remarks
V
*1
V
*2
V
V
AVcc=Vcc
μF
For built-in
regulator*3
Operating temperature
Ta
- 40
+ 105
°C
*1 : When P81/UDP0 and P80/UDM0 pin are used as USB (UDP0, UDM0).
*2 : When P81/UDP0 and P80/UDM0 pin are used as GPIO (P81, P80).
*3 : See " · C Pin" in "Handling Devices" for the connection of the smoothing capacitor.
*4 : In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage
or more, instruction execution and low voltage detection function by built-in High-speed CR(including
Main PLL is used) or built-in Low-speed CR is possible to operate only.
<WARNING>
The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure. No warranty is made
with respect to uses, operating conditions, or combinations not represented on the data sheet. Users
considering application outside the listed conditions are advised to contact their representatives beforehand.
46
CONFIDENTIAL
MB9A310K-DS706-00029-2v0-E, February 20, 2015
D a t a S h e e t
3.
DC Characteristics
(1) Current Rating
(Vcc = AVcc = 2.7V to 5.5V, USBVcc = 3.0V to 3.6V, Vss = AVss = 0V, Ta = - 40°C to + 105°C)
Parameter Symbol
Pin
name
Conditions
PLL
RUN mode
RUN
mode
current
Icc
High-speed
CR
RUN mode
VCC
Sub
RUN mode
Low-speed
CR
RUN mode
SLEEP
mode
current
Iccs
PLL
SLEEP mode
High-speed
CR
SLEEP mode
Sub
SLEEP mode
Low-speed
CR
SLEEP mode
CPU : 40 MHz,
Peripheral : 40 MHz,
MainFlash 0 Wait
FRWTR.RWT = 00
FSYNDN.SD = 000
CPU : 40 MHz,
Peripheral : 40 MHz,
MainFlash 3 Wait
FRWTR.RWT = 00
FSYNDN.SD = 011
CPU/ Peripheral : 4 MHz*2
MainFlash 0 Wait
FRWTR.RWT = 00
FSYNDN.SD = 000
CPU/ Peripheral : 32 kHz
MainFlash 0 Wait
FRWTR.RWT = 00
FSYNDN.SD = 000
CPU/ Peripheral : 100 kHz
MainFlash 0 Wait
FRWTR.RWT = 00
FSYNDN.SD = 000
Value
Unit Remarks
Typ*3 Max*4
32
41
mA
*1, *5
21
28
mA
*1, *5
3.9
7.7
mA
*1
0.15
3.2
mA
*1, *6
0.2
3.3
mA
*1
Peripheral : 40 MHz
10
15
mA
*1, *5
Peripheral : 4 MHz*2
1.2
4.4
mA
*1
Peripheral : 32 kHz
0.1
3.1
mA
*1, *6
Peripheral : 100 kHz
0.1
3.1
mA
*1
*1 : When all ports are fixed.
*2 : When setting it to 4 MHz by trimming.
*3 : Ta=+25°C, VCC=5.5V
*4 : Ta=+105°C, VCC=5.5V
*5 : When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)
*6 : When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
February 20, 2015, MB9A310K-DS706-00029-2v0-E
CONFIDENTIAL
47
D a t a S h e e t
(Vcc = AVcc = 2.7V to 5.5V, USBVcc = 3.0V to 3.6V, Vss = AVss = 0V, Ta = - 40°C to + 105°C)
Parameter Symbol
Pin
name
Conditions
Main
TIMER
mode
TIMER
mode
current
ICCT
Sub
TIMER
mode
RTC
mode
current
ICCR
STOP
mode
current
ICCH
RTC mode
STOP mode
VCC
ICCRD
Deep
stand-by
RTC mode
Deep
stand-by
mode
current
ICCHD
Deep
stand-by
STOP mode
Ta = + 25°C,
When LVD is off
Ta = + 105°C,
When LVD is off
*3
Ta = + 25°C,
When LVD is off
*4
Ta = + 105°C,
When LVD is off
*4
Ta = + 25°C,
When LVD is off
Ta = + 105°C,
When LVD is off
Ta = + 25°C,
When LVD is off
Ta = + 105°C,
When LVD is off
Ta = + 25°C,
When LVD is off
RAM hold off
Ta = + 25°C,
When LVD is off
RAM hold on
Ta = + 105°C,
When LVD is off
RAM hold off
Ta = + 105°C,
When LVD is off
RAM hold on
Ta = + 25°C,
When LVD is off
RAM hold off
Ta = + 25°C,
When LVD is off
RAM hold on
Ta = + 105°C,
When LVD is off
RAM hold off
Ta = + 105°C,
When LVD is off
RAM hold on
Value
Unit Remarks
Typ*2 Max*2
5.2
6
mA
*1, *3
-
9
mA
*1, *3
60
230
μA
*1, *4
-
3.1
mA
*1, *4
50
210
μA
*1, *4
-
3.1
mA
*1, *4
35
200
μA
*1
-
3
mA
*1
30
160
μA
*1, *4
33
160
mA
*1, *4
-
600
μA
*1
-
610
mA
*1
20
150
μA
*1, *4
23
150
mA
*1, *4
-
600
μA
*1
-
610
mA
*1
*1 : When all ports are fixed.
*2 : VCC=5.5V
*3 : When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)
*4 : When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
48
CONFIDENTIAL
MB9A310K-DS706-00029-2v0-E, February 20, 2015
D a t a S h e e t
· Low-Voltage Detection Current
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Pin
name
Low-voltage
detection circuit
(LVD) power
supply current
ICCLVD
VCC
Conditions
At operation
for interrupt
Vcc = 5.5V
Value
Typ
Max
4
7
Unit
μA
Remarks
At not detect
· Flash Memory Current
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Parameter
Flash memory
write/erase
current
Symbol
ICCFLASH
Pin
name
Conditions
VCC
MainFlash
At Write/Erase
WorkFlash
At Write/Erase
Value
Typ
Max
Unit
11.4
13.1
mA
11.4
13.1
mA
Remarks
· A/D Converter Current
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, Ta = - 40°C to + 105°C)
Parameter
Power supply
current
Reference power
supply current
Symbol
ICCAD
ICCAVRH
Pin
name
AVCC
AVRH
February 20, 2015, MB9A310K-DS706-00029-2v0-E
CONFIDENTIAL
Value
Typ
Max
Unit
At 1unit
operation
0.57
0.72
mA
At stop
0.06
20
μA
At 1unit
operation
AVRH=5.5V
1.1
1.96
mA
At stop
0.06
4
μA
Conditions
Remarks
49
D a t a S h e e t
(2) Pin Characteristics
(Vcc = AVcc = 2.7V to 5.5V, Vss = AVss = 0V, Ta = - 40°C to + 105°C)
Parameter Symbol Pin name
"H" level
input
voltage
(hysteresis
input)
VIHS
"L" level
input
voltage
(hysteresis
input)
VILS
CMOS
hysteresis
input pin,
MD0, MD1
5V tolerant
input pin
CMOS
hysteresis
input pin,
MD0, MD1
5V tolerant
input pin
4mA
type
"H" level
output voltage
VOH
12mA
type
P80/P81
50
CONFIDENTIAL
Conditions
Value
Typ
Min
Max
Unit Remarks
-
Vcc × 0.8
-
Vcc + 0.3
V
-
Vcc × 0.8
-
Vss + 5.5
V
-
Vss - 0.3
-
Vcc × 0.2
V
-
Vss - 0.3
-
Vcc × 0.2
V
Vcc - 0.5
-
Vcc
V
Vcc - 0.5
-
Vcc
V
USBVcc 0.4
-
USBVcc
V
Vcc ≥ 4.5 V
IOH = - 4mA
Vcc < 4.5 V
IOH = - 2mA
Vcc ≥ 4.5 V
IOH = - 12mA
Vcc < 4.5 V
IOH = - 8mA
USBVcc ≥ 4.5 V
IOH = - 20.5 mA
USBVcc < 4.5 V
IOH = - 13.0 mA
MB9A310K-DS706-00029-2v0-E, February 20, 2015
D a t a S h e e t
Parameter
Symbol
Pin
name
4mA type
"L" level
output voltage
VOL
12mA type
P80/P81
Input leak
current
Pull-up
resistance
value
Input
capacitance
IIL
-
RPU
Pull-up pin
CIN
Other than
VCC,
USBVCC,
VSS,
AVCC,
AVSS,
AVRH
February 20, 2015, MB9A310K-DS706-00029-2v0-E
CONFIDENTIAL
Min
Value
Typ
Max
Vss
-
0.4
V
Vss
-
0.4
V
Vss
-
0.4
V
-
-5
-
+5
μA
Vcc ≥ 4.5 V
25
50
100
Vcc < 4.5 V
30
80
200
-
-
5
15
Conditions
Vcc ≥ 4.5 V
IOL = 4mA
Vcc < 4.5 V
IOL = 2mA
Vcc ≥ 4.5 V
IOL = 12mA
Vcc < 4.5 V
IOL = 8mA
USBVcc ≥ 4.5 V
IOL = 18.5mA
USBVcc< 4.5 V
IOL = 10.5mA
Unit Remarks
kΩ
pF
51
D a t a S h e e t
4.
AC Characteristics
(1) Main Clock Input Characteristics
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Pin
Conditions
name
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
PWH/tCYLH
PWL/tCYLH
Value
Min
Max
4
4
4
4
20.83
50
48
20
48
20
250
250
Unit
Remarks
When crystal oscillator
is connected
Input frequency
FCH
When using external
MHz
clock
X0
When using external
Input clock cycle
tCYLH
ns
X1
clock
Input clock pulse
When using external
45
55
%
width
clock
Input clock rise
tCF,
When using external
5
ns
time and fall time
tCR
clock
FCM
42
MHz Master clock
Base clock
FCC
42
MHz
(HCLK/FCLK)
Internal operating
clock frequency*1
FCP0
42
MHz APB0 bus clock*2
FCP1
42
MHz APB1 bus clock*2
FCP2
42
MHz APB2 bus clock*2
Base clock
tCYCC
23.8
ns
(HCLK/FCLK)
Internal operating
t
23.8
ns
APB0 bus clock*2
CYCP0
clock cycle time*1
tCYCP1
23.8
ns
APB1 bus clock*2
tCYCP2
23.8
ns
APB2 bus clock*2
*1 : For more information about each internal operating clock, see "CHAPTER 2-1: Clock" in "FM3 Family
PERIPHERAL MANUAL".
*2 : For about each APB bus which each peripheral is connected to, see " Block Diagram" in this data sheet.
MHz
X0
52
CONFIDENTIAL
MB9A310K-DS706-00029-2v0-E, February 20, 2015
D a t a S h e e t
(2) Sub Clock Input Characteristics
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Input frequency
Symbol
Min
Value
Typ
Max
-
-
32.768
-
kHz
-
32
-
100
kHz
Pin
Conditions
name
Unit
1/ tCYLL
X0A
X1A
Input clock cycle
tCYLL
-
10
-
31.25
μs
Input clock pulse
width
-
PWH/tCYLL
PWL/tCYLL
45
-
55
%
Remarks
When crystal
oscillator is
connected
When using
external clock
When using
external clock
When using
external clock
X0A
(3) Internal CR Oscillation Characteristics
 High-speed Internal CR
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Conditions
Ta = + 25°C
Clock frequency
FCRH
Ta =
0°C to + 70°C
Ta =
- 40°C to + 85°C
Ta =
- 40°C to + 85°C
Min
Value
Typ
Max
3.96
4
4.04
3.84
4
4.16
Unit
Remarks
When trimming*
MHz
3.8
4
4.2
3
4
5
When not trimming
Frequency
tCRWT
90
μs *2
stability time
*1 : In the case of using the values in CR trimming area of Flash memory at shipment for frequency trimming.
*2 : Frequency stable time is time to stable of the frequency of the High-speed CR.
clock after the trim value is set. After setting the trim value, the period when the frequency stability
time passes can use the High-speed CR clock as a source clock.
 Low-speed Internal CR
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Clock frequency
Symbol
Conditions
FCRL
-
February 20, 2015, MB9A310K-DS706-00029-2v0-E
CONFIDENTIAL
Min
Value
Typ
Max
50
100
150
Unit
Remarks
kHz
53
D a t a S h e e t
(4-1) Operating Conditions of Main and USB PLL (In the case of using main clock for input of PLL)
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Value
Min Typ Max
Unit
PLL oscillation stabilization wait time*
(LOCK UP time)
PLL input clock frequency
PLL multiple rate
PLL macro oscillation clock frequency
Main PLL clock frequency*2
tLOCK
100
-
FPLLI
FPLLO
FCLKPLL
4
13
200
-
-
16
MHz
75 multiple
300 MHz
40
MHz
USB clock frequency*3
FCLKSPLL
-
-
48
-
Remarks
μs
MHz
After the M frequency
division
*1 : Time from when the PLL starts operating until the oscillation stabilizes.
*2 : For more information about Main PLL clock (CLKPLL), see "CHAPTER 2-1: Clock" in "FM3 Family
PERIPHERAL MANUAL".
*3 : For more information about USB clock, see "CHAPTER 2-2: USB Clock Generation" in "FM3 Family
PERIPHERAL MANUAL Communication Macro Part".
(4-2) Operating Conditions of Main PLL (In the case of using high-speed internal CR)
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Value
Min Typ Max
Unit
Remarks
PLL oscillation stabilization wait time*
tLOCK
100
μs
(LOCK UP time)
PLL input clock frequency
FPLLI
3.8
4
4.2
MHz
PLL multiple rate
50
71 multiple
PLL macro oscillation clock frequency
FPLLO
190
300 MHz
Main PLL clock frequency*2
FCLKPLL
42
MHz
*1 : Time from when the PLL starts operating until the oscillation stabilizes.
*2 : For more information about Main PLL clock (CLKPLL), see "CHAPTER 2-1: Clock" in "FM3 Family
PERIPHERAL MANUAL".
When setting PLL multiple rate, please take the accuracy of the built-in high-speed CR clock into account
and prevent the master clock from exceeding the maximum frequency.
Main PLL connection
Main clock (CLKMO)
High-speed CR clock (CLKHC)
K
divider
PLL input
clock
Main
PLL
PLL macro
oscillation clock
M
divider
Main PLL
clock
(CLKPLL)
N
divider
USB PLL connection
Main clock (CLKMO)
K
divider
PLL input
clock
USB PLL
PLL macro
oscillation clock
M
divider
USB
clock
N
divider
54
CONFIDENTIAL
MB9A310K-DS706-00029-2v0-E, February 20, 2015
D a t a S h e e t
(5) Reset Input Characteristics
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Reset input time
tINITX
Value
Pin
Conditions
name
Min
Max
INITX
500
-
-
Unit Remarks
ns
(6) Power-on Reset Timing
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Power supply rising time
Power supply shut down time
Time until releasing
Power-on reset
Symbol
Pin
name
Value
Max
0
-
ms
1
-
ms
0.66
0.89
ms
Tr
Toff
VCC
Tprt
Unit
Min
Remarks
VCC_minimum
VCC
VDH_minimum
0.2V
0.2V
0.2V
Tr
Tprt
Internal RST
RST Active
CPU Operation
Toff
Release
start
Glossary
 VCC_minimum : Minimum VCC of recommended operating conditions
 VDH_minimum : Minimum release voltage of Low-Voltage detection reset.
See "10. Low-Voltage Detection Characteristics"
February 20, 2015, MB9A310K-DS706-00029-2v0-E
CONFIDENTIAL
55
D a t a S h e e t
(7) Base Timer Input Timing
 Timer input timing
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Input pulse width
Symbol
Pin name
Conditions
tTIWH
tTIWL
TIOAn/TIOBn
(when using as
ECK, TIN)
-
tTIWH
Value
Min
Max
2tCYCP
-
Unit Remarks
ns
tTIWL
ECK
TIN
VIHS
VIHS
VILS
VILS
 Trigger input timing
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Input pulse width
Symbol
Pin name
Conditions
tTRGH
tTRGL
TIOAn/TIOBn
(when using as
TGIN)
-
tTRGH
TGIN
VIHS
Value
Min
Max
2tCYCP
-
Unit Remarks
ns
tTRGL
VIHS
VILS
VILS
Note: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see "Block Diagram" in this data sheet.
56
CONFIDENTIAL
MB9A310K-DS706-00029-2v0-E, February 20, 2015
D a t a S h e e t
(8) CSIO/UART Timing
 CSIO (SPI = 0, SCINV = 0)
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Pin
Conditions
name
Serial clock cycle time
tSCYC
SCK ↓ → SOT delay time
tSLOVI
SIN → SCK ↑ setup time
tIVSHI
SCK ↑ → SIN hold time
tSHIXI
Serial clock "L" pulse width
tSLSH
SCKx
Serial clock "H" pulse width
tSHSL
SCKx
SCK ↓ → SOT delay time
tSLOVE
SIN → SCK ↑ setup time
tIVSHE
SCK ↑ → SIN hold time
tSHIXE
SCK fall time
SCK rise time
tF
tR
SCKx
SCKx
SOTx
SCKx Master mode
SINx
SCKx
SINx
SCKx
SOTx
SCKx
SINx
SCKx
SINx
SCKx
SCKx
Vcc < 4.5V
Min
Max
Vcc ≥ 4.5V
Min
Max
Unit
4tcycp
-
4tcycp
-
ns
-30
+30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
-
ns
-
ns
2tcycp 10
tcycp +
10
-
2tcycp 10
tcycp +
10
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Slave mode
Notes:  The above characteristics apply to CLK synchronous mode.
 tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see "Block
Diagram" in this data sheet.
 These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
 When the external load capacitance = 30 pF.
February 20, 2015, MB9A310K-DS706-00029-2v0-E
CONFIDENTIAL
57
D a t a S h e e t
tSCYC
VOH
SCK
VOL
VOL
tSLOVI
VOH
VOL
SOT
tIVSHI
SIN
tSHIXI
VIH
VIL
VIH
VIL
Master mode
tSLSH
SCK
VIH
tF
SOT
SIN
VIL
tSHSL
VIL
VIH
VIH
tR
tSLOVE
VOH
VOL
tIVSHE
VIH
VIL
tSHIXE
VIH
VIL
Slave mode
58
CONFIDENTIAL
MB9A310K-DS706-00029-2v0-E, February 20, 2015
D a t a S h e e t
 CSIO (SPI = 0, SCINV = 1)
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Pin
Conditions
name
Serial clock cycle time
tSCYC
SCK ↑ → SOT delay time
tSHOVI
SIN → SCK ↓ setup time
tIVSLI
SCK ↓ → SIN hold time
tSLIXI
Serial clock "L" pulse width
tSLSH
SCKx
Serial clock "H" pulse width
tSHSL
SCKx
SCK ↑ → SOT delay time
tSHOVE
SIN → SCK ↓ setup time
tIVSLE
SCK ↓ → SIN hold time
tSLIXE
SCK fall time
SCK rise time
tF
tR
SCKx
SCKx
SOTx
SCKx Master mode
SINx
SCKx
SINx
SCKx
SOTx
SCKx
SINx
SCKx
SINx
SCKx
SCKx
Vcc < 4.5V
Min
Max
Vcc ≥ 4.5V
Min
Max
Unit
4tcycp
-
4tcycp
-
ns
-30
+30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
-
ns
-
ns
2tcycp 10
tcycp +
10
-
2tcycp 10
tcycp +
10
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Slave mode
Notes:  The above characteristics apply to CLK synchronous mode.
 tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see "Block
Diagram" in this data sheet.
 These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
 When the external load capacitance = 30 pF.
February 20, 2015, MB9A310K-DS706-00029-2v0-E
CONFIDENTIAL
59
D a t a S h e e t
tSCYC
VOH
SCK
VOH
VOL
tSHOVI
VOH
VOL
SOT
tIVSLI
SIN
VIH
VIL
tSLIXI
VIH
VIL
Master mode
tSHSL
SCK
VIH
SIN
VIH
VIL
tR
SOT
tSLSH
VIL
VIL
tF
tSHOVE
VOH
VOL
tIVSLE
VIH
VIL
tSLIXE
VIH
VIL
Slave mode
60
CONFIDENTIAL
MB9A310K-DS706-00029-2v0-E, February 20, 2015
D a t a S h e e t
 CSIO (SPI = 1, SCINV = 0)
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Pin
Conditions
name
Serial clock cycle time
tSCYC
SCK ↑ → SOT delay time
tSHOVI
SIN → SCK ↓ setup time
tIVSLI
SCK ↓ → SIN hold time
tSLIXI
SOT → SCK ↓ delay time
tSOVLI
Serial clock "L" pulse width
tSLSH
SCKx
Serial clock "H" pulse width
tSHSL
SCKx
SCK ↑ → SOT delay time
tSHOVE
SIN → SCK ↓ setup time
tIVSLE
SCK ↓ → SIN hold time
tSLIXE
SCK fall time
SCK rise time
tF
tR
SCKx
SCKx
SOTx
SCKx
SINx Master mode
SCKx
SINx
SCKx
SOTx
SCKx
SOTx
SCKx
SINx
SCKx
SINx
SCKx
SCKx
Vcc < 4.5V
Min
Max
Vcc ≥ 4.5V
Min
Max
Unit
4tcycp
-
4tcycp
-
ns
-30
+30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
-
ns
-
ns
-
ns
2tcycp 30
2tcycp 10
tcycp +
10
-
2tcycp 30
2tcycp 10
tcycp +
10
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Slave mode
Notes:  The above characteristics apply to CLK synchronous mode.
 tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see "Block
Diagram" in this data sheet.
 These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
 When the external load capacitance = 30 pF.
February 20, 2015, MB9A310K-DS706-00029-2v0-E
CONFIDENTIAL
61
D a t a S h e e t
tSCYC
VOH
VOL
SCK
SOT
VOH
VOL
VOH
VOL
tIVSLI
tSLIXI
VIH
VIL
SIN
VOL
tSHOVI
tSOVLI
VIH
VIL
Master mode
tSLSH
SCK
VIH
tR
VIH
tSHOVE
VOH
VOL
VOH
VOL
tIVSLE
SIN
VIH
VIL
tF
*
SOT
VIL
tSHSL
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
* : Changes when writing to TDR register
62
CONFIDENTIAL
MB9A310K-DS706-00029-2v0-E, February 20, 2015
D a t a S h e e t
 CSIO (SPI = 1, SCINV = 1)
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Pin
Conditions
name
Vcc < 4.5V
Min
Max
Vcc ≥ 4.5V
Min
Max
Unit
Serial clock cycle time
tSCYC
SCKx
4tcycp
-
4tcycp
-
ns
SCK ↓ → SOT delay time
tSLOVI
SCKx
SOTx
-30
+30
- 20
+ 20
ns
SIN → SCK ↑ setup time
tIVSHI
50
-
30
-
ns
SCK ↑ → SIN hold time
tSHIXI
0
-
0
-
ns
SOT → SCK ↑ delay time
tSOVHI
-
ns
Serial clock "L" pulse width
tSLSH
SCKx
-
ns
Serial clock "H" pulse width
tSHSL
SCKx
-
ns
SCK ↓→ SOT delay time
tSLOVE
SIN → SCK ↑ setup time
tIVSHE
SCK ↑ → SIN hold time
tSHIXE
SCK fall time
SCK rise time
tF
tR
SCKx
SINx Master mode
SCKx
SINx
SCKx
SOTx
SCKx
SOTx
SCKx
SINx
SCKx
SINx
SCKx
SCKx
2tcycp 30
2tcycp 10
tcycp +
10
-
2tcycp 30
2tcycp 10
tcycp +
10
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Slave mode
Notes:  The above characteristics apply to CLK synchronous mode.
 tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see "Block
Diagram" in this data sheet.
 These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
 When the external load capacitance = 30 pF.
February 20, 2015, MB9A310K-DS706-00029-2v0-E
CONFIDENTIAL
63
D a t a S h e e t
tSCYC
VOH
SCK
VOH
VOL
tSOVHI
tSLOVI
VOH
VOL
SOT
VOH
VOL
tSHIXI
tIVSHI
VIH
VIL
SIN
VIH
VIL
Master mode
tSHSL
tR
SCK
VIL
tSLSH
VIH
VIH
tF
VIL
VIL
VIH
tSLOVE
SOT
VOH
VOL
VOH
VOL
tIVSHE
tSHIXE
VIH
VIL
SIN
VIH
VIL
Slave mode
 UART external clock (EXT = 1)
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol Conditions
Serial clock "L" pulse width
Serial clock "H" pulse width
SCK fall time
SCK rise time
tSLSH
tSHSL
tF
tR
CL = 30 pF
tR
SCK
VIL
64
CONFIDENTIAL
Min
Max
tcycp + 10
tcycp + 10
-
5
5
tSHSL
VIH
VIL
ns
ns
ns
ns
tF
tSLSH
VIH
Unit Remarks
VIL
VIH
MB9A310K-DS706-00029-2v0-E, February 20, 2015
D a t a S h e e t
(9) External Input Timing
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Pin name
Conditions
Value
Unit
Min
Max
ADTG
FRCKx
Input pulse width
tINH,
tINL
-
2tCYCP*1
-
2tCYCP*1
-
ns
-
ns
ICxx
DTTIxX
1
INTxx
NMIX
*2
*3
2tCYCP + 100*
500
-
ns
ns
WKUPx
-*4
820
-
ns
Remarks
A/D converter
trigger input
Free-run timer input
clock
Input capture
Wave form
generator
External interrupt
NMI
Deep stand-by wake
up
*1 : tCYCP indicates the APB bus clock cycle time.
About the APB bus number which A/D converter, Multi-function Timer, External interrupt are connected to,
see "Block Diagram" in this data sheet.
*2 : When in run mode, in sleep mode.
*3 : When in stop mode, in rtc mode, in timer mode.
*4 : When in deep stand-by stop mode, in deep stand-by rtc mode.
February 20, 2015, MB9A310K-DS706-00029-2v0-E
CONFIDENTIAL
65
D a t a S h e e t
(10) Quadrature Position/Revolution Counter timing
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Value
Conditions
Min
Max
Unit
AIN pin "H" width
tAHL
AIN pin "L" width
tALL
BIN pin "H" width
tBHL
BIN pin "L" width
tBLL
BIN rise time from
PC_Mode2 or
tAUBU
AIN pin "H" level
PC_Mode3
AIN fall time from
PC_Mode2 or
tBUAD
BIN pin "H" level
PC_Mode3
BIN fall time from
PC_Mode2 or
tADBD
AIN pin "L" level
PC_Mode3
AIN rise time from
PC_Mode2 or
tBDAU
BIN pin "L" level
PC_Mode3
AIN rise time from
PC_Mode2 or
2tCYCP*
ns
tBUAU
BIN pin "H" level
PC_Mode3
BIN fall time from
PC_Mode2 or
tAUBD
AIN pin "H" level
PC_Mode3
AIN fall time from
PC_Mode2 or
tBDAD
BIN pin "L" level
PC_Mode3
BIN rise time from
PC_Mode2 or
tADBU
AIN pin "L" level
PC_Mode3
ZIN pin "H" width
tZHL
QCR:CGSC="0"
ZIN pin "L" width
tZLL
QCR:CGSC="0"
AIN/BIN rise and fall time
tZABE
QCR:CGSC="1"
from determined ZIN level
Determined ZIN level from
tABEZ
QCR:CGSC="1"
AIN/BIN rise and fall time
* : tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Quadrature Position/Revolution Counter is connected to, see "Block
Diagram" in this data sheet.
tALL
tAHL
AIN
tAUBU
tADBD
tBUAD
tBDAU
BIN
tBHL
66
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tBLL
MB9A310K-DS706-00029-2v0-E, February 20, 2015
D a t a S h e e t
tBLL
tBHL
BIN
tBUAU
tBDAD
tAUBD
tADBU
AIN
tAHL
tALL
ZIN
ZIN
AIN/BIN
February 20, 2015, MB9A310K-DS706-00029-2v0-E
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D a t a S h e e t
2
(11) I C Timing
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol Conditions
Standard-mode Fast-mode
Unit Remarks
Min
Max
Min Max
SCL clock frequency
FSCL
0
100
0
400 kHz
(Repeated) START condition
hold time
tHDSTA
4.0
0.6
μs
SDA ↓→ SCL ↓
SCLclock "L" width
tLOW
4.7
1.3
μs
SCLclock "H" width
tHIGH
4.0
0.6
μs
(Repeated) START setup time
tSUSTA
4.7
0.6
μs
SCL ↑→ SDA ↓
CL = 30pF,
Data hold time
1
tHDDAT R = (Vp/IOL)*
0
3.45*2
0
0.9*3 μs
SCL ↓→ SDA ↓ ↑
Data setup time
tSUDAT
250
100
ns
SDA ↓ ↑ → SCL ↑
STOP condition setup time
tSUSTO
4.0
0.6
μs
SCL ↑→ SDA ↑
Bus free time between
"STOP condition" and
tBUF
4.7
1.3
μs
"START condition"
Noise filter
tSP
2 tCYCP*4
2 tCYCP*4 ns
*1 : R and C represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively.
Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
*2 : The maximum tHDDAT must satisfy that it doesn't extend at least "L" period (tLOW) of device's SCL signal.
*3 : Fast-mode I2C bus device can be used on Standard-mode I2C bus system as long as the device satisfies the
requirement of "tSUDAT ≥ 250 ns".
*4 : tCYCP is the APB bus clock cycle time.
About the APB bus number that I2C is connected to, see "Block Diagram" in this data sheet.
To use Standard-mode, set the APB bus clock at 2 MHz or more.
To use Fast-mode, set the APB bus clock at 8 MHz or more.
SDA
SCL
68
CONFIDENTIAL
MB9A310K-DS706-00029-2v0-E, February 20, 2015
D a t a S h e e t
(12) JTAG Timing
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol Pin name
Conditions
TCK,
TMS, TDI
TCK,
TMS, TDI
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
TMS, TDI setup
time
tJTAGS
TMS, TDI hold time
tJTAGH
TDO delay time
tJTAGD
TCK,
TDO
Vcc < 4.5V
Value
Min
Max
Unit
15
-
ns
15
-
ns
-
25
-
45
Remarks
ns
Note: When the external load capacitance = 30 pF.
TCK
TMS/TDI
TDO
February 20, 2015, MB9A310K-DS706-00029-2v0-E
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69
D a t a S h e e t
5.
12-bit A/D Converter
 Electrical characteristics for the A/D converter
(Vcc = AVcc = 2.7V to 5.5V, Vss = AVss = 0V, Ta = - 40°C to + 105°C)
Parameter
Resolution
Integral nonlinearity
Differential nonlinearity
Zero transition voltage
Full-scale transition
voltage
Conversion time
Sampling time
Pin
Symbol
name
VZT
VFST
Ts
Min
ANxx
- 4.5
-2.5
- 20
AVRH ANxx
20
1.0*1
1.2*1
*2
*2
Value
Typ
-
Max
12
+ 4.5
+ 2.5
+ 20
Unit
Remarks
bit
LSB
LSB
mV AVRH = 2.7V to 5.5V
AVRH + 20 mV
-
-
μs
ns
Compare clock cycle*3
Tcck
-
50
-
2000
ns
State transition time to
operation permission
Tstt
-
-
-
1.0
μs
Analog input capacity
CAIN
-
-
-
12.9
pF
Analog input resistance
RAIN
-
-
-
2
3.8
4
kΩ
AVcc ≥ 4.5V
AVcc < 4.5V
AVcc ≥ 4.5V
AVcc < 4.5V
AVcc ≥ 4.5V
AVcc < 4.5V
Interchannel disparity
LSB
Analog port input
ANxx
5
μA
current
Analog input voltage
ANxx AVSS
AVRH
V
Reference voltage
AVRH
2.7
AVCC
V
*1 : Conversion time is the value of sampling time (Ts) + compare time (Tc).
The condition of the minimum conversion time is the following.
AVcc ≥ 4.5V, HCLK=40 MHz sampling time: 300 ns, compare time: 700 ns
AVcc < 4.5V, HCLK=40 MHz sampling time: 500 ns, compare time: 700 ns
Ensure that it satisfies the value of sampling time (Ts) and compare clock cycle (Tcck).
For setting*4 of sampling time and compare clock cycle, see "CHAPTER 1-1:A/D Converter" in "FM3
Famliy PERIPHERAL MANUAL Analog Macro Part".
The A/D Converter register is set at APB bus clock timing. The sampling clock and compare clock are set at
Base clock (HCLK).
About the APB bus number which the A/D Converter is connected to, see "Block Diagram" in this data
sheet.
*2 : A necessary sampling time changes by external impedance.
Ensure that it set the sampling time to satisfy (Equation 1).
*3 : Compare time (Tc) is the value of (Equation 2).
70
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MB9A310K-DS706-00029-2v0-E, February 20, 2015
D a t a S h e e t
Rext
ANxx
Analog input pin
Analog
signal source
Comparator
RAIN
CAIN
(Equation 1) Ts ≥ ( RAIN + Rext ) × CAIN × 9
Ts : Sampling time
RAIN : input resistance of A/D = 2kΩ at 4.5 < AVCC < 5.5
input resistance of A/D = 3.8kΩ at 2.7 < AVCC < 4.5
CAIN : input capacity of A/D = 12.9pF at 2.7 < AVCC < 5.5
Rext : Output impedance of external circuit
(Equation 2) Tc = Tcck × 14
Tc : Compare time
Tcck : Compare clock cycle
February 20, 2015, MB9A310K-DS706-00029-2v0-E
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D a t a S h e e t
 Definition of 12-bit A/D Converter Terms
 Resolution
 Integral nonlinearity
 Differential nonlinearity
: Analog variation that is recognized by an A/D converter.
: Deviation of the line between the zero-transition point
(0b000000000000←→0b000000000001) and the full-scale transition point
(0b111111111110←→0b111111111111) from the actual conversion
characteristics.
: Deviation from the ideal value of the input voltage that is required to change
the output code by 1 LSB.
Integral nonlinearity
Differential nonlinearity
0xFFF
Actual conversion
characteristics
0xFFE
Actual conversion
characteristics
0x(N+1)
{1 LSB(N-1) + VZT}
VFST
VNT
0x004
(Actuallymeasured
value)
(Actually-measured
value)
0x003
Digital output
Digital output
0xFFD
0xN
Ideal characteristics
V(N+1)T
0x(N-1)
(Actually-measured
value)
Actual conversion
characteristics
Ideal characteristics
0x002
VNT
(Actually-measured
value)
0x(N-2)
0x001
VZT (Actually-measured value)
AVss
Actual conversion characteristics
AVRH
AVss
Analog input
Integral nonlinearity of digital output N =
Differential nonlinearity of digital output N =
1LSB =
N
VZT
VFST
VNT
72
CONFIDENTIAL
:
:
:
:
AVRH
Analog input
VNT - {1LSB × (N - 1) + VZT}
1LSB
V(N + 1) T - VNT
1LSB
[LSB]
- 1 [LSB]
VFST - VZT
4094
A/D converter digital output value.
Voltage at which the digital output changes from 0x000 to 0x001.
Voltage at which the digital output changes from 0xFFE to 0xFFF.
Voltage at which the digital output changes from 0x(N − 1) to 0xN.
MB9A310K-DS706-00029-2v0-E, February 20, 2015
D a t a S h e e t
6.
USB Characteristics
(Vcc = 2.7V to 5.5V, USBVcc = 3.0V to 3.6V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Input "H" level voltage
Input "L" level voltage
Input
charact- Differential input
eristics sensitivity
Different common mode
input voltage
Pin
Conditions
name
Min
Value
Max
Unit Remarks
VIH
-
2.0
VIL
-
Vss - 0.3
USBVcc + 0.3 V
0.8
V
*1
*1
VDI
-
0.2
-
V
*2
VCM
-
0.8
2.5
V
*2
Minimum differential input
sensitivity [V]
External
pull-down
Output "H" level voltage
VOH
2.8
3.6
V *3
resistance
= 15kΩ
UDP0, External
UDM0
pull-up
Output "L" level voltage
VOL
0.0
0.3
V *3
resistance
Output
= 1.5kΩ
charact- Crossover voltage
VCRS
1.3
2.0
V *4
erstics
Rise time
tFR
Full-Speed
4
20
ns *5
Fall time
tFF
Full-Speed
4
20
ns *5
Rise/ fall time matching
tFRFM
Full-Speed
90
111.11
% *5
Output impedance
ZDRV
Full-Speed
28
44
Ω *6
Rise time
tLR
Low-Speed
75
300
ns *7
Fall time
tLF
Low-Speed
75
300
ns *7
Rise/ fall time matching
tLRFM
Low-Speed
80
125
% *7
*1 : The switching threshold voltage of Single-End-Receiver of USB I/O buffer is set as within V IL (Max) = 0.8V,
VIH (Min) = 2.0 V (TTL input standard).
There are some hysteresis to lower noise sensitivity.
*2 : Use differential-Receiver to receive USB differential data signal.
Differential-Receiver has 200 mV of differential input sensitivity when the differential data input is within
0.8 V to 2.5 V to the local ground reference level.
Above voltage range is the common mode input voltage range.
Common mode input voltage [V]
February 20, 2015, MB9A310K-DS706-00029-2v0-E
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73
D a t a S h e e t
*3 : The output drive capability of the driver is below 0.3 V at Low-State (VOL) (to 3.6 V and 1.5 kΩ load), and
2.8 V or above (to the VSS and 1.5 kΩ load) at High-State (VOH).
*4 : The cross voltage of the external differential output signal (D + /D − ) of USB I/O buffer is within 1.3 V to
2.0 V.
VCRS specified range
*5 : They indicate rise time (Trise) and fall time (Tfall) of the full-speed differential data signal.
They are defined by the time between 10% and 90% of the output signal voltage.
For full-speed buffer, Tr/Tf ratio is regulated as within ± 10% to minimize RFI emission.
Rising time
74
CONFIDENTIAL
Falling time
MB9A310K-DS706-00029-2v0-E, February 20, 2015
D a t a S h e e t
*6 : USB Full-speed connection is performed via twist pair cable shield with 90Ω ± 15% characteristic
impedance (Differential Mode).
USB standard defines that output impedance of USB driver must be in range from 28Ω to 44Ω. So, discrete
series resistor (Rs) addition is defined in order to satisfy the above definition and keep balance.
When using this USB I/O, use it with 25Ω to 30Ω (recommendation value 27Ω) Series resistor Rs.
28Ω to 44Ω Equiv. Imped.
28Ω to 44Ω Equiv. Imped.
Mount it as external resistance.
Rs series resistor 25Ω to 30Ω
Series resistor of 27Ω (recommendation value) must be added.
And, use "resistance with an uncertainty of 5% by E24 sequence".
*7 : They indicate rise time (Trise) and fall time (Tfall) of the low-speed differential data signal.
They are defined by the time between 10% and 90% of the output signal voltage.
Rising time
Falling time
See Figure " Low-Speed Load (Compliance Load)" for conditions of external load.
February 20, 2015, MB9A310K-DS706-00029-2v0-E
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75
D a t a S h e e t
 Low-Speed Load (Upstream Port Load) - Reference 1
CL = 50pF to 150pF
CL = 50pF to 150pF
 Low-Speed Load (Downstream Port Load) - Reference 2
CL =200pF to
600pF
CL =200pF to
600pF
 Low-Speed Load (Compliance Load)
CL = 200pF to 450pF
CL = 200pF to 450pF
76
CONFIDENTIAL
MB9A310K-DS706-00029-2v0-E, February 20, 2015
D a t a S h e e t
7.
Low-voltage Detection Characteristics
(1) Low-voltage Detection Reset
(Ta = - 40°C to + 105°C)
Parameter
Detected voltage
Released voltage
Symbol Conditions
VDL
VDH
-
Min
Value
Typ
Max
2.25
2.30
2.45
2.50
2.65
2.70
Unit
V
V
Remarks
When voltage drops
When voltage rises
(2) Interrupt of Low-voltage Detection
(Ta = - 40°C to + 105°C)
Parameter
Symbol Conditions
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
LVD stabilization
wait time
TLVDW
SVHI = 0000
SVHI = 0001
SVHI = 0010
SVHI = 0011
SVHI = 0100
SVHI = 0111
SVHI = 1000
SVHI = 1001
-
Min
Value
Typ
Max
2.58
2.67
2.76
2.85
2.94
3.04
3.31
3.40
3.40
3.50
3.68
3.77
3.77
3.86
3.86
3.96
2.8
2.9
3.0
3.1
3.2
3.3
3.6
3.7
3.7
3.8
4.0
4.1
4.1
4.2
4.2
4.3
3.02
3.13
3.24
3.34
3.45
3.56
3.88
3.99
3.99
4.10
4.32
4.42
4.42
4.53
4.53
4.64
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
-
-
2240 ×
tcycp*
μs
Unit
Remarks
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
* : tCYCP indicates the APB2 bus clock cycle time.
February 20, 2015, MB9A310K-DS706-00029-2v0-E
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D a t a S h e e t
8.
MainFlash Memory Write/Erase Characteristics
(1) Write / Erase time
(Vcc = 2.7V to 5.5V, Ta = - 40°C to + 105°C)
Value
Parameter
Sector erase
time
Large Sector
Typ*
Max*
0.7
3.7
Unit
Includes write time prior to internal
erase
s
Small Sector
Half word (16-bit)
write time
0.3
Remarks
1.1
Not including system-level overhead
time
Includes write time prior to internal
Chip erase time
3.8
16.2
s
erase
* : The typical value is immediately after shipment, the maximam value is guarantee value under 100,000
cycle of erase/write.
12
384
μs
(2) Erase/write cycles and data hold time
Erase/write cycles (cycle)
Data hold time (year)
1,000
20*
10,000
100,000
10*
5*
* : At average + 85C
9.
WorkFlash Memory Write/Erase Characteristics
(1) Write / Erase time
(Vcc = 2.7V to 5.5V, Ta = - 40°C to + 105°C)
Value
Parameter
Typ*
Max*
Sector erase time
0.3
1.5
Half word (16-bit)
write time
20
Unit
s
Remarks
Includes write time prior to internal
erase
Not including system-level overhead
time
Includes write time prior to internal
Chip erase time
1.2
6
s
erase
* : The typical value is immediately after shipment, the maximam value is guarantee value under 10,000 cycle
of erase/write.
384
μs
(2) Erase/write cycles and data hold time
Erase/write cycles (cycle)
Data hold time (year)
1,000
20*
10,000
10*
* : At average + 85C
78
CONFIDENTIAL
MB9A310K-DS706-00029-2v0-E, February 20, 2015
D a t a S h e e t
10. Return Time from Low-Power Consumption Mode
(1) Return Factor: Interrupt/WKUP
The return time from Low-Power consumption mode is indicated as follows. It is from receiving the
return factor to starting the program operation.
 Return Count Time
(VCC = 2.7V to 5.5V, Ta = - 40°C to + 105°C)
Parameter
Symbol
SLEEP mode
High-speed CR TIMER mode,
Main TIMER mode,
PLL TIMER mode
Value
Typ
Max*
tCYCC
Unit
ns
40
80
μs
370
740
μs
Sub TIMER mode
699
929
μs
STOP mode
505
834
μs
Low-speed CR TIMER mode
Ticnt
Remarks
* : The maximum value depends on the accuracy of built-in CR.
 Operation example of return from Low-Power consumption mode (by external interrupt*)
Ext.INT
Interrupt factor
accept
Active
Ticnt
CPU
Operation
Interrupt factor
clear by CPU
Start
* : External interrupt is set to detecting fall edge.
February 20, 2015, MB9A310K-DS706-00029-2v0-E
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D a t a S h e e t
 Operation example of return from Low-Power consumption mode (by internal resource
interrupt*)
Internal
Resource INT
Interrupt factor
accept
Active
Ticnt
CPU
Operation
Interrupt factor
clear by CPU
Start
* : Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode.
Notes:
80
CONFIDENTIAL
 The return factor is different in each Low-Power consumption modes.
See "CHAPTER 6: Low Power Consumption Mode" and "Operations of Standby
Modes" in FM3 Family PERIPHERAL MANUAL about the return factor from
Low-Power consumption mode.
 When interrupt recoveries, the operation mode that CPU recoveries depends on the
state before the Low-Power consumption mode transition. See "CHAPTER 6: Low
Power Consumption Mode" in "FM3 Family PERIPHERAL MANUAL".
MB9A310K-DS706-00029-2v0-E, February 20, 2015
D a t a S h e e t
(2) Return Factor: Reset
The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to
starting the program operation.
 Return Count Time
(VCC = 2.7V to 5.5V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Value
Unit
Typ
Max*
365
554
μs
365
554
μs
555
934
μs
Sub TIMER mode
608
976
μs
STOP mode
475
774
μs
SLEEP mode
High-speed CR TIMER mode,
Main TIMER mode,
PLL TIMER mode
Low-speed CR TIMER mode
Trcnt
Remarks
* : The maximum value depends on the accuracy of built-in CR.
 Operation example of return from Low-Power consumption mode (by INITX)
INITX
Internal RST
RST Active
Release
Trcnt
CPU
Operation
February 20, 2015, MB9A310K-DS706-00029-2v0-E
CONFIDENTIAL
Start
81
D a t a S h e e t
 Operation example of return from low power consumption mode (by internal resource reset*)
Internal
Resource RST
Internal RST
RST Active
Release
Trcnt
CPU
Operation
* : Internal resource reset
Notes:
82
CONFIDENTIAL
Start
is not included in return factor by the kind of Low-Power consumption mode.
 The return factor is different in each Low-Power consumption modes.
See "CHAPTER 6: Low Power Consumption Mode" and "Operations of Standby Modes" in FM3
Family PERIPHERAL MANUAL.
 When interrupt recoveries, the operation mode that CPU recoveries depends on the
state before the Low-Power consumption mode transition. See "CHAPTER 6: Low
Power Consumption Mode" in "FM3 Family PERIPHERAL MANUAL".
・ The time during the power-on reset/low-voltage detection reset is excluded. See "(6)
Power-on Reset Timing in 4. AC Characteristics in ■Electrical Characteristics" for
the detailon the time during the power-on reset/low -voltage detection reset.
・ When in recovery from reset, CPU changes to the high-speed CR run mode. When
using the main clock or the PLL clock, it is necessary to add the main clock
oscillation stabilization wait time or the main PLL clock stabilization wait time.
 The internal resource reset means the watchdog reset and the CSV reset.
MB9A310K-DS706-00029-2v0-E, February 20, 2015
D a t a S h e e t
 Ordering Information
Part number
MB9AF311KPMC-G-JNE2
MB9AF312KPMC-G-JNE2
MB9AF311KPMC1-G-JNE2
MB9AF312KPMC1-G-JNE2
MB9AF311KQN-G-AVE2
MB9AF312KQN-G-AVE2
On-chip
Flash
memory
Main: 64 Kbyte
Work: 32 Kbyte
Main: 128 Kbyte
Work: 32 Kbyte
Main: 64 Kbyte
Work: 32 Kbyte
Main: 128 Kbyte
Work: 32 Kbyte
Main: 64 Kbyte
Work: 32 Kbyte
Main: 128 Kbyte
Work: 32 Kbyte
February 20, 2015, MB9A310K-DS706-00029-2v0-E
CONFIDENTIAL
On-chip
SRAM
16 Kbyte
16 Kbyte
16 Kbyte
16 Kbyte
16 Kbyte
16 Kbyte
Package
Packing
Plastic  LQFP
48-pin (0.5mm pitch),
(FPT-48P-M49)
Plastic  LQFP
52-pin (0.65mm pitch),
(FPT-52P-M02)
Tray
Plastic  QFN
48-pin (0.5mm pitch),
(LCC-48P-M73)
83
D a t a S h e e t
 Package Dimensions
48-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
7.00 mm × 7.00 mm
Lead shape
Gullwing
Lead bend
direction
Normal bend
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.17 g
(FPT-48P-M49)
48-pin plastic LQFP
(FPT-48P-M49)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
9.00 ± 0.20(.354 ± .008)SQ
*7.00± 0.10(.276 ± .004)SQ
36
0.145± 0.055
(.006 ± .002)
25
37
24
0.08(.003)
48
13
"A"
1
C
CONFIDENTIAL
0°~8°
0.10 ± 0.10
(.004 ± .004)
(Stand off)
12
0.22 ± 0.05
(.008 ± .002)
0.08(.003)
2010 FUJITSU SEMICONDUCTOR LIMITED HMbF48-49Sc-1-2
84
+0.20
1.50 –0.10 (Mounting height)
+.008
.059 –.004
INDEX
0.50(.020)
Details of "A" part
0.25(.010)
M
0.60 ± 0.15
(.024 ± .006)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
MB9A310K-DS706-00029-2v0-E, February 20, 2015
D a t a S h e e t
48-pin plastic QFN
Lead pitch
0.5 mm
Package width×
package length
7.00 mm × 7.00 mm
Sealing method
Plastic mold
Mounting height
0.90 mm MAX
Weight
–
(LCC-48P-M73)
48-pin plastic QFN
(LCC-48P-M73)
7.00±0.10
(.276±.004)
5.50±0.10
(.217±.004)
7.00±0.10
(.276±.004)
0.25±0.05
(.010±.002)
5.50±0.10
(.217±.004)
INDEX AREA
0.45 (.018)
1PIN ID
(0.20R (.008R))
0.85±0.05
(.033±.002)
0.05 (.002) MAX
C
0.40±0.05
(.016±.002)
(0.20(.008))
2011 FUJITSU SEMICONDUCTOR LIMITED HMbC48-73Sc-2-1
February 20, 2015, MB9A310K-DS706-00029-2v0-E
CONFIDENTIAL
0.50 (.020)
(TYP)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
85
D a t a S h e e t
52-pin plastic LQFP
Lead pitch
0.65 mm
Package width ×
package length
10.00 × 10.00 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.32 g
Code
(Reference)
P-LFQFP52-10×10-0.65
(FPT-52P-M02)
52-pin plastic LQFP
(FPT-52P-M02)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
12.00± 0.20(.472 ±. 008)SQ
*10.00± 0.10(.394 ±. 004)SQ
39
0.145± 0.055
(.006 ±. 002)
27
40
Details of "A" part
26
+0.20
1.50 –0.10
+.008 (Mounting height)
.059 –.004
0.25(.010)
INDEX
0.10(.004)
52
14
"A"
1
13
0.65(.026)
C
2010 FUJITSU SEMICONDUCTOR LIMITED F52002Sc-2-1
86
CONFIDENTIAL
0~8˚
+0.065
0.30 –0.035
+.0026
.012 –.0014
0.13(.005)
M
0.50 ± 0.20
(.020 ±. 008)
0.10 ± 0.10
(.004 ±. 004)
(Stand off)
0.60 ± 0.15
(.024 ±. 006)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
MB9A310K-DS706-00029-2v0-E, February 20, 2015
D a t a S h e e t
 Major Changes
Page
Section
Revision 1.0
PRODUCT LINEUP
7
 Function
PACKAGES
8
I/O CIRCUIT TYPE
23
BLOCK DIAGRAM
34
ELECTRICAL CHARACTERISTICS
3. DC Characteristics
(1) Current Rating
45, 46
(9) External Input Timing
5. 12-bit A/D Converter
66
 Electrical characteristics for the A/D
converter
8. MainFlash Memory Write/Erase
Characteristics
Erase/write cycles and data hold time
74
9. WorkFlash Memory Write/Erase
Characteristics
Erase/write cycles and data hold time
Revision 1.1
Revision 2.0
Features
2
USB Interface
25
I/O Circuit Type
25, 26
I/O Circuit Type
32
Handling Devices
Handling Devices
32
Crystal oscillator circuit
Handling Devices
33
C Pin
35
Block Diagram
Memory Map
36
· Memory map(1)
Memory Map
37
· Memory map(2)
61
44, 45
46
47-49
52
53
54
Electrical Characteristics
1. Absolute Maximum Ratings
Electrical Characteristics
2. Recommended Operation Conditions
Electrical Characteristics
3. DC Characteristics
(1) Current rating
Electrical Characteristics
4. AC Characteristics
(1) Main Clock Input Characteristics
Electrical Characteristics
4. AC Characteristics
(3) Built-in CR Oscillation Characteristics
Electrical Characteristics
4. AC Characteristics
(4-1) Operating Conditions of Main and
USB PLL
(4-2) Operating Conditions of Main PLL
February 20, 2015, MB9A310K-DS706-00029-2v0-E
CONFIDENTIAL
Change Results
PRELIMINARY → Data sheet
Added the pin count.
Revised from "Planning".
Corrected the following description to "TypeB".
Digital output → Digital input
Corrected the following description.
 AHB (Max 40MHz) → AHB (Max 42MHz)
 APB0 (Max 40MHz) → APB0 (Max 42MHz)
 APB1 (Max 40MHz) → APB1 (Max 42MHz)
 APB2 (Max 40MHz) → APB2 (Max 42MHz)
 Revised the value of "TBD".
 Corrected the value.
- "Power supply current (ICCR)"
Typ: 60 → 50
- "Power supply current (ICCRD)" (RAM hold off)
Typ: 45 → 30
- "Power supply current (ICCRD)" (RAM hold on)
Typ: 48 → 33
Revised the value of "TBD".
 Deleted"(Preliminary value)".
 Corrected the value of "Compare clock cycle".
Max: 10000 → 2000
Deleted"(targeted value)".
Company name and layout design change
Added the description of PLL for USB
Added the description of I2C to the type of E and F
Added about +B input
Added "Stabilizing power supply voltage"
Added the following description
"Evaluate oscillation of your using crystal oscillator by your mount board."
Changed the description
Modified the block diagram
Modified the area of "Extarnal Device Area"
Added the summary of Flash memory sector and the note
· Added the Clamp maximum current
· Added the output current of P80 and P81
· Added about +B input
· Modified the minimum value of Analog reference voltage
· Added Smoothing capacitor
· Added the note about less than the minimum power supply voltage
· Changed the table format
· Added Main TIMER mode current
· Added Flash Memory Current
· Moved A/D Converter Current
Added Master clock at Ingernal operating clock frequency
Added Frequency stability time at Built-in high-speed CR
· Added Main PLL clock frequency
· Added USB clock frequency
· Added the figure of Main PLL connection and USB PLL connection
87
D a t a S h e e t
Page
55
57-64
70
79-82
83
88
CONFIDENTIAL
Section
Electrical Characteristics
4. AC Characteristics
(6) Power-on Reset Timing
Electrical Characteristics
4. AC Characteristics
(7) CSIO/UART Timing
Electrical Characteristics
5. 12bit A/D Converter
Electrical Characteristics
9. Return Time from Low-Power
Consumption Mode
Ordering Information
Change Results
· Added Time until releasing Power-on reset
· Changed the figure of timing
· Modified from UART Timing to CSIO/UART Timing
· Changed from Internal shift clock operation to Master mode
· Changed from External shift clock operation to Slave mode
· Added the typical value of Integral Nonlinearity, Differential Nonlinearity,
Zero transition voltage and Full-scale transition voltage
· Added Conversion time at AVcc < 4.5V
· Modified Stage transition time to operation permission
· Modified the minimum value of Reference voltage
Added Return Time from Low-Power Consumption Mode
Changed the description of part number
MB9A310K-DS706-00029-2v0-E, February 20, 2015
D a t a S h e e t
February 20, 2015, MB9A310K-DS706-00029-2v0-E
CONFIDENTIAL
89
D a t a S h e e t
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use,
including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not
designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless
extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury,
severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use
where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not
be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the
products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss
from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire
protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in
this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and
Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the
prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a
Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any
product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to
its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party
rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind
arising out of the use of the information in this document.
Copyright © 2012-2015 Spansion All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® EclipseTM,
ORNANDTM, Easy DesignSimTM, TraveoTM and combinations thereof, are trademarks and registered trademarks of
Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be
trademarks of their respective owners.
90
CONFIDENTIAL
MB9A310K-DS706-00029-2v0-E, February 20, 2015