FemtoClock® Crystal-to-HCSL Clock Generator ICS841664I DATA SHEET General Description Features The ICS841664I is an optimized sRIO clock generator and a member of the family of high-performance clock solutions from IDT. The device uses a 25MHz parallel crystal to generate 125MHz and 156.25MHz clock signals, replacing solution requiring multiple oscillator and fanout buffer solutions. The device has excellent phase jitter (< 1ps rms) suitable to clock components requiring precise and low-jitter sRIO clock signals. Designed for telecom, networking and industrial application, the ICS841664I can also drive the high-speed sRIO SerDes clock inputs of communication processors, DSPs, switches and bridges. • Four differential HCSL clock outputs: configurable for sRIO (125MHz or 156.25MHz) clock signals One REF_OUT LVCMOS/LVTTL clock output • Selectable crystal oscillator interface, 25MHz, 18pF parallel resonant crystal or LVCMOS/LVTTL single-ended reference clock input or LVCMOS/LVTTL single-ended input • • • • Supports the following output frequencies: 125MHz or 156.25MHz • • • Full 3.3V power supply mode VCO: 625MHz Supports PLL bypass and output enable functions RMS phase jitter, using a 25MHz crystal (1.875MHz - 20MHz): 0.45ps (typical) @ 125MHz -40°C to 85°C ambient operating temperature Available in lead-free (RoHS 6) package Pin Assignment Block Diagram XTAL_IN 25MHz XTAL_OUT OSC fref REF_IN Pulldown REF_SEL Pulldown 1 QA0 1 0 FemtoClock PLL nQA0 0 ÷NA VCO = 625MHz QA1 nQA1 M = ÷25 QB0 IREF nQB0 ÷NB BYPASS Pulldown QB1 FSEL[0:1] Pulldown nQB1 MR/nOE Pulldown REF_OUT nREF_OE VDD REF_OUT GND QA0 nQA0 V DDOA GND QA1 nQA1 nREF_OE BYPASS REF_IN REF_ SEL VDDA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 IREF FSEL0 FSEL1 QB0 nQB0 V DDOB GND QB1 nQB1 MR/nOE V DD XTAL _IN XTAL_OUT GND ICS841664I 28-Lead TSSOP 6.1mm x 9.7mm x 0.925mm package body G Package Top View Pullup ICS841664AGI REVISION A AUGUST 10, 2011 1 ©2011 Integrated Device Technology, Inc. FEMTOCLOCK® CRYSTAL-TO-HCSL CLOCK GENERATOR ICS841664I Data Sheet Table 1. Pin Descriptions Number Name Type Description 1, 18 VDD Power Core supply pins. 2 REF_OUT Output LVCMOS/LVTTL reference frequency clock output. 3, 7, 15, 22 GND Power Power supply ground. 4, 5, 8, 9 QA0, nQA0 QA1, nQA1 Output Differential Bank A output pairs. HCSL interface levels. 6 VDDOA Power Output supply pin for Bank A outputs. 10 nREF_OE Input Pullup 11 BYPASS Input Pulldown Selects PLL/PLL bypass mode. See Table 3C. LVCMOS/LVTTL interface levels. 12 REF_IN Input Pulldown LVCMOS/LVTTL reference clock input. 13 REF_SEL Input Pulldown Reference select, Selects the input reference source. See Table 3B. LVCMOS/LVTTL interface levels 14 VDDA Power Analog supply pin. 16,17 XTAL_OUT, XTAL_IN Input Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input. Active HIGH master reset. Active LOW output enable. When logic HIGH, the internal dividers are reset and the outputs are in high impedance (HiZ). When logic LOW, the internal dividers and the outputs are enabled. See Table 3D. LVCMOS/LVTTL interface levels. Pulldown Active low REF_OUT enable/disable. See Table 3E. LVCMOS/LVTTL interface levels. 19 MR/nOE Input 20, 21, 24, 25 nQB0, QB0 nQB1, QB1 Output Differential Bank B output pairs. HCSL interface levels. 23 VDDOB Power Output supply pin for Bank B outputs. 26, 27 FSEL1, FSEL0 Input 28 IREF Output Pulldown Output frequency select pins. LVCMOS/LVTTL interface levels. HCSL current reference resistor output. A fixed precision resistor (475Ω) form this pin to ground provides a reference current used for differential current-mode QXx/nQXx clock outputs. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance CPD Power Dissipat ion Capacitance RPULLUP Test Conditions Minimum Typical Maximum Units 4 pF 4 pF Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ ROUT Output Impedance 20 Ω VDD = 3.465V REF_OUT ICS841664AGI REVISION A AUGUST 10, 2011 VDD = 3.465V 2 ©2011 Integrated Device Technology, Inc. FEMTOCLOCK® CRYSTAL-TO-HCSL CLOCK GENERATOR ICS841664I Data Sheet Function Tables Table 3A. NA, NB FSELx Function Table (fref = 25MHz) Inputs Outputs Frequency Settings FSEL1 FSEL0 M QA0:1/nQA0:1 QB0:1/nQB0:1 0 0 25 VCO/5 (125MHz) VCO/5 (125MHz) 0 1 25 VCO/5 (125MHz) VCO/4 (156.25MHz) 1 0 25 VCO/5 (125MHz) QB0:1 = L, nQB0:1 = H 1 1 25 VCO/4 (156.25MHz) VCO/4 (156.25MHz) Table 3B. REF_SEL Function Table Input REF_SEL Input Reference 0 XTAL 1 REF_IN Table 3C. BYPASS Function Table Input BYPASS PLL Configuration NOTE 1 0 PLL enabled 1 PLL bypassed (QA, QB = fref/Nx, x = A or B) NOTE 1: Asynchronous control. Table 3D. MR/nOE Function Table Input MR/nOE Function NOTE 1 0 Outputs enabled 1 Internal dividers reset, outputs disabled (High impedance) NOTE 1: Asynchronous control. Table 3E. nREF_OE Function Table Input nREF_OE Function NOTE 1 0 REF_OUT enabled 1 REF_OUT disabled (high impedance) NOTE 1: Asynchronous control. ICS841664AGI REVISION A AUGUST 10, 2011 3 ©2011 Integrated Device Technology, Inc. FEMTOCLOCK® CRYSTAL-TO-HCSL CLOCK GENERATOR ICS841664I Data Sheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI XTAL_IN Other Inputs 0V to VDD -0.5V to VDD + 0.5V Outputs,IO Continuous Current REF_OUT Surge Current REF_OUT +/- 15mA +/- 30mA Package Thermal Impedance, θJA 64.5°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = VDDOA = VDDOB = 3.3V±5%, TA = -40°C to 85°C Symbol Parameter VDD Core Supply Voltage VDDA Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V Analog Supply Voltage VDD – 0.20 3.3 3.465 V VDDOA, VDDOB Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current No Load 80 mA IDDA Analog Supply Current No Load 20 mA IDDOA, IDDOB Output Supply Current No Load, RREF = 475Ω +/− 1% 5 mA Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V±5%, TA = -40°C to 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH IIL Input High Current Input Low Current Test Conditions Minimum Typical Maximum Units 2 VDD + 0.3 V -0.3 0.8 V REF_IN, REF_SEL, BYPASS, MR/nOE, FSEL0, FSEL1 VDD = VIN = 3.465V 150 µA nREF_OE VDD = VIN = 3.465V 5 µA REF_IN, REF_SEL, BYPASS, MR/nOE, FSEL0, FSEL1 VDD = 3.465V, VIN = 0V -5 µA nREF_OE VDD = 3.465V, VIN = 0V -150 µA 2.6 V VOH Output High Voltage; NOTE 1 REF_OUT VDD = 3.465V VOL Output Low Voltage; NOTE 1 REF_OUT VDD = 3.465V 0.5 V NOTE 1: Outputs termination with 50Ω to VDD /2. See Parameter Measurement Information Section, Output Load Test Circuit diagram. ICS841664AGI REVISION A AUGUST 10, 2011 4 ©2011 Integrated Device Technology, Inc. FEMTOCLOCK® CRYSTAL-TO-HCSL CLOCK GENERATOR ICS841664I Data Sheet Table 5. Crystal Characteristics Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental Frequency 25 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF NOTE: Characterized using an 18pF parallel resonant crystal. AC Electrical Characteristics Table 6A. LVCMOS AC Characteristics, VDD = 3.3V±5%, TA = -40°C to 85°C Symbol Parameter fOUT Output Frequency REF_OUT tR / tF Output Rise/Fall Time odc Output Duty Cycle ICS841664AGI REVISION A AUGUST 10, 2011 Test Conditions Minimum Typical Maximum 25 20% to 80% 5 Units MHz 1.5 2.2 ns 47 53 % ©2011 Integrated Device Technology, Inc. FEMTOCLOCK® CRYSTAL-TO-HCSL CLOCK GENERATOR ICS841664I Data Sheet Table 6B. HCSL AC Characteristics, VDD = VDDOA = VDDOB = 3.3V±5%, TA = -40°C to 85°C Symbol Parameter fOUT Output Frequency tjit(Ø) Test Conditions RMS Phase Jitter (Random); NOTE 1 Minimum Typical Maximum VCO/5 125 MHz VCO/4 156.25 MHz 125MHz, Integration Range: 1.875MHz - 20MHz 0.45 0.55 ps 156.25MHz, Integration Range: 1.875MHz - 20MHz 0.41 0.54 ps 60 ps 140 ps 100 ms 950 mV 150 mV tjit(cc) Cycle-to-Cycle Jitter; NOTE 3 tsk(o) Output Skew; NOTE 2, 3 tL PLL Lock Time VHIGH Voltage High 650 VLOW Voltage Low -150 VOVS Max. Voltage, Overshoot VUDS Min. Voltage, Undershoot VRB Ringback Voltage VCROSS Absolute Crossing Voltage ∆VCROSS Total Variation of VCROSS over all edges tR / tF Output Rise/Fall Time ∆ tR / ∆ tF Rise/Fall Time Variation odc Output Duty Cycle QAx/nQAx, QBx/nQBx 700 0.3 -0.3 QAx/nQAx, QBx/nQBx Units 200 measured between 0.175V to 0.525V QAx/nQAx, QBx/nQBx 100 47 V V 0.2 V 550 mV 160 mV 700 ps 125 ps 53 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: All measurements are taken at 125MHz and 156.25MHz. NOTE 1: Please refer to the Phase Noise Plot. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. ICS841664AGI REVISION A AUGUST 10, 2011 6 ©2011 Integrated Device Technology, Inc. FEMTOCLOCK® CRYSTAL-TO-HCSL CLOCK GENERATOR ICS841664I Data Sheet Typical Phase Noise at 125MHz At 3.3V Noise Power dBc Hz 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.45ps typical) Offset Frequency (Hz) Typical Phase Noise at 156.25MHz At 3.3V Noise Power dBc Hz 156.25MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.41ps typical Offset Frequency (Hz) ICS841664AGI REVISION A AUGUST 10, 2011 7 ©2011 Integrated Device Technology, Inc. FEMTOCLOCK® CRYSTAL-TO-HCSL CLOCK GENERATOR ICS841664I Data Sheet Parameter Measurement Information 3.3V±5% 3.3V±5% 3.3V±5% 3.3V±5% SCOPE VDD, VDDOA VDDOB VDDA 50Ω VDD, VDDOA VDDOB VDDA 50Ω Qx 2pF 50Ω 33Ω IREF Measurement Point nQx GND GND Measurement Point 49.9Ω HCSL IREF 49.9Ω 475Ω 0V 50Ω 33Ω 2pF 475Ω 0V 0V 3.3V HCSL Output Load AC Test Circuit 3.3V HCSL Output Load AC Test Circuit 1.65V±5% Phase Noise Plot Noise Power 1.65V±5% SCOPE VDD VDDA Qx LVCMOS GND f1 Offset Frequency f2 RMS Jitter = Area Under Curve Defined by the Offset Frequency Markers -1.65V±5% 3.3V LVCMOS Output Load AC Test Circuit RMS Phase Jitter nQA[0:1], nQB[0:1] nQx QA[0:1], QB[0:1] Qx ➤ t cycle n ➤ t cycle n+1 nQy ➤ ➤ t jit(cc) = |t cycle n – t cycle n+1| 1000 Cycles Qy t sk(o) Cycle-to-Cycle Jitter ICS841664AGI REVISION A AUGUST 10, 2011 HCSL Output Skew 8 ©2011 Integrated Device Technology, Inc. FEMTOCLOCK® CRYSTAL-TO-HCSL CLOCK GENERATOR ICS841664I Data Sheet Parameter Measurement Information, continued V V DD 80% 80% REF_OUT tR 2 Qx t PW 20% 20% REF_OUT DD 2 t PERIOD tF t PW odc = nQx x 100% t PERIOD LVCMOS Output Duty Cycle/Pulse Width/Period LVCMOS Output Rise/Fall Time Clock Period (Differential) nQAx, nQBx 0.525V Positive Duty Cycle (Differential) 0.525V Negative Duty Cycle (Differential) VSW I N G QAx, QBx 0.175V 0.175V tR 0.0V tF Q - nQ Differential Measurement Points For Duty Cycle/Period Differential Measurement Points For Rise/Fall Time TSTABLE VRB nQ +150mV VRB = +100mV 0.0V VRB = -100mV -150mV ∆VCROSS_Delta= 140mV Q Q - nQ VRB TSTABLE SE Measurement Points For Delta Cross Point ICS841664AGI REVISION A AUGUST 10, 2011 Differential Measurement Points For Ringback 9 ©2011 Integrated Device Technology, Inc. FEMTOCLOCK® CRYSTAL-TO-HCSL CLOCK GENERATOR ICS841664I Data Sheet Parameter Measurement Information, continued VMAX nQ VCROSS_MAX VCROSS_MIN Q VMIN = -0.30V SE Measurement Points For Absolute Cross Point/Swing Applications Information Recommendations for Unused Input and Output Pins Inputs: Outputs: Crystal Inputs HCSL Outputs All unused HCSL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from XTAL_IN to ground. LVCMOS Outputs All unused LVCMOS outputs can be left floating. There should be no trace attached. REF_CLK Input For applications not requiring the use of the reference clock, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the REF_CLK to ground. LVCMOS Control Pins All control pins have internal pullups and pulldowns; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. ICS841664AGI REVISION A AUGUST 10, 2011 10 ©2011 Integrated Device Technology, Inc. FEMTOCLOCK® CRYSTAL-TO-HCSL CLOCK GENERATOR ICS841664I Data Sheet Applications Information, continued Schematic Layout Figure 1 shows an example of ICS841664I application schematic. In this example, the device is operated at VDD = VDDA = VDDOA = VDDOB = 3.3V. The 18pF parallel resonant 25MHz crystal is used. The load capacitance C1 = 27pF and C2 = 27pF are recommended for frequency accuracy. Depending on the parasitic of the printed circuit board layout, these values might require a slight adjustment to optimize the frequency accuracy. Crystals with other load capacitance specifications can be used. This will require adjusting C1 and C2. For this device, the crystal load capacitors are required for proper operation. As with any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS841664I provides separate power supplies to isolate any high switching noise from coupling into the internal PLL. R1 Zo = 50 33 RE F_OU T Logic Control Input Examples LVC MOS Set Logic Input to '1' VD D Set Logic Input to '0' VD D RD 2 1K 1 2 3 4 5 6 7 8 9 10 11 12 13 14 VD D O nR EF_OE BY PA SS REF _I N R EF_SEL VD D Q1 Ro ~ 7 Ohm R 12 Zo = 50 R4 I REF FSEL0 FSEL1 QB0 nQB0 VD D OB GN D QB1 nQB1 MR /nOE VD D XTAL_I N XTAL_OU T GN D VDD REF _OU T GN D QA0 nQA0 VDD OA GN D QA1 nQA1 nR EF_OE BYP ASS REF _I N REF _SE L VDD A 28 27 26 25 24 23 22 21 20 19 18 17 16 15 FS EL0 FS EL1 + 33 nQB0 ToLogic Input pins RD 1 Not I ns t all 33 QB 0 U1 V DD To Logic Input pins R3 R2 475 RU 2 Not I ns t all RU 1 1K Zo = 50 R5 50 VD D O - R6 50 Recommended for PCI Express Add-In Card QB1 nQB 1 MR/ nOE VDD=3.3V VDD VDDOA=3.3V HCSL Termination VDDOB=3.3V Zo = 50 Ohm 43 Optional Driv er_LVC MOS R8 0-33 Zo = 50 + R7 V DD 10 VD D A R9 0-33 Zo = 50 X1 C3 C4 10u C1 27pF - 25MH z 1 8p F 0.1u HCSL Optional Termination C2 27pF R10 50 R11 50 Recommended for PCI Express Point-to-Point Connection 3. 3V 3. 3V B LM18BB221S N1 BLM18BB221SN 2 1 1 (U1:6) 2 F errit e Bead Ferrit e Bead C9 0.1uF C 10 C11 10uF (U1:1) (U1:18) C7 C8 VD D 2 (U1:23) VD D O C 12 0. 1uF C5 0. 1uF C6 10uF 0. 1uF 0.1uF 0.1uF Figure 1. ICS841664I Schematic Example In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB as close to the power pins as possible. If space is limited, the 0.1µF capacitor in each power pin filter should be placed on the device side of the PCB and the other components can be placed on the opposite side. Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter performance is designed for wide range of noise frequency. This low-pass filter starts to attenuate noise at approximately 10 kHz. If a ICS841664AGI REVISION A AUGUST 10, 2011 specific frequency noise component with high amplitude interference is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally general design practice for power plane voltage stability suggests adding bulk capacitances in the general area of all devices. The schematic example focuses on functional connections and is not configuration specific. Refer to the pin description and functional tables in the datasheet to ensure the logic control inputs are properly set. 11 ©2011 Integrated Device Technology, Inc. FEMTOCLOCK® CRYSTAL-TO-HCSL CLOCK GENERATOR ICS841664I Data Sheet Applications Information, continued Overdriving the XTAL Interface The XTAL_IN input can be overdriven by an LVCMOS driver or by one side of a differential driver through an AC coupling capacitor. The XTAL_OUT pin can be left floating. The amplitude of the input signal should be between 500mV and 1.8V and the slew rate should not be less than 0.2V/nS. For 3.3V LVCMOS inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. Figure 2A shows an example of the interface diagram for a high speed 3.3V LVCMOS driver. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This VCC can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and changing R2 to 50Ω. The values of the resistors can be increased to reduce the loading for a slower and weaker LVCMOS driver. Figure 2B shows an example of the interface diagram for an LVPECL driver. This is a standard LVPECL termination with one side of the driver feeding the XTAL_IN input. It is recommended that all components in the schematics be placed in the layout. Though some components might not be used, they can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. XTAL_OUT R1 100 Ro Rs C1 Zo = 50 ohms XTAL_IN R2 100 Zo = Ro + Rs .1uf LVCMOS Driver Figure 2A. General Diagram for LVCMOS Driver to XTAL Input Interface XTAL_OUT C2 Zo = 50 ohms XTAL_IN .1uf Zo = 50 ohms LVPECL Driver R1 50 R2 50 R3 50 Figure 2B. General Diagram for LVPECL Driver to XTAL Input Interface ICS841664AGI REVISION A AUGUST 10, 2011 12 ©2011 Integrated Device Technology, Inc. FEMTOCLOCK® CRYSTAL-TO-HCSL CLOCK GENERATOR ICS841664I Data Sheet Applications Information, continued Recommended Termination Figure 3A is the recommended source termination for applications where the driver and receiver will be on a separate PCBs. This termination is the standard for PCI Express™ and HCSL output 0.5" Max Rs 22 to 33 +/-5% types. All traces should be 50Ω impedance single-ended or 100Ω differential. 1-14" 0-0.2" 0.5 - 3.5" L1 L2 L4 L5 L1 L2 L4 L5 PCI Expres s PCI Express Connector Driver 0-0.2" L3 PCI Express L3 Add-in Card 49.9 +/- 5% Rt Figure 3A. Recommended Source Termination (where the driver and receiver will be on separate PCBs) Figure 3B is the recommended termination for applications where a point-to-point connection can be used. A point-to-point connection contains both the driver and the receiver on the same PCB. With a matched termination at the receiver, transmission-line reflections will 0.5" Max Rs 0 to 33 L1 be minimized. In addition, a series resistor (Rs) at the driver offers flexibility and can help dampen unwanted reflections. The optional resistor can range from 0Ω to 33Ω. All traces should be 50Ω impedance single-ended or 100Ω differential. 0-18" 0-0.2" L2 L3 L2 L3 0 to 33 L1 PCI Express Driver Rt 49.9 +/- 5% Figure 3B. Recommended Termination (where a point-to-point connection can be used) ICS841664AGI REVISION A AUGUST 10, 2011 13 ©2011 Integrated Device Technology, Inc. FEMTOCLOCK® CRYSTAL-TO-HCSL CLOCK GENERATOR ICS841664I Data Sheet Power Considerations This section provides information on power dissipation and junction temperature for the ICS841664I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS841664I is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. Core and HCSL Output Power Dissipation • Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (80mA + 20mA) = 346.5mW • Power (outputs)MAX = 44.5mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 44.5mW = 178mW LVCMOS Driver Power Dissipation • Dynamic Power Dissipation at 25MHz Power (25MHz) = CPD * Frequency * (VDD)2 = 4pF * 25MHz * (3.465V)2 = 1.20mW per output Total Power Dissipation • Total Power = Power (core) + Power (Outputs) + Total Power (25MHz) = 346.5mW + 178mW + 1.2mW = 525.7mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 64.5°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.526W * 64.3°C/W = 118.9°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 7. Thermal Resistance θJA for 28 Lead TSSOP, Forced Convection θJA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards ICS841664AGI REVISION A AUGUST 10, 2011 0 1 2.5 64.5°C/W 60.4°C/W 58.5°C/W 14 ©2011 Integrated Device Technology, Inc. FEMTOCLOCK® CRYSTAL-TO-HCSL CLOCK GENERATOR ICS841664I Data Sheet 3. Calculations and Equations. The purpose of this section is to calculate power dissipation on the IC per HCSL output pair. HCSL output driver circuit and termination are shown in Figure 4. VDD IOUT = 17mA ➤ VOUT RREF = 475Ω ± 1% RL 50Ω IC Figure 4. HCSL Driver Circuit and Termination HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power dissipation, use the following equations which assume a 50Ω load to ground. The highest power dissipation occurs when VDD_MAX. Power = (VDD_MAX – VOUT) * IOUT since VOUT = IOUT * RL Power = (VDD_MAX – IOUT * RL) * IOUT = (3.465V – 17mA * 50Ω) * 17mA Total Power Dissipation per output pair = 44.5mW ICS841664AGI REVISION A AUGUST 10, 2011 15 ©2011 Integrated Device Technology, Inc. FEMTOCLOCK® CRYSTAL-TO-HCSL CLOCK GENERATOR ICS841664I Data Sheet Reliability Information Table 8. θJA vs. Air Flow Table for a 28 Lead TSSOP θJA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 64.5°C/W 60.4°C/W 58.5°C/W Transistor Count The transistor count for ICS841664I is: 2954 ICS841664AGI REVISION A AUGUST 10, 2011 16 ©2011 Integrated Device Technology, Inc. FEMTOCLOCK® CRYSTAL-TO-HCSL CLOCK GENERATOR ICS841664I Data Sheet Package Outline and Package Dimensions Package Outline - G Suffix for 28 Lead TSSOP Table 9. Package Dimensions All Dimensions in Millimeters Symbol Minimum Maximum N 28 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 9.60 9.80 E 8.10 Basic E1 6.00 6.20 e 0.65 Basic L 0.45 0.75 α 0° 8° aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 ICS841664AGI REVISION A AUGUST 10, 2011 17 ©2011 Integrated Device Technology, Inc. FEMTOCLOCK® CRYSTAL-TO-HCSL CLOCK GENERATOR ICS841664I Data Sheet Ordering Information Table 10. Ordering Information Part/Order Number 841664AGILF 841664AGILFT Marking ICS841664AGI ICS841664AGI Package 28 Lead “Lead-Free” TSSOP 28 Lead “Lead-Free” TSSOP Shipping Packaging Tube 2500 Tape & Reel Temperature -40°C to 85°C -40°C to 85°C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS841664AGI REVISION A AUGUST 10, 2011 18 ©2011 Integrated Device Technology, Inc. FEMTOCLOCK® CRYSTAL-TO-HCSL CLOCK GENERATOR ICS841664I Data Sheet We’ve Got Your Timing Solution 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support [email protected] +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. 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Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2011. All rights reserved.