A p p l i c a t io n N o t e , V 2 . 2 . 1 , J u ly 2 0 0 3 AP24001 OCDS Level 1 JTAG Connector 16-Bit & 32-Bit Microcontrollers A I M ic r o c o n t r o l l e r s N e v e r s t o p t h i n k i n g . OCDS Level 1 JTAG Connector Revision History: 2003-07 V2.2.1 Previous Version:V2.2.0 Page Subjects (major changes since last revision) Changes and corrections to the technical content and document layout and design. Adapted to reflect current signal naming conventions. Table footnotes added. V2.1 was an intermediate version. pg3/5 Added Connector manufacturer example (section 2.2) and confirmed which signals are Pull-up (section 3.1) Controller Area Network (CAN): License of Robert Bosch GmbH We Listen to Your Comments Is there any information in this document that you feel is wrong, unclear or missing? Your feedback will help us to continuously improve the quality of our documentation. Please send your comments (including a reference to this document) to: [email protected] AP24001 OCDS Level1 JTAG Connector Introduction 1 Introduction This document describes the Infineon Technologies JTAG Connector for the C166CBC, C166S V1, C166S V2 and TriCore cores. Since there is no standard connector defined in the JTAG standard (IEEE1149.1) specification, nor an established industry standard, we are defining, for debug purposes, our own standard. 2 The Connector Layout 2.1 Slow and Fast Signals, Shielding Since the connector will be used together with a flat ribbon cable, the pins on the left and right side of the connector will alter within the flat ribbon cable. Slow signals and GND are on the right side and fast signals are on the left side. This gives some shielding. The key pin should be forced down by the debugger side to GND. 2.2 Mechanical The connector (Pin Header) is a standard 2.54 mm (0.1 inch) centres and 10mm pins. An example manufacturer is Molex (www.molex.com) C-Grid III, 8w Dual Row (Molex part number 90131-0764. These can also be ordered from RS). TMS 1 2 VDD TDO 3 4 GND CPU_CLOCK 5 6 GND TDI 7 8 RESET TRST 9 10 BRKOUT TCK 11 12 GND BRKIN 13 14 OCDSE RCAP1 15 16 RCAP2 Figure 1 Connector Layout Application Note 3 V2.2.1, 2003-07 AP24001 OCDS Level1 JTAG Connector The Connector Layout 2.3 Signal Description The following are the Infineon JTAG connector signals. Note that directions are indicated as follows: • O = output from the CPU processor board to the debugger. • I = input to the CPU processor board from the debugger. Table 1 Signal Descriptions Signal Name Direction Pin TDO O 3 Comment IEEE 1149.1 TDI I 7 IEEE 1149.1 TMS I 1 IEEE 1149.1 TCK I 11 IEEE 1149.1 TRST I 9 IEEE 1149.1 BRKIN I 13 Break Input & OCDS configuration BRKOUT O 10 RESET I 8 Open drain, TriCore: PORST (Power On Reset) CPU_CLOCK O 5 Optional 15 Reserved for customer application purposes 14 TriCore, OCDS configuration RCAP1 OCDSE1) I GND 4,6,12 VDD 2 I/O ring voltage of CPU RCAP2 16 Reserved for customer application purposes 1) This signal is not available on each Microcontroller implementation. This signal must be forced to a low level from the Trace Hardware (Emulator). If the Microcontroller derivative has no corresponding signal, it should be left unconnected in the target hardware. 2.4 Voltage All Signals have the voltage of the I/O ring. Current Microcontroller implementations have 5 V, 3.3 V or 2.5 V VDD on I/O ring. The VDD I/O ring should be provided from the target based board to the active buffers at the cable level (if present). Application Note 4 V2.2.1, 2003-07 AP24001 OCDS Level1 JTAG Connector Implementation Considerations 3 Implementation Considerations 3.1 Pull-Ups On the CPU board the following signals should each be connected to pull-ups of 10 kΩ respectively. • • • • • • • OCDS TMS TCK TDI TRST RESET BRKIN 3.2 Clock Pin The clock is optional since not every CPU has a Clock-out pin available. Since the clock pin could be a very good antenna it should be connected via any sort of Jumper. If not implemented it should be GND so that it can be sensed if there is clock or not. 3.3 RCAP1 and RCAP2 Pins These pins are reserved for customer application purposes. 3.4 OCDSE and BRKIN Pins These pins are used during power on reset (POR reset pin) to setup the OCDS system (TriCore only) Application Note 5 V2.2.1, 2003-07 AP24001 OCDS Level1 JTAG Connector Low Cost EVA Board Connector 4 Low Cost EVA Board Connector The Infineon StarterKit boards are equipped with a low cost DB25 printer port connector. The JTAG Signals are mapped to the following Printer-Port signals. It is not recommended to use a DB25 connector in customer applications since the onboardwiggler would eat up additional board space & power. Table 2 LPT Pin Connector Signals LPT Signal Type JTAG/Board Signals 16-pin JTAG Connector 1 Strobe O 14 Auto feed O VPP User 2 D0 O TDI 15 Error I 10 kΩ pullup to 5 Volt 3 D1 O TMS 1 16 Init O 11 Optional: 12 V for external User. FLASH programming 7 4 D2 O TCK 17 Select O VPP Mon Optional: 12 V for external Mon. FLASH programming. 5 D3 O TRST 9 18 GND SH GND 4,6,12 6 D4 O BRKIN 13 19 GND SH GND 4,6,12 7 D5 O RESET 8 20 GND SH GND 4,6,12 1) 8 D6 O 21 GND SH GND 9 D7 O NMI 22 GND SH GND OCDSE TriCore: PORST (Power On Reset) 14 4,6,12 Optional 4,6,12 10 Ack I BRKOUT 10 23 GND SH GND 4,6,12 Application Note Comment 6 V2.2.1, 2003-07 AP24001 OCDS Level1 JTAG Connector Low Cost EVA Board Connector Table 2 LPT Pin Connector Signals LPT Signal Type JTAG/Board Signals 11 Busy I 10 kΩ pulldown to GND 24 GND SH GND 4,6,12 12 Paper empty I TDO 3 25 GND SH GND 4,6,12 Select O IRQ pending 13 1) 16-pin JTAG Connector Comment Optional This signal is not available on each Microcontroller implementation. This signal must be forced to a low level from the Trace Hardware (Emulator). If the Microcontroller derivative has no corresponding signal, it should be left unconnected in the target hardware. Application Note 7 V2.2.1, 2003-07 AP24001 OCDS Level1 JTAG Connector Onboard Wiggler 5 Onboard Wiggler The Infineon Technologies StarterKit boards are equipped with Onboard Wigglers. The Onboard Wiggler protects the microcontroller from voltage peaks and operates as a level shifter if needed. Please note that the above Wiggler describes a stand-alone version. On the StarterKit board the right side of the Wiggler would be connected with the chip. 10k LED 470 10k 10k 10k 10k 10k 10k 10k 0.01 10k 10k 82 (Schottky) 82 1 2 3 4 13 25 0 Vcc1 1 51 a1 b1 a2 b2 5 TMS 6 TDO VCC 2 GND 51 3 a3 b3 a4 b4 a5 b5 a6 b6 b7 a7 b8 a8 a9 b9 7 5 6 82 7 8 82 9 10 82 11 12 82 13 14 15 16 RESET# GND 10k 4 1 1 8 TDI 2 TRST# 2 TCLK 5 BRK_IN# GND 1 2 3 14 6 BRK_OUT# 7 OCDS_E# 82 Wiremount Socket 1 110 4 a10 8 0 2x SN74HC244N DB25-F Figure 2 b10 GND 0.01µ Wiggler Circuit Diagram Application Note 8 V2.2.1, 2003-07 Infineon goes for Business Excellence “Business excellence means intelligent approaches and clearly defined processes, which are both constantly under review and ultimately lead to good operating results. Better operating results and business excellence mean less idleness and wastefulness for all of us, more professional success, more accurate information, a better overview and, thereby, less frustration and more satisfaction.” Dr. Ulrich Schumacher http://www.infineon.com Published by Infineon Technologies AG