A3988 Datasheet

A3988
Quad DMOS Full Bridge PWM Motor Driver
FEATURES AND BENEFITS
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DESCRIPTION
36 V output rating
4 full bridges
Dual stepper motor driver
High current outputs
3.3 and 5 V compatible logic supply
Synchronous rectification
Internal undervoltage lockout (UVLO)
Thermal shutdown circuitry
Crossover-current protection
Low profile QFN package
The A3988 is a quad DMOS full-bridge driver capable of driving
up to two stepper motors or four DC motors. Each full-bridge
output is rated up to 1.2 A and 36 V. The A3988 includes fixed
off-time pulse width modulation (PWM) current regulators,
along with 2- bit nonlinear DACs (digital-to-analog converters)
that allow stepper motors to be controlled in full, half, and
quarter steps, and DC motors in forward, reverse, and coast
modes. The PWM current regulator uses the Allegro™ patented
mixed decay mode for reduced audible motor noise, increased
step accuracy, and reduced power dissipation.
Internal synchronous rectification control circuitry is provided
to improve power dissipation during PWM operation.
Packages
Protection features include thermal shutdown with hysteresis,
undervoltage lockout (UVLO) and crossover current protection.
Special power up sequencing is not required.
Package EV, 36 pin QFN
0.90 mm nominal height
with exposed thermal pad
The A3988 is supplied in two packages, EV and JP, with exposed
power tabs for enhanced thermal performance. The EV is a
6 mm x 6 mm, 36 pin QFN package with a nominal overall
package height of 0.90 mm. The JP is a 7 mm × 7 mm 48 pin
LQFP. Both packages are lead (Pb) free, with 100% matte tin
leadframe plating.
Approximate scale
Package JP, 48 pin LQFP
with exposed thermal pad
Microprocessor
I12
PHASE3
I03
I13
PHASE4
I04
I14
VREF1
VREF
VREF2
VREF3
VREF4
VDD 3.3 V
VDD
A3988
OUT2A
OUT2B
OUT3A
Bipolar Stepper Motors
OUT3B
OUT4A
OUT4B
SENSE2
SENSE1
SENSE3
SENSE4
Typical Application Circuit
A3988DS, Rev. 10
0.22 µF
50 V
OUT1B
I11
I02
100 µF
50 V
OUT1A
I01
PHASE2
VMOTOR 32 V
VBB2
VCP
CP2
CP1
PHASE1
VBB1
0.1 µF
50 V
0.1 µF
50 V
RS2
RS1
RS3
RS4
A3988
Quad DMOS Full Bridge PWM Motor Driver
Selection Guide
Part Number
Package
Packing
A3988SEV-T
36 pin QFN with exposed thermal pad
61 pieces per tube
A3988SEVTR-T
36 pin QFN with exposed thermal pad
1500 pieces per reel
A3988SJPTR-T
48 pin LQFP with exposed thermal pad
1500 pieces per reel
SPECIFICATIONS
Absolute Maximum Ratings
Characteristic
Symbol
Load Supply Voltage
VBB
Logic Supply Voltage
VDD
Output Current
IOUT
Logic Input Voltage Range
VIN
Notes
Pulsed tw < 1 µs
May be limited by duty cycle, ambient temperature, and heat sinking. Under
any set of conditions, do not exceed the specified current rating or a Junction
Temperature of 150°C.
Pulsed tw < 1 µs
SENSEx Pin Voltage
VSENSEx
Pulsed tw < 1 µs
VREFx Pin Voltage
Operating Temperature Range
Junction Temperature
Storage Temperature Range
VREFx
Rating
Units
-0.5 to 36
V
38
V
–0.4 to 7
V
1.2
A
2.8
A
–0.3 to 7
V
0.5
V
2.5
V
2.5
V
–20 to 85
ºC
TJ(max)
150
ºC
Tstg
–40 to 125
ºC
TA
Range S
Thermal Characteristics (may require derating at maximum conditions)
Characteristic
Symbol
Package Thermal Resistance
RθJA
Test Conditions
Min.
Units
EV package, 4 layer PCB based on JEDEC standard
27
ºC/W
JP package, 4 layer PCB based on JEDEC standard
23
ºC/W
Power Dissipation versus Ambient Temperature
5500
5000
JP Package
4-layer PCB
(RθJA = 23 ºC/W)
4500
Power Dissipation, PD (mW)
4000
3500
3000
2500
2000
1500
EV Package
4-layer PCB
(RθJA = 27 ºC/W)
1000
500
0
25
50
75
100
125
Temperature (°C)
150
175
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
A3988
Quad DMOS Full Bridge PWM Motor Driver
0.1 µF
50 V
0.1 µF
50 V
0.22 µF
50 V
VBB1
VCP
CP2
CP1
100 µF
50 V
VDD
DMOS
FULL-BRIDGE 1
VBB1
VCP
OSC
CHARGE PUMP
OUT1A
PHASE1
OUT1B
I01
Control Logic
Bridges 1 and 2
I11
PHASE2
SENSE1
I02
GATE
DRIVE
VREF1
3
+
Sense1
VBB1
DMOS
FULL-BRIDGE 2
-
I12
PWM Latch
BLANKING
OUT2A
3
PWM Latch
BLANKING
OUT2B
-
Sense2
+
VREF2
PHASE3
VCP
I03
Sense2
Control Logic
Bridges 3 and 4
I13
SENSE2
VBB2
PHASE4
DMOS
FULL-BRIDGE 3
I04
OUT3A
OUT3B
I14
GATE
DRIVE
VREF3
3
Sense3
PWM Latch
BLANKING
DMOS
FULL-BRIDGE 4
Sense4
OUT4B
SENSE4
GND
-
Sense4
PWM Latch
BLANKING
GND
3
OUT4A
+
VREF4
SENSE3
VBB2
+
Sense3
Functional Block Diagram
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
A3988
19 I14
20 OUT4A
21 SENSE4
22 OUT4B
23 VBB2
24 OUT3B
25 SENSE3
26 OUT3A
27 I13
25 NC
26 NC
27 OUT4A
28 SENSE4
29 OUT4B
30 NC
31 VBB2
32 OUT3B
34 OUT3A
35 NC
36 NC
Pin-out Diagrams and Terminal List Table
33 SENSE3
Quad DMOS Full Bridge PWM Motor Driver
I13 37
24
I14
I12 38
23
NC
I11 39
22
PHASE1
GND 40
21
PHASE2
20
GND
19
VREF4
I12 28
18
PHASE1
NC 41
I11 29
17
PHASE2
VCP 42
GND 30
16
GND
CP1 43
18
VREF3
VCP 31
15
VREF4
CP2 44
17
VREF2
14
VREF3
I01 45
16
VREF1
15
VDD
PAD
CP1 32
PAD
Package EV, 36-Pin QFN Pin-out
9
SENSE2
NC 12
8
OUT2B
NC 11
7
NC
OUT2A 10
6
4
SENSE1
VBB1
3
OUT1A
5
2
OUT1B
1
NC
9
PHASE4
Packages are not to scale
NC
8
PHASE3
OUT2A
10
7
PHASE4
I03 36
SENSE2
13
6
I04 48
OUT2B
VDD
5
11
VBB1
PHASE3
I02 35
4
14
OUT1B
I03 47
3
VREF1
SENSE1
12
2
I01 34
1
VREF2
I04
13
OUT1A
CP2 33
I02 46
Package JP, 48-Pin LQFP Pin-out
Terminal List Table
EV
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
1
–
–
1VBB1
Number
JP
3
4
5
6
8
9
10
13
14
15
16
17
18
19
20
21
22
24
27
28
29
31
32
33
34
37
38
39
40
42
43
44
45
46
47
48
1, 2, 7, 11,
12, 23, 25,
26, 30, 35,
36, 41
–
Pin Name
Pin Description
OUT1A
SENSE1
OUT1B
VBB11
OUT2B
SENSE2
OUT2A
PHASE4
PHASE3
VDD
VREF1
VREF2
VREF3
VREF4
GND
PHASE2
PHASE1
I14
OUT4A
SENSE4
OUT4B
VBB21
OUT3B
SENSE3
OUT3A
I13
I12
I11
GND
VCP
CP1
CP2
I01
I02
I03
I04
DMOS Full-Bridge 1 Output A
Sense Resistor Terminal for Bridge 1
DMOS Full-Bridge 1 Output B
Load Supply Voltage
DMOS Full-Bridge 2 Output B
Sense Resistor Terminal for Bridge 2
DMOS Full-Bridge 2 Output A
Control Input
Control Input
Logic Supply Voltage
Analog Input
Analog Input
Analog Input
Analog Input
Ground
Control Input
Control Input
Control Input
DMOS Full-Bridge 4 Output A
Sense Resistor Terminal for Bridge 4
DMOS Full-Bridge 4 Output B
Load Supply Voltage
DMOS Full-Bridge 3 Output B
Sense Resistor Terminal for Bridge 3
DMOS Full-Bridge 3 Output A
Control Input
Control Input
Control Input
Ground
Reservoir Capacitor Terminal
Charge Pump Capacitor Terminal
Charge Pump Capacitor Terminal
Control Input
Control Input
Control Input
Control Input
NC
No Connect
PAD
Exposed pad for enhanced thermal
performance. Should be soldered to the
PCB.
and VBB2 need to be connected together close to the A3988
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
A3988
Quad DMOS Full Bridge PWM Motor Driver
ELECTRICAL CHARACTERISTICS1: valid at TA = 25°C, VBB = 36 V, unless otherwise noted
Min.
Typ.2
Max.
Units
Load Supply Voltage Range
Characteristics
VBB
Operating
8.0
–
36
V
Logic Supply Voltage Range
VDD
Operating
3.0
–
5.5
V
VDD Supply Current
IDD
–
7
10
mA
Source driver, IOUT = –1.2 A, TJ = 25°C
–
700
800
mΩ
–
700
800
mΩ
IOUT = 1.2 A
–
–
1.3
V
–20
–
20
µA
–
–
8
mA
VIN(1)
0.7×VDD
–
–
V
VIN(0)
–
–
0.3×VDD
V
–20
<1.0
20
µA
Output On Resistance
Symbol
RDS(on)
Vf , Outputs
Test Conditions
Sink driver, IOUT = 1.2 A, TJ = 25°C
Output Leakage
IDSS
Outputs, VOUT = 0 to VBB
VBB Supply Current
IBB
IOUT = 0 mA, outputs on, PWM = 50 kHz,
DC = 50%
Control Logic
Logic Input Voltage
Logic Input Current
Input Hysteresis
IIN
VIN = 0 to 5 V
150
300
500
mV
PWM change to source on
350
550
1000
ns
PWM change to source off
35
–
300
ns
PWM change to sink on
350
550
1000
ns
PWM change to sink off
35
–
250
ns
tCOD
300
425
1000
ns
Blank Time
tBLANK
0.7
1
1.3
µs
VREFx Pin Input Voltage Range
Propagation Delay Times
Crossover Delay
Vhys
tpd
VREFx
Operating
0.0
–
1.5
V
VREFx Pin Reference Input Current
IREF
VREF = 1.5
–
–
±1
μA
VREF = 1.5, phase current = 100%
–5
–
5
%
Current Trip-Level Error3
VERR
VREF = 1.5, phase current = 67%
–5
–
5
%
VREF = 1.5, phase current = 33%
–15
–
15
%
Protection Circuits
VBB UVLO Threshold
VBB Hysteresis
VDD UVLO Threshold
VDD Hysteresis
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
VUV(VBB)
VBB rising
VUV(VBB)hys
VUV(VDD)
VDD rising
7.3
7.6
7.9
V
400
500
600
mV
2.65
2.8
2.95
V
VUV(VDD)hys
75
105
125
mV
TJTSD
155
165
175
°C
TJTSDhys
–
15
–
°C
1For
input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.
data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual units, within the
specified maximum and minimum limits.
3V
ERR = [(VREF/3) – VSENSE] / (VREF/3).
2Typical
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
A3988
Quad DMOS Full Bridge PWM Motor Driver
FUNCTIONAL DESCRIPTION
Device Operation
Fixed Off-Time
The A3988 is designed to operate two stepper motors, four DC
motors, or one stepper and two DC motors. The currents in each
of the output full-bridges, all N-channel DMOS, are regulated
with fixed off-time pulse width modulated (PWM) control
circuitry. Each full-bridge peak current is set by the value of
an external current sense resistor, RSx , and a reference voltage,
VREFx .
The internal PWM current control circuitry uses a one shot
circuit to control the time the drivers remain off. The one shot
off-time, toff , is internally set to 30 µs.
If the logic inputs are pulled up to VDD, it is good practice to use
a high value pull-up resistor in order to limit current to the logic
inputs, should an overvoltage event occur. Logic inputs include:
PHASEx, I0x, and I1x.
Internal PWM Current Control
Each full-bridge is controlled by a fixed off-time PWM current
control circuit that limits the load current to a desired value,
ITRIP . Initially, a diagonal pair of source and sink DMOS outputs
are enabled and current flows through the motor winding and
RSx. When the voltage across the current sense resistor equals the
voltage on the VREFx pin, the current sense comparator resets
the PWM latch, which turns off the source driver.
The maximum value of current limiting is set by the selection of
RS and the voltage at the VREF input with a transconductance
function approximated by:
ITripMax = VREF / (3×RS)
Each current step is a percentage of the maximum current,
ITripMax. The actual current at each step ITrip is approximated by:
ITrip = (% ITripMax / 100) ITripMax
where % ITripMax is given in the Step Sequencing table.
Note: It is critical to ensure that the maximum rating of ±500
mV on each SENSEx pin is not exceeded.
Blanking
This function blanks the output of the current sense comparator when the outputs are switched by the internal current control
circuitry. The comparator output is blanked to prevent false
detections of overcurrent conditions, due to reverse recovery
currents of the clamp diodes, or to switching transients related to
the capacitance of the load. The stepper blank time, tBLANK , is
approximately 1 μs.
Control Logic
Communication is implemented via the industry standard I1,
I0, and PHASE interface. This communication logic allows
for full, half, and quarter step modes. Each bridge also has an
independent VREF input so higher resolution step modes can be
programmed by dynamically changing the voltage on the VREFx
pins.
Charge Pump (CP1 and CP2)
The charge pump is used to generate a gate supply greater than
the VBB in order to drive the source-side DMOS gates. A 0.1 μF
ceramic capacitor should be connected between CP1 and CP2
for pumping purposes. A 0.1 μF ceramic capacitor is required
between VCP and VBBx to act as a reservoir to operate the highside DMOS devices.
Shutdown
In the event of a fault (excessive junction temperature, or low
voltage on VCP), the outputs of the device are disabled until the
fault condition is removed. At power-up, the undervoltage lockout (UVLO) circuit disables the drivers.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
A3988
Quad DMOS Full Bridge PWM Motor Driver
Synchronous Rectification
Mixed Decay Operation
When a PWM-off cycle is triggered by an internal fixed off-time
cycle, load current will recirculate. The A3988 synchronous rectification feature will turn on the appropriate MOSFETs during the
current decay, and effectively short out the body diodes with the
low RDS(on) driver. This significantly lowers power dissipation.
When a zero current level is detected, synchronous rectification is
turned off to prevent reversal of the load current.
The bridges operate in mixed decay mode. Referring to Figure
1, as the trip point is reached, the device goes into fast decay
mode for 30.1% of the fixed off-time period. After this fast decay
portion, tFD , the device switches to slow decay mode for the
remainder of the off-time. During transitions from fast decay to
slow decay, the drivers are forced off for approximately 600 ns.
This feature is added to prevent shoot-through in the bridge. As
shown in Figure 1, during this “dead time” portion, synchronous
rectification is not active, and the device operates in fast decay
and slow decay only.
VPHASE
+
IOUT
See Enlargement A
0
–
Enlargement A
Fixed Off-Time 30 µs
9 µs
21 µs
ITrip
IOUT
SDSR
FDSR
FDDT
SDDT
SDDT
Figure 1: Mixed Decay Mode Operation
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
A3988
Quad DMOS Full Bridge PWM Motor Driver
STEP SEQUENCING DIAGRAMS
Phase 1
(%)
100.0
100.0
66.7
66.7
Phase 1
(%)
0
–66.7
–66.7
Phase 2
(%)
0
–100.0
–100.0
100.0
100.0
66.7
66.7
Phase 2
(%)
0
0
–66.7
–66.7
–100.0
–100.0
Full step 2 phase
Half step 2 phase
Modified full step 2 phase
Modified half step 2 phase
Figure 2: Step Sequencing for Full-Step
Increments.
Figure 3: Step Sequencing for Half-Step Increments.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
A3988
Quad DMOS Full Bridge PWM Motor Driver
100.0
66.7
33.3
Phase 1
(%)
0
–33.3
–66.7
–100.0
100.0
66.7
33.3
Phase 2
(%)
0
–33.3
–66.7
–100.0
Figure 4: Step Sequence for Quarter-Step Increments
Table 1: Step Sequencing Settings
Full
1
1/2
1/4
Phase 1
(%ITripMax)
I0x
I1x
PHASE
Phase 2
(%ITripMax)
I0x
I1x
PHASE
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
0
33
100/66*
100
100
100
100/66*
33
0
33
100/66*
100
100
100
100/66*
33
H
L
L/H*
L
L
L
L/H*
L
H
L
L/H*
L
L
L
L/H*
L
H
H
L
L
L
L
L
H
H
H
L
L
L
L
L
H
X
1
1
1
1
1
1
1
X
0
0
0
0
0
0
0
100
100
100/66*
33
0
33
100/66*
100
100
100
100/66*
33
0
33
100/66*
100
L
L
L/H*
L
H
L
L/H*
L
L
L
L/H*
L
H
L
L/H*
L
L
L
L
H
H
H
L
L
L
L
L
H
H
H
L
L
0
0
0
0
X
1
1
1
1
1
1
1
X
0
0
0
2
3
2
4
5
3
6
7
4
*Denotes
8
modified step mode
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
9
A3988
Quad DMOS Full Bridge PWM Motor Driver
APPLICATIONS INFORMATION
Motor Configurations
For applications that require either a stepper/DC motor driver
or dual DC motor driver, Allegro offers the A3989 and A3995.
These devices are offered in the same 36 pin QFN package as the
A3988. The DC motor drivers are capable of supplying 2.4 A at
36 V. Commutation is done with a standard phase/enable logic
interface. Please refer to the Allegro website for further information and datasheets about those devices.
DC Motor Control
Each of the 4 full bridges has independent PWM current control
circuitry that makes the A3988 capable of driving up to four
DC motors at currents up to 1.2 A. Control of the DC motors
is accomplished by tying the I0, I1 pins together creating an
equivalent ENABLE function with maximum current defined by
the voltage on the corresponding VREF pin. The DC motors can
be driven via a PWM signal on this enable signal, or on the corresponding PHASE pin. Motor control includes forward, reverse,
and coast.
package is an exposed pad, which provides a path for enhanced
thermal dissipation. The thermal pad should be soldered directly
to an exposed surface on the PCB. Thermal vias are used to transfer heat to other layers of the PCB.
Grounding
In order to minimize the effects of ground bounce and offset
issues, it is important to have a low impedance single-point
ground, known as a star ground, located very close to the device.
By making the connection between the exposed thermal pad and
the groundplane directly under the A3988, that area becomes an
ideal location for a star ground point.
A low impedance ground will prevent ground bounce during
high current operation and ensure that the supply voltage remains
stable at the input terminal. The recommended PCB layout shown
in the diagram below, illustrates how to create a star ground
under the device, to serve both as low impedance ground point
and thermal path.
Solder
A3988
Layout
Trace (2 oz.)
Signal (1 oz.)
The printed circuit board should use a heavy groundplane. For
optimum electrical and thermal performance, the A3988 must be
soldered directly onto the board. On the underside of the A3988
Ground (1 oz.)
PCB
Thermal (2 oz.)
Thermal Vias
VBB
VBB
CVCP
CVCP
GND
CCP
OUT3A
OUT1A
OUT3B
RS1
OUT1B
RS2
I11
I12
GND
CP1
VCP
OUT4A
CIN2
RS4
I14
PHASE1
PHASE2
PHASE4
GND
RS4
RS2
OUT2A
VREF2
OUT4B
OUT4A
OUT4B
SENSE4
VREF1
OUT2B
OUT2A
RS3
VBB2
SENSE2
VDD
CIN2
OUT3B
OUT2B
PHASE3
CIN1
SENSE3
PAD
VBB1
CIN1
OUT3A
A3988
SENSE1
VREF4
OUT1B
I13
I04
VREF3
U1
I01
1
RS3
CP2
RS1
OUT1A
I02
CIN3
I03
GND
CIN3
CCP
CVDD1
CVDD1
GND
VDD
CVDD2
EV package layout shown
CVDD2
Figure 5: Printed circuit board layout with typical application circuit, shown at right.
The copper area directly under the A3988 (U1) is soldered to the exposed thermal pad on the underside of the device. The thermal vias serve
also as electrical vias, connecting it to the ground plane on the other side of the PCB , so the two copper areas together form the star ground.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
10
A3988
Quad DMOS Full Bridge PWM Motor Driver
The two input capacitors should be placed in parallel, and as
close to the device supply pins as possible. The ceramic capacitor should be closer to the pins than the bulk capacitor. This is
necessary because the ceramic capacitor will be responsible for
delivering the high frequency current components.
Sense Pins
sense comparators. Long ground traces will cause additional
voltage drops, adversely affecting the ability of the comparators
to accurately measure the current in the windings. As shown in
the layout below, the SENSEx pins have very short traces to the
RSx resistors and very thick, low impedance traces directly to the
star ground underneath the device. If possible, there should be no
other components on the sense circuits.
The sense resistors, RSx, should have a very low impedance
path to ground, because they must carry a large current while
supporting very accurate voltage measurements by the current
Note:
When selecting a value for the sense resistors, be sure not to
exceed the maximum voltage on the SENSEx pins of ±500 mV.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
11
A3988
Quad DMOS Full Bridge PWM Motor Driver
Package Outline Diagrams
For Reference Only – Not for Tooling Use
(Reference JEDEC MO-220VJJD-3, except pin count)
Dimensions in millimeters – NOT TO SCALE
Exact case and lead configuration at supplier discretion within limits shown
0.50
0.30
6.00 ±0.15
36
36
1.15
1
2
1
2
A
4.15
6.00 ±0.15
D
C
37X
0.08
0.90 ±0.10
C
5.80
4.15
5.80
SEATING
PLANE
+0.05
0.25 –0.07
C
PCB Layout Reference View
0.50
0.55 ±0.20
B
4.15
2
1
A
Terminal #1 mark area
B
Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion)
C
Reference land pattern layout (reference IPC7351 QFN50P600X600X100-37V1M); All pads a
minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process
requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at
the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard
JESD51-5)
D
Coplanarity includes exposed thermal pad and terminals
36
4.15
Figure 6: EV Package, 36 Pin QFN with Exposed Thermal Pad
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
12
A3988
Quad DMOS Full Bridge PWM Motor Driver
For Reference Only – Not for Tooling Use
(Reference JEDEC MS-026 BBCHD)
Dimensions in millimeters – NOT TO SCALE
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
0.30
9.00 ±0.20
7º
0º
7.00 ±0.20
0.15
+0.05
–0.06
1.70
C
B
9.00 ±0.20
0.50
4° ±4
7.00 ±0.20
5.00
5.00 ±0.04
48
8.60
48
A
0.60 ±0.15 (1.00)
1
2
1 2
0.25
5.00 ±0.04
5.00
SEATING PLANE
GAGE PLANE
8.60
C
48X
0.22 ±0.05
C
1.40 ±0.05 1.60 MAX
0.08 C
SEATING
PLANE
PCB Layout Reference View
A
Terminal #1 mark area
B
Exposed thermal pad (bottom surface)
C
Reference land pattern layout (reference IPC7351 QFP50P900X900X160-48M);
adjust as necessary to meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal vias at the exposed
thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard
JESD51-5)
0.50
0.10 ±0.05
Figure 7: JP Package, 48 Pin LQFP with Exposed Thermal Pad
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
13
A3988
Quad DMOS Full Bridge PWM Motor Driver
Revision History
Revision
Revision Date
9
June 14, 2011
10
July 9, 2014
Description of Revision
Change in packing options
Revised Step Sequence Settings table and Functional Block Diagram
Copyright ©2006-2014, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
14
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