A3989 Datasheet

A3989
Bipolar Stepper and High Current DC Motor Driver
Not for New Design
The A3989SEVTR-T is in production but has been determined to be
NOT FOR NEW DESIGN. This classification indicates that sale of
this device is currently restricted to existing customer applications. The
device should not be purchased for new design applications because
obsolescence in the near future is probable. Samples are no longer
available.
Date of status change: June 27, 2016
Recommended Substitutions:
Recommended Substitutions:
A5989GEVTR-T
NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
A3989
Bipolar Stepper and High Current DC Motor Driver
Features and Benefits
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Description
36 V output rating
2.4 A DC motor driver
1.2 A bipolar stepper driver
Synchronous rectification
Internal undervoltage lockout (UVLO)
Thermal shutdown circuitry
Crossover-current protection
Very thin profile QFN package
The A3989 is designed operate at voltages up to 36 V while driving
one bipolar stepper motor, at currents up to 1.2A, and one DC motor,
at currents up to 2.4 A. The A3989 includes a fixed off-time pulse
width modulation (PWM) regulator for current control. The stepper
motor driver features dual 2-bit nonlinear DACs (digital-to-analog
converters) that enable control in full, half, and quarter steps. The
DC motor is controlled using standard PHASE and ENABLE signals.
Fast or slow current decay is selected via the MODE pin. The PWM
current regulator uses the Allegro™ patented mixed decay mode for
reduced audible motor noise, increased step accuracy, and reduced
power dissipation.
Internal synchronous rectification control circuitry is provided to
improve power dissipation during PWM operation.
Package: 36 pin QFN with exposed thermal pad
0.90 mm nominal height (suffix EV)
Protection features include thermal shutdown with hysteresis,
undervoltage lockout (UVLO) and crossover current protection.
Special power up sequencing is not required.
The A3989 is supplied in a leadless 6 mm × 6 mm × 0.9 mm,
36 pin QFN package with exposed power tab for enhanced thermal
performance. The package is lead (Pb) free, with 100% matte tin
leadframe plating.
Approximate scale 1:1
0.1 μF
50 V
CP1
0.1 μF
50 V
CP2
100 μF
50 V
VCP
VDD
VBB
VBB
OUT1A
OUT1B
PHASE1
I01
Microcontroller or
Controller Logic
SENSE1
A3989
I11
OUT2A
PHASE2
OUT2B
I02
SENSE2
I12
PHASE3
OUT3A
ENABLE
OUT3A
MODE
OUT3B
VREF1
OUT3B
VREF2
SENSE3
VREF3
GND
GND
SENSE3
Figure 1. Typical application circuit
A3989DS, Rev. 3
0.22 μF
50 V
A3989
Bipolar Stepper and High Current DC Motor Driver
Selection Guide
Part Number
Packing
A3989SEV-T
61 pieces per tube
A3989SEVTR-T
1500 pieces per reel
Absolute Maximum Ratings
Characteristic
Symbol
Load Supply Voltage
VBB
Logic Supply Voltage
VDD
Output Current*
IOUT
Logic Input Voltage Range
VIN
Notes
Pulsed tw < 1 μs
VREFx Pin Voltage
Operating Temperature Range
Junction Temperature
Storage Temperature Range
VSENSEx
Units
V
38
V
–0.4 to 7
V
A
Stepper motor driver, continuous
1.2
Stepper motor driver, pulsed tw < 1 μs
2.8
A
Dc motor driver, continuous
2.4
A
Dc motor driver, pulsed tw < 1 μs
SENSEx Pin Voltage
Rating
-0.5 to 36
Pulsed tw < 1 μs
3.5
A
–0.3 to 7
V
0.5
V
2.5
V
2.5
V
–20 to 85
ºC
TJ(max)
150
ºC
Tstg
–55 to 150
ºC
VREFx
TA
Range S
* May be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a
Junction Temperature of 150°C.
Thermal Characteristics (may require derating at maximum conditions)
Symbol
RθJA
Test Conditions
Min. Units
EV package, 4 layer PCB based on JEDEC standard
27
ºC/W
Power Dissipation versus Ambient Temperature
5500
5000
4500
4000
Power Dissipation, PD (mW)
Characteristic
Package Thermal Resistance
3500
3000
2500
2000
EV Package
4-layer PCB
(RQJA = 27 ºC/W)
1500
1000
500
0
25
50
75
100
125
Temperature (°C)
150
175
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
A3989
Bipolar Stepper and High Current DC Motor Driver
Functional Block Diagram
0.1 μF
50 V
0.1 μF
50 V
VDD
DMOS
Full Bridge 1
OSC
0.22 μF
50 V
To
VBB2
VBB
VBB
VCP
CP2
CP1
100 μF
50 V
VBB1
CHARGE PUMP
VCP
OUT1A
PHASE1
OUT1B
I01
I11
Control Logic
Stepper Motor
PHASE2
RS1
DMOS
Full Bridge 2
I12
VBB1
-
Sense1
3
PWM Latch
BLANKING
+
VREF1
SENSE1
GATE
DRIVE
I02
OUT2A
3
+
VREF2
PWM Latch
BLANKING
OUT2B
-
Sense 2
VCP
PHASE3
Control Logic
DC Motor
ENABLE
Sense 2
MODE
SENSE2
RS2
Sense 3
GATE
DRIVE
OUT3A
OUT3A
DMOS
Full Bridge 3
PWM Latch
BLANKING
+
3
OUT3B
OUT3B
SENSE3
RS3
GND
GND
NC
NC
NC
SENSE3
NC
VREF3
-
Sense 3
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
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3
A3989
Bipolar Stepper and High Current DC Motor Driver
ELECTRICAL CHARACTERISTICS1, valid at TA = 25 °C, VBB = 36 V, unless otherwise noted
Characteristics
Symbol
Test Conditions
Min.
Typ.2
Max.
Units
Load Supply Voltage Range
VBB
Operating
8.0
–
36
V
Logic Supply Voltage Range
VDD
Operating
3.0
–
5.5
V
VDD Supply Current
IDD
–
7
10
mA
Output On Resistance (DC motor driver)
RDS(on)DC
Source driver, IOUT = –1.2 A, TJ = 25°C
Sink driver, IOUT = 1.2 A, TJ = 25°C
–
350
450
mΩ
–
350
450
mΩ
Output On Resistance (stepper motor
driver)
RDS(on)st
Source driver, IOUT = –1.2 A, TJ = 25°C
Sink driver, IOUT = 1.2 A, TJ = 25°C
–
700
800
mΩ
–
700
800
mΩ
Vf , Outputs
IOUT = 1.2 A
Output Leakage
IDSS
Outputs, VOUT = 0 to VBB
VBB Supply Current
IBB
IOUT = 0 mA, outputs on, PWM = 50 kHz,
DC = 50%
–
–
1.3
V
–20
–
20
μA
–
–
8
mA
V
Control Logic
VIN(1)
0.7×VDD
–
–
VIN(0)
–
–
0.3×VDD
V
VIN = 0 to 5 V
–20
<1.0
20
μA
150
300
500
mV
PWM change to source on
350
550
1000
ns
PWM change to source off
35
–
300
ns
PWM change to sink on
350
550
1000
ns
PWM change to sink off
35
–
250
ns
tCOD
300
425
1000
ns
Blank Time (DC motor driver)
tBLANKdc
2.5
3.2
4
μs
Blank Time (stepper motor driver)
tBLANKst
0.7
1
1.3
μs
Logic Input Voltage
Logic Input Current
Input Hysteresis
Propagation Delay Times
Crossover Delay
VREFx Pin Input Voltage Range
IIN
Vhys
tpd
VREFx
Operating
0.0
–
1.5
V
VREFx Pin Reference Input Current
IREF
VREF = 1.5
–
–
±1
μA
VREF = 1.5, phase current = 100%
–5
–
5
%
Current Trip-Level Error3
VERR
VREF = 1.5, phase current = 67%
–5
–
5
%
VREF = 1.5, phase current = 33%
–15
–
15
%
Protection Circuits
VBB UVLO Threshold
VBB Hysteresis
VDD UVLO Threshold
VDD Hysteresis
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
VUV(VBB)
VBB rising
VUV(VBB)hys
VUV(VDD)
VDD rising
7.3
7.6
7.9
V
400
500
600
mV
2.65
2.8
2.95
V
VUV(VDD)hys
75
105
125
mV
TJTSD
155
165
175
°C
TJTSDhys
–
15
–
°C
1For
input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.
data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual units, within the specified maximum and minimum limits.
3V
ERR = [(VREF/3) – VSENSE] / (VREF/3).
2Typical
DC Control Logic
PHASE
ENABLE
MODE
OUTA
OUTB
Function
1
1
1
H
L
Forward (slow decay SR)
1
1
0
H
L
Forward (fast decay SR)
0
1
1
L
H
Reverse (slow decay SR)
0
1
0
L
H
Reverse (fast decay SR)
X
0
1
L
L
Brake (slow decay SR)
1
0
0
L
H
Fast decay SR*
0
0
0
H
L
Fast decay SR*
* To prevent reversal of current during fast decay SR – the outputs will go to the high impedance state as the current gets near zero.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
A3989
Bipolar Stepper and High Current DC Motor Driver
Functional Description
Device Operation The A3989 is designed to operate one
DC motor and one bipolar stepper motor. The currents in each of
the full bridges, all N-channel DMOS, are regulated with fixed
off-time pulse width modulated (PWM) control circuitry. The
peak current in each full bridge is set by the value of an external
current sense resistor, RSx , and a reference voltage, VREFx .
If the logic inputs are pulled up to VDD, it is good practice to use
a high value pullup resistor in order to limit current to the logic
inputs should an overvoltage event occur. Logic inputs include:
PHASEx, I0x, I1x, ENABLE, and MODE.
Internal PWM Current Control Each full-bridge is
controlled by a fixed off-time PWM current control circuit that
limits the load current to a user-specified value, ITRIP . Initially,
a diagonal pair of source and sink DMOS outputs are enabled
and current flows through the motor winding and RSx. When the
voltage across the current sense resistor equals the voltage on the
VREFx pin, the current sense comparator resets the PWM latch,
which turns off the source driver.
The maximum value of current limiting is set by the selection of
RS and the voltage at the VREF input with a transconductance
function approximated by:
ITripMax = VREF / (3×RS)
Blanking This function blanks the output of the current sense
comparator when the outputs are switched by the internal current
control circuitry. The comparator output is blanked to prevent
false detections of overcurrent conditions, due to reverse recovery
currents of the clamp diodes, or to switching transients related to
the capacitance of the load. Dc motors require more blank time
than stepper motors. The stepper driver blank time, tBLANKst ,
is approximately 1 s. The DC driver blank time, tBLANKdc , is
approximately 3 s.
Control Logic Stepper motor communication is implemented
via industry standard I1, I0, and PHASE interface. This communication logic allows for full, half, and quarter step modes. Each
bridge also has an independent VREF input so higher resolution step
modes can be programmed by dynamically changing the voltage on
the corresponding VREFx pin. The DC motor is controlled using
standard PHASE, ENABLE communication. Fast or slow current
decay during the off-time is selected via the MODE pin.
Charge Pump (CP1 and CP2) The charge pump is used to
generate a gate supply greater than the VBB in order to drive the
source-side DMOS gates. A 0.1 F ceramic capacitor should be
connected between CP1 and CP2 for pumping purposes. A 0.1 F
ceramic capacitor is required between VCP and VBBx to act as a
reservoir to operate the high-side DMOS devices.
The stepper motor outputs will define each current step as a
percentage of the maximum current, ITripMax. The actual current at Shutdown In the event of a fault (excessive junction temperature, or low voltage on VCP), the outputs of the device are
each step ITrip is approximated by:
disabled until the fault condition is removed. At power-up, the
ITrip = (% ITripMax / 100) ITripMax
undervoltage lockout (UVLO) circuit disables the drivers.
where % ITripMax is given in the Step Sequencing table.
Synchronous Rectification When a PWM-off cycle is
Note: It is critical to ensure that the maximum rating of 500 mV triggered by an internal fixed off-time cycle, load current will
on each SENSEx pin is not exceeded.
recirculate. The A3989 synchronous rectification feature will
turn on the appropriate MOSFETs during the current decay. This
Fixed Off-Time The internal PWM current control circuitry
effectively shorts the body diode with the low RDS(on) driver. This
uses a one shot circuit to control the time the drivers remain off.
significantly lowers power dissipation. When a zero current level
The one shot off-time, toff , is internally set to 30 μs.
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
A3989
Bipolar Stepper and High Current DC Motor Driver
is detected, synchronous rectification is turned off to prevent
reversal of the load current.
puts the device in slow decay mode. Synchronous rectification is
always enabled when ENABLE is low.
Mixed Decay Operation The stepper driver operates in
mixed decay mode. Referring to figure 2, as the trip point is
reached, the device goes into fast decay mode for 30.1% of
the fixed off-time period. After this fast decay portion, tFD , the
device switches to slow decay mode for the remainder of the
off-time. The DC driver decay mode is determined by the MODE
pin. During transitions from fast decay to slow decay, the drivers
are forced off for approximately 600 ns. This feature is added to
prevent shoot-through in the bridge. As shown in figure 2, during
this “dead time” portion, synchronous rectification is not active,
and the device operates in fast decay and slow decay only.
Braking Driving the device in slow decay mode via the MODE
pin and applying an ENABLE chop command implements
the Braking function. Because it is possible to drive current in
both directions through the DMOS switches, this configuration effectively shorts the motor-generated BEMF as long as the
ENABLE chop mode is asserted. The maximum current can be
approximated by VBEMF/RL. Care should be taken to ensure that
the maximum ratings of the device are not exceeded in worst case
MODE Control input MODE is used to toggle between fast
decay mode and slow decay mode for the DC driver. A logic high
braking situations: high speed and high inertia loads.
VPHASE
+
IOUT
See Enlargement A
0
–
Enlargement A
Fixed Off-Time 30 μs
9 μs
21 μs
ITrip
IOUT
SDSR
FDSR
FDDT
SDDT
SDDT
Figure 2. Mixed Decay Mode Operation
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115 Northeast Cutoff
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6
A3989
Bipolar Stepper and High Current DC Motor Driver
Step Sequencing Diagrams
Phase 1
(%)
100.0
100.0
66.7
66.7
Phase 1
(%)
0
0
–66.7
–66.7
Phase 2
(%)
–100.0
–100.0
100.0
100.0
66.7
66.7
Phase 2
(%)
0
0
–66.7
–66.7
–100.0
–100.0
Full step 2 phase
Half step 2 phase
Modified full step 2 phase
Modified half step 2 phase
Figure 3. Step Sequencing for Full-Step Increments.
Figure 4. Step Sequencing for Half-Step Increments.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
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7
A3989
Bipolar Stepper and High Current DC Motor Driver
100.0
66.7
33.3
Phase 1
(%)
0
–33.3
–66.7
–100.0
100.0
66.7
33.3
Phase 2
(%)
0
–33.3
–66.7
–100.0
Figure 5. Decay Modes for Quarter-Step Increments
Step Sequencing Settings
Full
1/2
1
1/4
Phase 1
(%ITripMax)
1
2
1
2
3
4
3
5
6
2
4
7
8
5
9
10
3
6
11
12
7
13
14
4
8
15
16
* Denotes modified step mode
0
33
100 / 66*
100
100
100
100 / 66*
33
0
33
100 / 66*
100
100
100
100 / 66*
33
I0x
I1x
PHASE
Phase 2
(%ITripMax)
I0x
I1x
PHASE
H
L
H
L
L
L
H
L
H
L
H
L
L
L
H
L
H
H
L/H*
L
L
L
L/H*
H
H
H
L/H*
L
L
L
L/H*
H
x
1
1
1
1
1
1
1
x
0
0
0
0
0
0
0
100
100
100 / 66*
33
0
33
100 / 66*
100
100
100
100 / 66*
33
0
33
100 / 66*
100
L
L
H
L
H
L
H
L
L
L
H
L
H
L
H
L
L
L
L/H*
H
H
H
L/H*
L
L
L
L/H*
H
H
H
L/H*
L
1
1
1
1
X
0
0
0
0
0
0
0
X
1
1
1
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
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8
A3989
Bipolar Stepper and High Current DC Motor Driver
Logic Timing Diagram, DC Driver
ENB
PH
MODE
VBB
OUTA
0V
VBB
OUTB
0V
IOUT
0A
A
1
2
3
4
5
6
7
VBB
8
9
VBB
1 5
6
OutA
OutB
3
2 4
7
OutA
OutB
8
9
A
Charge Pump and VREG Power-up Delay (z200 μs)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
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A3989
Bipolar Stepper and High Current DC Motor Driver
Applications Information
Motor Configurations For applications that require either dual
DC or dual stepper motors, Allegro offers the A3988 and A3995.
Both devices are offered in a 36 pin QFN package. Please refer to
the Allegro website for further information and datasheets for the
devices.
Layout The printed circuit board should use a heavy groundplane. For optimum electrical and thermal performance, the
A3989 must be soldered directly onto the board. On the underside of the A3989 package is an exposed pad, which provides a
path for enhanced thermal dissipation. The thermal pad should be
soldered directly to an exposed surface on the PCB. Thermal vias
are used to transfer heat to other layers of the PCB.
Grounding In order to minimize the effects of ground bounce
and offset issues, it is important to have a low impedance singlepoint ground, known as a star ground, located very close to the
device. By making the connection between the exposed thermal
pad and the groundplane directly under the A3989, that area
becomes an ideal location for a star ground point.
A low impedance ground will prevent ground bounce during
high current operation and ensure that the supply voltage remains
stable at the input terminal. The recommended PCB layout shown
in the diagram below, illustrates how to create a star ground
under the device, to serve both as low impedance ground point
and thermal path.
The two input capacitors should be placed in parallel, and as
close to the device supply pins as possible. The ceramic capacitor should be closer to the pins than the bulk capacitor. This is
necessary because the ceramic capacitor will be responsible for
delivering the high frequency current components.
Sense Pins The sense resistors, RSx, should have a very
low impedance path to ground, because they must carry a large
current while supporting very accurate voltage measurements
by the current sense comparators. Long ground traces will cause
additional voltage drops, adversely affecting the ability of the
comparators to accurately measure the current in the windings.
As shown in the layout below, the SENSEx pins have very short
traces to the RSx resistors and very thick, low impedance traces
directly to the star ground underneath the device. If possible,
there should be no other components on the sense circuits.
Note: When selecting a value for the sense resistors, be sure not to
exceed the maximum voltage on the SENSEx pins of ±500 mV.
VBB
VBB
CVCP
CVCP
CIN3
CCP
GND
GND
OUT3B
A3989
SENSE1
RS1
OUT1B
CIN1
CIN2
OUT2B
RS2
I11
SENSE3
OUT3B
PAD
VBB
CIN1
I12
GND
CP1
VCP
I01
MODE
OUT3A
OUT1A
U1
OUT1B
NC
CP2
1
OUT1A
I02
CIN3
RS3
RS1
ENABLE
CCP
OUT2B
OUT3B
SENSE2
SENSE3
OUT2A
OUT3A
PHASE1
PHASE2
GND
NC
VREF3
VREF2
VREF1
VDD
RS2
PHASE3
OUT3A
CIN2
NC
NC
OUT2A
RS3
VBB
CVDD1
GND
VDD
CVDD2
CVDD1
CVDD2
Figure 5. Printed circuit board layout with typical application circuit, shown at right. The copper area directly under the
A3989 (U1) is soldered to the exposed thermal pad on the underside of the device. The thermal vias serve also as electrical
vias, connecting it to the ground plane on the other side of the PCB , so the two copper areas together form the star ground.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
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10
A3989
Bipolar Stepper and High Current DC Motor Driver
19 NC
20 OUT3A
21 SENSE3
22 OUT3B
23 VBB
24 OUT3B
25 SENSE3
26 OUT3A
27 MODE
Pin-out Diagram
I12 28
18
PHASE1
I11 29
17
PHASE2
16
GND
15
NC
CP1 32
14
VREF3
CP2 33
13
VREF2
I01 34
12
VREF1
I02 35
11
VDD
ENABLE 36
10
PHASE3
GND 30
PAD
1
2
3
4
5
6
7
8
9
NC
OUT1A
SENSE1
OUT1B
VBB
OUT2B
SENSE2
OUT2A
NC
VCP 31
Terminal List Table
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
–
Name
NC
OUT1A
SENSE1
OUT1B
VBB
OUT2B
SENSE2
OUT2A
NC
PHASE3
VDD
VREF1
VREF2
VREF3
NC
GND
PHASE2
PHASE1
NC
OUT3A
SENSE3
OUT3B
VBB
OUT3B
SENSE3
OUT3A
MODE
I12
I11
GND
VCP
CP1
CP2
I01
I02
ENABLE
PAD
Description
No Connect
DMOS Full Bridge 1 Output A
Sense Resistor Terminal for Bridge 1
DMOS Full Bridge 1 Output B
Load Supply Voltage
DMOS Full Bridge 2 Output B
Sense Resistor Terminal for Bridge 2
DMOS Full Bridge 2 Output A
No Connect
Control Input
Logic Supply Voltage
Analog Input
Analog Input
Analog Input
No Connect
Ground
Control Input
Control Input
No Connect
DMOS Full Bridge 3 Output A
Sense Resistor Terminal for Bridge 3
DMOS Full Bridge 3 Output B
Load Supply Voltage
DMOS Full Bridge 3 Output A
Sense Resistor Terminal for Bridge 3
DMOS Full Bridge 3 Output B
Control Input
Control Input
Control Input
Ground
Reservoir Capacitor Terminal
Charge Pump Capacitor Terminal
Charge Pump Capacitor Terminal
Control Input
Control Input
Control Input
Exposed pad for enhanced thermal performance. Should
be soldered to the PCB
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
11
A3989
Bipolar Stepper and High Current DC Motor Driver
EV Package, 36 Pin QFN with Exposed Thermal Pad
1.15
6.00 ±0.15
0.30
0.50
36
36
1
2
1
2
A
6.00 ±0.15
D 37X
SEATING
PLANE
0.08 C
4.15
C
5.80
4.15
5.80
0.90 ±0.10
+0.05
0.25 –0.07
0.50
All dimensions nominal, not for tooling use
(reference JEDEC MO-220VJJD-3, except pin count)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
0.55 ±0.20
B
A Terminal #1 mark area
4.15
2
1
36
4.15
B Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
C Reference land pattern layout (reference IPC7351
QFN50P600X600X100-37V1M); All pads a minimum of 0.20 mm from
all adjacent pads; adjust as necessary to meet application process
requirements and PCB layout tolerances; when mounting on a
multilayer PCB, thermal vias at the exposed thermal pad land can
improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
D Coplanarity includes exposed thermal pad and terminals
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
12
A3989
Bipolar Stepper and High Current DC Motor Driver
Revision History
Revision
Revision Date
Rev. 3
May 2, 2011
Description of Revision
Change in Vf
Copyright ©2006-2013, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
13
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