Data Sheet

PBSS305PD
100 V, 2 A PNP low VCEsat (BISS) transistor
Rev. 02 — 8 December 2009
Product data sheet
1. Product profile
1.1 General description
PNP low VCEsat Breakthrough In Small Signal (BISS) transistor in a SOT457 (SC-74)
small Surface-Mounted Device (SMD) plastic package.
NPN complement: PBSS305ND.
1.2 Features
„
„
„
„
„
Low collector-emitter saturation voltage VCEsat
High collector current capability IC and ICM
High collector current gain (hFE) at high IC
High efficiency due to less heat generation
Smaller required Printed-Circuit Board (PCB) area than for conventional transistors
1.3 Applications
„
„
„
„
„
„
High-voltage DC-to-DC conversion
High-voltage MOSFET gate driving
High-voltage motor control
High-voltage power switches (e.g. motors, fans)
Thin Film Transistor (TFT) backlight inverter
Automotive applications
1.4 Quick reference data
Table 1.
Quick reference data
Symbol Parameter
VCEO
collector-emitter voltage
Conditions
open base
[1]
IC
collector current
ICM
peak collector current
single pulse;
tp ≤ 1 ms
RCEsat
collector-emitter
saturation resistance
IC = −2 A;
IB = −200 mA
[1]
Device mounted on a ceramic PCB, Al2O3, standard footprint.
[2]
Pulse test: tp ≤ 300 μs; δ ≤ 0.02.
[2]
Min
Typ
Max
Unit
-
-
−100
V
-
-
−2
A
-
-
−3
A
-
88
125
mΩ
PBSS305PD
NXP Semiconductors
100 V, 2 A PNP low VCEsat (BISS) transistor
2. Pinning information
Table 2.
Pinning
Pin
Description
1
collector
2
collector
3
base
4
emitter
5
collector
6
collector
Simplified outline
6
5
Symbol
4
1, 2, 5, 6
3
1
2
3
4
sym030
3. Ordering information
Table 3.
Ordering information
Type number
PBSS305PD
Package
Name
Description
Version
SC-74
plastic surface-mounted package (TSOP6); 6 leads
SOT457
4. Marking
Table 4.
Marking codes
Type number
Marking code
PBSS305PD
AK
PBSS305PD_2
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 8 December 2009
2 of 15
PBSS305PD
NXP Semiconductors
100 V, 2 A PNP low VCEsat (BISS) transistor
5. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VCBO
collector-base voltage
open emitter
-
−100
V
VCEO
collector-emitter voltage
open base
-
−100
V
VEBO
emitter-base voltage
open collector
collector current
IC
ICM
peak collector current
IB
base current
IBM
peak base current
single pulse;
tp ≤ 1 ms
Ptot
total power dissipation
Tamb ≤ 25 °C
−5
V
-
−1
A
[2]
-
−2
A
-
−3
A
-
−800
mA
-
−2
A
[1]
-
360
mW
[3]
-
600
mW
[4]
-
750
mW
[2]
-
1.1
W
[1][5]
-
2.5
W
single pulse;
tp ≤ 1 ms
Tj
junction temperature
-
150
°C
Tamb
ambient temperature
−65
+150
°C
Tstg
storage temperature
−65
+150
°C
[1]
Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint.
[2]
Device mounted on a ceramic PCB, Al2O3, standard footprint.
[3]
Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for collector 1 cm2.
[4]
Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for collector 6 cm2.
[5]
Pulse test: tp ≤ 10 ms; δ ≤ 10 %.
PBSS305PD_2
Product data sheet
[1]
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 8 December 2009
3 of 15
PBSS305PD
NXP Semiconductors
100 V, 2 A PNP low VCEsat (BISS) transistor
006aaa270
1600
Ptot
(mW)
1200
(1)
800
(2)
(3)
(4)
400
0
−75
−25
25
75
125
175
Tamb (°C)
(1) Ceramic PCB, Al2O3, standard footprint
(2) FR4 PCB, mounting pad for collector 6 cm2
(3) FR4 PCB, mounting pad for collector 1 cm2
(4) FR4 PCB, standard footprint
Fig 1.
Power derating curves
6. Thermal characteristics
Table 6.
Thermal characteristics
Symbol
Parameter
Rth(j-a)
Rth(j-sp)
Conditions
thermal resistance from
junction to ambient
in free air
thermal resistance from
junction to solder point
Typ
Max
Unit
-
-
350
K/W
[2]
-
-
208
K/W
[3]
-
-
167
K/W
[4]
-
-
113
K/W
[1][5]
-
-
50
K/W
-
-
45
K/W
[1]
Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint.
[2]
Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for collector 1 cm2.
[3]
Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for collector 6 cm2.
[4]
Device mounted on a ceramic PCB, Al2O3, standard footprint.
[5]
Pulse test: tp ≤ 10 ms; δ ≤ 10 %.
PBSS305PD_2
Product data sheet
Min
[1]
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 8 December 2009
4 of 15
PBSS305PD
NXP Semiconductors
100 V, 2 A PNP low VCEsat (BISS) transistor
006aaa271
103
Zth(j-a)
(K/W)
102
duty cycle =
1
0.75
0.5
0.33
0.2
0.1
0.05
10
0.02
0.01
1
0
10−1
10−5
10−4
10−3
10−2
10−1
1
10
102
103
tp (s)
FR4 PCB, standard footprint
Fig 2.
Transient thermal impedance from junction to ambient as a function of pulse duration; typical values
006aaa272
103
Zth(j-a)
(K/W)
102
duty cycle =
1
0.75
0.5
0.33
0.2
0.1
10
0.05
0.02
0.01
1
0
10−1
10−5
10−4
10−3
10−2
10−1
1
10
102
103
tp (s)
FR4 PCB, mounting pad for collector 1 cm2
Fig 3.
Transient thermal impedance from junction to ambient as a function of pulse duration; typical values
PBSS305PD_2
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 8 December 2009
5 of 15
PBSS305PD
NXP Semiconductors
100 V, 2 A PNP low VCEsat (BISS) transistor
006aaa273
103
Zth(j-a)
(K/W)
102
duty cycle =
1
0.75
0.5
0.33
0.2
0.1
10
0.05
0.02
0.01
1
0
10−1
10−5
10−4
10−3
10−2
10−1
1
10
102
103
tp (s)
FR4 PCB, mounting pad for collector 6 cm2
Fig 4.
Transient thermal impedance from junction to ambient as a function of pulse duration; typical values
006aaa751
103
Zth(j-a)
(K/W)
102
duty cycle =
1
0.75
0.5
0.33
0.2
0.1
10
0.05
0.02
0.01
1
0
10−1
10−5
10−4
10−3
10−2
10−1
1
10
102
103
tp (s)
Ceramic PCB, Al2O3, standard footprint
Fig 5.
Transient thermal impedance from junction to ambient as a function of pulse duration; typical values
PBSS305PD_2
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 8 December 2009
6 of 15
PBSS305PD
NXP Semiconductors
100 V, 2 A PNP low VCEsat (BISS) transistor
7. Characteristics
Table 7.
Characteristics
Tamb = 25 °C unless otherwise specified.
Symbol Parameter
ICBO
Conditions
Min
Typ
Max
Unit
collector-base cut-off VCB = −100 V; IE = 0 A
current
VCB = −100 V; IE = 0 A;
Tj = 150 °C
-
-
−100
nA
-
-
−50
μA
ICES
collector-emitter
cut-off current
VCE = −80 V; VBE = 0 V
-
-
−100
nA
IEBO
emitter-base cut-off
current
VEB = −5 V; IC = 0 A
-
-
−100
nA
hFE
DC current gain
VCE = −2 V; IC = −500 mA
VCEsat
collector-emitter
saturation voltage
175
275
-
VCE = −2 V; IC = −1 A
[1]
145
225
-
VCE = −2 V; IC = −2 A
[1]
55
75
-
VCE = −2 V; IC = −3 A
[1]
20
30
-
-
−65
−90
IC = −500 mA; IB = −50 mA
IC = −1 A; IB = −50 mA
-
−130
−185
mV
IC = −2 A; IB = −200 mA
[1]
-
−175
−250
mV
IC = −3 A; IB = −300 mA
[1]
-
−275
−395
mV
RCEsat
collector-emitter
IC = −2 A; IB = −200 mA
saturation resistance
[1]
-
88
125
mΩ
VBEsat
base-emitter
saturation voltage
-
−0.80
−0.85
V
-
−0.82
−0.88
V
-
−0.84
−0.90
V
IC = −500 mA; IB = −50 mA
IC = −1 A; IB = −50 mA
IC = −1 A; IB = −100 mA
[1]
IC = −3 A; IB = −300 mA
[1]
-
−0.95
−1.01
V
VBEon
base-emitter turn-on
voltage
VCE = −2 V; IC = −2 A
-
−0.83
−1.00
V
td
delay time
VCC = −9.2 V; IC = −2 A;
IBon = −0.1 A; IBoff = 0.1 A
-
13
-
ns
tr
rise time
-
197
-
ns
ton
turn-on time
-
210
-
ns
ts
storage time
-
169
-
ns
tf
fall time
-
197
-
ns
toff
turn-off time
-
366
-
ns
fT
transition frequency
-
110
-
MHz
Cc
collector capacitance VCB = −10 V; IE = ie = 0 A;
f = 1 MHz
-
36
-
pF
[1]
VCE = −10 V; IC = −100 mA;
f = 100 MHz
Pulse test: tp ≤ 300 μs; δ ≤ 0.02.
PBSS305PD_2
Product data sheet
mV
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 8 December 2009
7 of 15
PBSS305PD
NXP Semiconductors
100 V, 2 A PNP low VCEsat (BISS) transistor
006aaa743
600
006aaa744
−6
IB = −750 mA
−675
−600
IC
−525
(A)
−450
−375
−4
−300
hFE
(1)
400
−225
−150
(2)
−75
200
−2
(3)
0
−10−1
−1
−10
−102
0
−103
−104
IC (mA)
0
VCE = −2 V
−0.4
−0.8
−1.2
−1.6
−2.0
VCE (V)
Tamb = 25 °C
(1) Tamb = 100 °C
(2) Tamb = 25 °C
(3) Tamb = −55 °C
Fig 6.
DC current gain as a function of collector
current; typical values
006aaa745
−1.2
VBE
(V)
Fig 7.
Collector current as a function of
collector-emitter voltage; typical values
006aaa746
−1.2
VBEsat
(V)
−0.8
−0.8
(1)
(1)
(2)
(2)
−0.4
0
−10−1
−1
(3)
−0.4
(3)
−10
−102
0
−10−1
−103
−104
IC (mA)
VCE = −2 V
−1
(1) Tamb = −55 °C
(2) Tamb = 25 °C
(2) Tamb = 25 °C
(3) Tamb = 100 °C
(3) Tamb = 100 °C
Base-emitter voltage as a function of collector
current; typical values
Fig 9.
−103
−104
IC (mA)
Base-emitter saturation voltage as a function
of collector current; typical values
PBSS305PD_2
Product data sheet
−102
IC/IB = 20
(1) Tamb = −55 °C
Fig 8.
−10
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 8 December 2009
8 of 15
PBSS305PD
NXP Semiconductors
100 V, 2 A PNP low VCEsat (BISS) transistor
006aaa747
−1
006aaa748
−1
VCEsat
(V)
VCEsat
(V)
(1)
(2)
(3)
−10−1
(1)
−10−1
(2)
(3)
−10−2
−10−1
−1
−10
−102
−103
−104
IC (mA)
−10−2
−10−1
−1
−10
−102
−103
−104
IC (mA)
Tamb = 25 °C
IC/IB = 20
(1) Tamb = 100 °C
(1) IC/IB = 100
(2) Tamb = 25 °C
(2) IC/IB = 50
(3) Tamb = −55 °C
(3) IC/IB = 10
Fig 10. Collector-emitter saturation voltage as a
function of collector current; typical values
006aaa749
103
Fig 11. Collector-emitter saturation voltage as a
function of collector current; typical values
RCEsat
(Ω)
102
102
10
10
(1)
(2)
(1)
(2)
(3)
1
006aaa750
103
RCEsat
(Ω)
1
10−1
(3)
10−1
10−2
−10−1
−1
−10
−102
−103
−104
IC (mA)
10−2
−10−1
−1
−102
−103
−104
IC (mA)
Tamb = 25 °C
IC/IB = 20
(1) Tamb = 100 °C
(1) IC/IB = 100
(2) Tamb = 25 °C
(2) IC/IB = 50
(3) Tamb = −55 °C
(3) IC/IB = 10
Fig 12. Collector-emitter saturation resistance as a
function of collector current; typical values
Fig 13. Collector-emitter saturation resistance as a
function of collector current; typical values
PBSS305PD_2
Product data sheet
−10
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 8 December 2009
9 of 15
PBSS305PD
NXP Semiconductors
100 V, 2 A PNP low VCEsat (BISS) transistor
8. Test information
− IB
input pulse
(idealized waveform)
90 %
− I Bon (100 %)
10 %
− I Boff
output pulse
(idealized waveform)
− IC
90 %
− I C (100 %)
10 %
t
td
ts
tr
t on
tf
t off
006aaa266
Fig 14. BISS transistor switching time definition
VBB
RB
VCC
RC
Vo
(probe)
oscilloscope
450 Ω
(probe)
450 Ω
oscilloscope
R2
VI
DUT
R1
mgd624
VCC = −9.2 V; IC = −2 A; IBon = −0.1 A; IBoff = 0.1 A
Fig 15. Test circuit for switching times
PBSS305PD_2
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 8 December 2009
10 of 15
PBSS305PD
NXP Semiconductors
100 V, 2 A PNP low VCEsat (BISS) transistor
9. Package outline
3.1
2.7
6
3.0
2.5
1.7
1.3
1.1
0.9
5
4
2
3
0.6
0.2
pin 1 index
1
0.40
0.25
0.95
0.26
0.10
1.9
Dimensions in mm
04-11-08
Fig 16. Package outline SOT457 (SC-74)
10. Packing information
Table 8.
Packing methods
The indicated -xxx are the last three digits of the 12NC ordering code.[1]
Type number
Package
Description
Packing quantity
3000
PBSS305PD
[1]
SOT457
4 mm pitch, 8 mm tape and reel; T1
-115
-135
4 mm pitch, 8 mm tape and reel; T2
[3]
-125
-165
For further information and the availability of packing methods, see Section 14.
[2]
T1: normal taping
[3]
T2: reverse taping
PBSS305PD_2
Product data sheet
10000
[2]
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 8 December 2009
11 of 15
PBSS305PD
NXP Semiconductors
100 V, 2 A PNP low VCEsat (BISS) transistor
11. Soldering
3.45
1.95
solder lands
0.95
solder resist
0.45 0.55
3.30 2.825
occupied area
solder paste
1.60
1.70
3.10
3.20
msc422
Dimensions in mm
Fig 17. Reflow soldering footprint SOT457 (SC-74)
5.30
solder lands
5.05
0.45 1.45 4.45
solder resist
occupied area
1.40
msc423
4.30
Dimensions in mm
Fig 18. Wave soldering footprint SOT457 (SC-74)
PBSS305PD_2
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 8 December 2009
12 of 15
PBSS305PD
NXP Semiconductors
100 V, 2 A PNP low VCEsat (BISS) transistor
12. Revision history
Table 9.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PBSS305PD_2
20091208
Product data sheet
-
PBSS305PD_1
Modifications:
PBSS305PD_1
•
This data sheet was changed to reflect the new company name NXP Semiconductors,
including new legal definitions and disclaimers. No changes were made to the technical
content.
•
Figure 5 “Transient thermal impedance from junction to ambient as a function of pulse
duration; typical values”: updated
•
Figure 18 “Wave soldering footprint SOT457 (SC-74)”: updated
20060530
Product data sheet
PBSS305PD_2
Product data sheet
-
-
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 8 December 2009
13 of 15
PBSS305PD
NXP Semiconductors
100 V, 2 A PNP low VCEsat (BISS) transistor
13. Legal information
13.1 Data sheet status
Document status[1][2]
Product status[3]
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
Definition
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
13.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
13.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
13.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
14. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
PBSS305PD_2
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 8 December 2009
14 of 15
PBSS305PD
NXP Semiconductors
100 V, 2 A PNP low VCEsat (BISS) transistor
15. Contents
1
1.1
1.2
1.3
1.4
2
3
4
5
6
7
8
9
10
11
12
13
13.1
13.2
13.3
13.4
14
15
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General description . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . 1
Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Thermal characteristics . . . . . . . . . . . . . . . . . . 4
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Test information . . . . . . . . . . . . . . . . . . . . . . . . 10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
Packing information . . . . . . . . . . . . . . . . . . . . 11
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13
Legal information. . . . . . . . . . . . . . . . . . . . . . . 14
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Contact information. . . . . . . . . . . . . . . . . . . . . 14
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 8 December 2009
Document identifier: PBSS305PD_2