FUJITSU SEMICONDUCTOR CM44-10132-1E CONTROLLER MANUAL 2 F MC-16LX 16-BIT MICROCONTROLLER MB90350 Series HARDWARE MANUAL F2MC-16LX 16-BIT MICROCONTROLLER MB90350 Series HARDWARE MANUAL FUJITSU LIMITED PREFACE ■ Objectives and intended reader Thank you very much for your continued patronage of Fujitsu semiconductor products. The MB90350 series has been developed as a general-purpose version of the F2MC-16LX series, which is an original 16-bit single-chip microcontroller compatible with the Application Specific IC (ASIC). This manual explains the functions and operation of the MB90350 series for designers who actually use the MB90350 series to design products. Please read this manual first. ■ Trademark F2MC is the abbreviation of FUJITSU Flexible Microcontroller. Other system and product names in this manual are trademarks of respective companies or organizations. The symbols ™ and ® are sometimes omitted in this manual. ■ Structure of this preliminary manual CHAPTER 1 "OVERVIEW" The MB90350 Series is a family member of the F2MC-16LX microcontrollers. CHAPTER 2 "CPU" This chapter explains the CPU. CHAPTER 3 "INTERRUPTS" This chapter explains the interrupt functions and operations. CHAPTER 4 "DELAYED INTERRUPTS" This chapter explains the functions and operations of the delayed interrupt. CHAPTER 5 "CLOCKS" This chapter explains the functions and operations of clocks. CHAPTER 6 "RESETS" This chapter describes resets for the MB90350 series. CHAPTER 7 "LOW-POWER CONTROL CIRCUIT" This chapter explains the functions and operations of the low-power control circuits. CHAPTER 8 "MEMORY ACCESS MODES" This chapter explains the functions and operations of the memory access modes. CHAPTER 9 "I/O PORTS" This chapter explains the functions and operations of the I/O ports. CHAPTER 10 "TIMEBASE TIMER" This chapter explains the functions and operations of the timebase timer. i CHAPTER 11 "WATCHDOG TIMER" This chapter explains the functions and operations of the watchdog timer. CHAPTER 12 "16-BIT I/O TIMER" This chapter explains the functions and operations of the 16-bit I/O timer. CHAPTER 13 "16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)" This chapter explains the functions and operations of the 16-bit reload timer (with the event count function). CHAPTER 14 "WATCH TIMER" This chapter explains the functions and operations of the Watch Timer. CHAPTER 15 "8/16-BIT PPG" This chapter explains the 8/16-bit PPG and explains its functions. CHAPTER 16 "DTP/EXTERNAL INTERRUPTS" This chapter explains the functions and operations of the DTP/external interrupts. CHAPTER 17 "8/10-BIT A/D CONVERTER" This chapter explains the functions and operations of the A/D converter. CHAPTER 18 "LIN-UART" This chapter explains the functions and operation of the LIN-UART. CHAPTER 19 "400 kHz I2C INTERFACE" This chapter explains the functions and operation of the I2C interface. CHAPTER 20 "CAN CONTROLLER" This chapter explains the functions and operations of the CAN controller. CHAPTER 21 "ADDRESS MATCH DETECTION FUNCTION" This chapter explains the address match detection function and operation. CHAPTER 22 "ROM MIRRORING MODULE" This chapter explains the ROM mirroring module. CHAPTER 23 "1M-BIT FLASH MEMORY" This chapter explains the functions and operation of the 1M/2M/3M-bit flash memory. CHAPTER 24 "EXAMPLES OF MB90F352/C(S) SERIAL PROGRAMMING CONNECTION" This chapter provides examples of F2MC-16LX MB90F347 serial programming connection. APPENDIX The appendixes provide I/O maps, instructions, and other information. ii • • • • • • The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party' s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. ©2005 FUJITSU LIMITED Printed in Japan iii iv CONTENTS CHAPTER 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 CHAPTER 2 2.1 2.2 2.3 2.4 2.5 2.6 2.6.1 2.6.2 2.6.3 2.6.4 2.7 2.8 2.9 CPU ............................................................................................................ 23 Outline of the CPU ............................................................................................................................ Memory Space .................................................................................................................................. Linear Addressing ............................................................................................................................. Bank Addressing Types .................................................................................................................... Multi-byte Data in Memory Space ..................................................................................................... Registers ........................................................................................................................................... Accumulator (A) ........................................................................................................................... User Stack Pointer (USP) and System Stack Pointer (SSP) ....................................................... Processor Status (PS) ................................................................................................................. Program Counter (PC) ................................................................................................................. Register Bank ................................................................................................................................... Prefix Codes ..................................................................................................................................... Interrupt Disable Instructions ............................................................................................................ CHAPTER 3 3.1 3.2 3.3 3.4 3.5 3.5.1 3.5.2 3.5.3 3.6 3.7 3.7.1 3.7.2 3.8 3.9 3.9.1 3.9.2 OVERVIEW ................................................................................................... 1 Product Overview ............................................................................................................................... 2 Features .............................................................................................................................................. 3 Block Diagram of MB90V340(S) ......................................................................................................... 5 Block Diagram of Flash/Mask ROM version ....................................................................................... 6 Pin Assignment ................................................................................................................................... 7 Package Dimensions .......................................................................................................................... 9 Pin Functions .................................................................................................................................... 10 Input-Output Circuits ......................................................................................................................... 16 Handling Device ................................................................................................................................ 20 24 25 28 29 31 32 35 36 37 40 41 43 46 INTERRUPTS ............................................................................................. 49 Outline of Interrupts .......................................................................................................................... Interrupt Vector ................................................................................................................................. Interrupt Control Registers (ICR) ...................................................................................................... Interrupt Flow .................................................................................................................................... Hardware Interrupts .......................................................................................................................... Hardware Interrupt Operation ...................................................................................................... Occurrence and Release of Hardware Interrupt .......................................................................... Multiple interrupts ........................................................................................................................ Software Interrupts ........................................................................................................................... Extended Intelligent I/O Service (EI2OS) .......................................................................................... Extended Intelligent I/O Service Descriptor (ISD) ....................................................................... EI2OS Status Register (ISCS) ..................................................................................................... Operation Flow of and Procedure for Using the Extended Intelligent I/O Service (EI2OS) .............. µDMAC Interrupt ............................................................................................................................... µDMAC Functions ....................................................................................................................... µDMAC Registers ........................................................................................................................ v 50 55 57 60 62 63 64 66 67 69 71 73 74 77 78 79 3.9.3 DMA Descriptor window register (DDWR) ................................................................................... 85 3.9.4 µDMAC Operation ....................................................................................................................... 92 3.10 Exceptions ........................................................................................................................................ 96 CHAPTER 4 4.1 4.2 4.3 Outline of Delayed Interrupt Module ................................................................................................. 98 Delayed Interrupt Register ................................................................................................................ 99 Delayed Interrupt Operation ........................................................................................................... 100 CHAPTER 5 5.1 5.2 5.3 5.3.1 5.3.2 5.4 5.5 5.6 122 124 126 127 129 132 LOW-POWER CONSUMPTION MODE ................................................... 133 Overview of Low-Power Consumption Mode .................................................................................. Block Diagram of the Low-Power Consumption Control Circuit ..................................................... Low-Power Consumption Mode Control Register (LPMCR) ........................................................... CPU Intermittent Operation Mode .................................................................................................. Standby Mode ................................................................................................................................. Sleep Mode ............................................................................................................................... Timebase Timer Mode ............................................................................................................... Watch Mode .............................................................................................................................. Stop Mode ................................................................................................................................. Status Change Diagram ................................................................................................................. Status of Pins in Standby Mode and during Hold and Reset .......................................................... Usage Notes on Low-Power Consumption Mode ........................................................................... CHAPTER 8 102 105 107 108 112 114 118 119 RESETS .................................................................................................... 121 Resets ............................................................................................................................................. Reset Cause and Oscillation Stabilization Wait Times ................................................................... External Reset Pin .......................................................................................................................... Reset Operation .............................................................................................................................. Reset Cause Bits ............................................................................................................................ Status of Pins in a Reset ................................................................................................................ CHAPTER 7 7.1 7.2 7.3 7.4 7.5 7.5.1 7.5.2 7.5.3 7.5.4 7.6 7.7 7.8 CLOCKS ................................................................................................... 101 Clocks ............................................................................................................................................. Block Diagram of the Clock Generation Block ................................................................................ Clock Selection Registers ............................................................................................................... Clock Selection Register (CKSCR) ........................................................................................... PLL/Subclock Control Register (PSCCR) .................................................................................. Clock Mode ..................................................................................................................................... Oscillation Stabilization Wait Interval .............................................................................................. Connection of an Oscillator or an External Clock to the Microcontroller ......................................... CHAPTER 6 6.1 6.2 6.3 6.4 6.5 6.6 DELAYED INTERRUPT ............................................................................. 97 134 137 140 143 144 146 149 151 153 156 158 163 MEMORY ACCESS MODES .................................................................... 167 8.1 Outline of Memory Access Modes .................................................................................................. 8.1.1 Mode Pins .................................................................................................................................. 8.1.2 Mode Data ................................................................................................................................. 8.1.3 Memory Space in Each Bus Mode ............................................................................................ 8.2 External Memory Access (Bus Pin Control Circuit) ........................................................................ vi 168 169 170 171 173 8.2.1 External Memory Access (External Bus Pin Control Circuit) Registers ..................................... 8.2.2 Automatic Ready Function Selection Register (ARSR) ............................................................. 8.2.3 External Address Output Control Register (HACR) ................................................................... 8.2.4 Bus Control Signal Selection Register (ECSR) ......................................................................... 8.3 External Memory Access Control Signal Operation ........................................................................ 8.3.1 Ready Function ......................................................................................................................... 8.3.2 Hold Function ............................................................................................................................ CHAPTER 9 174 175 177 178 181 183 185 I/O PORTS ................................................................................................ 187 9.1 I/O Ports .......................................................................................................................................... 9.2 I/O Port Registers ........................................................................................................................... 9.2.1 Port Data Register ..................................................................................................................... 9.2.2 Data Direction Register ............................................................................................................. 9.2.3 Pull-up Control Register (PUCR) ............................................................................................... 9.2.4 Analog Input Enable Register .................................................................................................... 9.2.5 Input Level Select Register ........................................................................................................ 188 189 190 192 194 195 196 CHAPTER 10 TIMEBASE TIMER ................................................................................... 199 10.1 10.2 10.3 Outline of Timebase Timer ............................................................................................................. 200 Timebase Timer Control Register ................................................................................................... 201 Operations of Timebase Timer ....................................................................................................... 203 CHAPTER 11 WATCHDOG TIMER ................................................................................ 205 11.1 11.2 Outline of WatchDog Timer ............................................................................................................ 206 Watchdog Timer Operation ............................................................................................................. 209 CHAPTER 12 16-BIT I/O TIMER ..................................................................................... 211 12.1 Outline of 16-Bit I/O Timer .............................................................................................................. 12.2 16-Bit I/O Timer Registers .............................................................................................................. 12.3 16-bit Free-running Timer ............................................................................................................... 12.3.1 Data Register ............................................................................................................................. 12.3.2 Control Status Register ............................................................................................................. 12.3.3 16-bit Free-running Timer Operation ......................................................................................... 12.4 Output Compare ............................................................................................................................. 12.4.1 Output Compare Register .......................................................................................................... 12.4.2 Control Status Register of Output Compare .............................................................................. 12.4.3 16-bit Output Compare Operation ............................................................................................. 12.5 Input Capture .................................................................................................................................. 12.5.1 Input Capture Register Details .................................................................................................. 12.5.2 16-bit Input Capture Operation .................................................................................................. 212 214 216 217 218 221 223 224 225 230 235 236 241 CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) ................ 243 13.1 Outline of 16-Bit Reload Timer (with Event Count Function) .......................................................... 13.2 16-Bit Reload Timer (with Event Count Function) .......................................................................... 13.2.1 Timer Control Status Register (TMCSR) ................................................................................... 13.2.2 Register Layout of 16-bit Timer Register (TMR)/16-bit Reload Register (TMRLR) ................... 13.3 Internal Clock and External Clock Operations of 16-bit Reload Timer ........................................... vii 244 246 247 250 251 13.4 13.5 13.6 Underflow Operation of 16-bit Reload Timer .................................................................................. 253 Output Pin Functions of 16-bit Reload Timer .................................................................................. 254 Counter Operation State ................................................................................................................. 255 CHAPTER 14 WATCH TIMER ........................................................................................ 257 14.1 14.2 14.3 Outline of Watch Timer ................................................................................................................... 258 Watch Timer Control Register (WTC) ............................................................................................. 259 Watch Timer Operation ................................................................................................................... 261 CHAPTER 15 8/16-BIT PPG ........................................................................................... 263 15.1 Outline of 8/16-bit PPG ................................................................................................................... 15.2 Block Diagram of 8/16-bit PPG ....................................................................................................... 15.3 8/16-bit PPG Registers ................................................................................................................... 15.3.1 PPG8 Operation Mode Control Register (PPGC8) .................................................................... 15.3.2 PPG9 Operation Mode Control Register (PPGC9) .................................................................... 15.3.3 PPG8/9 Clock Select Register (PPG89) .................................................................................... 15.3.4 Reload Register (PRLL/PRLH) .................................................................................................. 15.4 Operations of 8/16-bit PPG ............................................................................................................. 15.5 Selecting a Count Clock for 8/16-bit PPG ....................................................................................... 15.6 Controlling Pin Output of 8/16-bit PPG Pulses ............................................................................... 15.7 8/16-bit PPG Interrupts ................................................................................................................... 15.8 Initial Values of 8/16-bit PPG Hardware ......................................................................................... 264 266 268 269 271 273 275 276 278 279 280 281 CHAPTER 16 DTP/EXTERNAL INTERRUPTS .............................................................. 283 16.1 16.2 16.3 16.4 16.5 Outline of DTP/External Interrupts .................................................................................................. DTP/External Interrupt Registers .................................................................................................... Operations of DTP/External Interrupts ............................................................................................ Switching between External Interrupt and DTP Requests .............................................................. Notes on Using DTP/External Interrupts ......................................................................................... 284 286 289 291 292 CHAPTER 17 A/D CONVERTER .................................................................................... 295 17.1 Features of A/D Converter .............................................................................................................. 17.2 Block Diagram of A/D Converter ..................................................................................................... 17.3 Registers for A/D Converter ............................................................................................................ 17.3.1 Control status register (ADCS0) ................................................................................................ 17.3.2 Control status register (ADCS1) ................................................................................................ 17.3.3 Data Register (ADCR0, ADCR1) ............................................................................................... 17.3.4 Setting Register (ADSR0, ADSR1) ............................................................................................ 17.4 Operation of A/D Converter ............................................................................................................ 17.5 Conversion Using EI2OS ................................................................................................................ 17.5.1 Example of activating of EI2OS in single mode ......................................................................... 17.5.2 Example of activating of EI2OS in continuous mode ................................................................. 17.5.3 Example of activating of EI2OS in stop mode ............................................................................ 17.6 Convert-data Protection Function ................................................................................................... 296 298 299 300 302 305 306 310 312 313 315 317 319 CHAPTER 18 LIN-UART ................................................................................................. 321 18.1 Overview of LIN-UART ................................................................................................................... 322 viii 18.2 Configuration of LIN-UART ............................................................................................................. 18.3 LIN-UART Pins ............................................................................................................................... 18.4 LIN-UART Registers ....................................................................................................................... 18.4.1 Serial Control Register (SCR) ................................................................................................... 18.4.2 Serial Mode Register (SMR) ...................................................................................................... 18.4.3 Serial Status Register (SSR) ..................................................................................................... 18.4.4 Reception and Transmission Data Register (RDR/TDR) ........................................................... 18.4.5 Extended Status/Control Register (ESCR) ................................................................................ 18.4.6 Extended Communication Control Register (ECCR) ................................................................. 18.4.7 Baud Rate/Reload Counter Register 0 and 1 (BGR0/1) ............................................................ 18.5 LIN-UART Interrupts ....................................................................................................................... 18.5.1 Reception Interrupt Generation and Flag Set Timing ................................................................ 18.5.2 Transmission Interrupt Generation and Flag Set Timing ........................................................... 18.6 LIN-UART Baud Rates ................................................................................................................... 18.6.1 Setting the Baud Rate ............................................................................................................... 18.6.2 Restarting the Reload Counter .................................................................................................. 18.7 Operation of LIN-UART .................................................................................................................. 18.7.1 Operation in Asynchronous Mode (Op. Modes 0 and 1) ........................................................... 18.7.2 Operation in Synchronous Mode (Operation Mode 2) ............................................................... 18.7.3 Operation with LIN Function (Operation Mode 3) ...................................................................... 18.7.4 Direct Access to Serial Pins ...................................................................................................... 18.7.5 Bidirectional Communication Function (Normal Mode) ............................................................. 18.7.6 Master-Slave Communication Function (Multiprocessor Mode) ................................................ 18.7.7 LIN Communication Function .................................................................................................... 18.7.8 Sample Flowcharts for UART in LIN communication (Operation Mode 3) ................................ 18.8 Notes on Using LIN-UART .............................................................................................................. 325 329 330 331 333 335 337 339 341 343 344 347 348 350 352 355 357 359 361 364 367 368 370 373 374 376 CHAPTER 19 400 kHz I2C INTERFACE ......................................................................... 379 19.1 I2C Interface Overview .................................................................................................................... 19.2 I2C Interface Registers ................................................................................................................... 19.2.1 Bus Status Register (IBSR) ....................................................................................................... 19.2.2 Bus Control Register (IBCR) ..................................................................................................... 19.2.3 Ten Bit Slave Address Register (ITBA) ..................................................................................... 19.2.4 Ten Bit Address Mask Register (ITMK) ..................................................................................... 19.2.5 Seven Bit Slave Address Register (ISBA) ................................................................................. 19.2.6 Data Register (IDAR) ................................................................................................................. 19.2.7 Clock Control Register (ICCR) .................................................................................................. 19.3 I2C Interface Operation ................................................................................................................... 19.4 Programming Flow Charts .............................................................................................................. 380 382 384 387 394 395 397 399 400 403 406 CHAPTER 20 CAN CONTROLLER ................................................................................ 409 20.1 20.2 20.3 20.4 20.5 20.6 Features of CAN Controller ............................................................................................................ Block Diagram of CAN Controller ................................................................................................... List of Overall Control Registers ..................................................................................................... List of Message Buffers (ID Registers) ........................................................................................... List of Message Buffers (DLC Registers and Data Registers) ........................................................ Classifying the CAN Controller Registers ....................................................................................... ix 410 411 412 414 417 420 20.6.1 Control Status Register (CSR) .................................................................................................. 20.6.2 Bus Operation Stop Bit (HALT = 1) ........................................................................................... 20.6.3 Last Event Indicator Register (LEIR) ......................................................................................... 20.6.4 Receive and Transmit Error Counters (RTEC) .......................................................................... 20.6.5 Bit Timing Register (BTR) .......................................................................................................... 20.6.6 Message Buffer Valid Register (BVALR) ................................................................................... 20.6.7 IDE register (IDER) .................................................................................................................... 20.6.8 Transmission Request Register (TREQR) ................................................................................ 20.6.9 Transmission RTR Register (TRTRR) ....................................................................................... 20.6.10 Remote Frame Receiving Wait Register (RFWTR) ................................................................... 20.6.11 Transmission Cancel Register (TCANR) ................................................................................... 20.6.12 Transmission Complete Register (TCR) .................................................................................... 20.6.13 Transmission Interrupt Enable Register (TIER) ......................................................................... 20.6.14 Reception Complete Register (RCR) ........................................................................................ 20.6.15 Remote Request Receiving Register (RRTRR) ........................................................................ 20.6.16 Receive Overrun Register (ROVRR) ......................................................................................... 20.6.17 Reception Interrupt Enable Register (RIER) ............................................................................. 20.6.18 Acceptance Mask Select Register (AMSR) ............................................................................... 20.6.19 Acceptance Mask Registers 0 and 1 (AMR0 and AMR1) .......................................................... 20.6.20 Message Buffers ........................................................................................................................ 20.6.21 ID Register x (x = 0 to 15) (IDRx) .............................................................................................. 20.6.22 DLC Register x (x = 0 to 15) (DLCRx) ....................................................................................... 20.6.23 Data Register x (x = 0 to 15) (DTRx) ......................................................................................... 20.7 Transmission of CAN Controller ..................................................................................................... 20.8 Reception of CAN Controller .......................................................................................................... 20.9 Reception Flowchart of CAN Controller .......................................................................................... 20.10 How to Use the CAN Controller ...................................................................................................... 20.11 Procedure for Transmission by Message Buffer (x) ....................................................................... 20.12 Procedure for Reception by Message Buffer (x) ............................................................................. 20.13 Setting Configuration of Multi-level Message Buffer ....................................................................... 20.14 Setting the CAN Direct Mode Register ........................................................................................... 20.15 Precautions when Using CAN Controller ........................................................................................ 421 426 427 429 430 433 434 435 436 437 438 439 440 441 442 443 444 445 447 449 450 452 453 455 457 459 460 461 463 465 467 468 CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION ......................................... 469 21.1 21.2 21.3 21.4 Outline of the Address Match Detection Function .......................................................................... Registers of the Address Match Detection Function ....................................................................... Operation of the Address Match Detection Function ...................................................................... Example of the Address Match Detection Function ........................................................................ 470 471 473 474 CHAPTER 22 ROM MIRRORING MODULE ................................................................... 477 22.1 22.2 Outline of ROM Mirroring Module ................................................................................................... 478 ROM Mirroring Register (ROMM) ................................................................................................... 479 CHAPTER 23 1M-BIT FLASH MEMORY ........................................................................ 481 23.1 23.2 23.3 Overview of 1M-bit Flash Memory .................................................................................................. 482 Block Diagram of the Entire Flash Memory and Sector Configuration of the Flash Memory .......... 483 Write/Erase Modes ......................................................................................................................... 485 x 23.4 Flash Memory Control Status Register (FMCS) ............................................................................. 23.5 Starting the Flash Memory Automatic Algorithm ............................................................................ 23.6 Confirming the Automatic Algorithm Execution State ..................................................................... 23.6.1 Data Polling Flag (DQ7) ............................................................................................................ 23.6.2 Toggle Bit Flag (DQ6) ................................................................................................................ 23.6.3 Timing Limit Exceeded Flag (DQ5) ........................................................................................... 23.6.4 Sector Erase Timer Flag (DQ3) ................................................................................................. 23.6.5 Toggle Bit-2 Flag (DQ2) ............................................................................................................ 23.7 Detailed Explanation of Writing to and Erasing Flash Memory ....................................................... 23.7.1 Setting The Read/Reset State ................................................................................................... 23.7.2 Writing Data ............................................................................................................................... 23.7.3 Erasing All Data (Erasing Chips) ............................................................................................... 23.7.4 Erasing Optional Data (Erasing Sectors) ................................................................................... 23.7.5 Suspending Sector Erase .......................................................................................................... 23.7.6 Restarting Sector Erase ............................................................................................................ 23.8 Notes on using 1M-bit Flash Memory ............................................................................................. 23.9 Flash Security Feature .................................................................................................................... 23.10 Example of Programming 1M-bit Flash Memory ............................................................................ 487 489 491 493 495 496 497 498 500 501 502 504 505 507 508 509 511 512 CHAPTER 24 EXAMPLES OF MB90F352/C(S)PROGRAMMINGCONNECTION ......... 517 24.1 24.2 24.3 24.4 24.5 Basic Configuration of MB90F352/C(S) Serial Programming Connection ...................................... 518 Example of Serial Programming Connection (User Power Supply Used) ...................................... 521 Example of Serial Programming Connection (Power Supplied from the Programmer) .................. 523 Example of Minimum Connection to the Flash Microcomputer Programmer (User Power Supply Used) ......................................................................................................................................................... 525 Example of Minimum Connection to the Flash Microcomputer Programmer (Power Supplied from the Programmer) ......................................................................................... 527 APPENDIX ......................................................................................................................... 529 APPENDIX A I/O Maps .............................................................................................................................. APPENDIX B Instructions ........................................................................................................................... B.1 Instruction Types ............................................................................................................................ B.2 Addressing ..................................................................................................................................... B.3 Direct Addressing ........................................................................................................................... B.4 Indirect Addressing ........................................................................................................................ B.5 Execution Cycle Count ................................................................................................................... B.6 Effective address field .................................................................................................................... B.7 How to Read the Instruction List .................................................................................................... B.8 F2MC-16LX Instruction List ............................................................................................................ B.9 Instruction Map ............................................................................................................................... APPENDIX C Timing Diagrams in Flash Memory Mode ............................................................................ APPENDIX D List of Interrupt Vectors ........................................................................................................ 530 542 543 544 546 552 559 562 563 566 580 602 610 INDEX................................................................................................................................... 615 xi xii CHAPTER 1 OVERVIEW The MB90350 Series is a family member of the F2MC16LX micro controllers. 1.1 Product Overview 1.2 Features 1.3 Block Diagram of MB90V340(S) 1.4 Block Diagram of Flash/Mask ROM version 1.5 Pin Assignment 1.6 Package Dimensions 1.7 Pin Functions 1.8 Input-Output Circuits 1.9 Handling Device 1 CHAPTER 1 OVERVIEW 1.1 Product Overview Table 1.1-1 provides a quick outlook of the MB90350 Series. ■ Product overview Table 1.1-1 Product overview Features MB90V340(S) MB90F352/C(S) MB90352/C(S) Product type Evaluation sample Flash version Mask ROM version CPU F2MC-16LX CPU On-chip PLL clock multiplier (x1, x2, x3, x4, x6, 1/2 when PLL stops) Minimum instruction execution time: 42 ns (4 MHz osc. PLL x 6) System clock 2 ROM memory External RAM 30 Kbytes Technology 0.35µm CMOS with on-chip voltage regulator for internal power supply Package PGA-299 Boot-block, Flash memory 128K bytes Boot-block, Mask ROM 128K bytes 4K bytes 4K bytes 0.35µm CMOS with on-chip voltage 0.35µm CMOS with on-chip voltage regulator for internal power supply + Flash regulator for internal power supply memory with on-chip charge pump for programming voltage LQFP-64 CHAPTER 1 OVERVIEW 1.2 Features Table 1.2-1 lists the features of the MB90350 series. ■ Features Table 1.2-1 MB90350 features (1/2) Part Number Parameter MB90F352/C(S), MB90352/C(S) MB90V340(S) 2 channels UART I2C (400Kbit/s) 3 channels Wide range of baud rate settings using a dedicated reload timer Special synchronous options for adapting to different synchronous serial protocols LIN functionality working either as master or slave LIN device devices with ’C’-suffix: 1ch devices without ’C’-suffix: -- 1 channels 15 input channels 15 input channels A/D Converter 10-bit or 8-bit resolution Conversion time: Minimum 3 µs include sample time (per one channel) 16-bit Reload Timer (4 channels) Operation clock frequency: fsys/21, fsys/23, fsys/25 (fsys = System clock frequency) Supports External Event Count function 16-bit I/O Timer (2 channels) Signals an interrupt when overflowing Supports Timer Clear when a match with Output Compare (Channel 4) Operation clock freq.: fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27 (fsys = System clock freq.) I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1 I/O Timer 1 (clock input FRCK1) corresponds to ICU 4/5/6/7, OCU 4/5/6/7 16-bit Output Compare (4 channels) Signals an interrupt when a match with 16-bit I/O Timer 16-bit compare registers. A pair of compare registers can be used to generate an output signal. 16-bit Input Capture (6 channels) Rising edge, falling edge or rising & falling edge sensitive Signals an interrupt upon external event 6 channels/16-bit 10 channels/8-bit 8/16-bit Programmable Pulse Generator 8 channels/16-bit 12 channels/8-bit Supports 8-bit and 16-bit operation modes Twelve 8-bit reload counters Twelve 8-bit reload registers for L pulse width Twelve 8-bit reload registers for H pulse width A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as 8-bit prescaler plus 8-bit reload counter Operation clock freq.: fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 102.4µs fosc=@5MHz (fsys = System clock frequency, fosc = Oscillation clock frequency) 3 CHAPTER 1 OVERVIEW Table 1.2-1 MB90350 features (2/2) Part Number Parameter MB90F352/C(S), MB90352/C(S) MB90V340(S) 1 ch CAN Interface External Interrupt (16 channels) D/A converter Up to 100kHz Subclock for low power operation 2 channels Conforms to CAN Specification Version 2.0 Part A and B Automatic re-transmission in case of error Automatic transmission responding to Remote Frame Prioritized 16 message buffers for data and ID’s Supports multiple messages Flexible configuration of acceptance filtering: Full bit compare / Full bit mask / Two partial bit masks Supports up to 1Mbps Can be programmed edge sensitive or level sensitive - 1 channels devices without ’S’-suffix: yes devices with ’S’-suffix: -- I/O Ports Virtually all external pins can be used as general purpose I/O All push-pull outputs Bit-wise programmable as input/output or peripheral signal Programmable in groups of 8 as CMOS / Automotive inputs (default) TTL input level programmable for external bus (default for external reset vector fetch) Flash Memory Supports automatic programming, Embedded AlgorithmTM* Write/Erase/Erase-Suspend/Resume commands A flag indicating completion of the algorithm Number of erase cycles: 10,000 times Data retention time: 10 years Boot block configuration Erase can be performed on each block Block protection with external programming voltage Flash Security Feature for protecting the content of the Flash *: Embedded Algorithm is a trade mark of Advanced Micro Devices Inc. 4 CHAPTER 1 OVERVIEW 1.3 Block Diagram of MB90V340(S) Figure 1.3-1 shows a block diagram of the MB90V340(S). ■ Block diagram of MB90V340(S) Figure 1.3-1 Block diagram of MB90V340(S) X0,X1 X0A,X1A * RST Clock Controller 16LX CPU IO Timer 0 RAM 30 K Input Capture 6 ch Output Compare 4 ch SOT4 to SOT2 SCK4 to SCK2 SIN4 to SIN2 Prescaler 3 ch IO Timer 1 UART 3 ch CAN Controller 2 ch 16-bit Reload AVSS Timer 4 ch AN14 to AN0 AVRH 10-bit ADC 15 ch ADTG FMC-16 Bus AVCC FRCK0 IN7 to IN4, IN1 to IN0 OUT7 to OUT4 FRCK1 RX2 to RX1 TX2 to TX1 TIN3, TIN1 TOT3, TOT1 AD15 to AD00 A21 to A16 DA00 10-bit DAC 1 ch ALE RD External Bus Interface WRL WRH HRQ PPGF to PPG8, PPG6, PPG4, PPG2, PPG0 8/16-bit PPG 12/8 ch HAK RDY CLK SDA0 I2C SCL0 Interface 1 ch External Interrupt INT15 to INT8 (INT11R to INT9R) DMAC * : Only for MB90V340 (without ‘S’ Suffix ) 5 CHAPTER 1 OVERVIEW 1.4 Block Diagram of Flash/Mask ROM version Figure 1.4-1 shows a block diagram of Flash/Mask ROM version. ■ Block diagram of Flash/Mask ROM version Figure 1.4-1 Block diagram of Flash/Mask ROM version X0,X1 X0A,X1A *1 RST Clock Controller 16LX CPU IO Timer 0 RAM 4K Input Capture 6 ch ROM/Flash 128 K Output Compare 4 ch Prescaler 2 ch SOT3, SOT2 SCK3, SCK2 SIN3, SIN2 IO Timer 1 CAN Controller 1 ch UART 2 ch 16-bit Reload Timer 4 ch AN14 to AN0 10-bit ADC 15 ch AVRH FMC-16 Bus AVCC AVSS FRCK0 IN7 to IN4, IN1, IN0 OUT7 to OUT4 FRCK1 RX1 TX1 TIN3, TIN1 TOT3, TOT1 AD15 to AD00 A21 to A16 ADTG ALE RD PPGF to PPG8 PPG6, PPG4 8/16-bit PPG 10/6 ch External Bus Interface WRL WRH HRQ HAK SDA0*2 SCL0*2 I2C Interface 1 ch DMAC *1 : Only for devices without ‘S’ Suffix *2 : Only for devices with ‘C’ Suffix 6 RDY CLK External Interrupt INT15 to INT8 (INT11R to INT9R) CHAPTER 1 OVERVIEW 1.5 Pin Assignment This chapter shows the pin assignments for the MB90350 series. ■ Pin assignments (LQFP-64) Figure 1.5-1 shows the Pin assignment without suffix-C. Figure 1.5-1 Pin assignment without suffix-C P11/AD09/TOT1 P12/AD10/SIN3/INT11R P13/AD11/SOT3 P14/AD12/SCK3 P15/AD13 P16/AD14 P17/AD15 P20/A16/PPG9(8) P21/A17/PPGB(A) P22/A18/PPGD(C) P23/A19/PPGF(E) P24/A20/IN0 RST X1 X0 Vss (TOP VIEW) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Vcc 49 32 P10/AD08/TIN1 C 50 31 P07/AD07/INT15 P25/A21/IN1/ADTG 51 30 P06/AD06/INT14 P44/FRCK0 52 29 P05/AD05/INT13 P45//FRCK1 53 28 P04/AD04/INT12 P30/ALE/IN4 54 27 P03/AD03/INT11 P31/RD/IN5 55 26 P02/AD02/INT10 P32/WRL/WR/INT10R 56 25 P01/AD01/INT9 P33/WRH 57 24 P00/AD00/INT8 P34/HRQ/OUT4 58 23 MD0 P35/HAK/OUT5 59 22 MD1 P36/RDY/OUT6 60 21 MD2 P37/CLK/OUT7 61 20 P41/X1A * P60/AN0 62 19 P40/X0A * P61/AN1 63 18 Vss AVcc 64 17 P43/IN7/TX1 LQFP - 64 P42/IN6/RX1/INT9R P56/AN14 P55/AN13 P54/AN12/TOT3 P53/AN11/TIN3 P52/AN10/SCK2 P51/AN9/SOT2 P50/AN8/SIN2 P67/AN7/PPGE(F) P66/AN6/PPGC(D) P65/AN5/PPGA(B) P64/AN4/PPG8(9) P63/AN3/PPG6(7) P62/AN2/PPG4(5) AVss AVRH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (FPT-64P-M09) *: MB90F352/352 : X0A, X1A MB90F352S/352S : P40, P41 7 CHAPTER 1 OVERVIEW Figure 1.5-2 shows the Pin assignment with suffix-C Figure 1.5-2 Pin assignment with suffix-C P11/AD09/TOT1 P12/AD10/SIN3/INT11R P13/AD11/SOT3 P14/AD12/SCK3 P15/AD13 P16/AD14 P17/AD15 P20/A16/PPG9(8) P21/A17/PPGB(A) P22/A18/PPGD(C) P23/A19/PPGF(E) P24/A20/IN0 RST X1 X0 Vss (TOP VIEW) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Vcc 49 32 P10/AD08/TIN1 C 50 31 P07/AD07/INT15 P25/A21/IN1/ADTG 51 30 P06/AD06/INT14 P44/SDA0/FRCK0 52 29 P05/AD05/INT13 P45/SCL0/FRCK1 53 28 P04/AD04/INT12 P30/ALE/IN4 54 27 P03/AD03/INT11 P31/RD/IN5 55 26 P02/AD02/INT10 P32/WRL/WR/INT10R 56 25 P01/AD01/INT9 P33/WRH 57 24 P00/AD00/INT8 P34/HRQ/OUT4 58 23 MD0 P35/HAK/OUT5 59 22 MD1 P36/RDY/OUT6 60 21 MD2 P37/CLK/OUT7 61 20 P41/X1A * P60/AN0 62 19 P40/X0A * P61/AN1 63 18 Vss AVcc 64 17 P43/IN7/TX1 LQFP - 64 (FPT-64P-M09) *: 8 MB90F352C/352C : X0A, X1A MB90F352CS/352CS : P40, P41 P42/IN6/RX1/INT9R P56/AN14 P55/AN13 P54/AN12/TOT3 P53/AN11/TIN3 P52/AN10/SCK2 P51/AN9/SOT2 P50/AN8/SIN2 P67/AN7/PPGE(F) P66/AN6/PPGC(D) P65/AN5/PPGA(B) P64/AN4/PPG8(9) P63/AN3/PPG6(7) P62/AN2/PPG4(5) AVss AVRH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CHAPTER 1 OVERVIEW 1.6 Package Dimensions Figure 1.6-1 shows the package dimensions of the MB90350 series. Note that the dimensions show below are reference dimensions. For formal dimensions of each package, contact us. ■ Package dimensions Figure 1.6-1 FPT-64P-M09 Package dimensions 64-pin plastic LQFP Lead pitch 0.65 mm Package width ⋅ package length 12 ⋅ 12 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm MAX Code (Reference) P-LQFP64-12⋅ 12-0.65 (FPT-64P-M09) 64-pin plastic LQFP (FPT-64P-M09) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 14.00±0.20(.551±.008)SQ * 12.00±0.10(.472±.004)SQ 48 0.145±0.055 (.0057±.0022) 33 49 32 0.10(.004) Details of "A" part +0.20 1.50 –0.10 +.008 .059 –.004 (Mounting height) 0.25(.010) INDEX 0~8 64 17 1 1 0.65(.026) C 2003 FUJITSU LIMITED F64018S-c-3-5 "A" 6 0.32±0.05 (.013±.002) 0.13(.005) 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.10±0.10 (.004±.004) (Stand off) M Dimensions in mm (inches). Note: The values in parentheses are reference values. 9 CHAPTER 1 OVERVIEW 1.7 Pin Functions Table 1.7-1 describes the pin functions of the MB90350 series. ■ Pin functions Table 1.7-1 Pin description (1/6) Pin No. Pin name Circuit type Function LQFP64* 46 X1 47 X0 45 RST E Reset input pin. 3 to 8 P62 to P67 I General purpose I/O ports. 9 10 11 12 13 14, 15 Oscillation output pin. Oscillation input pin. AN2 to AN7 Analog input pins for A/D converter. PPG4, 6, 8, A, C, E Output pins for PPGs. P50 O General purpose I/O port. AN8 Analog input pin for A/D converter. SIN2 Serial data input pin for UART2. P51 I General purpose I/O port. AN9 Analog input pin for A/D converter. SOT2 Serial data output pin for UART2. P52 I General purpose I/O port. AN10 Analog input pin for A/D converter. SCK2 Serial data output pin for UART2. P53 I General purpose I/O port. AN11 Analog input pin for A/D converter. TIN3 Event input pin for reload timer3. P54 I General purpose I/O port. AN12 Analog input pin for A/D converter. TOT3 Output pin for reload timer3. P55, P56 AN13, AN14 10 A I General purpose I/O ports. Analog input pins for A/D converter. CHAPTER 1 OVERVIEW Table 1.7-1 Pin description (2/6) Pin No. Pin name Circuit type Function LQFP64* 16 17 19, 20 24 to 31 32 33 34 P42 F General purpose I/O port. IN6 Data sample input pin for input capture ICU6. RX1 RX input pin for CAN1. INT9R External interrupt request input pin for INT9. P43 F General purpose I/O port. IN7 Data sample input pin for input capture ICU7. TX1 TX output pin for CAN1. P40, P41 F General purpose I/O ports (devices with S-suffix) . X0A, X1A B Oscillation input pins for sub clock (devices without S-suffix) . P00 to P07 G General purpose I/O ports.The register can be set to select whether to use a pull-up resistor.This function is enabled in single-chip mode. AD00 to AD07 Input/output pins of external address data bus lower 8 bit. This function is enabled when the external bus is enabled. INT8 to INT15 External interrupt request input pins for INT8 to INT15. P10 G General purpose I/O port.The register can be set to select whether to use a pull-up resistor.This function is enabled in single-chip mode. AD08 Input/output pin for external bus address data bus bit 8. This function is enabled when external bus is enabled. TIN1 Event input pin for reload timer1. P11 G General purpose I/O.The register can be set to select whether to use a pull-up resistor.This function is enabled in single-chip mode. AD09 Input/output pin for external bus address data bus bit 9. This function is enabled when external bus is enabled. TOT1 Output pin for reload timer1. P12 N General purpose I/O port. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. AD10 Input/output pin for external bus address data bus bit 10. This function is enabled when external bus is enabled. SIN3 Serial data input pin for UART3. INT11R External interrupt request input pin for INT11 11 CHAPTER 1 OVERVIEW Table 1.7-1 Pin description (3/6) Pin No. Pin name Circuit type Function LQFP64* 35 36 37 P13 G AD11 Input/output pin for external bus address data bus bit 11. This function is enabled when external bus is enabled. SOT3 Serial data output pin for UART3. P14 G Input/output pin for external bus address data bus bit 12. This function is enabled when external bus is enabled. SCK3 Clock input/output pin for UART3. P15 N P16 P17 G 12 P20 to P23 General purpose I/O port. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. Input/output pin for external bus address data bus bit 14. This function is enabled when external bus is enabled. G AD15 40 to 43 General purpose I/O port. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. Input/output pin for external bus address data bus bit 13. This function is enabled when external bus is enabled. AD14 39 General purpose I/O port. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. AD12 AD13 38 General purpose I/O port. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. General purpose I/O port. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. Input/output pin for external bus address data bus bit 15. This function is enabled when external bus is enabled. G General purpose I/O ports. The register can be set to select whether to use a pull-up resistor. In external bus mode, the pin is enabled as a generalpurpose I/O port when the corresponding bit in the external address output control register (HACR) is 1. A16 to A19 Output pins for A16 to A19 of the external address bus. When the corresponding bit in the external address output control register (HACR) is 0, the pins are enabled as high address output pins A16 to A19. PPG9, PPGB, PPGD, PPGF Output pins for PPGs. CHAPTER 1 OVERVIEW Table 1.7-1 Pin description (4/6) Pin No. Pin name Circuit type Function LQFP64* 44 51 52 53 54 P24 G General purpose I/O port. The register can be set to select whether to use a pull-up resistor. In external bus mode, the pin is enabled as a generalpurpose I/O port when the corresponding bit in the external address output control register (HACR) is 1. A20 Output pins for A20 of the external address bus. When the corresponding bit in the external address output control register (HACR) is 0, the pin is enabled as high address output pins A20. IN0 Data sample input pin for input capture ICU0. P25 G General purpose I/O port. The register can be set to select whether to use a pull-up resistor. In external bus mode, the pin is enabled as a generalpurpose I/O port when the corresponding bit in the external address output control register (HACR) is 1. A21 Output pin for A21 of the external address bus. When the corresponding bit in the external address output control register (HACR) is 0, the pin is enabled as high address output pin A21. IN1 Data sample input pin for input capture ICU1. ADTG Trigger input pin for A/D converter. P44 H General purpose I/O port SDA0 Serial data I/O pin for I2C 0 (devices with C-suffix) FRCK0 Input pin for the 16-bit I/O Timer 0 P45 H General purpose I/O port. SCL0 Serial clock I/O pin for I2C 0 (devices with C-suffix) FRCK1 Input for the 16-bit I/O Timer 1 P30 G General purpose I/O port. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. ALE Address latch enable output pin. This function is enabled when external bus is enabled. IN4 Data sample input pin for input capture ICU4. 13 CHAPTER 1 OVERVIEW Table 1.7-1 Pin description (5/6) Pin No. Pin name Circuit type Function LQFP64* 55 56 57 P31 G RD Read strobe output pin for data bus. This function is enabled when external bus is enabled. IN5 Data sample input pin for input capture ICU5. P32 G 59 14 General purpose I/O port. The register can be set to select whether to use pull-up resistor. This function is enabled either in single-chip mode or with the WR/WRL pin output disabled. WR/WRL Write strobe output pin for the data bus. This function is enabled when both the external bus and the WR/WRL pin output are enabled. WRL is used to write-strobe 8 lower bits of the data bus in 16-bit access. WR is used to write-strobe 8 bits of the data bus in 8-bit access. INT10R External interrupt request input pin for INT10. P33 G WRH 58 General purpose I/O port. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. P34 General purpose I/O port. The register can be set to select whether to use a pull-up resistor. This function is enabled either in single-chip mode or with the WRH pin output disabled. Write strobe output pin for the 8 higher bits of the data bus. This function is enabled when the external bus is enabled, when the external bus 16-bit mode is selected, and when the WRH output pin is enabled. G General purpose I/O port. The register can be set to select whether to use a pull-up resistor. This function is enabled either in single-chip mode or with the hold function disabled. HRQ Hold request input pin. This function is enabled when both the external bus and the hold function are enabled. OUT4 Waveform output pin for output compare OCU4. P35 G General purpose I/O port. The register can be set to select whether to use a pull-up resistor. This function is enabled either in single-chip mode or with the hold function disabled. HAK Hold acknowledge output pin. This function is enabled when both the external bus and the hold function are enabled. OUT5 Waveform output pin for output compare OCU5. CHAPTER 1 OVERVIEW Table 1.7-1 Pin description (6/6) Pin No. Pin name Circuit type Function LQFP64* 60 61 62, 63 P36 G General purpose I/O port. The register can be set to select whether to use a pull-up resistor. This function is enabled either in single-chip mode or with the external ready function disabled. RDY Ready input pin. This function is enabled when both the external bus and the external ready function are enabled. OUT6 Waveform output pin for output compare OCU6. P37 G General purpose I/O port. The register can be set to select whether to use a pull-up resistor. This function is enabled either in single-chip mode or with the CLK output disabled. CLK CLK output pin. This function is enabled when both the external bus and CLK output are enabled. OUT7 Waveform output pin for output compare OCU7. P60, P61 I AN0, AN1 General purpose I/O ports. Analog input pins for A/D converter. 64 AVCC K VCC power input pin for analog circuits. 2 AVRH L Reference voltage input for the A/D converter. This power supply must be turned on or off while a voltage higher than or equal to AVRH is applied to AVCC. 1 AVSS K VSS power input pin for analog circuits. 22, 23 MD1, MD0 C Input pins for specifying the operating mode. The pins must be directly connected to VCC or VSS. 21 MD2 D Input pins for specifying the operating mode. The pins must be directly connected to VCC or VSS. 49 VCC - Power (3.5 V to 5.5 V) input pin. 18, 48 VSS - Power (0 V) input pins. 50 C K This is the power supply stabilization capacitor pin. It should be connected to a higher than or equal to 0.1 µF ceramic capacitor. * : FPT-64P-M09 15 CHAPTER 1 OVERVIEW 1.8 Input-Output Circuits Table 1.8-1 lists the input-output circuits. ■ Input-output circuits Table 1.8-1 I/O circuit types (1/4) Type Circuit Remarks A X1 Xout Oscillation circuit High-speed oscillation feedback resistor = approx. 1 MΩ X0 Standby control signal B X1A Xout Oscillation circuit Low-speed oscillation feedback resistor = approx. 10 MΩ X0A Standby control signal C Mask ROM device: CMOS Hysteresis input pin R Hysteresis inputs D R Hysteresis inputs Pull-down Resistor 16 Flash device: CMOS input pin Mask ROM device: CMOS Hysteresis input pin Pull-down resistor value: approx. 50 kΩ Flash device: CMOS input pin No Pull-down CHAPTER 1 OVERVIEW Table 1.8-1 I/O circuit types (2/4) Type Circuit Remarks E CMOS Hysteresis input pin Pull-up resistor value: approx. 50 kΩ Pull-up Resistor R Hysteresis inputs F Pout Nout CMOS level output (IOL = 4 mA, IOH = −4 mA) CMOS hysteresis inputs (With the standby-time input shutdown function) Automotive input (With the standby-time input shutdown function) R Hysteresis inputs Automotive inputs Standby control for input shutdown G pull-up control pull-up resister Pout Nout R CMOS level output (IOL = 4 mA, IOH = −4 mA) CMOS hysteresis inputs (With the standby-time input shutdown function) Automotive input (With the standby-time input shutdown function) TTL input (With the standby-time input shutdown function) Programmable pull-up resistor: approx. 50 kΩ Hysteresis inputs Automotive inputs TTL input Standby control for input shutdown 17 CHAPTER 1 OVERVIEW Table 1.8-1 I/O circuit types (3/4) Type Circuit Remarks H CMOS level output (IOL = 3 mA, IOH = −3 mA) CMOS hysteresis inputs (With the standby-time input shutdown function) Automotive input (With the standby-time input shutdown function) Pout Nout R Hysteresis inputs Automotive inputs Standby control for input shutdown I CMOS level output (IOL = 4 mA) CMOS hysteresis inputs (With the standby-time input shutdown function) Automotive input (With the standby-time input shutdown function) A/D analog input Pout Nout R Hysteresis inputs Automotive inputs Standby control for input shutdown Analog input K Power supply input protection circuit L A/D converter reference voltage power supply input pin, with the protection circuit Flash devices do not have a protection circuit against VCC for pin AVRH ANE AVR ANE 18 CHAPTER 1 OVERVIEW Table 1.8-1 I/O circuit types (4/4) Type Circuit N Remarks pull-up control pull-up registor Pout Nout R CMOS level output (IOL = 4 mA, IOH = −4 mA) CMOS inputs (With the standby-time input shutdown function) Automotive input (With the standby-time input shutdown function) TTL input (With the standby-time input shutdown function) Programmable pull-up resistor: approx. 50 kΩ CMOS inputs Automotive inputs TTL input Standby control for input shutdown O Pout Nout R CMOS level output (IOL = 4 mA, IOH = −4 mA) CMOS inputs (With the standby-time input shutdown function) Automotive input (With the standby-time input shutdown function) A/D analog input CMOS inputs Automotive inputs Standby control for input shutdown Analog input 19 CHAPTER 1 OVERVIEW 1.9 Handling Device Special care is required for the following when handling the device: • Preventing latch-up • Treatment of unused pins • Using external clock • Power supply pins (VCC/VSS) • • • • • • • Pull-up/down resistors Crystal Oscillator Circuit Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs Connection of Unused Pins of A/D Converter Note on Power-on profile Initialization Output of Port0 to Port3 during power-on (External-bus mode) ■ Handling the device ● Preventing latch-up CMOS IC chips may suffer latch-up under the following conditions: • A voltage higher than VCC or lower than VSS is applied to an input or output pin. • A voltage higher than the rated voltage is applied between VCC and VSS. • The AVCC power supply is applied before the VCC voltage. Latch-up may increase the power supply current drastically, causing thermal damage to the device. For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVRH) exceed the digital power-supply voltage. ● Handling unused pins Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the device. Therefore they must be pulled up or pulled down through resistors. In this case those resistors should be more than 2 kΩ. Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above described connection. 20 CHAPTER 1 OVERVIEW ● Using external clock To use external clock, drive the X0 pin and leave X1 pin open. Figure 1.9-1 Using external clock MB90350 Series MB90590 Series X0 X1 ● Power supply pins (VCC/VSS) • If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential are connected the inside of the device to prevent such malfunctioning as latch up. To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level, and to keep the recommended DC characteristics specified as the total current, be sure to connect the VCC and VSS pins to the power supply and ground externally. • Connect VCC and VSS to the device from the power supply with lowest possible impedance. • As a measure against power supply noise, connect a capacitor of about 0.1 µF as a bypass capacitor between VCC and VSS in the vicinity of VCC and VSS pins of the device Figure 1.9-2 Power supply pins (VCC/VSS) Vcc Vss Vcc Vss Vss Vcc MB90350 Series Vcc Vss Vss Vcc 21 CHAPTER 1 OVERVIEW ● Pull-up/down resistors The MB90350 Series does not support internal pull-up/down resistors (except Port0 to Port3: programmable pull-up resistors). Use external components where needed. ● Crystal Oscillator Circuit Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits. It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with a ground area for stabilizing the operation. ● Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN14) after turning-on the digital power supply (VCC). Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure that the voltage not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable). ● Connection of Unused Pins of A/D Converter if A/D Converter is used Connect unused pins of A/D converter as AVCC = VCC, AVSS = AVRH = VSS. ● Notes on Power-on Profile To prevent malfunction of the internal voltage regulator, supply voltage profile while turning on the power. ● Initialization In the device, there are internal registers which is initialized only by a power-on reset. To initialize these registers, turn on the power again. ● Output of Port0 to Port3 during Power-on (External-bus mode) As shown below, when power is turned on in External-Bus mode, there is a possibility that output signal of Port0 to Port3 might be unstable. Figure 1.9-3 Output of Port0 to Port3 when power is turning 1/2VCC VCC Port0 ~ Port3 Port0 to Port3 output might unstable 22 Port0 to Port3 outputs = Hi-Z CHAPTER 2 CPU This chapter explains the CPU. 2.1 Outline of the CPU 2.2 Memory Space 2.3 Linear Addressing 2.4 Bank Addressing Types 2.5 Multi-byte Data in Memory Space 2.6 Registers 2.7 Register Bank 2.8 Prefix Codes 2.9 Interrupt Disable Instructions 23 CHAPTER 2 CPU 2.1 Outline of the CPU The F2MC-16LX CPU core is a 16-bit CPU designed for applications that require highspeed real-time processing, such as home-use or vehicle-mounted electronic appliances. The F2MC-16LX instruction set is designed for controller applications, and is capable of high-speed, highly efficient control processing. ■ Outline of the CPU In addition to 16-bit data, the F2MC-16LX CPU core can process 32-bit data by using an internal 32-bit accumulator. (32-bit data can be processed with some instructions.) Up to 16 Mbytes of memory space (expandable) can be used, which can be accessed by either the linear pointer or bank method. The instruction system, based on the F2MC-8 A-T architecture, has been reinforced by adding instructions compatible with high-level languages, expanding addressing modes, reinforcing multiplication and division instructions, and enhancing bit processing. The features of the F2MC-16LX CPU are explained below. ● Minimum instruction execution time: 42 ns (at 4-MHz oscillation, 6 times clock multiplication) ● Maximum memory space: 16 Mbytes, accessed in linear or bank mode ● Instruction set optimized for controller applications • Rich data types: Bit, byte, word, long word • Extended addressing modes: 23 types • High-precision operation (32-bit length) based on 32-bit accumulator ● Powerful interrupt functions Eight priority levels (programmable) ● CPU-independent automatic transfer •Up to 16 channels of the extended intelligent I/O service •Up to 16 channels of DMAC ● Instruction set compatible with high-level language (C)/multitasking System stack pointer/instruction set symmetry/barrel-shift instructions ● Improved execution speed: 4-byte queue 24 CHAPTER 2 CPU 2.2 Memory Space An F2MC-16LX CPU has a 16-Mbyte memory space. All data program input and output managed by the F2MC-16LX CPU are located in this 16-Mbyte memory space. The CPU accesses the resources by indicating their addresses using a 24-bit address bus. ■ Outline of CPU memory space All I/O, programs and data are located in the 16-megabyte memory space of the F2MC-16LX CPU. The CPU is able to access each resource through an address indicated by the 24-bit address bus. Figure 2.2-1 shows a sample relationship between the F2MC-16LX system and memory map. Figure 2.2-1 Sample relationship between F2MC-16LX system and memory F2MC-16LX device FFFFFFH FFFC00H Programs FF0000H *1 Vector table area Program area ROM area External area *3 010000H Peripheral circuits 008000H F2MC-16LX CPU Internal Bus 007900H 001900H *2 Data EI2OS 000380H 000180H 000100H ROM Mirror area (FF bank image) Peripheral Function Control Register Area I/O area Data Area General-Purpose Register EI2OS Descriptor area RAM area External area *3 Peripheral circuits Interrupts 0000F0H 0000C0H 0000B0H Peripheral circuits General-purpose ports 000020H 000000H Peripheral Function Control Register Area Interrupt Control Register Area Peripheral Function Control Register Area I/O Port Control Register Area I/O area *1: The size of the internal ROM differs for each model. *2: The size of the internal RAM differs for each model. *3: Access is not possible in single-chip mode. 25 CHAPTER 2 CPU ■ ROM area ● Vector table area (address: FFFC00H to FFFFFFH) This area is used as a vector table for vector call instructions, interrupt vectors, and reset vectors. This area is allocated at the highest addresses of the ROM area. The start address of the corresponding processing routine is set as data in each vector table address. ● Program area (address: Up to FFFBFFH) ROM is built in as an internal program area. The size of internal ROM differs for each model. ■ RAM area ● Data area (address: From 000100H to 0018FFH (for 6KByte)) The static RAM is built in as an internal data area. The size of internal RAM differs for each model. ● General-purpose register area (address: 000180H to 00037FH) Auxiliary registers used for 8-bit, 16-bit, and 32-bit arithmetic operations and transfer are allocated in this area. Since this area is allocated to a part of the RAM area, it can be used as ordinary RAM. When this area is used as a general-purpose register, general-purpose register addressing enables highspeed access with short instructions. ● Extended intelligent I/O service (EI2OS) descriptor area (address: 000100H to 00017FH) This area retains the transfer modes, I/O addresses, transfer count, and buffer addresses. Since this area is allocated to a part of the RAM area, it can be used as ordinary RAM. ■ I/O area ● Interrupt control register area (address: 0000B0H to 0000BFH) The interrupt control registers (ICR00 to ICR15) correspond to all peripheral functions that have an interrupt function. These registers set interrupt levels and control the extended intelligent I/O service (EI2OS). ● Peripheral function control register area (address: 000020H to 0000AFH , 0000C0H to 0000EFH , 007900H to 007FFFH) This register controls the built-in peripheral functions and inputs and outputs data. ● I/O port control register area (address: 000000H to 00001FH) This register controls I/O ports, and inputs and outputs data. 26 CHAPTER 2 CPU ■ Address generation types The F2MC-16LX has the following two addressing modes: ● Linear addressing An entire 24-bit address is specified by an instruction. ● This register Bank addressing. The eight high-order bits of an address are specified by an appropriate bank register, and the remaining 16 low-order bits are specified by an instruction. 27 CHAPTER 2 CPU 2.3 Linear Addressing There are two types of linear addressing: • 24-bit operand specification: Directly specifies a 24-bit address using operands. • 32-bit register indirect specification: Indirectly specifies the 24 low-order bits of a 32bit general-purpose register value as the address. ■ 24-bit operand specification Figure 2.3-1 shows an example of 24-bit operand specification. Figure 2.3-2 shows an example of 32-bit register indirect specification. Figure 2.3-1 Example of linear method (24-bit register operand specification) JMPP 123456 H Old program counter + program bank 17 17452D H 452D JMPP 123456 H 123456 H New program counter + program bank 12 Next instruction 3456 Figure 2.3-2 Example of linear method (32-bit register indirect specification) MOV A, @RL1+7 Old AL 090700 H XXXX 3A +7 RL1 (The high-order eight bits are ignored.) New AL 28 003A 240906F9 CHAPTER 2 CPU 2.4 Bank Addressing Types In the bank method, the 16-Mbyte space is divided into 256 64-Kbyte banks. The following five bank registers are used to specify the banks corresponding to each space: • Program bank register (PCB) • Data bank register (DTB) • User stack bank register (USB) • System stack bank register (SSB) • Additional bank register (ADB) ■ Bank addressing types ● Program bank register (PCB) The 64-Kbyte bank specified by the PCB is called a program (PC) space. The PC space contains instruction codes, vector tables, and immediate value data, for example. ● Data bank register (DTB) The 64-Kbyte bank specified by the DTB is called a data (DT) space. The DT space contains readable/ writable data, and control/data registers for internal and external resources. ● User stack bank register (USB)/system stack bank register (SSB) The 64-Kbyte bank specified by the USB or SSP is called a stack (SP) space. The SP space is accessed when a stack access occurs during a push/pop instruction or interrupt register saving. The S flag in the condition code register determines the stack space to be accessed. ● Additional bank register (ADB) The 64-Kbyte bank specified by the ADB is called an additional (AD) space. The AD space, for example, contains data that cannot fit into the DT space. Table 2.4-1 lists the default spaces used in each addressing mode, which are pre-determined to improve instruction coding efficiency. To use a non-default space for an addressing mode, specify a prefix code corresponding to a bank before the instruction. This enables access to the bank space corresponding to the specified prefix code. After reset, the DTB, USB, SSB, and ADB are initialized to 00H. The PCB is initialized to a value specified by the reset vector. After reset, the DT, SP, and AD spaces are allocated in bank 00H (000000H to 00FFFFH), and the PC space is allocated in the bank specified by the reset vector. 29 CHAPTER 2 CPU Table 2.4-1 Default space Default space Program space Addressing mode PC indirect, program access, branch Data space Addressing mode using @RW0, @RW1, @RW4, or @RW5, @A, addr16, and dir Stack space Addressing mode using PUSHW, POPW, @RW3, or @RW7 Additional space Addressing mode using @RW2 or @RW6 Figure 2.4-1 is an example of a memory space divided into register banks. Figure 2.4-1 Physical addresses of each space FFFFFF H Program space FF0000 H FF H : PCB (Program bank register) B3 H : ADB (Additional bank register) 92 H : USB (User stack bank register) 68 H : DTB (Data bank register) 4B H : SSB (System stack bank register) B3FFFF H Additional space Physical address B30000 H 92FFFF H User stack space 920000 H 68FFFF H 680000 H Data space 4BFFFF H System stack space 4B0000 H 000000 H 30 CHAPTER 2 CPU 2.5 Multi-byte Data in Memory Space Data is written to memory from the low-order addresses. Therefore, for a 32-bit data item, the low-order 16 bits are transferred before the high-order 16 bits. If a reset signal is input immediately after the low-order bits are written, the high-order bits might not be written. ■ Multi-byte data allocation in memory space Figure 2.5-1 is a diagram of multi-byte data configuration in memory. The low-order eight bits of a data item are stored at address n, then address n+1, address n+2, address n+3, etc. Figure 2.5-1 Sample allocation of multi-byte data in memory MSB H LSB 01010101 11001100 11111111 00010100 01010101 11001100 11111111 Address n 00010100 L ■ Accessing multi-byte data Fundamentally, accesses are made within a bank. For an instruction accessing a multi-byte data item, address FFFFH is followed by address 0000H of the same bank. Figure 2.5-2 is an example of an instruction accessing multi-byte data. Figure 2.5-2 Execution of MOVW A, 080FFFFH H 80FFFF H AL before execution ?? AL after execution 23 H ?? 01H · · · 800000 H 23 H 01H L 31 CHAPTER 2 CPU 2.6 Registers The F2MC-16LX registers are largely classified into two types: special registers in the CPU and general-purpose registers in memory. The special registers are dedicated internal hardware of the CPU, and they have specific use defined by the CPU architecture. The general-purpose registers share the CPU address space with RAM. The general-purpose registers are the same as the special registers in that they can be accessed without using an address. The applications of the general-purpose registers can be specified by the user however, as is ordinary memory space. ■ Special registers The F2MC-16LX CPU core has the following special registers: • Accumulator (A=AH:AL): Two 16-bit accumulators (Can be used as a single 32-bit accumulator.) • User stack pointer (USP): 16-bit pointer indicating the user stack area • System stack pointer (SSP): 16-bit pointer indicating the system stack area • Processor status (PS): 16-bit register indicating the system status • Program counter (PC): 16-bit register holding the address of the program • Program bank register (PCB): 8-bit register indicating the PC space • Data bank register (DTB): 8-bit register indicating the DT space • User stack bank register (USB): 8-bit register indicating the user stack space • System stack bank register (SSB): 8-bit register indicating the system stack space • Additional bank register (ADB): 8-bit register indicating the AD space • Direct page register (DPR): 8-bit register indicating a direct page Figure 2.6-1 is a diagram of the special registers. 32 CHAPTER 2 CPU Figure 2.6-1 Special registers AH AL Accumulator USP User stack pointer SSP System stack pointer PS Processor status PC Program counter DPR Direct page register PCB Program bank register DTB Data bank register USB User stack bank register SSB System stack bank register ADB Additional data bank register 8 bit 16 bit 32 bit 33 CHAPTER 2 CPU ■ General-purpose registers The F2MC-16LX general-purpose registers are located from addresses 000180H to 00037FH (maximum configuration) of main storage. The register bank pointer (RP) indicates which of the above addresses are currently being used as a register bank. Each bank has the following three types of registers. These registers are mutually dependent as described in Figure 2.6-2. • R0 to R7: 8-bit general-purpose register • RW0 to RW7: 16-bit general-purpose register • RL0 to RL3: 32-bit general-purpose register Figure 2.6-2 General-purpose registers MSB LSB 16 bit 000180H + RP × 10H RW0 Low-order RL0 First address of general-purpose register RW1 RW2 RL1 RW3 R1 R0 RW4 R3 R2 RW5 R5 R4 RW6 R7 R6 RW7 RL2 RL3 High-order The relationship between the high-order and low-order bytes of a byte or word register is expressed as follows: RW (i+4) = R (i×2+1) × 256+R (i×2) [i=0 to 3] The relationship between the high-order and low-order bytes of Rli and RW can be expressed as follows: RL (i) = RW (i×2+1) × 65536+RW (i×2) [i=0 to 3] 34 CHAPTER 2 CPU 2.6.1 Accumulator (A) The accumulator (A) register consists of two 16-bit arithmetic operation registers (AH and AL), and is used as a temporary storage for operation results and transfer data. ■ Accumulator (A) The A register consists of two 16-bit arithmetic operation registers (AH and AL). The A register is used as a temporary storage for operation results and transfer data. During 32-bit data processing, AH and AL are used together. Only AL is used for word processing in 16-bit data processing mode or for byte processing in 8-bit data processing mode (see Figure 2.6-3 and Figure 2.6-4). The data stored in the A register can be operated upon with the data in memory or registers (Ri, Rwi, or Rli). In the same manner as with the F2MC-8L, when a word or shorter data item is transferred to AL, the previous data item in AL is automatically sent to AH (data preservation function). The data preservation function and operation between AL and AH help improve processing efficiency. When a byte or shorter data item is transferred to AL, the data is sign-extended or zero-extended and stored as a 16-bit data item in AL. The data in AL can be handled either as word or byte long. When a byte-processing arithmetic operation instruction is executed on AL, the high-order eight bits of AL before operation are ignored. The high-order eight bits of the operation result all become zeroes. The A register is not initialized by a reset. The A register holds an undefined value immediately after a reset. Figure 2.6-3 32-bit data transfer MO VL A,@R W1+6 Old A XXXX H MSB XXXX H A6 H DTB New A 8F74 H AH LSB A61540 H 8F H 74 H A6153E H 2B H 52 H 15 H 38 H +6 2B52 H RW1 AL Figure 2.6-4 AL-AH transfer MSB MO VW A,@R W1+6 Old A XXXX H 1234 H DTB New A 1234 H 1234 H A6 H LSB A61540 H 8F H 74 H A6153E H 2B H 52 H 15 H 38 H +6 RW1 35 CHAPTER 2 CPU 2.6.2 User Stack Pointer (USP) and System Stack Pointer (SSP) USP and SSP are 16-bit registers that indicate the memory addresses for saving and restoring data when a push/pop instruction or subroutine is executed. ■ User stack pointer (USP) and system stack pointer (SSP) USP and SSP are 16-bit registers that indicate the memory addresses for saving and restoring data in the event of a push/pop instruction or subroutine execution. The USP and SSP registers are used by stack instructions. The USP register is enabled when the S flag in the processor status register is “0”, and the SSP register is enabled when the S flag is “1” (see Figure 2.6-5). Since the S flag is set when an interrupt is accepted, register values are always saved in the memory area indicated by SSP during interrupt processing. SSP is used for stack processing in an interrupt routine, while USP is used for stack processing outside an interrupt routine. If the stack space is not divided, use only the SSP. During stack processing, the high-order eight bits of an address are indicated by SSB (for SSP) or USB (for USP). USP and SSP are not initialized by a reset. Instead, they hold undefined values. Figure 2.6-5 Stack manipulation instruction and stack pointer Example 1 PUSHW A when the S flag is '0' Before execution AL S flag After execution AL MSB C6F326 H LSB A624 H USB C6 H USP F328 H 0 SSB 56 H SSP 1234 H A624 H USB C6 H USP F326 H 0 SSB 56 H SSP 1234 H C6F326 H A6 H 24 H A624 H USB C6 H USP F328 H 561232 H XX XX 1 SSB 56 H SSP 1234 H A624 H USB C6 H USP F328 H 561232 H A6 H 24 H 1 SSB 56 H SSP 1232 H XX XX User stack is used because the S flag is '0.' Example 2 PUSHW A when the S flag is '1' AL AL System stack is used because the S flag is "1". Note: Specify an even-numbered address in the stack pointer whenever possible. 36 CHAPTER 2 CPU 2.6.3 Processor Status (PS) The PS register consists of the bits controlling the CPU Operation and the bits indicating the CPU status. ■ Processor status (PS) As shown in Figure 2.6-6, the high-order byte of the PS register consists of a register bank pointer (RP) and an interrupt level mask register (ILM). The RP indicates the start address of a register bank. The low-order byte of the PS register is a condition code register (CCR), containing the flags to be set or reset depending on the results of instruction execution or interrupt occurrences. Figure 2.6-6 Processor status (PS) structure 15 PS 13 12 0 8 7 ILM RP CCR ■ Condition code register (CCR) Figure 2.6-7 is a diagram of condition code register configuration. Figure 2.6-7 Condition code register (CCR) configuration Initial value 7 6 5 4 3 2 1 0 - I S T N Z V C - 0 1 * * * * * : CCR *: Undefined ● I: Interrupt enable flag: Interrupts other than software interrupts are enabled when the I flag is 1 and are masked when the I flag is 0. The I flag is cleared by a reset. ● S: Stack flag: When the S flag is 0, USP is enabled as the stack manipulation pointer. When the S flag is 1, SSP is enabled as the stack manipulation pointer. The S flag is set by an interrupt reception or a reset. 37 CHAPTER 2 CPU ● T: Sticky bit flag: 1 is set in the T flag when there is at least one "1" in the data shifted out from the carry after execution of a logical right/arithmetic right shift instruction. Otherwise, 0 is set in the T flag. In addition, "0" is set in the T flag when the shift amount is zero. ● N: Negative flag: The N flag is set when the MSB of the operation result is "1", and is otherwise cleared. ● Z: Zero flag: The Z flag is set when the operation result is all zeroes, and is otherwise cleared. ● V: Overflow flag: The V flag is set when an overflow of a signed value occurs as a result of operation execution and is otherwise cleared. ● C: Carry flag: The C flag is set when a carry-up or carry-down from the MSB occurs as a result of operation execution, and is otherwise cleared. ■ Register bank pointer (RP) The RP register indicates the relationship between the general-purpose registers of the F2MC-16LX and the internal RAM addresses. Specifically, the RP register indicates the first memory address of the currently used register bank in the following conversion expression: [00180H + (RP)*10H] (see Figure 2.6-8). The RP register consists of five bits, and can take a value between 00H and 1FH. Register banks can be allocated at addresses from 000180H to 00037H in memory. Even within that range, however, the register banks cannot be used as general-purpose registers if the banks are not in internal RAM. The RP register is initialized to all zeroes by a reset. An instruction may transfer an eight-bit immediate value to the RP register; however, only the low-order five bits of that data are used. Figure 2.6-8 Register bank pointer (RP) Initial value 38 B4 B3 B2 B1 0 0 0 0 B0 0 : RP CHAPTER 2 CPU ■ Interrupt level mask register (ILM) The ILM register consists of three bits, indicating the CPU interrupt masking level. An interrupt request is accepted only when the level of the interrupt is higher than that indicated by these three bits. Level 0 is the highest priority interrupt, and level 7 is the lowest priority interrupt (see Table 2.6-1). Therefore, for an interrupt to be accepted, its level value must be smaller than the current ILM value. When an interrupt is accepted, the level value of that interrupt is set in ILM. Thus, an interrupt of the same or lower level cannot be accepted subsequently. ILM is initialized to all zeroes by a reset. An instruction may transfer an eight-bit immediate value to the ILM register, but only the low-order three bits of that data are used. Figure 2.6-9 Interrupt level register (ILM) Initial value ILM2 ILM1 ILM0 0 0 0 : ILM Table 2.6-1 Levels indicated by the interrupt level mask (ILM) register ILM2 ILM1 ILM0 Level value Acceptable interrupt level 0 0 0 0 Interrupt disabled 0 0 1 1 0 only 0 1 0 2 Level value smaller than 1 0 1 1 3 Level value smaller than 2 1 0 0 4 Level value smaller than 3 1 0 1 5 Level value smaller than 4 1 1 0 6 Level value smaller than 5 1 1 1 7 Level value smaller than 6 39 CHAPTER 2 CPU 2.6.4 Program Counter (PC) The PC register is a 16-bit counter that indicates the low-order 16 bits of the memory address of an instruction code to be executed by the CPU. The high-order eight bits of the address are indicated by the PCB. The PC register is updated by a conditional branch instruction, subroutine call instruction, interrupt, or reset. The PC register can also be used as a base pointer for operand access. ■ Program counter (PC) Figure 2.6-10 shows the program counter. Figure 2.6-10 Program counter PCB FE H PC ABCD H Next instruction to be executed FEABCD H 40 CHAPTER 2 CPU 2.7 Register Bank A register bank consists of eight words. The register bank can be used as the following general-purpose registers for arithmetic operations: byte registers R0 to R7, word registers RW0 to RW7, and long word registers RL0 to RL3. In addition, the register bank can be used as instruction pointers. ■ Register bank Table 2.7-1 lists the functions of the registers. Table 2.7-2 indicates the relationship between the registers. In the same manner as for an ordinary RAM area, the register bank values are not initialized by a reset. The status before a reset is maintained. When the power is turned on, however, the register bank will have an undefined value. Table 2.7-1 Register functions R0 to R7 Used as operands of instructions. Note: R0 is also used as a counter for barrel shift or normalization instructions. RW0 to RW7 Used as pointers. Used as operands of instructions. Note: RW0 is used as a counter for string instructions. RL0 to RL3 Used as long pointers. Used as operands of instructions. Table 2.7-2 Relationship between registers RW0 RL0 RW1 RW2 RL1 RW3 R0 RW4 R1 RL2 R2 RW5 R3 R4 RW6 R5 RL3 R6 RW7 R7 41 CHAPTER 2 CPU ● Direct page register (DPR) <Initial value: 01H> DPR specifies addr8 to addr15 of the instruction operands in direct addressing mode as shown in Figure 2.7-1. DPR is eight bits long, and is initialized to 01H by a reset. DPR can be read or written to by an instruction. Figure 2.7-1 Generating a physical address in direct addressing mode DTB register DPR register Direct address during instruction αααααααα ββββββββ γγγγγγγγ LSB MSB 24-bit physical address ααααααααββββββββγγγγγγγγ ● Program counter bank register (PCB) <Initial value: Value in reset vector> ● Data bank register (DTB) <Initial value: 00H> ● User stack bank register (USB) <Initial value: 00H> ● System stack bank register (SSB) <Initial value: 00H> ● Additional data bank register (ADB) <Initial value: 00H> Each bank register indicates the memory bank where the PC, DT, SP (user), SP (system), or AD space is allocated. All bank registers are one byte long. PCB is initialized to 00H by a reset. Bank registers other than PCB can be read or written to. PCB can be read but cannot be written to. PCB is updated when the JMPP, CALLP, RETP, RETIQ, or RETF instruction branching to the entire 16Mbyte space is executed or when an interrupt occurs. For operation of each register, see Section "2.2 Memory Space". 42 CHAPTER 2 CPU 2.8 Prefix Codes Placing a prefix code before an instruction partially changes the operation of the instruction. Three types of prefix codes can be used: bank select prefix, common register bank prefix, and flag change disable prefix. ■ Bank select prefix The memory space used for accessing data is determined for each addressing mode. When a bank select prefix is placed before an instruction, the memory space used for accessing data by that instruction can be selected regardless of the addressing mode. Table 2.8-1 lists the bank select prefixes and the corresponding memory spaces. Table 2.8-1 Bank select prefix Bank select prefix Space selected PCB PC space DTB Data space ADB AD space SPB Either the SSP or USP space is used according to the stack flag value. Use the following instructions with care: ● String instructions (MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW) The bank register specified by an operand is used regardless of the prefix. ● Stack manipulation instructions (PUSHW, POPW) SSB or USB is used according to the S flag regardless of the prefix. ● I/O access instructions MOV A, io / MOV io, A /MOVX A, io / MOVW A, io /MOVW io, A / MOV io, #imm8 MOV io, #imm16 / MOVB A, io:bp / MOB io:bp, A /SETB io:bp / CLRB io:bp BBC io:bp, rel / BBS io:bp, rel WBTC, WBTS The IO space of the bank is used regardless of the prefix. ● Flag change instructions (AND CCR,#imm8, OR CCR,#imm8) The instruction is executed normally, but the prefix affects the next instruction. ● POPW PS SSB or USB is used according to the S flag regardless of the prefix. The prefix affects the next instruction. 43 CHAPTER 2 CPU ● MOV ILM,#imm8 The instruction is executed normally, but the prefix affects the next instruction. ● RETI SSB is used regardless of the prefix. ■ Common register bank prefix (CMR) To simplify data exchange between multiple tasks, the same register bank must be accessed relatively easily regardless of the RP value. When CMR is placed before an instruction that accesses a register bank, that instruction accesses the common bank (the register bank selected when RP=0) at addresses from 000180H to 00018FH regardless of the current RP value. Use the following instructions with care: ● String instructions (MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW) If an interrupt request occurs during execution of a string instruction with a prefix code, the prefix code becomes invalid when the string instruction is resumed after the interrupt is processed. Thus, the string instruction is executed falsely after the interrupt is processed. Do not prefix any of the above string instructions with CMR. ● Flag change instructions (AND CCR,#imm8, OR CCR,#imm8, POPW PS) The instruction is executed normally, but the prefix affects the next instruction. ● MOV ILM,#imm8 The instruction is executed normally, but the prefix affects the next instruction. ■ Flag change disable prefix (NCC) To disable flag changes, use the flag change disable prefix code (NCC). Placing NCC before an instruction disables flag changes associated with that instruction. Use the following instructions with care: ● String instructions (MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW) If an interrupt request occurs during execution of a string instruction with a prefix code, the prefix code becomes invalid when the string instruction is resumed after the interrupt is processed. Thus, the string instruction is executed incorrectly after the interrupt is processed. Do not prefix any of the above string instructions with NCC. ● Flag change instructions (AND CCR,#imm8, OR CCR,#imm8, POPW PS) The instruction is executed normally, but the prefix affects the next instruction. ● Interrupt instructions (INT #vct8, INT9, INT addr16, INTP addr24, RETI) CCR changes according to the instruction specifications regardless of the prefix. ● JCTX @A CCR changes according to the instruction specifications regardless of the prefix. 44 CHAPTER 2 CPU ● MOV ILM,#imm8 The instruction is executed normally, but the prefix affects the next instruction. 45 CHAPTER 2 CPU 2.9 Interrupt Disable Instructions Interrupt requests are not sampled for the following ten instructions: - MOV ILM,#imm8 - PCB - SPB - OR CCR,#imm8 - AND CCR,#imm8 - ADB - CMR - POPW PS - NCC - DTB ■ Interrupt disable instructions If a valid interrupt request occurs during execution of any of the above instructions, the interrupt can be processed only when an instruction other than the above is executed. For details, see Figure 2.9-1. Figure 2.9-1 Interrupt disable instruction Interrupt disable instruction •••••••• (a) ••• (a) Ordinary instruction Interrupt request Interrupt acceptance ■ Restrictions on interrupt disable instructions and prefix instructions When a prefix code is placed before an interrupt disable instruction, the prefix code affects the first instruction after the code other than the interrupt disable instruction. For details, see Figure 2.9-2. Figure 2.9-2 Interrupt disable instructions and prefix codes Interrupt disable instruction MOV A, FF H CCR:XXX10XX NCC MOV ILM,#imm8 •••• ADD A,01 H CCR:XXX10XX CCR does not change with NCC. 46 CHAPTER 2 CPU ■ Consecutive prefix codes When competitive prefix codes are placed consecutively, the latter becomes valid. In the figure below, competitive prefix codes are PCB, ADB, DTB, and SPB. For details, see Figure 2.9-3. Figure 2.9-3 Consecutive prefix codes Prefix code ••••• ADB DTB PCB ADD A,01H •••• PCB is valid as the prefix code 47 CHAPTER 2 CPU 48 CHAPTER 3 INTERRUPTS This chapter explains the interrupt functions and operations. 3.1 Outline of Interrupts 3.2 Interrupt Vector 3.3 Interrupt Control Registers (ICR) 3.4 Interrupt Flow 3.5 Hardware Interrupts 3.6 Software Interrupts 3.7 Extended Intelligent I/O Service (EI2OS) 3.8 Operation Flow of and Procedure for Using the Extended Intelligent I/O Service (EI2OS) 3.9 µDMAC Interrupt 3.10 Exceptions 49 CHAPTER 3 INTERRUPTS 3.1 Outline of Interrupts The F2MC-16LX has interrupt functions that terminate the currently executing processing and transfer control to another specified program when a specified event occurs. There are five types of interrupt functions: • Hardware interrupt: Interrupt processing due to an internal resource event • Software interrupt:Interrupt processing due to a software event occurrence instruction • Extended intelligent I/O service (EI2OS):Transfer processing due to an internal resource event • µDMAC: Transfer processing due to an internal resource event. • Exception: Termination due to an operation exception ■ Hardware interrupts A hardware interrupt is activated by an interrupt request from an internal resource. A hardware interrupt request occurs when both the interrupt request flag and the interrupt enable flag in an internal resource are set. Therefore, an internal resource must have an interrupt request flag and interrupt enable flag to issue a hardware interrupt request. ● Specifying an interrupt level An interrupt level can be specified for the hardware interrupt. To specify an interrupt level, use the level setting bits (IL0, IL1, and IL2) of the interrupt controller. ● Masking a hardware interrupt request A hardware interrupt request can be masked by using the I flag of the processor status register (PS) in the CPU and the ILM bits (IL0, IL1, and IL2). When an unmasked interrupt request occurs, the CPU saves 12 bytes of data that consists of registers PS, PC, PCB, DTB, ADB, DPR, and A in the memory area indicated by the SSB and SSP registers. 50 CHAPTER 3 INTERRUPTS Figure 3.1-1 Overview of hardware interrupts PS Register file F2MC-16 bus Microcode IR (6) I ILM Check Comparator (5) F2M C - 1 6 LX . CPU (4) PS I ILM IR : : : : Processor status Interrupt enable flag Interrupt level mask register Instruction register Enable FF AND (7) Cause FF (1) (2) Interrupt level IL Peripheral Level comparator (3) Interrupt controller (1.)An interrupt cause occurs in a peripheral. (2.)The interrupt enable bit in the peripheral is referenced. If interrupts are enabled, the peripheral issues an interrupt request to the interrupt controller. (3.)Upon reception of the interrupt request, the interrupt controller determines the priority levels of simultaneously requested interrupts. Then, the interrupt controller transfers the interrupt level of the corresponding interrupt to the CPU. (4.)The CPU compares the interrupt level requested by the interrupt controller with the ILM bit of the processor status register. (5.)If the comparison shows that the requested level is higher than the current interrupt processing level, the I flag value of the same processor status register is checked. (6.)If the check in step 5. shows that the I flag indicates interrupt enable status, the requested level is written to the ILM bit. Interrupt processing is performed as soon as the currently executing instruction is completed, then control is transferred to the interrupt processing routine. (7.)When the interrupt cause of step 1. is cleared by software in the user interrupt processing routine, the interrupt request is completed. ■ Software interrupts Interrupts requested by executing the INT instruction are software interrupts. An interrupt request by the INT instruction does not have an interrupt request or enable flag. An interrupt request is issued always by executing the INT instruction. No interrupt level is assigned to the INT instruction. Therefore, ILM is not updated when the INT instruction is used. Instead, the I flag is cleared and the continuing interrupt requests are suspended. 51 CHAPTER 3 INTERRUPTS Figure 3.1-2 Overview of software interrupts (1) PS F2MC-16 bus Register file I (2) Microcode S B unit IR F 2 M C - 1 6 LX · C P U Queue PS I ILM IR B unit : : : : : Processor status Interrupt enable flag Interrupt level mask register Instruction register Bus interface unit Fetch Save Instruction bus RAM (1.)The software interrupt instruction is executed. (2.)Special CPU registers in the register file are saved according to the microcode corresponding to the software interrupt instruction. (3.)The interrupt processing is completed with the RETI instruction in the user interrupt processing routine. ■ Extended intelligent I/O service (EI2OS) The extended intelligent I/O service automatically transfers data between an internal resource and memory. This processing is traditionally performed by an interrupt processing program, but the EI2OS enables data to be transferred in a manner similar to a DMA (direct memory access) operation. To activate the extended intelligent I/O service function from an internal resource, the interrupt control register (ICR) of the interrupt controller must have an extended intelligent I/O service enable flag (ISE). The extended intelligent I/O service is started when an interrupt request occurs with 1 specified in the ISE flag. To generate a normal interrupt using a hardware interrupt request, set the ISE flag to 0. 52 CHAPTER 3 INTERRUPTS Figure 3.1-3 Overview of the extended intelligent I/O service (EI2OS) Memory space by IOA I/O register I/O register Peripheral Interrupt request CPU (3) ISD (3) (1) by ICS (2) Interrupt control register Interrupt controller (1) (2) by BAP (3) (4) Buffer by DCT (4) I/O requests transfer. The interrupt controller selects the descriptor. The transfer source and destination are read from the descriptor. Data is transferred between I/O and memory. 53 CHAPTER 3 INTERRUPTS ■ Direct memory access (DMA) DMA is a function used to automatically transfer data between peripheral functions and memory. Previous data transfers by an interrupt processing program is provided in the same way as the direct memory access (DMA). When a transfer of data of a specified count is completed, an interrupt processing program is automatically executed. Interrupt by DMA is a type of hardware interrupts. Figure 3.1-4 Overview of the Direct Memory access (DMA) Memory space IOA I/O register I/O register Peripheral function (I/O) RAM for descriptor (1) (4)(a) (2) (3) DMA controller DMA descriptor (2) (4)(b) BAP Buffer CPU Interrupt controller IOA: I/O address pointer BAP: Buffer address pointer DER: DMA enable register DCT: Data counter DCT (1) The peripheral resource (I/O) requests DMA transfer. (2) When the corresponding bit of DMA enable register (DER) is "1", DMAC reads from the descriptor the transfer data such as the transfer source address, transfer destination address, and transfer count of specified channels. (3) DMA data transfer is started between I/O and memory. (4) After one item(either Byte data or Word data) transferred (a) Transfer has not been completed (DCT does not reached to 0): µDMAC requests to clear the DMA transfer request to the peripheral resource. (b) At transfer end(DCT reached to 0): After completion of DMA transfer, the flag indicating completion of transfer is set in the DMA status register, outputting an interrupt request to the interrupt controller. *: Write access to the internal registers DCSR, DSRH, DSRL, DSSR, DERH, and DERL is prohibited during DMA transfer. ■ Exceptions Exception processing is basically the same as interrupt processing. When an exception is detected between instructions, exception processing is performed. In general, exception processing occurs as a result of an unexpected operation. Therefore, use exception processing only for debugging programs or for activating recovery software in an emergency. 54 CHAPTER 3 INTERRUPTS 3.2 Interrupt Vector An interrupt vector uses the same area for both hardware and software interrupts. For example, interrupt request number INT42 is used for a delayed hardware interrupt and for software interrupt INT #42. Therefore, the delayed interrupt and INT #42 call the same interrupt processing routine. Interrupt vectors are allocated between addresses FFFC00H and FFFFFFH as shown in Table 3.2-1. ■ Interrupt vector Table 3.2-1 Interrupt vectors (1/2) Interrupt request Interrupt cause Interrupt control register Number Address Vector address L Vector address H Vector address bank Mode register INT 0 * -- -- -- FFFFFCH FFFFFDH FFFFFEH Unused INT 1 * -- -- -- FFFFF8H FFFFF9H FFFFFAH Unused -- -- -- . . . . . . . . . . . . -- -- -- FFFFE0H FFFFE1H FFFFE2H Unused . . . INT 7 * INT 8 Reset -- -- FFFFDCH FFFFDDH FFFFDEH FFFFDFH INT 9 INT9 instruction -- -- FFFFD8H FFFFD9H FFFFDAH Unused INT 10 Exception -- -- FFFFD4H FFFFD5H FFFFD6H Unused INT 11 Reserved FFFFD1H FFFFD2H Unused 0000B0H FFFFD0H ICR00 FFFFCCH FFFFCDH FFFFCEH Unused FFFFC8H FFFFC9H FFFFCAH Unused FFFFC4H FFFFC5H FFFFC6H Unused FFFFC0H FFFFC1H FFFFC2H Unused FFFFBCH FFFFBDH FFFFBEH Unused FFFFB8H FFFFB9H FFFFBAH Unused FFFFB4H FFFFB5H FFFFB6H Unused FFFFB0H FFFFB1H FFFFB2H Unused FFFFACH FFFFADH FFFFAEH Unused FFFFA8H FFFFA9H FFFFAAH Unused FFFFA4H FFFFA5H FFFFA6H Unused INT 12 Reserved INT 13 CAN1 RX / Input Capture6 INT 14 CAN1 TX/NS /Input Caputer7 INT 15 I2C0 INT 16 Reserved INT 17 16-bit ReloadTimer0 ICR01 ICR02 ICR03 INT 18 16-bit ReloadTimer1 INT 19 16-bit ReloadTimer2 ICR04 INT 20 16-bit ReloadTimer3 INT 21 PPG 4/5 ICR05 INT 22 PPG 6/7 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 55 CHAPTER 3 INTERRUPTS Table 3.2-1 Interrupt vectors (2/2) Interrupt request INT 23 Interrupt cause Interrupt control register Number Address ICR06 0000B6H PPG 8/9/C/D INT 24 PPG A/B/E/F INT 25 Time Base Timer ICR07 INT 26 External Interrupt 8-11 INT 27 Watch Timer ICR08 INT 28 External Interrupt 12-15 INT 29 A/D Converter ICR09 INT 30 I/O Timer 0/1 INT 31 Input Capture 4/5 ICR10 INT 32 Output Compare 4/5 INT 33 Input Capture 0/1 ICR11 INT 34 Output Compare 6/7 INT 35 Reserved ICR12 INT 36 Reserved INT 37 UART3 RX ICR13 INT 38 UART 3 TX INT 39 UART 2 RX ICR14 INT 40 UART 2 TX INT 41 Flash Memory ICR15 INT 42 INT 43 Delayed Interrupt 0000B7H 0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH Vector address L Vector address H Vector address bank Mode register FFFFA0H FFFFA1H FFFFA2H Unused FFFF9CH FFFF9DH FFFF9EH Unused FFFF98H FFFF99H FFFF9AH Unused FFFF94H FFFF95H FFFF96H Unused FFFF90H FFFF91H FFFF92H Unused FFFF8CH FFFF8DH FFFF8EH Unused FFFF88H FFFF89H FFFF8AH Unused FFFF84H FFFF85H FFFF86H Unused FFFF80H FFFF81H FFFF82H Unused FFFF7CH FFFF7DH FFFF7EH Unused FFFF78H FFFF79H FFFF7AH Unused FFFF74H FFFF75H FFFF76H Unused FFFF70H FFFF71H FFFF72H Unused FFFF6CH FFFF6DH FFFF6EH Unused FFFF68H FFFF69H FFFF6AH Unused FFFF64H FFFF65H FFFF66H Unused FFFF60H FFFF61H FFFF62H Unused FFFF5CH FFFF5DH FFFF5EH Unused FFFF58H FFFF59H FFFF5AH Unused FFFF54H FFFF55H FFFF56H Unused -- -- -- FFFF50H FFFF51H FFFF52H Unused -- -- -- . . . . . . . . . . . . INT 254 -- -- -- FFFC04H FFFC05H FFFC06H Unused INT 255 -- -- -- FFFC00H FFFC01H FFFC02H Unused . . . *: When PCB is FFH, the vector area for the CALLV instruction is the same as that for INT #vct8 (#0 to #7). Care must be taken when using the vector for the CALLV instruction. 56 CHAPTER 3 INTERRUPTS 3.3 Interrupt Control Registers (ICR) The interrupt control registers are in the interrupt controller. Each interrupt control register has a corresponding I/O that has an interrupt function. The interrupt control registers have the following three functions: • Setting an interrupt level for corresponding peripherals • Selecting whether to use an ordinary interrupt or extended intelligent I/O service for the corresponding peripherals • Selecting the extended intelligent I/O service channel Do not access an interrupt control register by using a read-modify-write instruction, as doing so causes a misoperation. ■ Interrupt control register (ICR) Figure 3.3-1 is a diagram of the bit configuration of an interrupt control register. Figure 3.3-1 Interrupt control register (ICR) 14/6 15/7 ICS3 ICS2 W W 13/5 12/4 11/3 10/2 9/1 8/0 ICS1 or S1 ICS0 or S0 ISE IL2 IL1 IL0 R/W R/W R/W R/W * * Interrupt control register 00000111B when reset Note: ICS3 to ICS0 are valid only when EI2OS is activated. Set "1" in ISE to activate EI2OS, and set "0" in ISE not to activate it. When EI2OS is not to be activated, any value can be set in ICS3 to ICS0. * "1" is read always. ICS1 and ICS0 are valid for write only. S1 and S0 are valid for read only. [bits 10 to 8] [bits 2 to 0]: IL0, IL1, and IL2 (interrupt level setting bits) These bits are readable and writable, and specify the interrupt level of the corresponding internal resources. Upon a reset, these bits are initialized to level 7 (no interrupt). Table 3.3-1 describes the relationship between the interrupt level setting bits and interrupt levels. 57 CHAPTER 3 INTERRUPTS Table 3.3-1 Interrupt level setting bits and interrupt levels IL2 IL1 IL0 Level 0 0 0 0 (Strongest) 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 (Weakest) 1 1 1 7 (No interrupt) [bit 11] [bit 3]: ISE (extended intelligent I/O service enable bits) The ISE bit is readable and writable. In response to an interrupt request, EI2OS is activated when "1" is set in the ISE bit and an interrupt sequence is activated when "0" is set in the ISE bit. Upon completion of EI2OS, the ISE bit is cleared to a zero. If the corresponding peripheral does not have the EI2OS function, the ISE bit must be set to '0' on the software side. Upon a reset, the ISE bit is initialized to '0'. [bits 15 to 12] [bits 7 to 4]: ICS 3 to 0 (extended intelligent I/O service channel select bits) ICS3 to ICS0 are write-only bits. These bits specify the EI2OS channel. The values set in these bits determined the intelligent I/O service descriptor addresses in memory, which is explained later. The ICS bits are initialized by a reset. Table 3.3-2 describes the correspondence between the ICS bits, channel numbers, and descriptor addresses. 58 CHAPTER 3 INTERRUPTS Table 3.3-2 ICS bits, channel numbers, and descriptor addresses ICS3 ICS2 ICS1 ICS0 Selected channel Descriptor address 0 0 0 0 0 000100H 0 0 0 1 1 000108H 0 0 1 0 2 000110H 0 0 1 1 3 000118H 0 1 0 0 4 000120H 0 1 0 1 5 000128H 0 1 1 0 6 000130H 0 1 1 1 7 000138H 1 0 0 0 8 000140H 1 0 0 1 9 000148H 1 0 1 0 10 000150H 1 0 1 1 11 000158H 1 1 0 0 12 000160H 1 1 0 1 13 000168H 1 1 1 0 14 000170H 1 1 1 1 15 000178H [bits 13 and 12] [bits 5 and 4]: S0 and S1 (extended intelligent I/O service status) S0 and S1 are read-only bits. The values set in these bits indicate the end condition of EI2OS. These bits are initialized to "00" upon a reset. Table 3.3-3 shows the relationship between the S bits and the end conditions. Table 3.3-3 S bits and end conditions S1 S0 End condition 0 0 EI2OS running or not activated 0 1 Termination by count 1 0 Reserved 1 1 Termination by request from resource 59 CHAPTER 3 INTERRUPTS 3.4 Interrupt Flow Figure 3.4-1 shows the interrupt flow. ■ Interrupt flow Figure 3.4-1 Interrupt flow START I & IF & IE = 1 AND ILM > IL I:Flag in CCR ILM:Level register in CPU IF:Internal resource interrupt request IE:Internal resource interrupt enable flag ENx:Request flag excuting DMA of DMA Enable Register ISE: EI 2OS enable flag IL:Internal resource interruptrequest level S:Flag in CCR YES NO YES ENx=1? DMA processing NO Has the specified number of YES times been completed? Or did a peripheral function issue a complete request? NO NO YES ISE = 1 Fetching and decoding the next instruction Saving PS, PC, PCB, DTB, ADB, DPR, and A into the stack of SSP, and setting ILM=IL Executing the extended intelligent I/O service YES INT instruction NO Executing an ordinary instruction NO Completion of string instruction repetition YES Updating PC 60 Saving PS, PC, PCB, DTB, ADB, DPR, and A into the stack of SSP, and setting I=O and ILM=IL 1 S Fetching the interrupt vector CHAPTER 3 INTERRUPTS Figure 3.4-2 Register saving during interrupt processing Word (16 bits) MSB LSB H SSP (SSP value before interrupt) AH AL DPR ADB DPB PCB PC PS L SSP (SSP value after interrupt) 61 CHAPTER 3 INTERRUPTS 3.5 Hardware Interrupts In response to an interrupt request signal from an internal resource, the CPU pauses current program execution and transfers control to the interrupt processing program defined by the user. This function is called the hardware interrupt function. ■ Hardware interrupts A hardware interrupt occurs when the relevant conditions are satisfied as a result of two operations: comparison between the interrupt request level and the value in the interrupt level mask register (ILM) of PS in the CPU, and hardware reference to the I flag value of PS. The CPU performs the following processing when a hardware interrupt occurs: • Saves the values in the PC, PS, AH, AL, PCB, DTB, ADB, and DPR registers of the CPU to the system stack. • Sets ILM in the PS register. The currently requested interrupt level is automatically set. • Fetches the corresponding interrupt vector value and branches to the processing indicated by that value. ■ Structure of hardware interrupt Hardware interrupts are handled by the following three sections: ● Internal resources Interrupt enable and request bits: Used to control interrupt requests from resources. ● Interrupt controller ICR: Assigns interrupt levels and determines the priority levels of simultaneously requested interrupts. ● CPU I and ILM: Used to compare the requested and current interrupt levels and to identify the interrupt enable status. Microcode: Interrupt processing step The status of these sections are indicated by the resource control registers for internal resources, the ICR for the interrupt controller, and the CCR value for the CPU. To use a hardware interrupt, set the three sections beforehand by using software. The interrupt vector table referenced during interrupt processing is assigned to addresses FFFC00H to FFFFFFH in memory. These addresses are shared with software interrupts. 62 CHAPTER 3 INTERRUPTS 3.5.1 Hardware Interrupt Operation An internal resource that has the hardware interrupt request function has an interrupt request flag and interrupt enable flag. The interrupt request flag indicates whether an interrupt request exists, and the interrupt enable flag indicates whether the relevant internal resource requests an interrupt to the CPU. The interrupt request flag is set when an event occurs that is unique to the internal resource. When the interrupt enable flag indicates "enable", the resource issues an interrupt request to the interrupt controller. ■ Hardware interrupt operation When two or more interrupt requests are received at the same time, the interrupt controller compares the interrupt levels (IL) in ICR, selects the request at the highest level (the smallest IL value), then reports that request to the CPU. If multiple requests are at the same level, the interrupt controller selects the request with the lowest interrupt number. The relationship between the interrupt requests and ICRs is determined by the hardware. The CPU compares the received interrupt level and the ILM in the PS register. If the interrupt level is smaller than the ILM value and the I bit of the PS register is set to 1, the CPU activates the interrupt processing microcode after the currently executing instruction is completed. The CPU references the ISE bit of the ICR of the interrupt controller at the beginning of the interrupt processing microcode, checks that the ISE bit is 0 (interrupt), and activates the interrupt processing body. The interrupt processing body saves 12 bytes (PS, PC, PCB, DTB, ADB, DPR, and A) to the memory area indicated by SSB and SSP, fetches three bytes of interrupt vector and loads them onto PC and PCB, updates the ILM of PS to a level value of the received interrupt, sets the S flag, then performs branch processing. As a result, the interrupt processing program defined by the user is executed next. Figure 3.5-1 illustrates the flow from the occurrence of a hardware interrupt until there is no interrupt request in the interrupt processing program. 63 CHAPTER 3 INTERRUPTS 3.5.2 Occurrence and Release of Hardware Interrupt Figure 3.5-1 shows the processing flow from occurrence of a hardware interrupt to release of the interrupt request in an interrupt processing program. ■ Occurrence and release of hardware interrupt Figure 3.5-1 Occurrence and release of hardware interrupt PS F2MC-16LX bus Register file Microcode IR (6) I ILM Check F2M C - 1 6 LX . C P U (1) (2) Interrupt level IL AND Level comparator Enable FF (7) : : : : Processor status Interrupt enable flag Interrupt level mask register Instruction register (4) (3) Peripheral Cause FF Comparator (5) PS I ILM IR Interrupt controller (1) An interrupt cause occurs in a peripheral. (2) The interrupt enable bit in the peripheral is referenced. If interrupts are enabled, the peripheral issues an interrupt request to the interrupt controller. (3) Upon reception of the interrupt request, the interrupt controller determines the priority levels of simultaneously requested interrupts. Then, the interrupt controller transfers the interrupt level of the corresponding interrupt to the CPU. (4) The CPU compares the interrupt level requested by the interrupt controller with the ILM bit of the processor status register. (5) If the comparison shows that the requested level is higher than the current interrupt processing level, the I flag value of the same processor status register is checked. (6) If the check in step 5. shows that the I flag indicates interrupt enable status, the requested level is written to the ILM bit. Interrupt processing is performed as soon as the currently executing instruction is completed, then control is transferred to the interrupt processing routine. (7) When the interrupt cause of step 1. is cleared by software in the user interrupt processing routine, the interrupt request is completed. 64 CHAPTER 3 INTERRUPTS The time required for the CPU to execute the interrupt processing in steps 6. and 7. is shown below. Interrupt start: 24 + 6 × (Table 3.5-1 machine cycles) Interrupt return: 15 + 6 × (Table 3.5-1 machine cycles) RETI instruction Table 3.5-1 Compensation values for interrupt processing cycle count Address pointed to by the stack pointer Interpolation value [cycles] External 8-bit +4 External even-numbered address +1 External odd-numbered address +4 Internal even-numbered address 0 Internal odd-numbered address +2 65 CHAPTER 3 INTERRUPTS 3.5.3 Multiple interrupts As a special case, no hardware interrupt request can be accepted while data is being written to the I/O area. This is intended to prevent the CPU from operating falsely because of an interrupt request issued while an interrupt control register for a resource is being updated. If an interrupt occurs during interrupt processing, a higher-level interrupt is processed first. ■ Multiple interrupts The F2MC-16LX CPU supports multiple interrupts. If an interrupt of a higher level occurs while another interrupt is being processed, control is transferred to the high-level interrupt after the currently executing instruction is completed. After processing of the high-level interrupt is completed, the original interrupt processing is resumed. An interrupt of the same or lower level may be generated while another interrupt is being processed. If this happens, the new interrupt request is suspended until the current interrupt processing is completed, unless the ILM value or I flag is changed by an instruction. The extended intelligent I/O service cannot be activated from multiple sources; while an extended intelligent I/O service is being processed, all other interrupt requests or extended intelligent I/O service requests are suspended. Figure 3.5-2 shows the order of the registers saved in the stack. Figure 3.5-2 Registers saved in stack Word (16 bits) MSB LSB H SSP (SSP value before interrupt) AH AL DPR ADB DPB PCB PC PS L 66 SSP (SSP value after interrupt) CHAPTER 3 INTERRUPTS 3.6 Software Interrupts In response to execution of a special instruction, control is transferred from the program currently executed by the CPU to the interrupt processing program defined by the user. This is called the software interrupt function. A software interrupt occurs always when the software interrupt instruction is executed. ■ Software interrupts The CPU performs the following processing when a software interrupt occurs: • Saves the values in the PC, PS, AH, AL, PCB, DTB, ADB, and DPR registers of the CPU to the system stack. • Sets I in the PS register. Interrupts are automatically disabled. • Fetches the corresponding interrupt vector value, then branches to the processing indicated by that value. A software interrupt request issued by the INT instruction has no interrupt request or enable flag. A software interrupt request is always issued by executing the INT instruction. The INT instruction does not have an interrupt level. Therefore, the INT instruction does not update ILM. The INT instruction clears the I flag to suspend subsequent interrupt requests. ■ Structure of software interrupts Software interrupts are handled within the CPU: CPU.....Microcode: Interrupt processing step ■ List of interrupt vectors "Table D-1 Interrupt vectors" lists the interrupt vectors of the MB90350 series. As shown in "Table D-1 Interrupt vectors", software interrupts share the same interrupt vector area with hardware interrupts. For example, interrupt request number INT 12 is used for external interrupt #0 to #7 of a hardware interrupt as well as for INT #12 of a software interrupt. Therefore, external interrupt #0 and INT #12 call the same interrupt processing routine. ■ Software interrupt operation When the CPU fetches and executes the software interrupt instruction, the software interrupt processing microcode is activated. The software interrupt processing microcode saves 12 bytes (PS, PC, PCB, DTB, ADB, DPR, and A) to the memory area indicated by SSB and SSP. The microcode then fetches three bytes of interrupt vector and loads them onto PC and PCB, resets the I flag, and sets the S flag. Then, the microcode performs branch processing. As a result, the interrupt processing program defined by the user application program is executed next. Figure 3.6-1 illustrates the flow from the occurrence of a software interrupt until there is no interrupt request in the interrupt processing program. 67 CHAPTER 3 INTERRUPTS Figure 3.6-1 Occurrence and release of software interrupt (1) PS F2MC-16LX bus Register file (2) Microcode F 2 M C - 1 6 LX . C P U I S B unit IR Queue Fetch PS I ILM IR B unit : : : : : Processor status Interrupt enable flag Interrupt level mask register Instruction register Bus interface unit Save Instruction bus RAM (1) The software interrupt instruction is executed. (2) Special CPU registers in the register file are saved according to the microcode corresponding to the software interrupt instruction. (3) The interrupt processing is completed with the RETI instruction in the user interrupt processing routine. ■ Others When the program bank register (PCB) is FFH, the CALLV instruction vector area overlaps the table of the INT #vct8 instruction. When designing software, ensure that the CALLV instruction does not use the same address as that of the #vct8 instruction. Table D-2 shows the relationship of interrupt cause, interrupt vector, and interrupt control register in the MB90350 series. 68 CHAPTER 3 INTERRUPTS 3.7 Extended Intelligent I/O Service (EI2OS) The EI2OS function automatically transfers data between input and output and memory. An interrupt processing program was conventionally used for such processing, but EI2OS enables data transfer to be performed like DMA (direct memory access). ■ Extended intelligent I/O service (EI2OS) EI2OS has the following advantages over the conventional method: • The program size can be small because it is not necessary to write a transfer program. • No internal register is used for transfer, eliminating the need for register saving and increasing the transfer speed. • Transfer can be terminated from I/O, preventing unnecessary data from being transferred. • The buffer address may either be incremented or left unupdated. • The I/O register address may either be incremented or left unupdated. At the end of EI2OS, processing automatically branches to an interrupt processing routine after the end condition is set. Thus, the user can identify the end condition. To implement EI2OS, the hardware is distributed in two blocks. Each block has the following registers and descriptors. • Interrupt control register: Exists in the interrupt controller and indicates the ISD address. • Extended intelligent I/O service descriptor (ISD): Exists in RAM and holds the transfer mode, I/O address, number of transfers, and buffer address. Figure 3.7-1 outlines the extended intelligent I/O service. 69 CHAPTER 3 INTERRUPTS Figure 3.7-1 Outline of extended intelligent I/O service Memory space by IOA I/O register ••• ••• ••• ••• ••• I/O register Peripheral CPU Interrupt request (1) (3) ISD (3) by ICS (2) Interrupt control register Interrupt controller (1) I/O requests transfer. by BAP (2) The interrupt controller selects the descriptor. (4) Buffer by DCT (3) The transfer source and destination are read from the descriptor. (4) Data is transferred between I/O and memory. Note: The area that can be specified by IOA is between 000000H and 00FFFFH. The area that can be specified by BAP is between 000000H and FFFFFFH. The maximum transfer count that can be specified by DCT is 65,536. ■ Structure EI2OS is handled by the following four sections: Internal resources Interrupt enable and request bits: Used to control interrupt requests from resources. Interrupt controller ICR: Assigns interrupt levels, determines the priority levels of simultaneously requested interrupts, and selects the EI2OS operation. CPU I and ILM: Used to compare the requested and current interrupt levels and to identify the interrupt enable status Microcode: EI2OS processing step RAM Descriptor: Describes the EI2OS transfer information. 70 CHAPTER 3 INTERRUPTS 3.7.1 Extended Intelligent I/O Service Descriptor (ISD) The extended intelligent I/O service descriptor exists between 000100H and 00017FH in internal RAM, and consists of the following items: • Data transfer control data • Status data • Buffer address pointer ■ Extended intelligent I/O service descriptor (ISD) Figure 3.7-2 shows the configuration of the extended intelligent I/O service descriptor. Figure 3.7-2 Extended intelligent I/O service descriptor configuration H High-order 8 bits of data counter (DCTH) Low-order 8 bits of data counter (DCTL) High-order 8 bits of I/O address pointer (IOAH) Low-order 8 bits of I/O address pointer (IOAL) EI 2OS status (ISCS) High-order 8 bits of buffer address pointer (BAPH) 000100 H + 8 × ICS Medium-order 8 bits of buffer address pointer (BAPM) ISD start address Low-order 8 bits of buffer address pointer (BAPL) L ■ Data counter (DCT) This is a 16-bit register that works as a counter corresponding to the number of data items transferred. This counter is decremented by one before data transfer. EI2OS is terminated when this counter reaches 0. Figure 3.7-3 is a diagram of the data counter configuration. Figure 3.7-3 Data counter configuration 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B15 B14 B13 B12 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00 DCT (Undefined when reset) 71 CHAPTER 3 INTERRUPTS ■ I/O register address pointer (IOA) This is a 16-bit register that indicates the low-order address (A15 to A0) of the buffer and I/O register used for data transfer. The high-order address (A23 to A16) are all zeroes, and any I/O between addresses 000000H and 00FFFFH can be specified. Figure 3.7-4 is a diagram of the IOA configuration. Figure 3.7-4 I/O register address pointer configuration 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00 IOA (Undefined when reset) ■ Buffer address pointer (BAP) This 24-bit register holds the address used for the next EI2OS transfer. BAP exists for each EI2OS channel. Therefore, each EI2OS channel can be used for transfer with anywhere in the 16-Mbyte space. If the BF bit of ISCS is set to "0" (update enabled), only the low-order 16 bits of BAP changes and BAPH does not change. 72 CHAPTER 3 INTERRUPTS EI2OS Status Register (ISCS) 3.7.2 This eight-bit register indicates the update direction (increment/decrement), transfer data format (byte/word), and transfer direction of the buffer address pointer and the I/O register address pointer. This register also indicates whether the buffer address pointer or I/O register address pointer is updated or fixed. ■ EI2OS status register (ISCS) Figure 3.7-5 is a diagram of the ISCS configuration. Figure 3.7-5 ISCS configuration 7 6 5 Reserved Reserved Reserved 4 IF 3 2 1 0 BW BF DIR SE ISCS (Undefined when reset) Note: Always write 0 to bits 7 to 5 of ISCS. Each bit is described below. [bit 4] IF: Specify whether the I/O register address pointer is updated or fixed. 0: The I/O register address pointer is updated after data transfer. 1: The I/O register address pointer is not updated after data transfer. Note: Only increment is allowed. [bit 3] BW: Specify the transfer data length. 0: Byte 1: Word [bit 2] BF: Specify whether the buffer address pointer is updated or fixed. 0: The buffer address pointer is updated after data transfer. 1: The buffer address pointer is not updated after data transfer. Note: Only the low-order 16 bits of the buffer address are updated. Only increment is allowed. [bit 1] DIR: Specify the data transfer direction. 0: I/O --> Buffer 1: Buffer --> I/O [bit 0] SE: Control the termination of the extended intelligent I/O service based on resource requests. 0: The extended intelligent I/O service is not terminated by a resource request. 1: The extended intelligent I/O service is terminated by a resource request. 73 CHAPTER 3 INTERRUPTS 3.8 Operation Flow of and Procedure for Using the Extended Intelligent I/O Service (EI2OS) Figure 3.8-1 is a diagram of the EI2OS operation flow. Figure 3.8-2 is a diagram of the EI2OS use procedure. ■ EI2OS operation flow Figure 3.8-1 EI2OS operation flow BAP I/OA ISD ISCS DCT ISE S1 and S0 Interrupt request issued from internal resource ISE = 1 : : : : : : : Buffer address pointer I/O address pointer EI 2OS descriptor EI2 OS status Data counter EI2OS enable bit EI2OS end status NO Interrupt sequence YES Reading ISD/ISCS End request from resource YES SE = 1 NO DIR = 1 YES NO Data indicated by IOA ⇓ (Data transfer) Memory indicated by BAP IF = 0 YES NO BF = 0 Data indicated by BAP ⇓ (Data transfer) Memory indicated by IOA Update value depends on BW. Updating IOA Update value depends on BW. Updating BAP YES NO Decrementing DCT DCT = 00 YES NO Setting S1 and S0 to '01' Setting S1 and S0 to '11' Setting S1 and S0 to '00' 74 Clearing resource interrupt request Clearing ISE to '0' CPU operation return Interrupt sequence CHAPTER 3 INTERRUPTS Figure 3.8-2 EI2OS use flow Processing by EI2OS Processing by CPU EI2OS initialization JOB execution Normal termination (Interrupt request) AND (ISE = 1) Data transfer Re-setting of extended intelligent I/O service (Switching channels) Processing data in buffer The extended EI2OS execution time for each flow is described below. ● When data transfer continues (when the stop condition is not satisfied) (Table 3.8-1 + Table 3.8-2) machine cycles ● When a stop request is issued from a resource (36 + 6 × Table 3.8-3) machine cycles ● When the counting is completed (Table 3.8-1 + Table 3.8-2 + 21 + 6 * Table 3.8-3) machine cycles Table 3.8-1 Execution time when the extended EI2OS continues ISCS SE bit Set to "0" I/O address pointer Set to "1" Fixed Updated Fixed Updated Fixed 32 34 33 35 Updated 34 36 35 37 Buffer address pointer 75 CHAPTER 3 INTERRUPTS Table 3.8-2 Data transfer compensation values for extended EI2OS execution time Internal access I/O address pointer Buffer address pointer Internal access B/E O B/E 0 +2 O +2 +4 B: Byte data transfer E: Even address word transfer O: Odd address word transfer Table 3.8-3 Compensation values for interrupt handling times Address pointed to by the stack pointer Interpolation value [cycles] External 8-bit +4 External even-numbered address +1 External odd-numbered address +4 Internal even-numbered address 0 Internal odd-numbered address +2 76 CHAPTER 3 INTERRUPTS 3.9 µDMAC Interrupt µDMAC is a simplified DMA with the same function as EI2OS 3.9.1 µDMAC Functions 3.9.2 µDMAC Registers 3.9.3 DMA Descriptor window register (DDWR) 3.9.4 µDMAC Operation 77 CHAPTER 3 INTERRUPTS 3.9.1 µDMAC Functions This section describes the µDMAC functions. ■ µDMAC functions µDMAC function has the following functions: • Automatic data transfer between peripheral resources (I/O) and memory • CPU program execution stopped during starting of DMA • 16 DMA transfer channels (The smaller the channel number, the higher the DMA transfer priority .) • Allow selection of whether or not to increment the transfer source, transfer destination addresses. • DMA transfer started by peripheral resource (I/O) interrupts. • DMA transfer controlled by: (a) DMA enable register (DER), (b) DMA stop status register (DSSR), (c) DMA status register (DSR), (d) DMA descriptor channel specification register (DCSR), and (e) Descriptor (DMACS) • STOP requests are issued as a means to stop DMA transfers from a peripheral resource. • After the end of a DMA transfer, a flag is set to the bit corresponding to the transfer end channel of the DMA status register, and an end interrupt is then output to the interrupt controller. 78 CHAPTER 3 INTERRUPTS 3.9.2 µDMAC Registers µDMAC has four registers: DCSR, DSR, DSSR, and DER. The DMA descriptor used to set DMA transfer is explained in Section "3.9.3 DMA Descriptor window register (DDWR)". ■ Registers List · DMA descriptor channel specification register (DCSR) 15 Address: 00009B H Read/write Initial value 14 13 12 11 10 9 8 STPctrl Reserved Reserved Reserved DCSR3 DCSR2 DCSR1 DCSR0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Bit No. DCSR (R/W) 00000000B · DMA status register (DSR) 15 14 13 12 11 10 9 8 Address: 00009D H Read/write Initial value DTE15 DTE14 DTE13 DTE12 DTE11 DTE10 DTE9 7 6 5 4 3 2 1 0 Address: 00009C H Read/write Initial value DTE7 DTE6 DTE5 DTE4 DTE3 DTE2 DTE1 DTE0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) DTE8 Bit No. DSRH (R/W) 00000000B Bit No. DSRL 00000000B · DMA stop status register (DSSR) 15 14 13 12 11 10 9 8 Bit No. DSSR Address: 0000A4 H Read/write Initial value STP15 STP14 STP13 STP12 STP11 STP10 STP9 7 6 5 4 3 2 1 0 Bit No. Address: 0000A4 H Read/write Initial value STP7 STP6 STP5 STP4 STP3 STP2 STP1 STP0 DSSR (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) STP8 (R/W) 00000000B Bit 8 to 15 are used for DSSR when DCSR:STPctrl bit is "0", while bit 0 to 7 are used when the bit is "1". 00000000B · DMA enable register (DER) 15 14 13 12 11 10 9 8 Address: 0000AD H Read/write Initial value EN15 EN14 EN13 EN12 EN11 EN10 EN9 EN8 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 7 6 5 4 3 2 1 0 Address: 0000AC H Read/write Initial value EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Bit No. DERH 00000000B Bit No. DERL 00000000B 79 CHAPTER 3 INTERRUPTS 3.9.2.1 DMA descriptor channel specification register (DCSR) This section describes the DMA descriptor channel specification register (DCSR). ■ DMA descriptor channel specification register (DCSR) Figure 3.9-1 DMA descriptor channel specification register (DCSR) configuration 15 Address: 00009B H Read/write Initial value 14 13 12 11 10 9 8 STPctrl Reserved Reserved Reserved DCSR3 DCSR2 DCSR1 DCSR0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Bit No. DCSR (R/W) 00000000B [bit 11 to 8] DCSRx: DMA Descriptor Channel Specification Table 3.9-1 Relationship between DCSR and Selected Channels DCSR3 to 0 Selected Channels Resource Interrupt Request 0000 0 16-bit Reload Timer 0 0001 1 16-bit Reload Timer 1 0010 2 16-bit Reload Timer 2 0011 3 External Interrupt 8 to 11 0100 4 External Interrupt 12 to 15 0101 5 A/D Converter 0110 6 Input Capture 4/5 0111 7 Output Compare 4/5 1000 8 Input Capture 0/1 1001 9 Output Compare 6/7 1010 10 Reserved 1011 11 Reserved 1100 12 UART3 RX 1101 13 UART3 TX 1110 14 UART2 RX 1111 15 UART2 TX One (descriptor channel) of 16 channels is selected by the DCSR setting. For details, see Section "3.9.3 DMA Descriptor window register (DDWR)". 80 CHAPTER 3 INTERRUPTS [bit 15] STPctrl: STP Control Bit STPctrl bit Function 0 [Initial value] STP8 to 15 are selected as DSSR. 1 STP0 to 7 are selected as DSSR. [bit 14 to 12] Reserved: Reserved Bits Bit 12 to 14 (three bits) are reserved bits, so bit manipulation instructions cannot be executed for them. When setting DSCR, always write “0” to these bits. Reading these bits always returns “0”. 81 CHAPTER 3 INTERRUPTS 3.9.2.2 DMA status register (DSR) This section describes the DMA status register (DSR). ■ DMA status register (DSR) Figure 3.9-2 DMA status register (DSR) configuration 15 Address: 00009D H Read/write Initial value Address: 00009C H Read/write Initial value 14 13 12 11 10 9 DTE15 DTE14 DTE13 DTE12 DTE11 DTE10 DTE9 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 8 DTE8 (R/W) 00000000B 7 6 5 4 3 2 1 0 DTE7 DTE6 DTE5 DTE4 DTE3 DTE2 DTE1 DTE0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 0 [Initial value] 1 Function Indicates no interrupt request present. When DTEx is “0”, write “0” to this bit. Writing “1” to it is prohibited. Indicates that DMA transfer completed and interrupt requested. When DTEx is “1”, writing “0” to this bit clears it to “0”; writing “1” to it retains the previous data. Note: For write access to this register, always use a read-modify-write instruction. 82 Bit No. DSRL 00000000B [bit 15 to 0] DTEx: DMA Status DTEx bit Bit No. DSRH CHAPTER 3 INTERRUPTS 3.9.2.3 DMA stop status register (DSSR) This section describes the DMA stop status register (DSSR) ■ DMA stop status register (DSSR) Figure 3.9-3 DMA stop status register (DSSR) configuration (When DCSR:STPctrl=0) Address: 0000A4 H Read/write Initial value (When DCSR:STPctrl=1) Address: 0000A4 H Read/write Initial value 15 14 13 12 11 10 9 STP15 STP14 STP13 STP12 STP11 STP10 STP9 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 8 STP8 Bit No. DSSR (R/W) 00000000B 7 6 5 4 3 2 1 0 Bit No. STP7 STP6 STP5 STP4 STP3 STP2 STP1 STP0 DSSR (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 00000000B [bit 15 to 0] STPx: DMA Stop Status STPx bit 0 [Initial value] 1 Function No STOP request is accepted in a DMA transfer. When STPx is “0”, write “0” to this bit. Writing “1” to it is prohibited. Indicates that DMA transfer stopped due to STOP request issued by resource during DMA transfer. When the DMA control register SE bit is “1” and the corresponding channel receives the STOP request, the corresponding bit of the DMA enable register is cleared to “0”. When STPx is “1”, writing “0” to this bit clears it to “0”; writing “1” retains the previous data. Note: DSSR is controlled by the MSB of DCSR (STPctrl). When STPctrl is "0", bit 8 to 15 are selected as DSSR; when STPctrl is “1”, bit 0 to 7 are. Since the initial value of STPctrl is “0”, bit 8 to 15 are selected as DSSR at first. When writing to DSSR, use an RMW (read-modify-write) instruction. The following two channels supports the STOP request: Channels Corresponding STPx bits Resource ch12 STP12 UART3RX ch14 STP14 UART2RX Note: Bits other than STP12, and STP14 have no meaning. 83 CHAPTER 3 INTERRUPTS 3.9.2.4 DMA enable register (DER) This section describes DMA enable register (DER). ■ DMA enable register (DER) Figure 3.9-4 DMA enable register (DER) configuration Address: 0000AD H Read/write Initial value Address: 0000AC H Read/write Initial value 15 14 13 12 11 10 9 8 EN15 EN14 EN13 EN12 EN11 EN10 EN9 EN8 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 00000000B 7 6 5 4 3 2 1 0 EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Bit No. DERL 00000000B [bit 15 to 0] ENx: DMA Enable ENx bit Function 0 [Initial value] The interrupt request from the resource is output to the interrupt controller. (The interrupt request from the resource is not processed as a DMA start request.) 1 The interrupt request from the resource is processed as a DMA start request. At completion of DMA transfer, the interrupt request is output to the interrupt controller. This bit is cleared to “0” when the DMA transfer byte count becomes “0” or when DMA transfer is stopped by the STOP request from the resource. Note: When writing to DER, use an RMW (read-modify-write) instruction. Before entering the sleep mode, these bits must be cleared to "0". 84 Bit No. DERH CHAPTER 3 INTERRUPTS 3.9.3 DMA Descriptor window register (DDWR) The DMA descriptor consists of 8 bytes x 16 channels and is used to set DMA transfer. One channel selected from the 16 channels is mapped to the DMA descriptor window register (DDWR), making it possible to access this channel. DDWR addresses are “0000D0H” to “0000D7H”. ■ Configuration of DMA Descriptor window register (DDWR) The DMA descriptor consists of 8 bytes x16 channels and the structure of each channel is as shown in Figure 3.9-5 The descriptor for the channel selected by the DMA descriptor channel specification register (DCSR) or by the interrupt request channel number is mapped onto the DMA descriptor window register (DDWR). For the relationship between the DMA descriptor channel specification register (DCSR) and the channels to be selected, see Table 3.9-1. Figure 3.9-5 Configuration of DMA Descriptor Window Register (DDWR) Address 0000D7H Upper 8 bits of data counter (DCTH) 0000D6H Lower 8 bits of data counter (DCTL) 0000D5H Upper 8 bits of I/O Register address pointer (IOAH) 0000D4H Lower 8 bits of I/O Register address pointer (IOAL) 0000D3H DMA Control register (DMACS) 0000D2H Upper 8 bits of buffer address pointer (BAPH) 0000D1H Middle 8 bits of buffer address pointer (BAPM) 0000D0H Lower 8 bits of buffer address pointer (BAPL) 85 CHAPTER 3 INTERRUPTS ■ Each Register of DMA Descriptor Each register making up the DMA descriptor is explained in the following sections. The registers must be initialized before setting ENx to “1” because their initial values become undefined when they are reset. Note: Access to the DDWR register is not allowed over 2 machine clock cycles after the setting of the DCSR register is changed. 86 CHAPTER 3 INTERRUPTS 3.9.3.1 Data counter (DCT) This section describes the Data counter (DCT). ■ Data counter (DCT) The data counter (DCT) is a 16-bit register to store the transfer count. After each data transfer, the data counter is decremented by 1 irrespective of whether the transfer is word or byte transfer. When the data counter becomes “0”, DMA transfer ends. Figure 3.9-6 shows the configuration of the data counter (DCT). When “0” is set to DCT, the maximum data transfer count (65536) is set. Figure 3.9-6 Data Counter (DCT) Configuration DCTH 15 14 13 12 11 DCTL 10 09 08 07 06 05 04 03 02 01 00 Bit No. Address: DCT 0000D7H/0000D6H B15 B14 B13 B12 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00 Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value XXXXXXXXXXXXXXXX B R/W: Read/write X: Undefined ■ Value in Data Counter The following table explains the relationship between the number of bytes and the value in the DCT register. DMACS register DCT register BW bit BYTEL bit 0 2 N 1 0 N/2 1 1 (N+1)/2 N: Number of bytes 87 CHAPTER 3 INTERRUPTS 3.9.3.2 I/O register address pointer (IOA) This section describes the I/O register address pointer (IOA). ■ I/O register address pointer (IOA) The I/O register address pointer (IOA) is a 16-bit register and indicates the lower addresses (A15 to A00) of the I/O register. Its upper addresses (A23 to A16) are all “0”, allowing any I/O address space in the range from the “000000H” address to the “00FFFFH” address to be specified. When “Update Performed” is specified with the IF bit (this bit selects whether to update IOA or fix IOA) of the DMA control register (DMACS), IOA is incremented by 1 at byte transfer; and incremented by 2 at word transfer. When “Update Not Performed” is specified with the IF bit, IOA is fixed (IOA does not change). Figure 3.9-7 shows the configuration of the data counter (IOA). Figure 3.9-7 I/O Register Address Pointer (IOA) Configuration IOAH IOAL 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Bit No. Address: IOA 0000D5H/0000D4H A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Read/write Initial value XXXXXXXXXXXXXXXXB R/W: Read/write X: Undefined 88 CHAPTER 3 INTERRUPTS 3.9.3.3 DMA control register (DMACS) This section describes the DMA control register (DMACS). ■ DMA control register (DMACS) The DMA control register (DMACS) is 8-bit long and is used to specify whether to update or fix the buffer address pointer and the I/O register address pointer, to specify the transfer data format (byte or word), to specify the transfer direction, to specify byte transfer, and to issue wait instructions. Figure 3.9-8 shows the configuration of DMACS. Figure 3.9-8 Configuration of DMACS 7 Address: 0000D3H Read/write 6 5 RDY2 RDY1 BYTEL R/W R/W R/W 4 3 2 1 0 IF BW BF DIR SE R/W R/W R/W R/W R/W DMA transfer end control bit 0 DMA transfer can not be stopped by a request from a peripheral function. 1 DMA transfer can be stopped by a request from a peripheral function. Data transfer direction specification bit 0 I/O register address pointer 1 Buffer address pointer BF Buffer address pointer I/O register address pointer BAP update/fix selection bit 0 After data transfer, the buffer address pointer is updated. 1 After data transfer, the buffer address pointer is not updated. BW Transfer data length specification bit 0 Byte 1 Word IF IOA update/fix selection bit 0 After data transfer, the I/O register address pointer is updated. 1 After data transfer, the I/O register address pointer is not updated. BYTEL Byte transfer specification bit (only enabled for word transfer) 0 Even number of bytes 1 Odd number of bytes (RDY2, RDY1) X: Undefined XXXXXXXXB SE DIR R/W: Read/write Bit No. Initial value Wait instruction bits (see Figure 3.9-9.) (0, 0) No wait is inserted between transfers. (0, 1) A 1-cycle wait is inserted between transfers. (1, 0) A 2-cycle wait is inserted between transfers. (1, 1) A 3-cycle wait is inserted between transfers. 89 CHAPTER 3 INTERRUPTS Figure 3.9-9 Explanation of Wait Instruction Bits source destination wait source destination The wait in the data transfer shown in the above figure is defined using the RDY2 and RDY1 bits. Note: If writing transmission data to LIN-UART by using µDMAC, not setting RDY2 and RDY1 bit of DMACS register in (0, 0). 90 CHAPTER 3 INTERRUPTS 3.9.3.4 Buffer address pointer (BAP) This section describes the Buffer address pointer (BAP). ■ Buffer address pointer (BAP) The buffer address pointer (BAP) is a 24-bit register and is used to store addresses that will be used for DMA transfer. There is an independent BPA for each DMA channel, so each DMA channel can transfer data between any address in the 16-MByte address space and I/O. When "Update Performed" is specified using the BF bit (selects whether to update BAP or fix BAP) of the DMA control register (DMACS), the BAP lower 16 bits (BAPM, BAPL) are incremented by "1" at byte transfer and incremented by "2" at word transfer. Its upper 8 bits do not change. Figure 3.9-10 shows the configuration of the buffer address pointer (BAP). Figure 3.9-10 Buffer Address Pointer (BAP) Address: 0000D2H /0000D1H /0000D0H Read/write Initial value 23 to 16 15 to 08 07 to 00 BAPH BAPM BAPL (R/W) (R/W) (R/W) Bit No. BAP XXXXXXXXXXXXXXXXXXXXXXX B R/W: Read/write X: Undefined Notes: • The area that can be specified using the I/O register address pointer (IOA) is "000000H" to "00FFFFH". • The area that can be specified using the buffer address pointer (BAP) is "000000H" to "FFFFFFH. • The following may not be specified for IOA and BAP: addresses of µDMA internal registers (DCSR, DSRH, DSRL, DSSR, DERH, DERL); addresses of DMA descriptor window register (DDWR). 91 CHAPTER 3 INTERRUPTS 3.9.4 µDMAC Operation This section describes the µDMAC operation. ■ DMAC Operation Figure 3.9-11 shows the DMAC operation. Data transfer using DMAC is performed in the following order: (1) The peripheral resource (I/O) requests DMA transfer. (2) When the corresponding bit of DMA enable register (DER) is "1", DMAC reads from the descriptor the transfer data such as the transfer source address, transfer destination address, and transfer count of specified channels. (3) DMA data transfer is started between I/O and memory. (4) After one item (either Byte data or Word data) transferred (a) Transfer has not been completed (DCT does not reached to 0): µ DMAC requests to clear the DMA transfer request to the peripheral resource. (b) At transfer end (DCT reached to 0): After completion of DMA transfer, the flag indicating completion of transfer is set in the DMA status register, outputting an interrupt request to the interrupt controller. Note: Write access to the internal registers DCSR, DSRH, DSRL, DSSR, DERH, and DERL is prohibited during DMA transfer. 92 CHAPTER 3 INTERRUPTS Figure 3.9-11 DMAC Operation Memory space IOA I/O register I/O register Peripheral function (I/O) RAM for descriptor (1) (4) (a) (2) (3) DMA controller DMA descriptor (2) (4) (b) BAP Buffer CPU Interrupt controller IOA: I/O address pointer BAP: Buffer address pointer DER: DMA enable register DCT: Data counter DCT 93 CHAPTER 3 INTERRUPTS ■ Procedure for using DMAC Figure 3.9-12 illustrates the procedure for using DMAC. Figure 3.9-12 Procedure for Using DMAC Hardware processing Software processing (Interrupt generating) Start ENx=1 of Corresponding ch Set the system stack area. Initialize Yes STOP request and SE=1 Initialize the peripheral function. No DMA transfer Set the interrupt control register. (BAP) Initialize the µDMAC controller. BF=0 (IOA) Parallel processing No BW=1 No No IF=0 No BW=1 Execute the user program. BYTEL=0 Yes No BAP=BAP+2 No No BYTEL=0 No Yes DCT=0 Yes Yes IOA=IOA+2 IOA=IOA+1 BAP=BAP+1 DCT=0 STPx=1 DCT=0 NO DTEx=0 (Jump to interrupt routine.) ENx=0 * Interrupt Interrupt processing Other Interrupt Processing end ENx : Corresponding bit of DMA enable register DTEx : Corresponding bit of DMA status register STPx : Corresponding bit of DMA stop status register * : Outputting interrupt request to interrupt controller 94 Yes NO Yes CHAPTER 3 INTERRUPTS ■ Data Transfer Cycle Count (internal transfer) When µDMAC retains the bus right and executes data transfer in LSI, transfer cycle count is following. Table 3.9-2 Transfer start from retaining of bus right When matching DCSR3 to 0 of DCSR and interrupt request channel When not matching DCSR3 to 0 of DCSR and interrupt request channel 1 machine cycle 2 machine cycles Table 3.9-3 Transfer cycles Address pointer DMACS Cycle count BAP IOA BW BYTEL - - 0 - 4 + (RDY2, RDY1)*1 machine cycle Odd Even 1 - Even Odd 6 + (RDY2, RDY1)*2 machine cycle Odd Odd 1 - 8 + (RDY2, RDY1)*2 machine cycle Even Even 1 - 4 + (RDY2, RDY1)*1 machine cycle *1: At the last transfer, (RDY2, RDY1) is 0. *2: BYTEL = 1: 4 cycles, (RDY2, RDY1) is 0. BYTEL = 0: (RDY2, RDY0) is 0. Odd : Odd address Even: Even address 95 CHAPTER 3 INTERRUPTS 3.10 Exceptions The F2MC-16LX performs exception processing when the following event occurs: ■ Execution of an undefined instruction Exception processing is fundamentally the same as interrupt processing. When an exception is detected between instructions, exception processing is performed separately from ordinary processing. In general, exception processing is performed as a result of an unexpected operation. Fujitsu recommends using exception processing only for debugging or for activating emergency recovery software. ■ Exception due to execution of an undefined instruction The F2MC-16LX handles all codes that are not defined in the instruction map as undefined instructions. When an undefined instruction is executed, processing equivalent to the INT 10 software interrupt instruction is performed. Specifically, the AL, AH, DPR, DTB, ADB, PCB, PC, and PS values are saved into the system stack, and processing branches to the routine indicated by the interrupt number 10 vector. In addition, the I flag is cleared and the S flag is set. The PC value saved in the stack is the address at which the undefined instruction is stored. Processing can be restored by the RETI instruction, but is of no use, however, because the same exception occurs again. 96 CHAPTER 4 DELAYED INTERRUPT This chapter explains the functions and operations of the delayed interrupt. 4.1 Outline of Delayed Interrupt Module 4.2 Delayed Interrupt Register 4.3 Delayed Interrupt Operation 97 CHAPTER 4 DELAYED INTERRUPT 4.1 Outline of Delayed Interrupt Module The delayed interrupt source module is used to generate interrupts for switching tasks. Using this module, interrupt requests to the F2MC-16LX CPU can be issued and canceled by software. ■ Block diagram of delayed interrupt Figure 4.1-1 is a block diagram of the delayed interrupt source module. Figure 4.1-1 Block diagram F2MC-16LX Delayed interrupt cause issuance/cancellation decoder Cause latch ■ Notes on operation The delayed interrupt signal is activated by writing "1" to the corresponding bit of DIRR and inactivated by writing "0" to the same bit. Therefore, the interrupt bit in DIRR should be cleared to "0" within the interrupt service routine. Otherwise the same interrupt is serviced again right after the first interrupt service is completed. 98 CHAPTER 4 DELAYED INTERRUPT 4.2 Delayed Interrupt Register DIRR controls issuance and cancellation of delayed interrupt requests. Writing "1" to this register issues a delayed interrupt request, and writing "0" cancels the delayed interrupt request. Upon a reset, the request is canceled. ■ Delayed interrupt cause issuance/cancellation register (DIRR: delayed interrupt request register) Figure 4.2-1 Delayed Interrupt Cause/Cancel Register (DIRR) Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 00009F H R/W X - : : : bit8 - - - - - - - R0 - - - - - - - R/W Initial value XXXXXXX0B Readable and writable Undefined Undefined bit Table 4.2-1 Functional Explanation of Each Bit of the Delayed Interrupt Cause/Cancel Register (DIRR) Bit name Function bit15 to bit9 -: Undefined bit • When these bits are read, the values are undefined. • Writing to these bits does not affect operation. bit8 R0: Delayed interrupt request output bit • • • • This bit sets the generation/cancel of a delayed interrupt request. When this bit is "1", a delayed interrupt request is output. When this bit is "0", the delayed interrupt request is cleared. When a reset is specified, interrupt causes are canceled (cleared to "0"). 99 CHAPTER 4 DELAYED INTERRUPT 4.3 Delayed Interrupt Operation When the CPU writes "1" to the relevant bit of DIRR by software, the request latch in the delayed interrupt source module is set and an interrupt request is issued to the interrupt controller. ■ Delayed interrupt occurrence When the CPU writes “1” to the relevant bit of DIRR by software, the request latch in the delayed interrupt source module is set and an interrupt request is issued to the interrupt controller. If this interrupt has the highest priority or if there is no other interrupt request, the interrupt controller issues an interrupt request to the F2MC-16LX CPU. The F2MC-16LX CPU compares the ILM bit of its internal CCR register and the interrupt request, and starts the hardware interrupt processing microprogram as soon as the current instruction is completed if the interrupt level of the request is higher than that of the ILM bit. The interrupt processing routine for this interrupt is thus executed. Figure 4.3-1 Delayed interrupt issuance Delayed interrupt source module Interrupt controller F2MC-16LX CPU WRITE Other requests ICR yy IL CMP CMP DIRR ICR xx ILM INTA 100 CHAPTER 5 CLOCKS This chapter explains the clocks used by MB90350 series microcontrollers. 5.1 Clocks 5.2 Block Diagram of the Clock Generation Block 5.3 Clock Selection Registers 5.4 Clock Mode 5.5 Oscillation Stabilization Wait Interval 5.6 Connection of an Oscillator or an External Clock to the Microcontroller 101 CHAPTER 5 CLOCKS 5.1 Clocks The clock generation block controls the operation of the internal clock that controls operation of the CPU and peripheral functions. This internal clock is called the machine clock. One internal clock cycle is called one machine cycle. Other clocks include a clock generated by source oscillation, called an oscillation clock, and a clock generated by the internal PLL oscillation, called a PLL clock. ■ Clocks The clock generation block contains the oscillation circuit that generates the oscillation clock. An external oscillator is attached to this circuit. The oscillation clock can also be supplied by inputting an external clock to the clock generation block. The clock generation block also contains the PLL clock multiplier circuit, which generates five clocks whose frequencies are multiples of the oscillation clock frequency. The clock generation block controls the oscillation stabilization wait interval and PLL clock multiplication as well as internal clock operation by changing the clock with a clock selector. ● Oscillation clock (HCLK) The oscillation clock is generated either from an external oscillator attached to the oscillation circuit or by the input of an external clock. ● Subclock (SCLK) The subclock runs the watch timer and can also be used as a low-speed machine clock. The subclock is generated either from an external oscillator attached to the oscillation circuit or by the input of an external clock. Frequency of the subclock is oscillation clock frequency divided by 2 or 4. The division ratio is determined by SCDS bit of PLL/Subclock Control Register (PSCCR). ● Main clock (MCLK) The main clock, whose frequency is the oscillation clock frequency divided by 2, supplies the clock input to the timebase timer and the clock selector. ● PLL clock (PCLK) The PLL clock is obtained by multiplying the oscillation clock frequency with the internal PLL clock multiplier circuit (PLL oscillation circuit). Selection can be made from among five different PLL clocks. 102 CHAPTER 5 CLOCKS ● Machine clock (φ) The machine clock controls the operation of the CPU and peripheral functions. One clock cycle is regarded as one machine cycle (1/φ). An operating machine clock can be selected from among the main clock (whose frequency is the source clock frequency divided by 2) and the other five clocks (whose frequencies are multiples of the source clock frequency). Note: When the operating voltage is 5V, the OSC source oscillation can be between 16MHz and 3MHz. When an external clock source is used, its frequency can be between 3MHz and 24MHz. The highest operating frequency for the CPU and peripheral resource circuits is 24MHz, however. Normal operation is not guaranteed if a multiplication factor resulting in a higher frequency than 24MHz is specified. For example, if the external clock frequency is 16MHz, only 1 can be specified as the multiplication factor. The lowest operating frequency of the VCO oscillation is 4MHz, and an oscillation below 4MHz must not be specified. ■ Clock Supply Map Since the machine clock generated in the clock generation block is supplied as the clock that controls the operation of the CPU and peripheral functions, the operation of the CPU and the peripheral functions is affected by switching between the main clock, the PLL clock and the subclock (clock mode) and by a change in the PLL clock multiplier. Since some peripheral functions receive frequency-divided output from the timebase timer, a peripheral unit can select the clock best suited for this operation. Figure 5.1-1 shows the clock supply map. 103 CHAPTER 5 CLOCKS Figure 5.1-1 Clock supply map Peripheral function 4 Watch timer Watchdog timer 4 Timebase timer 1 Clock generation block X1A 3 4 8/16-bit PPG timer 0 to F 6 16-bit reload timer 0 to 3 PLL multiplier circuit X0A Pin 2 Divideby-4/2 CAN0 to CAN2 Clock Selector c A/D converter (24ch) X0 X1 Pin PPG0 to F Pin TIN0 to 3 Pin TOT0 to 3 Pin RX0 to RX2 Pin TX0 to TX2 Pin AN0 to AN23 Pin SCK0 to 4 PCLK (PLL clock) Clock generation circuit Pin Pin Pin Clock generation circuit HCLK Divideby-2 (Oscillation clock) Clock Selector MCLK (Main clock) UART0 to 4 + Serial I/O (Machine clock) Pin SIN0 to 4 Pin SOT0 to 4 Pin OUT4 to OUT7 Pin IN0, IN1, IN4 to IN7 Pin SDA0, SDA1 Pin SCL0, SCL1 Pin CKOT I/O timer Output compare 4 to 7 mDMA Free-runnig timer 0, 1 CPU Input capture 0, 1, 4 to 7 I2C 0/1 HCLK MCLK PCLK SLLK c 104 : Oscillation clock : Main clock : PLL clock : Sub clock : Machine clock : CAN0 to CAN2 clock Clock monitor 4 Oscillation stabilization wait control CHAPTER 5 CLOCKS 5.2 Block Diagram of the Clock Generation Block The clock generation block consists of five blocks: • System clock generation circuit • PLL multiplier circuit • Clock selector • Clock selection register (CKSCR) • Oscillation stabilization wait interval selector ■ Block Diagram of the Clock Generation Block Figure 5.2-1 shows a block diagram of the clock generation block. Figure 5.2-1 Block Diagram of the Clock Generation Block Low Power Consumption Mode Control Register (LPMCR) STP SLP SPL RST TMD CG1 CG0 RESV CPU intermittend operation cycle selector 2 CPU clock control circuit CPU operation clock Sleep signal Stop signal Peripheral clock control circuit Peripheral function operation clock S Q S R Reset S Q R Q S Q Interrupt R R Standard Control Circuit Clock Selector Oscillation stabilization wait time interval selector 2 CS2 Bit8 of PLL/ Subclock control register(PSCCR) 2 SCM MCM WS1 WS0 SCS MCS CS1 CS0 PLL multiplier circuit Clock Selection register (CKSCR) Mainclock X0 Pin HCLK X1 Divideby-512 Divideby-2 Pin Divideby-2 Divideby-2 Divideby-2 Divideby-2 Divideby-2 Divideby-4 Timebase Timer System clock generation circuit Watchdog Timer Subclock generation circuit X0A Pin Divideby-4 Divideby 4 or 2 Watch Timer Subclock Divideby-1024 Divideby-8 Divideby-2 Divideby-2 X1A Pin SCDS Bit10 of PLL/ Subclock control register(PSCCR) 105 CHAPTER 5 CLOCKS ● Oscillation clock generation circuit The oscillation clock generation circuit generates an oscillation clock (HCLK) from an external oscillator attached to it. Alternatively, an external clock can be input to this circuit. ● Subclock generation circuit The subclock generation circuit generates a subclock (SCLK) from an external oscillator attached to it. An external clock can be also input to this circuit. ● PLL multiplier circuit The PLL multiplier circuit multiplies the oscillation clock frequency through PLL oscillation and supplies a clock whose frequency is a multiple of the oscillation clock frequency to the CPU clock selector. ● Clock selector From among the main clock, subclock and five different PLL clocks and subclock, the clock selector selects the clock that is supplied to the CPU and peripheral clock control circuits. ● Clock selection register (CKSCR) The clock selection register is used to switch between the main clock and PLL clocks and subclock also used to select an oscillation stabilization wait interval and a PLL clock multiplier. ● PLL/subclock control register (PSCCR) The PLL/subclock control register is used to select multiplication factor of the PLL (CS2 bit in this register in addition to CS1 and CS0 bit in the CKSCR register) and to specify division factor (1/4 or 1/2) of the subclock. ● Oscillation stabilization wait interval selector This oscillation stabilization wait interval selector selects an oscillation stabilization wait interval for the oscillation clock when the stop mode is released or when a watchdog timer reset occurs. Selection is made from among three different timebase timer outputs. In all other cases, an oscillation stabilization wait interval is not selected. 106 CHAPTER 5 CLOCKS 5.3 Clock Selection Registers This section lists the clock selection registers and describes the function of each register in details. ■ Clock Selection Registers Figure 5.3-1 shows the clock selection register (CKSCR) and PLL/Subclock Control Register (PSCCR) Figure 5.3-1 Clock selection registers 15 Address: 0000A1H Read/write Address: 0000CFH Read/write Bit No. CKSCR 14 13 12 11 10 9 8 SCM MCM WS1 WS0 SCS MCS CS1 CS0 (R) (R) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 15 14 13 12 11 10 9 8 Reserved SCDS Reserved CS2 Bit No. PSCCR (W) (W) (W) (W) Initial value ( ) ( ) ( ) ( ) Initial value 11111100B XXXX0000 B R/W : Readable and writable R : Read only W : Write only X : Undefined value : Undefined 107 CHAPTER 5 CLOCKS 5.3.1 Clock Selection Register (CKSCR) The clock selection register (CKSCR) is used to switch between the main clock and a PLL clock and subclock, also used to select an oscillation stabilization wait interval and a PLL clock multiplier. ■ Configuration of the Clock Selection Register (CKSCR) Figure 5.3-2 shows the configuration of the clock selection register (CKSCR). Table 5.3-1 describes the function of each bit of the clock selection register (CKSCR). Figure 5.3-2 Configuration of the Clock Selection Register (CKSCR) Address 0000A1H bit15 bit13 bit12 bit11 bit10 bit9 bit8 SCM MCM WS1 WS0 SCS MCS CS1 CS0 R/W R/W R/W R/W R/W R bit14 R R/W bit7 bit0 Initial value (LPMCR) 11111100B CS2 (PSCCR register: bit8) bit9 bit8 CS2 CS1 CS0 0 0 0 0 1 1 0 0 1 1 1 1 0 1 0 1 0 1 Multiplier selection bits The resulting fregaenay for an oscillation clock (HCLK)of 4 MHz in the parentheses. 1 x HCLK (4MHz) 2 x HCLK (8MHz) 3 x HCLK (12MHz) 4 x HCLK (16MHz) 6 x HCLK (24MHz) Setting prohibited. Machine clock selection bit MCS 0 PLL clock selected. 1 Main clock selected. Machine clock selection bit (sub) SCS 0 1 Subclock selected. Main clock selected. Oscillation stabilization wait interval selection bits WS1 WS0 The corresponding time interval for an oscillation clock of 4 MHz is given in parentheses. 0 0 210/ HCLK(approx. 256 µs) 0 1 213/ HCLK (aprox. 2.05 ms) 1 0 217/ HCLK (aprox. 32.77 ms) 1 1 215/ HCLK (aprox. 8.19 ms)* *: When a power-on reset occurs, the oscillation stabilization wait time is 216/HCLK (aprox. 16.38 ms). MCM 0 Machine clock indication bit Running on a PLL clock. 1 Running on the main clock. SCM HCLK : Oscillation clock R/W : Read/write : Read only R : Initial value 108 0 1 Machine clock indication bit (sub) Running on the subclock. Running on the main clock. CHAPTER 5 CLOCKS Note: The machine clock selection bit is initialized to main clock selection at a reset. Table 5.3-1 Function Description of Each Bit of the Clock Selection Register (CKSCR) (1/3) Bit name bit 15 SCM: Machine clock indication bit (sub) Function • • • bit 14 MCM: Machine clock indication bit • • • bit 13 bit 12 WS1 and WS0: Oscillation stabilization wait interval selection bits This bit indicates whether the main clock or subclock has been selected as the machine clock. When this bit is "0", the subclock has been selected. When it is "1", the main clock has been selected. If SCS = 1 and SCM = 0, the main clock oscillation stabilization wait interval is in effect. This bit indicates whether the main clock or a PLL clock has been selected as the machine clock. When this bit is 0, a PLL clock has been selected. When it is 1, the main clock has been selected. If MCS = 0 and MCM = 1, the PLL clock oscillation stabilization wait interval is in effect. • These bits select an oscillation stabilization wait interval of the oscillation clock when stop mode was released, when transition occurred from subclock mode to main clock mode, or when transition occurred from subclock mode to PLL clock mode. • These bits are initialized to "11B" by all reset causes. Note: The oscillation stabilization wait interval must be set to a value appropriate for the oscillator used. See Section , "6.2 Reset Cause and Oscillation Stabilization Wait Times". These bits can be reset to "00B" only for main clock mode. Reference: When main clock mode is switched to PLL clock mode, the oscillation stabilization wait interval is fixed at 214/HCLK (that is, the oscillation stabilization wait interval is approximately 4.1 ms when the oscillation clock frequency is 4 MHz). When subclock mode is switched to PLL clock mode or when PLL stop mode is released, the oscillation stabilization wait interval uses the specified values in the WS1 and WS0 bits. For PLL oscillation stabilization, at least 214/HCLK is required. Accordingly, when subclock mode is switched to PLL clock mode, or when PLL clock mode is switched to PLL stop mode, set WS1 and WS0 bits to "10B" or "11B". 109 CHAPTER 5 CLOCKS Table 5.3-1 Function Description of Each Bit of the Clock Selection Register (CKSCR) (2/3) Bit name Function bit 11 SCS: Machine clock selection bit (sub) • bit 10 MCS: Machine clock selection bit • This bit specifies whether the main clock or a PLL clock is selected as the machine clock. • When this bit is “0”, a PLL clock is selected. When it is 1, the main clock is selected. • If this bit has been set to "1" and "0" is written to it, the oscillation stabilization wait interval for the PLL clock starts. As a result, the timebase timer is automatically cleared, and the TBOF bit of the timebase timer control register (TBTC) is also cleared. • When main clock mode is switched to PLL clock mode, the oscillation stabilization wait interval is fixed at 214/HCLK (that is, the oscillation stabilization wait interval is approximately 4.1 ms when the oscillation clock frequency is 4 MHz). When subclock mode is switched to PLL clock mode or when PLL stop mode is released, the oscillation stabilization wait interval uses the specified values in the WS1 and WS0 bits. For PLL oscillation stabilization, at least 214/HCLK is required. Accordingly, when subclock mode is switched to PLL clock mode, or when PLL clock mode is switched to PLL stop mode, set the WS1 and WS0 bits to "10B" or "11B." • When the main clock has been selected, the operating clock frequency is the oscillation clock frequency divided by 2 (that is, the operating clock is 2 MHz when the oscillation clock frequency is 4 MHz). • This bit is initialized to "1" by all reset causes. Note: When the MCS bit is "1", write "0" to it only when the timebase timer interrupt is masked by the TBIE bit of the timebase timer control register (TBTC) or the interrupt level register (ILM). 110 This bit specifies whether the main clock or subclock is selected as the machine clock. • If 0 is written when this bit is 1, the mode is switched to the subclock mode by synchronizing with the subclock (about 130 µs when the subclock oscillation frequency is 32kHz and is divided by 4). • If this bit has been set to “0” and "1" is written to it, the oscillation stabilization wait interval for the main clock starts. As a result, the timebase timer is automatically cleared. • When the subclock has been selected, the operating clock frequency is the oscillation clock frequency divided by 2 or 4 (that is, the machine clock frequency is 16kHz or 8 kHz when the oscillation clock frequency is 32 kHz). • The subclock division ratio is determined by SCDS bit of PLL/Subclock Control Register (PSCCR). • If both the SCS and MCS bits are "0", the SCS bit takes precedence, that is, the subclock is selected. • This bit is initialized to "1" by all reset causes. Note: The oscillation stabilization wait time of the subclock (about 2s, when the subclock oscillation frequency is 32 kHz and is divided by 4) is generated when the power is turned on or the stop mode is canceled. Thus, if the mode is switched from the main cock mode to the subclock mode during this period, an oscillation stabilization wait time is generated. CHAPTER 5 CLOCKS Table 5.3-1 Function Description of Each Bit of the Clock Selection Register (CKSCR) (3/3) Bit name bit 9 bit 8 CS1 and CS0: Multiplier selection bits Function • These bits and CS2 bits in PSCCR register select a PLL clock multiplier. • Selection can be made from among five different multipliers. • These bits are initialized to “00B” by all reset causes. • Recommended setting of CS2,1,0: CS2 CS1 CS0 PLL clock Multiplex time 0 0 0 x1 0 0 1 x2 0 1 0 x3 0 1 1 x4 1 1 0 x6 1 1 1 Prohibited Note: When the MCS or MCM bit is “0”, writing to these bits is not possible. Write to the CS0, CS1 and CS2 bits only after setting the MCS bit to “1” (main clock mode). HCLK: Oscillation clock 111 CHAPTER 5 CLOCKS 5.3.2 PLL/Subclock Control Register (PSCCR) PLL/Subclock control register adds the selection of a PLL clock multiplier. ■ Configuration of the PLL/Subclock Control Register (PSCCR) Figure 5.3-3 shows the configuration of the PLL/Subclock control register (PSCCR). Figure 5.3-3 Configuration of the PLL/Subclock Control Register (PSCCR) Address 0000CFH bit15 bit14 bit13 bit12 bit11 bit10 bit9 Reserved SCDS Reserved W W W bit8 bit7 bit0 Initial value XXXX0000B CS2 W CS2 0 1 Reserved 0 Additional multiplier selection bit Refer to the description for CS1 and CS0 bits in the CKSCR register. Reserved bit Always write "0" to this bit. The value read from this bit is always "1". SCDS Sub Clock Division Select bit W X 112 : Write only : Undefined value : Undefined : Initial value 0 Sub clock divided by 4 1 Sub clock divided by 2 Reserved 0 Reserved bit Always write "0" to this bit. The value read from this bit is always "1". CHAPTER 5 CLOCKS Table 5.3-2 Function Description of Each Bit of the PLL/Subclock Control Register (PSCCR) Bit name Function bit 15 to bit 12 Unused bits • These bits are unused. • Writing to these bits has no effect. • Reading these bits always returns “1”. bit 11 bit 9 Reserved: Reserved bit • These bits are reserved bits. • Always write “0” to these bits • Reading these bits always returns “1”. bit 10 SCDS: Sub clock division ratio select bit • This bit selects the sub clock division ratio. • Writing “0” to this bit sets operating clock in sub clock mode to sub clock oscillation frequency divided by 4. Writing “1” to this bit sets the clock to the oscillation frequency divided by 2. • This bit is initialized to “0” by all reset causes. bit 8 CS2: Multiplier selection bit2 • This bit and CS1 and CS0 bits of the Clock selection register (CKSCR) select a PLL clock multiplier. • About the relationship between setting CS2,CS1 and CS0 bits and the PLL clock multiplier selection, please refer to the description for the CS1 and CS0 bits of the CKSCR register. • This bit is initialized to “0” by all reset causes. Note: When the MCS or MCM bit is “0”, changing the setting of this bit is not allowed. Change this bit only after setting the MCS bit to “1” (main clock mode). Note: The PSCCR is a write-only register, so the read value is different from the write value. Therefore, instructions that perform a read-modify-write (RMW) operation, such as the INC/DEC instruction, cannot be used. 113 CHAPTER 5 CLOCKS 5.4 Clock Mode Three clock modes are provided: main clock mode, PLL clock mode and subclock mode. ■ Main Clock Mode, PLL Clock Mode and subclock Mode ● Main clock mode In main clock mode, a clock whose frequency is the oscillation clock frequency divided by 2 is used as the operating clock for the CPU and peripheral resources, and the PLL clocks are disabled. ● PLL clock mode In PLL clock mode, a PLL clock is used as the operating clock for the CPU and peripheral resources. A PLL clock multiplier is selected with the clock selection register (CKSCR: CS1 and CS0) and PLL/ Subclock control register (PSCCR: CS2). ● Subclock mode In subclock mode, a clock whose frequency is the oscillation clock frequency divided by 2 or 4 is used as the operating clock for the CPU and peripheral resources, and the main clock and PLL clocks are disabled. The subclock division ratio is determined by SCDS bit of PLL/Subclock Control Register (PSCCR). ■ Clock Mode Transition Transition among main clock mode, PLL clock mode, and subclock mode is performed by writing to the MCS and SCS bits of the clock selection register (CKSCR). ● Transition from main clock mode to PLL clock mode When the MCS bit of the clock selection register (CKSCR) is rewritten from “1” to “0” in main clock mode, switching from the main clock to a PLL clock occurs after the PLL clock oscillation stabilization wait interval (214/HCLK). ● Transition from PLL clock mode to main clock mode When the MCS bit of the clock selection register (CKSCR) is rewritten from “0” to “1” in PLL clock mode, switching from the PLL clock to the main clock occurs when the edges of the PLL clock and the main clock coincide (after 1 to 12 PLL clocks). ● Transition from main clock mode to subclock mode When the SCS bit of the clock selection register (CKSCR) is rewritten from “1” to “0” in main clock mode, switching from the main clock to a subclock occurs by synchronizing with the subclock (about 130µs when the subclock oscillation frequency is 32kHz and is divided by 4). 114 CHAPTER 5 CLOCKS ● Transition from subclock mode to main clock mode When the SCS bit of the clock selection register (CKSCR) is rewritten from "0" to "1" in subclock mode, switching from the subclock to the main clock occurs after the main clock oscillation stabilization wait interval. The oscillation stabilization wait interval is selected based on the WS1 and WS0 bits of the clock selection register (CKSCR). ● Transition from PLL clock mode to subclock mode When the SCS bit of the clock selection register (CKSCR) is rewritten from "1" to "0" in PLL clock mode, switching from the PLL clock to the subclock occurs. ● Transition from subclock mode to PLL clock mode When the SCS bit of the clock selection register (CKSCR) is rewritten from "0" to "1" in subclock mode, switching from the subclock to a PLL clock occurs after the main clock oscillation stabilization wait interval. The oscillation stabilization wait interval is selected based on the WS1 and WS0 bits of the clock selection register (CKSCR). Notes: Even though the MCS and SCS bits of the clock selection register (CKSCR) are rewritten, machine clock switching does not occur immediately. When operating a resource that depends on the machine clock, confirm that machine clock switching has been performed by referring to the MCM and SCM bits of the clock selection register (CKSCR) before operating the resource. When the clock mode is switched, do not switch to other clock mode and low power consumption mode before this switching is completed. Confirm the completion of clock mode switching by referring to the MCM and SCM bits of the clock selection register (CKSCR). If both the SCS and MSC bits are “0”, the SCS bit takes precedence, that is, subclock mode is selected. ■ Selection of a PLL Clock Multiplier Writing a value from "00B" to "11B" to the CS1 and CS0 bits of the clock selection register (CKSCR) and "0"or "1" to the CS2 bit of the PLL/Subclock control register (PSCCR) selects a PLL clock multiplier of 1 to 4 (when CS2=0), 2 to 6 (when CS2=1, CS1 = 1, CS0 = 0). ■ Machine Clock The machine clock may be a PLL clock output from the PLL multiplier circuit, a clock whose frequency is the source oscillation frequency divided by 2, or a clock whose frequency is the subclock oscillation frequency divided by 4 or 2. This machine clock is supplied to the CPU and peripheral functions. The main clock, PLL clock, or subclock can be selected by writing to the MCS or SCS bit of the clock selection register (CKSCR). And the subclock division ratio, 4 or 2, can be selected by writing to SCDS bit of the PLL/Subclock control register (PSCCR). 115 CHAPTER 5 CLOCKS Figure 5.4-1 shows the status change caused by machine clock switching. Figure 5.4-1 Status Change Diagram for Machine Clock Selection Main MCS = 1 MCM = 1 SCS = 1 SCM = 1 CS1, CS0 = xxB CS2=x (10) (12) (20) (13) (8) (9) (9) (9) (9) 116 (11) (1) (2) Main PLLx MCS = 0 (3) MCM = 1 (4) SCS = 1 (5) SCM = 1 (6) CS1, CS0 = xxB CS2=x (9) Main Sub MCS = 1 MCM = 1 SCS = 0 SCM = 1 CS1, CS0 = xxB CS2=x Sub Main MCS = 1 MCM = 1 SCS = 1 SCM = 0 CS1, CS0 = xxB CS2=x (12) Sub MCS = X MCM = 1 SCS = 0 SCM = 0 CS1, CS0 = xxB CS2=x (11) (10) (14) (15) (16) (17) (18) Sub PLL MCS = 0 MCM = 1 SCS = 1 SCM = 0 CS1, CS0 = xxB CS2=0 PLL1 Main MCS = 1 MCM = 0 SCS = 1 SCM = 1 CS1, CS0 = 00B CS2=0 PLL1: Multiplied MCS = 0 MCM = 0 SCS = 1 SCM = 1 (8) CS1, CS0 = 00B (10) CS2=0 PLL1 Sub MCS = 1 MCM = 0 SCS = 0 SCM = 1 CS1, CS = 00B CS2=0 PLL2 Main MCS = 1 MCM = 0 SCS = 1 SCM = 1 CS1, CS0 = 01B CS2=0 PLL2: Multiplied MCS = 0 MCM = 0 SCS = 1 (10) (8) SCM = 1 CS1, CS0 = 01B CS2=0 PLL2 Sub (21) MCS = 1 MCM = 0 SCS = 0 SCM = 1 CS1, CS0 = 01B CS2=0 PLL3 Main MCS = 1 MCM = 0 SCS = 1 SCM = 1 CS1, CS0 = 10B CS2=0 PLL3: Multiplied MCS = 0 MCM = 0 SCS = 1 (10) (8) SCM = 1 CS1, CS0 = 10B CS2=0 PLL4 Main MCS = 1 MCM = 0 SCS = 1 SCM= 1 CS1, CS0 = 11B CS2=0 PLL4: Multiplied MCS = 0 MCM = 0 SCS = 1 (10) (8) SCM = 1 CS1, CS0 = 11B CS2=0 PLL6 Main MCS = 1 MCM = 0 SCS = 1 SCM = 1 CS1, CS0 = 10B CS2=1 PLL6: Multiplied MCS = 0 MCM = 0 SCS = 1 (10) (8) SCM = 1 CS1, CS0 = 10B CS2=1 PLL3 Sub MCS = 1 MCM = 0 SCS = 0 SCM = 1 CS1, CS0 =10B CS2=0 (21) (21) PLL4 Sub (21) MCS = 1 MCM = 0 SCS = 0 SCM = 1 CS1, CS0 = 11B CS2=0 (21) PLL6 Sub MCS = 1 MCM = 0 SCS = 0 SCM = 1 CS1, CS0 =10B CS2=1 CHAPTER 5 CLOCKS (1) Writing "0" to the MCS bit (2) End of PLL clock oscillation stabilization wait & CS1 and CS0 = 00B & CS2 = 0 (3) End of PLL clock oscillation stabilization wait & CS1 and CS0 = 01B & CS2 = 0 (4) End of PLL clock oscillation stabilization wait & CS1 and CS0 = 10B & CS2 = 0 (5) End of PLL clock oscillation stabilization wait & CS1 and CS0 = 11B & CS2 = 0 (6) End of PLL clock oscillation stabilization wait & CS1 and CS0 = 10B & CS2 = 1 (8) Writing "1" to the MCS bit (including reset) (9) Timing of synchronization between the PLL clock and the main clock (10) Writing "0" to the SCS bit (11) Timing of synchronization between the main clock and the subclock. (12) Writing "1" to the SCS bit (MCS = 1) (13) End of main clock oscillation stabilization wait (14) End of main clock oscillation stabilization wait & CS1 and CS0 = 00B & CS2 = 0 (15) End of main clock oscillation stabilization wait & CS1 and CS0 = 01B & CS2 = 0 (16) End of main clock oscillation stabilization wait & CS1 and CS0 = 10B & CS2 = 0 (17) End of main clock oscillation stabilization wait & CS1 and CS0 = 11B & CS2 = 0 (18) End of main clock oscillation stabilization wait & CS1 and CS0 = 10B & CS2 = 1 (20) Writing "1" to the SCS bit (MCS = 0) (21) Timing of synchronization between the PLL clock and the subclock MCS : Machine clock selection bit of the clock selection register (CKSCR) MCM : Machine clock indication bit of the clock selection register (CKSCR) SCS : Machine clock selection bit of the clock selection register (CKSCR) (sub) SCM : Machine clock indication bit of the clock indication register (CKSCR) (sub) CS1, CS0 : Multiplier selection bits of the clock selection register (CKSCR) CS2 : Multiplier selection bits of the PLL/subclock control register (PSCCR) Notes: • The initial value for the machine clock setting is main clock (CKSCR: MCS = 1, SCS = 1). • If both the SCS and MCS bits are "0", the SCS bit takes precedence, that is, the subclock is selected. • When subclock mode is switched to PLL clock mode, set the WS1 and WS0 bits of CKSCR to "10B" or "11B". 117 CHAPTER 5 CLOCKS 5.5 Oscillation Stabilization Wait Interval When the power is turned on, when stop mode is released, or switching from the subclock to the main clock or from subclock to the PLL clock occurs, an oscillation stabilization wait interval is required after oscillation begins because there is no oscillation. When switching from the main clock to the PLL clock or from the main clock to the subclock occurs, an oscillation stabilization wait interval is required. ■ Oscillation Stabilization Wait Interval Ceramic and crystal oscillators generally require several to dozens of ms to stabilize at their natural frequency (oscillation frequency) when oscillation starts. For this reason, CPU operation is not allowed immediately after oscillation starts but is allowed only after full oscillation stabilization. After the oscillation stabilization wait interval has elapsed, the clock is supplied to the CPU. Because the oscillation stabilization time depends on the type of oscillator (crystal, ceramic, etc.), the proper oscillation stabilization wait interval for the oscillator used must be selected. An oscillation stabilization wait interval is selected by setting the clock selection register (CKSCR). When clock mode is switched from main clock to PLL clock, main clock to subclock, subclock to main clock, or subclock to PLL clock, the CPU runs in the clock mode set before switching for the oscillation stabilization wait time. After the oscillation stabilization wait time has elapsed, the CPU changes to the specified clock mode. Figure 5.5-1 shows the operation immediately after oscillation starts. Figure 5.5-1 Operation Immediately after Oscillation Starts Oscillator-activated oscillation time Start of oscillation 118 Oscillation stabilization wait interval Stable oscillation Normal operation start or switching to PLL clock/sub-clock CHAPTER 5 CLOCKS 5.6 Connection of an Oscillator or an External Clock to the Microcontroller The MB90350 series microcontroller contains a system clock generation circuit. Connecting an external oscillator to this circuit generates the system clock. Alternatively, an externally generated clock can be input to the microcontroller. ■ Connection of an Oscillator or an External Clock to the Microcontroller ● Example of connecting a crystal or ceramic oscillator to the microcontroller Connect a crystal or ceramic oscillator as shown in the example in Figure 5.6-1. Figure 5.6-1 Example of Connecting a Crystal or Ceramic Oscillator to the Microcontroller MB90350 series X0(X0A) X1(X1A) ● Example of connecting an external clock to the microcontroller As shown in the example in Figure 5.6-2, connect an external clock to pin X0 (X0A). Pin X1 (X1A) must be open. Figure 5.6-2 Example of Connecting an External Clock to the Microcontroller MB90350 series X0(X0A) X1(X1A) Open 119 CHAPTER 5 CLOCKS 120 CHAPTER 6 RESETS This chapter describes resets for the MB90350-series microcontrollers. 6.1 Resets 6.2 Reset Cause and Oscillation Stabilization Wait Times 6.3 External Reset Pin 6.4 Reset Operation 6.5 Reset Cause Bits 6.6 Status of Pins in a Reset 121 CHAPTER 6 RESETS 6.1 Resets If a reset is generated, the CPU immediately stops the current execution process and waits for the reset to be cleared. The CPU then begins processing at the address indicated by the reset vector. The four causes of a reset are as follows • Power-on reset • Watchdog timer overflow • External reset request via the RST pin • Software reset request ■ Causes of a reset Table 6.1-1 lists the causes of a reset. Table 6.1-1 Causes of a reset Type of reset Cause Machine clock Watchdog timer Oscillation stabilization wait Power-on When the power is turned on Main clock (MCLK) Stop Yes External pin L level input to RST pin Main clock (MCLK) Stop No Software A "0" is written to the RST bit of the low power consumption mode control register (LPMCR). Main clock (MCLK) Stop No Watchdog timer Watchdog timer overflow Main clock (MCLK) Stop No Main clock: Oscillation clock frequency divided by 2 ● External reset An external reset is generated by the L level input to an external reset pin (RST pin). The minimum required period of the L level is 500ns . The oscillation stabilization wait time is not required for external resets. In the MB90350 series the external reset has to be min. 100 µs for wake-up from Main-Time base timer mode. If the reset cause is generated during a write operation (during the execution of a transfer instruction such as MOV), the CPU waits for the reset to be cleared after completion of the instruction only for reset requests via the RST pin. Therefore, the normal write operation is completed even though a reset is input concurrently. 122 CHAPTER 6 RESETS Note that a reset may prevent the data transfer requested by a string-processing instruction (such as MOVS) from being completed because the reset is accepted before a specified number of bytes are transferred. Also note that when the RDY signal of the external bus interface is kept active, the external reset takes its effect after 16 machine clock cycles. When the external reset is applied while in the stop mode, subclock mode, sub-sleep mode and watch mode, the external reset signal must be kept active for more than the duration of the required stabilization time of the external oscillator plus 100 us. When the external reset is applied while in the timebase timer mode, the external reset signal must be kept active for more than 100 us. ● Software reset A software reset is an internal reset generated by writing "0" to the RST bit of the low power consumption mode control register (LPMCR). The oscillation stabilization wait time is not required for a software reset. ● Watchdog timer reset A watchdog timer reset is generated by a watchdog timer overflow that occurs when "0" is written to the WTE bit of the watchdog timer control register (WDTC) within a given time after the watchdog timer is activated. The oscillation stabilization wait time can be set by the clock selection register (CKSCR). ● Power-on reset A power-on reset is generated when the power is turned on. The oscillation stabilization wait times at 216/ HCLK (approx. 16.38 ms, HCLK = 4 MHz). When the oscillation stabilization wait time has elapsed, the reset is executed. Reference Definition of clocks HCLK: Oscillation clock MCLK: Main clock φ: Machine clock (CPU operating clock) 1/φ: Machine cycle (CPU operating clock period) See "CHAPTER 5 CLOCKS", for details on machine clocks. 123 CHAPTER 6 RESETS 6.2 Reset Cause and Oscillation Stabilization Wait Times The MB90350 series has four reset causes. The oscillation stabilization wait time for a reset depends on the reset cause. ■ Reset causes and oscillation stabilization wait times Table 6.2-1 summarizes reset causes and oscillation stabilization wait times. Table 6.2-1 Reset causes and oscillation stabilization wait times Reset cause Oscillation stabilization wait time The corresponding time interval for an oscillation clock frequency of 4 MHz is given in parentheses. Power-on reset always 216/HCLK (approx. 16.38 ms at 4 MHz oscillator) Watchdog timer None; though bits WS1 and WS0 are initialized to "11". External reset via the RST pin None; though bits WS1 and WS0 are initialized to "11". Software reset None; though bits WS1 and WS0 are initialized to "11". HCLK: Oscillation clock WS1 and WS0: Oscillation stabilization wait time selection bits of the clock selection register (CKSCR) Figure 6.2-1 shows the oscillation stabilization wait times at a power-on reset. 124 CHAPTER 6 RESETS Figure 6.2-1 Oscillation stabilization wait times at a power-on reset Evaluation/flash model Vcc 215/HCLK 215/HCLK CLK CPU operation Voltage step-down circuit stabilization wait interval Oscillation stabilization wait time HCLK: Oscillation clock Note: Ceramic and crystal oscillators generally require an oscillation stabilization wait time of several milliseconds to 10 to 20 milliseconds, until stabilization at a natural frequency is attained. A proper oscillation stabilization wait time must be set for the particular oscillator used. See Section "5.5 Oscillation Stabilization Wait Interval", for details about oscillation stabilization wait times. ■ Oscillation stabilization wait and reset state A reset operation in response to a power-on reset and other resets during stop mode or subclock mode is performed after the oscillation stabilization wait time has elapsed. This time interval is generated by the timebase timer. If the external reset has not been cleared after the interval, the reset operation is performed after the external reset is cleared. 125 CHAPTER 6 RESETS 6.3 External Reset Pin The external reset pin (RST pin) is an input pin used exclusively for a reset. Inputting an L level signal generates an internal reset. For the MB90350-series, resets are generated in synchronization with the CPU operating clock. However, initialization of external pin is asynchronous with the CPU operating clock. ■ Block diagram of the external reset pin ● Block diagram of the external reset pin Figure 6.3-1 Block diagram of the external reset pin CPU operating clock (PLL multiplier circuit with an HCLK frequency divided by 2) RST CPU Pch Synchronization circuit Pin Nch Input buffer Peripheral functions I/O port or other pin Note: Inputs to the RST are accepted during cycles in which memory is not affected to prevent memory from being destroyed by a reset during a write operation. A clock is required to initialize the internal circuit. In particular, an operation with an external clock requires clock input together with reset input. 126 CHAPTER 6 RESETS 6.4 Reset Operation When a reset signal is inactivated, the reset vector and mode data is fetched from the predetermined locations depending on the setting of the mode pins. This operation, the mode fetch, then defines the operation mode of the CPU and the start address of the first instruction. For the power on reset, reset from the stop mode or subclock mode, the mode fetch is performed after the oscillation stabilization wait time is elapsed. ■ Overview of reset operation Figure 6.4-1 shows the reset operation flow. Figure 6.4-1 Reset operation flow Power-on reset Stop mode Subclock mode External reset Software reset Watchdog timer reset During a reset Oscillation stabilization wait and reset state Fetching the mode data Mode fetch (Reset operation) Normal operation (Run state) Pin state and function change associated with external bus mode Fetching the reset vector CPU executes an instruction, fetching instruction codes from the address indicated by the reset vector. ■ Mode pins Setting the mode pins (MD0 to MD2) specifies how to fetch the reset vector and the mode data. Fetching the reset vector and the mode data is performed in the reset sequence. See Section "8.1.1 Mode Pins", for details on mode pins. 127 CHAPTER 6 RESETS ■ Mode fetch When the reset is cleared, the CPU transfers the reset vector and the mode data to the appropriate registers in the CPU core by hardware. The reset vector and mode data are allocated to the four bytes from "FFFFDCH" to "FFFFDFH". The CPU outputs these addresses to the bus immediately after the reset is cleared and then fetches the reset vector and mode data. Using mode fetching, the CPU can begin processing at the address indicated by the reset vector. Figure 6.4-2 shows the transfer of the reset vector and mode data. Figure 6.4-2 Transfer of reset vector and mode data Memory space FFFFDF H Mode data FFFFDE H Bits 23 to 16 of reset vector FFFFDDH Bits 15 to 8 of reset vector FFFFDCH Bits 7 to 0 of reset vector F2MC-16LX CPU core Mode register Reset sequence MicroROM PCB PC ● Mode data (address: FFFFDFH) Only a reset operation changes the contents of the mode register. The mode register setting is valid after a reset operation. See Section "8.1.2 Mode Data", for details on mode data. ● Reset vector (address: FFFFDCH to FFFFDEH) The reset vector points to the start address after the reset sequence. The CPU starts to execute the first instruction stop in the start address. 128 CHAPTER 6 RESETS 6.5 Reset Cause Bits A reset cause can be identified by reading the watchdog timer control register (WDTC). ■ Reset cause bits As shown in Figure 6.5-1, a flip-flop is associated with each reset cause. The contents of the flip-flops are obtained by reading the watchdog timer control register (WDTC). If the cause of a reset must be identified after the reset has been cleared, the value read from the WDTC should be processed by the software and a branch made to the appropriate program. Figure 6.5-1 Block diagram of reset cause bits RST pin No periodic clear RST=L External reset request detection cirtuit Power-on detection circuit Watchdog timer reset generation detection cirtuit Watchdog timer control register (WDTC) RST bit set LPMCR, RST bit write detection circuit Clear S R S Q R S Q R Q R S F/F F/F F/F F/F Delay circuit Q Reading of watchdog timer control register (WDTC) Internal data bus S : R : Q : F/F: Set Reset Output Flip Flop 129 CHAPTER 6 RESETS ■ Correspondence between reset cause bits and reset causes Figure 6.5-2 shows the configuration of the reset cause bits of the watchdog timer control register (WDTC). Table 6.5-1 maps the correspondence between the reset cause bits and reset causes. See "Watchdog timer control register (WDTC)" in Section "11.1 Outline of WatchDog Timer", for details. Figure 6.5-2 Configuration of reset cause bits (watchdog timer control register) Watchdog timer control register (WDTC) Address bit15 0000A8 H bit8 bit7 (TBTC) bit6 PONR - R - bit5 bit4 bit3 bit2 bit1 bit0 Initial value WRST ERST SRST WTE WT1 WT0 X X X X 1 1 1 R R R W W B W R : Read only W : Write only X : Undefined Table 6.5-1 Correspondence between reset cause bits and reset causes Reset cause PONR WRST ERST SRST Power-on reset 1 X X X Watchdog timer overflow * 1 * * External reset request via RST pin * * 1 * Software reset request * * * 1 *: Previous state defined X: Undefined ■ Notes about reset cause bits ● Multiple reset causes generated at the same time When multiple reset causes are generated at the same time, the corresponding reset cause bits of the watchdog timer control register (WDTC) are also set to "1". If, for example, an external reset request via the RST pin and the watchdog timer overflow occur at the same time, the ERST and the WRST bits are both set to "1". ● Power-on reset For a power-on reset, because the PONR bit is set to "1" but all other reset cause bits are undefined, the software should be programmed so that it will ignore all reset cause bits except the PONR bit if it is "1". 130 CHAPTER 6 RESETS ● Clearing the reset cause bits The reset cause bits are cleared only when the watchdog timer control register (WDTC) is read. Any bit corresponding to a reset cause that has already been generated is not cleared even though another reset is generated (a setting of "1" is retained). Note: If the power is turned on under conditions where no power-on reset occurs, the value in WDTC register may not be guaranteed. 131 CHAPTER 6 RESETS 6.6 Status of Pins in a Reset This section describes the status of pins when a reset occurs. ■ Status of pins during a reset The status of pins during a reset depends on the settings of mode pins (MD2 to MD0). ● When internal vector mode has been set: (MD2 to MD0 = "011B") All I/O pins (resource pins) are high impedance, and mode data is read from the internal ROM. About status of each pins during reset, please see "7.7 Status of Pins in Standby Mode and during Hold and Reset". ■ Status of pins after mode data is read The status of pins after mode data has been read depends on the mode data (M1 and M0 = "00"). ● When single-chip mode has been selected (M1, and M0 = 00B) All I/O pins (resource pins) are high impedance. Note: For those pins that change to high impedance when a reset cause is generated, confirm that devices connected to the pins do not malfunction. 132 CHAPTER 7 LOW-POWER CONSUMPTION MODE This chapter explains the low-power consumption mode of MB90350 series microcontrollers. 7.1 Overview of Low-Power Consumption Mode 7.2 Block Diagram of the Low-Power Consumption Control Circuit 7.3 Low-Power Consumption Mode Control Register (LPMCR) 7.4 CPU Intermittent Operation Mode 7.5 Standby Mode 7.6 Status Change Diagram 7.7 Status of Pins in Standby Mode and during Hold and Reset 7.8 Usage Notes on Low-Power Consumption Mode 133 CHAPTER 7 LOW-POWER CONSUMPTION MODE 7.1 Overview of Low-Power Consumption Mode The MB90350 series has the following CPU operating modes, any of which can be used depending on operating clock selection and clock operation control: • Clock mode (PLL clock mode, main clock mode, or subclock mode) • CPU intermittent operating mode (PLL clock intermittent operating mode, main clock intermittent operating mode, or subclock intermittent operating mode) • Standby mode (sleep mode, timebase timer mode, stop mode, or watch mode) ■ CPU Operating Modes and Current Consumption Figure 7.1-1 shows the relationship between the CPU operating modes and current consumption. Figure 7.1-1 CPU Operating Mode and Current Consumption Current consumption Several tens of mA CPU operating mode Multiplied-by-six clock PLL clock mode Multiplied-by-four clock Multiplied-by-three clock Multiplied-by-two clock Multiplied-by-one clock Multiplied-by-six clock PLL clock intermittent operating mode Multiplied-by-four clock Multiplied-by-three clock Multiplied-by-two clock Multiplied-by-one clock Main clock mode (HCLK/2) Main clock intermittent operating mode Subclock mode (SCLK/2 or SCLK/4) Several mA Subclock intermittent operating mode Standby mode Sleep mode Timebase timer mode Watch mode Several A Stop mode Low-power consumption mode Note: This figure is only an indication of the degree of power consumption for each mode. Actual current consumption values may not agree with those in the figure. 134 CHAPTER 7 LOW-POWER CONSUMPTION MODE ■ Clock Mode ● PLL clock mode In this mode, a PLL clock that is a multiple of the oscillation clock (HCLK) is used to operate the CPU and peripheral functions. ● Main clock mode In this mode, the main clock, with the oscillation clock (HCLK) frequency divided by 2 is used to operate the CPU and peripheral functions. In the main clock mode, the PLL multiplier circuit is inactive. ● Subclock mode In this mode, the subclock, with the oscillation clock (SCLK) frequency divided by 2 or 4 is used to operate the CPU and peripheral functions. In the subclock mode, the main clock and PLL multiplier circuit are inactive. The subclock oscillation stabilization wait time of 2 to 14/SCLK (Approx. 2s@32 kHz, 1/4 division) takes place when power-on reset and reactivation from stop mode. If a transition from main clock mode from subclock mode is performed during this oscillation stabilization wait time, actual transition may be delayed. Reference: For the clock mode, see Section "5.4 Clock Mode". ■ CPU Intermittent Operating Mode In this mode, the CPU is operated intermittently while high-speed clock pluses are supplied to peripheral functions, thereby reducing power consumption. In this mode, intermittent clock pulses are supplied only to the CPU while it is accessing a register, internal memory, peripheral function, or external unit. ■ Standby Mode In this mode, the low-power consumption control circuit stops supplying the clock to the CPU (sleep mode) or the CPU and peripheral functions (timebase timer mode) or stops the oscillation clock itself (stop mode), thereby reducing power consumption. ● PLL sleep mode The PLL sleep mode is activated to stop the CPU operating clock in the PLL clock mode. Components excluding the CPU operate on the PLL clock. ● Main sleep mode The main sleep mode is activated to stop the CPU operating clock in the main clock mode. Components excluding the CPU operate on the main clock. ● Sub-sleep mode The subsleep mode activated to stop the CPU operating clock in the subclock mode. Components excluding the CPU operate on the subclock oscillation frequency divided four or two. 135 CHAPTER 7 LOW-POWER CONSUMPTION MODE ● Timebase timer mode The timebase timer mode causes the operation of functions, excluding the oscillation clock, timebase timer, and watch timer, to stop. All functions other than the timebase timer and watch timer are inactivated. ● Watch mode The watch mode operates the watch timer only. The subclock operates and the main clock and PLL multiplier circuit stop. ● Stop mode The stop mode cause the oscillation to stop. All functions are inactivated. Note: Because the stop mode turns the oscillation clock off, data can be retained by the lowest power consumption. When the clock mode is switched, do not switch to other clock mode and low-power consumption mode before this switching is completed. Confirm the completion of clock mode switching by referring to the MCM and SCM bits of the clock selection register (CKSCR). 136 CHAPTER 7 LOW-POWER CONSUMPTION MODE 7.2 Block Diagram of the Low-Power Consumption Control Circuit The low-power consumption control circuit consists of the following seven blocks: • CPU intermittent operation selector • Standby control circuit • CPU clock control circuit • Peripheral clock control circuit • Pin high-impedance control circuit • Internal reset generation circuit • Low-power consumption mode control register (LPMCR) ■ Block Diagram of the Low-Power Consumption Control Circuit Figure 7.2-1 shows a block diagram of the low-power consumption control circuit. 137 CHAPTER 7 LOW-POWER CONSUMPTION MODE Figure 7.2-1 Block Diagram of the Low-Power Consumption Control Circuit Low Power Consumption Mode Control Register (LPMCR) STP SLP SPL RST TMD CG1 CG0 RESV Pin Hi-Z control circuit Internal reset generation circuit RST Pin CPU intermittent operation cycle selector Watch, Stop signal Interrupt (Release) Peripheral clock control circuit Peripheral function operation clock Sub clock oscillation stabilization wait release Main clock oscillation stabilization wait release Clock Generation Block Operation clock selector Machine clock 2 CS2 PLL/sub clock control register (PSCCR):bit8 Oscillation stabilization wait time selector 2 PLL multiplier circuit SCM MCM WS1 WS0 SCS MCS CS1 CS0 Clock Selection Register (CKSCR) Divideby-2 X0 Pin Oscillation clock (HCLK) X1 Pin Oscillation clock generation circuit X0A Pin Main clock Divideby-512 Divideby-4 Sub Clock Oscillation Circuit Divideby-2 Divideby-2 Timebase timer Divide-by-4/ Divide-by-2 Divideby-1024 SCDS PLL/Sub Clock Control Register (PSCCR):bit10 Divideby-2 Divideby-2 Divideby-2 To watchdog timer Sub clock (SCLK) Watch timer X1A Pin 138 CPU operation clock Watch, Sleep, Stop signal Standby control circuit 2 Internal reset Intermittent cycle selection CPU clock control circuit Reset (Release) Pin Hi-Z control Divideby-8 Divideby-2 Divideby-2 Divideby-4 CHAPTER 7 LOW-POWER CONSUMPTION MODE ● CPU intermittent operation selector This selector selects the number of clock pulses to halt the CPU during the CPU intermittent operation mode. ● Standby control circuit The standby control circuit controls the CPU clock control and the peripheral clock control circuits and turns the low-power consumption mode on and off. ● CPU clock control circuit This circuit controls clocks supplied to the CPU. This circuit controls clocks supplied to peripheral functions for the peripheral clock control circuit. ● Peripheral clock control circuit This circuit controls clocks supplied to peripheral functions. ● Pin high-impedance control circuit This circuit makes external pins high-impedance in the timebase timer mode and stop mode. For pins with the pull-up option, this circuit disconnects the pull-up resistor in the stop mode. ● Internal reset generation circuit This circuit generates an internal reset signal. ● Low-power consumption mode control register (LPMCR) This register is used to switch to and release the standby mode and to set the CPU intermittent operation function. 139 CHAPTER 7 LOW-POWER CONSUMPTION MODE 7.3 Low-Power Consumption Mode Control Register (LPMCR) This register switches to or releases the low-power consumption mode. This register also sets the number of CPU clock pulses to halt during the CPU intermittent operation mode. ■ Low-Power Consumption Mode Control Register (LPMCR) Figure 7.3-1 shows the configuration of the low-power consumption mode control register (LPMCR). Figure 7.3-1 Configuration of the low-power consumption mode control register (LPMCR) bit15 Address 0000A0H (CKSCR) bit8 bit7 bit7 bit6 bit6 bit5 bit5 bit4 bit4 bit3 bit2 bit1 STP SLP SPL RST RESV TMD CG1 CG0 RESV SSR W W R/W W W R/W R/W SSR RESV DRAM self refresh control bit Reserved 1 Controls DRAMS self refresh in the sleep mode. Count bit for CPU clock temporary halt cycle 0 0 0 cycles (CPU clock = Resource clock) 0 1 8 cycles (CPU clock:Resource clock = 1:3 to 4 approx.) 1 0 16 cycles (CPU clock:Resource clock = 1:5 to 6 approx.) 1 1 32 cycles (CPU clock:Resource clock = 1:9 to 10 approx.) Timebase timer mode bit 0 Switches to the timebase timer mode, or watch mode. 1 No change, no effect on operation RST Internal reset signal generation bit 0 Generates an internal reset signal of three machine cycles. 1 No change, no effect on operation SPL Watch and pin state setting bit (for timebase timer mode and stop mode) 0 Previous pin state retained. 1 High impedance SLP Sleep mode bit 0 No change, no effect on operation 1 Switches to sleep mode. STP 140 00011000B R/W Does notwrite control Always "0"DRAMC to this self bit refresh in the sleep mode. TMD : Read/write : Write-only : initial value Initial value 0 CG1 CG0 R/W W bit0 Stop mode bit 0 No change, no effect on operation 1 Switches to stop mode. CHAPTER 7 LOW-POWER CONSUMPTION MODE Table 7.3-1 Function Description of Each Bit of the Low-power Consumption Mode Control Register (LPMCR) Bit name Function bit 7 STP: Stop mode bit • • • • • This bit indicates switching to the stop mode. When 1 is written to this bit, a switch to the stop mode is performed. Writing 0 in this bit has no effect on operation. This bit is cleared to 0 by a reset or when an interrupt request occurs. The read value of this bit is always 0. bit 6 SLP: Sleep mode bit • • • • • This bit indicates switching to a sleep mode. When 1 is written to this bit, a switch to a sleep mode is performed. Writing 0 in this bit has no effect on operation. This bit is cleared to 0 by a reset or when an interrupt request occurs. The read value of this bit is always 0. bit 5 SPL: Pin state setting bit (for watch mode, timebase timer mode, and stop mode) • • • • This bit is enabled only in the watch mode, timebase timer mode, and stop mode. When this bit is 0, the level of the external pins is retained. When this bit is 1, the status of the external pins changes to high-impedance. This bit is initialized to 0 by a reset. bit 4 RST: Internal reset signal generation bit • When 0 is written to this bit, an internal reset signal of three machine cycles is generated. • Writing 1 in this bit has no effect on operation. • The read value of this bit is always 1. bit 3 TMD: Watch/timebase timer mode bit • This bit indicates switching to the watch mode or timebase timer mode. • When 0 is written to this bit in the main clock mode or PLL clock mode, a switch to timebase timer mode is performed. • When 0 is written to this bit in the subclock mode, a switch to the watch mode is performed. • This bit is cleared to 1 by a reset or when an interrupt request occurs. • The read value of this bit is always 1. bit 2 bit 1 CG1, CG0: Bits for selecting clock count for CPU temporary halt cycle • These bits set the number of CPU clock pulses per cycle to halt the CPU for the CPU intermittent operation function. • The clock supplied to the CPU is stopped for the specified number of pulses after the execution of each instruction. • Four types of clock counts are selectable. • These bits are initialized to 00B by a reset. bit 0 RESV: Reserved Note: Always write "0" to this bit. Note: • Switching to a low-power consumption mode is performed by writing the low-power consumption mode control register (LPMCR). Only the instructions listed in Table 7.3-2 should be used for this purpose. If other instructions are used for switching to a low-power consumption mode, operation cannot be assured. • The standby mode transition instruction in Table 7.3-2 must always be followed by an array of 141 CHAPTER 7 LOW-POWER CONSUMPTION MODE instructions highlighted by a dotted line below. MOV LPMCR, #H’ xx ; The low-power consumption mode transition instruction in Table 7.3-2. NOP NOP JMP $+3 ; Jump to the next instruction. MOV A, #H’ 10 ; any instruction The devices does not guarantee its operation after returning from the low-power consumption mode if you place the array of instructions other than the one enclosed in the dine. • To access the low-power consumption mode control register (LPMCR) with C language, refer to "Notes on Accessing the Low-Power Consumption Made Control Register (LPMCR) to Switch the Standby Mode" in the section "7.8 Usage Notes on Low-Power Consumption Mode". • When word-length is used for writing the low-power consumption mode control register (LPMCR), even addresses must be used. Using odd addresses to switch to a low-power consumption mode may result in a malfunction. • To set a pin to high impedance when the pin is shared by a peripheral function and a port in stop mode, watch mode or timebase timer mode, set the STP bit to 1 or set the TMD bit to 0 after disabling the output of peripheral functions. Table 7.3-2 Instructions to Be Used for Switching to a Low-Power Consumption Mode MOV io,#imm8 MOV dir,#imm8 MOV eam,#imm8 MOV eam,Ri MOV io,A MOV dir,A MOV addr16,A MOV eam,A MOVW io,#imm16 MOVW dir,#imm16 MOVW eam,#imm16 MOVW eam,RWi MOVW io,A MOVW dir,A MOVW addr16,A MOVW eam,A SETB io: bp SETB dir: bp SETB addr16: bp CLRB io: bp CLRB dir: bp SLRB addr16: bp MOV @Rli+disp8,A MOVW @Rli+disp8,A 142 CHAPTER 7 LOW-POWER CONSUMPTION MODE 7.4 CPU Intermittent Operation Mode This mode is used for intermittent operation of the CPU while external buses and peripheral functions continue to operate at high speeds. The purpose of this mode is to reduce power consumption. ■ CPU Intermittent Operation Mode This mode halts the supply of the clock pulse to the CPU for a certain period. The halt occurs after the execution of every instruction that accesses a register, internal memory (ROM and RAM), I/O, peripheral functions, or the external bus. Internal bus cycle activation is therefore delayed. While high-speed peripheral clock pulses are supplied to peripheral functions, the execution speed of the CPU is reduced, thereby enabling low-power consumption processing. • The low-power consumption mode control register (LPMCR: CG1 and CG0) is used to select the number of clock pulses per halt cycle of the clock supplied to the CPU. • External bus operation uses the same clock as that used for peripheral functions. • Instruction execution time in the CPU intermittent mode can be calculated. A correction value should be obtained by multiplying the execution count of instructions that access a register, internal memory, internal peripheral functions, or the external bus by the number of clock pulses per halt cycle. Add this corrective value to the normal execution time. Figure 7.4-1 shows the operating clock pulses during the CPU intermittent operation mode. Figure 7.4-1 Clock Pulses during the CPU Intermittent Operation Peripheral clock CPU clock Halt cycle Execution cycle of one instruction Internal bus activation 143 CHAPTER 7 LOW-POWER CONSUMPTION MODE 7.5 Standby Mode The standby mode includes the sleep (PLL sleep, main sleep, subsleep), watch, and stop modes. ■ Operation Status during Standby Mode Table 7.5-1 shows operation statuses during standby mode. Table 7.5-1 Operation Statuses during Standby Mode Standby mode Sleep mode Condition for switch PLL sleep mode SCS=1 MCS=0 SLP=1 Main sleep mode SCS=1 MCS=1 SLP=1 Main clock Subclock Machine clock CPU Peripheral Pin Release event Active Subsleep mode Timebase timer mode SCS=0 SLP=1 MCS=X Timebase timer mode (SPL=0) SCS=1 MCS=X TMD=0 Timebase timer mode (SPL=1) SCS=1 MCS=X TMD=0 Watch mode (SPL=0) TMD=0 MCS=X SCS=0 Active Active Active External reset Interrupt Inactive Inactive Active *1 External reset Retained Interrupt *3 Active Watch mode Watch mode (SPL=1) Stop mode Stop mode (SPL=0) TMD=0 MCS=X SCS=0 Inactive Hi-Z*6 Inactive Inactive STP=1 STP=1 Interrupt *4 *6 Retained *1: The timebase timer and watch timer operate. *2: The watch timer operates. *3: Watch timer, timebase timer and external interrupt *4: Watch timer and external interrupt *5: External interrupt *6: Input pins for DTP/External interrupt are enabled. SPL: Pin state setting bit of low-power consumption mode control register (LPMCR) SLP: Sleep mode bit of low-power consumption mode control register (LPMCR) STP: Stop mode bit of low-power consumption mode control register (LPMCR) TMD: Watch and timebase timer mode bit of low-power consumption mode control register (LPMCR) MCS: Machine clock selection bit of clock selection register (CKSCR) SCS: Machine clock selection bit (sub) of clock selection register (CKSCR) Hi-Z: High-impedance 144 External reset Retained Hi-Z Inactive Inactive Stop mode (SPL=1) *2 Inactive Hi-Z*6 External reset Interrupt *5 CHAPTER 7 LOW-POWER CONSUMPTION MODE ■ Note For those external pins shared between port functions and peripheral functions, disable output for the peripheral functions then set the STP bit to "1" or reset the TMD bit to "0" to set these pins in high impedance state. 145 CHAPTER 7 LOW-POWER CONSUMPTION MODE 7.5.1 Sleep Mode This mode causes the CPU operating clock to stop while other components continue to operate. When the low-power consumption mode control register (LPMCR) indicates a switch to a sleep mode, a switch to the PLL sleep mode occurs if the PLL clock mode has been set. A switch to the main clock mode occurs if the main clock mode has been set. A switch to the subsleep mode occurs if the subclock mode has been set. ■ Switching to Sleep Mode Writing 1 in the SLP bit and the TMD bit and 0 in the STP bit of the low-power consumption mode control register (LPMCR) triggers a switch to a sleep mode. At this time, if the MSC bit is 0 and the SCS bit is 1 in the clock selection register (CKSCR), a switch to the PLL sleep mode is triggered. If the MSC bit and the SCS bit are 1, a switch to the main sleep mode is triggered. If the SCS bit is 0, a switch to the subsleep mode is triggered. Note: When 1 is written to the SLP and STP bits at the same time, the STP bit setting overrides the SLP bit setting and the mode switches to the stop mode. When 1 is written to the SLP bit and 0 is written to the TMD bit at the same time, the TMD bit setting overrides the SLP bit setting and the mode switches to the timebase timer mode or watch mode. ● Data retention function In a sleep mode, the contents of dedicated registers, such as accumulators, and the internal RAM are retained. ● Hold function During a sleep mode, the external bus hold function is active. This function sets the hold status when requested to do so. ● Operation during an interrupt request Writing 1 in the SLP bit of the low-power consumption mode control register during an interrupt request does not trigger a switch to a sleep mode. If the CPU does not accept the interrupt, the CPU executes the next instruction. If the CPU accepts the interrupt, CPU operation immediately branches to the interrupt processing routine. ● Status of pins During a sleep mode, all pins (excluding those used for bus I/O or bus control) retain their previous status. ■ Release of Sleep Mode The low-power consumption control circuit releases sleep modes when a reset is input or an interrupt occurs. ● Return by a reset A sleep mode is initialized to the main clock mode by a reset. 146 CHAPTER 7 LOW-POWER CONSUMPTION MODE Note: When the sub-sleep mode is switched to main clock mode using an external reset pin (RST pin), input level “L” for at least the oscillation time of the oscillator * + 100 µs + 16 machine cycles. * : The oscillation time of the oscillator is the time required to reach 90% of amplitude. It takes several to dozens of ms for crystal oscillators, hundreds of µs to several ms for FAR/ceramic oscillators, and 0 ms for external clocks. ● Return by an interrupt If an interrupt request of higher than level seven is issued from a peripheral circuit during a sleep mode, the sleep mode is released. After the mode is released, the interrupt is handled as an ordinary interrupt. If the interrupt is accepted according to the setting of the I flag of the condition code register (CCR), interrupt level mask register (ILM), and interrupt control register (ICR), the CPU executes the interrupt processing. If the interrupt is not accepted, the CPU executes the instruction following the instruction specifying the sleep mode. Figure 7.5-1 shows the release of a sleep mode when an interrupt occurs. Figure 7.5-1 Release of Sleep Mode by Interrupt Occurrence Interrupt from peripheral function Set the enable flag. IL smaller than 7 INT occurrence? NO (IL smaller than 7) Sleep mode is not released. Sleep mode is not released. YES I=0 YES Next instruction is executed. Sleep mode is released. NO ILM smaller than IL YES Next instruction is executed. NO Interrupt is executed. Note: When interrupt processing is executed, the CPU normally executes the instruction that follows the instruction in which switching to a sleep mode has been specified. The CPU then proceeds to interrupt processing. If the switching to sleep mode and acceptance of an external bus hold request occur at the same time, however, the CPU may proceed to interrupt processing before executing the next instruction. Figure 7.5-2 shows a return from the Sleep mode. 147 CHAPTER 7 LOW-POWER CONSUMPTION MODE Figure 7.5-2 Release of the Sleep Mode (External Reset) RST pin Sleep mode Main clock Oscillating PLL clock Oscillating CPU clock PLL clock CPU operation inactive Sleep mode release 148 Reset sequence Reset cleared Execution CHAPTER 7 LOW-POWER CONSUMPTION MODE 7.5.2 Timebase Timer Mode This mode causes all functions, excluding oscillation, the timebase timer, and the watch timer, to stop. In this mode, only the timebase timer and watch timer operate. ■ Switching to the Timebase Timer Mode When 0 is written to the TMD bit of the low-power consumption mode control register (LPMCR) in the PLL clock mode or main clock mode (CKSCR: SCS = 1), switching to the timebase timer mode occurs. ● Data retention function In the timebase timer mode, the contents of dedicated registers, such as accumulators, and the internal RAM are retained. ● Hold function During the timebase timer mode, because the external bus hold function is inactive, a hold request is not accepted even if it is input. If a hold request is input during switching to the timebase timer mode, the bus may remain at high-impedance and prevent the HAK signal from going low. ● Operation during an interrupt request Writing 0 in the TMD bit of the low-power consumption mode control register (LPMCR) during an interrupt request does not trigger a switch to the timebase timer mode. ● Status of pins Whether the external pins in the timebase timer mode retain the state they had immediately before switching to the timebase timer mode or go to the high-impedance state can be controlled by the low-power consumption mode control register (LPMCR: SPL). ■ Release of Timebase Timer Mode The low-power consumption control circuit releases the timebase timer mode when a reset is input or an interrupt occurs. ● Return by a reset The timebase timer mode is initialized to the main clock mode by a reset. ● Return by an interrupt If a watch timer, timebase timer, or external interrupt generates an interrupt request at an interrupt level higher than 7 during the timebase timer mode (IL2, IL1, and IL0 of the interrupt control register (ICR) do not indicate 111B), the low-power consumption mode control circuit releases the timebase timer mode. After the mode is released, the interrupt is handled as an ordinary interrupt. If the interrupt is accepted according to the setting of the I flag of the condition code register (CCR), interrupt level mask register (ILM), or interrupt control register (ICR), the CPU executes the interrupt processing. If the interrupt is not accepted, the CPU executes the instruction following the instruction specifying the timebase timer mode. 149 CHAPTER 7 LOW-POWER CONSUMPTION MODE Note: When interrupt processing is executed, the CPU normally executes the instruction following the instruction in which switching to the timebase timer mode has been specified. The CPU then proceeds to interrupt processing. If the switching to the timebase timer mode and acceptance of an external bus hold request occur at the same time, however, the CPU may proceed to interrupt processing before executing the next instruction. Figure 7.5-3 shows a return from the timebase timer mode. Figure 7.5-3 Release of the timebase timer mode (External Reset) RST pin Timebase timer mode Main clock Oscillating PLL clock Oscillation stabilization wait time Main clock CPU clock CPU operation inactive Timebase timer mode release 150 Reset sequence Reset cleared Oscillating PLL clock Execution CHAPTER 7 LOW-POWER CONSUMPTION MODE 7.5.3 Watch Mode This mode causes all functions, excluding the subclock and watch timer, to stop. In this mode almost all chip functions stop. ■ Switching to the Watch Mode When 0 is written to the TMD bit of the low-power consumption mode control register (LPMCR) in the subclock run mode (CKSCR: SCS = 0), switching to the watch mode occurs. ● Data retention function In the watch mode, the contents of the dedicated registers, such as accumulators, and the internal RAM are retained. ● Hold function During the watch mode, because the external bus hold function is inactive, a hold request is not accepted even if it is input. If a hold request is input during switching to the watch mode, the bus may remain at high-impedance and prevent the HAK signal from going low. ● Operation during an interrupt request Writing 1 in the TMD bit of the low-power consumption mode control register (LPMCR) during an interrupt request does not trigger a switch to the watch mode. ● Status of pins Whether the external pins in the watch mode retain the state they had immediately before switching to the watch mode or go to the high-impedance state can be controlled by the SPL bit of the low-power consumption mode control register (LPMCR). 151 CHAPTER 7 LOW-POWER CONSUMPTION MODE ■ Release of Watch Mode The low-power consumption control circuit releases the watch mode when a reset is input or an interrupt occurs. ● Return by a reset The watch mode is released by a reset to the oscillation stabilization wait reset state. The reset sequence is executed after the oscillation stabilization wait time. The period of reset assertion depends on quality of main clock crystal oscillator. ● Return by an interrupt If a watch timer or external interrupt generates an interrupt request at an interrupt level higher than 7 during the watch mode (IL2, IL1, and IL0 of the interrupt control register (ICR) do not indicate 111B), the lowpower consumption mode control circuit releases the watch mode and causes switching to the subclock mode immediately. After the switching, the interrupt is handled as an ordinary interrupt. If the interrupt is accepted according to the setting of the I flag of the condition code register (CCR), interrupt level mask register (ILM), and interrupt control register (ICR), the CPU executes the interrupt processing. If the interrupt is not accepted, the CPU executes the instruction following the instruction specifying the watch mode. Note: When interrupt processing is executed, the CPU normally executes the instruction following the instruction in which switching to the watch mode has been specified. The CPU then proceeds to interrupt processing. If the switching to the watch mode and acceptance of an external bus hold request occur at the same time, however, the CPU may proceed to interrupt processing before executing the next instruction. Figure 7.5-4 shows a return from the watch mode. Figure 7.5-4 Release of the Watch Mode (External Reset) RST pin Watch mode Main clock PLL clock Subclock Oscillation stabilization wait Inactive Oscillating CPU clock Inactive Main clock CPU operation Inactive Reset sequence Execution Reset cleared. Watch mode released. 152 Oscillating CHAPTER 7 LOW-POWER CONSUMPTION MODE 7.5.4 Stop Mode Because this mode causes oscillation to stop and inactivates all functions, data can be retained by the lowest power consumption. ■ Switching to the Stop Mode When 1 is written to the STP bit of the low-power consumption mode control register (LPMCR), switching to the stop mode occurs. ● Data retention function In the stop mode, the contents of the dedicated registers, such as accumulators, and the internal RAM are retained. ● Hold function During the stop mode, because the external bus hold function is inactive, a hold request is not accepted even if it is input. If a hold request is input during switching to the stop mode, the bus may remain at highimpedance and prevent the HAK signal from going low. ● Operation during an interrupt request Writing 1 in the STP bit of the low-power consumption mode control register (LPMCR) does not trigger a switch to the stop mode. ● Status of pins Whether the external pins in the stop mode retain the state they had immediately before switching to the stop mode or go to the high-impedance state can be controlled by the SPL bit of the low-power consumption mode control register (LPMCR). Note: If "1" is specified for both the STP bit and the SLP bit of the low-power consumption mode control (LPMCR) simultaneously, the STP bit takes precedence, and a transition to stop mode occurs. For those external pins shared between port functions and peripheral functions, disable output for the peripheral functions then set the STP bit to "1" or reset the TMD bit to set these pins in high impedance state. 153 CHAPTER 7 LOW-POWER CONSUMPTION MODE ■ Release of Stop Mode The low-power consumption control circuit releases the stop mode when a reset is input or an interrupt occurs. Because the oscillation clock (HCLK) and subclock (SCLK) are halted, the stop mode is released after the oscillation stabilization wait interval of the main clock or subclock. ● Return by a reset After the stop mode is released by a reset, the oscillation stabilization wait state is set. The reset sequence is executed after the oscillation stabilization wait time. The period of reset assertion depends on quality of main clock crystal oscillator. ● Return by an interrupt If an external interrupt generates an interrupt request at interrupt level higher than 7 during the stop mode (IL2, IL1, and IL0 of the interrupt control register (ICR) do not indicate 111B), the low-power consumption mode control circuit releases the stop mode. The interrupt is then handled as an ordinary interrupt after the oscillation stabilization wait time of the main clock specified by the WS1 and WS0 bits of the clock selection register (CKSCR). If the interrupt is accepted according to the setting of the I flag of the condition code register (CCR), interrupt level mask register (ILM), and interrupt control register (ICR), the CPU executes the interrupt processing. If the interrupt is not accepted, the CPU executes the instruction following the instruction specifying the stop mode. Notes: • When interrupt processing is executed, the CPU normally executes the instruction following the instruction in which switching to the stop mode has been specified. The CPU then proceeds to interrupt processing. If the switching to the stop mode and acceptance of an external bus hold request occur at the same time, however, the CPU may proceed to interrupt processing before executing the next instruction. • In PLL stop mode, the main clock and PLL multiplication circuit stop. During recovery from PLL stop mode, it is necessary to allot the main clock oscillation stabilization wait time and PLL clock oscillation stabilization wait time. The oscillation stabilization wait times for the main clock and PLL clock are counted simultaneously according to the value specified in the oscillation stabilization wait time selection bits (CKSCR: WS1, WS0) in the clock selection register. The oscillation stabilization wait time selection bits (CKSCR: WS1, WS0) in the clock selection register must be selected accordingly to account for the longer of main clock and PLL clock oscillation stabilization wait time. The PLL clock oscillation stabilization wait time, however, requires 214/HCLK or more. Set the oscillation stabilization wait time selection bits (CKSCR: WS1, WS0) in the clock selection register to "10B" or "11B". Figure 7.5-5 shows a return from the stop mode. 154 CHAPTER 7 LOW-POWER CONSUMPTION MODE Figure 7.5-5 Release of the Stop Mode (External Reset) RST pin Stop mode Main clock PLL clock Oscillation stabilization wait Inactive Main clock CPU clock CPU operation Oscillating Inactive Reset sequence Execution Reset cleared. Stop mode released. 155 CHAPTER 7 LOW-POWER CONSUMPTION MODE 7.6 Status Change Diagram Figure 7.6-1 shows the status change diagram of the MB90350 series. ■ Status Change Diagram Figure 7.6-1 Status Change Diagram External reset, watchdog timer reset, software reset Power-on Reset Power-on reset Oscillation stabilization wait end SCS=0 SCS=1 MCS=0 Main clock mode Interrupt Main sleep mode InterTMD=0 rupt Timebase timer mode STP=1 Main stop mode Inter- Oscillation rupt stabilization wait end Main clock oscillation stabilization wait Subclock mode PLL clock mode MCS=1 SLP=1 SCS=0 SCS=1 SLP=1 Interrupt PLL sleep mode TMD=0 Interrupt Timebase timer mode Interrupt Subsleep mode Interrupt TMD=0 Watch mode STP=1 STP=1 PLL stop mode Interrupt SLP=1 Oscillation stabilization wait end Main clock oscillation stabilization wait Subclock stop mode Interrupt Oscillation stabilization wait end Subclock oscillation stabilization wait Note: During reading this diagram, refer to the priority of the standby modes (see the priorities of the STP, SLP, and TMD bits in Section "7.3 Low-Power Consumption Mode Control Register (LPMCR)"). When the clock mode is switched, do not switch to other clock mode and low-power consumption mode before this switching is completed. Confirm the completion of clock mode switching by referring to the MCM and SCM bits of the clock selection register (CKSCR). 156 CHAPTER 7 LOW-POWER CONSUMPTION MODE ■ Operation Status in Each Operating Mode Table Table 7.6-1 lists the operation status in each operating mode. Table 7.6-1 Operation Status in Each Operating Mode Operation status Main clock Subclock PLL clock PLL CPU Peripheral Watch Timebase timer Active Active Clock source Active Active PLL sleep Active Active Active Timebase timer *1 PLL clock PLL stop Inactive Inactive Inactive PLL oscillation stabilization wait Active Active Active Inactive Inactive Inactive Inactive Active Active Active Active Active Main Active Main sleep Active Active Timebase timer *2 Main clock Inactive Inactive Main stop Inactive Inactive Main oscillation stabilization wait Active Active Inactive Sub Inactive Inactive Active Active Active Active Subsleep Watch Active Active Inactive Inactive Subclock stop Inactive Subclock oscillation stabilization wait Active Power-on reset Inactive Inactive Inactive Subclock Active Main clock Inactive Active Inactive Active Reset Active Inactive Inactive Active Active *1: During the PLL clock mode *2: During the main clock mode 157 CHAPTER 7 LOW-POWER CONSUMPTION MODE 7.7 Status of Pins in Standby Mode and during Hold and Reset The status of pins in the standby mode and during hold and reset are described for each memory access mode. ■ Status of Each Pin in the Single Chip Mode Table 7.7-1 shows the Status of Each Pin in the Single Chip Mode. Table 7.7-1 Status of Each Pin in the Single Chip Mode Standby/timebase timer/watch mode Stop *6 Pin name Reset Sleep SPL = 0 SPL = 1 P17 to P10 P25 to P20 P37 to P30 P45 to P40 Status before the mode retained *2 P56 to P50 Input disabled *4 / Status before the mode retained *2 Input disabled*4/ output Hi-Z *5 Input not possible *3 / output Hi-Z *5 P67 to P60 P00 to P07*7 Input enabled *1 /status before the mode retained*2 P42, P32, P12*8 Input enabled *1 /output Hi-Z *5 *1: “Input enabled” means that the input function is available. The pull-up or pull-down option or external input is required. When the pin is used as an output port, the status is the same as other ports. *2: “Status before the mode retained” means that it keeps previous output state when output or that the input is "not possible" when input. *3: “Input not possible” means that the gate connected to the input pin is functioning as input but the internal circuit can not accept this input signal because the internal circuit is not functioning. *4: “Input disabled” means that the gate connected to the input pin is disabled. *5: “Output Hi-Z” means that the pin driving transistor is placed in the drive prohibited state to set the pin to high impedance. *6: The pull-up option is disconnected from each port pin in stop mode. *7: These pins are "Input enabled" in STOP mode only if INTxR bit of External interrupt source select register (EISSR) is “0”. Otherwise they are "Input disabled". *8: These pins are "Input enabled" in STOP mode only if INTxR bit of External interrupt source select register (EISSR) is “1”. Otherwise they are "Input disabled". Note: In the stop mode up to sixteen external signals can be input and the frequency of each signal must be 1 kHz or less. 158 CHAPTER 7 LOW-POWER CONSUMPTION MODE ■ Status of Each Pin in the External BUS 16-bit Data Bus Mode Table 7.7-2 shows the Status of Each Pin in the External Bus 16-bit Data Bus Mode. Table 7.7-2 Status of Each Pin in the External Bus 16-bit Data Bus Mode Standby/timebase timer/watch mode Pin name Hold Stop Reset Sleep SPL = 0 P07 to P00 (AD07 to AD00) P17 to P10 (D15 to AD08A) P25 to P20 (A21 to A16) P37(CLK) P36(RDY) P35(HAK) SPL = 1 Input not Input possible / disabled / output Hi-Z output Hi-Z Input not possible/ output Hi-Z Output state Output state Input not possible / output Hi-Z*3 *1,*3 *1,*3 Input not Input not possible / possible / output output state *2,*3 *1,*3 enabled Status before the mode retained*4 P34(HRQ) Input disabled / Status before the mode retained*4 Input not possible / output enabled*2,*3 Input disabled / output HiZ*5 P32(WRL) P45 to P40 P56 to P50 P67 to P60 P42, P32, P12*6 "L" output Status before the mode retained*4 Output Hi-Z / input enabled Output Hi-Z / input enabled Output state*1 Hold the address immediately before Output Hi-Z / input enabled Output Hi-Z / input enabled Input not possible / output Hi-Z Input not possible / output Hi-Z*3 “L” output*3 “H” output*3 Input not possible / output Hi-Z*3 "H" output “H” output “H” output "L" output Input not possible / output Hi-Z "L" output “L” output “L” output Status before the mode retained*4 Input not possible / output Hi-Z Output Hi-Z / input enabled Output Hi-Z / input enabled P31(RD) P30(ALE) At internal ROM access after external ROM access “1” input*3 P33(WRH) “H” output*3 At internal ROM access immediately after reset release Input disabled / Status before the mode retained*4 Input enabled/ status before the mode retained*4 Input enabled/ output HiZ*5 159 CHAPTER 7 LOW-POWER CONSUMPTION MODE *1: "Output state" means that the output is being driven by the internal circuit but the internal circuit is on hold. Thus the output value is fixed to either "0" or "1". When the internal circuit is in operation, the output value changes accordingly except during reset. *2: "Output enabled" means that the output is being driven and propagate the signal from the internal circuit in operation. *3: When used as output, it retains the previous output value. *4: "Status before the mode retained" means that it keeps the previous output state when output or that input is "not possible" when input. "Input not possible" means that the gate connected to the input pin is functioning as input but the internal circuit can not accept this input signal because the internal circuit is not functioning. *5: "Input disabled" means that the gate connected to the input pin is disabled. *6: These pins are "Input enabled" in STOP mode if the INTxR bit of External interrupt source select register (EISSR) is "1". Otherwise they are disabled. Note: For those external pins shared between port functions and peripheral functions, disable output for the peripheral functions then set the STP bit to "1" or reset the TMD bit to "0" to set these pins in high impedance state. 160 CHAPTER 7 LOW-POWER CONSUMPTION MODE ■ Status of Each Pin in the External BUS 8-bit Data Bus Mode Table 7.7-3 shows the Status of Each Pin in the External Bus 8-bit Data Bus Mode. Table 7.7-3 Status of Each Pin in the External Bus 8-bit Data Bus Mode Pin name Standby mode Sleep Input not possible / output Hi-Z P25 to P20 Output state (A21 to A16) *1,*3 P37(CLK) Input not possible / output enabled*2,*3 SPL = 1 P34(HRQ) Status before the mode retained*4 P33 Output Hi-Z / Output Hi-Z / input enabled input enabled Output state*1,*3 Input not possible / output Hi-Z *3 Output state*1 Hold the address immediately before Input not possible / output state Input not possible / output enabled Input not *2,*3 possible / output Hi-Z Input not possible / output Hi-Z *3 *1,*3 Input Input disabled / disabled / “L” output*3 Status before output Hi-Z *5 the mode “1” input*3 retained*4 Status before the mode retained*4 “H” output*3 “H” output*3 P31(RD) "H" output "H" output P30(ALE) "L" output "L" output P54 to P51 P90,P91, P95, PA0 P42, P32, P12*6 Status before the mode retained*4 At internal ROM access after external ROM access Input not possible / output Hi-Z P32 P45 to P40 P56 to P50 P67 to P60 At internal ROM access immediately after reset release Input disabled / output Hi-Z P36(RDY) P35(HAK) Reset Stop SPL = 0 P07 to P00 (AD07 to AD00) P17 to P10 (AD15 to AD08) Hold Input not possible / output Hi-Z*3 Input not possible / output Hi-Z Input disabled / Status before the mode retained*4 Input enabled/ status before the mode retained. Output Hi-Z / Output Hi-Z / input enabled input enabled Input enabled/ output HiZ*5 Status before the mode retained*4 "H" output “H” output “H” output "L" output “L” output “L” output Input disabled Output Hi-Z / Output Hi-Z / / output Hi-Z input enabled input enabled 161 CHAPTER 7 LOW-POWER CONSUMPTION MODE *1: "Output state" means that the output is being driven by the internal circuit but the internal circuit is on hold. Thus the output value is fixed to either "0" or "1". When the internal circuit is in operation, the output value changes accordingly except during reset. *2: "Output enabled" means that the output is being driven and propagate the signal from the internal circuit in operation. *3: When used as output, it retains the previous output value. *4: "Status before the mode retained" means that it keeps the previous output state when output or that input is "not possible" when input "Input not possible" means that the gate connected to the input pin is functioning as input but the internal circuit can not accept this input signal because the internal circuit is not functioning. *5: "Input disabled" means that the gate connected to the input pin is disabled. *6: These pins are "Input enabled" in STOP mode if the INTxR bit of External interrupt source select register (EISSR) is "1". Otherwise they are disabled. Note: For those external pins shared between port functions and peripheral functions, disable output for the peripheral functions then set the STP bit to "1" or reset the TMD bit to "0" to set these pins in high impedance state. 162 CHAPTER 7 LOW-POWER CONSUMPTION MODE 7.8 Usage Notes on Low-Power Consumption Mode Note the following five items when using the low-power consumption mode: • Switching to a standby mode and interrupt • Release of a standby mode by an interrupt • Release of the stop mode • Oscillation stabilization wait time Oscillation • Clock mode switching ■ Switching to a Standby Mode and Interrupt When there is a pending interrupt request to the CPU, writing "1" to the STP bit or SLP bit or writing "1" to the TMD bit in the LPMCR register does not take its effect. In other words, the desired mode transition is not performed even after interrupt service is completed. If the interrupt is being serviced already and the interrupt request is cleared and if there are no other pending requests, the desired mode transition can be performed. Note that this behavior is not dependent on whether the setting in the PS register allows the CPU to accept the interrupt request. ● Release of the Standby Mode by an Interrupt If an interrupt request of interrupt level higher than seven priority is issued from a peripheral function during the sleep, timebase timer, or stop mode, the standby mode is released, which does not depend on whether the CPU accepts the interrupt. After the release of the standby mode by an interrupt, normal processing is performed. The CPU branches to the interrupt handling routine provided that the priority of the interrupt request indicated by the interrupt level setting bits (IL2, IL1, and IL0 of ICR) is higher than the interrupt level mask register (ILM) and the interrupt enable flag ((I) of the condition code register (CCR) is set to 1 (enabled). If the interrupt is not accepted, the CPU starts the execution with the instruction following the instruction in which switching to the standby mode has been specified. When interrupt processing is executed normally, the CPU first executes the instruction following the instruction in which switching to the standby mode has been specified. The CPU then proceeds to interrupt processing. Depending on the condition when switching to a standby mode was performed, however, the CPU may proceed to interrupt processing before executing the next instruction. Note: If the CPU does not branch to the interrupt processing routine immediately after a return, action such as interrupt disabling must be taken before a standby mode is set. ● Release of the Stop Mode The stop mode can be released by an input that has been set as an external interrupt input cause before the system enters the stop mode. As an input cause, an H-level signal, L-level signal, rising edge, or falling edge can be selected. 163 CHAPTER 7 LOW-POWER CONSUMPTION MODE ■ Oscillation Stabilization Wait Time ● Clock oscillation stabilization wait time Because the oscillator is halted in the stop mode, an oscillation stabilization wait time is required. A time period selected by the WS1 and WS0 bits of the clock selection register (CKSCR) is used as the oscillation stabilization wait time. ● PLL clock oscillation stabilization wait time In main clock mode, the PLL multiplication circuit stops. When changing to PLL clock mode, it is necessary to reserve the PLL clock oscillation stabilization wait time. The CPU runs in main clock mode till the PLL clock oscillation stabilization wait time has elapsed. When the main clock mode is switched to PLL clock mode, the PLL clock oscillation stabilization wait time is fixed at 214/HCLK (HCLK: oscillation clock). In subclock mode, the main clock and PLL multiplication circuit stop. When changing to PLL clock mode, it is necessary to reserve the main clock oscillation stabilization wait time and PLL clock oscillation stabilization wait time. The oscillation stabilization wait times for main clock and PLL clock are counted simultaneously according to the value specified in the oscillation stabilization wait time selection bits (CKSCR: WS1, WS0) in the clock selection register. The oscillation stabilization wait time selection bits (CKSCR: WS1, WS0) in the clock selection register must be selected accordingly to account for the longer of the main clock and PLL clock oscillation stabilization wait times. The PLL clock oscillation stabilization wait time, however, requires 214/HCLK or more. Set the oscillation stabilization wait time selection bits (CKSCR: WS1, WS0) in the clock selection register to "10B" or "11B". In PLL stop mode, the main clock and PLL multiplication circuit stop. During recovery from PLL stop mode, it is necessary to allot the main clock oscillation stabilization wait time and PLL clock oscillation stabilization wait time. The oscillation stabilization wait times for the main clock and PLL clock are counted simultaneously according to the value specified in the oscillation stabilization wait time selection bits (CKSCR: WS1, WS0) in the clock selection register. The oscillation stabilization wait time selection bits (CKSCR: WS1, WS0) in the clock selection register must be selected accordingly to account for the longer of main clock and PLL clock oscillation stabilization wait time. The PLL clock oscillation stabilization wait time, however, requires 214/HCLK or more. Set the oscillation stabilization wait time selection bits (CKSCR: WS1, WS0) in the clock selection register to "10B" or "11B". ● Clock mode switching When the clock mode is switched, do not switch to other clock mode and low-power consumption mode before this switching is completed. Confirm the completion of clock mode switching by referring to the MCM and SCM bits of the clock selection register (CKSCR). ■ Notes on accessing the Low-Power Consumption mode Control Register (LPMCR) to switch the Standby Mode ● To access the low-power consumption mode control register (LPMCR) with assembler language. To set the low power consumption mode control register (LPMCR) to switch the standby mode, use the instruction listed in Table 7.3-2. The standby mode transition instruction in Table 7.3-2 must always be followed by an array of 164 CHAPTER 7 LOW-POWER CONSUMPTION MODE instructions highlighted by a line below. MOV LPMCR, #H’ xx ; The low-power consumption mode transition instruction in Table 7.3-2. NOP NOP JMP $+3 ; Jump to the next instruction. MOV A, #H’ 10 ; Arbitrary instruction The devices does not guarantee its operation after returning from the standby mode if you place an array of instructions other than the one enclosed in the line. ● To access the low-power consumption mode (LPMCR) with C language. To switch the standby mode using the low power consumption mode control register (LPMCR), use one of the following methods 1. to 3. to access the register: 1. Specify the standby mode transition instruction as a function and insert two __wait_nop() built-in functions after that instruction.If any interrupt other than the interrupt to return from the standby mode can occur within the function, optimize the function during compilation to suppress the LINK and UNLINK instructions from occurring. Example: Watch mode or timebase timer mode transition function void enter_watch(){ IO_LPMCR.byte = 0x10; /* Set LPMCR TMD bit to 0 */ __wait_nop(); __wait_nop(); } 2. Define the standby mode transition instruction using __asm statements and insert two NOP and JMP instructions after that instruction. Example: Transition to sleep mode __asm("MOV I:_IO_LPMCR, #H’58); /* Set LPMCR SLP bit to 1 */ __asm("NOP"); __asm("NOP"); __asm("JMP $+3"); /* Jump to the next instruction*/ 3. Define the standby mode transition instruction between #pragma asm and #pragma endasm and insert two NOP and JMP instructions after that instruction. Example: Transition to stop mode #pragma asm MOV I:_IO_LPMCR, #HÅf 98 /* Set LPMCR STP bit to 1 */ NOP NOP JMP $+3 /* Jump to the next instruction */ #pragma endasm 165 CHAPTER 7 LOW-POWER CONSUMPTION MODE 166 CHAPTER 8 MEMORY ACCESS MODES This chapter explains the functions and operations of the memory access modes. 8.1 Outline of Memory Access Modes 8.2 External Memory Access (Bus Pin Control Circuit) 8.3 External Memory Access Control Signal Operation 167 CHAPTER 8 MEMORY ACCESS MODES 8.1 Outline of Memory Access Modes In the F2MC-16LX, various modes are provided for access methods and access areas. ■ Memory Access Modes Table 8.1-1 Mode Pins and Modes Operation mode Bus mode Access mode Single chip - Internal ROM, external bus 8 bits 16 bits RUN External ROM, external bus 8 bits 16 bits Flash programming - - ● Operation mode Operation mode means the mode for controlling the device operation status. The operation mode is specified by the MDx mode setting pin and the Mx bit in mode data. By selecting an operation mode, normal operation activation or flash serial programming can be performed. ● Bus mode Bus mode means the mode for controlling the internal ROM operation and external access function. The bus mode is specified by the MDx mode setting pin and the Mx bit in mode data. The MDx mode setting pin specifies the bus mode for reading the reset vector and mode data, and the Mx bit in mode data specifies the bus mode for normal operation. ● Access mode Access mode means the mode for controlling the external data bus width. The access mode is specified by the MDx mode setting pin and the S0 bit in mode data. By selecting an access mode, an 8- or 16-bit external data bus is specified. 168 CHAPTER 8 MEMORY ACCESS MODES 8.1.1 Mode Pins Table 8.1-2 lists the operations that can be specified by combining the three external pins MD2 to MD0. ■ Mode pins Table 8.1-2 Mode Pins and Modes Mode pin setting Mode name Reset vector access area External data bus width Remarks MD2 MD1 MD0 0 0 0 External vector mode 0 External 8 bits 0 0 1 External vector mode 1 External 16 bits Reset vector, 16-bit bus width access 0 1 0 Reserved 0 1 1 Internal vector mode Internal (Mode data) Reset sequence and later segments are controlled based on mode data. 1 0 0 1 0 1 1 1 0 Flash memory serial programming * -- -- -- 1 1 1 Flash memory -- -- Mode when parallel writer is used Reserved *: Flash serial programming mode involves other pin settings than the mode pins. See "CHAPTER 24 EXAMPLES OF MB90F352/C(S) PROGRAMMING CONNECTION". 169 CHAPTER 8 MEMORY ACCESS MODES 8.1.2 Mode Data Mode data is stored at FFFFDFH of main memory and used for controlling the CPU operation. This data is fetched during a reset sequence and stored in the mode register inside the device. The mode register value can be changed only by a reset sequence. The setting of this register is valid after the reset sequence. Always set the reserved bits to "0". ■ Mode Data Figure 8.1-1 Mode Data Configuration Mode data address address FFFFDFH 7 6 5 M1 M0 4 3 Reserved Reserved S0 2 1 0 Bit No. Reserved Reserved Reserved [Bits 7 and 6] M1, M0 (bus mode setting bits) The M1 and M0 bits are used to specify the operation mode after the reset sequence is completed. Table 8.1-3 shows the relationship between the M1 and M0 bits and the functions. Table 8.1-3 M1 and M0 (Bus Mode Setting Bit) Functions M1 M0 Function 0 0 Single-chip mode 0 1 Internal ROM, external bus mode 1 0 External ROM, external bus mode 1 1 Setting prohibited Remarks [Bit 3] S0 (mode setting bit) The S0 bit is used to specify the bus mode or access mode after the reset sequence is completed. Table 8.1-4 shows the relationship between the S0 bit and the functions. Table 8.1-4 S0 (Mode Setting Bit) Functions S0 170 Function 0 External 8-bit data bus mode 1 External 16-bit data bus mode Remarks CHAPTER 8 MEMORY ACCESS MODES 8.1.3 Memory Space in Each Bus Mode Figure 8.1-2 shows the correspondence between the access areas and physical addresses for each bus mode. ■ Memory Space in Each Bus Mode Figure 8.1-2 Relationship between Access Areas and Physical Addresses for Each Bus Mode Single chip Internal ROM, external bus ROM area ROM area ROM area image of bank FF ROM area image of bank FF Peripheral Peripheral External ROM, external bus FFFFFFH Address #1 C00100H 010000H 008000H Peripheral 007900H : Internal Address #2 : External RAM 000100H 0000F0H Register Peripheral 000000H RAM Register Peripheral RAM Register : No access Peripheral Table 8.1-5 Relationship between addresses #1 and #2 by product type TYPE Address #1 Address #2 MB90(F)352/C/S/CS FE0000H 001100H 171 CHAPTER 8 MEMORY ACCESS MODES ■ Recommended Setting Table 8.1-6 lists an example of recommended settings for mode pins and mode data. Table 8.1-6 Example of Recommended Settings for Mode Pins and Mode Data Sample setting MD2 MD1 MD0 M1 M0 S0 Single chip 0 1 1 0 0 x Internal ROM and external bus mode, 16-bit bus 0 1 1 0 1 1 Internal ROM and external bus mode, 8-bit bus 0 1 1 0 1 0 External ROM and external bus mode, 16-bit bus, vector 16 bus width 0 0 1 1 0 1 External ROM and external bus mode, 8-bit bus 0 0 0 1 0 0 External pins have signal functions that depend on each mode. Table 8.1-7 External Pin Functions for Each Mode Function Pin name External bus expansion Flash programming Single chip 8 bits P07 to P00 16 bits AD07 to AD00 P17 to P10 A15 to AD08 DQ07 to DQ00 AD15 to AD08 AQ15 to AQ08 P25 to P20 A21 to A16* AQ07 to AQ00 P30 ALE AQ16 P31 RD CE P32 P33 Port WR WRL OE Port WRH * WE P34 HRQ* AQ17 P35 HAK * AQ18 P36 RDY* BYTE P37 CLK* RY/BY *: The upper address output pins and the WRL/WR, WRH, HRQ, HAK, RDY, and CLK pins can be used as ports through function selection. See Section "8.2 External Memory Access (Bus Pin Control Circuit)" for details. 172 CHAPTER 8 MEMORY ACCESS MODES 8.2 External Memory Access (Bus Pin Control Circuit) The external bus pin control circuit controls the external bus pins for external expansion of the CPU address and data buses. ■ External Memory Access (Bus Pin Control Circuit) The following address, data, and control signals are used to access external memory and peripherals of the MB90350 device: • CLK (P37): Machine cycle clock (KBP) output pin • RDY (P36): External ready input pin • WRH (P33): Active only when 16 bit access • WRL/WR (P32): Active both when 16 bit and 8 bit access • RD (P31): Read signal • ALE (P30): Address latch enable signal The external bus pin control circuit is used to control the external bus pins to enable external expansion of the CPU address and data buses. ■ Block Diagram of External Memory Access Figure 8.2-1 External Bus Controller P0 P0 data P1 P2 P3 P3 P0 P0 direction RB Data control Address control Access control Access control 173 CHAPTER 8 MEMORY ACCESS MODES 8.2.1 External Memory Access (External Bus Pin Control Circuit) Registers External memory access (external bus pin control circuit) uses the following three types of registers: • Automatic ready function selection register • External address output control register • Bus control signal selection register ■ External Memory Access Registers Figure 8.2-2 External memory access (external bus pin control circuit) registers Automatic ready function selection register 15 Address:0000A5H Read/write Initial value 14 13 12 11 10 IOR1 IOR0 HMR1 HMR0 (W) (0) 9 8 LMR1 LMR0 (W) (0) (W) (1) (W) (1) (-) (X) (-) (X) (W) (0) (W) (0) 6 5 4 3 2 1 0 E21 E20 E19 E18 E17 E16 Bit No. ARSR External address output control register 7 Address:0000A6H Read/write Initial value 174 (-) (X) (-) (X) (W) (0) (W) (0) (W) (0) (W) (0) (W) (0) (W) (0) Bus control signal selection register 15 14 13 12 11 10 9 8 Address:0000A7H CKE RYE HDE Read/write Initial value (W) (0) (W) (0) (W) (0) IOBS HMBS WRE LMBS (W) (0) (W) (0) (W) (0) (W) (0) Bit No. HACR Bit No. ECSR (-) (X) CHAPTER 8 MEMORY ACCESS MODES 8.2.2 Automatic Ready Function Selection Register (ARSR) The automatic ready function selection register (ARSR) is used to set the automatic wait time for memory access for each area during external access. ■ Automatic Ready Function Selection Register (ARSR) Figure 8.2-3 Automatic Ready Function Selection Register Configuration Automatic ready function selection register 15 Address:0000A5H Read/write Initial value 14 13 12 11 10 IOR1 IOR0 HMR1 HMR0 (W) (0) (W) (0) (W) (1) (W) (1) 9 8 Bit No. LMR1 LMR0 (-) (X) (-) (X) (W) (0) ARSR (W) (0) [Bits 15 and 14] IOR1, IOR0 The IOR1 and IOR0 bits are used to specify the automatic wait function for external access to the area from 0000F0H to 0000FFH. Table 8.2-1 lists the settings that can be specified by combining the IOR1 and IOR0 bits. Table 8.2-1 IOR1 and IOR0 (Automatic Wait Function Specification Bit) Functions IOR1 IOR0 Function 0 0 Automatic wait disabled [initial value] 0 1 Automatic wait of 1 cycle is inserted for external access 1 0 Automatic wait of 2 cycles is inserted for external access 1 1 Automatic wait of 3 cycles is inserted for external access [Bits 13 and 12] HMR1, HMR0 The HMR1 and HMR0 bits are used to specify the automatic wait function for external access to the area from 800000H to FFFFFFH. Table 8.2-2 lists the settings that can be specified by combining the HMR1 and HMR0 bits. Table 8.2-2 HMR1 and HMR0 (Automatic Wait Function Specification Bit) Functions HMR1 HMR0 Function 0 0 Automatic wait disabled 0 1 Automatic wait of 1 cycle is inserted for external access 1 0 Automatic wait of 2 cycles is inserted for external access 1 1 Automatic wait of 3 cycles is inserted for external access [initial value] 175 CHAPTER 8 MEMORY ACCESS MODES [Bits 9 and 8] LMR1, LMR0 The LMR1 and LMR0 bits are used to specify the automatic wait function for external access to the areas between 008000H and 7FFFFFH. Table 8.2-3 lists the settings that can be specified by combining the LMR1 and LMR0 bits. Table 8.2-3 LMR1 and LMR0 (Automatic Wait Function Specification Bit) Functions 176 LMR1 LMR0 Function 0 0 Automatic wait disabled [initial value] 0 1 Automatic wait of 1 cycle is inserted for external access 1 0 Automatic wait of 2 cycles is inserted for external access 1 1 Automatic wait of 3 cycles is inserted for external access CHAPTER 8 MEMORY ACCESS MODES 8.2.3 External Address Output Control Register (HACR) The external address output control register (HACR) controls the external output of addresses (A23 to A16). The bits correspond to addresses A23 to A16, which control address output pins, as shown in Figure 8.2-4. ■ External Address Output Control Register (HACR) Figure 8.2-4 External Address Output Control Register Configuration External address output control register 7 6 Address:0000A6H Read/write Initial value (-) (X) (-) (X) 5 4 3 2 1 0 E21 E20 E19 E18 E17 E16 (W) (0) (W) (0) (W) (0) (W) (0) (W) (0) (W) (0) Bit No. HACR The HACR register controls output of addresses (A21 to A16) to the external circuit. The address output pin is controlled as follows with the six bits that correspond to address bits A23 to A16. The HACR register cannot be accessed when the device is in single-chip mode, since all pins function as I/ O ports whatever the value of this register. All bits of this register are write-only bits, and the value read from the bits is 1. Table 8.2-4 External Address Output Control Register (E23 to E16 bits) Functions 0 The corresponding pin is used for address output (AXX) [initial value]. 1 The corresponding pin is used as an I/O port (PXX). 177 CHAPTER 8 MEMORY ACCESS MODES 8.2.4 Bus Control Signal Selection Register (ECSR) The bus control signal selection register sets the bus operation control function in external bus mode. This register cannot be accessed when the device is in single-chip mode, since all pins function as I/O ports whatever the value of this register. All bits of the bus control signal selection register are write-only bits, and the value from the bits is 1. ■ Bus Control Signal Selection Register (ECSR) Figure 8.2-5 Bus Control Signal Selection Register Configuration Bus control signal selection register 15 14 Address:0000A7H CKE RYE Read/write Initial value (W) (0) (W) (0) 13 12 11 10 9 8 Bit No. HDE IOBS HMBS WRE LMBS (W) (0) (W) (0) (W) (0) (W) (0) (W) (0) ECSR (-) (X) [Bit 15] CKE The CKE bit controls output of the external clock signal pin (CLK), as shown in Table 8.2-5. Table 8.2-5 CKE (External Clock (CLK) Output Control Bit) Functions 0 I/O port (P37) operation (clock output disabled) [initial value] 1 Clock signal (CLK) output enabled [Bit 14] RYE The RYE bit controls input of the external ready (RDY) signal pin, as shown in Table 8.2-6. Table 8.2-6 RYE (External Ready (RDY) Input Control Bit) Functions 0 I/O port (P36) operation (external RDY input disabled) [initial value] 1 External ready (RDY) input enabled [Bit 13] HDE The HDE bit specifies that input-output of hold signals is enabled. The hold request input signal (HRQ) and hold acknowledge output signal (HAK) are controlled according to the setting of the HDE bit, as shown in Table 8.2-7. Table 8.2-7 HDE (Hold Signal Input-Output Enable Specification Bit) Functions 178 0 I/O port (P35, P34) operation (hold function input-output disabled) [initial value] 1 Hold request (HRQ) input/hold acknowledge (HAK) output enabled CHAPTER 8 MEMORY ACCESS MODES [Bit 12] IOBS The IOBS bit is used to specify the bus width for external access to the area from 0000F0H to 0000FFH in external 16-bit data bus mode. Control is based on the setting of this bit, as shown in Table 8.2-8. Table 8.2-8 IOBS (Bus Width Specification Bit) 0 16-bit bus width access [initial value] 1 8-bit bus width access [Bit 11] HMBS The HMBS bit is used to specify the bus width for external access to the area from 800000H to FFFFFFH in external 16-bit data bus mode. Control is based on the setting of this bit, as shown in Table 8.2-9. Table 8.2-9 HMBS (Bus Width Specification Bit) 0 16-bit bus width access [initial value] 1 8-bit bus width access [Bit 10] WRE The WRE bit controls output of external write signals (both WRH and WRL pins in external 16-bit data bus mode and WR pin in external 8-bit data bus mode), as shown in Table 8.2-10. In external 8-bit data bus mode, P33 functions as the I/O port regardless of the setting value of this bit. Table 8.2-10 WRE (External Write Signal Output Control Bit) Functions 0 I/O port (P33, P32) operation (write signal output disabled) [initial value] 1 Write strobe signal (WRH/WRL or WR only) output enabled 179 CHAPTER 8 MEMORY ACCESS MODES [Bit 9] LMBS The LMBS bit is used to specify the bus width for external access to the area from 008000H to 7FFFFFH in external 16-bit data bus mode. Control is based on the setting of this bit, as shown in Table 8.2-11. Table 8.2-11 LMBS (Bus Width Specification Bit) 0 16-bit bus width access [initial value] 1 8-bit bus width access Notes: 180 • To use the WRE bit to enable the WRH and WRL functions in external 16-bit data bus mode, place P33 and P32 in input mode (set bits 3 and 2 of the DDR3 register to 0). • To use the WRE bit to enable the WR function in external 8-bit data bus mode, place P32 in input mode (set bit 2 of the DDR3 register to 0). • If the RYE and HDE bits are used to enable the RDY and HRQ signals, the I/O port function of the port is also enabled. Be sure to write 0 (input mode) to the DDR3 register that corresponds to the port. CHAPTER 8 MEMORY ACCESS MODES 8.3 External Memory Access Control Signal Operation If the ready function is not used, external memory is accessed in three cycles. The 8-bit bus width access function is used to read and write the 8-bit width peripheral chip when the 8- and 16-bit width peripheral chips are connected together to the external bus. ■ External Memory Access Control Signal The HMBS, LMBS, and IOBS bits are used to specify whether 16-bit bus width access or 8-bit bus width access is to be used in external 16-bit data bus mode. The ALE and address signals may be asserted even when no external bus access is performed. Do not use the ALE signal only to allow access to the external component. The RD, WRL, and WRH signals must be used together with the ALE signal to control the external access. Figure 8.3-1 Access Timing Chart for External 8-bit Data Bus Mode) Read Read Write P37/CLK P33/WRH (Port data) P32/WRL/WR P31/RD P30/ALE P25 to P20/A21 to A16 Read address Write address Read address P17 to P10/A15 to A08 Read address Write address Read address P07 to P00/AD07 to AD00 Read address Write address Read address Read data Write data 181 CHAPTER 8 MEMORY ACCESS MODES Figure 8.3-2 Access Timing Chart for External 16-bit Data Bus Mode (16-bit bus width access) 8-bit bus width byte read Even address byte read 8-bit bus width byte write Even address byte write P37/CLK P33/WRH P32/WRL/WR P31/RD P30/ALE P25 to P20/A21 to A16 P17 to P10/AD15 to AD08 Read address P07 to P00/AD07 to AD00 Read address Read address Write address Read address Invalid (Undefined) Write address Read address Write address Write data Read data Odd address byte read Read address Odd address byte write P37/CLK P33/WRH P32/WRL/WR P31/RD P30/ALE P25 to P20/A21 to A16 Write address Read address P17 to P10/AD15 to AD08 Read address P07 to P00/AD07 to AD00 Read address Read address Read address Write address Invalid Read address Write data Read data Even address word read (Undefined) Write address Even address word write P37/CLK P33/WRH P32/WRL/WR P31/RD P30/ALE P25 to P20/A21 to A16 Write address Read address Read address P17 to P10/AD15 to AD08 Read address Write address Read address P07 to P00/AD07 to AD00 Read address Write address Read address Read data Write data Note: Set the external circuit so that data is always read in word mode. The setting of P36/RDY pin or the automatic ready function selection register (ARSR) enables access to low-speed memory and peripheral circuits. 182 CHAPTER 8 MEMORY ACCESS MODES 8.3.1 Ready Function The setting of P36/RDY pin or the automatic ready function selection register (ARSR) enables access to the low-speed memory and peripheral circuits. If the RYE bit of the bus control signal selection register (EPCR) is set to 1, the wait cycle is entered to enable extension of the access cycle while the L level is input to P36/ RDY signal during access to the external circuit. ■ Ready Function Figure 8.3-3 Timing Chart for Ready Function Even address word read Even address word write P37/CLK P33/WRH P32/WRL/WR P31/RD P30/ALE P25 to P20/A21 to A16 Read address Write address P17 to P10/AD15 to AD08 Read address Write address P07 to P00/AD07 to AD00 Read address Write address P36/RDY RDY pin fetch Even address word write Read data Write data Even address word read P37/CLK P33/WRH P32/WRL/WR P31/RD P30/ALE P25 to P20/A21 to A16 Read address Write address P17 to P10/AD15 to AD08 Write address Read address P07 to P00/AD07 to AD00 Write address Read address Write data Cycle extended by auto ready 183 CHAPTER 8 MEMORY ACCESS MODES The MB90350 series has two types of auto ready functions for external memory access. The auto ready function can automatically insert 1 to 3 wait cycles to extend the access cycle without an external circuit for access to the external areas at lower addresses 008000H to 7FFFFFH and at upper addresses 800000H to FFFFFFH. This function is activated according to the setting of the LMR1 and LMR0 bits (external areas at lower addresses) of ARSR and the HMR1 and HMR0 bits (external area at upper addresses) of ARSR. The MB90350 series also has an auto ready function for I/O that is independent of the auto ready function for memory. When the IOR1 and IOR0 bits of the ARSR register are set to 0, 1 to 3 wait cycles can be automatically inserted to extend the access cycle without an external circuit for access to the external area from addresses 0000C0H to 0000FFH. If the RYE bit of the EPCR register is set to "1" and when the P36/RDY pin is signaled as "0", then the wait cycle is extended even after the wait cycle by the auto ready function is completed. 184 CHAPTER 8 MEMORY ACCESS MODES 8.3.2 Hold Function If the HDE bit in the bus control signal selection register (EPCR) is set to 1, the external bus hold function specified by the P34/HRQ and P35/HAK pins is enabled. ■ Hold Function If the high level is applied to the P34/HRQ pin, the hold state is set up at termination of a CPU instruction (for a string instruction, at termination of 1-element data processing). The P35/HAK pin outputs the low level to place the following pins in a high-impedance state: • Address output: P25/A21 to P20/A16 • Address/data I/O: P17/AD15 to P00/AD00 • Bus control signal: P30/ALE, P31/RD, P32/WRL/WR, P33/WRH Thus, an external bus can be used from a device external circuit. When the low level is input to the P34/ HRQ pin, the P35/HAK pin outputs the high-level, thereby restoring the external pin state and restarting the CPU operation. In the stop status, hold request can not be accepted. Figure 8.3-4 shows the hold timing. Figure 8.3-4 Hold Timing Read cycle Hold cycle Write cycle P37/CLK P34/HRQ P35/HAK P33/WRH P32/WRL/WR P31/RD P30/ALE P25 to P20/A21 to A16 (Address) (Address) P17 to P10/AD15 to AD08 (Address) P07 to P00/AD07 to AD00 (Address) Read data Write data 185 CHAPTER 8 MEMORY ACCESS MODES 186 CHAPTER 9 I/O PORTS This chapter explains the functions and operations of the I/O ports. 9.1 I/O Ports 9.2 I/O Port Registers 187 CHAPTER 9 I/O PORTS 9.1 I/O Ports Each pin of the ports can be specified as input or output using the direction register if the corresponding peripheral does not use the pin. When a pin is specified as input, the logic level at the pin is read. When a pin is specified as output, the data register value is read. The above also applies to a read operation for the read-modify-write instructions. ■ I/O ports When a pin is used as an output of other peripheral function, the peripheral output value is read regardless of the direction register value. It is generally recommended that the read-modify-write instructions should not be used for setting the data register prior to setting the port as an output. This is because the read-modify-write instruction in this case results reading the logic level at the port rather than the register value. Figure 9.1-1 is a block diagram of the I/O ports. Figure 9.1-1 I/O port block diagram Internal data bus Data register read Data register Data register write Direction register Direction register write Direction register read 188 Pin CHAPTER 9 I/O PORTS 9.2 I/O Port Registers There are four types of I/O port registers: • Port data register (PDR0 to 6) • Port direction register (DDR0 to 6) • SIN input level setting register (DDRA) • Pull-up control register (PUCR0 to 3) • Analog input enable register (ADER) • Input level select register (ILSR) ■ I/O port registers Figure 9.2-1 shows the I/O port registers. Figure 9.2-1 I/O port registers Address: 000000H Bit 7 P07 6 P06 5 P05 4 P04 3 P03 2 P02 1 P01 0 P00 Port 0 data register (PDR0) Address: 000001H P17 P16 P15 P14 P13 P12 P11 P10 Port 1 data register (PDR1) Address: 000002H - - P25 P24 P23 P22 P21 P20 Port 2 data register (PDR2) Address: 000003H P37 P36 P35 P34 P33 P32 P31 P30 Port 3 data register (PDR3) Address: 000004H - - P45 P44 P43 P42 P41 P40 Port 4 data register (PDR4) Address: 000005H - P56 P55 P54 P53 P52 P51 P50 Port 5 data register (PDR5) Address: 000006H P67 P66 P65 P64 P63 P62 P61 P60 Port 6 data register (PDR6) Address: 000010H D07 D06 D05 D04 D03 D02 D01 D00 Port 0 direction register (DDR0) Address: 000011H D17 D16 D15 D14 D13 D12 D11 D10 Port 1 direction register (DDR1) Address: 000012H - - D25 D24 D23 D22 D21 D20 Port 2 direction register (DDR2) Address: 000013H D37 D36 D35 D34 D33 D32 D31 D30 Port 3 direction register (DDR3) Address: 000014H - - D45 D44 D43 D42 D41 D40 Port 4 direction register (DDR4) Address: 000015H - D56 D55 D54 D53 D52 D51 D50 Port 5 direction register (DDR5) Address: 000016H D64 D63 D62 D61 D60 D67 D66 D65 Address: 00001AH - SIL3 SIL2 - Address: 00001CH PU07 PU06 PU05 PU04 PU03 PU02 PU01 PU00 Port 0 pull-up control register (PUCR0) Address: 00001DH PU17 PU16 PU15 PU14 PU13 PU12 PU11 PU10 Port 1 pull-up control register (PUCR1) - - - - Port 6 direction register (DDR6) SIN input level setting register (DDRA) Address: 00001E H - - PU25 PU24 PU23 PU22 PU21 PU20 Port 2 pull-up control register (PUCR2) Address: 00001F H PU37 PU36 PU35 PU34 PU33 PU32 PU31 PU30 Port 3 pull-up control register (PUCR3) Address: 00000B H Bit 15/7 - 13/5 12/4 11/3 10/2 9/1 8/0 ADE14 ADE13 ADE12 ADE11 ADE10 ADE9 ADE8 Port 5 analog input enable register (ADER5) ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 Port 6 analog input enable register (ADER6) Address: 00000E H IL7 IL6 IL5 IL4 IL3 IL2 IL1 IL0 Input level select register0 (ILSR0) Address: 00000F H ILT3 ILT2 ILT1 ILT0 - - - - Input level select register1 (ILSR1) Address: 00000CH 14/6 189 CHAPTER 9 I/O PORTS 9.2.1 Port Data Register Note that R/W for I/O ports differ from R/W for memory in the following points: • Input mode Read: The level at the corresponding pin is read. Write: Data is written to an output latch. • Output mode Read: The data register latch value is read. Write: Data is written to an output latch and output to the corresponding pin. ■ Port data register Figure 9.2-2 shows the port data registers. Figure 9.2-2 Port data registers PDR0 7 6 5 4 3 2 1 0 Initial value Access Address: 000000H P07 P06 P05 P04 P03 P02 P01 P00 Undefined R/W PDR1 7 P17 6 P16 5 P15 4 P14 3 P13 2 P12 1 P11 0 P10 Undefined R/W PDR2 7 6 5 4 3 2 1 0 Address: 000002H - - P25 P24 P23 P22 P21 P20 Undefined R/W 7 P37 6 P36 5 P35 4 P34 3 P33 2 P32 1 P31 0 P30 Undefined R/W PDR4 7 6 5 4 3 2 1 0 Address: 000004H - - P45 P44 P43 P42 P41 P40 Undefined R/W PDR5 7 - 6 P56 5 P55 4 P54 3 P53 2 P52 1 P51 0 P50 Undefined R/W Undefined R/W Address: 000001H PDR3 Address: 000003H Address: 000005H PDR6 Address: 000006H R/W : Readable and writable : Undefined 190 7 6 5 4 3 2 1 0 P67 P66 P65 P64 P65 P62 P61 P60 CHAPTER 9 I/O PORTS ● Reading the port data register When a Port Data register is read, the value depends on the corresponding bit in the Data Direction Register and on the current status of the resource that is connected to the same pin (if applicable). The following cases are possible: DDR value Resource Read value 0 (input) enabled Resource value 1 (output) enabled Resource value 0 (input) disabled Pin value 1 (output) disabled PDR value 191 CHAPTER 9 I/O PORTS 9.2.2 Data Direction Register This register has following functions: • Setting the data direction of each pin that is used as a port. • Setting the input level of SIN -- Serial data input pin for LIN-UART. ■ Data direction register Figure 9.2-3 shows the Data Direction Registers. Figure 9.2-3 Data direction registers DDR0 Address: 000010H 7 6 5 4 3 2 1 0 Initial value Access D07 D06 D05 D04 D03 D02 D01 D00 00000000B R/W 00000000B R/W 00000000B R/W 00000000B R/W 00000000B R/W 00000000B R/W 00000000B R/W X00XXXXXB bit5,6 : W other : 7 6 5 4 3 2 1 0 D17 D16 D15 D14 D13 D12 D11 D10 DDR2 7 6 5 4 3 2 1 0 Address: 000012H - - D25 D24 D23 D22 D21 D20 DDR1 Address: 000011H 7 6 5 4 3 2 1 0 D37 D36 D35 D34 D33 D32 D31 D30 DDR4 7 6 5 4 3 2 1 0 Address: 000014H - - D45 D44 D43 D42 D41 D40 DDR5 7 6 5 4 3 2 1 0 Address: 000015H - D56 D55 D54 D53 D52 D51 D50 DDR3 Address: 000013H DDR6 Address: 000016H 7 6 5 4 3 2 1 0 D67 D66 D65 D64 D65 D62 D61 D60 DDRA 7 6 5 4 3 2 1 0 Address: 00001AH - SIL3 SIL2 - - - - - R/W : Readable and writable W : Write Only (Read always returns "1") - : Undefined • Bits Dxx (DDR0 to DDR6) These bits set the data direction of ports. When a pin is used as a port, the corresponding pin is controlled as described bellow: 0 Input mode 1 Output mode Note: The Data Direction Register can be read independently from the status of the corresponding resource. However, the value of the DDR influences the result of a read access on the Port Data Register. In MB90350 series, P26 and P27 corresponding to bit 6 and bit 7 of DDR2 are not existent, but be sure to set to "0". If setting to "1", abnormal operation can be occurred in emulation using MB90V340. 192 CHAPTER 9 I/O PORTS • Bits SIL2 to SIL3 (DDRA bit5 to bit6) These bits set the input level of the corresponding SIN (Serial Data Input for LIN-UART) signal to CMOS forcibly. SIL2 sets the input level of SIN2(LIN-UART2), SIL3 sets the input level of SIN2(LIN-UART3). Setting these bits to “0” selects CMOS or Automotive or TTL input, depending of the setting of the corresponding ILx bit and ILTx bit of ILSR. (About ILSR, please see section "9.2.5 Input Level Select Register", also.) Setting these bits to "1" selects CMOS input level, independent of the setting of the corresponding ILx bit and ILTx bit of ILSR. The initial value of these bits is “0”. Table 9.2-1 The input level setting of SIN2 SIL2 IL5 0 0 Automotive level 0 1 CMOS level 1 x CMOS level input level of SIN2 Table 9.2-2 The input level setting of SIN3 SIL3 ILT1 IL1 0 0 0 Automotive level 0 0 1 CMOS level 0 1 x TTL 1 x x CMOS level input level of SIN3 Note: SIL2 to SIL3 are write-only, and “1” is always read from these bits. Therefore, instructions that perform a read-modify-write (RMW) operation such as the INC/DEC instruction, cannot be used at DDRA. • DDRA: bit 0 to bit 4 ,bit 7(non-used bit) Reading value of these bits are undefined. writing is not effected. 193 CHAPTER 9 I/O PORTS 9.2.3 Pull-up Control Register (PUCR) Each pin of port0 to port3 has programmable pull-up resistor. Each bit of this register controls corresponding pull-up register whether to be used or not. Figure 9.2-4 shows the pull-up control register (PUCR), and Figure 9.2-5 is the block diagram. ■ Pull-up Control Register (PUCR) Figure 9.2-4 Pull-up Control Register PUCR0 7 Address: 00001CH PU07 6 PU06 15 PUCR1 PU17 Address: 00001DH PUCR2 14 PU16 7 6 Address: 00001E H 5 PU05 13 PU15 5 PU25 15 PUCR3 PU37 Address: 00001FH 14 PU36 13 PU35 4 PU04 12 PU14 4 PU24 12 PU34 3 PU03 11 PU13 3 PU23 11 PU33 2 1 PU02 10 0 PU01 9 PU12 2 10 Access 00000000B R/W PU10 00000000B R/W 00000000B R/W 00000000B R/W 0 PU21 9 PU32 Initial value 8 PU11 1 PU22 PU00 PU20 8 PU31 PU30 R/W : Readable and writable : Unused X : Undefined ■ Block Diagram of Pull-up Control Register (PUCR) Figure 9.2-5 Block Diagram of Pull-up Control Register (PUCR) Pull-up resistor (about 50KΩ) Data register Port input-output Direction register Resistor register Internal data bus In input mode, the pull-up resistor is controlled. 0: No pull-up resistor in input mode 1: Pull-up resistor in input mode Reading value of bit 6 and bit 7 in PUCR2 is undefined. Writing is not effected. Note: In output mode, this register has no meaning (no pull-up resistor). The direction register (DDR) determines the input-output mode. In stop mode (SPL=1), the state with no pull-up resistor is entered (high impedance). If the port is used as an external bus, this function is disabled and data is not written to the register. 194 CHAPTER 9 I/O PORTS 9.2.4 Analog Input Enable Register This register controls the port 5 to 7 pins as described below: 0: Port input/output mode 1: Analog input mode If an external pin is used as an analog input for the A/D converter, the corresponding bit should be set to “1”. ■ Analog input enable registers Figure 9.2-6 shows the analog input enable register. Figure 9.2-6 Analog input enable registers (ADER7/6/5) ADER6 Address: 00000CH ADER5 Address: 00000B H 7 6 5 4 3 2 1 0 ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 14 13 12 11 10 9 15 ADE14 ADE13 ADE12 ADE11 ADE10 ADE9 11111111B R/W X1111111B R/W 8 ADE8 R/W : Readable and writable : Unused X : Undefined ■ Note Initial value of the ADEx bits are "1". Therefore the corresponding pins can not be used as logical input/ output as initial setting. If these pins are used as IO ports or peripheral function IOs, then write "0" to the ADEx bits. 195 CHAPTER 9 I/O PORTS 9.2.5 Input Level Select Register The Input Level Select Register allows to switch from Automotive Hysteresis input levels to CMOS Hysteresis input levels or to TTL input levels. ■ Input level select register The input level select register ILSR is located on addresses 0EH and 0FH. Figure 9.2-7 Input level select register (ILSR) Address ILSR1 : 00000F H ILSR0 : 00000E H Initial value: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ILT3 ILT2 ILT1 ILT0 - - - - - IL6 IL5 IL4 IL3 IL2 IL1 IL0 R/W R/W R/W R/W - - - - - 0/1 0/1 0/1 0/1 X X X X X R/W R/W R/W R/W R/W R/W R/W 0/1 0/1 0/1 0/1 0/1 0/1 0/1 R/W : Readable and writable : Unused X : Undefined Bits 0 to 6: IL0 to IL6 These bits set the input level of the corresponding port. IL0 sets the input level of Port0, IL6 sets the input level of Port 6. Setting these bits to “0” selects the Automotive input level. Setting these bits to “1” selects the CMOS input level. The initial value of these bits depend on the mode pin setting: • For the Flash memory mode, the initial value is “1” (CMOS). • For all other modes, the initial value is "0" (Automotive). Bit 6 to 11: undefined Reading value of these bits are unused. Writing is not effected. Bit 12 to 15: ILT0 to ILT3 These bits set the input level of the corresponding port to TTL or CMOS/Automotive. ILT0 sets the input level of Port0, ILT3 sets the input level of Port3. Setting these bits to “0” selects the CMOS input level or the Automotive input level, depending of the setting of the corresponding ILx register. Setting these bits to “1” selects the TTL input level, independent of the setting of the corresponding ILx register. The initial value of these bits depend on the mode pin setting: • For the external reset vector fetch modes, the initial value is “1” (TTL). • For all other modes, the initial value is “0” (Automotive/CMOS). 196 CHAPTER 9 I/O PORTS ■ Initialization of ILSR Initial value of each bit of ILSR are determined when External Reset Signal is released depending on the value of MD2, MD1, MD0 pin input, as shown in following table. About detail of each mode, please see "CHAPTER 8 MEMORY ACCESS MODES". Initial value MD2 MD1 MD0 Port Input level Mode Name ILTx ILx Port 0 to 3 Port 4 to 6 0 0 0 External vector mode 0 1 0 TTL Automotive 0 0 1 External vector mode 1 1 0 TTL Automotive 0 1 0 0 1 1 Automotive Automotive 1 0 0 1 0 1 1 1 0 Flash memory serial programing 0 0 Automotive Automotive 1 1 1 Flash memory 0 1 CMOS CMOS Reserved Internal vector mode 0 0 Reserved 197 CHAPTER 9 I/O PORTS 198 CHAPTER 10 TIMEBASE TIMER This chapter explains the functions and operations of the timebase timer. 10.1 Outline of Timebase Timer 10.2 Timebase Timer Control Register 10.3 Operations of Timebase Timer 199 CHAPTER 10 TIMEBASE TIMER 10.1 Outline of Timebase Timer The timebase timer consists of an 18-bit timebase counter and a control register. The 18-bit timebase counter divides the system clock. The timebase timer issues interrupts at specified intervals based on carry signals of the timebase counter. ■ Outline of timebase timer When the power is turned on, the timebase counter can be cleared to all zeroes by setting the stop mode or by software (writing "0" to the TBR bit). The timebase counter is incremented while the source oscillation is input. The timebase counter can be used as a timer for supplying clock to the watchdog timer or for waiting for the oscillation to stabilize. ■ Block diagram of timebase timer Figure 10.1-1 shows a block diagram of the timebase timer. Figure 10.1-1 Block diagram of timebase timer To watchdog timer To PPG timer Timebase counter 21/HCLK × 21 × 22 × 23 × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218 OF Power-on reset Stop mode CKSCR: MCS = 1 0*1 CKSCR: SCS = 0 1*2 Counter clear circuit Reserved OF Interval timer selector TBOF set TBIE TBOF TBR TBC1 TBC0 Timebase timer interrupt signal OF HCLK *1 *2 200 OF To clock control block oscillation stabilization wait time selector TBOF clear Timebase timer control register (TBTC) OF : Overflow : Oscillation clock : When the machine clock is switched from the main clock to PLL clock. : When the machine clock is switched from the subclock to the main clock. CHAPTER 10 TIMEBASE TIMER 10.2 Timebase Timer Control Register The timebase timer control register controls interrupts of the timebase timer and can clear the timebase counter. ■ Timebase timer control register (TBTC) Figure 10.2-1 Configuration of the timebase timer control register (TBTC) Address: 0000A9 H 15 14 R/W - 13 12 11 10 9 Initial value 1XX00100B 8 - R/W R/W W R/W R/W bit9 bit8 TBC1 TBC0 0 0 1.024 ms (at 4 MHz) 0 1 4.096 ms (at 4 MHz) 1 0 16.384 ms (at 4MHz) 1 1 131.072 ms (at 4 MHz) Timebase Timer Interval Control bit10 Timebase Timer Reset TBR Read 0 Write clear all bits to 0 always 1 1 no effect bit11 Timebase Timer Interrupt Request Flag TBOF Read Write 0 no interrupt clear this bit 1 interrupt request no effect bit12 TBIE Timebase Timer Interrupt Enable 0 disable Interrupt 1 enable Interrupt bit13 Undefined bit14 Undefined bit15 Reser ved Reserved R/W W X - : : : : Readable and writable Write only (read always returns "0") Undefined value Undefined : Initial value 0 - 1 always write"1" to this bit Table 10.2-2 shows the settings for TBC1 and TBC0: 201 CHAPTER 10 TIMEBASE TIMER Table 10.2-1 Function description of each bit of the timebase timer control register Bit name Function bit 15 Reserved This is a reserved bit. When writing data to the TBTC register ensure that "1" is written to this bit. bit 14 Undefined bit 13 Undefined bit 12 TBIE This bit is used to enable interval interrupts based on the timebase timer. Writing "1" to this bit enables interrupts, and writing "0" disables interrupts. This bit is initialized to "0" upon a reset. This bit is readable and writable. bit 11 TBOF This is an interrupt request flag for the timebase timer. While the TBIE bit is "1", an interrupt request is issued when "1" is written to TBOF. This bit is set to "1" for each interval specified with the TBC1 and TBC0 bits. This bit is cleared by writing "0", transition to stop or a reset. Writing "1" has no effect. "1" is always read by a read-modify-write instruction. bit 10 TBR This bit is also cleared when transition to the stop mode or transition between different clock modes (from the subclock mode to the main clock mode, from the subclock mode to the PLL clock mode and from the main clock mode to the PLL clock mode), or by writing "0" to the TBR bit of the TBTC register and by any reset. bit 9/8 TBC1/0 These bits are used to set the timebase timer interval. Table 10.2-2 lists the specifiable intervals. Table 10.2-2 Selecting the timebase timer interval 202 TBC1 TBC0 Interval at 4 MHz source oscillation 0 0 1.024 ms 0 1 4.096 ms 1 0 16.384 ms 1 1 131.072 ms CHAPTER 10 TIMEBASE TIMER 10.3 Operations of Timebase Timer The timebase timer functions as a watchdog timer clock source, timer for waiting for the oscillation to stabilize, and interval timer for generating interrupts at specified intervals. ■ Timebase counter The timebase counter consists of an 18-bit counter for a clock generated by dividing the source oscillation input by two. This clock is used to generate the machine clock. While the source oscillation is input, the timebase counter keeps counting. The timebase counter is cleared by a power-on reset, transition to stop or writing “0” to the TBR bit of the TBTC register. ■ Interval interrupt function Interrupts are generated at specified intervals according to the carry signals of the timebase counter. The TBOF flag is set at the intervals specified with the TBC1 and TBC0 bits of the TBTC register. The flag is set with reference to the time at which the timebase timer is cleared last time. Upon transition from stop mode, the timebase timer is used as a timer for waiting for the oscillation to stabilize upon recovery. Therefore, the TBOF flag is immediately cleared upon the mode transition to the stop mode. ■ Timebase counter clear The timebase timer counter is cleared when transition to the stop mode or transition between different clock modes (from the subclock mode to the main clock mode, from the subclock mode to the PLL clock mode and from the main clock mode to the PLL clock mode), or by writing "0" to the TBR bit of the TBTC register and by the power on reset. 203 CHAPTER 10 TIMEBASE TIMER 204 CHAPTER 11 WATCHDOG TIMER This chapter explains the functions and operations of the watchdog timer. 11.1 Outline of WatchDog Timer 11.2 Watchdog Timer Operation 205 CHAPTER 11 WATCHDOG TIMER 11.1 Outline of WatchDog Timer The watchdog timer consists of a two-bit watchdog counter, control register, and watchdog reset controller. The two-bit watchdog counter uses the carry signals of an 18-bit timebase counter as a clock source. ■ Watchdog timer block diagram Figure 11.1-1 is a diagram of the configuration of the watchdog timer. Figure 11.1-1 Watchdog timer block diagram Watch-dog timer control register (WDTC) PONR Watch timer control register (WTC) WRST ERST SRST WTE WT1 WT0 Watchdog timer WDCS 2 Activation Reset occurrence Transition to sleep mode Transition to timebase timer mode Transition to watch mode Transition to stop mode Counter clear control circuit Count clock selector 2-bit counter Watch-dog reset generation circuit To internal reset generation circuit Clear 4 4 (Timebase timer counter) Main clock (HCLK divided by 2) × 21 × 22 × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218 (Watch counter) Subclock SCLK* × 21 × 22 × 25 × 26 × 27 × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 HCLK : Oscillation clock SCLK : Subclock * : SCLK is the oscillation circuit clock (X0A pin and X1A pin) divided by 2 or 4. The division ratio is determined by SCDS bit of PLL/Subclock Control Register (PSCCR). (Refere to "CHAPTER 5 CLOCKS".) 206 CHAPTER 11 WATCHDOG TIMER ■ Watchdog timer control register (WDTC) WDTC Address : 0000A8H 7 6 PONR - R - 5 4 WRST ERST SRST R R 2 1 0 Initial value WTE WT1 WT0 XXXXX111B W W W 3 R [bit 7, bit 5 to 3] PONR, WRST, ERST, and SRST These flags indicate the reset causes. The flags are set upon a reset as described in Table 11.1-1. All bits are cleared to "0" after the WDTC register is read. These bits are read-only bits. Table 11.1-1 Reset cause registers Reset cause PONR WRST ERST SRST Power-on 1 -- -- -- Watchdog timer * 1 * * External pin * * 1 * RST bit * * * 1 *: The previous value is maintained. [bit 2] WTE While the watchdog timer is stopped, writing "0" to this bit activates the watchdog timer. Subsequently, writing "0" clears the watchdog timer counter. Writing "1" has no effect. The watchdog timer is stopped by power-on or reset by watchdog timer. "1" is always read from this bit. 207 CHAPTER 11 WATCHDOG TIMER [bits 1 and 0] WT1 and WT0 These bits are used to select the watchdog timer interval. Only the data items written during watchdog timer activation are valid. Data items that are written outside watchdog timer activation are ignored. Table 11.1-2 lists the interval settings. These bits are write-only bits. • When selecting timebase timer output (WTC: WDCS = 0) Table 11.1-2 Watchdog timer interval selection bit Interval * WT1 WT0 Main clock cycle count Minimum Maximum 0 0 approx. 3.58 ms approx. 4.61 ms 214 plus or minus 211 cycles 0 1 approx. 14.33 ms approx. 18.43 ms 216 plus or minus 213 cycles 1 0 approx. 57.23 ms approx. 73.73 ms 218 plus or minus 215 cycles 1 1 approx. 458.7 ms approx. 589.82 ms 221 plus or minus 218 cycles *: For a source oscillation of 4 MHz. • When selecting watch timer output (WTC: WDCS = 1) Table 11.1-3 Watchdog timer interval selection bit Interval * WT1 WT0 Main clock cycle count Minimum Maximum 0 0 approx. 0.438 s approx. 0.563 s 212 plus or minus 29 cycles 0 1 approx. 3.5 s approx. 4.5 s 215 plus or minus 212 cycles 1 0 approx. 7.0 s approx. 9.0 s 216 plus or minus 213 cycles 1 1 approx. 14.0 s approx. 18.0 s 217 plus or minus 214 cycles *: For a source oscillation of 8.192 kHz. Note: The interval time uses carry signal of the time-base timer or watch timer as a count clock. If the timebase timer or watch timer is cleared, the interval time of the watchdog timer may become longer. The time-base timer is also cleared by writing zero to the TBR bit in the time-base timer control register (TBTC), transition from main clock mode to PLL clock mode, transition from subclock mode to main clock mode and transition from subclock mode to PLL clock mode. 208 CHAPTER 11 WATCHDOG TIMER 11.2 Watchdog Timer Operation The watchdog timer function enables detection of program surge. If the watchdog timer is not accessed within the specified time due to, for example, a program surge, the watchdog timer resets the system. ■ Activation The watchdog timer is activated by writing "0" to the WTE bit of the WDTC register while the watchdog timer is stopped. At the same time, the WT1 and WT0 bits are used to set the watchdog timer reset interval. Only the interval setting specified during activation is valid. ■ Watchdog counter Once the watchdog timer is activated, the watchdog timer counter must be periodically cleared within the program. Writing "0" to the WTE bit of the WDTC register clears the watchdog counter. The watchdog counter consists of a two-bit counter which uses carry signals of the timebase counter or watch timer as a clock source. Therefore, the watchdog reset time may become shorter than the setting if the timebase counter is cleared. The watchdog counter is cleared not only by writing to the WTE bit but also by reset and transition to the standby (sleep, stop, watch, timebase timer modes) or stop mode. Figure 11.2-1 is a diagram of the watchdog timer operation. Figure 11.2-1 Watchdog timer operation Timebase Watch-dog 00 01 10 00 01 10 11 00 WTE write Watch-dog activation Watch-dog clear Watch-dog reset ■ Watchdog stop Once activated, the watchdog timer can be stopped only by reset. 209 CHAPTER 11 WATCHDOG TIMER 210 CHAPTER 12 16-BIT I/O TIMER This chapter explains the functions and operations of the 16-bit I/O timer. 12.1 Outline of 16-Bit I/O Timer 12.2 16-Bit I/O Timer Registers 12.3 16-bit Free-running Timer 12.4 Output Compare 12.5 Input Capture 211 CHAPTER 12 16-BIT I/O TIMER 12.1 Outline of 16-Bit I/O Timer The MB90350 Series contains two 16-bit free-running timer modules, two output compare modules, and four input capture modules and supports eight input channels and four output channels. The following sections describe the 16-bit free-running timer, Output Compare and Input Capture. ■ 16-bit free-running timer The two 16-bit free-run timers consist of a 16-bit up counter, control register, and prescaler each. The values output from these timer counters are used as the base time for input capture and output compare. ● Eight counter clocks are available. Internal clock: φ, φ/2, φ/4, φ/8, φ/16, φ/32, φ/64, φ/128 (φ: machine clock) ● An interrupt can be generated upon a counter overflow or a match with compare register 0 and 4. ● The counter value can be initialized to "0000H" upon a reset, software clear, or match with compare register 0 for timer 0, resp. compare register 4 for timer 1. ■ Output compare (2 channels per one module) The two output compare modules consist of two 16-bit compare registers, compare output latch, and control register each. Output Compare 2 and 3 (channels OUT4, OUT5, OUT6 and OUT7) are assigned to Free-running Timer 1. When a 16-bit free-running timer value matches the corresponding compare register value, the output level is toggled and an interrupt can be issued. ● The two compare registers can be used independently for each Output Compare. Output pins and interrupt flags corresponding to compare registers ● Output pins can be controlled based on pairs of the two compare registers. Output pins can be toggled by using the two compare registers. ● Initial values for output pins can be set. ● Interrupts can be generated upon a compare match. 212 CHAPTER 12 16-BIT I/O TIMER ■ Input capture (2 channels per one module) The four input capture modules consist of two 16-bit capture registers and control registers each corresponding to two independent external input pins. The 16-bit free-running timer values can be stored in the capture register and an interrupt is issued simultaneously upon detection of an edge of a signal input from an external input pin. ● The detection edge of an external input signal can be specified. Rising, falling, or both edges ● Two input channels can operate independently. ● An interrupt can be issued upon a valid edge of an external input signal. The intelligent I/O service can be activated upon an input capture interrupt. ■ Block diagram of 16-bit I/O timer Figure 12.1-1 shows a block diagram of the 16-bit I/O timer. Figure 12.1-1 Block diagram of 16-bit I/O timer Control logic To each block Interrupt 16-bit free-run timer 0/1 16-bit timer FRCK0 FRCK1 Bus Clear Output compare 4/6 Compare register 0 T Q OUT4 OUT6 T Q OUT5 OUT7 Output compare 5/7 Compare register 1 Input capture 0/2/4/6 Capture register 0 Input capture 1/3/5/7 Capture register 1 Edge selection IN0 IN2 IN4 IN6 Edge selection IN1 IN3 IN5 IN7 213 CHAPTER 12 16-BIT I/O TIMER 12.2 16-Bit I/O Timer Registers The 16-bit I/O timer has the following three registers: • 16-bit free-running timer register • 16-bit output compare register • 16-bit input capture register ■ 16-bit free-running timer 0 and 1 15 0 007940 H TCDT0 Timer data register 0 007944 H TCDT1 Timer data register 1 007942 H 007943 H TCCSH0 TCCSL0 Timer status register 0 007946 H 007947 H TCCSH1 TCCSL1 Timer status register 1 ■ 16-bit output compare 15 214 0 007930 H 007932 H OCCP0/1 Compare register 0/1 007934 H 007936 H OCCP2/3 Compare register 2/3 007938 H 00793A H OCCP4/5 Compare register 4/5 00793C H 00793E H OCCP6/7 Compare register 6/7 00005C H 00005D H OCS5 OCS4 Control status register 4/5 00005E H 00005F H OCS7 OCS6 Control status register 6/7 CHAPTER 12 16-BIT I/O TIMER ■ 16-bit input capture 15 0 007920 H 007922 H IPCP0/1 Capture register 0/1 007924 H 007926 H IPCP2/3 Capture register 2/3 007928 H 00792A H IPCP4/5 Capture register 4/5 00792C H 00792E H IPCP6/7 Capture register 6/7 000050 H 000051 H ICS01 000053 H ICS23 ICS45 000057 H ICS67 ICE67 Control register 4/5 Capture Edge register 4/5 ICE45 000056 H Control register 2/3 Capture Edge register 2/3 ICE23 000054 H 000055 H Capture Edge register 0/1 ICE01 000052 H Control register 0/1 Control register 6/7 Capture Edge register 6/7 215 CHAPTER 12 16-BIT I/O TIMER 12.3 16-bit Free-running Timer The 16-bit free-running timer consists of a 16-bit up counter and a control status register. The count values of this timer are used as the base time for the output compares and input captures. • Eight counter clock frequencies are available. • An interrupt can be generated upon a counter value overflow. • The counter value can be initialized upon a match with compare register 0 and compare register 4, depending on the mode. • Two separate timers are available on MB90350 series ■ 16-bit free-running timer block diagram Figure 12.3-1 16-bit free-running timer block diagram φ Interrupt request IVF IVFE STOP MODE CLR CLK2 CLK1 CLK0 Divider FRCK0 Comparator 0 /1 Bus 16-bit up counter Clock Count value output Note: The figure above is also valid for Timer 1 Timer 0 is connected to ICU0/1/2/3 and OCU0/1/2/3 Timer 1 is connected to ICU4/5/6/7 and OCU4/5/6/7 216 T15 to T00 CHAPTER 12 16-BIT I/O TIMER 12.3.1 Data Register The data register can read the count value of the 16-bit free-running timer. The counter value is cleared to "0000" upon a reset. The timer value can be set by writing a value to this register. However, ensure that the value is written while the operation is stopped (STOP=1). The data register must be accessed by the word access instructions. ■ Data register of free-running timer Figure 12.3-2 Data register of free-running timer (TCDT0/1) Address: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TCDT0:007940 H 007941 H R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCDT1:007944 H 007945 H TCDT0/1 Initial value 0000000000000000B bit0 to bit7 TCDT0/1 lower bits Tn0 Timer Data Reg. 0 Tn1 Timer Data Reg. 1 Tn2 Timer Data Reg. 2 Tn3 Timer Data Reg. 3 Tn4 Timer Data Reg. 4 Tn5 Timer Data Reg. 5 Tn6 Timer Data Reg. 6 Tn7 Timer Data Reg. 7 n = 0, 1 bit8 to bit15 TCDT0/1 Tn8 R/W : Readable and writable upper bits Timer Data Reg. 8 Tn9 Timer Data Reg. 9 Tn10 Timer Data Reg. 10 Tn11 Timer Data Reg. 11 Tn12 Timer Data Reg. 12 Tn13 Timer Data Reg. 13 Tn14 Timer Data Reg. 14 Tn15 Timer Data Reg. 15 n = 0, 1 The 16-bit free-running timer is initialized upon the following factors: • Reset • Clear bit (CLR) of control status register • A match between compare register 0 and the timer counter value. 217 CHAPTER 12 16-BIT I/O TIMER 12.3.2 Control Status Register The control status register sets the operation mode of the 16-bit free-running timer, starts and stops the 16-bit free-running timer, and controls interrupts. ■ Control status register of free-running timer (lower) Figure 12.3-3 Control status register of free-running timer (TCCSL0/1) Address: TCCSL0:007942 H TCCSL1:007946 H 7 6 5 4 3 2 1 0 TCCSL0/1 Initial value 0 0 0 0 0 0 0 0B R/W R/W R/W R/W R/W R/W R/W R/W bit 2 bit1 CLK2 CLK1 bit 0 0 0 0 φ 0 0 1 φ/2 0 1 0 φ/4 0 1 1 φ/8 1 0 0 φ / 16 1 0 1 φ / 32 1 1 0 φ / 64 1 1 1 φ / 128 CLK0 Count Clock Selection φ = MCU clock bit 3 CLR 0 1 Clear Timer Read read always "0" Write no effect clear timer to "0000" bit 4 MODE 0 1 Set Reset condition of timer Initialization by reset or clear bit Init. by reset, clear bit, or compare reg. 0 and 4 bit 5 STOP 0 1 Stop the timer Counter enabled Counter disabled (stop) bit 6 IVFE Interrupt enable bit 0 Interrupt disabled 1 Interrupt enabled bit 7 IVF R/W : : 218 Interrupt request flag bit Read Write Readable and writable 0 No interrupt clear this bit Initial value 1 Interrupt request no effect CHAPTER 12 16-BIT I/O TIMER Table 12.3-1 Control status register of free-running-timer (lower) Bit name Function bit 7 IVF • • • • • This bit is the interrupt request flag bit and clear bit Writing "0": A possible interrupt is cleared. Writing "1": No effect. "1" is always read during a read-modify-write cycle. This bit is set to "1" if the free-running timer overflows or if the timer value matches with the compare register 0 and 4 when the MODE bit is set to "1". bit 6 IVFE • This bit enables the interrupt request • Writing "0": Interrupt disabled. • Writing "1": Interrupt enabled. bit 5 STOP • The STOP bit is used to stop the timer. • Writing "0": Counter enabled (operation). • Writing "1": Counter disabled (stop). bit 4 MODE • "0": Initialization by reset or clear bit • "1": Initialization by reset, clear bit, or compare register 0 and 4 bit 3 CLR • The CLR bit initializes the operating free-running timer to the value "0000" • Writing "0": no effect. • Writing "1": Counter is initialized. Note: To initialize the counter value while the timer is stopped (STOP = 1), write "0000" to the data register (TCDT). bit 2 to 0 CLK2, CLK1, CLK0 These bits are used to select the count clock for the 16-bit-free-running timer. The clock is updated immediately after a value is written to these bits. Therefore, ensure that the input capture and output compare operations are stopped before a value is written to these bits. CLK2 CLK1 CLK0 Count clock Φ = 20 MHz Φ = 16 MHz Φ=8 MHz Φ=4 MHz Φ=1 MHz 0 0 0 Φ 50 ns 62.5 ns 125 ns 0.25 µs 1 µs 0 0 1 Φ/2 100 ns 125 ns 0.25 µs 0.5 µs 2 µs 0 1 0 Φ/4 0.2 µs 0.25 µs 0.5 µs 1 µs 4 µs 0 1 1 Φ/8 0.4 µs 0.5 µs 1 µs 2 µs 8 µs 1 0 0 Φ / 16 0.8 µs 1 µs 2 µs 4 µs 16 µs 1 0 1 Φ / 32 1.6 µs 2 µs 4 µs 8 µs 32 µs 1 1 0 Φ / 64 3.2 µs 4 µs 8 µs 16 µs 64 µs 1 1 1 Φ / 128 6.4 µs 8 µs 16 µs 32 µs 128 µs 219 CHAPTER 12 16-BIT I/O TIMER ■ Control status register of free-running timer (upper) Figure 12.3-4 Control status register of free-running timer (TCCSH0/1) Address: TCCSH0:007943 H TCCSH1:007947 H 15 14 13 12 11 10 9 8 TCCSH0/1 Initial value 0xxxxxxx R/W - - - - - - ECKE R/W : Readable and writable - : Undefined : Initial value B External clock enable 0 Internal time clock 1 external clock from FRCK pin Table 12.3-2 Control status register of free-running-timer (upper) Bit name bit 15 ECKE bit 14 to 8 Undefined 220 Function • This bit chose between internal time clock and external clock from FRCK • Writing “0”: Internal clock selected. • Writing “1”: External clock selected. CHAPTER 12 16-BIT I/O TIMER 12.3.3 16-bit Free-running Timer Operation The 16-bit free-running timer starts counting from counter value "0000" after the reset is released. The counter value is used as the base time for the 16-bit output compare and 16-bit input capture operations. ■ 16-bit free-running timer operation The counter value is cleared in the following conditions: • When an overflow occurs. • When a match with the output compare register 0 and 4 occurs. (This depends on the mode.) • When "1" is written to the CLR bit of the TCCS register during operation. • When "0000" is written to the TCDT register during stop. • Reset An interrupt can be generated when an overflow occurs or when the counter is cleared by a match with the compare register 0 and 4. (Compare match interrupts can be used only in an appropriate mode.) ■ Clearing the counter by an overflow Figure 12.3-5 Clearing the counter by an overflow Counter value FFFF H Overflow BFFF H 7FFF H 3FFF H 0000 H Time Reset Interrupt 221 CHAPTER 12 16-BIT I/O TIMER ■ Clearing the counter upon a match with output compare register 0 Figure 12.3-6 Clearing the counter upon a match with output compare register 0 Counter value FFFF H Match BFFF H Match 7FFF H 3FFF H Time 0000 H Reset Compare register value Interrupt BFFFH ■ 16-bit free-running timer timing ● 16-bit free-running timer clear timing (match with the compare register 0) The counter can be cleared upon a reset, software clear, or a match with the compare register 0. By a reset or software clear, the counter is immediately cleared. By a match with compare register 0, the counter is cleared in synchronization with the count timing. Figure 12.3-7 16-bit free-running timer clear timing (match with the compare register 0) φ N Compare register value Compare match Counter value 222 N 0000 CHAPTER 12 16-BIT I/O TIMER 12.4 Output Compare The output compare module consists of two 16-bit compare registers, two compare output pins, and one control register. If the value written to the compare register of this module matches the 16-bit free-running timer value, the output level of the pin can be toggled and an interrupt can be issued. ■ Output compare • Four separate Output Compare Modules are available on MB90350 series. • For each module, two compare registers exist which can be used independently. Depending on the mode setting, the two compare registers can be used to control pin outputs. • The initial value for each pin output can be specified separately. • An interrupt can be issued upon a match as a result of comparison. • Each module can generate one PWM signal using two compare registers. (Except for OUT4 pin) • Two PWM signals can be generated by one output compare module using three compare registers. (OUT6/7 pins) • There compare registers can be used to generate one cyclic waveform signal. (OUT7 pin) ■ Output compare block diagram Figure 12.4-1 shows a block diagram of output compare. Figure 12.4-1 Output compare block diagram 16-bit timer counter value (T15 to T00) T Compare control Q OTE4 OUT4 CMP4EXT Compare register 4 CMOD1 16-bit timer counter value (T15 to T00) Bus CMOD0 T Compare control Q OTE5 OUT5 Compare register 5 ICP5 ICP4 ICE5 ICE4 Controller Control blocks Compare 5 interrupt Compare 4 interrupt Note: The figure above is also valid for Output Compare Unit 6/7 The CMP4EXT signal is explained in Figure 13.4-5 223 CHAPTER 12 16-BIT I/O TIMER 12.4.1 Output Compare Register These 16-bit compare registers are compared with the 16-bit free-running timer. Since the initial register values are undefined, set appropriate value before enabling the operation. These registers must be accessed by the word access instructions. When the value of the register matches that of the 16-bit free-running timer, a compare signal is generated and the output compare interrupt flag is set. If output is enabled, the output level corresponding to the compare register is reversed. If a compare match coincides with write operation to this register, resulting compare operation is not predictable. Therefore make sure to evaluate the counter value of the free-running timer or to initialize the timer before writing to this register. ■ Output compare register Figure 12.4-2 Output compare register (OCCP) Address: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OCCP0:007930 H OCCP0:007931 H OCCP1:007932 H OCCP1:007933 H R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W OCCP2:007934 H OCCP2:007935 H OCCP3:007936 H OCCP3:007937 H OCCP0 OCCP1 : OCCP7 Initial value XXXXXXXXXXXXXXXX bit0 to bit7 OCCPn OCCP4:007938 H OCCP4:007939 H OCCP5:00793A H OCCP5:00793B H OCCP6:00793C H OCCP6:00793DH OCCP7:00793E H OCCP7:00793F H lower bits C00 Compare Data Reg. 0 C01 Compare Data Reg. 1 C02 Compare Data Reg. 2 C03 Compare Data Reg. 3 C04 Compare Data Reg. 4 C05 Compare Data Reg. 5 C06 Compare Data Reg. 6 C07 Compare Data Reg. 7 n = 0, 1, 2, 3, 4, 5, 6, 7 bit8 to bit15 OCCPn R/W 224 : Readable and writable upper bits C08 Compare Data Reg. 8 C09 Compare Data Reg. 9 C10 Compare Data Reg. 10 C11 Compare Data Reg. 11 C12 Compare Data Reg. 12 C13 Compare Data Reg. 13 C14 Compare Data Reg. 14 C15 Compare Data Reg. 15 n = 0, 1, 2, 3, 4, 5, 6, 7 B CHAPTER 12 16-BIT I/O TIMER 12.4.2 Control Status Register of Output Compare The control status register sets the operation mode of output compare, starts and stops output compare, controls interrupts, and sets the external output pins. ■ Control status register of output compare (lower byte) Figure 12.4-3 Control status register of output compare (OCS4/6) Address: OCS4:00005C H 7 6 5 4 3 2 1 0 OCS6:00005E H R/W R/W R/W R/W - - R/W R/W OCS4 OCS6 Initial value 0 0 0 0 X X 0 0B bit 0 CSTn Comparison with timer for unit n (even) 0 Compare operation disabled for unit n 1 Compare operation enabled for unit n bit 1 CSTm Comparison with timer for unit m (odd) 0 Compare operation disabled for unit m 1 Compare operation enabled for unit m bit 4 ICEn Compare interrupt enable for unit n (even) 0 Output compare interrupt disabled for unit n 1 Output compare interrupt enabled for unit n bit 5 ICEm Compare interrupt enable for unit m (odd) 0 Output compare interrupt disabled for unit m 1 Output compare interrupt enabled for unit m bit 6 ICPn Compare match enable for unit n (even) 0 No compare match for unit n 1 Compare match for unit n bit 7 ICPm Compare match enable for unit m (odd) R/W : Readable and writable 0 No compare match for unit m X : : Undefined value Undefined 1 Compare match for unit m : Initial value - n = 4, 6 m = 5, 7 225 CHAPTER 12 16-BIT I/O TIMER Table 12.4-1 Control status register of output compare (lower) Bit name Function bit 7 ICPm bit 6 ICPn • These bits are used as output compare interrupt flags. "1" is set to these bits when the compare register value matches the 16-bit free-run timer value. While the interrupt request bits (ICEm and ICEn) are enabled, an output compare interrupt occurs when the ICPm and ICPn bits are set. These bits are cleared by writing "0". • "0": No compare match. • "1": Compare match. • Writing "1" has no effect. • "1" is always read by a read-modify-write instruction. Note: ICPn: Corresponds to output compare n (even). ICPm: Corresponds to output compare m (odd). bit 5 ICEm bit 4 ICEn bit 3 to 2 Undefined bit 1 CSTm bit 0 CSTn n = 4, 6 226 m = 5, 7 • These bits are used as output compare interrupt enable flags. While the "1" is written to these bits, an output compare interrupt occurs when an interrupt flag (ICPm or ICPn) is set. • Writing "0": Output compare interrupt disabled. • Writing "1": Output compare interrupt enabled. Note: ICEn: Corresponds to output compare unit n (even). ICEm: Corresponds to output compare unit m (odd). • These bits are used to enable the compare operation. • Writing "0": Compare operation disabled. • Writing "1": Compare operation enabled. Note: Ensure that a value is written to the compare register before the compare operation is enabled. CSTn: Corresponds to output compare n (even). CSTm: Corresponds to output compare m (odd). Since output compare is synchronized with the 16-bit free-running timer clock, stopping the 16-bit free-running timer stops compare operation. CHAPTER 12 16-BIT I/O TIMER ■ Control status register of output compare (upper byte) Figure 12.4-4 Control status register of output compare (OCS5/7) Address: OCS5:00005DH 15 14 13 12 11 10 9 8 OCS7:00005F H R/W - - R/W R/W R/W R/W R/W OCS5 OCS7 Initial value 0XX00000B bit 8 OTDn Output Pin Level Select for unit n (odd) 0 Sets "0" for compare pin output for unit n 1 Sets"1" for compare pin output for unit n bit 9 OTDm Output Pin Level Select for unit m (even) 0 Sets "0" for compare pin output for unit m 1 Sets"1" for compare pin output for unit m bit 10 OTEn General-purpose port for correspond. pin of unit n 1 Output compare pin output for unit n bit11 OTEm R/W : Readable and writable X - : : Undefined value Undefined : Initial value Output Pin Select for unit n (odd) 0 Output Pin Select for unit m (even) 0 General-purpose port for correspond. pin of unit m 1 Output compare pin output for unit m bit 15 bit 12 CMOD1 CMOD0 0 0 Define Comparison mode for Pin see description for details n = 4, 6 m = 5, 7 227 CHAPTER 12 16-BIT I/O TIMER Table 12.4-2 Control status register of output compare (upper) Bit name Function bit 15 and 12 CMOD0, CMOD1 bit 14, 13 Undefined bit 11 OTEm bit 10 OTEn bit 9 OTDm bit 8 OTDn n = 4, 6 These bits define the operation mode for the pin output signals. Depending on the defined mode, the level is toggled upon a match with different compare registers. See Table 12.4-3 and Section "12.4.3 16-bit Output Compare Operation" for details. These bits are used to enable the output compare output pins. The initial value for these bits is "0". • "0": General-purpose port. • "1": Output compare pin output. Note: OTEn: Corresponds to output compare n (n is an even number). OTEm: Corresponds to output compare m (m is an odd number). When they are specified as outputs, the corresponding bits of the Port Direction Registers should also be set to "1". These bits are used to change the pin output level when the compare pin output is enabled. The initial value of the compare pin output is "0". Ensure that the compare operation is stopped before a value is written. When read, these bits indicate the output compare pin output value. • Writing "0": Sets "0" for compare pin output. • Writing "1": Sets "1" for compare pin output. Note: OTDn: Corresponds to OUTn. (n is an even number). OTDm: Corresponds to OUTm. (m is an odd number). m = 5, 7 Table 12.4-3 Function of CMOD1 and 0 bits Pin output value toggled upon match with compare register number OCS5 Register OCCPx CMOD1 CMOD0 OUT4 OUT5 x 0 4 5 x 1 4 4/5 OCS7 228 Register OCCPx CMOD1 CMOD0 OUT6 OUT7 0 0 6 7 0 1 6 6/7 1 0 4/6 4/7 1 1 4/6 4/6/7 CHAPTER 12 16-BIT I/O TIMER Figure 12.4-5 Block diagram of output selection (OCU module 1) Compare Control 6 OUT6 CMOD1 CMP4EXT CMOD0 Compare Control 7 OUT7 For OCU module 1, which requires a match with Output Compare Register 0 if CMOD[1:0] = “10B” the comparison result from module 0 is carried inside by the CMP4EXT signal. Of course, this does not apply to module 0 itself. Here, no other register can be used but OCCP4 and OCCP5. 229 CHAPTER 12 16-BIT I/O TIMER 12.4.3 16-bit Output Compare Operation In the 16-bit output compare operation, an interrupt request flag can be set and the output level can be toggled when the specified compare register value matches the 16bit free-run timer value. The CMOD0 and CMOD1 bits can be used to define the corresponding compare registers for each pin. ■ Sample output waveform when CMOD[1:0] = "00B" When CMOD[1:0] = “00B”, the output level of the pin corresponding to the compare register is reversed on every match with the register value. Each output value is controlled by one compare register. OUT4: The level is only reversed by a match with compare register 4. OUT5: The level is only reversed by a match with compare register 5. Figure 12.4-6 Sample of output waveform when CMOD[1:0] = "00B" Counter value FFFFH BFFFH 7FFFH 3FFFH 0000H Time Reset OCCP0 value BFFFH OCCP1 value 7FFFH OUT4 OUT5 Compare 4 interrupt Compare 5 interrupt Note: In this figure, the initial value is "0" for both pins. 230 CHAPTER 12 16-BIT I/O TIMER ■ Sample output waveform with two compare registers when CMOD[1:0] = "01B" When CMOD[1:0] = "01B", the output level of the pin corresponding to compare register 4 (6) is reversed upon every match with the register value. This is identical to the behavior for CMOD[1:0] = "00B". However, the output level of the second pin is reversed upon a match with either compare register 4 or compare register 5 (7). This allows to define a pulsed signal with one edge defined by the value in compare register 4 and the other edge defined by compare register 5 (7) or vice versa. If both compare registers have the same value, the operation is identical to the case for CMOD[1:0] = "00B". A pulse width modulated signal with differing frequency can be defined by using this mode together with the reset option by compare register match for the Free-running timer (MODE-bit in TCCSL1 registers). OUT4 (6): The level is only reversed by a match with compare register 4 (6). OUT5 (7): The level is reversed by a match with compare register 4 (6) or with compare register 5 (7). Figure 12.4-7 Sample of a output waveform when CMOD[1:0] = "01B" (no timer reset by match) Counter value FFFFH BFFFH 7FFFH 3FFFH 0000H Time Reset OCCP4 value BFFFH OCCP5 value 7FFFH OUT4 OUT5 Note: In this figure, the initial value is "0" for both pins. Figure 12.4-8 Sample of a output waveform when CMOD[1:0] = "01B" (with timer reset by match) Counter value FFFFH BFFFH 7FFFH 3FFFH 0000H Time Reset OCCP4 value BFFFH OCCP5 value 7FFFH OUT4 OUT5 Note: In this figure, the initial value is "0" for both pins. 231 CHAPTER 12 16-BIT I/O TIMER ■ Sample output waveform when CMOD[1:0] = "10B" The operation mode defined by CMOD[1:0] = "10B" is intended for the use of three pulse width modulated signals for each free-running timer instead of two. If this mode is set to OCU module 1, a match of the timer value with compare register 0 reverses both OUT6 and OUT7. For the third pulsed signal, the CMOD[1:0] bits of OCU module 0 should be set to "01B". In register OCS5: CMOD[1:0] = "01B" OUT4: The level is only reversed by a match with compare register 4. OUT5: The level is reversed by a match with compare register 4 or with compare register 5. In register OCS7: CMOD[1:0] = "10B" OUT6: The level is reversed by a match with compare register 4 or with compare register 6. OUT7: The level is reversed by a match with compare register 4 or with compare register 7. Figure 12.4-9 Output waveform when OCS5.CMOD[1:0] = "01B" and OCS7.CMOD[1:0] = "10B" Counter value FFFFH BFFFH 7FFFH 3FFFH 0000H Time Reset OCCP0 value BFFFH OCCP1 value 7FFFH OCCP2 value 3FFFH OCCP3 value 5FFFH OUT0 OUT1 OUT2 OUT3 Note: In this figure, the initial value is "0" for all pins. Timer reset is by match with compare register 4. 232 CHAPTER 12 16-BIT I/O TIMER ■ Sample output waveform when CMOD[1:0] = "11B" When CMOD[1:0] = "11B", the output level of the OUT7 pin is reversed by the compare registers 4, 6 or 7. For the pin OUT5, this setting is identical to CMOD[1:0] = "01B" (see also Table 12.4-3) OUT4: The level is only reversed by a match with compare register 4. OUT5: The level is reversed by a match with compare register 4 or with compare register 5. OUT6: The level is reversed by a match with compare register 4 or with compare register 6. OUT7: The level is reversed by a match with compare register 4, compare register 6 or with compare register 7. Figure 12.4-10 Output waveform when OCS5.CMOD[1:0] = "11B" and OCS7.CMOD[1:0] = "11B" Counter value FFFFH BFFFH 7FFFH 3FFFH 0000H Time Reset OCCP4 value BFFFH OCCP5 value 7FFFH OCCP6 value 3FFFH OCCP7 value 5FFFH OUT4 OUT5 OUT6 OUT7 Note: In this figure, the initial value is "0" for all pins. Timer reset is by match with compare register 4. 233 CHAPTER 12 16-BIT I/O TIMER ■ Output compare timing In output compare operation, a compare match signal is generated when the free-running timer value matches the specified compare register value. The output value can be reversed and an interrupt can be issued. The output reverse timing upon a compare match is synchronized with the counter timing. ● Compare operation upon update of compare register When the compare register is updated, comparison with the counter value is not performed. ● Interrupt timing Figure 12.4-11 Interrupt timing φ N Counter value N+1 N Compare register value Compare match Interrupt ● Output pin change timing Figure 12.4-12 Output pin change timing Counter value Compare register value Compare match signal Pin output 234 N N+1 N N N+1 CHAPTER 12 16-BIT I/O TIMER 12.5 Input Capture Input capture detects a rising or falling edge or both edges of an external input signal and stores a 16-bit free-running timer value at that time in a register. In addition, input capture can generate an interrupt upon detection of an edge. One input capture module consists of two input capture data registers and one control register. ■ Input capture Each input capture data register has a corresponding external input pin. ● The valid edge of an external input can be selected from the following three types: Table 12.5-1 Types of external input edges Rising edge Falling edge Both edges ● An interrupt can be generated upon detection of a valid edge of an external input. ■ Input capture block diagram Figure 12.5-1 shows a block diagram of input capture. Figure 12.5-1 Input capture block diagram IN0 Edge detection Capture data register 0 Count value from Free-running Timer EG11 EG10 EG01 EG00 IEI1 IEI0 Bus Capture data register 1 Edge detection ICP1 ICP0 ICE1 IN1 ICE0 Interrupt Interrupt Note: The figure above is also valid for Input Capture Unit 2/3, 4/5 and 6/7 235 CHAPTER 12 16-BIT I/O TIMER 12.5.1 Input Capture Register Details Input capture module has the two data registers listed. These registers store a value from the 16-bit free-running timer when a valid edge of the corresponding external pin input waveform is detected. (The registers must be accessed in word mode. No values can be written to the registers.) • Input capture data register • Input capture control register ■ Input capture data register Figure 12.5-2 Input capture data register (IPCP) Address: IPCP0:007920 H . . . IPCP7:00792E H 15 14 13 12 11 10 R R R R R R 9 R 8 R 7 6 5 4 3 2 1 0 R R R R R R R R IPCP0 IPCP1 : IPCP7 Initial value XXXXXXXXXXXXXXXXB IPCPn lower bits CP00 Input Capt. Data bit 0 CP01 Input Capt. Data bit 1 CP02 Input Capt. Data bit 2 CP03 Input Capt. Data bit 3 CP04 Input Capt. Data bit 4 CP05 Input Capt. Data bit 5 CP06 Input Capt. Data bit 6 CP07 Input Capt. Data bit 7 n = 0,1,2,3,4,5,6,7 IPCPn R : 236 Read only upper bits CP08 Input Capt. Data bit 8 CP09 Input Capt. Data bit 9 CP10 Input Capt. Data bit 10 CP11 Input Capt. Data bit 11 CP12 Input Capt. Data bit 12 CP13 Input Capt. Data bit 13 CP14 Input Capt. Data bit 14 CP15 Input Capt. Data bit 15 n = 0,1,2,3,4,5,6,7 CHAPTER 12 16-BIT I/O TIMER ■ Control status register Figure 12.5-3 Control status register (ICS01,ICS23,ICS45,ICS67) Address: 7 6 5 4 3 2 1 0 ICS01:000050 H ICS23:000052 H ICS45:000054 H R/W R/W R/W R/W R/W R/W R/W R/W ICS67:000056 H ICS01 ICS23 ICS45 ICS67 Initial value 0 0 0 0 0 0 0 0B bit1 bit0 EGn1 EGn0 0 0 No edge detection (stop) 0 1 Rising edge detection 1 0 Falling edge detection 1 1 Both edges detection Edge selection bit (input capture n) bit3 bit2 EGn+11 EGn+10 0 0 No edge detection (stop) 0 1 Rising edge detection 1 0 Falling edge detection 1 1 Both edges detection bit4 ICEn Edge selection bit (input capture n+1) Interrupt Enable Bit (input capture n) 0 Disable Interrupt 1 Enable Interrupt bit5 ICEn+1 Interrupt Enable Bit (input capture n+1) 0 Disable Interrupt 1 Enable Interrupt bit6 ICPn Interrupt request flag bit (input capture n) Read Write 0 No edge detected Clear this bit 1 Edge detected No effect bit7 ICPn+1 R/W : Readable and writable : Initial value Interrupt request flag bit (input capture n+1) Read Write 0 No edge detected Clear this bit 1 Edge detected No effect n = 0, 2, 4, 6 m = 1, 3, 5, 7 237 CHAPTER 12 16-BIT I/O TIMER Table 12.5-2 Input capture control status register bits Bit name Function bit7 ICPn+1: Interrupt request flag bit (Input capture n+1) • This bit is used as interrupt request flag for input capture n. • "1" is set to this bit upon detection of a valid edge of an external input pin. • While the interrupt enable bit (ICEn+1) is set, an interrupt can be generated upon detection of a valid edge. • Writing "0" will clear this bit. • Writing "1" has no effect. • In read-modify-write operation, "1" is always read. bit6 ICPn: Interrupt request flag bit (Input capture n) • This bit is used as interrupt request flag for input capture n. • "1" is set to this bit upon detection of a valid edge of an external input pin. • While the interrupt enable bit (ICEn) is set, an interrupt can be generated upon detection of a valid edge. • Writing "0" will clear this bit. • Writing "1" has no effect. • In read-modify-write operation, "1" is always read. bit5 ICEn+1: Interrupt request enable bit (Input capture n+1) • This bit is used to enable input capture interrupt request for input capture n+1. • While “1” is written to this bit, an input capture interrupt is generated when the interrupt flag (ICPn+1) is set. bit4 ICEn: Interrupt request enable bit (Input capture n) • This bit is used to enable input capture interrupt request for input capture n. • While “1” is written to this bit, an input capture interrupt is generated when the interrupt flag (ICPn) is set. bit3/2 EG[n+1]1, EG[n+1]0 • These bits are used to specify the valid edge polarity of an external input for input capture n+1 • These bits are also used to enable input capture operation bit1/0 EGn1, EGn0 • These bits are used to specify the valid edge polarity of an external input for input capture n • These bits are also used to enable input capture operation n = 0, 2, 4, 6 238 CHAPTER 12 16-BIT I/O TIMER ■ Input capture edge register (ICE01, ICE23, ICE45, ICE67) Figure 12.5-4 Input capture edge register (ICE01,23,45,67) ICE01 : 000051 H 15 - 14 - 13 - 12 ICUS1 11 - 10 ICUS0 9 IEI1 8 IEI0 ICE23 : 000053 H 15 - 14 - 13 - R/W 12 - 11 - R/W 10 - R 9 IEI3 R 8 IEI2 - - - - - - R 15 - 14 - 13 - 12 - 11 - 10 - 15 - 14 - 13 - - - Address ICE45 : 000055 H ICE67 : 000057 H R/W : Readable and writable X : Undefined 12 11 10 ICUS7 ICUS61 ICUS60 R/W R/W R/W Initial value XXX0X0XX B XXXXXXXX B R 9 IEI5 8 IEI4 XXXXXXXX R 9 IEI7 R 8 IEI6 XXX000XXB R R B Table 12.5-3 Input capture edge register bits (upper and lower) Bit name Function bit15 to 13 Undefined bit12 for ICE01: ICUS1 for ICE67: ICUS7 This bit defines the input signal for Input Capture1 or 7, and is used by UART1 or 3 for LIN operation: • Writing “0”: The Input Capture source is external. • This bit should not be set to "1". bit11,10 for ICE67: ICUS61, ICUS60 This bit defines the input signal for Input Capture6: •I CUS61 / 60 = “00B”: Pin IN6 input signal used as ICU6 input signal. •I CUS61 / 60 = “01B”: ICU6 connected to UART2. •I CUS61 / 60 = “10B” or “11B”: ICU6 connected to UART4. bit10 for ICE01: ICUS0 This bit defines the input signal for Input Capture0: •I CUS0 = “0B”: Pin IN0 input signal used as ICU0 input signal. •I CUS0 = “1B”: ICU0 connected to UART0. bit9 IEIm: Valid edge indication bit • This bit is a valid edge indication bit for capture register IPCP1, IPCP3, IPCP5 and IPCP7 to indicate that a rising or falling edge is detected • "0": falling edge detected. • "1": rising edge detected. • This bit is read only. Note: The read value is meaningless, if EG [n+1] 1, EG [n+1] 0 = “00”. bit8 IEIn: Valid edge indication bit • This bit is a valid edge indication bit for capture register IPCP0, IPCP2, IPCP4 and IPCP6 to indicate that a rising of falling edge is detected • "0": falling edge detected. • "1": rising edge detected. • This bit is read only. Note: The read value is meaningless, if EGn1, EGn0 = “00”. n = 0, 2, 4, 6 m = 1, 3, 5, 7 239 CHAPTER 12 16-BIT I/O TIMER Figure 12.5-5 shows input signal connection of Input Captures. Figure 12.5-5 Block diagram of Input Capture connection ICUS0 IN0 UART0 Input capture 0 IN1 UART1 Input capture 1 ICUS1 IN2 Input capture 2 IN3 Input capture 3 IN4 Input capture 4 IN5 Input capture 5 ICUS60 ICUS61 IN6 UART2 Input capture 6 UART4 IN7 UART3 Input capture 7 ICUS7 240 CHAPTER 12 16-BIT I/O TIMER 12.5.2 16-bit Input Capture Operation In 16-bit input capture operation, an interrupt can be generated upon detection of at the specified edge, fetching the 16-bit free-run timer value and writing it to the capture data register. ■ Sample of input capture fetch timing • Capture 0: Rising edge • Capture 1: Falling edge • Capture example: Both edges Figure 12.5-6 Sample of input capture fetch timing Counter value FFFF H BFFF H 7FFF H 3FFF H 0000 H Time Reset IN0 IN1 IN example Capture 0 Capture 1 Capture example Undefined 3FFFH Undefined Undefined 7FFFH BFFFH 3FFFH Capture 0 interrupt Capture 1 interrupt Capture interrupt 241 CHAPTER 12 16-BIT I/O TIMER ■ Input capture input timing ● Capture timing for input signals Figure 12.5-7 Capture timing for input signals φ Counter value Input capture input N N+1 Valid edge Capture signal Capture register Interrupt 242 N+1 CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) This chapter explains the functions and operations of the 16-bit reload timer (with the event count function). 13.1 Outline of 16-Bit Reload Timer (with Event Count Function) 13.2 16-Bit Reload Timer (with Event Count Function) 13.3 Internal Clock and External Clock Operations of 16-bit Reload Timer 13.4 Underflow Operation of 16-bit Reload Timer 13.5 Output Pin Functions of 16-bit Reload Timer 13.6 Counter Operation State 243 CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) 13.1 Outline of 16-Bit Reload Timer (with Event Count Function) The 16-bit reload timer consists of a 16-bit down-counter, a 16-bit reload register, one input pin (TIN) and one output pin (TOT), and a control register. The input clock can be selected from one external clock and three types of internal clock. ■ Outline of 16-bit reload timer (with event count function) The output pin (TOT) outputs a toggle output waveform in reload mode and outputs a square waveform indicating counting in one-shot mode. The input pin (TIN) is used for event input in event count mode, and can be used for trigger input or gate input in internal clock mode. The MB90350 Series has four 16-bit reload timers. ■ Intelligent I/O service (EI2OS) function, DMA and interrupts The timer includes a circuit that supports EI2OS. The timer can activate EI2OS when an underflow occurs. EI2OS can be used with all four reload timers on this product. However, as two timers (ch0 and ch1, ch2 and ch3) are connected to the same interrupt control register (ICRx) in the interrupt controller, ch0 and ch1, ch2 and ch3 cannot be assigned to different EI2OS services. Also, as the four timers have different interrupt vectors, they can be assigned to four different interrupt services. However, as ch0 and ch1, ch2 and ch3 share an interrupt control register as described above, the same interrupt level applies to both pair of channels. 244 CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) ■ Block diagram of 16-bit reload timer Figure 13.1-1 shows a block diagram of the 16-bit reload timer. Figure 13.1-1 Block diagram of 16-bit reload timer 16 F2 M C - 16 L X B U S 16-bit reload register 8 Reload RELD UF 16-bit down-counter OUTE 16 OUTL 2 OUT CTL. GATE INTE IRQ UF CSL1 Clock selector CNTE CSL0 Clear I 2OSCLR TRG Re-trigger 2 EXCK f 2 f 1 2 3 f 3 Port (TIN) IN CTL 5 2 Prescaler clear Output enable Port (TOT) MOD2 MOD1 Peripheral clock A/DC (ch1) MOD0 3 245 CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) 13.2 16-Bit Reload Timer (with Event Count Function) The 16-bit reload timer has the following two types of registers: • Timer control register (TMCSR) • 16-bit timer register (TMR)/16-bit reload register (TMRLR) ■ 16-bit reload timer register Figure 13.2-1 16-bit reload timer register Address: TMCSR0:000061 H TMCSR1:000063 H TMCSR2:000065 H TMCSR3:000067 H 15 14 13 12 - - - - CSL1 CSL0 MOD2 MOD1 - - - - R/W R/W R/W R/W Address: TMCSR0:000060 H TMCSR1:000062 H TMCSR2:000064 H TMCSR3:000066 H 7 6 5 4 11 3 MOD0 OUTE OUTL RELD I NTE 10 2 UF 246 R/W : Readable and writable X : Undefined value - : Undefined 1 8 0 CNTE TRG TMCSR0/1/2/3 (upper) Initial value XXXX0000 B TMCSR0/1/2/3 (lower) Initial value 0 0 0 0 0 0 0 0B R/W R/W R/W R/W R/W R/W R/W R/W Address: 15 14 13 12 11 10 TMR0/TMRLR0:007949 H TMR1/TMRLR1:00794B H TMR2/TMRLR2:00794D H TMR3/TMRLR3:00794F H R/W R/W R/W R/W R/W R/W Address: TMR0/TMRLR0:007948 H TMR1/TMRLR1:00794A H TMR2/TMRLR2:00794C H TMR3/TMRLR3:00794E H 9 7 6 5 4 3 2 9 8 TMR/TMRLR0/1/2/3 (upper) Initial value XXXXXXXX B R/W R/W 1 0 TMR/TMRLR0/1/2/3 (lower) Initial value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) 13.2.1 Timer Control Status Register (TMCSR) Controls the operation mode and interrupts for the 16-bit timer. ■ Register layout of timer control register (TMCSR) Figure 13.2-2 Register layout of timer control register (TMCSR) Address: TMCSR0:000061H TMCSR1:000063H TMCSR2:000065H TMCSR3:000067H 15 14 13 12 - - - - CSL1 CSL0 MOD2 MOD1 - - - - R/W R/W R/W R/W Address: TMCSR0:000060H TMCSR1:000062H TMCSR2:000064H TMCSR3:000066H 7 6 5 4 R/W : Readable and writable X : Undefined value - : Undefined 11 3 MOD0 OUTE OUTL RELD I NTE 10 2 UF 9 8 1 0 CNTE TRG TMCSR0/1/2/3 (upper) Initial value XXXX0000 B TMCSR0/1/2/3 (lower) Initial value 0 0 0 0 0 0 0 0B R/W R/W R/W R/W R/W R/W R/W R/W ■ Register contents of timer control register (TMCSR) [Bits 11, 10] CSL1, CSL0 (Clock select 1, 0) The count clock select bits. Table 13.2-1 lists the selected clock sources. Table 13.2-1 Clock sources for CSL bit settings CSL1 CSL0 Clock Source (Machine cycle φ = 24 MHz) 0 0 φ/21 (0.083 µs) 0 1 φ/23 (0.33 µs) 1 0 φ/25 (1.3 µs) 1 1 External event count mode 247 CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) [Bits 9, 8, 7] MOD2, MOD1, MOD0 These bits set the operation mode and I/O pin functions. The MOD2 bit selects the I/O functions. When MOD2 = "0", the input pin functions as a trigger input. In this case, the reload register contents is loaded to the counter when an active edge is input to the input pin and count operation proceeds. When MOD2 = "1", the timer operates in gate counter mode and the input pin functions as a gate input. In this mode, the counter only counts while an active level is input to the input pin. The MOD1 and 0 bits set the pin functions for each mode. Table 13.2-2 and Table 13.2-3 list the MOD2, 1, 0 bit settings. Table 13.2-2 MOD2, 1, 0 bit settings (1) MOD2 MOD1 MOD0 Input Pin Function Active Edge or Level 0 0 0 Trigger disabled - 0 0 1 Trigger input Rising edge 0 1 0 Falling edge 0 1 1 Both edges 1 x 0 1 x 1 Gate input "L" level "H" level Internal clock mode (CSL0, 1 = “00B”, “01B”, or “10B”) Table 13.2-3 MOD2, 1, 0 bit settings (2) MOD2 x 248 MOD1 MOD0 Input Pin Function Active Edge or Level 0 0 - - 0 1 Trigger input Rising edge 1 0 Falling edge 1 1 Both edges • Event counter mode (CSL0,1 = “11B”) • Bits marked as x in the table can be set to any value. CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) [Bit 6] OUTE Output enable bit. Setting of this bit is enable only for reload timer 1 and 3. The TOT pin functions as a general-purpose port when this bit is "0" and as the timer output pin when this bit is "1". In reload mode, the output waveform toggles. In one-shot mode, TOT outputs a square waveform that indicates that counting is in progress. [Bit 5] OUTL This bit sets the output level for the TOT pin. Setting of this bit is enable only for reload timer 1 and 3. Table 13.2-4 OUTE, RELD, and OUTL settings OUTE RELD OUTL Output Waveform 0 x x General-purpose port 1 0 0 Output an "H" level pulse during counting. 1 0 1 Output an "L" level pulse during counting. 1 1 0 Toggle output. Starts with "L" level output. 1 1 1 Toggle output. Starts with "H" level output. [Bit 4] RELD (Reload) This bit enables reload operations. When RELD is "1", the timer operates in reload mode. In this mode, the timer loads the reload register contents into the counter and continues counting whenever an underflow occurs (when the counter value changes from 0000H to FFFFH). When RELD is "0", the timer operates in one-shot mode. In this mode, the count operation stops when an underflow occurs due to the counter value changing from 0000H to FFFFH. [Bit 3] INTE (Interrupt enable) Timer interrupt request enable bit. When INTE is "1", an interrupt request is generated when the UF bit changes to "1". When INTE is "0", no interrupt request is generated, even when the UF bit changes to "1". [Bit 2] UF (Underflow) Timer interrupt request flag. UF is set to "1" when an underflow occurs (when the counter value changes from 0000H to FFFFH). Cleared by writing "0" or by the intelligent I/O service. Writing "1" to this bit has no meaning. Read as "1" by read-modify-write instructions. [Bit 1] CNTE (Count enable) Timer count enable bit. Writing "1" to CNTE sets the timer to wait for a trigger. Writing "0" stops count operation. [Bit 0] TRG (Trigger) Software trigger bit. Writing "1" to TRG applies a software trigger, causing the timer to load the reload register contents to the counter and start counting. Writing "0" has no meaning. Reading always returns "0". Applying a trigger using this register is only valid when CNTE = "1". Writing "1" has no effect if CNTE = "0". 249 CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) 13.2.2 Register Layout of 16-bit Timer Register (TMR)/16-bit Reload Register (TMRLR) • TMR contents (for reading) Reading this register reads the count value of the 16-bit timer. The initial value is undefined. Always read this register using the word access instructions. • TMRLR contents (for writing) The 16-bit reload register holds the reload value. The initial value is undefined. Always write to this register using the word access instructions. ■ Register layout of 16-bit timer register (TMR)/16-bit reload register (TMRLR) Figure 13.2-3 Register layout of 16-bit timer register (TMR)/16-bit reload register (TMRLR) Address: 15 14 13 12 11 10 TMR0/TMRLR0:007949 H TMR1/TMRLR1:00794BH TMR2/TMRLR2:00794DH TMR3/TMRLR3:00794F H R/W R/W R/W R/W R/W R/W Address: TMR0/TMRLR0:007948 H TMR1/TMRLR1:00794A H TMR2/TMRLR2:00794CH TMR3/TMRLR3:00794E H 250 R/W : Readable and writable X : Undefined value 7 6 5 4 3 2 9 8 TMR/TMRLR0/1/2/3 (upper) Initial value XXXXXXXX B R/W R/W 1 0 TMR/TMRLR0/1/2/3 (lower) Initial value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) 13.3 Internal Clock and External Clock Operations of 16-bit Reload Timer The machine clock divided by 21, 23, or 25 can be selected as the clock sources for operating the timer from an internal divide clock. The external input pin can be selected as either a trigger input or gate input by a register setting. If an external clock is selected, the TIN pin functions as an external event input pin to count the number of valid edges set in the register. ■ Internal clock operation of 16-bit reload timer Writing "1" to both the CNTE and TRG bits in the control register enables and starts counting at one time. Using the TRG bit as a trigger input is always available when the timer is enabled (CNTE = "1"), regardless of the operation mode. Figure 13.3-1 shows counter activation and counter operation. A time period T (T: machine cycle) is required from the counter start trigger being input until the reload register data is loaded into counter. Figure 13.3-1 Activation and operation of 16-bit reload timer counter Count clock Counter Reload data -1 -1 -1 Data load CNTE (bit) TRG (bit) T 251 CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) ■ Input pin functions of 16-bit reload timer (in internal clock mode) The TIN pin can be used as either a trigger input or a gate input when an internal clock is selected as the clock source. When used as a trigger input, input of an active edge causes the timer to load the reload register contents to the counter and then start count operation after clearing the internal prescaler. Input a pulse width of at least 2T (T is the machine cycle) to TIN. Figure 13.3-2 shows the operation of trigger input. Figure 13.3-2 Trigger input operation of 16-bit reload timer Count clock Rising edge detected TIN Prescaler clear Counter Reload data 0000H -1 -1 -1 Load 2T2.5T When used as a gate input, the counter only counts while the active level specified by the MOD0 bit of the control register is input to the TIN pin. In this case, the count clock continues to operate unless stopped. The software trigger can be used in gate mode, regardless of the gate level. Input a pulse width of at least 2T (T is the machine cycle) to the TIN pin. Figure 13.3-3 shows the operation of gate input. Figure 13.3-3 Gate input operation of 16-bit reload timer Count clock TIN Counter When MOD0 = "1" (Count when "H" is input) -1 -1 -1 ■ External event counter The TIN pin functions as an external event input pin when an external clock is selected. The counter counts on the active edge specified in the register. Input a pulse width of at least 4T (T is the machine cycle) to the TIN pin. 252 CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) 13.4 Underflow Operation of 16-bit Reload Timer An underflow is defined for this timer as the time when the counter value changes from 0000H to FFFFH. Therefore, an underflow occurs after (reload register setting + 1) counts. ■ Underflow operation of 16-bit reload timer If the RELD bit in the control register is "1" when the underflow occurs, the contents of the reload register is loaded into the counter and counting continues. When RELD is "0", counting stops with the counter at FFFFH. The UF bit in the control register is set when the underflow occurs. If the INTE bit is "1" at this time, an interrupt request is generated. Figure 13.4-1 shows the operation when an underflow occurs. Figure 13.4-1 Underflow operation of 16-bit reload timer Count clock Counter 0000H Reload data -1 -1 -1 Data load Underflow set [RELD=1] Count clock Counter 0000H FFFFH Underflow set [RELD=0] 253 CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) 13.5 Output Pin Functions of 16-bit Reload Timer In reload mode, the TOT pin performs toggle output (inverts at each underflow). In oneshot mode, the TOT pin functions as a pulse output that shows a particular level while the count is in progress. ■ Output pin functions of 16-bit reload timer The OUTL bit of the control register sets the output polarity. When OUTL = "0", the initial value for toggle output is "0" and the one-shot pulse output is "1" while the count is in progress. The output waveforms are opposite when OUTL = "1". Figure 13.5-1 and Figure 13.5-2 show the output pin functions. Figure 13.5-1 Output pin function of 16-bit reload timer (1) Count start Underflow Level is opposite when OUTL = "1" TOT General-purpose port CNTE Trigger [RELD=1, OUTL=0] Figure 13.5-2 Output pin function of 16-bit reload timer (2) Underflow TOT Level is opposite when OUTL = "1" General-purpose port CNTE Trigger Waiting for a trigger [RELD=0, OUTL=0] 254 CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) 13.6 Counter Operation State The counter state is determined by the CNTE bit in the control register and the internal WAIT signal. Available states are: CNTE = "0" and WAIT = "1" (STOP state), CNTE = "1" and WAIT = "1" (WAIT state for trigger), and CNTE = "1" and WAIT = "0" (RUN state). ■ Counter operation state Figure 13.6-1 shows the transitions between each state. Figure 13.6-1 Counter state transitions Reset State transitions by hardware STOP CNTE=0, WAIT=1 State transitions by register access TIN pin: Input disabled TOT pin: General-purpose port Counter: Retains the value while counting stopped. Value undefined after reset. CNTE=0 CNTE=0 CNTE=1 TRG=1 CNTE=1 TRG=0 WAIT CNTE=1, WAIT=1 RUN TIN pin: Only trigger input enabled CNTE=1, WAIT=0 TIN pin: Functions as TIN pin TOT pin: Initial value output TOT pin: Functions as TOT pin RELD * UF Counter: Retains the value while counting stopped. Value undefined after reset until load. Counter: Running TRG=1 LOAD TRG=1 CNTE=1, WAIT=0 Load contents of the reload register to the counter. RELD UF Load complete 255 CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) 256 CHAPTER 14 WATCH TIMER This chapter explains the functions and operations of the watch timer. 14.1 Outline of Watch Timer 14.2 Watch Timer Control Register (WTC) 14.3 Watch Timer Operation 257 CHAPTER 14 WATCH TIMER 14.1 Outline of Watch Timer The watch timer consists of a 15-bit timer and a circuit that controls an interval interrupt. The watch timer uses subclock signals regardless of the MCS bit and SCS bit of the clock selection register (CKSCR). ■ Watch Timer Register Figure 14.1-1 Watch Timer Control Register (WTC) Watch timer control register 7 6 5 4 3 2 1 WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0 Read/write (R/W) (R) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (1) (X) Address: 0000AAH (0) (0) (1) (0) (0) Bit No. 0 WTC (0) ■ Block Diagram of Watch Timer Figure 14.1-2 Block Diagram of Watch Timer To watchdog timer Watch timer counter SCLK × 21 × 22 × 23 × 24 × 25 × 26 × 27 × 28 OF × 29 × 210 × 211 × 212 × 213 × 214 × 215 OF OF OF OF OF Power-on reset Transition to hardware standby Transition to stop mode Counter clear circuit OF OF To subclock oscillation stabilization wait time Interval timer selector Watch timer interrupt OF : Overflow HCLK : Subclock 258 WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0 Watch timer control register(WTC) CHAPTER 14 WATCH TIMER 14.2 Watch Timer Control Register (WTC) The watch timer control register (WTC) controls the operation of the watch timer and the interval interrupt time. ■ Watch Timer Control Register (WTC) Figure 14.2-1 Watch Timer Control Register (WTC) Watch timer control register 7 6 5 4 3 2 1 0 WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0 Read/write (R/W) (R) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (1) (X) Address: 0000AAH (0) (0) (1) (0) (0) Bit No. WTC (0) [Bit 7] WDCS The WDCS bit is used to specify whether the clock signals from the watch timer or timebase timer is used as the input clock of the watchdog timer when the main clock or PLL clock is selected as the machine clock. When WDCS=0, the clock signal from the watch timer is selected. When WDCS=1, the clock signal from the timebase timer is selected. Write "0" to this bit when switching to the subclock mode. This bit is initialized to 1 by reset. Note: If WDCS is set to 1, the watchdog timer counter may be incremented because the timebase timer output and watch timer output are asynchronous. If WDCS is set to 1, the watchdog timer must be cleared before and after the WDCS bit is changed. [Bit 6] SCE The SCE bit indicates that the subclock oscillation stabilization wait time has elapsed. When this bit is 0, the oscillation stabilization is currently in progress. The oscillation stabilization time is fixed at 214 cycles (subclock). This bit is initialized to 0 by a power-on reset and stop. [Bit 5] WTIE The WTIE bit enables an interval interrupt by the watch timer. When this bit is 1, the interrupt is enabled. When this bit is 0, the interrupt is disabled. This bit is initialized to 0 by a reset. This bit can be read and written to. [Bit 4] WTOF The WTOF bit is the watch timer interrupt flag. When the WTIE bit is 1 and WTOF is set to 1, an interrupt request is issued. This bit is set to 1 at each interval specified by the WTC1 and WTC0 bits. This bit is cleared by writing 0, transition to stop mode or a reset. Writing 1 has no effect. During read operation using a read-modify-write instruction, 1 is always read from this bit. 259 CHAPTER 14 WATCH TIMER [Bit 3] WTR The WTR bit clears all bits of the watch timer counter to 0. Writing 0 to this bit clears the timer counter. Writing 1 has no effect. The value read from this bit is always 1. [Bits 2, 1, and 0] WTC2, WTC1, WTC0 The WTC2, WTC1, and WTC0 bits set the watch timer interval. Table 14.2-1 lists the settings for the interval. These bits are initialized to 000 by a reset. These bits can be read and written to. When data is written to these bits, bit 4 (WTOF) should be cleared at the same time. Table 14.2-1 Settings for the Watch Timer Interval WTC2 WTC1 WTC0 Interval (when SCLK*=8.192kHz) 0 0 0 28 / SCLK (31.25 ms) 0 0 1 29 / SCLK (62.5 ms) 0 1 0 210 / SCLK (125 ms) 0 1 1 211 / SCLK (250 ms) 1 0 0 212 / SCLK (500 ms) 1 0 1 213 / SCLK (1.000 s) 1 1 0 214 / SCLK (2.000 s) 1 1 1 215 / SCLK (4.000 s) *: SCLK is Sub Clock, whose frequency is the oscillation clock frequency divided by 2 or 4. The subclock division ratio is determined by SCDS bit of PLL/Subclock Control Register (PSCCR). 260 CHAPTER 14 WATCH TIMER 14.3 Watch Timer Operation The watch timer functions as a watchdog counter clock source, timer for waiting for the subclock oscillation to stabilize, and interval timer for generating interrupts at specified intervals. ■ Watch Timer The watch timer consists of a 15-bit counter that counts clock pulses originated from the subclock. As long as the subclock is input, the watch timer keeps counting. The watch timer is cleared by a power-on reset transition to stop mode or writing 0 to the WTR bit of the watch timer control register (WTC). Notes: • Clearing the clock counter affects the watchdog counter and interval interrupts that use watch timer output. • To clear the watch timer by writing “0” to the WTR bit in the watch timer control register (WTC), set the WTIE bit to “0” and set the watch timer to interrupt inhibited state. Before permitting an interrupt, clear the interrupt request issued by writing “0” to the WTOF flag. ■ Interval Interrupt Function of Watch Timer The interval interrupt function generates interrupts at specified intervals according to the carry signals of the timer counter. The WTOF flag is set at the intervals specified by the WTC1 and WTC0 bits of the watch timer control register (WTC). This flag is set with reference to the last time when the watch timer was cleared. On transition to stop, the watch timer is used as a timer for subclock oscillation to stabilize upon recovery, and the WTOF flag is immediately cleared upon mode transition. ■ Setting Operation Clock of Watchdog timer The watchdog clock select bit (WDCS) in the watch timer control register (WTC) can be used to set the clock input source of the watchdog timer. When using the subclock as the machine clock, always set the WDCS bit to "0" and select the output of the watch timer. 261 CHAPTER 14 WATCH TIMER 262 CHAPTER 15 8/16-BIT PPG This chapter explains the 8/16-bit PPG and explains its functions. 15.1 Outline of 8/16-bit PPG 15.2 Block Diagram of 8/16-bit PPG 15.3 8/16-bit PPG Registers 15.4 Operations of 8/16-bit PPG 15.5 Selecting a Count Clock for 8/16-bit PPG 15.6 Controlling Pin Output of 8/16-bit PPG Pulses 15.7 8/16-bit PPG Interrupts 15.8 Initial Values of 8/16-bit PPG Hardware 263 CHAPTER 15 8/16-BIT PPG 15.1 Outline of 8/16-bit PPG The 8/16-bit Programmable Pulse Generator (PPG) consists of two eight-bit down counters, four eight-bit reload registers, one 16-bit control register, two external pulse output signals, and two interrupt outputs. The following functions are implemented: ■ Function of 8/16-bit PPG ● 8-bit PPG output, 2-channel independent operation mode: Two independent channels of PPG output operation are implemented. ● 16-bit PPG output operation mode: One channel of 16-bit PPG output operation is implemented. ● 8+8-bit PPG output operation mode: 8-bit PPG output operation is implemented at specifies intervals, using channel 0 output as channel 1 clock input. ● PPG output operation: Pulse waves are output at specified intervals and duty ratio. With an external circuit, this module can be used as a D/A converter. The MB90350 Series contains eight PPG’s. The following sections only describe the functionality of the PPG 0/1. The remaining PPG’s have the identical function and the register addresses should be found in the I/O map. Figure 15.1-1 shows the connection of internal PPG modules and external pins. 264 CHAPTER 15 8/16-BIT PPG Figure 15.1-1 Relationship between PPG modules and external pins PPG0 / PPG1 PPG2 / PPG3 Internal Modules PPG4 / PPG5 PPG6 / PPG7 PPG8 / PPG9 PPGA / PPGB PPGC / PPGD PPGE / PPGF PPG0 PPG1 PPG2 PPG3 PPG4 PPG5 PPG6 PPG7 PPG8 PPG9 External Pins PPGA PPGB PPGC PPGD PPGE PPGF 265 CHAPTER 15 8/16-BIT PPG 15.2 Block Diagram of 8/16-bit PPG Figure 15.2-1 shows a block diagram of the 8/16-bit PPG (ch0). Figure 15.2-2 shows a block diagram of the 8/16-bit PPG (ch1). ■ Block diagram of 8/16-bit PPG Figure 15.2-1 8-bit PPG ch0 block diagram PPG0 output enable PPG0 Peripheral clock 16-division Peripheral clock 8-division Peripheral clock 4-division Peripheral clock 2-division Peripheral clock PPG0 Output latch Invert Clear PEN0 In MB90340 series, this IRQ signal merged with the Channel1 IRQ signal by OR logic. Count clock selection Timebase counter output, 512-division of main clock L/H selection S R Q PCNT (down counter) IRQ Reload ch1-borrow L/H selector PRLBH0 PRLBH0 Temporary buffer PIE0 PRLH0 PUF0 L data bus H data bus PPGC0 (Operation mode control) 266 CHAPTER 15 8/16-BIT PPG Figure 15.2-2 8-bit PPG ch1 block diagram PPG1 output enable PPG1 Peripheral clock 16-division Peripheral clock 8-division Peripheral clock 4-division Peripheral clock 2-division Peripheral clock PPG1 Output latch Invert Count clock selection Clear PEN1 In MB90340 series, this IRQ signal merged with the Channel1 IRQ signal by OR logic. PCNT (down counter) ch0-borrow Timebase counter output, 512-division of main clock L/H selection S R Q IRQ Reload L/H selector PRLBL1 PRLBH1 Temporary buffer PIE1 PRLH1 PUF1 L data bus H data bus PPGC1 (Operation mode control) 267 CHAPTER 15 8/16-BIT PPG 15.3 8/16-bit PPG Registers The 8/16-bit PPG has the following five types of registers: • PPGC0 (2, 4, 6, 8, A, C, E) Operation Mode Control Register • PPGC1 (3, 5, 7, 9, B, D, F) Operation Mode Control Register • PPG01 (23, 45, 67, 89, AB CD, EF) Clock Select Register • Reload register H • Reload register L ■ 8/16-bit PPG registers Figure 15.3-1 8/16-bit PPG register PPGn Operation Mode Control Register ch0 000030H Address: ch2 000034H ch4 000038H ch6 00003CH ch8 000040H chA 000044H chC 000048H chE 00004CH PPGm Operation Mode Control Register ch1 000031H Address: ch3 000035H ch5 000039H ch7 00003DH ch9 000041H chB 000045H chD 000049H chF 00004DH PPGnm Clock Select Register Address: ch01 000032H ch23 000036H ch45 00003AH ch67 00003EH ch89 000042H chAB 000046H chCD 00004AH chEF 00004EH Reload register H Address: Reload register L Address: 268 ch0 079010H ch1 079030H ch2 007905H ch3 007907H ch4 007909H ch5 00790BH ch6 00790DH ch7 00790FH ch8 007911H ch9 007913H chA 007915H chB 007917H chC 007919H chD 00791BH chE 00791DH chF 00791FH ch0 007900H ch1 079020H ch2 007904H ch3 007906H ch4 007908H ch5 00790AH ch6 00790CH ch7 00790EH ch8 007910H ch9 007912H chA 007914H chB 007916H chC 007918H chD 00791AH chE 00791CH chF 00791EH 7 6 5 PEN0 4 3 2 PE0 PIE0 PUF0 (R/W) (0) (R/W) (0) (R/W) (0) 1 0 Reserved PPGCn (R/W) (0) 15 (-) (X) 14 PEN1 13 PE 12 PIE1 (-) (X) (-) (X) 11 10 9 PUF1 MD1 MD0 (W) (1) 8 Reserved PPGCm (R/W) (0) 7 (-) (X) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) 6 5 4 3 2 1 (W) (1) 0 PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 REV PPGnm (R/W) (0) 15 (R/W) (0) 14 (R/W) (0) 13 (R/W) (0) (R/W) (0) (R/W) (0) 12 11 10 (-) (X) 9 (R/W) (0) 8 PRLHn PRLHm (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) 7 6 5 4 (R/W) (X) 3 (R/W) (X) (R/W) (X) (R/W) (X) 2 1 0 PRLLn PRLLm (R/W) (X) (R/W) (R/W) (X) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) n = 0, 2, 4, 6, 8, A, C, E m = 1, 3, 5, 7, 9, B, D, F CHAPTER 15 8/16-BIT PPG 15.3.1 PPG8 Operation Mode Control Register (PPGC8) PPGC8 is a five-bit control register that selects the operation mode of the block, controls pin outputs, selects count clock, and controls triggers. ■ PPG0 operation mode control register (PPGC8) Figure 15.3-2 Configuration of the PPG8 operation mode control register PPG8 operation mode control register Address: ch0 ; 000030H Read/write Initial value 6 5 4 3 2 1 0 PEN0 - PE0 PIE0 PUF0 - - Reserved (R/W) (0) (-) (x) (R/W) (0) (R/W) (0) (R/W) (0) (-) (0) (-) (x) (R/W) (0) Other ch.: ch4 ; 000038H ch6 ; 00003CH chA ; 000044H chC ; 000048H chE ; 00004CH PPGC 8 bit 0 Reserved 1 bit 3 PUF0 : : : : Readable and writable Undefined value Undefined Initial value When setting PPGC8, always set this bit to 1. Reading Writing 0 PPG counter underflow is not detected. PPG0 bit is cleared. 1 PPG counter underflow is detected. noeffect. bit 4 PIE0 R/W X - PPG underflow flag Bit No. 7 PPG interrupt enaable 0 1 bit 5 PIE0 Interrupt disabled. 0 1 bit 7 PEN0 Pulse output disabled (general-purpose port). Pulse output enaabled (PPG8 output). 0 1 Interrupt enaabled. PPG output enable PPG8 enable Stop ("L" level output maintained). PPG operation enaabled. 269 CHAPTER 15 8/16-BIT PPG Table 15.3-1 Bit function description of the PPG8 operation mode control register Bit name Function bit 7 PEN0: Operation enable bit When set to "1", this bit enables the counter operation of the PPG. When operation is disabled but output is enabled (bit 5), a low level is maintained at the output. bit 5 PE0: PPG8 pin output enable bit When set to “1”, this bit enables the pulse output. For MB90350 Series, the pulse signal is output to the “PPG8” external pin. When disabled, the pin can be used as general-purpose port. bit 4 PIE0: PPG interrupt enable bit While this bit is "1", an interrupt request is issued as soon as PUF0 is set to "1". No interrupt request is issued while this bit is set to "0". bit 3 PUF0: PPG counter underflow bit In 8-bit PPG 2-channel mode or 8-bit prescaler + 8-bit PPG mode, this bit is set to "1" when an underflow occurs as a result of the ch0 counter value becoming from 00H to FFH. In 16-bit PPG mode, this bit is set to "1" when an underflow occurs as a result of the Channel 0 and 1 counter value becoming from 0000H to FFFFH. To set this bit to "0", write "0". Writing "1" to this bit has not effect. Upon a read operation during a readmodify-write instruction, "1" is read. bit 0 Reserved bit. This is a reserved bit. When setting PPGC8, always set this bit to 1. 270 CHAPTER 15 8/16-BIT PPG 15.3.2 PPG9 Operation Mode Control Register (PPGC9) PPGC9 is a seven-bit control register that selects the operation mode of the block, controls pin outputs, selects count clock, and controls triggers. ■ PPG1 operation mode control register (PPGC9) Figure 15.3-3 Configuration of the PPG9 operation mode control register PPG9 operation mode control register 15 Address: ch9 ; 000041H PEN1 Read/write Initial value (R/W) (0) 14 13 12 11 10 9 - PE1 PIE1 PUF1 MD1 MD0 (-) (x) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) Other ch.: ch5 ; 000039H ch7 ; 00003DH chB ; 000045H chD ; 000049H chF ; 00004DH 8 Bit No. Reserved PPGC 9 (R/W) (0) bit 8 Reserved 1 bit 10 MD1 bit 9 MD0 0 0 1 1 0 1 0 1 bit 11 PUF1 0 1 bit 12 PIE1 0 1 bit 13 PE1 0 1 bit 15 PEN0 R/W X - : : : : Readable and writable Undefined value Undefined Initial value When setting PPGC9, always set this bit to 1. 0 1 PPG count mode 8-bit PPG 2ch independent mode 8-bit prescaler + 8-bit PPG 1ch mode Reserved 16-bit PPG 1ch mode PPG underflow flag PPG counter underflow flag is not detected. PPG counter underflow flag is detected. PPG interrupt enaable Interrupt disabled. Interrupt enaabled. PPG output enable 1 Pulse output disabled (general-purpose port). Pulse output enaabled. PPG enable Stop ("L" level output maintained). PPG operation enaabled. 271 CHAPTER 15 8/16-BIT PPG Table 15.3-2 Bit function description of the PPG1 operation mode control register Bit name Function bit 15 PEN1: Operation enable bit When set to "1", this bit enables the counter operation of the PPG. When operation is disabled but output is enabled (bit 13), a low level is maintained at the output. bit 13 PE1: PPG1 pin output enable bit When set to “1”, this bit enables the pulse output. For MB90350 Series, the pulse signal is output to the “PPG9” external pin. When disabled, the pin can be used as general-purpose port. bit 12 PIE1: PPG interrupt enable bit While this bit is "1", an interrupt request is issued as soon as PUF1 is set to "1". No interrupt request is issued while this bit is set to "0". bit 11 PUF1: PPG counter underflow bit In 8-bit PPG 2-channel mode or 8-bit prescaler + 8-bit PPG mode, this bit is set to "1" when an underflow occurs as a result of the ch1 counter value becoming from 00H to FFH. In 16-bit PPG mode, this bit is set to "1" when an underflow occurs as a result of the Channel 0 and 1 counter value becoming from 0000H to FFFFH. To set this bit to "0", write "0". Writing "1" to this bit has not effect. Upon a read operation during a read-modify-write instruction, "1" is read. bit 10, 9 MD1, MD0: PPG count mode These bits select the PPG timer operation mode as described in "Figure 15.3-3. Do not set "10" in these bits. To write "01" to these bits, ensure that "01" is not written to the PEN0 bit of PPGC0 or PEN1 bit of PPGC1. Write "11" or "00" in both the PEN0 and PEN1 bits simultaneously. To write "11" to these bits, update PPGC0 and PPGC1 by word transfer and write "11" or "00" to both the PEN0 and PEN1 bits simultaneously. bit 8 Reserved bit. This is a reserved bit. When setting PPGC1, always write "1" to this bit. 272 CHAPTER 15 8/16-BIT PPG 15.3.3 PPG8/9 Clock Select Register (PPG89) The PPG8/9 Clock Select Register (PPG89) is an 8-bit control register that controls the counter clock of the 8/16-bit PPG. ■ PPG8/9 clock select register (PPG89) Figure 15.3-4 Configuration of the PPG0/1 clock select register (PPG89) PPG8/9 Clock Select Registers Address: 7 ch9: 000042 H 6 5 4 3 2 PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 Other ch.: ch45: 00003A H (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) ch67: 00003E H chAB: 000046 H chCD: 00004A H chEF: 00004E H R/W : Readable and writable X : Undefined value - : Undefined : Initial value PPG89 1 0 - REV (-) (R/W) Initial value 000000X0 bit 0 PPG output Ch0/Ch1 swap bit REV 0 Default outputs pin is used 1 Output pins are swapped bit 4 bit 3 bit 2 PCM2 PCM1 PCM0 0 0 0 Peripheral Clock 0 0 1 Peripheral Clock/2 0 1 0 Peripheral Clock/4 0 1 1 Peripheral Clock/8 1 0 0 Peripheral Clock/16 1 1 1 Clock input from timebase timer Count clock selection bit (ch0) bit 7 bit 6 bit 5 PCS2 PCS1 PCS0 0 0 0 Peripheral Clock 0 0 1 Peripheral Clock/2 0 1 0 Peripheral Clock/4 0 1 1 Peripheral Clock/8 1 0 0 Peripheral Clock/16 1 1 1 Clock input from timebase timer Count clock selection bit (ch1) 273 CHAPTER 15 8/16-BIT PPG Table 15.3-3 Bit function description of the clock select register (PPG89) Bit name bits 7 to 5 bits 4 to 2 bit 0 274 PCS2 to PCS0: Count clock selection bit PCM2 to PCM0: Count clock selection bit REV: PPG output ch0/ch1 swap bit Function These bits select the operation clock for the down counter of Channel 1 as described below. Note: In 8-bit prescaler + 8-bit PPG mode or in 16-bit PPG mode, ch1 PPG operates in response to a counter clock from ch0. Therefore, the setting in these bits has no effect. PCS2 PCS1 PCS0 Operation mode 0 0 0 Peripheral Clock (62.5 ns machine clock, 16 MHz) 0 0 1 Peripheral Clock/2 (125 ns machine clock, 16 MHz) 0 1 0 Peripheral Clock/4 (250 ns machine clock, 16 MHz) 0 1 1 Peripheral Clock/8 (500 ns machine clock, 16 MHz) 1 0 0 Peripheral Clock/16 (1 µs machine clock, 16 MHz) 1 0 1 Clock input from the timebase timer (128 µs, 4 MHz source oscillation) These bits select the operation clock for the down counter of Channel 0 as described below. PCM2 PCM1 PCM0 Operation mode 0 0 0 Peripheral Clock (62.5 ns machine clock, 16 MHz) 0 0 1 Peripheral Clock/2 (125 ns machine clock, 16 MHz) 0 1 0 Peripheral Clock/4 (250 ns machine clock, 16 MHz) 0 1 1 Peripheral Clock/8 (500 ns machine clock, 16 MHz) 1 0 0 Peripheral Clock/16 (1 µs machine clock, 16 MHz) 1 0 1 Clock input from the timebase timer (128 µs, 4 MHz source oscillation) Set this bit to "1" , swap PPG channel1 output pin and PPG channel0 output pin. Set this bit to "0"(default value), both PPG channel0 and channel1 signals output from default output pins. CHAPTER 15 8/16-BIT PPG 15.3.4 Reload Register (PRLL/PRLH) The reload registers (PRLL and PRLH) are 8-bit registers that store reload values for the PCNT down counters. The PRLL and PRLH registers are readable and writable. ■ Reload register (PRLL/PRLH) Figure 15.3-5 Reload register (PRLL/PRLH) Reload register H Address: ch8: 007911H ch9: 007913 H ch4: 007909 H ch5: 00790B H ch6: 00790D H ch7: 00790F H chA: 007915 H chB: 007917 H chC: 007919H chD: 00791BH chE: 00791DH chF: 00791F H Reload register L Address: ch8: 007910H ch9: 007912 H ch4: 007908 H ch5: 00790A H ch6: 00790C H ch7: 00790E H chA: 007914 H chB: 007916 H chC: 007918 H chD: 00791A H chE: 00791CH chF: 00791E H 15 14 13 12 11 10 9 8 PRLHn (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) 7 6 5 4 3 (R/W) (R/W) (X) (X) 2 1 (R/W) (X) 0 PRLLn (R/W) (X) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (R/W) (R/W) (X) (X) (R/W) (X) n = 0, 1, ... , E, F Table 15.3-4 Register function of the reload registers Register name Function PRLLn Holds the L side reload value. PRLHn Holds the H side reload value. Note: In 8-bit prescaler + 8-bit PPG mode, different values in PRLL and PRLH of Channel 0 may cause the PPG waveform of ch1 to vary in each cycle. Write the same value to PRLL and PRLH of ch0. 275 CHAPTER 15 8/16-BIT PPG 15.4 Operations of 8/16-bit PPG One 8/16-bit PPG consists of two channels of 8-bit PPG units. These two channels can be used in three modes: independent two-channel mode, 8-bit prescaler + 8-bit PPG mode, and single-channel 16-bit PPG mode. ■ Operations of 8/16-bit PPG Each of the 8-bit PPG units has two eight-bit reload registers. One reload register is for the L pulse width (PRLL) and the other is for the H pulse width (PRLH). The values stored in these registers are reloaded into the 8-bit down counter (PCNT), from the PRLL and PRLH in turn. The pin output value is inverted upon a reload caused by counter borrow. This operation results in the pulses of the specified L pulse width and H pulse width. Table 15.4-1 lists the relationship between the reload operation and pulse outputs. Table 15.4-1 Reload operation and pulse output Reload operation Pin output change PRLH --> PCNT PPG0/1 [0 --> 1] Rise PRLL --> PCNT PPG0/1 [1 --> 0] Fall When 1 is set in bit 4 (PIE0) of PPGC0 or in bit 12 (PIE1) of PPGC1, an interrupt request is output upon a borrow from 00 to FF (from 0000 to FFFF in 16-bit PPG mode) of each counter. ■ Operation modes of 8/16-bit PPG This block can be used in three modes: independent two-channel mode, 8-bit prescaler + 8-bit PPG mode, and single-channel 16-bit PPG mode. ● Independent two-channel mode The two channels of 8-bit PPG units operate independently. The PPG0 pin is connected to the ch0 PPG output, while the PPG1 pin is connected to the ch1 PPG output. ● 8-bit prescaler + 8-bit PPG mode ch0 is used as an 8-bit prescaler while the count in ch1 is based on borrow outputs from ch0. Thus, 8-bit PPG waveforms can be output with arbitrary length of cycle time. The PPG0 pin is connected to the ch0 prescaler output, while the PPG1 pin is connected to the ch1 PPG output. ● 16-bit PPG 1ch mode ch0 and ch1 are connected and used as a single 16-bit PPG. The PPG0 and PPG1 pins are connected to the 16-bit PPG output. 276 CHAPTER 15 8/16-BIT PPG ■ 8/16-bit PPG output operation In this block, the ch0 PPG is activated to start counting when "1" is written to bit 7 (PEN0) of the PPGC0 (PWM operation mode control) register. Similarly, the ch1 PPG is activated to start counting when "1" is written to bit 15 (PEN1) of the PPGC1 register. Once the operation has started, counting is terminated by writing "0" to bit 7 (PEN0) of PPGC0 or in bit 15 (PEN1) of PPGC1. Once the counting is terminated, the output is maintained at the L level. In 8-bit prescaler + 8-bit PPG mode, do not set ch1 to be in operation while ch0 operation is stopped. In 16-bit PPG mode, ensure that bit 7 (PEN0) of PPGC0 register and bit 15 (PEN1) of PPGC1 register are started or stopped simultaneously. The figure below is a diagram of PPG output operation. During PPG operation, a pulse wave is continuously output at a frequency and duty ratio (the ratio of the H-level period of the pulse wave to the L-level period). PPG continues operation until stop is specified explicitly. Figure 15.4-1 PPG output operation, output waveform PEN Starts operation based on PEN (from Lside). Output pin PPG T (L+1) T L : PRLL value H : PRLH value (H+1) T : Input from peripheral clock (φ, φ/4, φ/16) or timer base counter (depending on the (Start) clock selection by PPG01) ■ Relationship between 8/16-bit PPG reload value and pulse width The width of the output pulse is determined by adding 1 to the reload register value and multiplying it by the count clock cycle. Note that when the reload register value is 00H during 8-bit PPG operation or 0000H during 16-bit PPG operation, the pulse width is equivalent to one count clock cycle. In addition, note that when the reload register value is FFH during 8-PPG operation, the pulse width is equivalent to 256 count clock cycles. When the reload register value is FFFFH during 16-bit PPG operation, the pulse width is equivalent to 65536 count clock cycles. P1=T Ph=T (L+1) (H+1) L : PRLL value H : PRLH value T : Input clock cycle Ph : High pulse width Pl : Low pulse width 277 CHAPTER 15 8/16-BIT PPG 15.5 Selecting a Count Clock for 8/16-bit PPG The count clock used for the operation is supplied from the peripheral clock or the timebase timer. The count clock can be selected from six choices. ■ Selecting a count clock for 8/16-bit PPG Select ch0 clock at bit 4 to 2 (PCM2 to 0) of the PPG01 register, and ch1 clock at bit 7 to 5 (PCS2 to 0) of the PPG01 register. The clock is selected from a peripheral clock 1/16 to 1 times higher than a machine clock or an input clock from the timebase timer. In 8-bit prescaler + 8-bit PPG mode or 16-bit PPG mode, however, the setting in the PCS2 to 0 has no effect. When the timebase timer input is used, the first count cycle after a trigger or a stop may be shifted. The cycle may also be shifted if the timebase counter is cleared during operation of this module. In 8-bit prescaler + 8-bit PPG mode, if ch1 is activated while ch0 is in operation and ch1 is stopped, the first count cycle may be shifted. 278 CHAPTER 15 8/16-BIT PPG 15.6 Controlling Pin Output of 8/16-bit PPG Pulses The pulses generated by this module can be output from external pins PPG0 and PPG1. ■ Controlling pin output of 8/16-bit PPG pulses To output the pulses from an external pin, write "1" to the bit corresponding to each pin (PPGC0: PE0, PPGC1: PE1). When "0" is written to these bits (default), the pulses are not output from the corresponding external pins; the pins work as general-purpose ports. In 16-bit PPG mode, the same waveform is output from PPG0 and PPG1. Thus, the same output can be obtained by enabling both external pin. In 8-bit prescaler + 8-bit PPG mode, the 8-bit prescaler square waveform is output from PPG0, while the 8bit PPG waveform is output from PPG1. Figure 15.6-1 is a diagram of output waveforms in this mode. Figure 15.6-1 8+8 PPG output operation waveform Ph0 Pl0 PPG0 PPG1 Ph1 Pl0 = T Pl1 (L0+1) Ph0 = T (L0+1) Pl1 = T (L0+1) (Ll+1) Ph1 = T (L0+1) (Hl+1) L0 : ch0 PRLL value and ch0 PRLH value L1 : ch1 PRLL value H1 : ch1 PRLH value T : Ph0 : Pl0 : Input clock cycle PPG0 high pulse width PPG0 low pulse width Ph1 : Pl1 : PPG1 high pulse width PPG1 low pulse width Note: Set the same value in ch0 PRLL and ch0 PRLH. 279 CHAPTER 15 8/16-BIT PPG 15.7 8/16-bit PPG Interrupts For the 8/16-bit PPG, an interrupt becomes active when the reload value counts out and a borrow occurs. ■ 8/16-bit PPG interrupts In 8-bit PPG 2ch mode or 8-bit prescaler + 8-bit PPG mode, an interrupt is requested by a borrow in each counter. In 16-bit PPG mode, PUF0 and PUF1 are simultaneously set by a borrow in the 16-bit counter. Therefore, enable only PIE0 or PIE1 to unify the interrupt causes. In addition, simultaneously clear the interrupt flags for PUF0 and PUF1. 280 CHAPTER 15 8/16-BIT PPG 15.8 Initial Values of 8/16-bit PPG Hardware The hardware components of this block are initialized to the following values when reset: ■ Initial values of 8/16-bit PPG hardware ● Registers • PPGC0 --> 0X000XX1B • PPGC1 --> 0X000001B • PPG01 --> 000000X0B ● Pulse outputs • PPG0 --> "L" • PPG1 --> "L" • PE0 --> PPG0 output disabled • PE1 --> PPG1 output disabled ● Interrupt requests • IRQ0 --> "L" • IRQ1 --> "L" Hardware components other than the above are not initialized. Note: In a mode other than 16-bit PPG mode, it is recommended to use a word transfer instruction to write data in reload registers PRLL and PRLH. If two byte transfer instructions are used to write a data item to these registers, a pulse of unexpected cycle time may be output depending on the timing. Figure 15.8-1 Write timing for 8/16-bit PPG reload registers (PRLL and PRLH) PPG0 B A B A C B C C D D Assume that PRLL is updated from A to C before point 1 in the time chart above, and PRLH is updated from B to D after point 1. Since the PRL values at point 1 are PRLL=C and PRLH=B, a pulse of L side count value C and H side count value B is output only once. Similarly, to write data in PRL of ch0 and ch1 in 16-bit PPG mode, use a long word transfer instruction, or use word transfer instructions in the order of ch0 and then ch1. In this mode, the data is only temporarily written to ch0 PRL. Then, the data is actually written into ch0 PRL when the ch1 PRL is written to. 281 CHAPTER 15 8/16-BIT PPG In a mode other than 16-bit PPG mode, ch0 and ch1 PRL are written independently. Figure 15.8-2 PRL write operation block diagram ch0 PRL write data ch1 PRL write data Transferred in synchronization with ch1 write in 16-bit Temporary latch PPG mode ch0 write in a mode other than 16-bit PPG mode ch1 write ch0 PRL 282 ch1 PRL CHAPTER 16 DTP/EXTERNAL INTERRUPTS This chapter explains the functions and operations of the DTP/external interrupts. 16.1 Outline of DTP/External Interrupts 16.2 DTP/External Interrupt Registers 16.3 Operations of DTP/External Interrupts 16.4 Switching between External Interrupt and DTP Requests 16.5 Notes on Using DTP/External Interrupts 283 CHAPTER 16 DTP/EXTERNAL INTERRUPTS 16.1 Outline of DTP/External Interrupts The data transfer peripheral (DTP) is located between an external peripheral and the F2MC-16LX CPU. The DTP receives a DMA request or interrupt request from the external peripheral, transfers the request to the F2MC-16LX CPU to activate the intelligent I/O service or interrupt processing. ■ Outline of DTP/external interrupts For the intelligent I/O service, "H" and "L" request levels are available. For an external interrupt request, four request levels are available: "H", "L", rising edge, and falling edge. ■ Block diagram of DTP/external interrupts Figure 16.1-1 Block diagram of DTP/external interrupts 8 8 8 16 284 Interrupt/DTP enable register Gate Cause F/F Edge detection circuit Interrupt/DTP cause register Request level setting register 8 Request input CHAPTER 16 DTP/EXTERNAL INTERRUPTS ■ DTP/External interrupts registers ENIR0 bit Address : 0000C6H ENIR1 bit Address : 0000CAH EIRR0 bit 7 6 5 4 3 2 1 0 Initial Value EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 00000000 B 7 6 5 4 3 2 1 0 EN10 EN9 EN8 9 8 EN15 EN14 EN13 EN12 EN11 15 Address : 0000C7H ER7 bit EIRR1 Address : 0000CBH 15 ELVR0 bit Address : 0000C8H ELVR0 bit Address : 0000C9H ELVR1 bit Address : 0000CCH ELVR1 bit Address : 0000CDH EISSR bit 14 13 12 11 10 ER6 ER5 ER4 ER3 ER2 14 13 12 11 10 ER15 ER14 ER13 ER12 ER11 7 6 5 4 3 LB3 LA3 LB2 LA2 LB1 15 14 13 12 LB7 LA7 LB6 LA6 11 LB5 ER1 ER0 9 8 ER10 ER9 ER8 2 1 0 LB0 LA0 LA1 10 9 8 LA5 LB4 LA4 7 6 5 4 3 2 1 LB11 LA11 LB10 LA10 LB9 LA9 LB8 LA8 15 14 13 12 11 10 9 8 LB14 LA14 LB13 LA13 LB15 LA15 7 6 5 4 3 2 Address : 0000CEH INT15R INT14R INT13R INT12R INT11R INT10R XXXXXXXX B XXXXXXXX B 00000000 B 00000000 B 0 LB12 LA12 1 00000000 B 00000000 B 00000000 B 0 INT9R INT8R 00000000 B 285 CHAPTER 16 DTP/EXTERNAL INTERRUPTS 16.2 DTP/External Interrupt Registers The DTP/external interrupts has the following three types of registers: • Interrupt/DTP enable register (ENIR: External interrupt request enable register) • Interrupt/DTP flag (EIRR: External interrupt request register) • Request level setting register (ELVR: External level register) • External interrupt source select register (EISSR) ■ Interrupt/DTP enable register (ENIR: External interrupt request enable register) Figure 16.2-1 External interrupt request enable register (ENIR) 7 EN7 6 EN6 5 EN5 4 EN4 3 EN3 2 EN2 1 EN1 0 EN0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 EN15 EN14 5 EN13 4 EN12 3 EN11 2 EN10 R/W R/W R/W : Readable and writable R/W R/W R/W R/W ENIR0 Address : 0000C6 H ENIR1 Address : 0000CAH 1 EN9 Initial value 00000000B 0 EN8 R/W 00000000B R/W The ENIR register contains the interrupt enable bits of the DTP/external interrupt module. When an ENx bit is enabled, an interrupt request is signaled if the specified interrupt event is detected at the corresponding pin. Writing "1" to these bits enables and writing "0" disables interrupt requests. ■ Interrupt/DTP flags (EIRR: External interrupt request register) Figure 16.2-2 External interrupt request register (EIRR) EIRR Address : 0000C7 H EIRR Address : 0000CB H 15 14 13 12 11 10 ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 ER13 ER12 ER11 ER10 ER9 ER8 R/W R/W R/W R/W R/W R/W ER15 ER14 R/W R/W R/W : Readable and writable X : Undefined 9 8 Initial value XXXXXXXX B Initial value XXXXXXXX B The EIRR register contains the interrupt flags. If the specified interrupt event is detected at a pin, the corresponding ERx bit is set and if the ENx bit is "1", then an interrupt request is signaled to the interrupt controller. Writing "1" to these bits has no effect and writing "0" clears the flags. "1" is always read from these bits by the read-modify-write instructions. Note: When clearing the interrupt flag, make sure to clear the flag which caused the interrupt alone but not others. 286 CHAPTER 16 DTP/EXTERNAL INTERRUPTS ■ Request level setting register (ELVR: External Interrupt level register) Figure 16.2-3 External interrupt level register (ELVR) 7 ELVR0 Address : 0000C8 H Address : 0000C9 H ELVR1 Address : 0000CC H Address : 0000CD H 6 5 4 3 2 1 0 Initial value LB1 LA1 LB0 LA0 00000000B LB3 LA3 LB2 LA2 R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 LB11 LA11 LB10 LA10 LB9 LA9 LB8 LA8 R/W 15 R/W 14 R/W 13 R/W 12 R/W 11 R/W R/W R/W 10 9 8 LB15 LA15 LB14 LA14 LB13 LA13 LB12 LA12 R/W R/W R/W R/W R/W R/W R/W R/W 00000000 B 00000000 B 00000000 B R/W : Readable and writable ELVR defines the request event at the external pin. Each pin is assigned with two bits as described in Table 16.2-1. If a request is detected by the input level, the interrupt flag is set as long as the input is at the specified level even after the flag is reset by software. Table 16.2-1 Interrupt request detection factor for external pins LBx LAx Interrupt request detection factor 0 0 L level pin input 0 1 H level pin input 1 0 Rising edge pin input 1 1 Falling edge pin input 287 CHAPTER 16 DTP/EXTERNAL INTERRUPTS ■ External interrupt source select register Figure 16.2-4 External interrupt source select register (EISSR) 7 EISSR 6 5 4 Address : 0000CEH R/W R/W R/W R/W 3 2 1 INT11R INT10R INT9R 0 R/W R/W R/W R/W Initial value 00000000B R/W : Readable and writable The 8 external interrupt inputs INT9 to INT11 can be relocated to different pins to offer a “wakeup by resource input” function like CAN wakeup. The standard location of INT9 to INT11 is Port0 (External bus). some interrupt inputs are moved to other pins to use the interrupt function even when the external bus is used. The source for the interrupt function will be defined by this EISSR register according to the following table. Table 16.2-2 The selection of the interrupt function 288 EISSR bit “0” (Initial value) “1” INT9R P01 P42(RX1/IN6) INT10R P02 P32 INT11R P03 P12(SIN3) CHAPTER 16 DTP/EXTERNAL INTERRUPTS 16.3 Operations of DTP/External Interrupts When the interrupt flag is set, this block signals an interrupt to the interrupt controller. The interrupt controller judges the priority levels of the simultaneous interrupts, and issues an interrupt request to the F2MC-16LX CPU if the interrupt from this block has the highest priority. The F2MC-16LX CPU compares the ILM bits of its internal CCR register and the interrupt request. If the interrupt level of the request is higher than that indicated by the ILM bits, the F2MC-16LX CPU activates the hardware interrupt processing microprogram as soon as the currently executing instruction is terminated. ■ External interrupt operation In the hardware interrupt processing microprogram, the CPU reads the ISE bit information from the interrupt controller, identifies that the request is for interrupt processing based on that information, and branches to the interrupt processing microprogram. The interrupt processing microprogram reads the interrupt vector area and issues an interrupt acknowledgment signal for the interrupt controller. Then, the microprogram transfers the jump destination address of the macro instruction generated from the vector to the program counter, and executes the user interrupt processing program. Figure 16.3-1 External interrupt External interrupt/DTP Interrupt controller F2MC-16LX CPU ICRyy IL Other request ELVR EIRR ENIR Cause CMP ICRxx CMP ILM INTA 289 CHAPTER 16 DTP/EXTERNAL INTERRUPTS ■ DTP operation To activate the intelligent I/O service, the user program initially sets the address of a register, assigned between 000000H and 0000FFH, in the I/O address pointer of the intelligent I/O service descriptor. Then, the user program sets the start address of the memory buffer in the buffer address pointer. The DTP operation sequence is almost the same as for external interrupts. The operation is identical until the CPU activates the hardware interrupt processing microprogram. Then, for the DTP, control is transferred to the intelligent I/O service processing microprogram, since the ISE bit read by the CPU within the hardware interrupt processing microprogram indicates the DTP. Once the intelligent I/O service is activated, a read or write signal is sent to the addresses external peripheral, and data is transferred between the peripheral and the chip. The external peripheral must cancel the interrupt request to this chip within three machine cycles after the transfer is made. When the transfer is completed, the descriptor is updated, and the interrupt controller generates a signal that clears the transfer cause. Upon receiving the signal to clear the transfer cause, this resource clears the flip-flop holding the cause and prepares for the next request from the pin. For details of the intelligent I/O service processing, refer to the MB90500 Programming Manual. Figure 16.3-2 Timing to cancel the external interrupt at the end of DTP operation Edge request or H level request Internal operation Interrupt cause * When data is transferred from the I/O register to memory in the intelligent I/O service Selecting and reading descriptor Read address Address bus pin Data bus pin Write address Read data Write data Read signal Write signal Cancel within three machine cycles. Data, address bus Internal bus Register External peripheral Figure 16.3-3 Sample interface to the external peripheral INT IRQ DTP Cancel within three machine cycles after transfer. 290 MB90350 CORE MEMORY CHAPTER 16 DTP/EXTERNAL INTERRUPTS 16.4 Switching between External Interrupt and DTP Requests To switch between external interrupt and DTP requests, use the ISE bit in the ICR register corresponding to this block, which is in the interrupt controller. Each pin is individually assigned ICR. Thus, a pin is used for a DTP request if "1" is written to the ISE bit of the corresponding ICR, and is used for an external interrupt request if "0" is written to the bit. ■ Switching between external interrupt and DTP requests Figure 16.4-1 Switching between external interrupt and DTP requests Interrupt controller 0 ICR xx ICR yy 1 F2MC-16LX CPU Pin External interrupt/DTP DTP External interrupt 291 CHAPTER 16 DTP/EXTERNAL INTERRUPTS 16.5 Notes on Using DTP/External Interrupts Note carefully the following items when using DTP/external interrupts: The following points must be considered to use the DTP/External function. • Conditions on the behavior of external circuit for the DTP function • Clearing interrupt flag • External interrupt request level ■ Notes on using DTP/external interrupts ● Conditions on the externally connected peripheral when DTP is used DTP supports only external peripherals that automatically clear a request once a transfer is completed. The system must be designed so that a transfer request is canceled within three machine cycles (provisional) after transfer operation starts. Otherwise, this resource assumes that a transfer request is issued. ● External interrupt/DTP operation procedure To set registers in the external interrupt/DTP, follow the steps below: 1. Disable the bits corresponding to the enable register. 2. Set the bits corresponding to the request level setting register. 3. Clear the bits corresponding to the cause register. 4. Enable the bits corresponding to the enable register. (Steps 3. and 4. can be simultaneously performed by word specification.) To set a register in this resource, ensure that the enable register is disabled. Before enabling the enable register, ensure that the cause register is cleared. Clearing the cause register prevents a false interrupt cause from being determined while registers are set or interrupts are enabled. ● External interrupt request level • When edge detection is specified as the event input, the pulse width of the input signal must be greater than equal to 3 machine clock cycles to recognize the input edge. • When level detection is specified as the event input, the interrupt flag keeps active status once the specified level is input even after the input signal changes to the inactive level as shown in Figure 16.51 . In order to clear the request, the interrupt flag must be cleared. To detect an edge for an edge request level, the pulse width must be at least three machine cycles. As shown in Figure 16.5-1, when the request input level is related to the level setting, a request that is input from an external device to the interrupt controller is kept active even if the request is later canceled because a cause hold circuit has been installed. To cancel the request to the interrupt controller, the cause hold circuit must be cleared as shown in Figure 16.5-2. 292 CHAPTER 16 DTP/EXTERNAL INTERRUPTS Figure 16.5-1 Clearing interrupt/DTP cause register upon level set Level detection Interrupt cause Interrupt flag (interrupt/DTP cause register) Interrupt enable To interrupt controller The cause is kept held unless cleared. Figure 16.5-2 Interrupt cause and interrupt request to the interrupt controller while interrupts are enabled Interrupt cause H level Interrupt request to the interrupt controller Set inactive when the cause F/F is cleared. 293 CHAPTER 16 DTP/EXTERNAL INTERRUPTS 294 CHAPTER 17 A/D CONVERTER This chapter explains the function and operation of the A/D converter. 17.1 Features of A/D Converter 17.2 Block Diagram of A/D Converter 17.3 Registers for A/D Converter 17.4 Operation of A/D Converter 17.5 Conversion Using EI2OS 17.6 Convert-data Protection Function 295 CHAPTER 17 A/D CONVERTER 17.1 Features of A/D Converter The A/D converter converts analog input voltages to digital values. ■ Features of A/D converter • Conversion time: 1.9 µs min. per channel (with 24-MHz machine clock) • RC successive approximation conversion with sample and hold circuit • Resolution: 10 bits or 8 bits • Analog input pin selected from up to 15 channels by program - Single-channel conversion:1 channel is selected and converted. - Scan conversion:Sequential channels (up to 24* channels) are converted. • Mode setting - Single mode : Converts the specified channels once. Up to 24* channels can be specified. - Continuous mode : Converts the specified channels repeatedly. Up to 24* channels can be specified. - Stop mode : Converts one channel, then the converter stops and stands by for the next activation. (starting of conversion can be synchronized) • Interrupt requests At the end of A/D conversion end, the interrupt request for an A/D conversion can be signaled to the interrupt controller. This interrupt can start EI2OS or µDMA, which can transfer A/D conversion result data to the memory. • Selectable activation cause The activation can be done by software, reload timer 1, or external trigger (falling edge). *: 24 channel Analog inputs are only supported by the products with 'C'-suffix. The products without 'C'suffix have 16 channel Analog inputs. ■ Analog input enable register The A/D converter's analog input pins are assigned to ports 5 to 7. Set pins to be used as analog input to “analog input enable (default)” by setting “1” to corresponding bit of analog input enable register. For details, see Section "9.2.4 Analog Input Enable Register". 296 CHAPTER 17 A/D CONVERTER Figure 17.1-1 Analog Input Enable register for Port5 15 14 13 12 11 10 9 8 ADER5 OBH ADE15 ADE14 ADE13 ADE12 ADE11 ADE10 ADE9 ADE8 Read/Write Initial Value (R/W) (1) (R/W) (1) (R/W) (1) (R/W) (1) (R/W) (1) (R/W) (1) (R/W) (1) (R/W) (1) Analog Input Enable register for Port6 7 ADER6 OCH Read/Write Initial Value 6 5 4 3 2 1 0 ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 (R/W) (1) (R/W) (1) (R/W) (1) (R/W) (1) (R/W) (1) (R/W) (1) (R/W) (1) (R/W) (1) Pins of port 5 and 6 are controlled as described below. 0: Port input/output mode 1: Analog input mode “1” is set upon a reset Table 17.1-1 Analog input pins pin name Port Analog input channel name corresponding ADE bit LQFP QFP 34 36 AN0 ADE0 35 37 AN1 ADE1 36 38 AN2 ADE2 37 39 AN3 Port6 Port5 corresponding ADE register ADE3 ADER6 38 40 AN4 ADE4 39 41 AN5 ADE5 40 42 AN6 ADE6 41 43 AN7 ADE7 22 24 AN8 ADE8 23 25 AN9 ADE9 24 26 AN10 ADE10 25 27 AN11 26 28 AN12 ADE12 27 29 AN13 ADE13 28 30 AN14 ADE14 ADER5 ADE11 297 CHAPTER 17 A/D CONVERTER 17.2 Block Diagram of A/D Converter Figure 17.2-1 shows the block diagram of A/D converter. ■ Block diagram of A/D converter Figure 17.2-1 Block diagram of A/D converter MPX AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 Input circuit Port6 Input circuit Port5 AN14 AN13 AN12 AN11 AN10 AN9 AN8 AVCC AVRH/L AVSS D/A Converter Sequential comparison register Comparator Sample & Hold circuits ADCR0/1 Hold circuit Decoder Setting register 0 Setting register 1 ADSR0/1 Operating clock φ Prescaler A/D control register 0 ADTG pin 16-bit reload timer 1 External trigger starts A/D control register 1 ADCS0/1 Timer starts Analog input enable register 5 Analog input enable register 6 ADER5/6 298 Internal data bus Data Register CHAPTER 17 A/D CONVERTER 17.3 Registers for A/D Converter The A/D converter has the following three registers: • Control status register: ADCS0/1 • Data register: ADCR0/1 • Setting register: ADSR0/1 ■ Registers for A/D converter Figure 17.3-1 Registers for A/D Converter A/D control status register ( Upper) Address: 000069H Read/write Initial value 15 14 13 12 11 10 9 8 BUSY INT INTE PAUS STS1 STS0 STRT - (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (W) (0) (-) (X) 6 5 4 Bit No. ADCS1 A/D control status register (Lower) 7 Address: 000068H Read/write Initial value 3 2 1 0 Bit No. - reserved ADCS0 (-) (X) (-) (0) MD1 MD0 S10 - - - (R/W) (0) (R/W) (0) (R/W) (0) (-) (X) (-) (X) (-) (X) 15 14 13 12 11 10 9 8 Bit No. - - - - - D9 D8 ADCR1 (-) (X) (-) (X) (-) (X) (-) (X) (-) (X) (-) (X) (R) (0) (R) (0) 7 6 5 4 2 1 0 Bit No. D7 D6 D5 D4 D3 D2 D1 D0 ADCR0 (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) 9 8 Data register ( Upper) Address: 00006BH Read/write Initial value - Data register ( Lower) Address: 00006AH Read/write Initial value 3 A/D setting register ( Upper) Address: 00006DH Read/write Initial value 15 14 13 12 11 10 ST2 ST1 ST0 CT2 CT1 CT0 ANS4 ANS3 (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) 6 5 4 2 1 0 Bit No. ADSR1 A/D setting register ( Lower) 7 Address: 00006CH Read/write Initial value 3 ANS2 ANS1 ANS0 ANE4 ANE3 ANE2 ANE1 ANE0 (R/W) (0) (R/W) (0) (R/W) (R/W) (R/W) (0) (0) (0) (R/W) (0) (R/W) (R/W) (0) (0) Bit No. ADSR0 299 CHAPTER 17 A/D CONVERTER 17.3.1 Control status register (ADCS0) The control status register (ADCS0) controls the A/D converter and indicates its status. Do not rewrite ADCS0 during A/D conversion. ■ Control Status Register (ADCS0) Figure 17.3-2 A/D control status register (ADCS0) A/D control status register (Lower) Address: 000068H Read/write Initial value 7 6 5 4 3 2 1 0 Bit No. MD1 MD0 S10 - - - - reserved ADCS0 (R/W) (0) (R/W) (0) (R/W) (0) (-) (X) (-) (X) (-) (X) (-) (X) (-) (0) [bit 7 and bit 6] MD1 and MD0 (A/D converter mode set) Table 17.3-1 Operation Mode Settings MD1 MD0 Operation mode 0 0 Single mode 1 (Reactivation during A/D conversion is allowed.) 0 1 Single mode 2 (Reactivation during A/D conversion is not allowed.) 1 0 Continuous mode (Reactivation during A/D conversion is not allowed.) 1 1 Stop mode (Reactivation during A/D conversion is not allowed.) • Single mode A/D conversion is continuously performed from the channel specified with ANS4 to ANS0 to the channel specified with ANE4 to ANE0. The conversion stops once it has been done for all these channels. • Continuous mode A/D conversion is repeatedly performed from the channel specified with ANS4 to ANS0 to the channel specified with ANE4 to ANE0 in a row. • Stop mode A/D conversion is performed from the channel specified with ANS4 to ANS0 to the channel specified with ANE4 to ANE0, pausing for each channel. The A/D conversion is resumed upon an activation. Note: • The A/D conversion in the continuous or stop mode continues until it is stopped by the BUSY bit. • Write 0 to the BUSY bit to stop the A/D conversion. • Reactivation disabled in single mode2, continuous mode, and stop mode this applies to all kinds of activation. 300 CHAPTER 17 A/D CONVERTER [bit 5] S10 This bit specifies the resolution of conversion. When “0” is written to this bit, 10-bit A/D conversion is performed. When “1” is written to this bit, 8-bit A/D conversion is performed and the conversion result is stored in D7 to D0. [bits 4 to bit 1] Unused bits Writing to these bits has no effect. Reading these bits always returns “1”. [bit 0] reserved (reserved bit) This bit is a reserved bit. Always write “0” to this bit. Reading this bit always returns “0”. 301 CHAPTER 17 A/D CONVERTER 17.3.2 Control status register (ADCS1) The control status register (ADCS1) controls the A/D converter and indicates its status. ■ Control Status Register (ADCS1) Figure 17.3-3 A/D control status register (ADCS1) A/D control status register (Upper) Address: 000069H Read/write Initial value 15 14 13 12 11 10 9 8 Bit No. BUSY INT INTE PAUS STS1 STS0 STRT - ADCS1 (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (W) (0) (-) (X) [bit 15] BUSY (busy flag and stop) • Read operation: - This bit indicates an operation of the A/D converter. - The bit is set by starting of A/D conversion, and cleared by end of A/D conversion. • Write operation: - When “0” is written to this bit during the A/D conversion, the conversion is forced to stop. - Writing “1” to this bit has no effect. Notes: • “1” is read from this bit when an read-modify-write instruction is used. • In the single mode, this bit is cleared when A/D conversion ends. • In the continuous or stop mode, the A/D conversion does not stop until writing "0" to this bit. • This bit is initialized to 0 by reset. • Do not perform the forced stop and the activation concurrently (using software (BUSY = 0, STRT = 1), external trigger, or timer). 302 CHAPTER 17 A/D CONVERTER [bit 14] INT (interrupt) This bit is set when converted data is written to ADCR. When this bit is set with bit5 (INTE) set to “1”, an interrupt request is generated. In addition, the EI2OS or µDMA is activated if it is enabled. Writing “1” to this bit has no effect. This bit is cleared by writing “0” or by the interrupt clear signal from the EI2OS/µDMA. Notes: • To clear this bit by writing “0”, ensure that A/D conversion is not in progress. • This bit is initialized to “0” at reset. • Using an RMW instruction, “1” is read from this bit. [bit 13] INTE (Interrupt enable) This bit enables and disables the interrupt. •0: Interrupt disabled •1: Interrupt enabled When using EI2OS or µDMA, set this bit (EI2OS or µDMA is started by an interrupt request). This bit is initialized to 0 at reset. [bit 12] PAUS (A/D converter pause) This bit is set when A/D conversion pauses. Only one register is available for storing the A/D conversion result. Therefore, unless the conversion results are transferred by the EI2OS (or µDMA), the result data would be continuously updated and destroyed in continuous conversion. To prevent the above condition, the system is so designed as not to store the next converted-data when a conversion result is not transferred yet (INT = “1”), with INTE = “1”. A/D conversion pauses during that period. When transfer by EI2OS (or µDMA) ends or when “0” is set to INT bit, A/D conversion is resumed. Once this bit is set, it is not cleared by itself, write "0" to clear this bit. This bit is valid only when EI2OS (or µDMA) is used. Notes: • Regarding the convert data protection function, see Section "17.6 Convert-data Protection Function". • This bit is initialized to “0” by reset. [bit 11 and bit 10] STS1 and STS0 (Start source select) These bits are initialized to “00B” by reset. Select an A/D conversion activation cause by setting these bits. Table 17.3-2 Function Settings STS1 STS0 Function 0 0 Activation A/D conversion by software 0 1 Activation A/D conversion by external pin trigger and by software 1 0 Activation A/D conversion by timer and by software 1 1 Activation A/D conversion by external pin trigger, timer, and by software 303 CHAPTER 17 A/D CONVERTER In a mode allowing two or more activation courses, A/D conversion is activated by the source that occurs first. When changing the setting of these bits during A/D conversion, the result is immediately reflected. Therefore it is not a recommended practice. Notes: • An external pin trigger is detected by the falling edge. When the external trigger input level is Low, setting external pin triggers starting may start A/D converter. • When the timer is selected, the 16-bit reload timer 1 is selected and the conversion is activated when the output from the timer becomes "1". [bit 9] STRT (Start) A/D conversion is started by writing “1” to this bit. To reactivate A/D conversion, write “1” to this bit again. At reset, this bit is initialized to “0”. Reading this bit always returns “1”. Using an read-modify-write instruction, “0” is read from this bit. Reactivation during the operation is only available in the single mode 1, but not supported in the single mode2, continuous mode and the stop mode. Check the BUSY bit before writing “1” to this bit in the latter three modes. Do not force to stop A/D conversion concurrently with activation of A/D conversion by software (BUSY=0, STRT=1). [bit 8] Unused bit Writing to this bit has no effect. Reading this bit always returns “1”. 304 CHAPTER 17 A/D CONVERTER 17.3.3 Data Register (ADCR0, ADCR1) The data register (ADCR0, ADCR1) is used to store digital value generated as a result of conversion. ADCR0 stores lower 8 bits; ADCR1 stores most significant 2 bits of the conversion result. These register's values are rewritten every time conversion ends. Normally, the last converted value is stored in these register's bits. ■ Data register (ADCR0, ADCR1) Figure 17.3-4 Data register (ADCR0, ADCR1) Data register (Upper) Address: 00006BH Read/write Initial value 15 14 13 12 11 10 9 8 Bit No. - - - - - - D9 D8 ADCR1 (-) (X) (-) (X) (-) (X) (-) (X) (-) (X) (-) (X) (R) (0) (R) (0) 7 6 5 4 3 2 1 0 Bit No. D7 D6 D5 D4 D3 D2 D1 D0 ADCR0 (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) Data register (Lower) Address: 00006AH Read/write Initial value (R) (0) (R) (0) (R) (0) Reading bit 10 to bit 15 of ADCR1 always returns “1”. When S10 bit of ADCS0 is “1”, the 8-bit mode is established, storing converted data in bit7 to bit0. In this case, Reading bit9 to bit8 always returns “1”. For the use of the conversion data protection function, see Section "17.4 Operation of A/D Converter". Do not write to this register. 305 CHAPTER 17 A/D CONVERTER 17.3.4 Setting Register (ADSR0, ADSR1) The setting register (ADSR) is used to set the A/D conversion time and the sampling channels and to indicate the current sampling channel. ■ Setting Register (ADSR) Figure 17.3-5 Setting register (ADSR) A/D setting register (Upper) Address: 00006DH Read/write Initial value 15 14 13 12 11 10 9 8 ST2 ST1 ST0 CT2 CT1 CT0 ANS4 ANS3 (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) 7 6 5 4 3 2 1 0 Bit No. ADSR1 A/D setting register (Lower) Address: 00006CH Read/write Initial value ANS2 ANS1 ANS0 ANE4 ANE3 ANE2 ANE1 ANE0 (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) Bit No. ADSR0 (R/W) (0) [bit 15 to bit 13] ST2, ST1, ST0 (Sampling time) Table 17.3-3 Function Settings ST2 ST1 ST0 Function 0 0 0 4-machine cycle (8 MHz, 0.5 µs) 0 0 1 6-machine cycle (8 MHz, 0.75 µs) 0 1 0 8-machine cycle (16 MHz, 0.5 µs) 0 1 1 12-machine cycle (24 MHz, 0.5 µs) 1 0 0 24-machine cycle (8 MHz, 3 µs) 1 0 1 36-machine cycle (16 MHz, 2.25 µs) 1 1 0 48-machine cycle (16 MHz, 3.0 µs) 1 1 1 128-machine cycle (24 MHz, 5.3 µs) These bits define the sampling time for the analog input signal. Setting for these bits must be carefully evaluated with the following conditions. Otherwise, the result may not provide the guaranteed conversion accuracy. • If the driving impedance. Rext is 1.5 kΩ or less, the sampling time must be greater than equal to; 0.5 µs; For 4.5 V ≤ AVCC ≤ 5.5 V 306 CHAPTER 17 A/D CONVERTER 1.2 µs; For 4.0 V ≤ AVCC < 4.5 V • If the driving impedance. Rext is greater than 1.5 kΩ, the sampling time must be greater than Tsamp given by the following formula: Tsamp = (2.25 kΩ + Rext) × 10.7 pF × 7; For 4.5 V ≤ AVCC ≤ 5.5 V Tsamp = (13.6 kΩ + Rext) × 10.7 pF × 7; For 4.0 V ≤ AVCC ≤ 4.5 V [bit 12 and bit 10] CT2, CT1, CT0 (Compare time) Table 17.3-4 Function Settings CT2 CT1 CT0 Function 0 0 0 22-machine cycle (8 MHz, 2.8 µs) 0 0 1 33-machine cycle (16 MHz, 2.1 µs) 0 1 0 44-machine cycle (20 MHz, 2.2 µs) 0 1 1 66-machine cycle (24 MHz, 2.8 µs) 1 0 0 88-machine cycle (8 MHz, 11.0 µs) 1 0 1 132-machine cycle (16 MHz, 8.3 µs) 1 1 0 176-machine cycle (20 MHz, 8.8 µs) 1 1 1 264-machine cycle (24 MHz, 11.0 µs) These bits are used to determine a duration of the comparison operation time. These bits define the conversion time of the successive approximation. Setting for these bits must meet the following conditions. Otherwise, the result may not provide the guaranteed conversion accuracy. ≥ 1.0 µs; For 4.5 V ≤ AVCC ≤ 5.5 V ≥ 2.0 µs; For 4.0 V ≤ AVCC < 4.5 V Conversion precision is not assured. [bit 9 to bit 5] ANS4, ANS3, ANS2, ANS1, ANS0 (Analog start channel set) These bits are used to set the starting channel for A/D conversion, and to indicate the current analog input channel. When the A/D converter is activated, A/D conversion is started from the channel selected by these bits. Table 17.3-5 Starting Channel Settings (1/2) ANS4 ANS3 ANS2 ANS1 ANS0 Starting channel 0 0 0 0 0 AN0 0 0 0 0 1 AN1 0 0 0 1 0 AN2 0 0 0 1 1 AN3 0 AN28 • • • 1 1 1 0 307 CHAPTER 17 A/D CONVERTER Table 17.3-5 Starting Channel Settings (Continued) (2/2) ANS4 ANS3 ANS2 ANS1 ANS0 Starting channel 1 1 1 0 1 AN29 1 1 1 1 0 AN30 1 1 1 1 1 AN31 • Read operation These bits indicates the current analog input channel for the conversion operation. When the conversion operation is stopped, the last channel is indicated. And before A/D conversion starts, the previous conversion channel will be read even if these bits have been already set to the new value. • At reset: These bits are initialized to “00000B”. [bit 4 to bit 0] ANE4, ANE3, ANE2, ANE1, ANE0 (Analog end channel set) These bits are used to set the ending channel for A/D conversion. Table 17.3-6 Ending Channel Settings ANE4 ANE3 ANE2 ANE1 ANE0 Ending channel 0 0 0 0 0 AN0 0 0 0 0 1 AN1 0 0 0 1 0 AN2 0 0 0 1 1 AN3 • • • 1 1 1 0 0 AN28 1 1 1 0 1 AN29 1 1 1 1 0 AN30 1 1 1 1 1 AN31 • At reset, these bits are initialized to “00000B”. 308 CHAPTER 17 A/D CONVERTER Note: • When writing to this register, always use word access. When byte write or read-modify-write is performed for this register, A/D conversion may be started from an unintended channel. • When the same channel is written to the ANE4 to ANE0 bits and to the ANS4 to ANS0 bits, conversion is performed for only 1 channel (single channel conversion). • When conversion of the Analog end channel set by ANE4 to ANE0 is ended, with the continuous mode or the stop mode, control returns to the Analog start channel set by the ANS4 to ANS0 bits. • When the ANS > ANE is set for channel, conversion starts from the Analog start channel and when conversion of AN31 ends, and then returns to the AN0 and ends in the Analog end channel. In this case, the conversion results could be incorrect, because analog input AN15 to AN31 do not exist. To prevent this operation, do not set ANS larger than ANE. • Do not set number of channel that doesn't exist on the device to ANEx bits or ANSx bits. 0 to 14 can be set to ANEx bits or ANSx bits. 309 CHAPTER 17 A/D CONVERTER 17.4 Operation of A/D Converter The A/D converter operates using the sequential-comparison converter system; and 10 bits or 8 bits can be selected for the A/D converter's resolution. Since this A/D converter has only one register (10 bits; conversion result data register ADCR0 and ADCR1) for storing conversion results, this register is rewritten every time conversion is ended. So, this A/D converter alone is not suitable for continuous conversion; and therefore conversion be performed with transferring converted data to the memory using the extended intelligent I/O function (EI2OS) or using µDMA is recommended. ■ Single mode 1 / 2 In the single mode, analog inputs from the starting channel set by the ANS bits to the ending channel set by the ANE bits are sequentially converted; and when conversion of the ending channel is ended, A/D conversion is stopped. When the starting channel and the ending channel are the same (ANS = ANE), conversion is performed for only the channel set by the ANS bits. Example: ANS = 00000B, ANE = 00011 B: Start --> AN0 --> AN1 --> AN2 --> AN3 --> End ANS = 00010 B, ANE = 00010 B: Start --> AN2 --> End ■ Continuous mode In the continuous mode, analog inputs from the starting channel set by the ANS bits to the ending channel set by the ANE bits are sequentially converted; and when conversion of the ending channel is ended, control returns to the starting channel to continue A/D conversion. When the starting channel and the ending channel are the same (ANS = ANE), conversion is continued for only the channel set by the ANS bits. Example: ANS = 00000B, ANE = 00011 B: Start --> AN0 --> AN1 --> AN2 --> AN3 --> AN0 -->-->--> Repetition of sequence ANS = 00010 B, ANE = 00010 B: Start --> AN2 --> AN2 --> AN2 -->-->--> Repetition of sequence In the continuous mode, A/D conversion is repeated until “0” is written to the BUSY bit (when “0” is written to the BUSY bit, operation of the A/D converter stops forcibly). Note that when operation of the A/D converter stops forcibly, A/D conversion stops halfway. In this case, the conversion result register contains the previous data for which conversion completed. ■ Stop mode In the stop mode, analog inputs from the starting channel set by the ANS bits to the ending channel set by the ANE bits are sequentially converted, but every time one channel is converted, conversion stops. When conversion of the ending channel is ended, control returns to the starting channel to continue A/D 310 CHAPTER 17 A/D CONVERTER conversion. When the starting channel and the ending channel are the same (ANS = ANE), conversion is performed for only one channel. Example: ANS = 00000B, ANE = 00011 B: Start --> AN0 --> Stop --> Start --> AN1 --> Stop --> Start --> AN2 --> Stop --> Start --> AN3 --> Stop --> Start --> AN0 -->-->--> Repetition of sequence ANS = 00010 B, ANE = 00010 B: Start --> AN2 --> Stop --> Start --> AN2 --> Stop --> Start --> AN2 -->-->--> Repetition of sequence In the above sequences, only A/D activation causes set using the STS1 and STS0 bits are valid. The start of conversion can be synchronized by this mode. 311 CHAPTER 17 A/D CONVERTER 17.5 Conversion Using EI2OS Figure 17.5-1 gives an example of flow (continuous mode) from the activation of A/D conversion to the transfer of converted data. ■ Conversion using EI2OS Figure 17.5-1 Example of flow (continuous mode) from activation of A/D conversion to transfer of converted data EI2OS controller A/D conveter A/D converter activated Sample & Hold Data transfer 2 EI OS request Conversion * Conversion ended ADCS:INT=0? N Y Store conversion data to ADCR0/1 Interrupt generated 312 interrupt cleared INT clear request *: The operation count depends 2 on the setting of the EI OS. Interrupt processing CHAPTER 17 A/D CONVERTER 17.5.1 Example of activating of EI2OS in single mode In the single mode, EI2OS is activated in the following procedure: • Convert analog inputs AN1 to AN3 and then end the conversion. • Transfer sequentially converted data to the 200H to 205H addresses. • Activate conversion using software. • Use the highest interrupt level. ■ Example of starting of EI2OS in single mode Table 17.5-1 Operation Description Setting item Sample program MOV ICR03, #08H Operation description Set the highest interrupt level, start EI2OS at the interrupt, and set the descriptor address. MOV BAPL, #00H MOV BAPM, #02H Transfer destination address for converted data MOV BAPH, #00H Setting of EI2OS MOV ISCS, #18H MOV IOAL, #6AH Transfer word data, and then increment the transfer destination address. Transfer converted data from I/O to the memory. Don't terminate transfer due to a request from the resource. Set the A/D converter result register MOV IOAH, #00H MOV DCTL, #03H MOV DCTH, #00H Setting of A/D converter Interrupt sequence Performs EI2OS transfer three times (the number of conversion times) MOV ADCS0, #00H Single mode1 MOVW ADSR0, #6823H The sampling time is 0.6 µs; the comparison operation time is 2.2 µs (as machine CLK is 20 MHz); the starting channel is AN1; the ending channel is AN3. MOV ADCS1, #A2H Start A/D conversion using software. MOV ADCS1, #80H RETI ICR03: Interrupt control register BAPM: Buffer address pointer (middle) ISCS: EI2OS status register IOAL: I/O address counter (lower) IOAH: I/O address counter (upper) Return from the interrupt. BAPL: Buffer address pointer (lower) BAPH: Buffer address pointer (upper) DCTL: Data counter (lower) DCTH: Data counter (upper) 313 CHAPTER 17 A/D CONVERTER Figure 17.5-2 Example of starting of EI2OS in single mode START AN1 Interrupt Transfer by EI2OS AN2 Interrupt Transfer by EI2OS AN3 Interrupt Transfer by EI2OS END Interrupt sequence Parallel processing 314 CHAPTER 17 A/D CONVERTER Example of activating of EI2OS in continuous mode 17.5.2 An example of the activating of EI2OS in the continuous mode is given below. • Convert analog inputs AN3 to AN5 and obtain two converted data for each channel. • Transfer sequentially converted data to the 600H to 60BH addresses. • Start conversion using an external edge input. • Use the highest interrupt level. ■ Example of starting of EI2OS in continuous mode Table 17.5-2 Operation Description Setting item Sample program MOV ICR03, #08H Operation description Set the highest interrupt level, start EI2OS at the interrupt, and set the descriptor address. MOV BAPL, #00H MOV BAPM, #06H Transfer destination address for converted data MOV BAPH, #00H Setting of EI2OS MOV ISCS, #18H MOV IOAL, #6AH Transfer word data, and then increment the transfer destination address. Transfer converted data from I/O to the memory. Don't terminate transfer due to a request from the resource. Transfer source address MOV IOAH, #00H MOV DCTL, #06H MOV DCTH, #00H Setting of A/D converter EI2OS end interrupt sequence Transfer converted data by EI2OS six times data for '3 channels × 2'. MOV ADCS0, #80H Continuous mode MOVW ADSR0, #6865H The sampling time is 0.6 µs; the comparison operation time is 2.2 µs (with machine CLK is 20 MHz); the starting channel is AN3; the ending channel is AN5. MOV ADCS1, #A4H Start A/D conversion using external edge. MOV ADCS1, #84H RETI Return from the interrupt. ICR03: Interrupt control register BAPL: Buffer address pointer (lower) BAPM: Buffer address pointer (middle) BAPH: Buffer address pointer (upper) ISCS: EI2 OS status register IOAL: I/O address counter (lower) DCTL: Data counter (lower) IOAH: I/O address counter (upper) DCTH: Data counter (upper) 315 CHAPTER 17 A/D CONVERTER Figure 17.5-3 Example of starting of EI2OS in continuous mode START AN3 Interrupt EI2OS AN4 Interrupt EI2OS AN5 Interrupt EI2OS After transfer 6 times in total: Interrupt sequence END 316 CHAPTER 17 A/D CONVERTER Example of activating of EI2OS in stop mode 17.5.3 An example of the activating of EI2OS in the stop mode is given below. • Convert the analog input AN3 12 times at regular intervals. • Transfer sequentially converted data to the 600H to 617H addresses. • Start conversion using an external edge input. • Use the highest interrupt level. ■ Example of starting of EI2OS in stop mode Table 17.5-3 Operation Description Setting item Sample program MOV ICR03, #08H Operation description Set the highest interrupt level, start EI2OS at the interrupt time, and set the descriptor address. MOV BAPL, #00H MOV BAPM, #06H Transfer destination address for converted data MOV BAPH, #00H Setting of EI2OS MOV ISCS, #18H MOV IOAL, #6AH Transfer word data, and then increment the transfer destination address. Transfer converted data from I/O to the memory. Don't terminate transfer due to a request from the resource. Transfer source address MOV IOAH, #00H MOV DCTL, #0CH MOV DCTH, #00H Setting of A/D converter EI2OS end interrupt sequence Transfer converted data by EI2OS 12 times. MOV ADCS0, #C0H Stop mode MOVW ADSR0, #6863H The sampling time is 0.6 µs; the comparison operation time is 2.2 µs (with machine CLK is 20 MHz); the starting channel is AN3; the ending channel is AN3 (1 channel is converted). MOV ADCS1, #A4H Start A/D conversion using the external edge. MOV ADCS1, #84H RETI Return from the interrupt. ICR03: Interrupt control register BAPL: Buffer address pointer (lower) BAPM: Buffer address pointer (middle) BAPH: Buffer address pointer (upper) ISCS: EI2 OS status register IOAL: I/O address counter (lower) DCTL: Data counter (lower) IOAH: I/O address counter (upper) DCTH: Data counter (upper) 317 CHAPTER 17 A/D CONVERTER Figure 17.5-4 Example of starting of EI2OS in stop mode START AN3 Interrupt Transfer by EI2OS After transfer 12 times: STOP External edge start Interrupt sequence END 318 CHAPTER 17 A/D CONVERTER 17.6 Convert-data Protection Function The A/D converter has the converted-data protection function, is featured by continuous conversion and securing two or more data using EI2OS (or µDMA). Only one conversion data register (ADCR0/1) is provided, so when A/D conversion is continuously performed, converted data is stored every time one conversion is ended, destroying the previous data. To prevent this, the A/D converter has a function that a conversion data is not stored in the register and the A/D conversion pauses even when conversion is ended unless the previous data is transferred to the memory using EI2OS (or µDMA). ■ Converted-data protection function The pause operation is cancelled after converted data is transferred to the memory via EI2OS (or µDMA). When the previous data is already transferred to the memory, A/D conversion is continuously performed without a pause. Note: This function is related to the INT and INTE bits of ADCS1 register. The data protection function operates only in the interrupt enabled state (INTE = 1). In the interrupt disabled state (INTE = 0), this function does not operate. In this state when A/D conversion is continuously performed, converted data is successively stored in the register, destroying old data. When EI2OS (or µDMA) is not used in the interrupt enabled state (INTE = 1), the INT bit is not cleared automatically, so the data protection functions works, placing A/D conversion in a pause. In this case, when the INT bit is cleared (by writing “0” to the bit) in an interrupt sequence, the pause is cancelled. When interrupts are disabled (by writing “0” to INTE bit), with EI2OS (or µDMA) operating and with the A/D converter pausing, A/D converter resume conversion and the contents of the converted-data register may change before it is transferred to memory. When A/D conversion is reactivated during a pause (by writing “1” to STRT bit in the single mode1), pending conversion result is destroyed. When the data protection function works to cause a pause, the PAUS bit is set. The PAUS bit is not cleared by itself, write "0" to clear this bit. 319 CHAPTER 17 A/D CONVERTER ■ Example of flow of data protection function (when EI2OS is used) Figure 17.6-1 Example of flow of data protection function (when EI2OS is used) 2 Set El OS Start continuous A/D conversion First conversion end Store in data register 2 Second conversion end Start EI OS NO A/D conversion pauses 2 EI OS end YES Stored in data register YES NO 2 EI OS end Third conversion end Continues 2 All conversions end Start EI OS Interrupt routine End A/D converter stopp When the A/D converter is reactivated during a pause, queued, converted data is destroyed. ■ Cautions To select the external trigger or the internal timer as the activation causes of A/D converted, the A/D start source select bits (STS1 and STS0 bits) of ADCS1 register are used.In this case, ensure that the input value of an external trigger or of the internal timer are “inactive”. If the values are “active”, A/D conversion may start operating immediately. When setting the STS1 bit and STS0 bit, always set the ADTG pin to “1” (input) and set the internal timer (reload timer 1) to "0" (output). 320 CHAPTER 18 LIN-UART This chapter explains the functions and operation of LIN-UART. 18.1 Overview of LIN-UART 18.2 Configuration of LIN-UART 18.3 LIN-UART Pins 18.4 LIN-UART Registers 18.5 LIN-UART Interrupts 18.6 LIN-UART Baud Rates 18.7 Operation of LIN-UART 18.8 Notes on Using LIN-UART 321 CHAPTER 18 LIN-UART 18.1 Overview of LIN-UART The LIN-UART with LIN (Local Interconnect Network) - Function is a general-purpose serial data communication interface for performing synchronous or asynchronous communication with external devices. UART provides bidirectional communication function (normal mode), master-slave communication function (multiprocessor mode in master/slave systems), and special features for LIN-bus systems (working both as master or as slave device). Please note that UART is not software compatible to the other UARTs. The MB90350 series contain up to five UARTs. ■ LIN-UART functions ● LIN-UART functions LIN-UART is a general-purpose serial data communication interface for transmitting serial data to and receiving data from another CPU and peripheral devices. It has the functions listed in Table 18.1-1. Table 18.1-1 UART functions (1/2) Item 322 Function Data buffer Full-duplex Serial Input 5 times oversampling in asynchronous mode Transfer mode • Clock synchronous (start-stop synchronization and start-stop-bitoption) • Clock asynchronous (using start-, stop-bits) Baud rate • A dedicated baud rate generator is provided, which consists of a 15-bit-reload counter • An external clock can be input and also be adjusted by the reload counter Data length • 7 bits (not in synchronous or LIN mode) • 8 bits Signal mode Non-return to zero (NRZ) Start bit timing Clock synchronization to the falling edge of the start bit in asynchronous mode Reception error detection • Framing error • Overrun error • Parity error CHAPTER 18 LIN-UART Table 18.1-1 UART functions (2/2) Item Function Interrupt request • Reception interrupt (reception complete, reception error detect, LIN-Synch-break detect) • Transmission interrupt (transmission data empty) • Interrupt request to ICU (LIN synch field detection: LSYN) • Both transmission and reception support for extended intelligent I/O service (EI2OS) and DMA function. Master-slave communication function (multiprocessor mode) One-to-n communication (one master to n slaves) (This function is supported both for master and slave system). Synchronous mode Function as Master- or Slave-UART Transceiving pins Direct access possible LIN bus options • • • • • Synchronous serial clock The synchronous serial clock can be output continuously on the SCK pin for synchronous communication with start & stop bits Clock delay option Special synchronous Clock Mode for delaying clock (useful for SPI) Operation as master device Operation as slave device Generation of LIN-Sync-break Detection of LIN-Sync-break Detection of start/stop edges in LIN-Sync-field connected to ICU 6 and 7 ■ UART operation modes The UART operates in four different modes, which are determined by the MD0- and the MD1-bit of the Serial mode register (SMR). Mode 0 and 2 are used for bidirectional serial communication, mode 1 for master/slave communication and mode 3 for LIN master/slave communication. Table 18.1-2 UART operation modes Data length Operation mode parity disabled 0 normal mode 7 or 8 1 multiprocessor 7 or 8 + 1 *2 2 normal mode 8 3 LIN mode 8 parity enabled -- -- Synchronization of mode Length of stop bit data bit direction *1 asynchronous 1 or 2 L/M asynchronous 1 or 2 L/M synchronous 0, 1 or 2 L/M asynchronous 1 L *1: means the data bit transfer format: LSB or MSB first. *2: "+1" means the indicator bit of the address/data selection in the multiprocessor mode, instead of parity. Note: Mode 1 operation is supported both for master or slave operation of UART in a master-slave connection system. In Mode 3 the UART function is locked to 8N1-Format, LSB first. 323 CHAPTER 18 LIN-UART If the mode is changed, UART cuts off all possible transmission or reception and awaits then new action. The MD1 and MD0 bit of the Serial Mode Register (SMR) determine the operation mode of UART as shown in the following table: Table 18.1-3 Mode bit setting MD1 MD0 Mode Description 0 0 0 Asynchronous (normal mode) 0 1 1 Asynchronous (multiprocessor mode) 1 0 2 Synchronous (normal mode) 1 1 3 Asynchronous (LIN mode) ■ UART interrupt and EI2OS Table 18.1-4 UART interrupt and EI2OS Interrupt control register Interrupt cause Interrupt number Vector table address Register name Address Lower Upper Bank EI2OS DMA channel number UART3 reception interrupt #37(25H) ICR13 0000BDH FFFF68H FFFF69H FFFF6AH *1 DRQ12 UART3 transmission interrupt #38(26H) ICR13 0000BDH FFFF64H FFFF65H FFFF66H *2 DRQ13 UART2 reception interrupt #39(27H) ICR14 0000BEH FFFF60H FFFF61H FFFF62H *1 DRQ14 UART2 transmission interrupt #40(28H) ICR14 0000BEH FFFF5CH FFFF5DH FFFF5EH *2 DRQ15 *1: Provided with a function that detects a UART reception error and stops EI2OS. *2: Usable when ICR12, ICR13 and ICR14 or interrupt causes that share an interrupt vector are not used. 324 CHAPTER 18 LIN-UART 18.2 Configuration of LIN-UART This section provides a short overview on the building blocks of LIN-UART. ■ Block diagram of LIN-UART LIN-UART consists of the following blocks: • Reload Counter • Reception Control Circuit • Reception Shift Register • Reception Data Register (RDR) • Transmission Control Circuit • Transmission Shift Register • Transmission Data Register (TDR) • Error Detection Circuit • Oversampling Unit • Interrupt Generation Circuit • LIN Synch Break/Synch Field Detection • Bus Idle Detection Circuit • LIN-UART Serial Mode Register (SMR) • Serial Control Register (SCR) • Serial Status Register (SSR) • Extended Com. Contr. Reg. (ECCR) • Extended Status/Contr. Reg. (ESCR) • Block Diagram of UART 325 CHAPTER 18 LIN-UART Figure 18.2-1 Block diagram of UART (OTO, EXT, REST) CLK PE ORE FRE TIE RIE LBIE LBD transmission clock Reload Counter SCKn TRANSMISSION CONTROL CIRCUIT RECEPTION CONTROL CIRCUIT Pin RBI TBI Start bit Detection circuit Transmission Start circuit Received Bit counter Transmission Bit counter Received Parity counter Transmission Parity counter Restart Reception Reload Counter SINn Interrupt Generation circuit reception clock Pin reception IRQ transm. IRQ TDRE SOTn Oversampling Unit Pin RDRF reception complete SOTn SINn Signal to ICU LIN break and Synch Field Detection circuit SINn Reception shift register Transmission shift register LIN break generation circuit transmission start Bus idle Detection circuit Error Detection RDRn To DMA/ EI 2OS PE ORE FRE LBR LBL1 LBL0 TDRn RBI LBD TBI Internal data bus PE ORE FRE RDRF TDRE BDS RIE TIE SSRn register MD1 MD0 OTO EXT REST UPCL SCKE SOE SMRn register PEN P SBL CL A/D CRE RXE TXE SCRn register LBIE LBD LBL1 LBL0 SOPE SIOP CCO SCES LBR MS ESCRn SCDE register SSM ECCRn register RBI TBI n = 2, 3 ■ Explanation of the different blocks ● Reload Counter The reload counter functions as the dedicated baud rate generator. It can select external input clock or internal clock for the transmitting and receiving clocks. The reload counter has a 15 bit register for the reload value. The actual count of the transmission reload counter can be read via the BGRn0/n1. ● Reception Control Circuit The reception control circuit consists of a received bit counter, start bit detection circuit, and received parity counter. The received bit counter counts reception data bits. When reception of one data item for the specified data length is complete, the received bit counter sets the Reception data register full flag. The start bit detection circuit detects start bits from the serial input signal and sends a signal to the reload counter to synchronize it to the falling edge of these start bits. The reception parity counter calculates the parity of the reception data. 326 CHAPTER 18 LIN-UART ● Reception Shift Register The reception shift register fetches reception data input from the SINn pin, shifting the data bit by bit. When reception is complete, the reception shift register transfers receive data to the RDR register. ● Reception Data Register This register retains reception data. Serial input data is converted and stored in this register. ● Transmission Control Circuit The transmission control circuit consists of a transmission bit counter, transmission start circuit, and transmission parity counter. The transmission bit counter counts transmission data bits. When the transmission of one data item of the specified data length is complete, the transmission bit counter sets the Transmission data register full flag. The transmission start circuit starts transmission when data is written to TDR. The transmission parity counter generates a parity bit for data to be transmitted if parity is enabled. ● Transmission Shift Register The transmission shift register transfers data written to the TDR register to itself and outputs the data to the SOTn pin, shifting the data bit by bit. ● Transmission Data Register (TDR) This register sets transmission data. Data written to this register is converted to serial data and output. ● Error Detection Circuit The error detection circuit checks if there was any error during the last reception. If an error has occurred it sets the corresponding error flags. ● Oversampling Unit The oversampling unit oversamples the incoming data at the SINn pin for five times. It is switched off in synchronous operation mode. ● Interrupt Generation Circuit The interrupt generation circuit administers all cases of generating a reception or transmission interrupt. If a corresponding enable flag is set and an interrupt case occurs the interrupt will be generated immediately. ● LIN synch Break and Synchronization Field Detection Circuit The LIN break and LIN synchronization field detection circuit detects a LIN break, if a LIN master node is sending a message header. If a LIN break is detected a special flag bit is generated. The first and the fifth falling edge of the synchronization field is recognized by this circuit by generating an internal signal for the Input Capture Unit to measure the actual serial clock time of the transmitting master node. ● LIN Synch Break Generation Circuit The LIN break generation circuit generates a LIN break of a determined length. 327 CHAPTER 18 LIN-UART ● Bus Idle Detection circuit The bus idle detection circuit recognizes if neither reception nor transmission is going on. In this case, the circuit generates the special flag bits TBI and RBI. ● LIN-UART Serial Mode Register (SMR) This register performs the following operations: • Selecting the LIN-UART operation mode • Selecting a clock input source • Selecting if an external clock is connected “one-to-one” or connected to the reload counter • Resetting dedicated reload timer • Resetting the LIN-UART (preserving the settings of the registers) • Specifying whether to enable serial data output to the corresponding pin • Specifying whether to enable clock output to the corresponding pin ● Serial Control Register (SCR) This register performs the following operations: • Specifying whether to provide parity bits • Selecting parity bits • Specifying a stop bit length • Specifying a data length • Selecting a frame data format in mode 1 • Clearing the error flags • Specifying whether to enable transmission • Specifying whether to enable reception ● Serial Status Register (SSR) This register checks the transmission and reception status and error status, enables and disables transmission and reception interrupt requests, and sets the bit direction to LSB first or MSB first. ● Extended Status/Control Register (ESCR) This register provides several LIN functions, direct access to the SINn and SOTn pin and setting for the UART synchronous clock mode. ● Extended Communication Control Register (ECCR) The extended communication control register provides bus idle recognition interrupt settings, synchronous clock settings, and the LIN break generation. 328 CHAPTER 18 LIN-UART 18.3 LIN-UART Pins This section describes the LIN-UART pins and provides a pin block diagram. ■ LIN-UART pins The UART pins also serve as general ports. Table 18.3-1 lists the pin functions, I/O formats, and settings required to use UART. Table 18.3-1 LIN-UART pins Pin name Pin function I/O format Pull-up P50/SIN2 P12/SIN3 Port I/O or serial data input CMOS output and CMOS input P51/SOT2 P13/SOT3 Port I/O or serial data output P52/SCK2 P14/SCK3 Port I/O or serial clock input/output P12 to P14 have programmable pullup register. Pins other than above do not have pull-up register. Standby control Provided Setting required to use pin Set as an input port (DDR: corresponding bit = 0) Set to output enable mode (SMRn: SOE = 1) Set as an input port when a clock is input (DDR: corresponding bit 1=0) Set to output enable mode when a clock is output (SMRn: SCKE = 1) Figure 18.3-1 Block diagram of UART pins Resource input * Port data register (PDR) Resource output Internal data bus Resource output enable PDR read Output latch Pch PDR write Pin Port direction register (DDR) Direction latch Nch DDR write general purpose I/O /SIN general purpose I/O /SCK general purpose I/O /SOT Standby control (SPL=1) DDR read Standby control: Stop mode, watch mode, and SPL=1 *: Resources are input or output to or from pins having peripheral functions. 329 CHAPTER 18 LIN-UART 18.4 LIN-UART Registers The following figure shows the LIN-UART registers. ■ LIN-UART registers Figure 18.4-1 UART registers - LIN-UART2 registers Address: 0000D9H, 0000D8H bit 8 bit 7 bit 0 SMR2 (Serial Mode Register) 0000DBH, 0000DAH SSR2 (Serial Status Register) RDR2/TDR2 (Rx, Tx Data Register) 0000DDH, 0000DCH ESCR2 (Extended Status/Control Reg.) ECCR2 (Extended Comm. Contr. Reg.) 0000DFH, 0000DEH BGR21 (Baud Rate Generator Reg. 21) BGR20 (Baud Rate Generator Reg. 20) - LIN-UART3 registers Address: 007951H, 007950H 330 bit 15 SCR2 (Serial Control Register) bit 15 bit 8 bit 7 bit 0 SCR3 (Serial Control Register) SMR3 (Serial Mode Register) 007953H, 007952H SSR3 (Serial Status Register) RDR3/TDR3 (Rx, Tx Data Register) 007955H, 007954H ESCR3 (Extended Status/Control Reg.) ECCR3 (Extended Comm. Contr. Reg.) 007957H, 007956H BGR31 (Baud Rate Generator Reg. 31) BGR30 (Baud Rate Generator Reg. 30) CHAPTER 18 LIN-UART 18.4.1 Serial Control Register (SCR) This register specifies parity bits, selects the stop bit and data lengths, selects a frame data format in mode 1, clears the reception error flag, and specifies whether to enable transmission and reception. ■ Serial control register (SCR) Figure 18.4-2 Configuration of the serial control register (SCR) Address: SCR2: 0000D9H SCR3: 007951H 15 14 13 12 11 10 9 Initial value 00000000B 8 R/W R/W R/W R/W R/W W R/W R/W bit8 TXE Transmission enable 0 Disable Transmission 1 Enable Transmission bit9 RXE Reception enable 0 Disable Reception 1 Enable Reception bit10 Clear Reception errors CRE write read 0 ignored 1 Clear all reception errors (PE, FRE, ORE) read always returns 0 bit11 AD Address / Data bit 0 Data bit 1 Address bit bit12 CL Character (Data frame) Length 0 7 bits 1 8 bits bit13 SBL Stop bit length 0 1 stop bit 1 2 stop bits bit14 P Parity setting 0 Even Parity enabled 1 Odd Parity enabled bit15 PEN Parity Enable R/W : Readable and writable 0 Parity disabled W : Write only 1 Parity enabled : Initial value 331 CHAPTER 18 LIN-UART Table 18.4-1 Functions of each bit of control register (SCR) Bit name Function bit15 PEN: Parity enable bit This bit selects whether to add a parity bit during transmission in serial asynchronous mode or detect it during reception. Parity is only provided in mode 0 and in mode 2 if SSM of the ECCR is selected. This bit is fixed to 0 (no parity) in mode 3 (LIN). bit14 P: Parity selection bit When parity is provided and enabled this bit selects even (0) or odd (1) parity bit13 SBL: Stop bit length selection bit This bit selects the length of the stop bit of an asynchronous data frame or a synchronous frame if SSM of the ECCR is selected. This bit is fixed to 0 (1 stop bit) in mode 3 (LIN). bit12 CL: Data length selection bit This bit specifies the length of transmission or reception data. This bit is fixed to 1 (8 bits) in mode 2 and 3. bit11 AD: Address/Data selection bit This bit specifies the data format in multiprocessor mode 1. Writing to this bit is provided for a master CPU, reading from it for slave CPU. A 1 indicates an address frame, a 0 indicates a usual data frame. Note: Please read the hints about using this bit in Section "18.8 Notes on Using LIN-UART". bit10 CRE: Clear reception error flags bit This bit clears the FRE, ORE, and PE flag of the Serial Status Register (SSR). Writing a 1 to it clears the error flag. Writing a 0 has no effect. Reading from it always returns 0. Note: Clear reception error flag after exception stops. bit9 RXE: Reception enable bit This bit enables/disables LIN-UART reception. If this bit is set to 0, UART disables the reception of data frames. If this bit is set to 1, UART enables the reception of data frames. The LIN synch break detection in mode 3 remains unaffected. Note: If reception is disabled (RXE=0) during receiving, it is stopped immediately. In this case, data is not guaranteed. bit8 TXE: Transmission enable bit This bit enables/disables LIN-UART transmission. If this bit is set to 0, UART disables the transmission of data frames. If this bit is set to 1, UART enables the transmission of data frames. Note: If transmission is disabled (RXE=0) during transmitting, it is stopped immediately. In this case, data is not guaranteed. 332 CHAPTER 18 LIN-UART 18.4.2 Serial Mode Register (SMR) This register selects an operation mode and baud rate clock and specifies whether to enable output of serial data and clocks to the corresponding pin. ■ Serial mode register (SMR) Figure 18.4-3 Configuration of the serial mode register (SMR) 7 Address: SMR2: 0000D8H SMR3: 007950H 6 5 4 3 R/W R/W R/W R/W W 2 1 0 W R/W R/W Initial value 00000000B bit0 SOE Serial data output enable bit of LIN-UART 0 General purpose I/O port 1 LIN-UART serial data output pin bit1 SCKE Serial clock output enable bit of LIN-UART 0 General purpose I/O port or LIN-UART clock input pin 1 Serial clock output pin of LIN-UART bit2 UPCL LIN-UART programmable clear (Software Reset) write read 0 ignored 1 Reset UART always 0 bit3 Restart dedicated Reload Counter REST write read 0 ignored 1 Restart Counter always 0 bit4 EXT External Serial Clock Source enable 0 Use internal Baud Rate Generator (Reload Counter) 1 Use external Serial Clock Source bit5 OTO One-to-one external clock Input enable 0 Use ext. Clock with Baud Rate Generator (Reload C.) 1 Use external Clock as is bit6 bit7 MD0 MD1 Operation Mode Setting R/W : Readable and writable 0 0 Mode 0: Asynchronous normal W : Write only 1 0 Mode 1: Asynchronous Multiprocessor : Initial value 0 1 Mode 2: Synchronous 1 1 Mode 3: Asynchronous LIN 333 CHAPTER 18 LIN-UART Table 18.4-2 Bit function of the serial mode register (SMR) Bit name Function bit7 bit6 MD1 and MD0: Operation mode selection bits These two bits sets the UART operation mode. bit5 OTO: One-to-one external clock selection bit This bit sets an external clock directly to the LIN-UART’s serial clock. This function is used for operating mode 2 (synchronous) slave mode operation. bit4 EXT: External clock selection bit This bit executes internal or external clock source for the reload counter bit3 REST: Restart of transmission reload counter bit If a 1 is written to this bit the reload counter is restarted. Writing 0 to it has no effect. Reading from this bit always returns 0. bit2 UPCL: UART programmable clear bit (Software reset) Writing a 1 to this bit resets LIN-UART immediately. The register settings are preserved. Possible reception or transmission will cut off. All flags (TDRE, RDRF, LBD, PE, ORE, FRE) are cleared and the Reception Data Register (RDR) contains 00H. Writing 0 to this bit has no effect. Reading from it always returns 0. LIN-UART reset should be performed after disabling the interrupt enable bits. bit1 SCKE: Serial clock output enable • This bit controls the serial clock I/O ports. • When this bit is 0, SCKn pin operate as general purpose I/O port or serial clock input pin. When this bit is 1, the pin operates as serial clock output pin and outputs clock in operating mode 2 (synchronous). Note: When using SCKn pin as serial clock input (SCKE=0) pin, set the corresponding bit of DDR as input port. Also, select external clock (EXT = 1) using the external clock selection bit. Reference: When the SCKn pin is assigned to serial clock output (SCKE=1), it functions as the serial clock output pin regardless of the status of the general purpose I/O ports. bit0 SOE: Serial data output enable bit • This bit enables or disables the output of serial data. • When this bit is 0, SOTn pin operates as general purpose I/O pin. When this bit is 1, SOTn pin operates as serial data output pins (SOT). Reference: When the output of serial data is enabled (SOE=1), SOTn pin functions as serial data output pin (SOT) regardless of the status of general input-output ports. 334 CHAPTER 18 LIN-UART 18.4.3 Serial Status Register (SSR) This register checks the transmission and reception status and error status, and enables and disables the transmission and reception interrupts. ■ Serial status register (SSR) Figure 18.4-4 Configuration of the serial status register (SSR) Address: SSR2: 0000DBH SSR3: 007953H 15 14 13 12 R R R R 11 10 9 Initial value 00001000B 8 R R/W R/W R/W bit8 TIE Transmission Interrupt enable 0 Disables Transmission Interrupt 1 Enables Transmission Interrupt bit9 RIE Reception Interrupt enable 0 Disables Reception Interrupt 1 Enables Reception Interrupt bit10 BDS Bit direction setting 0 send / receive LSB first 1 send / receive MSB first bit11 TDRE Transmission data register empty 0 Transmission data register is full 1 Transmission data register is empty bit12 RDRF Reception data register full 0 Reception data register is empty 1 Reception data register is full bit13 FRE Framing error 0 No framing error occurred 1 A framing error occurred during reception bit14 ORE Overrun error 0 No overrun error occurred 1 An overrun error occurred during reception bit15 PE Parity error R/W : Readable and writable 0 No parity error occurred R : Flag is read only, write to it has no effect 1 A parity error occurred during reception : Initial value 335 CHAPTER 18 LIN-UART Table 18.4-3 Functions of each bit of status register (SSR) Bit name Function bit15 PE: Parity error flag bit • This bit is set to 1 when a parity error occurs during reception at PE=1 and is cleared when 1 is written to the CRE bit of the serial control register (SCR). • A reception interrupt request is output when this bit and the RIE bit are 1. • Data in the reception data register (RDR) is invalid when this flag is set. bit14 ORE: Overrun error flag bit • This bit is set to 1 when an overrun error occurs during reception and is cleared when 0 is written to the CRE bit of the serial control register (SCR). • A reception interrupt request is output when this bit and the RIE bit are 1. • Data in the reception data register (RDR) is invalid when this flag is set. bit13 FRE: Framing error flag bit • This bit is set to 1 when a framing error occurs during reception and is cleared when 0 is written to the CRE bit of the serial control register (SCR). • A reception interrupt request is output when this bit and the RIE bit are 1. • Data in the reception data register (RDR) is invalid when this flag is set. bit12 RDRF: Receive data full flag bit • This flag indicates the status of the reception data register (RDR). • This bit is set to 1 when reception data is loaded into RDR and can only be cleared to 0 when the reception data register (RDR) is read. • A reception interrupt request is output when this bit and the RIE bit are 1. bit11 TDRE: Transmission data empty flag bit • This flag indicates the status of the transmission data register (TDR). • This bit is cleared to 0 when transmission data is written to TDR and is set to 1 when data is loaded into the transmission shift register and transmission starts. • A transmission interrupt request is generated if both this bit and the TIE bit are 1. • If the LBR bit in the ECCR register is set to "1" while the TDRE bit is "1", then this bit once changes to "0". After the completion of LIN synch break generation, the TDRE bit changes back to "1". Note: This bit is set to 1 (TDR empty) as its initial value. bit10 BDS: Transfer direction selection bit • This bit selects whether to transfer serial data from the least significant bit (LSB first, BDS=0) or the most significant bit (MSB first, BDS=1). Note: The high-order and low-order sides of serial data are interchanged with each other during reading from or writing to the serial data register. If this bit is set to another value after the data is written to the RDR register, the data becomes invalid. This bit is fixed to 0 in mode 3 (LIN) bit9 RIE: Reception interrupt request enable bit • This bit enables/disables the reception interrupt. If any of the RDRF, PE, ORE and FRE bits is set and this bit is "1", then a reception interrupt is signaled to the interrupt controller. bit8 TIE: Transmission interrupt request enable bit • This bit enables or disables output of a request for transmission interrupt to the CPU. • A transmission interrupt request is output when this bit and the TDRE bit are 1. 336 CHAPTER 18 LIN-UART 18.4.4 Reception and Transmission Data Register (RDR/TDR) The reception data register (RDR) holds the received data. The transmission data register (TDR) holds the transmission data. Both RDR and TDR registers are located at the same address. ■ Reception and transmission data registers (RDR/TDR) Figure 18.4-5 Transmission and reception data registers (RDR/TDR) Address: RDR2/TDR2: 0000DAH RDR3/TDR3: 007952H 7 6 5 4 3 2 1 0 Initial value 00000000 B R/W R/W R/W R/W R/W R/W R/W R/W bit 7 to 0 R/W Data Registers Read Read from Reception Data Register Write Write to Transmission Data Register R/W: Readable and writable ● Reception: RDR is the register that contains reception data. The serial data signal transmitted to the SINn pin is converted in the shift register and stored there. When the data length is 7 bits, the uppermost bit (D7) contains 0. When reception is complete the data is stored in this register and the reception data full flag bit (SSR: RDRF) is set to 1. If a reception interrupt request is enabled at this point, a reception interrupt occurs. Read RDR when the RDRF bit of the status register (SSR) is 1. The RDRF bit is cleared automatically to 0 when RDR is read. Also the reception interrupt is cleared if it is enabled and no error has occurred. Data in RDR is invalid when a reception error occurs (SSR: PE, ORE, or FRE = 1). ● Transmission: When data to be transmitted is written to the transmission data register in transmission enable state, it is transferred to the transmission shift register, then converted to serial data, and transmitted from the serial data output terminal (SOTn pin). If the data length is 7 bits, the uppermost bit (D7) is not sent. When transmission data is written to this register, the transmission data empty flag bit (SSR: TDRE) is cleared to 0. When transfer to the transmission shift register is complete and starts, the bit is set to 1. When the TDRE bit is 1, the next part of transmission data can be written. If output transmission interrupt requests have been enabled, a transmission interrupt is generated. Write the next part of transmission data when a transmission interrupt is generated or the TDRE bit is 1. 337 CHAPTER 18 LIN-UART Note: TDR is a write-only register and RDR is a read-only register. These registers are located in the same address, so the read value is different from the write value. Therefore, instructions that perform a readmodify-write (RMW) operation, such as the INC/DEC instruction, cannot be used. 338 CHAPTER 18 LIN-UART 18.4.5 Extended Status/Control Register (ESCR) This register provides several LIN functions, direct access to the SINn and SOTn pin and setting for UART synchronous clock mode. ■ Extended status/control register (ESCR) Figure 18.4-6 Configuration of the extended status/control register (ESCR) Address: ESCR2: 0000DDH ESCR3: 007955H 15 14 13 12 11 10 9 Initial value 0 0 0 0 0 1 0 0B 8 R/W R/W R/W R/W R/W R/W R/W R/W bit8 SCES Sampling Clock Edge Selection (Mode 2) 0 Sampling on rising clock edge (normal) 1 Sampling on falling clock edge (inverted clock) bit9 CCO Continuous Clock Output (Mode 2) 0 Continuous Clock Output disabled 1 Continuous Clock Output enabled bit10 Serial Input / Output Pin Access SIOP write (if SOPE = "1") read 0 SOT3 is forced to "0" 1 SOT3 is forced to "1" reading the actual value of SIN3 bit11 SOPE Enable Serial Output pin direct Access 0 Serial Output pin direct access disable 1 Serial Output pin direct access enable bit12 bit 13 LBL0 LBL1 0 0 LIN break length 13 bit times LIN synch break length select 1 0 LIN break length 14 bit times 0 1 LIN break length 15 bit times 1 1 LIN break length 16 bit times bit14 LIN synch break detected flag LBD write read 0 Clear LIN synch break detected flag No LIN synch break detected 1 Ignored LIN synch break detected bit15 LBIE R/W X : : : Readable and writable Indeterninate Initial value LIN synch break detection Interrupt enable 0 LIN synch break interrupt disable 1 LIN synch break interrupt enable 339 CHAPTER 18 LIN-UART Table 18.4-4 Function of each bit of the extended status/control register (ESCR) Bit name Function bit15 LBIE: LIN synch break detection interrupt enable bit This bit enables a reception interrupt, if a LIN synch break was detected. bit14 LBD: LIN synch break detected flag This bit goes 1 if a LIN synch break was detected in operating mode 3. Writing a 0 to it clears this bit and the corresponding interrupt, if it is enabled. It is recommended to write "0" to the RXE bit in the SCR register before using this bit. Read-modify-write instructions always return 1. Note that this dose not indicate a LIN synch break. bit13 bit12 LBL1/0: LIN synch break length selection These two bits determine how many serial bit times the LIN synch break is generated by UART. Receiving a LIN synch break is always fixed to 11 bit times. bit11 SOPE: Serial Output pin direct access enable* Setting this bit to 1 enables the direct write to the SOTn pin, if SOE = 1 (SMR). * bit10 SIOP: Serial Input/Output Pin direct access * Normal read instructions always return the actual value of the SINn pin. Writing to it sets the bit value to the SOTn pin, if SOPE = 1. During a Read-Modify-Write instruction the bit returns the SOTn value in the read cycle. * bit9 CCO: Continuos Clock Output enable bit This bit enables a continuos serial clock at the SCKn pin if UART operates in master mode 2 (synchronous) and the SCKn pin is configured as a clock output. <Note> When CCO bit is “1”, use SSM bit of ECCR as setting to “1”. bit8 SCES: Serial clock edge selection bit This bit inverts the serial clock signal in operation mode 2 (synchronous communication). Receiving data is sampled at the falling edge of the internal clock. If the MS bit of the ECCR register is "0" (master mode) and the SCKE bit of the SMR register is "1" (clock output enabled), the output clock signal is also inverted. During operation mode 0,1,3, please set this bit to 0. *: See Table 18.4-5. Table 18.4-5 Description of the interaction of SOPE and SIOP 340 SOPE SIOP Writing to SIOP Reading from SIOP 0 R/W has no effect on SOTn, but holds the written value returns current value of SINn 1 R/W write “0” or “1” to SOTn returns current value of SINn 1 RMW reads current value of SOTn and write it back CHAPTER 18 LIN-UART 18.4.6 Extended Communication Control Register (ECCR) The extended communication control register provides bus idle recognition interrupt settings, synchronous clock settings, and the LIN break generation. ■ Extended communication control register (ECCR) Figure 18.4-7 Configuration of the extended communication control register (ECCR) 7 Address: ECCR2: 0000DCH ECCR3: 007954H 6 LBR - 5 4 3 2 MS SCDE SSM 1 0 RBI TBI W R/W R/W R/W R/W R Initial value 0 0 0 0 0 0 X XB R bit0 Transmission bus idle TBI * 0 Transmission is ongoing 1 no transmission activity bit1 Reception bus idle RBI * 0 Reception is ongoing 1 no reception activity bit2 Unued bit BIE * Reading value is undefined. Always write "0". bit3 SSM Synchronous start/stop bits in mode 2 0 No start/stop bits in synchronous mode 2 1 Enable start/stop bits in synchronous mode 2 bit4 SCDE Serial Clock Delay enable in mode 2 0 disable clock delay 1 enable clock delay bit5 MS Master / Slave function in mode 2 0 Master mode (generating serial clock) 1 Slave mode (receiving external serial clock) bit6 Generating LIN break LBR write 0 ignored 1 Generate LIN break read always read 0 bit7 0 R/W : R : Read only W : Write only X : Indeterminate : Undefined : Initial value - Read value is undefined/always write 0. Readable and writable * : Not used in mode2 when SSM = 0 341 CHAPTER 18 LIN-UART Table 18.4-6 Function of each bit of the extended communication control register (ECCR) Bit name Function bit7 - This bit is undefined. Always write "0". bit6 LBR: Generating LIN synch break bit Writing a 1 to this bit generates a LIN synch break of the length selected by the LBL0/1 bits of the ESCR, if operation mode 3 is selected. Setting to “0” in operation mode 0. bit5 MS: Master/Slave mode selection bit This bit selects master or slave mode of UART in synchronous mode 2. If master is selected UART generates the synchronous clock by itself. If slave mode is selected, UART receives external serial clock. This bit is fixed to "0" in operation mode 0, 1 and 3. Note: If slave mode is selected, the clock source must be external and set to “One-to-One” (SMR: SCKE = 0, EXT = 1, OTO = 1). bit4 SCDE: Serial clock delay enable bit If this bit is set the serial output clock is delayed as shown in Figure 18.7-4 if UART operates in master mode 2. bit3 SSM: Start/Stop bit mode enable This bit adds start and stop bits to the synchronous data format in operation mode 2. It is ignored in mode 0, 1, and 3. bit2 Unused bit Unused bit. Reading value is undefined. Always write to “φ” bit1 RBI: Reception bus idle flag bit This bit is “1” if there is no reception activity on the SINn pin and it is kept at "1". Do not use this bit in mode 2 when SSM=0. bit0 TBI: Transmission bus idle flag bit This bit is “1” if there is no transmission activity on the SOTn pin. Do not use this bit in mode 2 when SSM=0. 342 CHAPTER 18 LIN-UART 18.4.7 Baud Rate/Reload Counter Register 0 and 1 (BGR0/1) The baud rate/reload counter registers set the division ratio for the serial clock. Also the actual count of the transmission reload counter can be read. ■ Baud rate generator register (BGRn0/n1) Figure 18.4-8 Baud rate generator register (BGRn0/n1) Address: BGR20: 0000DEH BGR21: 0000DFH BGR30: 007956H BGR31: 007957H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 00000000B 00000000B - R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W bit 7 to 0 BGR7 to 0 write read Baud rate Generator Register n0 Write bit 7 to 0 of reload value to counter Read bit 7 to 0 of transmittion reload counter bit 14 to 8 BGR14 to 8 write read Baud rate Generator Register n1 Write bit 14 to 8 of reload value to counter Read bit 14 to 8 of transmittion reload counter bit 15 Undefined bit R/W : Readable and writable R : Read only - : Undefined returns "0" n = 2, 3 ■ Baud rate/reload counter register The baud rate/reload counter registers determine the division ratio for the serial clock. Both registers can be read or written via byte or word access. 343 CHAPTER 18 LIN-UART 18.5 LIN-UART Interrupts LIN-UART uses both reception and transmission interrupts. An interrupt request can be generated for either of the following causes: • Receive data is set in the Reception Data Register (RDR), or a reception error occurs. • Transmission data is transferred from the Transmission Data Register (TDR) to the transmission shift register and started. • A LIN break is detected The extended intelligent I-O service (EI2OS) and DMA is available for these interrupts. ■ LIN-UART interrupts Table 18.5-1 Interrupt control bits and interrupt causes of LIN-UART Reception/ transmission/ ICU Interrupt request flag bit Flag Register Operation mode 0 Reception 1 2 Interrupt cause How to clear the Interrupt Request 3 RDRF SSR m m m m receive data is written to RDR ORE SSR m m m m Overrun error FRE SSR m m * m Framing error PE SSR m x * x LBD ESCR x x m LIN synch break detected Transmission TDRE SSR Input Capture Unit ICP6/7 ICP6/7 x Interrupt cause enable bit SSR: RIE Receive data is read "1" is written to clear rec. error bit (SCR: CRE) Parity error ESCR: LBIE “0” is written to ESCR: LBD m m m m TDR empty SSR: TIE Write data to TDR ICS67 x x x m 1st falling edge of LIN synch field ICS67: ICE6/7 disable ICP6/7 temporary ICS67 x x x m 5th falling edge of LIN synch field ICS67: ICE6/7 disable ICP6/7 m: Used x: Unused *: Only available if ECCR/SSM = 1 ● Reception Interrupt If one of the following events occurs in reception mode, the corresponding flag bit of the Serial Status Register (SSR) is set to “1”: • Data reception is complete, i. e. the received data was transferred from the serial input shift register to the Reception Data Register (RDR) and data can be read: RDRF • Overrun error, i. e. RDRF = 1 and RDR was not read by the CPU and received next serial data: ORE 344 CHAPTER 18 LIN-UART • Framing error, i. e. a stop bit was expected, but a "0"-bit was received: FRE • Parity error, i. e. a wrong parity bit was detected: PE If at least one of these flag bits above go “1” and the reception interrupt is enabled (SSR: RIE = 1), a reception interrupt request is generated. If the Reception Data Register (RDR) is read, the RDRF flag is automatically cleared to “0”. Note that this is the only way to reset the RDRF flag. The error flags are cleared to “0”, if a “1” is written to the Clear Reception Error (CRE) flag bit of the Serial Control Register (SCR). The RDR contains only valid data if the RDRF flag is “1” and no error bits are set. Note, that the CRE flag is "write only" and by writing a "1" to it, it is internally held to "1" for one machine clock cycle. ● Transmission Interrupt If transmission data is transferred from the Transmission Data Register (TDR) to the transfer shift register and transfer is started, the Transmission Data Register Empty flag bit (TDRE) of the Serial Status Register (SSR) is set to “1”. In this case an interrupt request is generated, if the Transmission Interrupt Enable (TIE) bit of the SSR was set to “1” before. Note, that the initial value of TDRE (after hardware or software reset) is “1”. So an interrupt is generated immediately then, if the TIE flag is set to “1”. Also note, that the only way to reset the TDRE flag is writing data to the Transmission Data Register (TDR). ● LIN Synchronization Break Interrupt This paragraph is only relevant, if UART operates in mode 3 as a LIN slave. If the bus (serial input) goes “0” (dominant) for more than 11 bit times, the LIN Break Detected (LBD) flag bit of the Extended Status/Control Register (ESCR) is set to “1”. Note, that in this case after 9 bit times the reception error flags are set to “1”, therefore the RXE flag has to set to “0”, if only a LIN synch break detect is desired. The interrupt and the LBD flag are cleared after writing a "1" to the LBD flag. This has to be performed before input capture interrupt for LIN synch field. ● LIN Synchronization Field Edge Detection Interrupts This paragraph is only relevant, if UART operates in mode 3 as a LIN slave. After a LIN break detection the next falling edge of the reception bus is indicated by UART. Simultaneously an internal signal connected to the ICU6/7 is set to “1”. This signal is reset to “0” after the fifth falling edge of the LIN Synchronization Field. In both cases the ICU6/7 generates an interrupt, if “both edge detection” and the ICU6/7 interrupt are enabled. The difference of the ICU6/7 counter values is the serial clock multiplied by 8. Dividing it by 8 results in the new detected and calculated baud rate for the dedicated reload counter. This value - 1 has then to be written to the Baud Rate Generator Registers (BGR1/0).There is no need to restart the reload counter, because it is automatically reset if a falling edge of a start bit is detected. 345 CHAPTER 18 LIN-UART ■ LIN-UART interrupts and EI2OS Table 18.5-2 UART interrupt and EI2OS Interrupt control register Interrupt cause Interrupt number Vector table address Register name Address Lower Upper Bank EI2OS DMA channel number UART3 reception interrupt #37(25H) ICR13 0000BDH FFFF68H FFFF69H FFFF6AH *1 DRQ12 UART3 transmission interrupt #38(26H) ICR13 0000BDH FFFF64H FFFF65H FFFF66H *2 DRQ13 UART2 reception interrupt #39(27H) ICR14 0000BEH FFFF60H FFFF61H FFFF62H *1 DRQ14 UART2 transmission interrupt #40(28H) ICR14 0000BEH FFFF5CH FFFF5DH FFFF5EH *2 DRQ15 *1: Provided with a function that detects a UART reception error and stops EI2OS. *2: Usable when ICR12, ICR13 and ICR14 or interrupt causes that share an interrupt vector are not used. ■ UART EI2OS functions UART has a circuit for operating EI2OS, which can be started up for either reception or transmission interrupts. ● For Reception EI2OS can be used regardless of the status of other resources. ● For Transmission UART shares the interrupt registers with the UART reception interrupts. Therefore, EI2OS can be started up only when no UART reception interrupts are used. 346 CHAPTER 18 LIN-UART 18.5.1 Reception Interrupt Generation and Flag Set Timing The following are the reception interrupt causes: completion of reception (SSR: RDRF) and occurrence of a reception error (SSR: PE, ORE, or FRE). ■ Reception interrupt generation and flag set timing Generally a reception interrupt is generated, if the received data is complete (RDRF = 1) and the Reception Interrupt Enable (RIE) flag bit of the Serial Status Register (SSR) was set to “1”. This interrupt is generated if the first stop bit is detected in mode 0, 1, 2 (if SSM = 1), 3, or the last data bit was read in mode 2 (if SSM = 0). Note: If a reception error has occurred, the Reception Data Register (RDR) contains invalid data in each mode. Figure 18.5-1 Reception operation and flag set timing Receive data (mode 0/3) ST Receive data (mode 1) ST Receive data (mode 2) PE D0 D0 D0 D1 D2 .... D5 D6 D7/P SP ST D1 D2 .... D6 D7 A/D SP ST D2 .... D5 D6 D7 D0 D1 D4 *1 , FRE RDRF ORE *2 (if RDRF = "1") reception interrupt occurs *1: The PE flag will always remain "0" in mode 1 or 3. *2: ORE only occurs, if the reception data is not read by the CPU (RDRF = 1) and another data frame is read. ST: Start Bit SP: Stop Bit A/D: Mode 1 (multi processor) address/data selection bit Note: The example in Figure 18.5-1 does not show all possible reception options for mode 0 and 3. Here it is: "7p1" and "8N1" (p = "E" [even] or "O" [odd]). Figure 18.5-2 ORE set timing: Receive data RDRF ORE 347 CHAPTER 18 LIN-UART 18.5.2 Transmission Interrupt Generation and Flag Set Timing A transmission interrupt is generated when the transmission data is transferred from transmission data register (TDR) to transmission shift register and started. ■ Transmission interrupt generation and flag set timing A transmission interrupt is generated, when the next data to be sent is ready to be written to the Transmission Data Register (TDR), i. e. the TDR is empty, and the transmission interrupt is enabled by setting the Transmission Interrupt Enable (TIE) bit of the Serial Status Register (SSR) to “1”. The Transmission Data Register Empty (TDRE) flag bit of the SSR indicates an empty TDR. Because the TDRE bit is “read only”, it only can be cleared by writing data into TDR. The following figure demonstrates the transmission operation and flag set timing for the four modes of UART. Figure 18.5-3 Transmission operation and flag set timing transmission interrupt occurs transmission interrupt occurs Mode 0, 1 or 3: write to TDR TDRE serial output ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP AD AD transmission interrupt occurs transmission interrupt occurs Mode 2 (SSM = 0): write to TDR TDRE serial output ST: Start bit D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D0 ... D7: data bits P: Parity SP: Stop bit AD: Address/data selection bit (mode1) Note: The example in Figure 18.5-3 does not show all possible transmission options for mode 0. Here it is: "8p1" (p = "E" [even] or "O" [odd]). Parity is not provided in mode 3 or 2, if SSM = 0. ■ Transmission interrupt request generation timing If the TDRE flag is set to "1" when a transmission interrupt is enabled (SSR: TIE=1), transmission interrupt request is generated. 348 CHAPTER 18 LIN-UART Note: A transmission completion interrupt is generated immediately after the transmission interrupt is enabled (TIE=1) because the TDRE bit is set to 1 as its initial value. TDRE is a read-only bit that can be cleared only by writing new data to the output data register (TDR). Carefully specify the transmission interrupt enable timing. 349 CHAPTER 18 LIN-UART 18.6 LIN-UART Baud Rates One of the following can be selected for the UART serial clock source: • Dedicated baud rate generator (Reload Counter) • External clock as it is (clock input to the SCKn pin) • External clock connected to the baud rate generator (Reload Counter) ■ UART baud rate selection The baud rate selection circuit is designed as shown below. One of the following three types of baud rates can be selected: ● Baud rates determined using the dedicated baud rate generator (reload counter) UART has two independent internal reload counters for transmission and reception serial clock. The baud rate can be selected via the 15-bit reload value determined by the Baud Rate Generator Register 0 and 1 (BGR0/1). The reload counter divides the machine clock by the value set in the Baud Rate Generator Register 0 and 1. ● Baud rates determined using external clock (one-to-one mode) The clock input from UART clock pulse input pins (SCK) is used as it is (synchronous). Any baud rate less than the machine clock divided by 4 and is divisible can be set externally. ● Baud rates determined using the dedicated baud rate generator with external clock An external clock source can also be connected internally to the reload counter. In this mode it is used instead of the internal machine clock. This was designed to use quartz oscillators with special frequencies and having the possibility to divide them. 350 CHAPTER 18 LIN-UART Figure 18.6-1 Baud rate selection circuit (reload counter) REST Start bit falling edge detected Reload Value: v Rxc = 0? Reception 15-bit Reload Counter set FF Reload Rxc = v/2? 0 Reception Clock reset 1 Reload Value: v Machine clock 0 SCKn (external clock input) EXT Txc = 0? Transmission 15-bit Reload Counter 1 Count Value: Txc set Txc = v/2? OTO FF Reload 0 reset 1 Transmission Clock Internal data bus EXT REST OTO SMRn register BGR14 BGR13 BGR12 BGR11 BGR10 BGR9 BGR8 BGRn1 register BGR7 BGR6 BGR5 BGR4 BGR3 BGR2 BGR1 BGR0 BGRn0 register n = 0, 1, 2, 3, 4 351 CHAPTER 18 LIN-UART 18.6.1 Setting the Baud Rate This section describes how the baud rates are set and the resulting serial clock frequency is calculated. ■ Calculating the baud rate The both 15-bit reload counters are programmed by the baud rate generator registers 1,0 (BGR). The following calculation formula should be used to set the desired baud rate: Reload Value: v = [Φ / b] - 1, where Φ is the machine clock, b the baud rate and [] gaussian brackets (mathematical rounding function). ● Example of calculation If the CPU clock is 16 MHz and the desired baud rate is 19200 bps baud then the reload value v is: v = [16*106 / 19200] - 1 = 832 The exact baud rate can then be recalculated: bexact = Φ / (v + 1), here it is: 16*106 / 833 = 19207.6831 Note: Setting the reload value to 0 stops the reload counter. For this reason the minimum division ratio is 2. For asynchronous communication, the reload value must be greater than equal to 4 because 5 times over-sampling is performed internally. 352 CHAPTER 18 LIN-UART ■ Suggested division ratios for different machine speeds and baud rates The following settings are suggested for different MCU clock speeds and baud rates: Table 18.6-1 Suggested baud rates and reload values at different machine speeds. 8 MHz Baud rate value 10 MHz dev. value 16 MHz dev. value 20 MHz dev. value 24 MHz dev. value dev. 4M - - - - - - 4 0 5 0 2M - - 4 0 7 0 9 0 11 0 1M 7 0 9 0 15 0 19 0 23 0 500000 15 0 19 0 31 0 39 0 47 0 460800 - - - - - - - - 51 -0.16 250000 31 0 39 0 63 0 79 0 95 0 230400 - - - - - - - - 103 -0.16 153600 51 -0.16 64 -0.16 103 -0.16 129 -0.16 155 -0.16 125000 63 0 79 0 127 0 159 0 191 0 115200 68 -0.64 86 0.22 138 0.08 173 0.22 207 -0.16 76800 103 -0.16 129 -0.16 207 -0.16 259 -0.16 311 -0.16 57600 138 0.08 173 0.22 277 0.08 346 -0.06 416 0.08 38400 207 -0.16 259 -0.16 416 0.08 520 0.03 624 0 28800 277 0.08 346 <0.01 554 -0.01 693 -0.06 832 -0.03 19200 416 0.08 520 0.03 832 -0.03 1041 0.03 1249 0 10417 767 <0.01 959 <0.01 1535 <0.01 1919 <0.01 2303 <0.01 9600 832 0.04 1041 0.03 1666 0.02 2083 0.03 2499 0 7200 1110 <0.01 1388 <0.01 2221 <0.01 2777 <0.01 3332 <0.01 4800 1666 0.02 2082 -0.02 3332 <0.01 4166 <0.01 4999 0 2400 3332 <0.01 4166 <0.01 6666 <0.01 8332 <0.01 9999 0 1200 6666 <0.01 8334 0.02 13332 <0.01 16666 <0.01 19999 0 600 13332 <0.01 16666 <0.01 26666 <0.01 - - - - 300 26666 <0.01 - - - - - - - - Note: 1) Deviations are given in%. 2) Maximum Synchronous Baud Rate: MCU-Clock div. by 5. 353 CHAPTER 18 LIN-UART ■ Using external clock If the EXT bit of the SMR is set, an external clock is selected, which has to be connected to the SCKn pin. The external clock is used in the same way as the machine clock to the baud rate reload counter. If One-to-one External Clock Input Mode (SMR: OTO) is selected the SCKn signal is directly connected to the UART serial clock inputs. This is needed for the UART synchronous mode 2 operating as slave device. Note, that in any case the resulting clock signal is synchronized to the machine clock in the UART module. This means that indivisible clock rates will result in phase unstable signals. ■ Counting example Assume the reload value is 832. The Figure 18.6-2 demonstrates the behavior of both Reload Counters: Figure 18.6-2 Counting example of the reload counters Transmission/ Reception Clock Reload Count 001 000 832 831 830 829 828 827 413 412 411 410 reload count value Transmission/ Reception Clock Reload Count 417 416 415 414 Note: The falling edge of the Serial Clock Signal always occurs after | (v + 1) / 2 |. 354 CHAPTER 18 LIN-UART 18.6.2 Restarting the Reload Counter The Reload Counters can be restarted of the following reasons: Transmission and reception reload counter: • Global MCU reset • UART programmable clear (SMR:UPCL bit) • User programmable restart (SMR: REST bit) Reception reload counter: • Start bit falling edge detection in asynchronous mode ■ Programmable restart If the REST bit of the Serial Mode Register (SMR) is set by the user, both Reload Counters are restarted at the next clock cycle. This feature is intended to use the Transmission Reload Counter as a small timer. The following figure illustrates a possible usage of this feature (assume that the reload value is 100.) Figure 18.6-3 Reload counter restart example MCU Clock Reload Counter Clock Outputs REST Reload Value 37 36 35 100 99 98 97 96 95 94 93 92 91 90 89 88 87 Read BGR0/1 Data Bus 90 : don’t care In this example the number of MCU clock cycles (cyc) after REST is then: cyc = v - c + 1 = 100 - 90 + 1 = 11, where v is the reload value and c is the read counter value. Note: If UART is reset by setting SMR:UPCL, the Reload Counters will restart too. • Automatic restart In asynchronous UART mode if a falling edge of a start bit is detected the Reception Reload Counter is restarted. This is intended to synchronize the serial input shifter to the incoming serial data stream. 355 CHAPTER 18 LIN-UART ● Counter clear The reload value of the baud rate generator register (BGR1 and BGR1) and the reload counter are cleared to 00H by a reset, and the reload counter stops. The counter is temporary cleared to 00H by LIN-UART (writing 1 to UPCL bit in SMR register), but the reload counter restarts because the reload value is maintained. The setting (writing 1 to REST bit in SMR register) dose not clear the counter to 00H and restarts it. 356 CHAPTER 18 LIN-UART 18.7 Operation of LIN-UART UART operates in operation mode 0 for normal bidirectional serial communication, in mode 2 and 3 in bidirectional communication as master or slave, and in mode 1 as master or slave in multiprocessor communication. ■ Operation of UART ● Operation modes There are four UART operation modes: modes 0 to 3. As listed in Table 18.7-1, an operation mode can be selected according to the communication method. Table 18.7-1 UART operation mode Data length Operation mode parity disabled 0 normal mode 7 or 8 1 multiprocessor 7 or 8 + 1*2 2 normal mode 8 3 LIN mode 8 parity enabled - - Synchronization of mode Length of stop bit data bit direction *1 asynchronous 1 or 2 L/M asynchronous 1 or 2 L/M synchronous 0, 1 or 2 L/M asynchronous 1 L *1: means the data bit transfer format: LSB or MSB first *2: "+1" means the indicator bit of the address/data selection in the multiprocessor mode, instead of parity. Note: Mode 1 operation is supported both for master or slave operation of UART in a master-slave connection system. In Mode 3 the UART function is locked to 8N1-Format, LSB first. If the mode is changed, UART cuts off all possible transmission or reception and awaits then new action. ■ Inter-CPU connection method External Clock One-to-one connection (normal mode) and master-slave connection (multiprocessor mode) can be selected. For either connection method, the data length, whether to enable parity, and the synchronization method must be common to all CPUs. Select an operation mode as follows: • In the one-to-one connection method, operation mode 0 or 2 must be used in the two CPUs. Select operation mode 0 for asynchronous transfer mode and operation mode 2 for synchronous transfer mode. Note that one CPU has to set to the master and the other to the slave in synchronous mode 2. • Select operation mode 1 for the master-slave connection method and use it either for the master or slave system. 357 CHAPTER 18 LIN-UART ■ Synchronization methods In asynchronous operation UART reception clock is automatically synchronized to the falling edge of a received start bit. In synchronous mode the synchronization is performed either by the clock signal of the master device or by UART itself if operating as master. ■ Signal mode UART can treat data only in non-return to zero (NRZ) format. ■ Operation enable bit UART controls both transmission and reception using the operation enable bit for transmission (SCR: TXE) and reception (SCR: RXE). • If reception operation is disabled during reception (data is input to the reception shift register), finish frame reception and read the received data of the reception data register (RDR). Then stop the reception operation. • If the transmission operation is disabled during transmission (data is output from the transmission shift register), wait until there is no data in the transmission data register (TDR) before stopping the transmission operation. 358 CHAPTER 18 LIN-UART 18.7.1 Operation in Asynchronous Mode (Op. Modes 0 and 1) When UART is used in operation mode 0 (normal mode) or operation mode 1 (multiprocessor mode), the asynchronous transfer mode is selected. ■ Operation in asynchronous mode ● Transfer data format Generally each data transfer in the asynchronous mode operation begins with the start bit (low-level on bus) and ends with at least one stop bit (high-level). The direction of the bit stream (LSB first or MSB first) is determined by the BDS bit of the Serial Status Register (SSR). The parity bit (if enabled) is always placed between the last data bit and the (first) stop bit. In operation mode 0 the length of the data frame can be 7 or 8 bits, with or without parity, and 1 or 2 stop bits. In operation mode 1 the length of the data frame can be 7 or 8 bits with a following address-/data-selection bit instead of a parity bit. 1 or 2 stop bits can be selected. The calculation formula for the bit length of a transfer frame is: Length = 1 + d + p + s (d = number of data bits [7 or 8], p = parity [0 or 1], s = number of stop bits [1 or 2] Figure 18.7-1 Transfer data format (operation modes 0 and 1)) *1 *2 Operation mode 0 ST D0 D1 D2 D3 D4 D5 D6 D7/P SP SP Operation mode 1 ST D0 D1 D2 D3 D4 D5 D6 D7 A/D SP *1: D7 (bit 7) if parity is not provided and data length is 8 bits P (parity) if parity is provided and data length is 7 bits *2: only if SBL bit of SCR is set to1 ST: Start Bit SP: Stop Bit A/D: Address/data selection bit in mode 1 (multiprocessor mode) Note: If BDS bit of the Serial Status Register (SSR) is set to “1” (MSB first), the bit stream processes as: D7, D6, ..., D1, D0, (P). During Reception both stop bits are detected, if selected. But the Reception data register full (RDRF) flag will go “1” at the first stop bit. The bus idle flag (RBI of ECCR) goes “1” after the second stop bit if no further start bit is detected. (The second stop bit belongs to “bus activity”, although it is just mark level.) ● Transmission operation If the Transmission Data Register Empty (TDRE) flag bit of the Serial Status Register (SSR) is “1”, transmission data is allowed to be written to the Transmission Data Register (TDR). When data is written, 359 CHAPTER 18 LIN-UART the TDRE flag goes “0”. If the transmission operation is enabled by the TXE-Bit (“1”) of the Serial Control Register (SCR), the data is written next to the transmission shift register and the transmission starts at the next clock cycle of the serial clock, beginning with the start bit. Thereby the TDRE flag goes “1”, so that new data can be written to the TDR. If transmission interrupt is enabled (TIE = 1), the interrupt is generated by the TDRE flag. Note, that the initial value of the TDRE flag is “1”, so that in this case if TIE is set to “1” an interrupt will occur immediately. When the character length is set to 7 bits (CL=0), the unused bit of the TDR is always the MSB, independently from the bit direction setting in the BDS bit (LSB first or MSB first). ● Reception operation Reception operation is performed when it is enabled by the Reception Enable (RXE) flag bit of the SCR. If a start bit is detected, a data frame is received according to the format specified by the SCR. In case of errors, the corresponding error flags are set (PE, ORE, FRE). After the reception of the data frame the data is transferred from the serial shift register to the Reception Data Register (RDR) and the Receive Data Register Full (RDRF) flag bit of the SSR is set. The data then has to be read by the CPU. By doing so, the RDRF flag is cleared. If reception interrupt is enabled (RIE = 1), the interrupt is simply generated by the RDRF. When the character length is set to 7 bits (CL=0), the unused bit of the RDR is always the MSB, independently from the bit direction setting in the BDS bit (LSB first or MSB first). Note: Only when the RDRF flag bit is set and no errors have occurred the Reception Data Register (RDR) contains valid data. ● Used clock Use the internal clock or external clock. Select the baud rate generator (SMR: EXT = 0 or 1, OTO = 0) for desired baud rate. ● Stop bit, error detection, and parity: Number of stop bit, 1 or 2 can be specified by the SBL bit of the SCR register. When receiving and 2-bit is specified as the stop bit, the second stop bit is checked in addition to the first stop bit. The RBI (bus idle) flag is set after the second stop bit. However the RDRF flag is set when the first stop bit is received. In mode 0, parity error, overrun error and framing error are checked. In mode 1, parity check is not supported and overrun error and framing error are checked. The PEN bit of the SCR register enables/disables the parity bit and the P bit specifies even or odd parity in mode 0. 360 CHAPTER 18 LIN-UART 18.7.2 Operation in Synchronous Mode (Operation Mode 2) The clock synchronous transfer method is used for UART operation mode 2 (normal mode). ■ Operation in synchronous mode (operation mode 2) ● Transfer data format In the synchronous mode, 8-bit data is transferred without start or stop bits if the SSM bit of the Extended Communication Control Register (ECCR) is 0. The figure below illustrates the data format during a transmission in the synchronous operation mode. Figure 18.7-2 Transfer data format (operation mode 2) Reception or transfer data (ECCR:SSM=0, SCR:PEN=0) D0 D1 D2 D3 D4 D5 D6 D7 Reception or transfer data (ECCR:SSM=1, SCR:PEN=0) ST D0 D1 D2 D3 D4 D5 D6 D7 SP SP Reception or transfer data (ECCR:SSM=1, SCR:PEN=1) ST D0 D1 D2 D3 D4 D5 D6 D7 P * * SP SP *: only if SBL bit of SCR is set to ST: Start Bit SP: Stop Bit P : Parity Bit ● Clock inversion and start/stop bits in mode 2 If the SCES bit of the Extended Status/Control Register (ESCR) is set the serial clock is inverted. Therefore in slave mode UART samples the data bits at the falling edge of the received serial clock. Note, that in master mode if SCES is set the clock signal’s mark level is “0”. If the SSM bit of the Extended Communication Control Register (ECCR) is set the data format gets additional start and stop bits like in asynchronous mode. 361 CHAPTER 18 LIN-UART Figure 18.7-3 Transfer data format with clock inversion mark level reception or transmission clock (SCES = 0, CCO = 0): reception or transmission clock (SCES = 1, CCO = 0): mark level data stream (SSM = 1) (here: no parity, 1 stop bit) ST SP data frame ● Clock supply: In operation mode 2, the number of clock cycles for the clock signal must be the same as the number of bits for the data including start and stop bits. If the MS bit of the ECCR register is "0" (master mode) and the SCKE bit of the SMR register is "1" (clock output enabled), the consistent clock cycles are generated automatically. If the MS bit of the ECCR register is "1" (slave mode), make sure that correct clock cycles are generated by the other communication device. While there is no communication, the clock signal must be kept at "1" as the mark level. If the SCDE bit of the ECCR register is "1", the clock output signal is delayed by the half of the serial clock cycle as shown in Figure 18.7-4. This operation is prepared for communication devices which use the falling edge of the serial clock signal for the data sampling. Figure 18.7-4 Delayed transmitting clock signal(SCDE=1) Transmission data writing Reception data sample edge (SCES = 0) Transmitting or receiving clock (normal) Mark level Mark level Transmitting clock (SCDE = 1) Transmission and reception data Mark level 0 LSB 1 1 0 1 Data 0 0 1 MSB If the SCES bit of the ESCR register is "1", the serial clock signal is inverted. Receiving data is sampled at the falling edge of the serial clock. If the MS bit of the ECCR register is "0" (master mode) and the SCKE bit of the SMR register is "1" (clock output enabled), the output clock signal is also inverted. While there is no communication, the clock signal must be kept at "0" as the mark level. If the CCO bit of the ESCR register is "1", the serial clock is signaled even while there is no data communication. Therefore it is recommended to specify the start/stop bits as shown in Figure 18.7-5. 362 CHAPTER 18 LIN-UART Figure 18.7-5 Continuous clock output in mode 2 reception or transmission clock (SCES = 0, CCO = 1): reception or transmission clock (SCES = 1, CCO = 1): data stream (SSM = 1) (here: no parity, 1 stop bit) ST SP data frame ● Error detection: If no start/stop bits are selected (ECCR: SSM = 0) only overrun errors are detected. ● Communication: For initialization of the synchronous mode, following settings have to be done: Baud rate generator registers (BGR0/1): Set the desired reload value for the dedicated baud rate reload counter. Serial mode control register (SMR): MD1, MD0: “10B” (Mode 2) SCKE: “1” for the dedicated Baud Rate Reload Counter “0” for external clock input SOE: “1” for transmission and reception “0” for reception only Serial control register (SCR): RXE, TXE: set one or both of these flags to "1" A/D: no Address/Data selection - don’t care CL: automatically fixed to 8-bit data : don’t care CRE: “1” (to clear receive error flags) -- when SSM=0 (default): PEN, P, SBL: don’t care. -- when SSM=1: PEN: “1” if parity bit is added/detected, “0” if not P: “0” for even parity, “1” odd parity SBL: "1" for 2 stop bits, "0" for 1 stop bit. Serial status register (SSR): BDS: “0” for LSB first, “1” for MSB first RIE: “1” if interrupts are used; “0” reception interrupts are disabled. TIE: “1” if interrupts are used; “0” transmission interrupts are disabled. Extended communication control register (ECCR): SSM: “0” if no start/stop bits are desired (normal); “1” for adding start/stop bits (special) MS: “0” for master mode (UART generates the serial clock); “1” for slave mode (UART receives serial clock from the master device) 363 CHAPTER 18 LIN-UART 18.7.3 Operation with LIN Function (Operation Mode 3) UART can be used either as LIN-Master or LIN-Slave. For this LIN function a special mode is provided. Setting the UART to mode 3 configures the data format to 8N1-LSBfirst format. ■ Operation in asynchronous LIN mode (operation mode 3) ● UART as LIN master In LIN master mode the master determines the baud rate of the whole sub bus, therefore slaves devices have to synchronize to the master. Therefore the desired baud rate remains fixed in master operation after initialization. Writing a “1” into the LBR bit of the Extended/Communication Control Register (ECCR) generates a 13 16 bit time low-level on the SOT pin, which is the LIN synchronization break and the start of a LIN message. Thereby the TDRE flag of the Serial Status Register (SSR) goes “0” and is reset to “1” after the break, and generates a transmission interrupt for the CPU (if TIE of SSR is “1”). The length of the Synchronization break to be sent can be determined by the LBL1/0 bits of the ESCR as follows: Table 18.7-2 LIN break length LBL1 LBL0 Length of Break 0 0 13 Bit times 1 0 14 Bit times 0 1 15 Bit times 1 1 16 Bit times The Synch Field is sent as byte data of 0x55 after the LIN break. To prevent a transmission interrupt, the 0x55 can be written to the TDR just after writing the “1” to the LBR bit, although the TDRE flag is “0”. The internal transmission shifter waits until the LIN break has finished and shifts the TDR value out afterwards. In this case no interrupt is generated after the LIN break and before the start bit. ● UART as LIN slave In LIN slave mode UART has to synchronize to the master’s baud rate. If Reception is disabled (RXE = 0) but LIN break Interrupt is enabled (LBIE = 1) UART will generate a reception interrupt, if a synchronization break from the LIN master is detected, and indicates it with the LBD flag of the ESCR. Writing a “0” to this bit clears the reception interrupt request. The LIN slave may need to calculate the baud rate from the synch field. In this case, the time between the first falling edge to the fifth falling edge of the synch field is measured by the input capture module. For this purpose, the input capture module is connected to the LIN-UART with an internal signal. This internal signal changes from "0" to "1" at the first falling edge. Also the input signal from the LIN-UART should be selected. The time measured by the input capture module represents 8 times of the baud rate clock cycle. 364 CHAPTER 18 LIN-UART Therefore, baud rate setting value is summarized as follows: without timer overflow : BGR value = (b-a)/8 with timer overflow : BGR value = (max + b-a)/8 where max is the timer maximum value at the overflow occurs. where a is the value of the ICU counter register after the first Interrupt where b is the value of the ICU counter register after the second Interrupt For the correspondence between other UARTs and ICUs, see "12.3 16-bit Free-running Timer". LIN Synch Break Detection Interrupt and Flags If a LIN Synch synchronization break is detected in the slave mode, the LIN Break Detected (LBD) Flag of the ESCR is set to “1”. This causes an interrupt, if the LIN Break Interrupt Enable (LBIE) bit is set LIN synch break detection and flag set timing. Serial clock 0 cycle# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Serial clock Serial Input (LIN bus) FRE (RXE=1) LBD (RXE=0) Reception interrupt occurs, if RXE=1 Reception interrupt occurs, if RXE=0 The figure above demonstrates the LIN synch break detection and flag set timing. Note, that if reception is enabled (RXE = 1) and reception interrupt is enabled (RIE = 1) the Reception Data Framing Error (FRE) flag bit of the SSR will cause a reception interrupt 2 bit times (“8N1”) earlier than the LIN break interrupt, so it is recommended to turn off RXE, if a LIN break is expected. LBD is only supported in operation mode 3. The Figure 18.7-6 shows a typical start of a LIN message frame and the behavior of the UART. 365 CHAPTER 18 LIN-UART Figure 18.7-6 UART behavior as slave in LIN mode Serial clock Serial Input (LIN bus) LBR cleared by CPU LBD Internal ICU Signal Synch break (e. g. 14 Tbit) Synch field ● LIN bus timing Figure 18.7-7 LIN bus timing and UART signals old serial clock no clock used (calibration frame) new (calibrated) serial clock ICU count LIN bus (SIN) RXE LBD (IRQ0) LBIE Internal Signal to ICU IRQ from ICU RDRF (IRQ0) RIE Read RDR by CPU Reception Interrupt enable LIN break begins LIN break detected and Interrupt IRQ cleared by CPU (LBD -> 0) IRQ from ICU IRQ cleared: Begin of Input Capture IRQ from ICU IRQ cleared: Calculate & set new baud rate LBIE disable Reception enable Edge of Start bit of Identifier byte Byte read in RDR RDR read by CPU 366 CHAPTER 18 LIN-UART 18.7.4 Direct Access to Serial Pins UART allows the user to directly access to the transmission pin (SOTn) or the reception pin (SINn). ■ UART direct pin access The UART provides the ability for the software to access directly to serial input or output pin. The software can always monitor the incoming serial data by reading the SIOP bit of the ESCR. If setting the Serial Output Pin direct access Enable (SOPE) bit of the ESCR the software can force the SOTn pin to a desired value. Note, that this access is only possible, if the transmission shift register is empty (i. e. no transmission activity). In LIN mode this function can be used for reading back the own transmission and is used for error handling if something is physically wrong with the single-wire LIN-bus. Notes: • Write the desired value to the SIOP pin before enabling the output pin access to prevent undesired output level, because SIOP holds the last written value. • During a Read-Modify-Write operation the SIOP bit returns the actual value of the SOTn pin in the read cycle instead of the value of SINn during a normal read instruction. 367 CHAPTER 18 LIN-UART 18.7.5 Bidirectional Communication Function (Normal Mode) In operation mode 0 or 2, normal serial bidirectional communication is available. Select operation mode 0 for asynchronous communication and operation mode 2 for synchronous communication. ■ Bidirectional communication function The settings shown in Figure 18.7-8 are required to operate UART in normal mode (operation mode 0 or 2). Figure 18.7-8 Settings for UART operation mode 0 and 2 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SCRn, SMRn PEN P SBL CL AD CRE RXE TXE MD1 MD0 OTO EXT REST UPCLSCKE SOE Mode 0 Mode 2 + X X SSRn, TDRn /RDRn PE ORE FRE RDRFTDRE BDS RIE 0 0 0 1 TIE 0 0 0 0 0 0 0 0 1 Set conversion data (during writing) Retain reception data (during reading) Mode 0 Mode 2 ESCRn, ECCRn LBIE LBD LBL1 LBL0 SOPE SIOP CCO SCES Mode 0 Mode 2 X X X X X X X X 0 LBR 0 0 X MS SCDE SSM X X : Bit used X : Bit not used 1 : Set 1 0 : Set 0 : Bit used if SSM = 1 (Synchronous start-/stop-bit mode) + : Bit automatically set to correct value X RBI TBI 0 0 n = 2,3 ● Inter-CPU connection As shown in Figure 18.7-9, interconnect two CPUs in UART mode 2 Figure 18.7-9 Connection example of UART mode 2 bidirectional communication SOT SOT SIN SIN SCK CPU-1 (Master) 368 Output Input SCK CPU-2 (Slave) CHAPTER 18 LIN-UART ● Procedure for communication Communication starts at any timing transmission from side when the transmission data is provided. When the transmission data is received at reception side, ANS (per byte in an example) is returned periodically. Figure 18.7-10 shows an example of bidirectional communication flowchart. Figure 18.7-10 Example of master-slave communication flowchart (Transmission side) (Reception side) Start Start Operating mode setting (either 0 or 2) Operating mode setting (match the transmission side) Set 1-byte data to TDR and communicate With reception data NO YES With reception data Read reception data and process NO YES Read reception data and process 1-byte data transmission (ANS) 369 CHAPTER 18 LIN-UART 18.7.6 Master-Slave Communication Function (Multiprocessor Mode) UART communication with multiple CPUs connected in master-slave mode is available for both master or slave systems. ■ Master-slave communication function The settings shown in Figure 18.7-11 are required to operate UART in multiprocessor mode (operation mode 1). Figure 18.7-11 Settings for UART operation mode 1 SCRn, SMRn Mode 1 SSRn, TDRn /RDRn Mode 1 PEN P + X SBL CL AD CRE RXE TXE MD1 MD0 OTO EXT REST UPCLSCKE SOE 0 0 PE ORE FRE RDRFTDRE BDS RIE TIE 1 0 0 0 0 1 Set conversion data (during writing) Retain reception data (during reading) X ESCRn, ECCRn Mode 1 X 1 0 + bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 LBIE LBD LBL1 LBL0 SOPE SIOP CCO SCES X X X X 0 0 LBR X MS SCDE SSM X : Bit used : Bit not used : Set 1 : Set 0 : Bit automatically set to correct value X X RBI TBI 0 n = 2,3 ● Inter-CPU connection As shown in Figure 18.7-12, a communication system consists of one master CPU and multiple slave CPUs connected to two communication lines. UART can be used for the master or slave CPU. Figure 18.7-12 Connection example of UART master-slave communication SOT1 SIN1 Master CPU SOT SIN Slave CPU #0 370 SOT SIN Slave CPU #1 CHAPTER 18 LIN-UART ● Function selection Select the operation mode and data transfer mode for master-slave communication as shown in Table 18.73. Table 18.7-3 Selection of the master-slave communication function Operation mode Data Master CPU Address transmission and reception Data transmission and reception Mode 1 (transmit/ receive ADbit) Parity Synchronization method None Asynchronous Slave CPU Mode 1 (transmit/receive AD-bit) Stop bit AD="1" + 7or 8-bit address 1 or 2 bits Bit direction LSB or MSB first AD="0" + 7or 8-bit data Communication procedure When the master CPU transmits address data, communication starts. The A/D bit in the address data is set to 1, and the communication destination slave CPU is selected. Each slave CPU checks the address data using a program. When the address data indicates the address assigned to a slave CPU, the slave CPU communicates with the master CPU. Figure 18.7-13 shows a flowchart of master-slave communication (multiprocessor mode) 371 CHAPTER 18 LIN-UART Figure 18.7-13 Master-slave communication flowchart (Master CPU) (Slave CPU) Start Start Set operation mode 1 Set operation mode 1 Set SIN pin as the serial data input pin. Set SOT pin as the serial data output pin. Set SIN pin as the serial data input pin. Set SOT pin as the serial data output pin. Set 7 or 8 data bits. Set 1 or 2 stop bits. Set 7 or 8 data bits. Set 1 or 2 stop bits. Set “1” in AD bit Set TXE = RXE = 1. Set TXE = RXE = 1. Receive Byte Send Slave Address Is AD bit = 1 ? NO YES Does Slave Address match? Set “0” in AD bit. NO YES Communicate with slave CPU Is communication complete? Communicate with master CPU NO YES Communicate with another slave CPU? YES NO YES Set TXE = RXE = 0. End 372 Is communication complete? NO CHAPTER 18 LIN-UART 18.7.7 LIN Communication Function UART communication with LIN devices is available for both LIN master or LIN slave systems. ■ LIN-master-slave communication function The settings shown in the figure below are required to operate UART in LIN communication mode (operation mode 3). Figure 18.7-14 Settings for UART in operation mode 3 (LIN) SCRn, SMRn Mode 3 SSRn, TDRn/RDRn Mode 3 ESCRx, ECCRx PEN P SBL CL AD CRE RXE TXE MD1 MD0 OTO EXT REST UPCL SCKE SOE + x + + x 1 PE ORE FRE RDRF TDRE BDS RIE TIE x 1 0 0 0 0 1 Set conversion data (during writing) Retain reception data (during reading) + LBIE LBD LBL1 LBL0 SOPE SIOP CCO SCES Mode 3 x 1 0 + 0 0 0 LBR MS SCDE SSM x : Bit used : Bit not used : Set 1 : Set 0 : Bit automatically set to correct value x x RBI TBI 0 n = 2, 3 ● LIN device connection As shown in the Figure below, a communication system of one LIN-Master device and a LIN-Slave device. UART can operate both as LIN-Master or LIN-Slave. Figure 18.7-15 Connection example of a small LIN-Bus system SOT SOT LIN bus SIN LIN-Master SIN Single-WireTransceiver Single-WireTransceiver LIN-Slave 373 CHAPTER 18 LIN-UART 18.7.8 Sample Flowcharts for UART in LIN communication (Operation Mode 3) This section contains sample flowcharts for UART in LIN communication. ■ UART as master device Figure 18.7-16 UART LIN master flow chart START Initial setting : Set operation mode 3 Serial data output enabled Baudrate setting Synch break length setting TXE=1, TIE=0 RXE=0, RIE=1 No Send Message? No (transmission) Yes (reception) Yes Wake up? RDRF=1 No Data field reception? (0x80 reception) Reception interrupt Yes (*1) Data 1 reception Transmission data 1 set : TDR=Data 1 Transmission interrupt enabled RDRF=1 RXE=0 TDRE=1 Reception interrupt Synch break interrupt enabled Synch break transmission : (*1) Data N reception Transmission interrupt ECCR : LBR=1 Transmission data N set : TDR=Data N Transmission interrupt disabled Synch field transmission : TDR=0x55 LBD=1 RDRF=1 Synch break interrupt Reception interrupt Reception enabled LBD=0 Synch break interrupt disabled (*1) Data 1 reception Data 1 reading RDRF=1 RDRF=1 Reception interrupt Reception interrupt (*1) (*1) Synch field reception Data 1 reception Data 1 reading Identify field set : TDR=ID RDRF=1 Reception interrupt (*1) (*2) ID field reception No Without error Yes 374 Error processing CHAPTER 18 LIN-UART ■ UART as slave device Figure 18.7-17 UART LIN slave flow chart START Initial setting : Set operation mode 3 Serial data output enabled Baudrate setting Synch break length setting TXE=1, TIE=0 RXE=0, RIE=1 Connection with UART and ICU Reception prohibited ICU interrupt enabled Synch break interrupt enabled Yes (reception) LBD=1 RDRF=1 Synch break interrupt No (transmission) Data field reception? Reception interrupt (*1) Synch break detection clear ECCR : LBD=0 Synch break interrupt prohibited Transmission data 1 set TDR=Data 1 Transmission interrupt enabled Data 1 reception RDRF=1 ICU interrupt Reception interrupt TDRE=1 (*1) Data N reception ICU data read ICU interrupt flag clear Transmission interrupt Transmission data N set TDR=Data N Transmission interrupt prohibited ICU interrupt Reception prohibited RDRF=1 ICU data read Baud rate regulation Reception enabled ICU interrupt flag clear ICU interrupt prohibited Reception interrupt (*1) Data 1 reception Data 1 read RDRF=1 LBD=1 Reception interrupt Synch break interrupt (*1) (*1) Data N reception Data N read Reception prohibited Identify field reception Sleep mode? No (*2) Yes No Without error Error processing Yes Wake up reception? No Yes Wake up transmission? No Yes Wake up code transmission 375 CHAPTER 18 LIN-UART 18.8 Notes on Using LIN-UART Notes on using UART are given below. ■ Notes on using UART ● Enabling operations In UART, the control register (SCR) has TXE (transmission) and RXE (reception) operation enable bits. Both, transmission and reception operations, must be enabled before the communication starts because they have been disabled as the default value (initial value). The operation can also be canceled by disabling these bits. ● Communication mode setting Set the communication mode while the system is not operating. If the mode is changed during transmission or reception, the transmission or reception is stopped and possible data will be lost. ● Transmission interrupt enabling timing The default (initial value) of the transmission data empty flag bit (SSR: TDRE) is “1” (no transmission data and transmission data write enable state). A transmission interrupt request is generated as soon as the transmission interrupt request is enabled (SSR: TIE=1). Be sure to set the TIE flag to “1” after setting the transmission data to avoid an immediate interrupt. ● Using LIN operation mode 3 The LIN features are available in mode 3 (transmitting, receiving synch break), but using mode 3 sets the UART data format automatically to LIN format (8N1, LSB first). Note that the length of the synch break for transmission is variable but for reception it is fixed 11-bit time. Note: During LIN operation, please set SCES bit of ESCR register to 0. ● Changing operation settings It is strongly recommended to reset UART after changing operation settings. Particularly if (for example) start-/stop-bits added to or removed from the data format. Note: If settings in the Serial Mode Register (SMR) are desired, it is not useful to set the UPCL bit at the same time to reset UART. The correct operation settings are not guaranteed in this case. Thus it is recommended to set the bits of the SMR and then to set them again plus the UPCL bit. ● LIN slave settings Set the baud rate before receiving the first LIN synch break for the slave operation. Otherwise, duration of the synch break can not be correctly checked against the minimum requirement of the LIN specification (13 master bit time and 11 slave bit time). 376 CHAPTER 18 LIN-UART ● Software compatibility Although this UART is similar to other UART in other microcontrollers, it is not software compatible to them. The programming models may be the same, but the structure of the registers differs. Furthermore the setting of the baud rate is now determined by a reload value instead of selecting a predefined value. ● Bus idle function The Bus Idle Function cannot be used in synchronous mode 2. ● AD bit (serial control register (SCR): address/data type select bit) Special care has to be taken when using the AD bit (Address-Data-Bit for multiprocessor mode 1) of the Serial Control Register. This bit is both a control and a flag bit, because writing to it sets the AD bit for transmission, whereas reading from it returns the last received AD Bit. Internally, the received and the transmitted value are stored in different registers, but in Read-Modify-Write instructions, the received value is read, modified and then written back for transmission. This can lead to a wrong value in the AD bit, when one of the other bits in the same register is accessed by an instruction of this kind. Therefore, this bit should be written by the last register access before transmission. Alternatively, using byte wise access and writing the correct values for all bits at once avoids this problem. Furthermore, the AD bit is not buffered like the transmission data register. Changing the bit when transmission will alter the AD bit of the currently transmitted data. ● Software reset of UART Perform the software reset (SMR: UPCL = 1), when the TXE bit of the SCR register is "1". ● LIN Synch field wait state In mode 3 (LIN operation), the LBD bit in the ESCR register is set to "1" if the input signal is kept at "0" for more than equal to 11-bit time. Then the UART waits for the following synch field to be received. If the UART is set into this state for other reasons than the synch break, it should be initialized by the software reset (SMR: UPCL = 1). 377 CHAPTER 18 LIN-UART 378 CHAPTER 19 400 kHz I2C INTERFACE This section describes the functions and operation of the fast I2C interface. 19.1 I2C Interface Overview 19.2 I2C Interface Registers 19.3 I2C Interface Operation 19.4 Programming Flow Charts 379 CHAPTER 20 400 kHz I2C INTERFACE 19.1 I2C Interface Overview The I2C interface is a serial I/O port supporting the Inter IC bus, operating as a master/ slave device on the I2C bus. The MB90350 Series contain one I2C Interface modules (only devices with suffix-"c"). ■ Features • Master/slave transmitting and receiving functions • Arbitration function • Clock synchronization function • General call addressing support • Transfer direction detection function • Restart condition generation and detection function • Bus error detection function • 7-bit addressing as master and slave • 10-bit addressing as master and slave • Possibility to give the interface a seven and a ten bit slave address • Acknowledging upon slave address reception can be disabled (Master-only operation) • Address masking to give interface several slave addresses (in 7 and 10 bit mode) • Up to 400 KBit transfer rate • Possibility to use built-in noise filters for SDA and SCL • Can receive data at 400 KBit if machine clock is higher than 6 MHz regardless of prescaler setting • Can generate MCU interrupts on transmission and bus error events • Supports being slowed down by a slave on bit and byte level The I2C interface does not support SCL clock stretching on bit level since it can receive the full 400K Bit data rate if the machine clock is higher than 6 MHz regardless of the prescaler setting. However, clock stretching on byte level is performed since SCL is pulled low during an interrupt (INT="1" in IBCR register). 380 CHAPTER 20 400 kHz I2C INTERFACE Figure 19.1-1 Block diagram ICCR I2C enable EN ICCR Clock Divider 1 2 3 4 5 ... 32 CS4 CS3 5 CS2 5 Clock Selector Sync CS1 CS0 Clock Divider 2 (by 12) SCL Duty Cycle Generator Shift Clock Generator IBSR BB Bus busy RSC Repeated start LRB Last Bit TRX Send/receive Bus Observer Bus Error ADT Address Data AL Arbitration Loss Detector ICCR NSF Internal data-bus IBCR enable BER BEIE MCU IRQ Interrupt Request INTE INT Noise Filter SCL SDA SCL SDA IBCR SCC MSS ACK GCAA Start Start-Stop Condition Generator Master ACK enable ACK Generator GC-ACK enable 8 IDAR IBSR AAS GCA ISMK ENSB ITMK ENTB RAL 8 Slave General call enable 7 bit mode Slave Address Comparator enable 10 bit mode received ad. length 7 10 10 ITBA ITMK 7 ISBA ISMK 10 10 7 7 381 CHAPTER 20 400 kHz I2C INTERFACE I2C Interface Registers 19.2 This section describes the function of the I2C interface registers in detail. ■ I2C Interface registers Figure 19.2-1 I2C Interface registers (1/2) Bus Control Register (IBCR0) Address: IBCR0: 007971H 15 14 13 12 11 10 9 BER BEIE SCC MSS ACK GCAA INTE 8 IBCR0 INT Initial value 00000000B R/W R/W W R/W R/W R/W R/W R/W Bus Status Register (IBSR0) Address: IBSR0: 007970H 7 6 BB R 5 4 3 RSC AL LRB TRX AAS GCA ADT R R R R R R 9 8 R 2 1 0 IBSR0 Initial value 0 0 0 0 0 0 0 0B Ten Bit slave Address register (ITBA0) Address: 15 14 13 12 11 10 ITBAH0: 007973H - - - - - - - - - - - - R/W R/W 7 6 5 4 3 2 Address: ITBAL0: 007972H TA9 TA8 1 ITBAH0 (upper) Initial value 00000000 B 0 ITBAL0 (lower) TA7 TA6 TA5 TA4 TA3 TA2 TA1 TA0 Initial value 0 0 0 0 0 0 0 0B R/W R/W R/W R/W R/W R/W R/W R/W Ten bit slave address MasK register (ITMK0) 13 12 11 10 ITMKH0: 007975H ENTB RAL - - - - R/W R/W - - - - R/W R/W 4 3 2 Address: Address: ITMKL0: 007974H 15 7 14 6 5 9 8 TM9 TM8 1 ITMKH0 (upper) Initial value 00111111B 0 ITMKL0 (lower) TM7 TM6 TM5 TM4 TM3 TM2 TM1TM0 Initial value 1 1 1 1 1 1 1 1B R/W R/W R/W R/W R/W R/W R/W R/W Seven Bit slave Address register (ISBA0) 382 Address: 7 ISBA0: 007976H - SA6 SA5 SA4 SA3 SA2 SA1 SA0 - R/W R/W R/W R/W R/W R/W R/W R/W : Readable and writable - : Undefined 6 5 4 3 2 1 0 ISBA0 Initial value 0 0 0 0 0 0 0 0B CHAPTER 20 400 kHz I2C INTERFACE Figure 19.2-1 I2C Interface registers (2/2) Seven bit slave address MasK register (ISMK0) Address: ISMK0: 007977H 15 14 13 12 11 10 9 8 ENSB SM6 SM5 SM4 SM3 SM2 SM1SM0 ISMK0 Initial value 0 1 1 1 1 1 1 1B R/W R/W R/W R/W R/W R/W R/W R/W Data Register (IDAR0) Address: IDAR0: 007978H 7 6 5 4 3 2 D7 D6 D5 D4 D3 D2 1 0 D1 D0 IDAR0 Initial value 00000000 R/W R/W R/W R/W R/W R/W R/W R/W B Clock control register (ICCR0) Address: ICCR0: 00797BH R/W : Readable and writable - : Undefined 15 14 13 12 11 10 9 8 - NSF EN CS4 CS3 CS2 CS1 CS0 - R/W R/W R/W R/W R/W R/W R/W ICCR0 Initial value 0 0 0 1 1 1 1 1B 383 CHAPTER 20 400 kHz I2C INTERFACE 19.2.1 Bus Status Register (IBSR) The bus status register (IBSR) has the following functions: • Bus busy detection • Restart start condition detection • Arbitration loss detection • Acknowledge detection • Data transfer direction indication • Addressing detection as slave • General call address detection • Address/data detection ■ Bus status register (IBSR) This register is read-only, all bits are controlled by the hardware. All bits are cleared if the interface is not enabled (EN = "0" in ICCR). Figure 19.2-2 Configuration of the bus status register (IBSR0/1) Address: IBSR0: 007970H 7 6 5 4 3 2 1 0 BB RSC AL LRB TRX AAS GCA ADT R R R R R R R R IBSR0 Initial value 0 0 0 0 0 0 0 0B bit 0 ADT Address data transfer bit 0 Incoming data is not address data (or bus not in use) 1 Incoming data is address bit 1 GCA General Call Address bit 0 Generall call address not received as slave 1 General call address received as slave bit 2 AAS Addressed as slave bit 0 not addressed as slave 1 Addressed as slave bit 3 TRX Transferring data bit 0 Not transmitting data 1 Transmitting data bit 4 LRB Last received bit 0 Receiver did acknowledge 1 Receiver did not acknowledge bit 5 AL Arbitration loss bit 0 No arbitration loss detected 1 Arbitration loss detected bit 6 RSC Restart condition bit 0 Restart condition not detected 1 Bus in use, restart condition detected bit 7 BB R 384 Bus busy bit : Read only 0 Stop condition detected (bus idle) : Initial value 1 Start condition detected (bus in use) CHAPTER 20 400 kHz I2C INTERFACE ■ Bus status register (IBSR) contents Table 19.2-1 Function of each bit of the bus status register (IBSR0/1) (1/2) Bit name Function bit 7 BB: Bus busy bit This bit indicates the status of the I2C bus. "0": Stop condition detected (bus idle) "1": Start condition detected (bus in use) This bit is set to "1" if a start condition is detected. It is reset upon a stop condition. bit 6 RSC: Restart condition bit This bit indicates detection of a restart condition. "0": Restart condition not detected. "1": Restart detected (bus in use). This bit is cleared at the end of an address data transfer (ADT="0") or detection of a stop condition. bit 5 AL: Arbitration loss bit This bit indicates an arbitration loss. "0": No arbitration loss detected. "1": Arbitration loss occurred during master sending. This bit is cleared by writing "0" to the INT bit or by writing "1" to the MSS bit in the IBCR register. An arbitration loss occurs if: - the data sent does not match the data read on the SDA line at the rising SCL edge - a repeated start condition is generated by another master in the first bit of a data byte - the interface could not generate a start or stop condition because signal transition caused from "1" to "0" by a certain external condition is observed at the SCL line. bit 4 LRB: Last received bit This bit is used to indicate the acknowledge from the receiving device. "0": Receiver acknowledged. "1": Receiver did not acknowledge. It is changed by the hardware upon reception of bit 9 (acknowledge bit) and is also cleared by a start or stop condition. bit 3 TRX: Transferring data bit This bit indicates data transmission operation. "0": Not transmitting data. "1": Transmitting data. It is set to "1": - if a start condition was generated in master mode - if addressed as slave in read access It is set to "0" if: - the bus is idle (BB="0") - an arbitration loss occurred - a "1" is written to the SCC bit during master interrupt (MSS="1" and INT="1") - the MSS bit being cleared during master interrupt (MSS="1" and INT="1") - the interface is in slave mode and the last transferred byte was not acknowledged - the interface is in slave mode and it is receiving data - the interface is in master mode and is reading data from a slave bit 2 AAS: Addressed as slave bit This bit indicates detection of a slave addressing. "0": Not addressed as slave. "1": Addressed as slave. This bit is cleared by a start, restart or stop condition. It is set if the interface detects its seven and/or ten bit slave address. 385 CHAPTER 20 400 kHz I2C INTERFACE Table 19.2-1 Function of each bit of the bus status register (IBSR0/1) (2/2) Bit name Function bit 1 GCA: General call address bit This bit indicates detection of a general call address (0x00). "0": General call address not received as slave. "1": General call address received as slave. This bit is cleared by a start, restart or stop condition. bit 0 ADT: Address data transfer bit This bit indicates the detection of an address data transfer. "0": Incoming data is not address data (or bus is not in use). "1": Incoming data is address data. This bit is set to "1" by a start condition. It is cleared after the second byte if a ten bit slave address header with write access is detected, else it is cleared after the first byte. This bit is also cleared when: - a “0” is written to the MSS bit during a master interrupt (MSS="1" and INT="1" in IBCR) - a “1” is written to the SCC bit during a master interrupt (MSS="1" and INT="1" in IBCR) - the INT bit is being cleared - the beginning of every byte transfer if the interface is not involved in the current transfer as master or slave 386 CHAPTER 20 400 kHz I2C INTERFACE 19.2.2 Bus Control Register (IBCR) The bus control register (IBCR) has the following functions: • Interrupt enabling flags • Interrupt generation flag • Bus error detection flag • Restart condition generation • Master / slave mode selection • General call acknowledge generation enabling • Data byte acknowledge generation enabling ■ Bus control register (IBCR) Write access to this register should only occur while the INT="1" or if a transfer is to be started. The user should not write to this register during an ongoing transfer since changes to the ACK or GCAA bits could result in bus errors. All bits in this register except the BER and the BEIE bit are cleared if the interface is not enabled (EN="0" in ICCR). 387 CHAPTER 20 400 kHz I2C INTERFACE Figure 19.2-3 Configuration of the bus control register (IBCR0) 15 Address: 14 13 12 BER BEIE SCC MSS 11 10 9 ACK GCAA INTE 8 IBCR0 INT Initial value 00000000B IBCR0: 007971H R/W R/W W R/W R/W R/W R/W R/W bit 8 INT 0 1 Interrupt bit see table on next page for details bit 9 INTE Interrupt enable bit 0 Interrupt disabled 1 Interrupt enabled bit 10 GCCA Generall call address acknowledge bit 0 No acknowledge on general call address 1 Acknowledge on general call address bit 11 ACK Acknowledge bit 0 No Acknowledge on data byte reception 1 Acknowledge on data byte reception bit 12 MSS Master slave select bit 0 Go to slave mode 1 Go to master mode (s. table below for details) bit 13 SCC Start condition continue bit 0 Write: No effect: 1 Write: Generate repeated start condition bit 14 BEIE 388 W : Write only bit R/W : Readable and writable : Initial value Bus error interrupt enable bit 0 Bus error interrupt disabled 1 Bus error interrupt enabled bit 15 Bus error bit BER write read 0 Clear bus error int. No error detected 1 No effect Error detected CHAPTER 20 400 kHz I2C INTERFACE ■ Bus control register (IBCR) contents Table 19.2-2 Function of each bit of the bus control register (IBCR0) (1/2) Bit name Function bit 15 BER: Bus error bit This bit is the bus error interrupt flag. It is set by the hardware and cleared by the user. It always reads "1" in a Read-Modify-Write access. Write access: "0": Clear bus error interrupt flag "1": No effect Read access: "0": No bus error detected "1": One of the error conditions described below detected When this bit is set, the EN bit in the ICCR register is cleared, the I2C interface goes to pause status, data transfer is interrupted and all bits in the IBSR and the IBCR registers except BER and BEIE are cleared. The BER bit must be cleared before the interface may be reenabled. This bit is set to "1" if: - start or stop conditions are detected at wrong places: during an address data transfer or during the transfer of the bits two to nine (acknowledge bit) - a ten bit address header with read access is received before a ten bit write access bit 14 BEIE: Bus error interrupt enable bit This bit enables the bus error interrupt. It only can be changed by the user. "0": Bus error interrupt disabled "1": Bus error interrupt enabled Setting this bit to "1" enables MCU interrupt generation when the BER bit is set to "1". bit 13 SCC Start condition continue bit This bit is used to generate a repeated start condition. It is write only - it always reads "0". "0": No effect "1": Generate repeated start condition during master transfer A repeated start condition is generated if a "1" is written to this bit while an interrupt in master mode (MSS="1" and INT="1") and the INT bit is cleared automatically. bit 12 MSS: Master slave select bit This is the master/slave mode selection bit. It can only be set by the user, but it can be cleared by the user and the hardware. "0": Go to slave mode "1": Go to master mode, generate start condition and send address data byte in IDAR register. It is cleared if an arbitration loss event occurs during master sending. If a "0" is written to it during a master interrupt (MSS="1" and INT="1"), the INT bit is cleared automatically, a stop condition will be generated and the data transfer ends. Note that the MSS bit is reset immediately, the generation of the stop condition can be checked by polling the BB bit in the IBSR register. If a "1" is written to it while the bus is idle (MSS="0" and BB="0"), a start condition is generated and the contents of the IDAR register (which should be address data) is sent. If a "1" is written to the MSS bit while the bus is in use (BB="1" and TRX="0" in IBSR; MSS="0" in IBCR), the interface waits until the bus is free and then starts sending. If the interface is addressed as slave with write access (data reception) in the meantime, it will start sending after the transfer ended and the bus is free again. If the interface is sending data as slave in the meantime (AAS="1" and TRX="1" in IBSR), it will not start sending data if the bus is free again. It is important to check whether the interface was addressed as slave (AAS="1" in IBSR), sent the data byte successfully (MSS="1" in IBCR) or failed to send the data byte (AL="1" in IBSR) at the next interrupt! 389 CHAPTER 20 400 kHz I2C INTERFACE Table 19.2-2 Function of each bit of the bus control register (IBCR0) (2/2) Bit name Function bit 11 ACK: Acknowledge bit This bit enables the acknowledge generation on data byte reception. It only can be changed by the user. "0": The interface will not acknowledge on data byte reception "1": The interface will acknowledge on data byte reception This bit is not valid when receiving address bytes in slave mode - if the interface detects its 7 or 10 bit slave address, it will acknowledge if the corresponding enable bit (ENTB in ITMK or ENSB in ISMK) is set. Write access to this bit should occur during an interrupt (INT="1") or if the bus is idle (BB="0" in the IBSR register) only. bit 10 GCAA: General call address acknowledge bit This bit enables acknowledge generation when a general call address is received. It only can be changed by the user. "0": The interface will not acknowledge on general call address byte reception. "1": The interface will acknowledge on general call address byte reception. Write access to this bit should occur during an interrupt (INT="1") or if the bus is idle (BB="0" in IBSR register) or the interface is disabled (EN="0" in ICCR register) only. bit 9 INTE: Interrupt enable bit This bit enables the MCU interrupt generation. It only can be changed by the user. "0": Interrupt disabled "1": Interrupt enabled Setting this bit to "1" enables MCU interrupt generation when the INT bit is set to "1" (by the hardware). bit 8 INT: Interrupt flag bit This bit is the transfer end interrupt request flag. It is changed by the hardware and can be cleared by the user. It always reads "1" in a Read-Modify-Write access. Write access: "0": Clear transfer end interrupt request flag "1": No effect Read access: "0": Transfer not ended or not involved in current transfer or bus is idle "1": Set at the end of a 1-byte data transfer or reception including the acknowledge bit under the following conditions: Device is bus master. Device is addressed as slave. General call address received. Arbitration loss occurred. Set at the end of an address data reception (after first byte if seven bit address received, after second byte if ten bit address received) including the acknowledge bit if the device is addressed as slave. While this bit is "1" the SCL line will hold an "L" level signal. Writing "0" to this bit clears the setting, releases the SCL line, and executes transfer of the next byte or a repeated start or stop condition is generated. Additionally, this bit is cleared if a "1" is written to the SCC bit or the MSS bit is being cleared. ■ SCC, MSS and INT bit competition Simultaneously writing to the SCC, MSS and INT bits causes a competition to transfer the next byte, to generate a repeated start condition or to generate a stop condition. In these cases the order of priority is as follows: 390 CHAPTER 20 400 kHz I2C INTERFACE • Next byte transfer and stop condition generation. When "0" is written to the INT bit and "0" is written to the MSS bit, the MSS bit takes priority and a stop condition is generated. • Next byte transfer and start condition generation. When “0” is written to the INT bit and “1” is written to the SCC bit, the SCC bit takes priority. A repeated start condition is generated and the contents of the IDAR register is sent. • Repeated start condition generation and stop condition generation. When a “1” is written to the SCC bit and “0” to the MSS bit, the MSS bit clearing takes priority. A stop condition is generated and the interface enters slave mode. Notes: When an instruction which generates a start condition is executed (the MSS bit is set to 1) at the timing shown in Figure 19.2-4 and Figure 19.2-5, arbitration lost detection (AL bit = 1) prevents an interrupt (INT bit = 1) from being generated. • Condition 1 in which an interrupt (INT bit = 1) upon detection of "AL bit = 1" does not occurs When an instruction which generates a start condition is executed (setting the MSS bit in the IBCR register to 1) with no start condition detected (BB bit = 0) and with the SDA or SCL pin at the "L" level Figure 19.2-4 Diagram of timing at which an interrupt upon detection of " AL bit = 1 " does not occur SCL pin SCL pin or SDA pin is Low level. SDA pin "L" "L" I2C operation enable state (EN bit = 1) Master mode setting (MSS bit = 1) 1 Arbitration lost detection (AL bit = 1) • Bus busy (BB bit) 0 Interruption (INT bit) 0 Case 2: When I2C interface is enabled while there is ongoing communication with another bus master; The interface participates in the I2C bus while the bus is occupied with ongoing communication if the EN bit is set from "0" to "1". In this case the BB bit stays "0" (no start condition is detected) and setting the MSS bit to "1" results in the AL bit indicating "1". However the AL bit will not set the INT bit under this circumstances. 391 CHAPTER 20 400 kHz I2C INTERFACE Figure 19.2-5 Diagram of timing at which an interrupt upon detection of "AL bit = 1" does not occur Start Condition Stop Condition INT bit interruption is not generated in 9th clock. SCL pin SDA pin SLAVE ADDRESS ACK ACK DAT EN bit MSS bit AL bit 0 BB bit 0 INT bit If a symptom as described above can occur, follow the procedure below for software processing. 1. Execute the instruction that generates a start condition (set the MSS bit to 1). 2. Use, for example, the timer function to wait for the time for three - bit data transmission at the I2C transfer frequency set in the ICCR register.* Example: Time for three-bit data transmission at an I2C transfer frequency of 100 kHz = (1/100 × 103) × 3 = 30 3. Check the AL and BB bits in the IBSR register and, if the AL and BB bits are 1 and 0, respectively, set the EN bit in the ICCR register to 0 to initialize I2C. When the AL and BB bits are not so, perform normal processing. A sample flow is given below. Master mode setting Setting “1” to MSS bit in bus control register (IBCR) Wait for the time for three-bit data transmission at the I2C transfer frequency set in the clock control register (ICCR).* BB bit = 0 and AL bit = 1 NO YES Setting EN bit to “0” and initializing of I2C To normal process *: Arbitration lost is detected within 3-bit time after setting the MSS bit to "1". 392 CHAPTER 20 400 kHz I2C INTERFACE • Example of occurrence of an interrupt (INT bit = 1) upon detection of "AL bit = 1" When an instruction which generates a start condition is executed (setting the MSS bit to 1) with "bus busy" detected (BB bit = 1) and arbitration is lost, the INT bit interrupt occurs upon detection of "AL bit = 1" . Figure 19.2-6 Diagram of timing at which an interrupt upon detection of "AL bit = 1" occurs Start Condition Interrupt at 9th clock. SCL pin SDA pin SLAVE ADDRESS ACK DAT EN bit MSS bit AL bit clear on soft AL bit BB bit INT bit INT bit clear on soft and open SCL 393 CHAPTER 20 400 kHz I2C INTERFACE 19.2.3 Ten Bit Slave Address Register (ITBA) This register (ITBAH / ITBAL) designates the ten bit slave address. ■ Ten bit slave address register (ITBA) Write access to this register is only possible if the interface is disabled (EN="0" in ICCR). Figure 19.2-7 Configuration of the ten bit slave address register (IBTA0) Address: ITBAH0: 007973H Address: ITBAL0: 007972H 15 14 13 12 11 10 9 - - - - - - TA9 TA8 - - - - - - R/W R/W 7 6 5 4 3 2 1 8 0 TA7 TA6 TA5 TA4 TA3 TA2 TA1 TA0 ITBAH0 (upper) Initial value 0 0 0 0 0 0 0 0B ITBAL0 (lower) Initial value 0 0 0 0 0 0 0 0B R/W R/W R/W R/W R/W R/W R/W R/W R/W : Readable and writable - : Undefined ■ Ten bit slave address register (ITBA) contents Table 19.2-3 Function of each bit of the ten bit slave address register (ITBA0) Bit name Function bits 15 to 10 Undefined These bits always return "0". bits 9 to 0 TBA9 to 0: Ten bit slave address When address data is received in slave mode, it is compared to the ITBA register if the ten bit address is enabled (ENTB="1" in the ITMK register). An acknowledge is sent to the master after reception of a ten bit address header with write access1. Then, the second incoming byte is compared to the TBAL register. If a match is detected, an acknowledge signal is sent to the master device and the AAS bit is set. Additionally, the interface acknowledges upon the reception of a ten bit header with read access2 after a repeated start condition. All bits of the slave address may be masked using the ITMK register. The received ten bit slave address is written back to the ITBA register, it is only valid while the AAS bit in the IBSR register is “1”. Note: • A ten bit header (write access) consists of the following bit sequence: 11110, TA9, TA8, 0. • A ten bit header (read access) consists of the following bit sequence: 11110, TA9, TA8, 1. 394 CHAPTER 20 400 kHz I2C INTERFACE 19.2.4 Ten Bit Address Mask Register (ITMK) This register contains the ten bit slave address mask and the ten bit slave address enable bit. ■ Ten bit address mask register (ITMK) Figure 19.2-8 Configuration of the ten bit address mask register (ITMK0) 15 Address: 14 13 12 11 10 - - - - TM9 TM8 R/W R/W - - - - R/W R/W 4 3 2 ITMKH0: 007975H ENTB RAL 7 Address: ITMKL0: 007974H 6 5 9 1 8 0 TM7 TM6 TM5 TM4 TM3 TM2 TM1TM0 ITMKH0 (upper) Initial value 00111111B ITMKL0 (lower) Initial value 1 1 1 1 1 1 1 1B R/W R/W R/W R/W R/W R/W R/W R/W R/W : Readable and writable - : Undefined ■ Ten bit address mask register (ITMK) contents Table 19.2-4 Function of each bit of the ten bit address mask register (ITMK0/1) Bit name Function bit 15 ENTB: Enable ten bit slave address bit This bit enables the ten bit slave address (and the acknowledging upon its reception). Write access to this bit is only possible if the interface is disabled (EN="0" in ICCR). "0": Ten bit address disabled "1": Ten bit address enabled bit 14 RAL: Received slave address length bit This bit indicates whether the interface was addressed as a seven or ten bit slave. It is read-only. "0": Addressed as seven bit slave "1": Addressed as ten bit slave This bit can be used to determine whether the interface was addressed as a seven or ten bit slave if both slave addresses are enabled (ENTB="1" and ENSB="1"). Its contents is only valid if the AAS bit in the IBSR register is "1". This bit is also reset if the interface is disabled (EN="0" in ICCR). bit 13 to 10 Undefined These bits always return "1" during reading. 395 CHAPTER 20 400 kHz I2C INTERFACE Table 19.2-4 Function of each bit of the ten bit address mask register (ITMK0/1) Bit name bit 9 to 0 396 TMK: Ten bit slave address mask bits Function This register is used to mask the ten bit slave address of the interface. Write access to these bits is only possible if the interface is disabled (EN="0" in ICCR). "0": Bit is not used in slave address comparison "1": Bit is used in slave address comparison This can be used to make the interface acknowledge on multiple ten bit slave addresses. Only the bits set to "1" in this register are used in the ten bit slave address comparison. The received slave address is written back to the ITBA register and thus may be determined by reading the ITBA register if the AAS bit in the IBSR register is “1”. Note: If the address mask is changed after the interface had been enabled, the slave address should also be set again since it could have been overwritten by a previously received slave address. CHAPTER 20 400 kHz I2C INTERFACE 19.2.5 Seven Bit Slave Address Register (ISBA) This register designates the seven bit slave address. ■ Seven bit slave address register Write access to this register is only possible if the interface is disabled (EN="0" in ICCR). Figure 19.2-9 Configuration of the seven bit slave address register (ISBA0) Address: 7 ISBA0: 007976H - SA6 SA5 SA4 SA3 SA2 SA1 SA0 - R/W R/W R/W R/W R/W R/W R/W R/W : Readable and writable - : Undefined 6 5 4 3 2 1 0 ISBA0 Initial value 0 0 0 0 0 0 0 0B ■ Seven bit slave address register contents Table 19.2-5 Function of each bit of the seven bit slave address register Bit name Function bit 7 Undefined This bit always returns "0" during reading. bit 6 to 0 SA6 to SA0: Seven bit slave address bits When address data is received in slave mode, it is compared to the ISBA register if the seven bit address is enabled (ENSB="1" in the ISMK register). If a match is detected, an acknowledge signal is sent to the master device and the AAS bit is set. All bits of the slave address may be masked using the ISMK register. The received seven bit slave address is written back to the ISBA register, it is only valid while the AAS bit in the IBSR register is “1”. The interface does not compare the contents of this register to the incoming data if a ten bit header or a general call is received. ■ Seven bit slave address mask register (ISMK) This register contains the seven bit slave address mask and the seven bit mode enable bit. Write access to this register is only possible if the interface is disabled (EN="0" in ICCR). Figure 19.2-10 Configuration of the seven bit address mask register (ISMK0) Address: 15 14 13 12 11 10 9 8 ISMK0: 007977H ENSB SM6 SM5 SM4 SM3 SM2 SM1SM0 ISMK0 Initial value 0 1 1 1 1 1 1 1B R/W R/W R/W R/W R/W R/W R/W R/W R/W : Readable and writable 397 CHAPTER 20 400 kHz I2C INTERFACE ■ Seven bit slave address mask register contents Table 19.2-6 Function of each bit of the seven bit slave address mask register (ISMK0) Bit name Function bit 15 ENSB: Enable seven bit slave address bit This bit enables the seven bit slave address (and the acknowledging upon its reception). "0": Seven bit slave address disabled "1": Seven bit slave address enabled bit 14 to 8 SMK: Seven bit slave address mask bits This register is used to mask the seven bit slave address of the interface. "0": Bit is not used in slave address comparison. "1": Bit is used in slave address comparison. This can be used to make the interface acknowledge on multiple seven bit slave addresses. Only the bits set to “1” in this register are used in the seven bit slave address comparison. The received slave address is written back to the ISBA register and may thus may be determined by reading the ISBA register if the AAS bit in the IBSR register is “1”. Note: If the address mask is changed after the interface had been enabled, the slave address should also be set again since it could have been overwritten by a previously received slave address. 398 CHAPTER 20 400 kHz I2C INTERFACE 19.2.6 Data Register (IDAR) Data Register for the 400 kHz I2C Interface. ■ Data register (IDAR) Figure 19.2-11 Configuration of the data register (IDAR0) Address: IDAR0: 007978H 7 6 5 4 3 2 D7 D6 D5 D4 D3 D2 1 0 D1 D0 IDAR0 Initial value 00000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W : B Readable and writable ■ Data register contents Table 19.2-7 Function of each bit of the data register Bit name bits 7 to 0 D7 to D0: Data bits Function The data register is used in serial data transfer, and transfers data MSB-first. This register is double buffered on the write side, so that when the bus is in use (BB="1"), write data can be loaded to the register for serial transfer. The data byte is loaded into the internal transfer register if the INT bit in the IBCR register is being cleared or the bus is idle (BB="0" in IBSR). In a read access, the internal register is read directly, therefore received data values in this register are only valid if INT="1" in the IBCR register. 399 CHAPTER 20 400 kHz I2C INTERFACE 19.2.7 Clock Control Register (ICCR) The clock control register (ICCR) has the following functions: • Enable test mode • Enable IO pad noise filters • Enable I2C interface operation • Setting the serial clock frequency ■ Clock control register (ICCR) Figure 19.2-12 Configuration of the clock control register (ICCR0) Address: ICCR0: 00797BH R/W : Readable and writable - : Undefined 15 14 13 12 11 10 9 8 ICCR0 - NSF EN CS4 CS3 CS2 CS1 CS0 - R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 1 1 1 1 1B ■ Clock control register (ICCR) contents Table 19.2-8 Function of each bit of the clock control register (ICCR0/1) (1/2) Bit name Function bit 15 Undefined This bit always returns "0" during reading. bit 14 NSF: IO pad noise filter enable bit This bit enables the noise filters built into the SDA and SCL IO pads. The noise filter will suppress single spikes with a pulse width of 0 ns (minimum) and between 1 and 1.5 cycles of the machine clock. The maximum depends on the phase relationship between I2C signals (SDA, ACL) and machine clock. It should be set to “1” if the interface is transmitting or receiving at data rates above 100 KBit. bit 13 EN: Enable bit This bit enables the I2C interface operation. It can only be set by the user but may be cleared by the user and the hardware. "0": Interface disabled "1": Interface enabled When this bit is set to “0” all bits in the IBSR register and IBCR register (except the BER and BEIE bits) are cleared and the module is disabled and the I2C lines are left open. It is cleared by the hardware if a bus error occurs (BER="1" in IBCR). Note: The interface immediately stops transmitting or receiving if is it is being disabled. This might leave the I2C bus in an undesired state. 400 CHAPTER 20 400 kHz I2C INTERFACE Table 19.2-8 Function of each bit of the clock control register (ICCR0/1) (2/2) Bit name bits 12 to 8 Function CS4 to CS0: Clock prescaler bits These bits select the serial bit rate. They can only be changed if the interface is disabled (EN="0") or the EN bit is being cleared in the same write access. n CS4 CS3 CS2 CS1 CS0 1 0 0 0 0 1 Bitrate: φ / 28(+1) 2 0 0 0 1 0 Bitrate: φ / 40(+1) 3 0 0 0 1 1 Bitrate: φ / 52(+1) 4 0 0 1 0 0 Bitrate: φ / 64(+1) 1 1 1 1 1 Bitrate: φ / 400(+1) ... 31 (+1) means: Add 1 to divisor, if noise filter is enabled ■ Clock prescaler settings The calculation formula for CS0 to CS4 is determined as follows: Bitrate = φ n × 12 + 16 n>0 φ : machine clock, Noise filter disabled Bitrate = φ n × 12 + 17 n>0 φ : machine clock, Noise filter enabled Table 19.2-9 Prescaler settings: n CS4 CS3 CS2 CS1 CS0 1 0 0 0 0 1 2 0 0 0 1 0 3 0 0 0 1 1 1 1 1 ... 31 1 1 Note: Do not use n=0 prescaler setting, it violates SDA/SCL timings. 401 CHAPTER 20 400 kHz I2C INTERFACE ■ Common machine clock frequencies The most common machine clock frequencies with their prescaler settings and the resulting sending bit rate: Table 19.2-10 Common machine clock frequencies Machine Clock [MHz] 402 100 KBit (Noise filter disabled) 400 KBit (Noise filter enabled) n Bit rate [Kbit] m Bit rate [Kbit] 24 19 98 4 369 20 16 96 3 377 16 12 100 2 390 40/3 = 13.3 10 98 2 325 12 9 96 2 292 64/6 = 10.6 8 94 1 367 10 7 100 1 344 8 6 90 1 275 CHAPTER 20 400 kHz I2C INTERFACE 19.3 I2C Interface Operation The I2C bus executes communication using two bi-directional bus lines, the serial data line (SDA) and serial clock line (SCL). The I2C interface has two open-drain I/O pins (SDA/SCL) corresponding to these lines, enabling wired logic applications. ■ Start conditions When the bus is free (BB="0" in IBSR, MSS="0" in IBCR), writing “1” to the MSS bit places the I2C interface in master mode and generates a start condition. If a “1” is written to it while the bus is idle (MSS="0" and BB="0"), a start condition is generated and the contents of the IDAR register (which should be address data) is sent. Repeated start conditions can be generated by writing “1” to the SCC bit when in bus master mode and interrupt status (MSS="1" and INT="1" in IBCR). If a “1” is written to the MSS bit while the bus is in use (BB="1" and TRX="0" in IBSR; MSS="0"and INT="0"in IBCR), the interface waits until the bus is free and then starts sending. If the interface is addressed as slave with write access (data reception) in the meantime, it will start sending after the transfer ended and the bus is free again. If the interface is sending data as slave in the meantime, it will not start sending data if the bus is free again. It is important to check whether the interface was addressed as slave (MSS="0" in IBCR and AAS="1" in IBSR), sent the data byte successfully (MSS="1" in IBCR) or failed to send the data byte (AL="1" in IBSR) at the next interrupt. Writing "1" to the MSS bit or SCC bit in any other situation has no significance. ■ Stop conditions Writing “0” to the MSS bit in master mode (MSS="1" and INT="1" in IBCR) generates a stop condition and places the device in slave mode. Writing “0” to the MSS bit in any other situation has no significance. After clearing the MSS bit, the interface tries to generate a stop condition which might fail if a certain external condition causes signal transition caused from "1" to "0" at the SCL line before the generation of this stop condition. In this case, the AL bit is set to "1" and interrupt is signaled at the end of the next byte. ■ Slave address detection In slave mode, after a start condition is generated the BB is set to “1” and data sent from the master device is received into the IDAR register. After the reception of eight bits, the contents of the IDAR register is compared to the ISBA register using the bit mask stored in ISMK if the ENSB bit in the ISMK register is “1”. If a match results, the AAS bit is set to “1” and an acknowledge signal is sent to the master. Then bit 0 of the received data (bit 0 of the IDAR register) is inverted and stored in the TRX bit. If the ENTB bit in the ITMK register is "1" and a ten bit address header (11110, TA1, TA0, write access) is detected, the interface sends an acknowledge signal to the master and stores the inverted last data bit in the TRX register. No interrupt is generated. Then, the next transferred byte is compared (using the bit mask stored in ITMK) to the lower byte of the ITBA register. If a match is found, an acknowledge signal is sent to the master, the AAS bit is set and an interrupt is generated. If the interface was addressed as slave and detects a repeated start condition, the AAS bit is set after reception of the ten bit address header (11110, TA1, TA0, read access) and an interrupt is generated. 403 CHAPTER 20 400 kHz I2C INTERFACE Since there are separate registers for the ten and seven bit address and their bit masks, it is possible to make the interface acknowledge on both addresses by setting the ENSB (in ISMK) and ENTB (in ITMK) bits. The received slave address length (seven or ten bit) may be determined by reading the RAL bit in the ITMK register (this bit is valid if the AAS bit is set only). It is also possible to give the interface no slave address by setting both bits to "0" if it is only used as a master. All slave address bits may be masked with their corresponding mask register (ITMK or ISMK). ■ Slave address masking Only the bits set to “1” in the mask registers (ITMK / ISMK) are used for address comparison, all other bits are ignored. The received slave address can be read from the ITBA (if ten bit address received, RAL="1") or ISBA (if seven bit address received, RAL="0") register if the AAS bit in the IBSR register is “1”. If the bit masks are cleared, the interface can be used as a bus monitor since it will always be addressed as slave. Note that this is not a real bus monitor because it acknowledges upon any slave address reception, even if there is no other slave listening. ■ Addressing slaves In master mode, after a start condition is generated the BB and TRX bits are set to “1” and the contents of the IDAR register is sent in MSB first order. After address data is sent and an acknowledge signal was received from the slave device, bit 0 of the sent data (bit 0 of the IDAR register after sending) is inverted and stored in the TRX bit. Acknowledgement by the slave may be checked using the LRB bit in the IBSR register. This procedure also applies to a repeated start condition. In order to address a ten bit slave for write access, two bytes have to be sent. The first one is the ten bit address header which consists of the bit sequence "1 1 1 1 0 A9 A8 0", it is followed by the second byte containing the lower eight bits of the ten bit slave address (A7 to A0). A ten bit slave is accessed for reading by sending the above byte sequence and generating a repeated start condition (SCC bit in IBCR) followed by a ten bit address header with read access (1 1 1 1 0 A9 A8 1). Summary of the address data bytes: 7 bit slave, write access: Start condition - A6 A5 A4 A3 A2 A1 A0 0. 7 bit slave, read access: Start condition - A6 A5 A4 A3 A2 A1 A0 1. 10 bit slave, write access: Start condition - 1 1 1 1 0 A9 A8 0 - A7 A6 A5 A4 A3 A2 A1 A0. 10 bit slave, read access: Start condition - 1 1 1 1 0 A9 A8 1 - A7 A6 A5 A4 A3 A2 A1 A0 - repeated start - 1 1 1 1 0 A9 A8 1. ■ Arbitration During sending in master mode, if another master device is sending data at the same time, arbitration is performed. If a device is sending the data value "1" and the data on the SDA line has an "L" level value, the device is considered to have lost arbitration, and the AL bit is set to "1." Also, the AL bit is set to "1" if a start condition is detected at the first bit of a data byte but the interface did not want to generate one or the generation of a start or stop condition failed by some reason. Arbitration loss detection clears both the MSS and TRX bit and immediately places the device in slave mode so it is able to acknowledge if its own slave address is being sent. 404 CHAPTER 20 400 kHz I2C INTERFACE ■ Acknowledgement Acknowledge bits are sent from the receiver to the transmitter. The ACK bit in the IBCR register can be used to select whether to send an acknowledgment when data bytes are received. When data is send in slave mode (read access from another master), if no acknowledgement is received from the master, the TRX bit is set to "0" and the device goes to receiving mode. This enables the master to generate a stop condition as soon as the slave has released the SCL line. In master mode, acknowledgement by the slave can be checked by reading the LRB bit in the IBSR register. 405 CHAPTER 20 400 kHz I2C INTERFACE 19.4 Programming Flow Charts Each programming flow charts for the 400 kHz I2C interface is shown below. ■ Programming flow charts Figure 19.4-1 Example of slave addressing and sending data Addressing a 7 bit slave Sending data Start Start Address slave for write Clear BER bit (if set); Enable Interface EN:=1; IDAR := Data Byte; INT := 0 IDAR := sl.address<<1+RW; MSS := 1; INT := 0 N INT=1? N INT=1? Y Y Y BER=1? Y Bus error BER=1? N N AL=1? Restart transfer Check if AAS Y AL=1? Restart transfer Check if AAS Y N N ACK? ACK? N N (LRB=0?) (LRB=0?) Y Y Ready to send data Last byte Y transferred? N Slave did not ACK Generate repeated start or stop condition Transfer End Generate repeated start or stop condition 406 CHAPTER 19 400 kHz I2C INTERFACE Figure 19.4-2 Example of receiving data Start Address slave for read Clear ACK bit in IBCR if it’s the last byte to read from slave; INT := 0 N INT=1? Y BER=1? Y Bus error reenable IF N N Last byte transferred? Y Transfer End Generate repeated start or stop condition 407 CHAPTER 19 400 kHz I2C INTERFACE 408 CHAPTER 20 CAN CONTROLLER This chapter explains the functions and operations of the CAN controller. Note: CAN controller 2 is not specified in the MB90350 series. For this reason Fujitsu recommends not to use these features. 20.1 Features of CAN Controller 20.2 Block Diagram of CAN Controller 20.3 List of Overall Control Registers 20.4 List of Message Buffers (ID Registers) 20.5 List of Message Buffers (DLC Registers and Data Registers) 20.6 Classifying the CAN Controller Registers 20.7 Transmission of CAN Controller 20.8 Reception of CAN Controller 20.9 Reception Flowchart of CAN Controller 20.10 How to Use the CAN Controller 20.11 Procedure for Transmission by Message Buffer (x) 20.12 Procedure for Reception by Message Buffer (x) 20.13 Setting Configuration of Multi-level Message Buffer 20.14 Setting the CAN Direct Mode Register 20.15 Precautions when Using CAN Controller 409 CHAPTER 20 CAN CONTROLLER 20.1 Features of CAN Controller The CAN controller is a module built into a 16-bit microcontroller (F2MC-16LX). The CAN (Controller Area Network) is the standard protocol for serial communication between automobile controllers and is widely used in industrial applications. ■ Features of CAN controller The CAN controller has the following features: ● Conforms to CAN Specification Version 2.0 Part A and B Supports transmission/reception in standard frame and extended frame formats ● Supports transmitting of data frames by receiving remote frames ● 16 transmitting/receiving message buffers 29-bit ID and 8-byte data Multi-level message buffer configuration ● Supports full-bit comparison, full-bit mask and partial bit mask filtering. Two acceptance mask registers in either standard frame format or extended frame formats ● Bit rate programmable from 10 Kbps to 1 Mbps (A minimum 8 MHz machine clock is required if 1 Mbps is used) 410 CHAPTER 20 CAN CONTROLLER 20.2 Block Diagram of CAN Controller Figure 20.2-1 shows a block diagram of the CAN controller. ■ Block diagram of CAN controller Figure 20.2-1 Block diagram of CAN controller TQ (Operating clock) F2MC-16LX bus Prescaler 1 to 64 frequency division Clock Bit timing generation SYNC, TSEG1, TSEG2 PSC TS1 BTR TS2 RSJ TOE TS RS CSR HALT NIE NT Node status change interrupt generation IDLE, INT, SUSPND, transmit, receive, ERR, OVRLD Bus state machine Node status change interrupt NS1, 0 Error control RTEC Transmitting/receiving sequencer BVALR TREQR TBFx, clear Transmitting buffer x decision TBFx Data counter Error frame generation Acceptance filter control Overload frame generation TDLC RDLC TBFx IDSEL BITER, STFER, CRCER, FRMER, ACKER TCANR Output driver ARBLOST TX TRTRR TCR Stuffing Transmission shift register RFWTR TBFx, set, clear Transmission complete interrupt Transmission complete interrupt generation TDLC TIER CRC generation ACK generation CRCER RBFx, set RDLC RCR Reception complete interrupt Reception complete interrupt generation RIER RBFx, TBFx, set, clear CRC generation/error check Receive shift register STFER Destuffing/stuffing error check RRTRR RBFx, set IDSEL ROVRR ARBLOST AMSR AMR0 0 1 Acceptance filter Receiving buffer x decision BITER Bit error check ACKER Acknowledgment error check AMR1 RBFx IDR0 to 15 DLCR0 to 15 DTR0 to 15 RAM RAM address generation Arbitration check FRMER Form error check PH1 Input latch RX RBFx, TBFx, RDLC, TDLC, IDSEL LEIR LDER 411 CHAPTER 20 CAN CONTROLLER 20.3 List of Overall Control Registers Table 20.3-1 lists overall control registers. ■ List of overall control registers Table 20.3-1 List of overall control registers (1/2) Address Register Abbreviation Access Initial Value CAN1 000080H 000081H 000082H 000083H 000084H 000085H 000086H Message buffer valid register BVALR R/W 00000000 00000000 Transmit request register TREQR R/W 00000000 00000000 Transmit cancel register TCANR W 00000000 00000000 Transmit complete register TCR R/W 00000000 00000000 Receive complete register RCR R/W 00000000 00000000 Remote request receiving register RRTRR R/W 00000000 00000000 Receive overrun register ROVRR R/W 00000000 00000000 Receive interrupt enable register RIER R/W 00000000 00000000 Control status register CSR R/W, R 00XXX000 0XXXX0X1 Last event indicator register LEIR R/W XXXXXXXX 000X0000 Receive/ transmit error counter RTEC R 00000000 00000000 Bit timing register BTR R/W X1111111 11111111 000087H 000088H 000089H 00008AH 00008BH 00008CH 00008DH 00008EH 00008FH 007D00H 007D01H 007D02H 007D03H 007D04H 007D05H 007D06H 007D07H 412 CHAPTER 20 CAN CONTROLLER Table 20.3-1 List of overall control registers (2/2) Address Register Abbreviation Access Initial Value CAN1 007D08H IDE register IDER R/W XXXXXXXX XXXXXXXX Transmit RTR register TRTRR R/W 00000000 00000000 Remote frame receive waiting register RFWTR R/W XXXXXXXX XXXXXXXX Transmit interrupt enable register TIER R/W 00000000 00000000 Acceptance mask select register AMSR R/W XXXXXXXX XXXXXXXX 007D09H 007D0AH 007D0BH 007D0CH 007D0DH 007D0EH 007D0FH 007D10H 007D11H 007D12H XXXXXXXX XXXXXXXX 007D13H 007D14H Acceptance mask register 0 AMR0 R/W XXXXXXXX XXXXXXXX 007D15H 007D16H XXXXXXXX XXXXXXXX 007D17H 007D18H Acceptance mask register 1 AMR1 R/W XXXXXXXX XXXXXXXX 007D19H 007D1AH XXXXXXXX XXXXXXXX 007D1BH 413 CHAPTER 20 CAN CONTROLLER 20.4 List of Message Buffers (ID Registers) Table 20.4-1 lists message buffers (ID registers). ■ List of message buffers (ID registers) Table 20.4-1 List of message buffers (ID registers) (1/3) Address Register CAN1 Abbreviati on Acces s Initial Value 007C00H to 007C1FH Generalpurpose RAM -- R/W XXXXXXXX to XXXXXXXX 007C20H ID register 0 IDR0 R/W XXXXXXXX XXXXXXXX 007C21H 007C22H XXXXXXXX XXXXXXXX 007C23H 007C24H ID register 1 IDR1 R/W XXXXXXXX XXXXXXXX 007C25H 007C26H XXXXXXXX XXXXXXXX 007C27H 007C28H ID register 2 IDR2 R/W XXXXXXXX XXXXXXXX 007C29H 007C2AH XXXXXXXX XXXXXXXX 007C2BH 007C2CH ID register 3 IDR3 R/W XXXXXXXX XXXXXXXX 007C2DH 007C2EH XXXXXXXX XXXXXXXX 007C2FH 007C30H ID register 4 IDR4 R/W XXXXXXXX XXXXXXXX 007C31H 007C32H 007C33H 414 XXXXXXXX XXXXXXXX CHAPTER 20 CAN CONTROLLER Table 20.4-1 List of message buffers (ID registers) (2/3) Address Register CAN1 007C34H ID register 5 Abbreviati on IDR5 Acces s R/W Initial Value XXXXXXXX XXXXXXXX 007C35H 007C36H XXXXXXXX XXXXXXXX 007C37H 007C38H ID register 6 IDR6 R/W XXXXXXXX XXXXXXXX 007C39H 007C3AH XXXXXXXX XXXXXXXX 007C3BH 007C3CH ID register 7 IDR7 R/W XXXXXXXX XXXXXXXX 007C3DH 007C3EH XXXXXXXX XXXXXXXX 007C3FH 007C40H ID register 8 IDR8 R/W XXXXXXXX XXXXXXXX 007C41H 007C42H XXXXXXXX XXXXXXXX 007C43H 007C44H ID register 9 IDR9 R/W XXXXXXXX XXXXXXXX 007C45H 007C46H XXXXXXXX XXXXXXXX 007C47H 007C48H ID register 10 IDR10 R/W XXXXXXXX XXXXXXXX 007C49H 007C4AH XXXXXXXX XXXXXXXX 007C4BH 007C4CH ID register 11 IDR11 R/W XXXXXXXX XXXXXXXX 007C4DH 007C4EH XXXXXXXX XXXXXXXX 007C4FH 415 CHAPTER 20 CAN CONTROLLER Table 20.4-1 List of message buffers (ID registers) (3/3) Address Register CAN1 007C50H ID register 12 Abbreviati on IDR12 Acces s R/W Initial Value XXXXXXXX XXXXXXXX 007C51H 007C52H XXXXXXXX XXXXXXXX 007C53H 007C54H ID register 13 IDR13 R/W XXXXXXXX XXXXXXXX 007C55H 007C56H XXXXXXXX XXXXXXXX 007C57H 007C58H ID register 14 IDR14 R/W XXXXXXXX XXXXXXXX 007C59H 007C5AH XXXXXXXX XXXXXXXX 007C5BH 007C5CH ID register 15 IDR15 R/W XXXXXXXX XXXXXXXX 007C5DH 007C5EH 007C5FH 416 XXXXXXXX XXXXXXXX CHAPTER 20 CAN CONTROLLER 20.5 List of Message Buffers (DLC Registers and Data Registers) Table 20.5-1 lists message buffers (DLC registers) and message buffers (data registers). ■ List of message buffers (DLC registers and data registers) Table 20.5-1 List of message buffers (DLC registers and data register) (1/3) Address Register Abbreviation Initial Value Access CAN1 007C60H DLC register 0 DLCR0 R/W XXXXXXXX DLC register 1 DLCR1 R/W XXXXXXXX DLC register 2 DLCR2 R/W XXXXXXXX DLC register 3 DLCR3 R/W XXXXXXXX DLC register 4 DLCR4 R/W XXXXXXXX DLC register 5 DLCR5 R/W XXXXXXXX DLC register 6 DLCR6 R/W XXXXXXXX DLC register 7 DLCR7 R/W XXXXXXXX DLC register 8 DLCR8 R/W XXXXXXXX DLC register 9 DLCR9 R/W XXXXXXXX DLC register 10 DLCR10 R/W XXXXXXXX 007C61H 007C62H 007C63H 007C64H 007C65H 007C66H 007C67H 007C68H 007C69H 007C6AH 007C6BH 007C6CH 007C6DH 007C6EH 007C6FH 007C70H 007C71H 007C72H 007C73H 007C74H 007C75H 417 CHAPTER 20 CAN CONTROLLER Table 20.5-1 List of message buffers (DLC registers and data register) (2/3) Address Register Abbreviation Initial Value Access CAN1 DLC register 11 DLCR11 R/W XXXXXXXX DLC register 12 DLCR12 R/W XXXXXXXX DLC register 13 DLCR13 R/W XXXXXXXX DLC register 14 DLCR14 R/W XXXXXXXX DLC register 15 DLCR15 R/W XXXXXXXX 007C80H to 007C87H Data register 0 (8 bytes) DTR0 R/W XXXXXXXX to XXXXXXXX 007C88H to 007C8FH Data register 1 (8 bytes) DTR1 R/W XXXXXXXX to XXXXXXXX 007C90H to 007C97H Data register 2 (8 bytes) DTR2 R/W XXXXXXXX to XXXXXXXX 007C98H to 007C9FH Data register 3 (8 bytes) DTR3 R/W XXXXXXXX to XXXXXXXX 007CA0H to 007CA7H Data register 4 (8 bytes) DTR4 R/W XXXXXXXX to XXXXXXXX 007CA8H to 007CAFH Data register 5 (8 bytes) DTR5 R/W XXXXXXXX to XXXXXXXX 007CB0H to 007CB7H Data register 6 (8 bytes) DTR6 R/W XXXXXXXX to XXXXXXXX 007CB8H to 007CBFH Data register 7 (8 bytes) DTR7 R/W XXXXXXXX to XXXXXXXX 007C76H 007C77H 007C78H 007C79H 007C7AH 007C7BH 007C7CH 007C7DH 007C7EH 007C7FH 418 CHAPTER 20 CAN CONTROLLER Table 20.5-1 List of message buffers (DLC registers and data register) (3/3) Address Register Abbreviation Initial Value Access CAN1 007CC0H to 007CC7H Data register 8 (8 bytes) DTR8 R/W XXXXXXXX to XXXXXXXX 007CC8H to 007CCFH Data register 9 (8 bytes) DTR9 R/W XXXXXXXX to XXXXXXXX 007CD0H to 007CD7H Data register 10 (8 bytes) DTR10 R/W XXXXXXXX to XXXXXXXX 007CD8H to 007CDFH Data register 11 (8 bytes) DTR11 R/W XXXXXXXX to XXXXXXXX 007CE0H to 007CE7H Data register 12 (8 bytes) DTR12 R/W XXXXXXXX to XXXXXXXX 007CE8H to 007CEFH Data register 13 (8 bytes) DTR13 R/W XXXXXXXX to XXXXXXXX 007CF0H to 007CF7H Data register 14 (8 bytes) DTR14 R/W XXXXXXXX to XXXXXXXX 007CF8H to 007CFFH Data register 15 (8 bytes) DTR15 R/W XXXXXXXX to XXXXXXXX 419 CHAPTER 20 CAN CONTROLLER 20.6 Classifying the CAN Controller Registers There are three types of CAN controller registers: • Overall control registers • Message buffer control registers • Message buffers ■ Overall control registers The overall control registers are the following four registers: • Control status register (CSR) • Last event indicator register (LEIR) • Receive and transmit error counter (RTEC) • Bit timing register (BTR) ■ Message buffer control registers The message buffer control registers are the following 14 registers: • Message buffer valid register (BVALR) • IDE register (IDER) • Transmission request register (TREQR) • Transmission RTR register (TRTRR) • Remote frame receiving wait register (RFWTR) • Transmission cancel register (TCANR) • Transmission complete register (TCR) • Transmission interrupt enable register (TIER) • Reception complete register (RCR) • Remote request receiving register (RRTRR) • Receive overrun register (ROVRR) • Reception interrupt enable register (RIER) • Acceptance mask select register (AMSR) • Acceptance mask registers 0 and 1 (AMR0 and AMR1) ■ Message buffers The message buffers are the following three registers: • ID register x (x = 0 to 15) (IDRx) • DLC register x (x = 0 to 15) (DLCRx) • Data register x (x = 0 to 15) (DTRx) 420 CHAPTER 20 CAN CONTROLLER 20.6.1 Control Status Register (CSR) The lower 8 bits with the control status register (CSR) is prohibited from executing any bit manipulation instructions (Read-Modify-Write instructions). Only in the case of HALT bits unchanged, use any bit manipulation instructions without problems (initialization of the macro instruction etc.). ■ Control status register (CSR) (lower) Figure 20.6-1 Configuration of the control status register (lower byte) Address: 7 6 5 4 3 2 1 0 CSRn (lower) Initial value 0 X X X X 0 X 1B CAN1: 007D00H R/W - - - - R/W W R/W bit 0 HALT Bus Operation styop bit 0 Write: Cancels bus operation stop Read: Bus operation not in stop mode 1 Write: Stops bus operation Read: Bus operation in stop mode bit 1 Reserved 0 bit 2 NIE Reserved bit Do not write "1" to this bit Node status transition interrupt enable 0 Node status transition interrupt enabled 1 Node status transition interrupt disabled bit 7 TOE R/W : Readable and writable W : Write only X : Undefined value - : Undefined : Initial value Transmit output enable 0 General-purpose port pin 1 Transmit pin of CAN controller n = 0, 1, 2 421 CHAPTER 20 CAN CONTROLLER ■ Control status register (CSR-lower) contents Table 20.6-1 Function of each bit of the control status register (lower) Bit Name Function bit 7 TOE: Transmit output enable bit Writing 1 to this bit switches from a general-purpose port pin to a transmit pin of the CAN controller. 0: General-purpose port pin 1: Transmit pin of CAN controller bit 6 to 3 Undefined bit 2 NIE: Node status transition flag bit This bit enables or disables a node status transition interrupt (when NT = 1). 0: Node status transition interrupt disabled 1: Node status transition interrupt enabled bit1 Reserved bit This is a reserved bit. Do not write "1" to this bit. bit 0 HALT: Bus operation stop bit This bit controls the bus halt. The halt state of the bus can be checked by reading this bit. Writing to this bit 0: Cancels bus halt 1: Halt bus Reading this bit 0: Bus operation not in stop state 1: Bus operation in stop state Note: When write 0 to this bit during the node status is Bus Off, ensure that 1 is written to this bit. Example program: switch ( IO_CANCT0.CSR.bit.NS ) { case 0 : /* error active */ break; case 1 : /* warning */ break; case 2 : /* error passive */ break; default : /* bus off */ for ( i=0; ( i <= 500 ) && ( IO_CANCT0.CSR.bit.HALT == 0); i++); IO_CANCT0.CSR.word = 0x0084; /* HALT = 0 */ break; } Note: The variable "i" is used for fail-safe. 422 CHAPTER 20 CAN CONTROLLER ■ Control status register (CSR) (upper) Figure 20.6-2 Configuration of the control status register (upper byte) Address: 15 14 13 12 11 10 9 8 CAN1: 007D01H CSRn (upper) Initial value 00XXX000B R R - - - R/W R R bit 9 NS1 bit 8 NS0 Node Status 0 0 Error active 0 1 Warning (error active) 1 0 Error passive 0 0 Bus off bit 10 NT Node status transition flag 0 No change 1 Status changed bit 14 RS Receive status bit 0 Message not being received 1 Message being received bit 15 TS R/W : R : Read only X : Undefined value : Undefined : Initial value - Readable and writable Transmit status bit 0 Message not being transmitted 1 Message being transmitted n = 0, 1, 2 423 CHAPTER 20 CAN CONTROLLER ■ Control status register (CSR-upper) contents Table 20.6-2 Function of each bit of the control status register (upper) Bit Name Function bit 15 TS: Transmit status bit This bit indicates whether a message is being transmitted. 0: Message not being transmitted 1: Message being transmitted This bit is 0 even while error and overload frames are transmitted. bit 14 RS: Receive status bit This bit indicates whether a message is being received. 0: Message not being received 1: Message being received While a message is on the bus, this bit becomes 1. Therefore, this bit is also 1 while a message is being transmitted. This bit does not necessarily indicates whether a receiving message passes through the acceptance filter. As a result, when this bit is 0, it implies that the bus operation is stopped (HALT = 0); the bus is in the intermission/bus idle or a error/overload frame is on the bus. bit 13 to 11 Undefined bit 10 NT: Node status transition flag If the node status is changed to increment, or from Bus Off to Error Active, this bit is set to 1. In other words, the NT bit is set to 1 if the node status is changed from Error Active (00) to Warning (01), from Warning (01) to Error Passive (10), from Error Passive (10) to Bus Off (11), and from Bus Off (11) to Error Active (00). Numbers in parentheses indicate the values of NS1 and NS0 bits. When the node status transition interrupt enable bit (NIE) is 1, an interrupt is generated. Writing 0 sets the NT bit to 0. Writing 1 to the NT bit is ignored. 1 is read when a Read Modify Write instruction is performed. bit 9, 8 NS1, NS0: Node status bit 1 and 0 These bits indicate the current node status. See Table 20.6-3 below for details. Table 20.6-3 Correspondence between NS1 and NS0 and node status NS1 NS0 Node Status 0 0 Error active 0 1 Warning (error active) 1 0 Error passive 1 1 Bus off Note: Warning (error active) is included in the error active in CAN Specification 2.0B for the node status, however, indicates that the transmit error counter or receive error counter has exceeded 96. The node status change diagram is shown in Figure 20.6-3. 424 CHAPTER 20 CAN CONTROLLER Figure 20.6-3 Node status transition diagram Hardware reset REC: Receive error counter TEC: Transmit error counter Error active After 0 has been written to the HALT bit of the register (CSR), continuous 11-bit High levels (recessive bits) are input 128 times to the receive input pin (RX). REC >= 96 or TEC >= 96 REC < 96 and TEC < 96 Warning (Error active) REC >= 128 or TEC >= 128 REC < 128 and TEC < 128 Error passive TEC >= 256 Bus off (HALT =1) 425 CHAPTER 20 CAN CONTROLLER 20.6.2 Bus Operation Stop Bit (HALT = 1) The bus operation stop bit sets or cancels stopping of bus operation, or indicates its status ■ Conditions for setting bus operation stop (HALT=1) There are three conditions for setting bus operation stop (HALT = 1): • After hardware reset • When node status changed to bus off • By writing 1 to HALT Note: The bus operation should be stopped by writing 1 to HALT before the F2MC-16LX is changed in lowpower consumption mode (stop mode and timebase timer mode). If transmission is in progress when 1 is written to HALT, the bus operation is stopped (HALT = 1) after transmission is terminated. If reception is in progress when 1 is written to HALT, the bus operation is stopped immediately (HALT = 1). If received messages are being stored in the message buffer (x), stop the bus operation (HALT = 1) after storing the messages. To check whether the bus operation has stopped, always read the HALT bit. ■ Conditions for canceling bus operation stop (HALT = 0) • By writing 0 to HALT Note: - Canceling the bus operation stop after hardware reset or by writing 1 to HALT as above conditions is performed after 0 is written to HALT and continuous 11-bit High levels (recessive bits) have been input to the receive input pin (RX) (HALT = 0). - Canceling the bus operation stop when the node status is changed to bus off as above conditions is performed after 0 is written to HALT and continuous 11-bit High levels (recessive bits) have been input 128 times to the receive input pin (RX) (HALT = 0). Then, the values of both transmit and receive error counters reach 0 and the node status is changed to error active. - When write 0 to HALT during the node status is Bus Off, ensure that 1 is written to this bit. ■ State during bus operation stop (HALT = 1) • The bus does not perform any operation, such as transmission and reception. • The transmit output pin (TX) outputs a High level (recessive bit). • The values of other registers and error counters are not changed. Note: The bit timing register (BTR) should be set during bus operation stop (HALT = 1). 426 CHAPTER 20 CAN CONTROLLER 20.6.3 Last Event Indicator Register (LEIR) This register indicates the last event. The NTE, TCE, and RCE bits are exclusive. When the corresponding bit of the last event is set to 1, other bits are set to 0s. ■ Last event indicator register (LEIR) Figure 20.6-4 Configuration of the last event indicator register (LEIR) Address: 7 6 5 4 3 2 1 0 LEIRn Initial value 0 0 0 X 0 0 0 0B CAN1: 007D02H R/W R/W R/W - R/W R/W R/W R/W bit 3 bit 2 bit 1 bit 0 MBP3 MBP2 MBP1 MBP0 Message buffer pointer bits 0 to 15 (initial value: "0000") bit 5 RCE Receive completion event bit read write 0 - clear bit 1 receive completion ignored bit 6 Transmit completion event bit TCE read write 0 - clear bit 1 transmit completion ignored bit 7 Node status transition event bit NTE read write R/W : Readable and writable 0 - clear bit X : Undefined value 1 transition event ignored : Undefined : Initial value - n = 0, 1, 2 427 CHAPTER 20 CAN CONTROLLER ■ Last event indicator register (LEIR) contents Table 20.6-4 Function of each bit of the last event indicator register Bit Name Function bit 3 to 0 MBP3, MBP2, MBP1, MBP0 bit 4 Undefined bit 5 RCE: Receive completion event bit When this bit is 1, it indicates that receive completion is the last event. This bit is set to 1 at the same time as any one of the bits of the receive complete register (RCR). This bit is also set to 1 irrespective of the settings of the bits of the receive interrupt enable register (RIER). Writing 0 sets this bit to 0. Writing 1 to this bit is ignored. 1 is read when a Read Modify Write instruction is performed. When this bit is set to 1, the MBP3 to MBP0 bits are used to indicate the message buffer number completing the receive operation. bit 6 TCE: Transmit completion event bit When this bit is 1, it indicates that transmit completion is the last event. This bit is set to 1 at the same time as any one of the bits of the transmit completion register (TCR). This bit is also set to 1, irrespective of the settings of the bits of the transmit interrupt enable register (TIER). Writing 0 sets this bit to 0. Writing 1 to this bit is ignored. 1 is read when a Read Modify Write instruction is performed. When this bit is set to 1, the MBP3 to MBP0 bits are used to indicate the message buffer number completing the transmit operation. bit 7 NTE: Node status transition event bit When this bit is 1, node status transition is the last event. This bit is set to 1 at the same time the NT bit of the control status register (CSR) is set. This bit is also set to 1 irrespective of the setting of the node status transition interrupt enable bit (NIE) of CSR. Writing 0 to this bit sets the NTE bit to 0. Writing 1 to this bit is ignored. 1 is read when a Read Modify Write instruction is executed. 428 When the TCE or RCE bit is set to 1, these bits indicate the corresponding numbers of the message buffers (0 to 15). If the NTE bit is set to 1, these bits have no meaning. Writing 0 sets these bits to 0s. Writing 1 to these bits is ignored. 1s are read when a Read Modify Write instruction is performed. If LEIR is accessed within an CAN interrupt handler, the event causing the interrupt is not necessarily the same as indicated by LEIR. In the time from interrupt request to the LEIR access by the interrupt handler there may occur other CAN events. CHAPTER 20 CAN CONTROLLER 20.6.4 Receive and Transmit Error Counters (RTEC) The receive and transmit error counters indicate the counts for transmission errors and reception errors defined in the CAN specifications. These registers can only be read. ■ Receive and transmit error counters (RTEC) Figure 20.6-5 Configuration of the receive and transmit error counters Address: CAN1: 007D05H Address: CAN1: 007D04H 15 14 13 12 11 10 9 8 TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 R R R R R R R R 7 6 5 4 3 2 1 0 REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 R R R R R R R R RTECn (upper) Initial value 00000000B RTECn (lower) Initial value 0 0 0 0 0 0 0 0B n = 0, 1, 2 R: Read only ■ Receive and transmit error counters (RTEC) contents Table 20.6-5 Function of each bit of the receive and transmit error counters (RTEC) Bit Name Function bit 15 to 8 TEC7 to 0: Transmit error counter bits These are transmit error counters. TEC7 to TEC0 values indicate 0 to 7 when the counter value is more than 256, and the subsequent increment is not counted for counter value. In this case, Bus Off is indicated for the node status (NS1 and NS0 of control status register CSR = 11). bit 7 to 0 REC7 to 0: Receive error counter bits These are receive error counters. REC7 to REC0 values indicate 0 to 7 when the counter value is more than 256, and the subsequent increment is not counted for counter value. In this case, Error Passive is indicated for the node status (NS1 and NS0 of control status register CSR = 10). 429 CHAPTER 20 CAN CONTROLLER 20.6.5 Bit Timing Register (BTR) Bit timing register (BTR) stores the prescaler and bit timing setting. ■ Bit timing register (BTR) Figure 20.6-6 Configuration of the bit timing register (BTR) Address: 15 CAN1: 007D07H Address: 14 12 11 10 9 8 - TS2.2 TS2.1 TS2.0 TS1.3 TS1.2 TS1.1 TS1.0 - R/W R/W R/W R/W R/W R/W R/W 7 CAN1: 007D06H 13 6 5 4 3 2 1 0 RSJ1 RSJ0 PSC5 PSC4 PSC3 REC2 PSC1 PSC0 R/W R/W R/W R/W R/W R/W R/W R/W R/W X BTRn (upper) Initial value X 1 1 1 1 1 1 1B BTRn (lower) Initial value 11111111B : Readable and writable : Undefined value n = 0, 1, 2 Note: This register should be set during bus operation stop (HALT = 1). ■ Bit timing register (BTR) contents Table 20.6-6 Function of each bit of the bit timing register (BTR) Bit Name Function bit 15 Undefined bit 14 to 12 TS2.2 to 2.0: Time segment2 setting bits These bits define the number of the time quanta (TQ’s) for the time segment 2 (TSEG2). The time segment 2 is equal to the phase buffer segment 2 (PHASE_SEG2) in the CAN specification. bit 11 to 8 TS1.3 to 1.0: Time segment1 setting bits These bits define the number of the time quanta (TQ’s) for the time segment 1 (TSEG1). The time segment 1 is equal to the propagation segment (PROP_SEG) + phase buffer segment 1 (PHASE_SEG1) in the CAN specification. bit 7, 6 RSJ1,0: Resynchronization jump width setting bits These bits define the number of the time quanta (TQ’s) for the resynchronization jump width. bit 5 to 0 PSC5 to 0: Prescaler setting bits These bits define the time quanta (TQ) of the CAN controller. (see below for details.) 430 CHAPTER 20 CAN CONTROLLER ■ Prescaler settings The bit time segments defined in the CAN specification, and the CAN controller are shown in Figure 20.67 and Figure 20.6-8 respectively. Figure 20.6-7 Bit time segment in CAN specification Nominal bit time SYNC_SEG PROP_SEG PHASE_SEG1 PHASE_SEG2 Sample point Figure 20.6-8 Bit time segment in CAN controller Nominal bit time SYNC_SEG TSEG1 TSEG2 Sample point The relationship between PSC = PSC5 to PSC0, TSI = TS1.3 to TS1.0, TS2 = TS2.2 to TS1.0, and RSJ = RSJ1 and RSJ0 when the input clock (CLK), time quanta (TQ), bit time (BT), synchronous segment (SYNC_SEG), time segment 1 and 2 (TSEG1 and TSEG2), and resynchronization jump width [(RSJ1 and RSJ0) +1] frequency division is shown below. The input clock is supplied with the machine clock. TQ BT = (PSC + 1) x CLK = SYNC_SEG + TSEG1 + TSEG2 = (1 + (TS1 + 1) + (TS2 +1)) x TQ = (3 + TS1 +TS2) x TQ RSJW = (RSJ + 1) x TQ For correct operation, the following conditions should be met. 431 CHAPTER 20 CAN CONTROLLER Device with "G" suffix: For 1 PSC TSEG1 TSEG1 TSEG2 TSEG2 For PSC = 0: TSEG1 TSEG2 TSEG2 63: 2TQ RSJW 2TQ RSJW 5TQ 2TQ RSJW Device without "G" suffix: For 1 PSC 63: TSEG1 RSJW TSEG2 RSJW + 2TQ For PSC = 0: TSEG1 5TQ TSEG2 RSJW + 2TQ In order to meet the bit timing requirements defined in the CAN specification, additions have to be met, e.g. the propagation delay has to be considered. 432 CHAPTER 20 CAN CONTROLLER 20.6.6 Message Buffer Valid Register (BVALR) Message buffer valid register (BVALR) stores the validity of the message buffers or displays their state. ■ Message buffer valid register (BVALR) Figure 20.6-9 Configuration of the message buffer valid register (BVALR) Address: CAN1: 000081 H 15 14 13 12 11 10 9 8 BVAL15 BVAL14 BVAL13 BVAL12 BVAL11 BVAL10 BVAL9 BVAL8 BVALR1 (upper) Initial value 00000000B R/W R/W R/W R/W R/W R/W R/W R/W Address: CAN1: 000080 H 7 6 5 4 3 2 1 0 BVAL7 BVAL6 BVAL5 BVAL4 BVAL3 BVAL2 BVAL1 BVAL0 R/W R/W R/W R/W R/W R/W R/W R/W BVALR1 (lower) Initial value 00000000B R/W : Readable and Writable 0: Message buffer (x) invalid 1: Message buffer (x) valid If the message buffer (x) is set to invalid, it will not transmit or receive messages. If the buffer is set to invalid during transmission operating, it becomes invalid (BVALx = 0) after the transmission is completed or terminated by an error. If the buffer is set to invalid during reception operating, it immediately becomes invalid (BVALx = 0). If received messages are stored in a message buffer (x), the message buffer (x) is invalid after storing the messages. Note: x indicates a message buffer number (x = 0 to 15). When invaliding a message buffer (x) by writing 0 to a bit (BVALx), execution of a bit manipulation instruction is prohibited until the bit is set to 0. To invalidate the message buffer (by setting the BVALR: BVAL bit to 0) while the CAN controller is operating for CAN communication (the read value of the CSR: HALT bit is 0 and the CAN controller is operating for CAN bus communication to enable transmission and reception), follow the procedure in Section "20.15 Precautions when Using CAN Controller". 433 CHAPTER 20 CAN CONTROLLER 20.6.7 IDE register (IDER) This register stores the frame format used by the message buffers (x) during transmission/reception. ■ IDE register (IDER) Figure 20.6-10 Configuration of the IDE register (IDER) Address: CAN1: 007D09H 15 14 13 12 11 10 9 8 IDE15 IDE14 IDE13 IDE12 IDE11 IDE10 IDE9 IDE8 IDER1(upper) Initial value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W Address: CAN1: 007D08H 7 6 5 4 3 2 IDE7 IDE6 IDE5 IDE4 IDE3 IDE2 1 0 IDE1 IDE0 R/W R/W R/W R/W R/W R/W R/W R/W IDER1 (lower) Initial value X X X X X X X XB R/W : Readable and Writable X : Undefined value 0: The standard frame format (ID11 bit) is used for the message buffer (x). 1: The extended frame format (ID29 bit) is used for the message buffer (x). Note: This register should be set when the message buffer (x) is invalid (BVALx of the message buffer valid register (BVALR) = 0). Setting when the buffer is valid (BVALx = 1) may cause unnecessary received messages to be stored. To invalidate the message buffer (by setting the BVALR: BVAL bit to 0) while the CAN controller is operating for CAN communication (the read value of the CSR: HALT bit is 0 and the CAN controller is operating for CAN bus communication to enable transmission and reception), follow the procedure in Section "20.15 Precautions when Using CAN Controller". 434 CHAPTER 20 CAN CONTROLLER 20.6.8 Transmission Request Register (TREQR) Transmission request register (TREQR) stores transmission requests to the message buffers (x) or displays their state. ■ Transmission request register (TREQR) Figure 20.6-11 Configuration of the transmission request register (TREQR) Address: 15 CAN1: 000083 H TREQ15 TREQ14 TREQ13 TREQ12 TREQ11 TREQ10 TREQ9 TREQ8 14 13 12 11 10 9 8 TREQR1 (upper) Initial value 0 0 0 0 0 0 0 0B R/W R/W R/W R/W R/W R/W R/W R/W Address: CAN1: 000082 H 7 6 5 4 3 2 1 0 TREQ7 TREQ6 TREQ5 TREQ4 TREQ3 TREQ2 TREQ1 TREQ0 R/W R/W R/W R/W R/W R/W R/W R/W TREQR1 (lower) Initial value 0 0 0 0 0 0 0 0B R/W : Readable and Writable When 1 is written to TREQx, transmission to the message buffer (x) starts. If RFWTx of the remote frame receiving wait register (RFWTR) *1 is 0, transmission starts immediately. However, if RFWTx = 1, transmission starts after waiting until a remote frame is received (RRTRx of the remote request receiving register (RRTRR)*1 becomes 1). Transmission starts already 1 when 1 is written to TREQx. *2 immediately even when RFWTx = 1, if RRTRx is *1: For RFWTR and TRTRR, see Sections "20.6.9 Transmission RTR Register (TRTRR)" and "20.6.10 Remote Frame Receiving Wait Register (RFWTR)". *2: For cancellation of transmission, see Sections "20.6.11 Transmission Cancel Register (TCANR)" and " 20.6.12 Transmission Complete Register (TCR)". Writing 0 to TREQx is ignored. 0 is read when a Read Modify Write instruction is performed. If clearing (to 0) at completion of the transmit operation and setting by writing 1 are concurrent, clearing is preferred. If 1 is written to more than one bit, transmission is performed, starting with the lower-numbered message buffer (x). TREQx is 1 while transmission is pending, and becomes 0 when transmission is completed or canceled. 435 CHAPTER 20 CAN CONTROLLER 20.6.9 Transmission RTR Register (TRTRR) This register stores the RTR (Remote Transmission Request) bits for the message buffers (x). ■ Transmission RTR register (TRTRR) Figure 20.6-12 Configuration of the transmission RTR register (TRTRR) Address: CAN1: 007D0BH 15 14 13 12 11 10 9 8 TRTR15 TRTR14 TRTR13 TRTR12 TRTR11 TRTR10 TRTR9 TRTR8 TRTRR1 (upper) Initial value 0 0 0 0 0 0 0 0B R/W R/W R/W R/W R/W R/W R/W R/W Address: 7 6 5 4 3 2 1 0 TRTR7 TRTR6 TRTR5 TRTR4 TRTR3 TRTR2 TRTR1 TRTR0 CAN1: 007D0AH R/W R/W R/W R/W R/W R/W R/W R/W R/W : Readable and Writable ■ Register Function 0: Data frame. 1: Remote frame. 436 TRTRR1 (lower) Initial value 0 0 0 0 0 0 0 0B CHAPTER 20 CAN CONTROLLER 20.6.10 Remote Frame Receiving Wait Register (RFWTR) Remote frame receiving wait register (RFWTR) stores the conditions for starting transmission when a request for data frame transmission is set (TREQx of the transmission request register (TREQR) is 1 and TRTRx of the transmitting RTR register (TRTRR) is 0). • 0: Transmission starts immediately • 1: Transmission starts after waiting until remote frame received (RRTRx of remote request receiving register (RRTRR) becomes 1) ■ Remote frame receiving wait register (RFWTR) Figure 20.6-13 Configuration of the remote frame receiving wait register (RFWTR) Address: CAN1: 007D0DH 15 14 13 12 11 10 9 8 RFWT15 RFWT14 RFWT13 RFWT12 RFWT11 RFWT10 RFWT9 RFWT8 RFWTR1 (upper) Initial value X X X X X X X XB R/W R/W R/W R/W R/W R/W R/W R/W Address: CAN1: 007D0CH 7 6 5 4 3 2 1 0 RFWT7 RFWT6 RFWT5 RFWT4 RFWT3 RFWT2 RFWT1 RFWT0 R/W R/W R/W R/W R/W R/W R/W R/W RFWTR1 (lower) Initial value XXXXXXXXB R/W : Readable and Writable X : Undefined value Note: Transmission starts immediately if RRTRx is already 1 when a request for transmission is set. For remote frame transmission, do not set RFWTx to 1. 437 CHAPTER 20 CAN CONTROLLER 20.6.11 Transmission Cancel Register (TCANR) When 1 is written to TCANx, this register cancels a pending request for transmission to the message buffer (x). At completion of cancellation, TREQx of the transmission request register (TREQR) becomes 0. Writing 0 to TCANx is ignored. This is a write-only register and its read value is always 0. ■ Transmission cancel register (TCANR) Figure 20.6-14 Configuration of the transmission cancel register (TCANR) Address: CAN1: 000085 H Address: CAN1: 000084 H 15 438 13 12 11 10 9 8 TCAN15 TCAN14 TCAN13 TCAN12 TCAN11 TCAN10 TCAN9 TCAN8 W W W W W W W W 7 6 5 4 3 2 1 0 TCAN7 TCAN6 TCAN5 TCAN4 TCAN3 TCAN2 TCAN1 TCAN0 W W : Write only 14 W W W W W W W TCANR1 (upper) Initial value 00000000 B TCANR1 (lower) Initial value 00000000 B CHAPTER 20 CAN CONTROLLER 20.6.12 Transmission Complete Register (TCR) At completion of transmission by the message buffer (x), the corresponding TCx becomes 1. If TIEx of the transmission complete interrupt enable register (TIER) is 1, an interrupt occurs. ■ Transmission complete register (TCR) Figure 20.6-15 Configuration of the transmission complete register (TCR) Address: CAN1: 000087 H 15 14 13 12 11 10 9 8 TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8 TCR1 (upper) Initial value 00000000B R/W R/W R/W R/W R/W R/W R/W R/W Address: CAN1: 000086 H 7 6 5 4 3 2 1 0 TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 R/W R/W R/W R/W R/W R/W R/W R/W TCR1 (lower) Initial value 00000000B R/W : Readable and Writable ● Conditions for TCx = 0 • Write 0 to TCx. • Write 1 to TREQx of the transmission request register (TREQR). After the completion of transmission, write 0 to TCx to set it to 0. Writing 1 to TCx is ignored. 1 is read when a Read Modify Write instruction is performed. Note: If setting to 1 by completion of the transmit operation and clearing to 0 by writing occur at the same time, the bit is set to 1. 439 CHAPTER 20 CAN CONTROLLER 20.6.13 Transmission Interrupt Enable Register (TIER) This register enables or disables the transmission interrupt by the message buffer (x). The transmission interrupt is generated at transmission completion (when TCx of the transmission complete register (TCR) is 1). ■ Transmission interrupt enable register (TIER) Figure 20.6-16 Configuration of the transmission interrupt enable register (TIER) Address: CAN1: 007D0FH 15 14 13 12 11 10 9 8 TIE15 TIE14 TIE13 TIE12 TIE11 TIE10 TIE9 TIE8 TIER1 (upper) Initial value 00000000B R/W R/W R/W R/W R/W R/W R/W R/W Address: CAN1: 007D0EH 7 6 5 4 3 2 TIE7 TIE6 TIE5 TIE4 TIE3 TIE2 1 0 TIE1 TIE0 R/W R/W R/W R/W R/W R/W R/W R/W R/W : Readable and Writable 0: Transmission interrupt disabled. 1: Transmission interrupt enabled. 440 TIER1 (lower) Initial value 00000000B CHAPTER 20 CAN CONTROLLER 20.6.14 Reception Complete Register (RCR) At completion of storing received message in the message buffer (x), RCx becomes 1. If RIEx of the reception complete interrupt enable register (RIER) is 1, an interrupt occurs. ■ Reception complete register (RCR) Figure 20.6-17 Configuration of the reception complete register (RCR) Address: CAN1: 000089 H 15 14 13 12 11 10 9 8 RC15 RC14 RC13 RC12 RC11 RC10 RC9 RC8 RCR1 (upper) Initial value 00000000B R/W R/W R/W R/W R/W R/W R/W R/W Address: CAN1: 000088 H 7 6 5 4 3 2 1 0 RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 R/W R/W R/W R/W R/W R/W R/W R/W RCR1 (lower) Initial value 00000000B R/W : Readable and Writable ● Conditions for RCx = 0 Write 0 to RCx. After completion of handling received message, write 0 to RCx to set it to 0. Writing 1 to RCx is ignored. 1 is read when a Read Modify Write instruction is performed. Note: If setting to 1 by completion of the receive operation and clearing to 0 by writing occur at the same time, the bit is set to 1. 441 CHAPTER 20 CAN CONTROLLER 20.6.15 Remote Request Receiving Register (RRTRR) After a remote frame is stored in the message buffer (x), RRTRx becomes 1 (at the same time as RCx setting to 1). ■ Remote request receiving register (RRTRR) Figure 20.6-18 Configuration of the remote request receiving register (RRTRR) Address: CAN1: 00008B H 15 14 13 12 11 10 9 8 RRTR15 RRTR14 RRTR13 RRTR12 RRTR11 RRTR10 RRTR9 RRTR8 RRTRR1 (upper) Initial value 0 0 0 0 0 0 0 0B R/W R/W R/W R/W R/W R/W R/W R/W Address: CAN1: 00008A H 7 6 5 4 3 2 1 0 RRTR7 RRTR6 RRTR5 RRTR4 RRTR3 RRTR2 RRTR1 RRTR0 R/W R/W R/W R/W R/W R/W R/W R/W RRTRR1 (lower) Initial value 0 0 0 0 0 0 0 0B R/W : Readable and Writable ● Conditions for RRTRx = 0 • Write 0 to RRTRx. • After a received data frame is stored in the message buffer (x) (at the same time as RCx setting to 1). • Transmission by the message buffer (x) is completed (TCx of the transmission complete register (TCR) is 1). Writing 1 to RRTRx is ignored. 1 is read when a Read Modify Write instruction is performed. Note: If setting to 1 by completion of the receive operation and clearing to 0 by writing occur at the same time, the bit is set to 1. 442 CHAPTER 20 CAN CONTROLLER 20.6.16 Receive Overrun Register (ROVRR) If RCx of the reception complete register (RCR) is 1 when completing storing of a received message in the message buffer (x), ROVRx becomes 1, indicating that reception has overrun. ■ Receive overrun register (ROVRR) Figure 20.6-19 Configuration of the receive overrun register (ROVRR) Address: CAN1: 00008DH 15 14 13 12 11 10 9 8 ROVR15 ROVR14 ROVR13 ROVR12 ROVR11 ROVR10 ROVR9 ROVR8 ROVRR1 (upper) Initial value 0 0 0 0 0 0 0 0B R/W R/W R/W R/W R/W R/W R/W R/W Address: CAN1: 00008CH 7 6 5 4 3 2 1 0 ROVR7 ROVR6 ROVR5 ROVR4 ROVR3 ROVR2 ROVR1 ROVR0 R/W R/W R/W R/W R/W R/W R/W R/W ROVRR1 (lower) Initial value 0 0 0 0 0 0 0 0B R/W : Readable and Writable Writing 0 to ROVRx results in ROVRx = 0. Writing 1 to ROVRx is ignored. After checking that reception has overrun, write 0 to ROVRx to set it to 0. 1 is read when a Read Modify Write instruction is performed. Note: If setting to 1 by completion of the receive operation and clearing to 0 by writing occur at the same time, the bit is set to 1. 443 CHAPTER 20 CAN CONTROLLER 20.6.17 Reception Interrupt Enable Register (RIER) Reception interrupt enable register (RIER) enables or disables the reception interrupt by the message buffer (x). The reception interrupt is generated at reception completion (when RCx of the reception completion register (RCR) is 1). ■ Reception interrupt enable register (RIER) Figure 20.6-20 Configuration of the reception interrupt enable register (RIER) Address: 15 CAN1: 0000BFH 14 13 12 11 10 9 8 RIE15 RIE14 RIE13 RIE12 RIE11 RIE10 RIE9 RIE8 RIER1 (upper) Initial value 00000000B R/W R/W R/W R/W R/W R/W R/W R/W Address: 7 CAN1: 0000BEH 6 5 4 3 2 1 0 RIE7 RIE6 RIE5 RIE4 RIE3 RIE2 RIE1 RIE0 R/W R/W R/W R/W R/W R/W R/W R/W R/W : Readable and Writable 0: Reception interrupt disabled. 1: Reception interrupt enabled. 444 RIER1 (lower) Initial value 00000000B CHAPTER 20 CAN CONTROLLER 20.6.18 Acceptance Mask Select Register (AMSR) This register selects masks (acceptance mask) for comparison between the received message ID’s and the message buffer ID’s. ■ Acceptance mask select register (AMSR) Figure 20.6-21 Configuration of the acceptance mask select register (AMSR) Address: CAN1: 007D10H 7 6 5 4 3 2 1 0 AMS AMS AMS AMS AMS AMS AMS AMS 3.1 3.0 2.1 2.0 1.1 1.0 0.1 0.0 AMSR1 Byte 0 Initial value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W Address: CAN1: 007D11H 15 14 13 12 11 10 9 8 AMS AMS AMS AMS AMS AMS AMS AMS 7.1 7.0 6.1 6.0 5.1 5.0 4.1 4.0 R/W R/W R/W R/W R/W R/W R/W R/W Address: CAN1: 007D12H 7 6 5 4 3 2 1 0 AMS AMS AMS AMS AMS AMS AMS AMS 11.1 11.0 10.1 10.0 9.1 9.0 8.1 8.0 AMSR1 Byte 1 Initial value XXXXXXXXB AMSR1 Byte 2 Initial value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W Address: CAN1: 007D13H 15 14 13 12 11 10 9 8 AMS AMS AMS AMS AMS AMS AMS AMS 15.1 15.0 14.1 14.0 13.1 13.0 12.1 12.0 R/W R/W R/W R/W R/W R/W R/W R/W AMSR1 Byte 3 Initial value XXXXXXXXB R/W : Readable and Writable X : Undefined value Table 20.6-7 Selection of acceptance mask AMSx.1 AMSx.0 Acceptance Mask 0 0 Full-bit comparison 0 1 Full-bit mask 1 0 Acceptance mask register 0 (AMR0) 1 1 Acceptance mask register 1 (AMR1) 445 CHAPTER 20 CAN CONTROLLER Note: AMSx.1 and AMSx.0 should be set when the message buffer (x) is invalid (BVALx of the message buffer valid register (BVALR) is 0). Setting when the buffer is valid (BVALx = 1) may cause unnecessary received messages to be stored. To invalidate the message buffer (by setting the BVALR: BVAL bit to 0) while the CAN controller is operating for CAN communication (the read value of the CSR: HALT bit is 0 and the CAN controller is operating for CAN bus communication to enable transmission and reception), follow the procedure in Section "20.15 Precautions when Using CAN Controller". 446 CHAPTER 20 CAN CONTROLLER 20.6.19 Acceptance Mask Registers 0 and 1 (AMR0 and AMR1) There are two acceptance mask registers, AMR0 and AMR1, both of which are available either in the standard frame format or extended frame format. AM28 to AM18 (11 bits) are used for acceptance masks in the standard frame format and AM28 to AM0 (29 bits) are used for acceptance masks in the extended format. ■ Acceptance mask registers 0 and 1 (AMR0 and AMR1) Figure 20.6-22 Configuration of the acceptance mask register 0 (AMR0) Address: 7 CAN1: 007D14H 6 5 4 3 2 1 0 AM28 AM27 AM26 AM25 AM24 AM23 AM22 AM21 AMR01 Byte 0 Initial value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W Address: 15 CAN1: 007D15H 14 13 12 11 10 9 8 AM20 AM19 AM18 AM17 AM16 AM15 AM14 AM13 R/W R/W R/W R/W R/W R/W R/W R/W Address: 7 CAN0: 007B16H 6 5 4 3 2 1 0 AM12 AM11 AM10 AM9 AM8 AM7 AM6 AM5 AMR01 Byte 1 Initial value XXXXXXXXB AMR01 Byte 2 Initial value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W Address: 15 14 13 12 11 10 9 8 AM4 AM3 AM2 AM1 AM0 - - - R/W R/W R/W R/W R/W - - - H CAN1: 007D17H R/W : Readable and writable X - : : Undefined value Undefined AMR01 Byte 3 Initial value XXXXXXXX B 447 CHAPTER 20 CAN CONTROLLER Figure 20.6-23 Configuration of the acceptance mask register 1 (AMR1) Address: CAN1: 007D18H 7 6 5 4 3 2 1 0 AM28 AM27 AM26 AM25 AM24 AM23 AM22 AM21 AMR11 Byte 0 Initial value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W Address: CAN1: 007D19H 15 14 13 12 11 10 9 8 AM20 AM19 AM18 AM17 AM16 AM15 AM14 AM13 R/W R/W R/W R/W R/W R/W R/W R/W Address: CAN1: 007D1A H 7 6 5 4 3 2 1 0 AM12 AM11 AM10 AM9 AM8 AM7 AM6 AM5 AMR11 Byte 1 Initial value XXXXXXXXB AMR11 Byte 2 Initial value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W R/W X - : : : Address: 15 CAN1: 007D1B H 14 13 12 11 10 9 8 AM4 AM3 AM2 AM1 AM0 - - - R/W R/W R/W R/W R/W - - - AMR11 Byte 3 Initial value X X X X X X X XB Readable and writable Undefined value Undefined ● 0: Compare Compare the bit of the acceptance code (ID register IDRx for comparing with the received message ID) corresponding to this bit with the bit of the received message ID. If there is no match, no message is received. ● 1: Mask Mask the bit of the acceptance code ID register (IDRx) corresponding to this bit. No comparison is made with the bit of the received message ID. Note: AMR0 and AMR1 should be set when all the message buffers (x) selecting AMR0 and AMR1 are invalid (BVALx of the message buffer valid register (BVALR) is 0). Setting when the buffers are valid (BVALx = 1) may cause unnecessary received messages to be stored. To invalidate the message buffer (by setting the BVALR: BVAL bit to 0) while the CAN controller is operating for CAN communication (the read value of the CSR: HALT bit is 0 and the CAN controller is operating for CAN bus communication to enable transmission and reception), follow the procedure in Section "20.15 Precautions when Using CAN Controller". 448 CHAPTER 20 CAN CONTROLLER 20.6.20 Message Buffers There are 16 message buffers. Message buffer x (x = 0 to 15) consists of an ID register (IDRx), DLC register (DLCRx), and data register (DTRx). ■ Message buffers ● The message buffer (x) is used both for transmission and reception. ● The lower-numbered message buffers are assigned higher priority. • At transmission, when a request for transmission is made to more than one message buffer, transmission is performed, starting with the lowest-numbered message buffer (See Section "20.7 Transmission of CAN Controller"). • At reception, when the received message ID passes through the acceptance filter (mechanism for comparing the acceptance-masked ID of received message and message buffer) of more than one message buffer, the received message is stored in the lowest-numbered message buffer (See Section " 20.8 Reception of CAN Controller"). ● When the same acceptance filter is set in more than one message buffer, the message buffers can be used as a multi-level message buffer. This provides allowance for receiving time. (See Section " 20.12 Procedure for Reception by Message Buffer (x)"). Note: A write operation to message buffers and general-purpose RAM areas should be performed in words to even addresses only. A write operation in bytes causes undefined data to be written to the upper byte at writing to the lower byte. Writing to the upper byte is ignored. When the BVALx bit of the message buffer valid register (BVALR) is 0 (Invalid), the message buffers x (IDRx, DLCRx, and DTRx) can be used as general-purpose RAM. During the receive/transmit operation of the CAN controller, the CAN Controller write/read to/from the message buffers. If the CPU tries to write/read to/from the message buffers in this period, the CPU has to wait a maximum time of 64 machine cycles. This is also true for the general-purpose RAM. 449 CHAPTER 20 CAN CONTROLLER 20.6.21 ID Register x (x = 0 to 15) (IDRx) ID Register x (x = 0 to 15) (IDRx) is the ID register for message buffer (x). ■ ID register x (x = 0 to 15) (IDRx) Figure 20.6-24 Configuration of the ID registers (IDRx) Address: CAN1: 007C20H + 4 * x 7 6 5 4 3 2 1 0 ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 IDRx1 Byte 0 Initial value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W Address: CAN1: 007C21H + 4 * x 15 14 13 12 11 10 9 8 ID20 ID19 ID18 ID17 ID16 ID15 ID14 ID13 R/W R/W R/W R/W R/W R/W R/W R/W Address: CAN1: 007C22H + 4 * x 7 6 5 4 ID12 ID11 ID10 ID9 3 2 1 ID8 ID7 ID6 IDRx1 Byte 1 Initial value XXXXXXXXB 0 IDRx1 Byte 2 ID5 Initial value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W Address: 15 14 13 12 11 10 9 8 IDRx1 Byte 3 CAN1: 007C23H + 4 * x ID4 ID3 ID2 ID1 ID0 - - - R/W R/W R/W R/W R/W - - - Initial value X X X X XX X X B R/W : Readable and Writable X : Undefined value - : Undefined x = 0, ... , 15 When using the message buffer (x) in the standard frame format (IDEx of the IDE register (IDER) = 0), use 11 bits of ID28 to ID18. When using the buffer in the extended frame format (IDEx = 1), use 29 bits of ID28 to ID0. ID28 to ID0 have the following functions: • Set acceptance code (ID for comparing with the received message ID). • Set transmitted message ID. Note: In the standard frame format, setting 1s to all bits of ID28 to ID22 is prohibited). • Store the received message ID. Note: All received message ID bits are stored (even if bits are masked). In the standard frame format, ID17 to ID0 stores image of old message left in the receive shift register. 450 CHAPTER 20 CAN CONTROLLER Note: A write operation to this register should be performed in words. A write operation in bytes causes undefined data to be written to the upper byte at writing to the lower byte. Writing to the upper byte is ignored. To invalidate the message buffer (by setting the BVALR: BVAL bit to 0) while the CAN controller is operating for CAN communication (the read value of the CSR: HALT bit is 0 and the CAN controller is operating for CAN bus communication to enable transmission and reception), follow the procedure in Section "20.15 Precautions when Using CAN Controller". 451 CHAPTER 20 CAN CONTROLLER 20.6.22 DLC Register x (x = 0 to 15) (DLCRx) DLC Register x (x = 0 to 15) (DLCRx) is the DLC register for message buffer x. ■ DLC register x (x = 0 to 15) (DLCRx) Figure 20.6-25 Configuration of the DLC registers (DLCRx) Address: CAN1: 007C60H + 2 * x 7 6 5 4 3 2 1 0 - - - - DLC3 DLC2 DLC1 DLC0 - - - - R/W R/W R/W R/W R/W : Readable and Writable X : Undefined value - : Undefined DLCR1x (lower) Initial value X X X XX X X X B x = 0, ... , 15 ● Transmission • Set the data length (byte count) of a transmitted message when a data frame is transmitted (TRTRx of the transmitting RTR register (TRTRR) is 0). • Set the data length (byte count) of a requested message when a remote frame is transmitted (TRTRx = 1). Note: Setting other than 0000 to 1000 (0 to 8 bytes) is prohibited. ● Reception • Store the data length (byte count) of a received message when a data frame is received (RRTRx of the remote frame request receiving register (RRTRR) is 0). • Store the data length (byte count) of a requested message when a remote frame is received (RRTRx = 1). Note: A write operation to this register should be performed in words. A write operation in bytes causes undefined data to be written to the upper byte at writing to the lower byte. Writing to the upper byte is ignored. 452 CHAPTER 20 CAN CONTROLLER 20.6.23 Data Register x (x = 0 to 15) (DTRx) Data register x (x = 0 to 15) (DTRx) is the data register for message buffer (x). This register is used only in transmitting and receiving a data frame but not in transmitting and receiving a remote frame. ■ Data register x (x = 0 to 15) (DTRx) Figure 20.6-26 Configuration of the data registers (DTRx) Address: CAN1: 007C80H + 8 * x 7 6 5 4 3 2 1 0 DTRx1 Byte 0 D7 D6 D5 D4 D3 D2 D1 D0 Initial value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W Address: CAN1: 007C81H + 8 * x 15 14 13 12 D7 D6 D5 D4 11 D3 10 9 8 DTRx1 Byte 1 D2 D1 D0 Initial value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W Address: CAN1: 007C82H + 8 * x 7 6 5 4 3 2 1 0 DTRx1 Byte 2 D7 D6 D5 D4 D3 D2 D1 D0 Initial value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W Address: CAN1: 007C83H + 8 * x 15 14 13 12 D7 D6 D5 D4 11 D3 10 9 8 DTRx1 Byte 3 D2 D1 D0 Initial value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W Address: CAN1: 007C84H + 8 * x 7 6 5 4 3 2 1 0 DTRx1 Byte 4 D7 D6 D5 D4 D3 D2 D1 D0 Initial value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W Address: CAN1: 007C85H + 8 * x 15 14 13 12 11 10 9 8 DTRx1 Byte 5 D7 D6 D5 D4 D3 D2 D1 D0 Initial value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W Address: CAN1: 007C86H + 8 * x 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 DTRx1 Byte 6 Initial value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W Address: CAN1: 007C87H + 8 * x 15 14 13 12 11 10 9 8 DTRx1 Byte 7 D7 D6 D5 D4 D3 D2 D1 D0 Initial value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W R/W : Readable and Writable X : Undefined value x = 0, 1, ... , 15 453 CHAPTER 20 CAN CONTROLLER ● Sets transmitted message data (any of 0 to 8 bytes). Data is transmitted in the order of BYTE0, BYTE1, ..., BYTE7, starting with the MSB. ● Stores received message data. Data is stored in the order of BYTE0, BYTE1, ..., BYTE7, starting with the MSB. Even if the received message data is less than 8 bytes, the remaining bytes of the data register (DTRx), to which data are stored, are undefined. Note: A write operation to this register should be performed in words. A write operation in bytes causes undefined data to be written to the upper byte at writing to the lower byte. Writing to the upper byte is ignored. 454 CHAPTER 20 CAN CONTROLLER 20.7 Transmission of CAN Controller When 1 is written to TREQx of the transmission request register (TREQR), transmission by the message buffer (x) starts. At this time, TREQx becomes 1 and TCx of the transmission complete register (TCR) becomes 0. ■ Starting transmission of the CAN controller If RFWTx of the remote frame receiving wait register (RFWTR) is 0, transmission starts immediately. If RFWTx is 1, transmission starts after waiting until a remote frame is received (RRTRx of the remote request receiving register (RRTRR) becomes 1). If a request for transmission is made to more than one message buffer (more than one TREQx is 1), transmission is performed, starting with the lowest-numbered message buffer. Message transmission to the CAN bus (by the transmit output pin TX) starts when the bus is idle. If TRTRx of the transmission RTR register (TRTRR) is 0, a data frame is transmitted. If TRTRx is 1, a remote frame is transmitted. If the message buffer competes with other CAN controllers on the CAN bus for transmission and arbitration fails, or if an error occurs during transmission, the message buffer waits until the bus is idle and repeats retransmission until it is successful. ■ Canceling a transmission request from the CAN controller ● Canceling by transmission cancel register (TCANR) A transmission request for message buffer (x) having not executed transmission during transmission pending can be canceled by writing 1 to TCANx of the transmission cancel register (TCANR). At completion of cancellation, TREQx becomes 0. ● Canceling by storing received message The message buffer (x) having not executed transmission despite transmission request also performs reception. If the message buffer (x) has not executed transmission despite a request for transmission of a data frame (TRTRx = 0 or TREQx = 1), the transmission request is canceled after storing received data frames passing through the acceptance filter (TREQx = 0). Note: A transmission request is not canceled by storing remote frames (TREQx = 1 remains unchanged). If the message buffer (x) has not executed transmission despite a request for transmission of a remote frame (TRTRx = 1 or TREQx = 1), the transmission request is canceled after storing received remote frames passing through the acceptance filter (TREQx = 0). Note: The transmission request is canceled by storing either data frames or remote frames. ■ Completing transmission of the CAN controller When transmission is successful, RRTRx becomes 0, TREQx becomes 0, and TCx of the transmission 455 CHAPTER 20 CAN CONTROLLER complete register (TCR) becomes 1. If the transmission complete interrupt is enabled (TIEx of the transmission complete interrupt enable register (TIER) is 1), an interrupt occurs. ■ Transmission flowchart of the CAN controller Figure 20.7-1 Transmission flowchart of the CAN controller Transmission request (TREQx := 1) TCx := 0 0 TREQx? 1 0 RFWTx? 1 0 RRTRx? 1 If there are any other message buffers meeting the above conditions, select the lowest-numbered message buffer. NO Is the bus idle? YES 0 1 TRTRx? A data frame is transmitted. A remote frame is transmitted. NO Is transmission successful? YES TCANx? 1 RRTRx : = 0 TREQx := 0 TCx := 1 TREQx := 0 1 TIEx ? 0 A transmission complete interrupt occurs. End of transmission 456 0 CHAPTER 20 CAN CONTROLLER 20.8 Reception of CAN Controller Reception starts when the start of data frame or remote frame (SOF) is detected on the CAN bus. ■ Acceptance filtering The received message in the standard frame format is compared with the message buffer (x) set in the standard frame format (IDEx of the IDE register (IDER) is 0). The received message in the extended frame format is compared with the message buffer (x) set (IDEx is 1) in the extended frame format. If all the bits set to Compare by the acceptance mask agree after comparison between the received message ID and acceptance code (ID register (IDRx) for comparing with the received message ID), the received message passes to the acceptance filter of the message buffer (x). ■ Storing received message When the receive operation is successful, received messages are stored in a message buffer x including IDs passed through the acceptance filter. When receiving data frames, received messages are stored in the ID register (IDRx), DLC register (DLCRx), and data register (DTRx). Even if received message data is less than 8 bytes, some data is stored in the remaining bytes of the DTRx and its value is undefined. When receiving remote frames, received messages are stored only in the IDRx and DLCRx, and the DTRx remains unchanged. If there is more than one message buffer including IDs passed through the acceptance filter, the message buffer x in which received messages are to be stored is determined according to the following rules. • The order of priority of the message buffer x (x = 0 to 15) rises as its number lower; in other words, message buffer 0 is given the highest and the message buffer 15 is given the lowest priority. • Basically, message buffers with the RCx bit of 0 in the receive completion register (RCR) are preferred in storing received messages. • If the bits of the acceptance mask select register (AMSR) are set to All Bits Compare (for message buffers with the AMSx.1 and AMSx.0 bits set to 00), received messages are stored irrespective of the value of the RCx bit of the RCR. • If there are message buffers with the RCx bit of the RCR set to 0, or with the bits of the AMSR set to All Bits Compare, received messages are stored in the lowest-number (highest-priority) message buffer x. • If there are no message buffers above-mentioned, received messages are stored in a lower-number message buffer x. • Message buffers should be arranged in ascending numeric order. The lowest message buffers should be with All Bits Compare, then AMR0 or AMR1 masks. And The highest message buffers should be with All Bits Mask. Figure 20.8-1 shows a flowchart for determining the message buffer (x) where received messages are to be stored. It is recommended that message buffers be arranged in the following order: message buffers in which each AMSR bit is set to All Bits Compare, message buffers using AMR0 or AMR1, and message buffers in which each AMSR bit is set to All Bits Mask. 457 CHAPTER 20 CAN CONTROLLER Figure 20.8-1 Flowchart determining message buffer (x) where received messages stored Start Are message buffers with RCx set to 0 or with AMSx.1 and AMSx.0 set to 00 found? NO YES Select the lowest-numbered message buffer. Select the lowest-numbered message buffer. End ■ Receive overrun When a message is stored in the message buffer with the corresponding RCx being already set to 1, it will results in receive overrun. In this case, the corresponding ROVRx bit in the receive overrun register ROVRR is set to 1. ■ Processing for reception of data frame and remote frame ● Processing for reception of data frame RRTRx of the remote request receiving register (RRTRR) becomes 0. TREQx of the transmission request register (TREQR) becomes 0 (immediately before storing the received message). A transmission request for message buffer (x) having not executed transmission will be canceled. Note: A request for transmission of either a data frame or remote frame is canceled. ● Processing for reception of remote frame RRTRx becomes 1. If TRTRx of the transmitting RTR register (TRTRR) is 1, TREQx becomes 0. As a result, the request for transmitting remote frame to message buffer having not executed transmission will be canceled. Note: A request for data frame transmission is not canceled. For cancellation of a transmission request, see Figure 20.7-1. ■ Completing reception RCx of the reception complete register (RCR) becomes 1 after storing the received message. If a reception interrupt is enabled (RIEx of the reception interrupt enable register (RIER) is 1), an interrupt occurs. Note: This CAN controller will not receive any messages transmitted by itself. 458 CHAPTER 20 CAN CONTROLLER 20.9 Reception Flowchart of CAN Controller Figure 20.9-1 shows a reception flowchart of the CAN controller. ■ Reception flowchart of the CAN controller Figure 20.9-1 Reception flowchart of the CAN controller Detection of start of data frame or remote frame (SOF) NO Is any message buffer (x) passing to the acceptance filter found? YES NO Is reception successful? YES Determine message buffer (x) where received messages to be stored. Store the received message in the message buffer (x). 1 RCx? 0 Data frame ROVRx := 1 Remote frame Received message? RRTRx := 0 RRTRx := 1 1 TRTRx? 0 TREQx := 0 RCx := 1 RIEx ? 0 1 A reception interrupt occurs. End of reception 459 CHAPTER 20 CAN CONTROLLER 20.10 How to Use the CAN Controller The following settings are required to use the CAN controller: • Bit timing • Frame format • ID • Acceptance filter • Low-power consumption mode ■ Setting bit timing The bit timing register (BTR) should be set during bus operation stop (when the bus operation stop bit (HALT) of the control status register (CSR) is 1). After the setting completion, write 0 to HALT to cancel bus operation stop. ■ Setting frame format Set the frame format used by the message buffer (x). When using the standard frame format, set IDEx of the IDE register (IDER) to 0. When using the extended frame format, set IDEx to 1. This setting should be made when the message buffer (x) is invalid (BVALx of the message buffer valid register (BVALR) is 0). Setting when the buffer is valid (BVALx = 1) may cause unnecessary received messages to be stored. ■ Setting ID Set the message buffer (x) ID to ID28 to ID0 of ID register (IDRx). The message buffer (x) ID need not be set to ID11 to ID0 in the standard frame format. The message buffer (x) ID is used as a transmission message at transmission and is used as an acceptance code at reception. This setting should be made when the message buffer (x) is invalid (BVALx of the message buffer valid register (BVALR) is 0). Setting when the buffer is valid (BVALx = 1) may cause unnecessary received messages to be stored. ■ Setting acceptance filter The acceptance filter of the message buffer (x) is set by an acceptance code and acceptance mask set. It should be set when the acceptance message buffer (x) is invalid (BVALx of the message buffer enable register (BVALR) is 0). Setting when the buffer is valid (BVALx = 1) may cause unnecessary received messages to be stored. Set the acceptance mask used in each message buffer (x) by the acceptance mask select register (AMSR). The acceptance mask registers (AMR0 and AMR1) should also be set if used (For the setting details, see Sections "20.6.18 Acceptance Mask Select Register (AMSR)" and "20.6.19 Acceptance Mask Registers 0 and 1 (AMR0 and AMR1)"). The acceptance mask should be set so that a transmission request may not be canceled when unnecessary received messages are stored. For example, it should be set to a full-bit comparison if only one specific ID is used for the transmission. ■ Setting low-power consumption mode To set the F2MC-16LX in a low-power consumption mode (Stop and Timebase timer), write 1 to the bus operation stop bit (HALT) of the control status register (CSR), and then check that the bus operation has stopped (HALT = 1). 460 CHAPTER 20 CAN CONTROLLER 20.11 Procedure for Transmission by Message Buffer (x) After setting the bit timing, frame format, ID, and acceptance filter, set BVALx to 1 to activate the message buffer (x). ■ Procedure for transmission by message buffer (x) ● Setting transmit data length code Set the transmit data length code (byte count) to DLC3 to DLC0 of the DLC register (DLCRx). For data frame transmission (when TRTRx of the transmission RTR register (TRTRR) is 0), set the data length of the transmitted message. For remote frame transmission (when TRTRx = 1), set the data length (byte count) of the requested message. Note: Setting other than 0000 to 1000 (0 to 8 bytes) is prohibited. ● Setting transmit data (only for transmission of data frame) For data frame transmission (when TRTRx of the transmission register (TRTRR) is 0), set data as the count of byte transmitted in the data register (DTRx). Note: Transmit data should be rewritten while the TREQx bit of the transmission request register (TREQR) set to 0. There is no need for setting the BVALx bit of the message buffer valid register (BVALR) to 0. Setting the BVALx bit to 0 may cause incoming remote frame to be lost. ● Setting transmission RTR register For data frame transmission, set TRTRx of the transmission RTR register (TRTRR) to 0. For remote frame transmission, set TRTRx to 1. ● Setting conditions for starting transmission (only for transmission of data frame) Set RFWTx of the remote frame receiving wait register (RFWTR) to 0 to start transmission immediately after a request for data frame transmission is set (TREQx of the transmission request register (TREQR) is 1 and TRTRx of the transmission RTR register (TRTRR) is 0). Set RFWTx to 1 to start transmission after waiting until a remote frame is received (RRTRx of the remote request receiving register (RRTRR) becomes 1) after a request for data frame transmission is set (TREQx = 1 and TRTRx = 0). Note: Remote frame transmission can not be made, if RFWTx is set to 1. 461 CHAPTER 20 CAN CONTROLLER ● Setting transmission complete interrupt When generating a transmission complete interrupt, set TIEx of the transmission complete interrupt enable register (TIER) to 1. When not generating a transmission complete interrupt, set TIEx to 0. ● Setting transmission request For a transmission request, set TREQx of the transmission request register (TREQR) to 1. ● Canceling transmission request When canceling a pending request for transmission to the message buffer (x), write 1 to TCANx of the transmission cancel register (TCANR). Check TREQx. For TREQx = 0, transmission cancellation is terminated or transmission is completed. Check TCx of the transmission complete register (TCR). For TCx = 0, transmission cancellation is terminated. For TCx = 1, transmission is completed. ● Processing for completion of transmission If transmission is successful, TCx of the transmission complete register (TCR) becomes 1. If the transmission complete interrupt is enabled (TIEx of the transmission complete interrupt enable register (TIER) is 1), an interrupt occurs. After checking the transmission completion, write 0 to TCx to set it to 0. This cancels the transmission complete interrupt. In the following cases, the pending transmission request is canceled by receiving and storing a message. • Request for data frame transmission by reception of data frame • Request for remote frame transmission by reception of data frame • Request for remote frame transmission by reception of remote frame Request for data frame transmission is not canceled by receiving and storing a remote frame. ID and DLC, however, are changed by the ID and DLC of the received remote frame. Note that the ID and DLC of data frame to be transmitted become the value of received remote frame. 462 CHAPTER 20 CAN CONTROLLER 20.12 Procedure for Reception by Message Buffer (x) After setting the bit timing, frame format, ID, and acceptance filter, make the settings described below. ■ Procedure for reception by message buffer (x) ● Setting reception interrupt To enable reception interrupt, set RIEx of the reception interrupt enable register (RIER) to 1. To disable reception interrupt, set RIEx to 0. ● Starting reception When starting reception after setting, set BVALx of the message buffer valid register (BVALR) to 1 to make the message buffer (x) valid. ● Processing for reception completion If reception is successful after passing to the acceptance filter, the received message is stored in the message buffer (x) and RCx of the reception complete register (RCR) becomes 1. For data frame reception, RRTRx of the remote request receiving register (RRTRR) becomes 0. For remote frame reception, RRTRx becomes 1. If a reception interrupt is enabled (RIEx of the reception interrupt enable register (RIER) is 1), an interrupt occurs. After checking the reception completion (RCx = 1), process the received message. After completion of processing the received message, check ROVRx of the reception overrun register (ROVRR). If ROVRx = 0, the processed received message is valid. Write 0 to RCRx to set it to 0 (the reception complete interrupt is also canceled) to terminate reception. If ROVRx = 1, a reception overrun occurred and the next message may have overwritten the processed message. In this case, received messages should be processed again after setting the ROVRx bit to 0 by writing 0 to it. Figure 20.12-1 shows an example of receive interrupt handling. 463 CHAPTER 20 CAN CONTROLLER Figure 20.12-1 Example of receive interrupt handling Interrupt with RCx = 1 Read received messages. A: = ROVRx ROVRx := 0 A = 0? YES RCx := 0 End 464 NO CHAPTER 20 CAN CONTROLLER 20.13 Setting Configuration of Multi-level Message Buffer If the receptions are performed frequently, or if several different ID’s of messages are received, in other words, if there is insufficient time for handling messages, more than one message buffer can be combined into a multi-level message buffer to provide allowance for processing time of the received message by CPU. ■ Setting configuration of multi-level message buffer To provide a multi-level message buffer, the same acceptance filter must be set in the combined message buffers. If the bits of the acceptance mask select register (AMSR) are set to All Bits Compare ((AMSx.1, AMSx.0) = (0, 0)), multi-level message configuration of message buffers is not allowed. This is because All Bits Compare causes received messages to be stored irrespective of the value of the RCx bit of the receive completion register (RCR), so received messages are always stored in lower-numbered (higher-priority) message buffers even if All Bits Compare and identical acceptance code (ID register (IDRx)) are specified for more than one message buffer. Therefore, All Bits Compare and identical acceptance code should not be specified for more than one message buffer. Figure 20.13-1 shows operational examples of multi-level message buffers. 465 CHAPTER 20 CAN CONTROLLER Figure 20.13-1 Examples of operation of multi-level message buffer Initialization AMS15, AMS14, AMS13 AMSR 10 10 10 Select AMR0. ... AM28 to AM18 AMS0 ID28 to ID18 Message buffer 13 Message buffer 14 Message buffer 15 0000 1111 111 IDE ... 0101 0000 000 0101 0000 000 0101 0000 000 RC15, RC14, RC13 0 ... RCR 0 0 0 ... 0 ... ROVRR 0 0 0 ... 0 ... ROVR15, ROVR14, ROVR13 Mask Message receiving "The received message is stored in message buffer 13. IDE ID28 to ID18 Message receiving 0101 1111 000 0 ... Message buffer 13 0101 1111 000 0 ... RCR 0 0 1 ... 0 ... ROVRR 0 0 0 ... 0 ... Message buffer 14 Message buffer 15 Message receiving 0101 0000 000 0101 0000 000 "The received message is stored in message buffer 14. Message receiving 0101 1111 001 0 ... Message buffer 13 0101 1111 000 0 ... RCR 0 1 1 ... Message buffer 14 0101 1111 001 0 ... ROVRR 0 0 0 ... 0 ... Message buffer 15 Message receiving 0101 0000 000 "The received message is stored in message buffer 15. Message receiving 0101 1111 010 0 ... Message buffer 13 0101 1111 000 0 ... RCR 1 1 1 ... Message buffer 14 0101 1111 001 0 ... ROVRR 0 0 0 ... Message buffer 15 0101 1111 010 0 ... Message receiving "An overrun occurs (ROVR13 = 1) and the received message is stored in message buffer 13. Message receiving 0101 1111 011 0 ... Message buffer 13 0101 1111 011 0 ... RCR 1 1 1 ... Message buffer 14 0101 1111 001 0 ... ROVRR 0 0 1 ... Message buffer 15 0101 1111 010 0 ... Note: Four messages are received with the same acceptance filter set in message buffers 13, 14 and 15. 466 CHAPTER 20 CAN CONTROLLER 20.14 Setting the CAN Direct Mode Register To operate CAN normally, this register must be set correctly. ■ CAN direct mode register (CDMR) Figure 20.14-1 Configuration of the CAN direct mode register (CDMR) R/W X - : : : Address: 7 6 5 4 3 2 1 CAN1: 00796EH - - - - - - - - - - - - - - R/W 0 DIRECT CDMR Initial value XXXXXXX0 B Readable and writable Undefined value Undefined ■ CAN direct mode register contents Table 20.14-1 Function of the DIRECT bit of the CAN direct mode register Bit Name bit 7 to 1 Undefined bit 0 DIRECT Function When the CAN direct mode is not needed, the bit should be set to "0". When the CAN direct mode is needed, the bit should be set to "1". 467 CHAPTER 20 CAN CONTROLLER 20.15 Precautions when Using CAN Controller Use of the CAN Controller requires the following cautions. ■ Caution for disabling message buffers by BVAL bits The use of BVAL bits may affect malfunction of CAN Controller when messages buffers are set disabled while CAN Controller is participating in CAN communication (the read value of the CSR: HALT bit is 0 and CAN Controller is ready to transmit messages). This section shows the work around of this malfunction. ● Condition When following two conditions occur at the same time, the CAN Controller will not perform to transmit messages normally. • CAN Controller is participating in the CAN communication. (i.e. The read value of the CSR: HALT bit is 0 and CAN Controller is ready to transmit messages) • Message buffers are read when BVAL bits disable the message buffers. ● Work around Operation for suppressing transmission request Do not use BVAL bit for suppressing transmission request, use TCAN bit instead of it. Operation for composing transmission message For composing a transmission message, it is necessary to disable the message buffer by BVAL bit to change contents of ID and IDE registers. In this case, BVAL bit should reset (BVAL=0) after checking if TREQ bit is 0 or after completion of the previous message transmission (TC=1). In case a buffer needs to be disabled, ensure that no transmission request is pending (if it was requested before)! Therefore, do not reset BVALx-Bit before testing, if a transmission is ongoing: a) Cancel the transmission request (TCANx=1;), if necessary b) and wait for the transmission completion (while (TREQx==1);) by polling or interrupt. Only after that the transmission buffer can be disabled (BVALx=0;). Note for case a), if transmission of that buffer has already started, canceling the request is ignored and disabling the buffer is delayed until the end of the transmission. 468 CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION This chapter explains the address match detection function and operation. 21.1 Outline of the Address Match Detection Function 21.2 Registers of the Address Match Detection Function 21.3 Operation of the Address Match Detection Function 21.4 Example of the Address Match Detection Function 469 CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION 21.1 Outline of the Address Match Detection Function When an address matches the value set in the address detection register, the instruction code to be read by the CPU is replaced with the INT9 instruction code (01H). Consequently, the CPU executes the INT9 instruction when executing a specified instruction. The address match detection function can be achieved using the INT9 interrupt routine for processing. There are 6 address detection registers, each with an interrupt permission bit. When an address matches the value set in the address detection register and the interrupt permission bit is 1, the instruction code to be read by the CPU is replaced with the INT9 instruction code. ■ Block diagram of the address match detection function Address latch Address detection register Permission bit F2MC-16LX bus 470 Comparison Figure 21.1-1 Block diagram of the address match detection function INT9 instruction F2MC-16LX CPU core CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION 21.2 Registers of the Address Match Detection Function The two types of registers for the address match detection function are as follows: • Program address detection registers (PADR0 to PADR5) • Program address detection control status register (PACSR0 and PACSR1) ■ Program address detection registers (PADR0 to PADR5) The program address detection registers 0 to 5 (PADR0 to PADR5) compare the address with the value written in each register. If they match when the interrupt permission bit corresponding to ADCSR is 1, the CPU is requested to issue the INT9 instruction. When the corresponding interrupt bit is 0, nothing occurs. Figure 21.2-1 Program address detection registers (PADR0 to PADR5) Program address detection registers PADR0 PADR1 PADR2 PADR3 PADR4 PADR5 byte 79E2H/79E1H/79E0H 79E5H/79E4H/79E3H 79E8H/79E7H/79E6H 79F2H/79F1H/79F0H 79F5H/79F4H/79F3H 79F8H/79F7H/79F6H byte byte Access Initial value R/W R/W R/W R/W R/W R/W Not defined Not defined Not defined Not defined Not defined Not defined Table 21.2-1 lists the correspondence between the program address detection registers (PADR0 to PADR5) and PACSR. Table 21.2-1 Correspondence between PADR0 to PADR5 registers and PACSR0 and PACSR1 registers Address detection register Interrupt permission bit PADR0 AD0E (bit 1) PADR1 AD1E (bit 3) PADR2 AD2E (bit 5) PADR3 AD3E (bit 1) PADR4 AD4E (bit 3) PADR5 AD5E (bit 5) 471 CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION ■ Program address detection control status register (PACSR) The program address detection control status register (PACSR) controls the operation of the address detection function. Figure 21.2-2 Program address detection control status registers (PACSR0/1) Address: 00009E H 7 6 5 4 3 2 1 0 Reserved Reserved AD2E Reserved AD1E Reserved AD0E Reserved R/W R/W R/W R/W R/W R/W R/W R/W Address: 15 00003B H Reserved Reserved AD5E Reserved AD4E Reserved AD3E Reserved 14 13 12 11 10 9 8 R/W R/W R/W R/W R/W R/W R/W R/W R/W PACSR0 Initial value 00000000 B PACSR1 Initial value 0 0 0 0 0 0 0 0B : Readable and writable Table 21.2-2 Function of each bit of PACSR1 and PACSR0 Name Function bit 15, 14 Reserved bits Bits 15, 14 are reserved. Set these bits to 0 before setting PACSR1. bit 13 AD5E: Address detect register 1 enable The AD5E bit is the operation permission bit of ASIE ADR5. When this bit is 1, the address is compared with the PADR5 register. If they match, the INT9 instruction is issued. bit 12 Reserved bit Bit 12 is reserved. Set this bit to 0 before setting PACSR1. bit 11 AD4E: Address detect register 1 enable The AD4E bit is the operation permission bit of ASIE ADR4. When this bit is 1, the address is compared with the PADR4 register. If they match, the INT9 instruction is issued. bit 10 Reserved bit Bit 10 is reserved. Set this bit to 0 before setting PACSR1. bit 9 AD3E: Address detect register 1 enable The AD3E bit is the operation permission bit of ASIE ADR3. When this bit is 1, the address is compared with the PADR3 register. If they match, the INT9 instruction is issued. bit 8 Reserved bit Bit 8 is reserved. Set this bit to 0 before setting PACSR1. bit 7, 6 Reserved bits Bits 7, 6 are reserved. Set these bits to 0 before setting PACSR0. bit 5 AD2E: Address detect register 1 enable The AD2E bit is the operation permission bit of ASIE ADR2. When this bit is 1, the address is compared with the PADR2 register. If they match, the INT9 instruction is issued. bit 4 Reserved bits Bits 4 is reserved. Set these bits to 0 before setting PACSR0. bit 3 AD1E: Address detect register 1 enable The AD1E bit is the operation permission bit of ASIE ADR1. When this bit is 1, the address is compared with the PADR1 register. If they match, the INT9 instruction is issued. bit 2 Reserved bit Bit 2 is reserved. Set this bit to 0 before setting PACSR0. bit 1 AD0E: Address detect register 0 enable The AD0E bit is the operation permission bit of ADR0. When this bit is 1, the address is compared with the PADR0 register. If they match, the INT9 instruction is issued. bit 0 Reserved bit Bit 0 is reserved. Set this bit to 0 before setting PACSR0. 472 CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION 21.3 Operation of the Address Match Detection Function If the program counter specifies the same address as the address match detection register, the INT9 instruction is executed. The address match detection function can be achieved by processing the INT9 instruction routine. ■ Operation of the address match detection function There are 6 address detection registers with a compare enable bit. When the value set in the address detection register and the value of the program counter match and the compare enable bit is set to 1, the CPU executes the INT9 instruction. Note: If the value of the address detection register and the value of the program counter match, the contents of internal data bus is changed to 01H. Consequently, the INT9 instruction is executed. Before changing the contents of the address detection register, always set the compare enable bit to 0. While the compare enable bit is set to 1, changing the contents of the address detection register may result in a malfunction. 473 CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION 21.4 Example of the Address Match Detection Function Figure 21.4-1 shows a system configuration example of the address match detection function. Table 21.4-1 lists the EEPROM memory map. ■ System configuration example of the address match detection function Figure 21.4-1 System configuration example of the address match detection function EEPROM MCU F2MC16LX SIN Pull-up resistor Connector (UART) Table 21.4-1 EEPROM memory map Address Description 0000H Number of bytes of patch program No.0 (If 0, no program error exists.) 0001H Program address No.0 bits 7 to 0 0002H Program address No.0 bits 15 to 8 0003H Program address No.0 bits 24 to 16 0004H Number of bytes of patch program No.1 (If 0, no program error exists.) 0005H Program address No.1 bits 7 to 0 0006H Program address No.1 bits 15 to 8 0007H Program address No.1 bits 24 to 16 0010H or higher Main body of patch program No. 0 ● Initial status EEPROM is set to all 0s. 474 CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION ● When a program error occurs: The main body of the patch program and program address are transferred to the MCU through the connector (UART). The MCU writes the information to EEPROM. ● Reset sequence The MCU reads the value of EEPROM after reset. If the number of bytes of the patch program is not 0, the main body of the patch program is read from EEPROM and written to RAM. The MCU then uses either PADR0 or PADR1 to set the patch address and sets the compare enable bit. If the relocatable patch program is required, the first address of the patched program can be written to the RAM area. In this case, the INT9 routine accesses this user-defined RAM area and jumps to the patched program. ● INT9 interrupt The interrupt routine can know the address where the interrupt occurs by checking the value of the stack program counter. The information that has been placed on the stack during the interrupt is discarded. ■ Example of program patch processing Figure 21.4-2 Example of program patch processing FFFFFFH (3) Abnormal program (1) PC = address in error ROM External EEPROM Register set for program patch Number of program bytes Address where the interrupt occurs Corrected program Data transfer using UART RAM Corrected program (2) 000000H 475 CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION Figure 21.4-3 Flow of program patch processing Reset Reads 00H of EEPROM INT9 YES 0000H(EEPROM)=0 To patch program JMP 000400H NO Read address 0001H to 0003H (EEPROM) MOV PADR0 (MCU) Execute patch program 000400H to 000480H Read patch program 0010H to 0090H (EEPROM) MOV 000400H to 000480H (MCU) Terminate patch program JMP FF0050H Enable compare MOV PACSR, #02H Execute normal program NO PC=PADR0 YES INT9 FFFFFFH FF0050H ROM EEPROM Abnormal program FF0000H FFFFH FE0000H 0090H Patch program 0010H 001100H Stack area 0003H 0002H 0001H 0000H 476 Program address low-order: Program address middle-order: Program address high-order: Number of bytes of the patch program: RAM area 00 00 000480H Patch program RAM 000400H RAM and register area FF 000100H I/O area 80 000000H CHAPTER 22 ROM MIRRORING MODULE This chapter explains the ROM mirroring module. 22.1 Outline of ROM Mirroring Module 22.2 ROM Mirroring Register (ROMM) 477 CHAPTER 22 ROM MIRRORING MODULE 22.1 Outline of ROM Mirroring Module The ROM Mirroring module switches whether to mirror the image of the FF bank of the ROM to the 00 bank. ■ Block diagram of ROM mirroring module Figure 22.1-1 Block diagram of ROM mirroring module F2MC-16LX BUS ROM Mirrroring Register Address Area FF bank 00 bank ROM 478 CHAPTER 22 ROM MIRRORING MODULE 22.2 ROM Mirroring Register (ROMM) Do not access the ROM mirroring register (ROMM) when addresses 008000H to 00FFFFH are being accessed. ■ ROM mirroring register (ROMM) Address: 15 14 13 12 11 10 9 8 00006FH - - - - - - - MI - - - - - - - W W : Write only X - : : Undefined value Undefined ROMM Initial value X X X X X X X1B Table 22.2-1 Function of each bit of ROM mirroring register Bit Name bit 15 to 9 Undefined bit 8 MI: Mirror bit Function The image of the ROM data in the FF bank can also be found in the 00 bank when "1" is written to this bit. However, this memory mapping will not be done when this bit is written to "0". This bit is write only. Note: Only FF8000H to FFFFFFH is mirrored to 008000H to 00FFFFH when the ROM mirroring function is activated. Therefore, addresses FF0000H to FF7FFFH will not be mirrored to 00 bank. 479 CHAPTER 22 ROM MIRRORING MODULE 480 CHAPTER 23 1M-BIT FLASH MEMORY This chapter explains the functions and operation of the 1M-bit flash memory. The following three methods are available for writing data to and erasing data from the flash memory: - Parallel programmer - Serial programmer - Executing programs to write/erase data This chapter explains “Executing programs to write/ erase data”. 23.1 Overview of 1M-bit Flash Memory 23.2 Block Diagram of the Entire Flash Memory and Sector Configuration of the Flash Memory 23.3 Write/Erase Modes 23.4 Flash Memory Control Status Register (FMCS) 23.5 Starting the Flash Memory Automatic Algorithm 23.6 Confirming the Automatic Algorithm Execution State 23.7 Detailed Explanation of Writing to and Erasing Flash Memory 23.8 Notes on using 1M-bit Flash Memory 23.9 Flash Security Feature 23.10 Example of Programming 1M-bit Flash Memory 481 CHAPTER 23 1M-BIT FLASH MEMORY 23.1 Overview of 1M-bit Flash Memory The 1M-bit flash memory is mapped to the FE to FF bank in the CPU memory map. The functions of the flash memory interface circuit enable read-access and program-access from the CPU in the same way as mask ROM. Instructions from the CPU can be used via the flash memory interface circuit to write data to and erase data from the flash memory. Internal CPU control therefore enables rewriting of the flash memory while it is mounted. As a result, improvements in programs and data can be performed efficiently. ■ 1M-bit flash memory features • Use of automatic program algorithm (Embedded Algorithm: Equivalent to MBM29LV200) • Erase pause/restart functions provided • Detection of completion of writing/erasing using data polling or toggle bit functions • Detection of completion of writing/erasing using CPU interrupts • Sector erase function (any combination of sectors) • Minimum of 10,000 write/erase operations • Flash reading cycle time: Minimum of 2 machine cycles Embedded Algorithm is a trademark of Advanced Micro Device, Inc. Note: The manufacturer code and device code do not have the reading function. These codes cannot be accessed by the command. ■ Writing to/erasing flash memory The flash memory cannot be written to and read at the same time. That is, when data is written to or erased data from the flash memory, the program in the flash memory must first be copied to RAM. The entire process is then executed in RAM so that data is simply written to the flash memory. This eliminates the need for the program to access the flash memory from the flash memory itself. ■ Flash memory control status register (FMCS) FMCS Address: 0000AEH 482 7 6 5 4 3 2 1 0 INTE RDYINT WE RDY Reserved Reserved Reserved Reserved (R/W) (R/W) (R/W) (R) - - - - Initial value 000X0000B CHAPTER 23 1M-BIT FLASH MEMORY 23.2 Block Diagram of the Entire Flash Memory and Sector Configuration of the Flash Memory Figure 23.2-1 shows a block diagram of the entire flash memory with the flash memory interface circuit included. Figure 23.2-2 shows the sector configuration of the flash memory. ■ Block diagram of the entire flash memory Figure 23.2-1 Block diagram of the entire flash memory Flash memory interface circuit Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 F2MC-16LX bus 1M bit Flash memory BYTE INT BYTE CE CE OE OE WE WE AQ0 to AQ18 AQ0 to AQ17 AQ-1 DQ0 to DQ15 DQ0 to DQ15 RY/BY RY/BY RESET Write enable interrupt signal (to CPU) External reset signal RY/BY write enable signal ■ Sector configuration of the 1M-bit flash memory Figure 23.2-2 shows the sector configuration of the 1M-bit flash memory. The addresses in the figure indicate the high-order and low-order addresses of each sector. 483 CHAPTER 23 1M-BIT FLASH MEMORY Figure 23.2-2 Sector configuration of the 1M-bit flash memory Programmer address* CPU address SA4 (16 KByes) 7FFFFH FFFFFFH SA3 (8 KBytes) 7BFFFH FFBFFFH SA2 (8 KByes) 79FFFH FF9FFFH SA1 (32 KBytes) 77FFFH FF7FFFH 6FFFFH FEFFFFH 60000 H FE0000 H MB90F352/C/S/CS SA0 (64 KBytes) *: The programmer address is equivalent to the CPU address when data is written to the flash memory using a parallel programmer. When a general programmer is used for writing/erasing, this address is used for writing/erasing. 484 CHAPTER 23 1M-BIT FLASH MEMORY 23.3 Write/Erase Modes The flash memory can be accessed in two different ways: Flash memory mode and alternative mode. Flash memory mode enables data to be directly written to or erased from the external pins. Alternative mode enables data to be written to or erased from the CPU via the internal bus. Use the mode external pins to select the mode. ■ Flash memory mode The CPU stops when the mode pins are set to 111 while the reset signal is asserted. The flash memory interface circuit is connected directly to ports 0, 1, 2, 3, 4 and 5, enabling direct control from the external pins. This mode makes the MCU seem like a standard flash memory to the external pins, and write/erase can be performed using a flash memory programmer. In flash memory mode, all operations supported by the flash memory automatic algorithm can be used. ■ Alternative mode The flash memory is located in the FE to FF banks in the CPU memory space, and like ordinary mask ROM, can be read-accessed and program-accessed from the CPU via the flash memory interface circuit. Since writing/erasing the flash memory is performed by instructions from the CPU via the flash memory interface circuit, this mode allows rewriting even when the MCU is soldered on the target board. Sector protect operations cannot be performed in these modes. ■ Flash memory control signals Table 23.3-1 lists the flash memory control signals in flash memory mode. There is almost a one-to-one correspondence between the flash memory control signals and the external pins of the MBM29LV200. The VID (12 V) pins required by the sector protect operations are MD0, MD1, and MD2 instead of A9, RESET, and OE for the MBM29LV200. In flash memory mode, the external data bus signal width is limited to 8 bits, enabling only one-byte access. The DQ15 to DQ8 pins are not supported. The BYTE pin should always be set to 0. Table 23.3-1 Flash memory control signals (1/2) MB90F352 Pin number Normal function Flash memory mode MBM29LV200 54 P30 AQ16 A15 55 P31 CE CE 56 P32 OE OE 57 P33 WE WE 58 (59) P34 (P35) AQ17 (AQ18) A16 60 P36 BYTE BYTE LQFP 485 CHAPTER 23 1M-BIT FLASH MEMORY Table 23.3-1 Flash memory control signals (2/2) MB90F352 Pin number Normal function Flash memory mode MBM29LV200 19 P37 RY/BY RY/BY 52, 53 P44, P45 AQ8, AQ9 A7, A8 9 to 14 P50 to P55 AQ10 to AQ15 A9 to A14 23 MD0 MDO A9 (VID) 22 MD1 MD1 RESET (VID) 21 MD2 MD2 OE (VID) 24 to 31 P00 to P07 DQ0 to DQ7 DQ0 to DQ7 32 to 39 P10 to P17 DQ8 to DQ15 DQ8 to DQ15 45 RST RESET RESET 40 to 44, 51 P20 to P25 AQ0 to AQ5 A-1, A0 to A4 16, 17 P42, P43 AQ6, AQ7 A5, A6 LQFP 486 CHAPTER 23 1M-BIT FLASH MEMORY 23.4 Flash Memory Control Status Register (FMCS) The flash memory control status register (FMCS), together with the flash memory interface circuit, is used to write data to and erase data from the flash memory. ■ Flash memory control status register (FMCS) Figure 23.4-1 Flash memory control status register (FMCS) 7 6 5 4 3 2 1 0 INTE RDYINT WE RDY Reserved Reserved Reserved Reserved (R/W) (R/W) (R/W) (R) - - - - FMCS Address: 0000AEH Initial value 000X0000B ● Explanation of bits [Bit 7] INTE (interrupt enable) This bit generates an interrupt to the CPU when flash memory write/erase terminates. An interrupt to the CPU is generated when the INTE and RDYINT bits are 1. No interrupt is generated when the INTE bit is 0. • 0: Disables interrupts when write/erase terminates. • 1: Enables interrupts when write/erase terminates. [Bit 6] RDYINT (ready interrupt) This bit indicates the operating state of the flash memory. This bit is set to 1 when flash memory write/erase terminates. Data cannot be written to or erased from the flash memory while this bit is 0 after a flash memory write/erase. Flash memory write/erase is enabled when write/erase terminates and this bit is set to 1. Writing 0 clears this bit to 0. Writing 1 is ignored. This bit is set to 1 at the termination timing of the flash memory automatic algorithm (see Section "23.5 Starting the Flash Memory Automatic Algorithm"). When the read-modify-write (RMW) instruction is used, 1 is always read. • 0: Write/erase is being executed. • 1: Write/erase has terminated (interrupt request generated). [Bit 5] WE (write enable) This bit enables writing to the flash memory area. When this bit is 1, writing after the command sequence (see Section "23.5 Starting the Flash Memory Automatic Algorithm") is issued to the FC (F9) to FF bank writes to the flash memory area. When this bit is 0, the write/erase signal is not generated. This bit is used when the flash memory Write/Erase command is started. If write/erase is not performed, it is recommended that this bit be set to 0 to prevent data from being mistakenly written to the flash memory. • 0: Disables flash memory write/erase. • 1: Enables flash memory write/erase. 487 CHAPTER 23 1M-BIT FLASH MEMORY [Bit 4] RDY (ready) This bit enables flash memory write/erase. Flash memory write/erase is disabled while this bit is 0. However, Suspend commands, such as the Read/Reset command and Sector Erase Suspend command, can be accepted even if this bit is 0. • 0: Write/erase is being executed. • 1: Write/erase has terminated (next data write/erase enabled). [Bits 3 to 0] Reserved bits These bits are reserved for testing. During regular use, they should always be set to 0. Note: This register can be accessed only in byte-access mode. The RDYINT and RDY bits cannot be changed at the same time. Create a program so that decisions are made using one or the other of these bits. Figure 23.4-2 Transitions of the RDYINT and RDY bits Automatic algorithm Termination timing RDYINT bit RDY bit 1 machine cycle 488 CHAPTER 23 1M-BIT FLASH MEMORY 23.5 Starting the Flash Memory Automatic Algorithm Four types of commands are available for starting the flash memory automatic algorithm: Read/Reset, Write, and Chip Erase. Control of suspend and restart is enabled for sector erase. ■ Command sequence table Table 23.5-1 lists the commands used for flash memory write/erase. All of the data written to the command register is in bytes, but use word access to write. The data of the high-order bytes at this time is ignored. Table 23.5-1 Command sequence table Command sequence Bus write access 1st bus write cycle 2nd bus write cycle Address Data Address 1 FxXXXX XXF0 - 4 FxAAAA Write program 4 Chip Erase Sector Erase Read/Reset * Read/Reset * 4th bus write cycle 5th bus write cycle 6th bus write cycle Data Address Data Address Data Address Data Address Data - - - - - - - - XXAA Fx5554 XX55 FxAAAA XXF0 RA RD - - - - FxAAAA XXAA Fx5554 XX55 FxAAAA XXA0 - - - - 6 FxAAAA XXAA Fx5554 XX55 FxAAAA XX80 FxAAAA XXAA Fx5554 XX55 FxAAAA XX10 6 FxAAAA XXAA Fx5554 XX55 FxAAAA XX80 FxAAAA XXAA Fx5554 XX55 Sector Erase Suspend Sector Erase Restart Auto-select 3rd bus write cycle 3 FxAAA - PA PD (even) (word) SA XX30 (even) Entering address FxXXXX data (xxB0H) suspends erasing during sector erase. Entering address FxXXXX data (xx30H) restarts erasing after erasing is suspended during sector erase. XXAA Fx5554 XX55 FxAAAA XX90 - - - - - - 489 CHAPTER 23 1M-BIT FLASH MEMORY Note: • The addresses Fx in the table mean FF and FE for 1M-bit Flash Memory. Use these addresses as the access target bank values for operations. • The addresses in the table are the values in the CPU memory map. All addresses and data are represented using hexadecimal notation. However, the letter X is an optional value. • RA: Read address • PA: Write address. Only even addresses can be specified. • SA: Sector address. See Section "23.2 Configuration of the Flash Memory". Block Diagram of the Entire Flash Memory and Sector • RD: Read data • PD: Write data. Only word data can be specified. *: Both of the two types of Read/Reset commands can reset the flash memory to read mode. The Auto-select command shown in Table 23.5-1 is used to know the state of sector protection. When using the Auto-select command, set the address as follows. Table 23.5-2 Address setting at auto-select Sector protection AQ13 to AQ17 (,AQ18) AQ7 AQ2 AQ1 AQ0 DQ7 to DQ0 Sector Address L H L L CODE* *: When the sector address is protected, the output is "01H". When the sector address is not protected, the output is "00H". 490 CHAPTER 23 1M-BIT FLASH MEMORY 23.6 Confirming the Automatic Algorithm Execution State Because the write/erase flow of the flash memory is controlled using the automatic algorithm, the flash memory has hardware for posting its internal operating state and completion of operation. This automatic algorithm enables confirmation of the operating state of the built-in flash memory using the following hardware sequences. ■ Hardware sequence flags The hardware sequence flags are configured from the five-bit output of DQ7, DQ6, DQ5, DQ3 and DQ2. The functions of these bits are those of the data polling flag (DQ7), toggle bit flag (DQ6), timing limit exceeded flag (DQ5), sector erase timer flag (DQ3) and toggle bit-2 flag (DQ2). The hardware sequence flags can therefore be used to confirm that writing or chip sector erase has been completed or that erase code write is valid. The hardware sequence flags can be accessed by read-accessing the addresses of the target sectors in the flash memory after setting of the command sequence (see Table 23.5-1 in Section "23.5 Starting the Flash Memory Automatic Algorithm"). Table 23.6-1 lists the bit assignments of the hardware sequence flags. Table 23.6-1 Bit assignments of hardware sequence flags Bit No. 7 6 5 4 3 2 1 0 Hardware sequence flag DQ7 DQ6 DQ5 - DQ3 DQ2 - - To determine whether automatic writing or chip sector erase is being executed, the hardware sequence flags can be checked or the status can be determined from the RDY bit of the flash memory control register (FMCS) that indicates whether writing has been completed. After writing/erasing has terminated, the state returns to the read/reset state. When creating a program, use one of the flags to confirm that automatic writing/erasing has terminated. Then, perform the next processing operation, such as data read. In addition, the hardware sequence flags can be used to confirm whether the second or subsequent sector erase code write is valid. The following sections describe each hardware sequence flag separately. Table 23.6-2 lists the functions of the hardware sequence flags. 491 CHAPTER 23 1M-BIT FLASH MEMORY Table 23.6-2 Hardware sequence flag functions State State change for normal operation Write --> Write completed (write address specified) DQ6 DQ5 DQ3 DQ2 0 --> DATA:5 0 --> DATA:3 1 --> DATA:2 DQ7 --> DATA:7 Toggle --> DATA:6 0 --> 1 Toggle --> Stop 0 --> 1 1 Toggle --> Stop Sector erase wait --> Erase started 0 Toggle 0 0 --> 1 Toggle Erase --> Sector erase suspended (sector being erased) 0 --> 1 Toggle --> 1 0 1 --> 0 Toggle Sector erase suspend --> Erase restarted (sector being erased) 1 --> 0 1 --> Toggle 0 0 --> 1 Toggle DATA:7 DATA:6 DATA:5 DATA:3 DATA:2 DQ7 Toggle 1 0 1 0 Toggle 1 1 * Chip/sector erase --> Erase completed Sector erase suspended (sector not being erased) Abnormal operation DQ7 Write Chip/sector erase *: If the DQ5 outputs "1" (exceed the timing limit), successive reads from a writing or erasing sector cause DQ2 to toggle. DQ2 does not toggle when the successive reads are executed from other sectors. 492 CHAPTER 23 1M-BIT FLASH MEMORY 23.6.1 Data Polling Flag (DQ7) The data polling flag (DQ7) uses the data polling function to post that the automatic algorithm is being executed or has terminated ■ Data polling flag (DQ7) Table 23.6-3 and Table 23.6-4 list the state transitions of the data polling flag. Table 23.6-3 Data polling flag state transitions (state change for normal operation) Operating state Write --> Completed Chip/sector erase --> Completed Sector erase wait --> Started Sector erase --> Erase suspend (sector being erased) Sector erase suspend --> Restarted (sector being erased) Sector erase suspended (sector not being erased) DQ7 DQ7 --> 0 --> 1 0 0 --> 1 1 --> 0 DATA:7 Table 23.6-4 Data polling flag state transitions (state change for abnormal operation) Operating state Write Chip/sector erase DQ7 DQ7 0 ● Write Read-access during execution of the automatic write algorithm causes the flash memory to output the opposite data of bit 7 last written, regardless of the value at the address specified by the address signal. Read-access at the end of the automatic write algorithm causes the flash memory to output bit 7 of the read value of the address specified by the address signal. ● Chip/sector erase For a sector erase, read-access during execution of the chip erase/sector erase algorithm causes the flash memory to output 0 from the sector currently being erased. For a chip erase, read-access causes the flash memory to output 0 regardless of the value at the address specified by the address signal. Read-access at the end of the automatic write algorithm causes the flash memory to output 1 in the same way. ● Sector erase suspend Read-access during a sector erase suspend causes the flash memory to output 1 if the address specified by the address signal belongs to the sector being erased. The flash memory outputs bit 7 (DATA: 7) of the read value at the address specified by the address signal if the address specified by the address signal does not belong to the sector being erased. Referencing this flag together with the toggle bit flag (DQ6) enables a decision to be made on whether the flash memory is in the erase suspended state and which sector is being erased. Note: When the automatic algorithm is being started, read-access to the specified address is ignored. Since 493 CHAPTER 23 1M-BIT FLASH MEMORY termination of the data polling flag (DQ7) can be accepted for a data read and other bits output, data read after the automatic algorithm has terminated should be performed after read-access has confirmed that data polling has terminated. 494 CHAPTER 23 1M-BIT FLASH MEMORY 23.6.2 Toggle Bit Flag (DQ6) Like the data polling flag, the toggle bit flag (DQ6) uses the toggle bit function to post that the automatic algorithm is being executed or has terminated. ■ Toggle bit flag (DQ6) Table 23.6-5 and Table 23.6-6 list the state transitions of the toggle bit flag. Table 23.6-5 Toggle bit flag state transitions (state change for normal operation) Operating state Write --> Completed Chip/sector erase --> Completed Sector erase wait --> Started Sector erase --> Erase suspend (sector being erased) Sector erase suspend --> Restarted (sector being erased) Sector erase suspended (sector not being erased) DQ6 Toggle --> DATA:6 Toggle --> Stop Toggle Toggle --> 1 1 --> Toggle DATA:6 Table 23.6-6 Toggle bit flag state transitions (state change for abnormal operation) Operating state Write Chip/sector erase DQ6 Toggle Toggle ● Write/chip sector erase Continuous read-access during execution of the automatic write algorithm and chip/sector erase algorithm causes the flash memory to toggle the 1 or 0 state for every read cycle, regardless of the value at the address specified by the address signal. Continuous read-access at the end of the automatic write algorithm and chip/sector erase algorithm causes the flash memory to stop toggling bit 6 and output bit 6 (DATA: 6) of the read value of the address specified by the address signal. ● Sector erase suspend Read-access during a sector erase suspend causes the flash memory to output 1 if the address specified by the address signal belongs to the sector being erased. The flash memory outputs bit 6 (DATA: 6) of the read value at the address specified by the address signal if the address specified by the address signal does not belong to the sector being erased. Note: For a write, if the sector where data is to be written is rewrite-protected, the toggle bit terminates the toggle operation after approximately 2µs without any data being rewritten. For an erase, if all of the selected sectors are write-protected, the toggle bit performs toggling for approximately 100µs and then returns to the read/reset state without any data being rewritten. 495 CHAPTER 23 1M-BIT FLASH MEMORY 23.6.3 Timing Limit Exceeded Flag (DQ5) The timing limit exceeded flag (DQ5) is used to post that execution of the automatic algorithm has exceeded the time (internal pulse count) prescribed in the flash memory. ■ Timing limit exceeded flag (DQ5) Table 23.6-7 and Table 23.6-8 list the state transitions of the timing limit exceeded flag. Table 23.6-7 Timing limit exceeded flag state transitions (state change for normal operation) Operating state Write --> Completed DQ5 0 --> DATA:5 Chip/sector erase --> Completed Sector erase wait --> Started Sector erase --> Erase suspend (sector being erased) Sector erase suspend --> Restarted (sector being erased) Sector erase suspended (sector not being erased) 0 --> 1 0 0 0 DATA:5 Table 23.6-8 Timing limit exceeded bit flag state transitions (state change for abnormal operation) Operating state Write Chip/sector erase DQ5 1 1 ● Write/chip sector erase Read-access after write or chip/sector erase automatic algorithm activation causes the flash memory to output 0 if the time is within the prescribed time (time required for write/erase) or to output 1 if the prescribed time has been exceeded. Because this is done regardless of whether the automatic algorithm is being executed or has terminated, it is possible to determine whether write/erase was successful or unsuccessful. That is, when this flag outputs 1, writing can be determined to have been unsuccessful if the automatic algorithm is still being executed by the data polling function or toggle bit function. For example, writing 1 to a flash memory address where 0 has been written will cause the fail state to occur. In this case, the flash memory will lock and execution of the automatic algorithm will not terminate. As a result, valid data will not be output from the data polling flag (DQ7). In addition, the toggle bit flag (DQ6) will exceed the time limit without stopping the toggle operation and the timing limit exceeded flag (DQ5) will output 1. Note that this state indicates that the flash memory is not faulty, but has been used correctly. When this state occurs, execute the Reset command. 496 CHAPTER 23 1M-BIT FLASH MEMORY 23.6.4 Sector Erase Timer Flag (DQ3) The sector erase timer flag (DQ3) is used to post whether the automatic algorithm is being executed during the sector erase wait period after the Sector Erase command has been started. ■ Sector erase timer Flag (DQ3) Table 23.6-9 and Table 23.6-10 list the state transitions of the sector erase timer flag. Table 23.6-9 Sector erase timer flag state transitions (state change for normal operation) Operating state Write --> Completed DQ3 0 --> DATA:3 Chip/sector erase --> Completed Sector erase wait --> Started Sector erase --> Erase suspend (sector being erased) Sector erase suspend --> Restarted (sector being erased) Sector erase suspended (sector not being erased) 1 0 --> 1 1 --> 0 0 --> 1 DATA:3 Table 23.6-10 Sector erase timer flag state transitions (state change for abnormal operation) Operating state Write Chip/sector erase DQ3 0 1 ● Sector erase Read-access after the Sector Erase command has been started causes the flash memory to output 0 if the automatic algorithm is being executed during the sector erase wait period, regardless of the value at the address specified by the address signal of the sector that issued the command. The flash memory outputs 1 if the sector erase wait period has been exceeded. If the data polling function or toggle bit function indicates that the erase algorithm is being executed, internally controlled erase has already started if this flag is 1. Continuous write of the sector erase codes or commands other than the Sector Erase Suspend command will be ignored until erase is terminated. If this flag is 0, the flash memory will accept write of additional sector erase codes. To confirm this, it is recommended that the state of this flag be checked before continuing to write sector erase codes. If this flag is 1 after the second state check, it is possible that additional sector erase codes may not be accepted. ● Read access during sector erase Read-access during execution of sector erase suspend causes the flash memory to output 1 if the address specified by the address signal belongs to the sector being erased. If this address does not belong to the sector being erased, the flash memory outputs bit 3 (DATA:3) of the corresponding memory value. 497 CHAPTER 23 1M-BIT FLASH MEMORY 23.6.5 Toggle Bit-2 Flag (DQ2) The toggle bit-2 flag (DQ2) is a flag that uses the toggle bit function to indicate that the sector is in the erase-suspended state. ■ Toggle bit-2 flag (DQ2) Table 23.6-11 and Table 23.6-12 list the state transitions of the toggle bit flag. Table 23.6-11 Toggle bit-2 flag state transitions (state change for normal operation) Operating state Write --> Completed Chip/sector erase --> Completed Sector erase wait --> Started Sector erase --> Erase suspend (sector being erased) Sector erase suspend --> Restarted (sector being erased) Sector erase suspended (sector not being erased) DQ2 1 --> DATA:2 Toggle --> Stop Toggle Toggle Toggle DATA:2 Table 23.6-12 Toggle bit-2 flag state transitions (state change for abnormal operation) Operating state Write Chip/sector erase DQ2 1 * *: If the DQ5 outputs "1" (exceed the timing limit), successive reads from a writing or erasing sector cause DQ2 to toggle. DQ2 does not toggle when the successive reads are executed from other sectors. ● During a sector erase operation If successive reads are executed during the execution of the chip sector erase algorithm, a flash memory toggles to output "1" and "0" to addresses alternately at every read access regardless of the location indicated by the addresses. If successive reads are executed after the chip sector erase algorithm is completed, the flash memory stops the toggle operation of the bit 2 and outputs the read value of the bit 2 (DATA: 2) to the location indicated by the address. 498 CHAPTER 23 1M-BIT FLASH MEMORY ● While a sector erase operation is suspended If successive reads are executed while a sector erase operation is suspended, and if the address indicates the sector to be erased, the flash memory toggles to alternately output "1" and "0". If the address indicates the sector is not to be erased, the flash memory outputs the read value of the bit 2 (DATA: 2) to the location indicated by the address. In the erase-suspend-program mode, successive reads from the non-erase suspended sector causes the flash memory to output "1". Both DQ2 and DQ6 are used for detecting an erase-suspended sector (DQ2 toggles, but DQ6 does not). DQ2 is also used for detecting an erasing sector. While erasing a sector, if a read access is executed from the erasing sector, DQ2 toggles. Reference: If all sectors selected for erasing are write-protected, the toggle bit-2 toggles for about 100µs, and then returns to the read/reset mode without writing the data. 499 CHAPTER 23 1M-BIT FLASH MEMORY 23.7 Detailed Explanation of Writing to and Erasing Flash Memory This section describes each operation procedure of flash memory Read/Reset, Write, Chip Erase, Sector Erase, Sector Erase Suspend, and Sector Erase Restart when a command that starts the automatic algorithm is issued. ■ Detailed explanation of flash memory write/erase The flash memory executes the automatic algorithm by issuing a command sequence (see Table 23.5-1 in Section "23.5 Starting the Flash Memory Automatic Algorithm") for a write cycle to the bus to perform Read/Reset, Write, Chip Erase, Sector Erase, Sector Erase Suspend, or Sector Erase Restart operations. Each bus write cycle must be performed continuously. In addition, whether the automatic algorithm has terminated can be determined using the data polling or other function. At normal termination, the flash memory is returned to the read/reset state. Each operation of the flash memory is described in the following order: • Setting the read/reset state • Writing data • Erasing all data (erasing chips) • Erasing optional data (erasing sectors) • Suspending sector erase • Restarting sector erase 500 CHAPTER 23 1M-BIT FLASH MEMORY 23.7.1 Setting The Read/Reset State This section describes the procedure for issuing the Read/Reset command to set the flash memory to the read/reset state. ■ Setting the flash memory to the read/reset state The flash memory can be set to the read/reset state by sending the Read/Reset command in the command sequence table (see Table 23.5-1 in Section "23.5 Starting the Flash Memory Automatic Algorithm") continuously to the target sector in the flash memory. The Read/Reset command has two types of command sequences that execute the first and third bus operations. However, there are no essential differences between these command sequences. The read/reset state is the initial state of the flash memory. When the power is turned on and when a command terminates normally, the flash memory is set to the read/reset state. In the read/reset state, other commands wait for input. In the read/reset state, data is read by regular read-access. As with the mask ROM, program access from the CPU is enabled. The Read/Reset command is not required to read data by a regular read. The Read/Reset command is mainly used to initialize the automatic algorithm in such cases as when a command does not terminate normally. 501 CHAPTER 23 1M-BIT FLASH MEMORY 23.7.2 Writing Data This section describes the procedure for issuing the Write command to write data to the flash memory. ■ Writing data to the flash memory The data write automatic algorithm of the flash memory can be started by sending the Write command in the command sequence table (see Table 23.5-1 in Section "23.5 Starting the Flash Memory Automatic Algorithm") continuously to the target sector in the flash memory. When data write to the target address is completed in the fourth cycle, the automatic algorithm and automatic write are started. ● Specifying addresses Only even addresses can be specified as the write addresses specified in a write data cycle. Odd addresses cannot be written correctly. That is, writing to even addresses must be done in units of word data. Writing can be done in any order of addresses or even if the sector boundary is exceeded. However, the Write command writes only data of one word for each execution. ● Notes on writing data Writing cannot return data 0 to data 1. When data 1 is written to data 0, the data polling algorithm (DQ7) or toggle operation (DQ6) does not terminate and the flash memory elements are determined to be faulty. If the time prescribed for writing is thus exceeded, the timing limit exceeded flag (DQ5) is determined to be an error. Otherwise, the data is viewed as if dummy data 1 had been written. However, when data is read in the read/reset state, the data remains 0. Data 0 can be set to data 1 only by erase operations. All commands are ignored during execution of the automatic write algorithm. If a hardware reset is started during writing, the data of the written addresses will be unpredictable. ■ Writing to the flash memory Figure 23.7-1 is an example of the procedure for writing to the flash memory. The hardware sequence flags (see Section "23.6 Confirming the Automatic Algorithm Execution State") can be used to determine the state of the automatic algorithm in the flash memory. Here, the data polling flag (DQ7) is used to confirm that writing has terminated. The data read to check the flag is read from the address written to last. The data polling flag (DQ7) changes at the same time that the timing limit exceeded flag (DQ5) changes. For example, even if the timing limit exceeded flag (DQ5) is 1, the data polling flag bit (DQ7) must be rechecked. Also for the toggle bit flag (DQ6), the toggle operation stops at the same time that the timing limit exceeded flag bit (DQ5) changes to 1. The toggle bit flag (DQ6) must therefore be rechecked. 502 CHAPTER 23 1M-BIT FLASH MEMORY Figure 23.7-1 Example of the flash memory write procedure Start writing FMCS: WE (bit 5) Enable flash memory write Write command sequence (1) FxAAAA <-- XXAA (2) Fx5554 <-- XX55 (3) FxAAAA <-- XXA0 (4) Write address <-- Write data Read internal address Data polling (DQ7) Next address Data Data 0 Timing limit (DQ5) 1 Read internal address Data Data polling (DQ7) Data Write error Final address FMCS: WE (bit 5) Disable flash memory write Complete writing Confirm with the hardware sequence flags. 503 CHAPTER 23 1M-BIT FLASH MEMORY 23.7.3 Erasing All Data (Erasing Chips) This section describes the procedure for issuing the Chip Erase command to erase all data in the flash memory. ■ Erasing all data in the flash memory (erasing chips) All data can be erased from the flash memory by sending the Chip Erase command in the command sequence table (see Table 23.5-1 in Section "23.5 Starting the Flash Memory Automatic Algorithm") continuously to the target sector in the flash memory. The Chip Erase command is executed in six bus operations. When writing of the sixth cycle is completed, the chip erase operation is started. For chip erase, the user need not write to the flash memory before erasing. During execution of the automatic erase algorithm, the flash memory writes 0 for verification before all of the cells are erased automatically. 504 CHAPTER 23 1M-BIT FLASH MEMORY 23.7.4 Erasing Optional Data (Erasing Sectors) This section describes the procedure for issuing the Sector Erase command to erase optional data (erase sector) in the flash memory. Individual sectors can be erased. Multiple sectors can also be specified at one time. ■ Erasing optional data (erasing sectors) in the flash memory Optional sectors in the flash memory can be erased by sending the Sector Erase command in the command sequence table (see Table 23.5-1 in Section "23.5 Starting the Flash Memory Automatic Algorithm") continuously to the target sector in the flash memory. ● Specifying sectors The Sector Erase command is executed in six bus operations. Sector erase wait of 50µs is started by writing the sector erase code (30H) to an accessible even-numbered address in the target sector in the sixth cycle. To erase multiple sectors, write the erase code (30H) to the addresses in the target sectors after the above processing operation. ● Notes on specifying multiple sectors Erase is started when the sector erase wait period of 50µs terminates after the final sector erase code has been written. That is, to erase multiple sectors at one time, an erase code (sixth cycle of the command sequence) must be written within 50µs of writing of the address of a sector and the address of the next sector must be written within 50µs of writing of the previous erase code. Otherwise, the address and erase code may not be accepted. The sector erase timer (hardware sequence flag DQ3) can be used to check whether writing of the subsequent sector erase code is valid. At this time, specify so that the address used for reading the sector erase timer indicates the sector to be erased. ■ Erasing sectors in the flash memory The hardware sequence flags (see Section "23.6 Confirming the Automatic Algorithm Execution State") can be used to determine the state of the automatic algorithm in the flash memory. Figure 23.7-2 is an example of the procedure for erasing sectors in the flash memory. Here, the toggle bit flag (DQ6) is used to confirm that erasing has terminated. The data that is read to check the flag is read from the sector to be erased. The toggle bit flag (DQ6) stops the toggle operation at the same time that the timing limit exceeded flag (DQ5) is changed to 1. For example, even if the timing limit exceeded flag (DQ5) is 1, the toggle bit flag (DQ6) must be rechecked. The data polling flag (DQ7) also changes at the same time that the timing limit exceeded flag bit (DQ5) changes. As a result, the data polling flag (DQ7) must be rechecked. 505 CHAPTER 23 1M-BIT FLASH MEMORY Figure 23.7-2 Example of the flash memory sector erase procedure Start erasing FMCS: WE (bit 5) Enable flash memory erase Erase command sequence (1) FxAAAA <-- XXAA (2) Fx5554 <-- XX55 (3) FxAAAA <-- XX80 (4) FxAAAA <-- XXAA (5) Fx5554 <-- XX55 1 Sector erase timer (DQ3) Read internal address 0 (6) Enter code to erase sector (30H) Y Another erase sector N Read internal address 1 Next sector Read internal address 2 Toggle bit (DQ6) data 1(DQ6) = data 2(DQ6) Y N 0 Timing limit (DQ5) 1 Read internal address 1 Read internal address 2 N Toggle bit (DQ6) data 1(DQ6) = data 2(DQ6) Y Erase error Final sector N Y FMCS: WE (bit 5) Disable flash memory erase Confirm with the hardware sequence flags. Complete erasing 506 CHAPTER 23 1M-BIT FLASH MEMORY 23.7.5 Suspending Sector Erase This section describes the procedure for issuing the Sector Erase Suspend command to suspend erasing of flash memory sectors. Data can be read from sectors that are not being erased. ■ Suspending erasing of flash memory sectors Erasing of flash memory sectors can be suspended by sending the Sector Erase Suspend command in the command sequence table (see Table 23.5-1 in Section "23.5 Starting the Flash Memory Automatic Algorithm") continuously to the target sector in the flash memory. The Sector Erase Suspend command suspends the sector erase operation being executed and enables data to be read from sectors that are not being erased. In this state, only reading is enabled; data cannot be written. This command is valid only during sector erase operations that include the erase wait time. The command will be ignored during chip erase or write operations. This command is implemented by writing the erase suspend code (B0h). At this time, specify an optional address in the flash memory for the address. An Erase Suspend command issued again during erasing of sectors will be ignored. Entering the Sector Erase Suspend command during the sector erase wait period will immediately terminate sector erase wait, cancel the erase operation, and set the erase stop state. Entering the Erase Suspend command during the erase operation after the sector erase wait period has terminated will set the erase suspend state after a maximum period of 15µs has elapsed. 507 CHAPTER 23 1M-BIT FLASH MEMORY 23.7.6 Restarting Sector Erase This section describes the procedure for issuing the Sector Erase Restart command to restart suspended erasing of flash memory sectors. ■ Restarting erasing of flash memory sectors Suspended erasing of flash memory sectors can be restarted by sending the Sector Erase Restart command in the command sequence table (see Table 23.5-1 in Section "23.5 Starting the Flash Memory Automatic Algorithm") continuously to the target sector in the flash memory. The Sector Erase Restart command is used to restart erasing of sectors from the sector erase suspend state set using the Sector Erase Suspend command. The Sector Erase Restart command is implemented by writing the erase restart code (30H). At this time, specify an optional address in the flash memory area for the address. If a Sector Erase Restart command is issued during sector erase, the command will be ignored. 508 CHAPTER 23 1M-BIT FLASH MEMORY 23.8 Notes on using 1M-bit Flash Memory This section contains notes on using 1M-bit flash memory. ■ Notes on using flash memory ● Input of a hardware reset (RST) To input a hardware reset when the automatic algorithm has not been started and reading is in progress, a minimum low-level width of 500 ns must be maintained. In this case, a maximum of 500 ns is required until data can be read from the flash memory after a hardware reset has been activated. Similarly, to input a hardware reset when the automatic algorithm has been activated and writing or erasing is in progress, a minimum low-level width of 50 ns must be maintained. In this case, 20 µs are required until data can be read after the operation for initializing the flash memory has terminated. A hardware reset during writing the data being written to be undefined. A hardware reset during erasing may make the sector being erased unusable. ● Canceling of a software reset and watchdog timer reset When the flash memory is being written to or erased with CPU access and if reset conditions occur while the automatic algorithm is active, the CPU may run out of control. This occurs because these reset conditions cause the automatic algorithm to continue without initializing the flash memory unit, possibly preventing the flash memory unit from entering the read state when the CPU starts the sequence after the reset has been deasserted. These reset conditions must be disabled during writing to or erasing of the flash memory. ● Program access to flash memory When the automatic algorithm is operating, read access to the flash memory is disabled. With the memory access mode of the CPU set to internal ROM mode, writing or erasing must be started after the program area is switched to another area such as RAM. In this case, when sectors (SA4) containing interrupt vectors are erased, writing or erasing interrupt processing cannot be executed. For the same reason, all interrupt sources other than the flash memory are disabled while the automatic algorithm is operating. Also, while the automatic algorithm is being executed, all interrupt sources except flash memory are disabled. ● Hold function When the CPU accepts a hold request, the Write signal WE of the flash memory unit may be skewed, causing erroneous writing or erasing due to an erroneous write. When the acceptance of a hold request is enabled (HDE bit of EPCR set to 1), ensure that the WE bit of the control status register (FMCS) is 0. ● Extended intelligent I/O service (EI2OS) Because write and erase interrupts issued to the CPU from the flash memory interface circuit cannot be accepted by the EI2OS, they should not be used. 509 CHAPTER 23 1M-BIT FLASH MEMORY ● Applying VID Applying VID required for the sector protect operation should always be started and terminated when the supply voltage is on. 510 CHAPTER 23 1M-BIT FLASH MEMORY 23.9 Flash Security Feature Flash Security Feature provides possibilities to protect the content of the flash memory from being read from external pins. ■ Abstract By writing the protection code of "01H" to one predefined address of the flash memory(1M-bit flash memory:FE0001H), access to the flash memory is restricted. Once the flash memory is protected, performing the chip erase operation only can unlock the function. Otherwise read/write access to the flash memory from the external pins is not possible. This function is suitable for applications requiring security of self-containing and data stored in the flash memory. ■ How to enable the Flash Security Feature After writing the code "01H" to the predefined address of each flash memory(1M-bit flash memory: FE0001H), the following external reset or power-on enables the Flash Security Feature. ■ How to disable the Flash Security Feature Performing the chip erase operation. Behavior under the Flash Security Feature Read operation: invalid data read Write operation: ignored ■ Others (1) About configuration of the standard parallel programmer, please follow to the specification of parallel programmer. (2) Writing the protection code at the last of flash memory programming is recommended, in order to prevent the device from enabling the Flash Security Feature accidentally. 511 CHAPTER 23 1M-BIT FLASH MEMORY 23.10 Example of Programming 1M-bit Flash Memory This section presents a programming example of 1M-bit flash memory. ■ Programming example of 1M-bit flash memory Flash Memory Sample Program NAME FLASHWE TITLE FLASHWE ;------------------------------------------------------------------------------;1M-bit-FLASH test program ; ;1: Transmits the program (address: FFA000H, sector: SA3) from FLASH to RAM ; (address: 000800H). ;2: Executes the program on RAM. ;3: Writes the PDR1 value to FLASH (address: FF0000H, sector: SA1). ;4: Reads the written value (address: FF0000H, sector: SA1) and outputs it to PDR2. ;5: Erases the written sector (SA1). ;6: Checks and outputs erase data. ;Conditions ; - Number of bytes transmitted to RAM: 100H (256B) ; - Write/erase termination judgment ; Judgment according to DQ5 (timing limit excess flag) ; Judgment according to DQ6 (toggle bit flag) ; Judgment according to RDY (FMCS) ; - Error handling ; Hi output to P00 to P07 ; Reset command issuance ;------------------------------------------------------------------; RESOUS IOSEG ABS=00 ;"RESOUS" I/O segment definition ORG 0000H PDR0 RB 1 PDR1 RB 1 PDR2 RB 1 PDR3 RB 1 ORG 0010H DDR0 RB 1 DDR1 RB 1 DDR2 RB 1 DDR3 RB 1 ORG 00A1H CKSCR RB 1 ORG 00AEH FMCS RB 1 ORG 006FH ROMM RB 1 RESOUS ENDS ; SSTA SSEG RW 0127H STA_T RW 1 SSTA ENDS ; DATA DSEG ABS=0FFH ;FLASH command address ORG 5554H COMADR2 RW 1 ORG 0AAAAH COMADR1 RW 1 DATA ENDS 512 CHAPTER 23 1M-BIT FLASH MEMORY ;///////////////////////////////////////////////////////////// ;Main program (FFA000H) ;///////////////////////////////////////////////////////////// CODE CSEG START: ; ///////////////////////////////////////////////////// ; Initialization ; ///////////////////////////////////////////////////// MOV CKSCR,#0BAH ;3-multiple setting MOV RP,#0 MOV A,#!STA_T MOV SSB,A MOVW A,#STA_T MOVW SP,A MOV ROMM,#00H ;Mirror OFF MOV PDR0,#00H ;For error check MOV DDR0,#0FFH MOV PDR1,#00H ;Port for data input MOV DDR1,#00H MOV PDR2,#00H ;Port for data output MOV DDR2,#0FFH ; ////////////////////////////////////////////////////////////// ; Transfer of "FLASH write erase program (FFA000H)" to RAM (0800H address) ; ////////////////////////////////////////////////////////////// MOVW A,#0800H ;Transfer destination RAM area MOVW A,#0A000H ;Transfer source address (program position) MOVW RW0,#100H ;Number of bytes to be transferred MOVS ADB,PCB ;Transfer of 100H from FFA000H to 000800H CALLP 001500H ;Jump to the address containing the transferred ; program ; ///////////////////////////////////////////////////// ; Data output ; ///////////////////////////////////////////////////// OUT MOV A,#0FFH MOV ADB,A MOVW RW2,#0000H MOVW A,@RW2+00 MOV PDR2,A END JMP * CODE ENDS ;//////////////////////////////////////////////////////////// ;FLASH write erase program (SA3) ;//////////////////////////////////////////////////////////// RAMPRG CSEG ABS=0FFH ORG 0BC00H ; //////////////////////////////////////////// Initialization ; //////////////////////////////////////////// MOVW RW0,#0500H ;RW0:RAM space for input data acquisition From 00:0500 MOVW RW2,#0000H ;RW2:Flash memory write address From FF:0000 MOV A,#00H ;DTB modification MOV DTB,A ;Bank specification for @RW0 MOV A,#0FFH ;ADB modification 1 MOV ADB,A ;Bank specification for write mode specification ; address MOV PDR3,#00H ;Switch initialization MOV DDR3,#00H ; WAIT1 BBC PDR3:0,WAIT1 ;PDR3: 0(write start at high level) ; 513 CHAPTER 23 1M-BIT FLASH MEMORY ;//////////////////////////////////////////////// ;Write (SA1) ;//////////////////////////////////////////////// MOV A,PDR1 MOVW @RW0+00,A ;PDR1 data allocation to RAM MOV FMCS,#20H ;Write mode setting MOVW ADB:COMADR1,#00AAH ;Flash write command 1 MOVW ADB:COMADR2,#0055H ;Flash write command 2 MOVW ADB:COMADR1,#00A0H ;Flash write command 3 ; MOVW A,@RW0+00 ;Input data (RW0) write to flash memory (RW2) MOVW @RW2+00,A WRITE ;Wait time check ; /////////////////////////////////////////////////////////////////// ; ERROR when the time limit excess check flag is set and toggle operation is ; in progress ; /////////////////////////////////////////////////////////////////// MOVW A,@RW2+00 AND A,#20H ;DQ5 time limit check BZ NTOW ;Time limit over MOVW A,@RW2+00 ;AH MOVW A,@RW2+00 ;AL XORW A ;XOR of AH and AL (1 when the values differ) AND A,#40H ;Is the DQ6 toggle bit different? BNZ ERROR ;To ERROR when the DQ6 toggle bit is different ; /////////////////////////////////////// ; Write termination check (FMCS-RDY) ; /////////////////////////////////////// ; /////////////////////////////////////// NTOW MOV A,FMCS AND A,#10H ;Extraction of FMCS RDY bit (bit 4) BZ WRITE ;End of write? MOV FMCS,#00H ;Write mode release ; ///////////////////////////////////////////////////// ; Write data output ; ///////////////////////////////////////////////////// MOVW RW2,#0000H ;Write data output MOVW A,@RW2+00 MOV PDR2,A ; WAIT2 BBC PDR3:1,WAIT2 ;PDR3: 1(sector erase start at high level) ; ;///////////////////////////////////////////// ;Sector erase (SA1) ;///////////////////////////////////////////// MOV @RW2+00,#0000H ;Address initialization MOV FMCS,#20H ;Erase mode setting MOVW ADB:COMADR1,#00AAH ;Flash erase command 1 MOVW ADB:COMADR2,#0055H ;Flash erase command 2 MOVW ADB:COMADR1,#0080H ;Flash erase command 3 MOVW ADB:COMADR1,#00AAH ;Flash erase command 4 MOVW ADB:COMADR2,#0055H ;Flash erase command 5 MOV @RW2+00,#0030H ;Issuance of erase command 6 to the sector to be erased ELS ;Wait time check ; /////////////////////////////////////////////////////////////////// ; ERROR when the time limit excess check flag is set and toggle operation is ; in progress ; /////////////////////////////////////////////////////////////////// MOVW A,@RW2+00 AND A,#20H ;DQ5 time limit check BZ NTOE ;Time limit over MOVW A,@RW2+00 ;AH High and Low are alternately output from MOVW A,@RW2+00 ;AL DQ6 per read during write operation. XORW A ;XOR of AH and AL (If the DQ6 value differs, ; write operation is in progress (1)). AND A,#40H ;Is the DQ6 toggle bit High? BNZ ERROR ;ERROR when the DQ6 toggle bit is High 514 CHAPTER 23 1M-BIT FLASH MEMORY ; ; ; NTOE /////////////////////////////////////// Erase termination check (FMCS-RDY) /////////////////////////////////////// MOV A,FMCS ; AND A,#10H ;Extraction of FMCS RDY bit (bi BZ ELS ;End of sector erase? MOV FMCS,#00H ;FLASH erase mode release RETP ;Return to the main program ;////////////////////////////////////////////// ;Error ;////////////////////////////////////////////// ERROR MOV FMCS,#00H ;FLASH mode release MOV PDR0,#0FFH ;Error handling check MOV ADB:COMADR1,#0F0H ;Reset command (read is enabled RETP ;Return to the main program RAMPRG ENDS ;///////////////////////////////////////////// VECT CSEG ABS=0FFH ORG 0FFDCH DSL START DB 00H VECT ENDS ; 515 CHAPTER 23 1M-BIT FLASH MEMORY 516 CHAPTER 24 EXAMPLES OF MB90F352/C(S) PROGRAMMING CONNECTION This chapter provides examples of F2MC-16LX MB90F352 serial programming connection. 24.1 Basic Configuration of F2MC-16LX MB90F352/C(S) Serial Programming Connection” 24.2 Example of Serial Programming Connection (User Power Supply Used) 24.3 Example of Serial Programming Connection (Power Supplied from the Programmer) 24.4 Example of Minimum Connection to the Flash Microcomputer Programmer (User Power Supply Used) 24.5 Example of Minimum Connection to the Flash Microcomputer Programmer (Power Supplied from the Programmer) 517 CHAPTER 24 EXAMPLES OF MB90F352/C(S) PROGRAMMING CONNECTION 24.1 Basic Configuration of MB90F352/C(S) Serial Programming Connection The MB90F352/C(S) supports flash ROM serial onboard programming (Fujitsu standard). This section describes the specifications. ■ Basic configuration of MB90F352/C(S) serial programming connection The AF220/AF210/AF120/AF110 flash microcomputer programmer from Yokogawa Digital Computer Corporation is used for Fujitsu standard serial onboard programming. Figure 24.1-1 Fujitsu standard serial onboard programming of MB90F352/C(S) Host interface cable (AZ201) AF220/AF210/ AF120/AF110 flash microcomputer programmer + memory card General-purpose common cable (AZ210) CLK synchronous serial MB90F352/C(S) User system Stand-alone operation enabled Note: Ask the company representative from Yokogawa Digital Computer Corporation for details about the functions and operations of the AF220/AF210/AF120/AF110 flash microcomputer programmer, general-purpose common cable for connection (AZ210), and connectors. Table 24.1-1 Pins used for Fujitsu standard serial onboard programming (1/2) Pin Function Additional information MD2, MD1 MD0 Mode pins Controls programming mode from the flash microcomputer programmer. X0, X1 Oscillation pins In programming mode, the CPU internal operation clock signal is one multiple of the PLL clock signal frequency. Therefore, because the oscillation clock frequency becomes the internal operation clock signal, the oscillator used for serial reprogramming is 3 MHz to 16 MHz. P00, P01 programming activation pins Set P00 to an input of "L" level and P01 to an input of "H" level. RST Reset pin SIN3 Serial data input pin SOT3 Serial data output pin SCK3 Serial clock signal input pin C C pin 518 - Serial input-output is used. This external capacitor pin is used to stabilize the power supply. Connect a ceramic capacitor of approximately 0.1 µF to the outside. CHAPTER 24 EXAMPLES OF MB90F352/C(S) PROGRAMMING CONNECTION Table 24.1-1 Pins used for Fujitsu standard serial onboard programming (2/2) Pin Function Additional information VCC Power voltage supply pin If the programming voltage (5 V ± 10%) is supplied from the user system, the flash microcomputer programmer need not be connected. Connect so that the power supply of the user side is not short-circuited. VSS GND pin Common to the ground of the flash microcomputer programmer. Even if the P00, P01, SIN3 SOT3, and SCK3 pins are used for the user system, the control circuit shown in the figure below is required. The /TICS signal of the flash microcomputer programmer can be used to disconnect the user circuit during serial programming. Sections "24.2 Example of Serial Programming Connection (User Power Supply Used)" to "24.5 Example of Minimum Connection to the Flash Microcomputer Programmer (Power Supplied from the Programmer)" present examples the following four types of serial programming connection. See each Section as required. • Serial programming connection (user power supply used) • Serial programming connection (power supplied from the programmer) • Minimum connection to the flash microcomputer programmer (user power supply used) • Minimum connection to the flash microcomputer programmer (power supplied from the programmer) Figure 24.1-2 Connecting user circuitry for serial programming AF220/AF210/ AF120/AF110 write control pin MB90F352/C(S) write control pin 10 kΩ AF220/AF210/ AF120/AF110 TICS pin User Table 24.1-2 System configuration of flash microcomputer programmers (manufactured by Yokogawa Digital Computer Corporation) (1/2) Model Main unit Function AF220/AC4P Ethernet interface built-in model and 100 to 220 V AC power adapter AF210/AC4P Standard model and 100 to 220 V AC power adapter AF120/AC4P Single-key Ethernet interface built-in model and 100 to 220 V AC power adapter AF110/AC4P Single-key model and 100 to 220 V AC power adapter AZ221 PC/AT RS232C cable for programmer AZ210 Standard target probe (a) with a 1 m cable FF201 Fujitsu F2MC-16LX flash microcomputer control module 519 CHAPTER 24 EXAMPLES OF MB90F352/C(S) PROGRAMMING CONNECTION Table 24.1-2 System configuration of flash microcomputer programmers (manufactured by Yokogawa Digital Computer Corporation) (2/2) Model Function AZ290 Remote controller /P2 2 MB PC card (optional) for flash memory sizes up to 128 KB /P4 4 MB PC card (optional) for flash memory sizes up to 512 KB Inquiries: Yokogawa Digital Computer Corporation Telephone number: (81)-42-333-6222 Note: Although the AF200 flash microcomputer programmer is no longer manufactured, the programmer still can be used in combination with the FF201 control module. Examples of serial programming connection are given in Sections "24.2 Example of Serial Programming Connection (User Power Supply Used)" and "24.3 Example of Serial Programming Connection (Power Supplied from the Programmer)". ■ Oscillating clock frequency and serial clock input frequency The equation listed below can be used to calculate the serial clock frequencies that can be used for the MB90F352/C(S). Set an appropriate serial clock input frequency in the flash microcomputer programmer according to the oscillating clock frequency in use. fSC = 0.125 × fOSC, where fSC is the serial clock frequency and fOSC is the oscillating clock frequency. Table 24.1-3 Examples of serial clock frequencies that can be used Oscillating clock frequency Maximum serial clock frequency that can be used for microcomputers Maximum serial clock frequency that can be used for the AF220, AF210, AF120, and AF110 Maximum serial clock frequency that can be used for the AF200 4 MHz 500 kHz 500 kHz 500 kHz 8 MHz * 1 MHz 850 kHz 500 kHz 16 MHz * 2 MHz 1.25 MHz 500 kHz *: External clock only. 520 CHAPTER 24 EXAMPLES OF MB90F352/C(S) PROGRAMMING CONNECTION 24.2 Example of Serial Programming Connection (User Power Supply Used) Figure 24.2-1 is an example of a serial programming connection for internal vector modes (single-chip mode) when the user power supply is used. The value 1 and 0 are input to mode pins MD2 and MD0 from TAUX3 and TMODE of the AF220/AF210/AF120/AF110 programmer. Serial reprogramming mode: MD2, MD1, MD0 = 110B. ■ Example of serial programming connection (user power supply used) Figure 24.2-1 Example of serial programming connection for MB90F352/C(S) internal vector modes (user power supply used) AF220/AF210/AF120/AF110 flash microcomputer programmer TAUX3 User system Connector DX10-28S or DX20-28S MB90F352/C(S) MD2 (19) 10 kΩ 10 kΩ MD1 10 kΩ TMODE MD0 X0 (12) X1 TAUX P00 (23) 10 kΩ /TICS (10) User 10 kΩ 10 kΩ /TRES RST (5) 10 kΩ User 0.1 µF or more TTXD TRXD TCK (13) (27) (6) TVcc (2) GND (7, 8, 14,15, 21, 22 1, 28) P01 C SIN3 SOT3 SCK3 Vcc User power supply Vss Pin 14 Pins 3, 4, 9, 11, 16, 17, 18, 20, 24, 25, and 26 are open. DX10-28S: Right-angle type DX20-28S: Straight type Pin 1 DX10-28S DX20-28S Pin 28 Pin 15 Connector (Hirose Electronics Ltd.) pin arrangement • Even if the SIN3, SOT3, and SCK3 pins are used for the user system, the control circuit shown in the figure below is required in the same way that it is for P00. The /TICS signal of the flash microcomputer programmer can be used to disconnect the user circuit during serial programming. 521 CHAPTER 24 EXAMPLES OF MB90F352/C(S) PROGRAMMING CONNECTION • Connect the AF220/AF210/AF120/AF110 while the user power is off. Figure 24.2-2 Connecting user circuitry (detail) AF220/AF210/ AF120/AF110 write control pin MB90F352/C(S) write control pin 10 kΩ AF220/AF210/ AF120/AF110 TICS pin User 522 CHAPTER 24 EXAMPLES OF MB90F352/C(S) PROGRAMMING CONNECTION 24.3 Example of Serial Programming Connection (Power Supplied from the Programmer) Figure 24.3-1 is an example of a serial programming connection for internal vector modes (single-chip mode) when power is supplied from the programmer. The value 1 and 0 are input to mode pins MD2 and MD0 from TAUX3 and TMODE of the AF220/AF210/AF120/AF110 programmer. Serial reprogramming mode: MD2, MD1, MD0 = 110B. ■ Example of serial programming connection (power supplied from the programmer) Figure 24.3-1 Example of serial programming connection for MB90F352/C(S) internal vector modes (power supplied from the programmer) AF220/AF210/AF120/AF110 flash microcomputer programmer TAUX3 User system Connector DX10-28S or DX20-28S MB90F352/C(S) MD2 (19) 10 kΩ 10 kΩ MD1 10 kΩ TMODE MD0 X0 (12) X1 TAUX P00 (23) 10 kΩ /TICS (10) User 10 kΩ 10 kΩ /TRES RST (5) 10 kΩ User 0.1 µF or more TTXD TRXD TCK TVcc GND (13) (27) (6) SIN3 SOT3 SCK3 (2) (7, 8, 14,15, 21, 22 1, 28) P01 C User power supply Vcc Vss Pin 14 Pins 3, 4, 9, 11, 16, 17, 18, 20, 24, 25, and 26 are open. DX10-28S: Right-angle type DX20-28S: Straight type Pin 1 DX10-28S DX20-28S Pin 28 Pin 15 Connector (Hirose Electronics Ltd.) pin arrangement • Even if the SIN3, SOT3, and SCK3 pins are used for the user system, the control circuit shown in the figure below is required in the same way that it is for P00. The /TICS signal of the flash microcomputer programmer can be used to disconnect the user circuit during serial programming. • Connect the AF220/AF210/AF120/AF110 while the user power is off. 523 CHAPTER 24 EXAMPLES OF MB90F352/C(S) PROGRAMMING CONNECTION • When the programming power is supplied from the AF220/AF210/AF120/AF110, be careful not to short-circuit the user power supply. Figure 24.3-2 Connecting user circuitry (detail) AF220/AF210/ AF120/AF110 write control pin MB90F342/C(S) write control pin 10 kΩ AF220/AF210/ AF120/AF110 TICS pin User 524 CHAPTER 24 EXAMPLES OF MB90F352/C(S) PROGRAMMING CONNECTION 24.4 Example of Minimum Connection to the Flash Microcomputer Programmer (User Power Supply Used) Figure 24.4-1 is an example of the minimum connection to the flash microcomputer programmer when the user power supply is used. Serial reprogramming mode: MD2, MD1, MD0 = 110B. ■ Example of minimum connection to the flash microcomputer programmer (user power supply used) For a flash memory write, the MD2, MD1, MD0, and P00 pins and flash microcomputer programmer need not be connected if the pins are set as described below. Figure 24.4-1 Example of minimum connection to the flash microcomputer programmer (user power supply used) AF220/AF210/AF120/AF110 User system flash microcomputer programmer MB90F352/C(S) 1 for serial reprogramming 10 k Ω MD2 10 k Ω 10 k Ω 1 for serial reprogramming MD1 10 k Ω 10 k Ω MD0 0 for serial reprogramming 10 k Ω X0 X1 10k Ω 0 for serial reprogramming P00 10 k Ω User circuit P01 1 for serial reprogramming User circuit Connector DX10-28S or DX20-28S /TRES TTXD TRXD TCK TVcc (5) (13) (27) (6) (2) GND (7, 8, 14,15, 21, 22, 1, 28) 0.1 µF or more 10 k Ω RST SIN3 SOT3 SCK3 Vcc User power supply Pins 3, 4, 9, 10, 11, 12, 16, 17, 18, 19, 20, 23, 24, 25, and 26 are open. DX10-28S: Right-angle type DX20-28S: Straight type C Vss Pin 14 Pin 1 Pin 28 Pin 15 DX10-28S DX20-28S Connector (Hirose Electronics Ltd.) pin arrangement 525 CHAPTER 24 EXAMPLES OF MB90F352/C(S) PROGRAMMING CONNECTION • Even if the SIN3, SOT3, and SCK3 pins are used for the user system, the control circuit shown in the figure below is required. The /TICS signal of the flash microcomputer programmer can be used to disconnect the user circuit during serial programming. • Connect the AF220/AF210/AF120/AF110 while the user power is off. Figure 24.4-2 Connecting user circuitry (detail) AF220/AF210/ AF120/AF110 write control pin MB90F352/C(S) write control pin 10 kΩ AF220/AF210/ AF120/AF110 TICS pin User 526 CHAPTER 24 EXAMPLES OF MB90F352/C(S) PROGRAMMING CONNECTION 24.5 Example of Minimum Connection to the Flash Microcomputer Programmer (Power Supplied from the Programmer) Figure 24.5-1 is an example of the minimum connection to the flash microcomputer programmer when power is supplied from the Programmer. Serial reprogramming mode: MD2, MD1, MD0 = 110B. ■ Example of minimum connection to the flash microcomputer programmer (power supplied from the programmer) For a flash memory write, the MD2, MD1, MD0, and P00 pins and flash microcomputer programmer need not be connected if the pins are set as described below. Figure 24.5-1 Example of minimum connection to the flash microcomputer programmer (power supplied from the programmer) AF220/AF210/AF120/AF110 User system flash microcomputer programmer 1 for serial reprogramming 10k Ω MB90F352/C(S) MD2 1 for serial reprogramming 10 k Ω 10 k Ω 10k Ω 10k Ω MD1 MD0 0 for serial reprogramming 10 k Ω X0 X1 10k Ω 0 for serial reprogramming P00 10 k Ω User circuit P01 1 for serial reprogramming User circuit Connector DX10-28S or DX20-28S /TRES TTXD TRXD TCK (5) (13) (27) (6) (2) (3) (16) 0.1 µF or more 10 k Ω RST SIN3 SOT3 SCK3 Vcc TVcc GND (7,8, 14,15, 21, 22, 1, 28) Pins 4, 9, 10, 11, 12, 17, 18, 19, 20, 23, 24, 25, and 26 are open. DX10-28S: Right-angle type DX20-28S: Straight type C Vss Pin 14 Pin 1 Pin 28 Pin 15 DX10-28S DX20-28S Connector (Hirose Electronics Ltd.) pin arrangement 527 CHAPTER 24 EXAMPLES OF MB90F352/C(S) PROGRAMMING CONNECTION • Even if the SIN3, SOT3, and SCK3 pins are used for the user system, the control circuit shown in the figure below is required. The /TICS signal of the flash microcomputer programmer can be used to disconnect the user circuit during serial programming. • Connect the AF220/AF210/AF120/AF110 while the user power is off. • When the programming power is supplied from the AF220/AF210/AF120/AF110, be careful not to short-circuit the user power supply. Figure 24.5-2 Connecting user circuitry (detail) AF220/AF210/ AF120/AF110 write control pin MB90F352/C(S) write control pin 10 kΩ AF220/AF210/ AF120/AF110 TICS pin User 528 APPENDIX The appendixes provide I/O maps, instructions, and other information. APPENDIX A I/O Maps APPENDIX B Instructions APPENDIX C Timing Diagrams in Flash Memory Mode APPENDIX D List of Interrupt Vectors 529 APPENDIX APPENDIX A I/O Maps Table A-1 lists addresses to be assigned to the registers in the peripheral blocks. ■ I/O maps (00XX addresses) Table A-1 I/O map (1/7) Address 530 Register Abbreviation Access Peripheral Initial value 00H Port 0 data register PDR0 R/W Port 0 XXXXXXXX 01H Port 1 data register PDR1 R/W Port 1 XXXXXXXX 02H Port 2 data register PDR2 R/W Port 2 XXXXXXXX 03H Port 3 data register PDR3 R/W Port 3 XXXXXXXX 04H Port 4 data register PDR4 R/W Port 4 XXXXXXXX 05H Port 5 data register PDR5 R/W Port 5 XXXXXXXX 06H Port 6 data register PDR6 R/W Port 6 XXXXXXXX 07H Reserved area 08H Reserved area 09H Reserved area 0AH Reserved area 0BH Analog Input Enable Port 5 ADER5 R/W Port 5, A/D X1111111 0CH Analog Input Enable Port 6 ADER6 R/W Port 6, A/D 11111111 0DH Reserved area 0EH Input level select register0 ILSR0 R/W Port 0 to port 6 00000000 0FH Input level select register1 ILSR1 R/W Port 0 to port 3 00000000 10H Port 0 direction register DDR0 R/W Port 0 00000000 11H Port 1 direction register DDR1 R/W Port 1 00000000 12H Port 2 direction register DDR2 R/W Port 2 00000000 13H Port 3 direction register DDR3 R/W Port 3 00000000 14H Port 4 direction register DDR4 R/W Port 4 XX000000 15H Port 5 direction register DDR5 R/W Port 5 X0000000 16H Port 6 direction register DDR6 R/W Port 6 00000000 17H Reserved area APPENDIX A I/O Maps Table A-1 I/O map (2/7) Address Register Abbreviation Access Peripheral Initial value DDRA R/W UART2, UART3 X00XXXXX 18H Reserved area 19H Reserved area 1AH SIN input level select register 1BH Reserved 1CH Port 0 Pull-up control register PUCR0 R/W Port 0 00000000 1DH Port 1 Pull-up control register PUCR1 R/W Port 1 00000000 1EH Port 2 Pull-up control register PUCR2 R/W Port 2 XX000000 1FH Port 3 Pull-up control register PUCR3 W, R/W Port 3 00000000 20H Reserved area 21H Reserved area 22H Reserved area 23H Reserved area 24H Reserved area 25H Reserved area 26H Reserved area 27H Reserved area 28H Reserved area 29H Reserved area 2AH Reserved area 2BH Reserved area 2CH Reserved area 2DH Reserved area 2EH Reserved area 2FH Reserved area 30H Reserved area 31H Reserved area 32H Reserved area 33H Reserved area 34H Reserved area 35H Reserved area 531 APPENDIX Table A-1 I/O map (3/7) Address Register Abbreviation Access 36H Reserved area 37H Reserved area 38H PPG4 operation mode control register PPGC4 W,R/W 39H PPG5 operation mode control register PPGC5 W,R/W 3AH PPG4 and PPG5 clock select register PPG45 R/W 3BH Address Match Detection Control Status 1 PACSR1 R/W 3CH PPG6 operation mode control register PPGC6 W,R/W 3DH PPG7 operation mode control register PPGC7 W,R/W 3EH PPG6 and PPG7 clock select register PPG67 R/W 3FH Reserved 40H PPG8 operation mode control register PPGC8 W,R/W 41H PPG9 operation mode control register PPGC9 W,R/W 42H PPG8 and PPG9 clock select register PPG89 R/W 43H Reserved 44H PPGA operation mode control register PPGCA W,R/W 45H PPGB operation mode control register PPGCB W,R/W 46H PPGA and PPGB clock select register PPGAB R/W 47H Reserved 48H PPGC operation mode control register PPGCC W,R/W 49H PPGD operation mode control register PPGCD W,R/W 4AH PPGC and PPGD clock select register PPGCD R/W 4BH Reserved area 4CH PPGE operation mode control register PPGCE W,R/W 4DH PPGF operation mode control register PPGCF W,R/W 4EH PPGE and PPGF clock select register PPGEF R/W 4FH Reserved area 50H Input Capture Control Status 0/1 ICS01 R/W Peripheral 16-bit Programable Pulse Generator 4/5 Address Match Detection 1 16-bit Programable Pulse Generator 6/7 16-bit Programable Pulse Generator 8/9 16-bit Programable Pulse Generator A/B 16-bit Programable Pulse Generator C/D 16-bit Programable Pulse Generator E/F Initial value 0X000XX1 0X000001 000000X0 00000000 0X000XX1 0X000001 000000X0 0X000XX1 0X000001 000000X0 0X000XX1 0X000001 000000X0 0X000XX1 0X000001 000000X0 0X000XX1 0X000001 000000X0 00000000 Input Capture 0/1 532 51H Input Capture Edge 0/1 52H Reserved area ICE01 R/W,R XXX0X0XX APPENDIX A I/O Maps Table A-1 I/O map (4/7) Address Register 53H Reserved area 54H Input Capture Control Status 4/5 Abbreviation Access ICS45 R/W Peripheral Initial value 00000000 Input Capture 4/5 55H Input Capture Edge 4/5 ICE45 R 56H Input Capture Control Status 6/7 ICS67 R/W XXXXXXXX 00000000 Input Capture 6/7 57H Input Capture Edge 6/7 58H Reserved area 59H Reserved area 5AH Reserved area 5BH Reserved area 5CH Output Compare Control Status 4 ICE67 R/W,R OCS4 R/W XXX000XX 0000XX00 Output Compare 4/5 5DH Output Compare Control Status 5 OCS5 R/W 5EH Output Compare Control Status 6 OCS6 R/W 0XX00000 0000XX00 Output Compare 6/7 5FH Output Compare Control Status 7 60H Timer Control Status 0 OCS7 R/W TMCSR0 R/W 0XX00000 00000000 16-bit Reload Timer 0 61H Timer Control Status 0 TMCSR0 R/W 62H Timer Control Status 1 TMCSR1 R/W XXXX0000 00000000 16-bit Reload Timer 1 63H Timer Control Status 1 TMCSR1 R/W 64H Timer Control Status 2 TMCSR2 R/W XXXX0000 00000000 16-bit Reload Timer 2 65H Timer Control Status 2 TMCSR2 R/W 66H Timer Control Status 3 TMCSR3 R/W XXXX0000 00000000 16-bit Reload Timer 3 67H Timer Control Status 3 68H TMCSR3 R/W XXXX0000 A/D Control Status 0 ADCS0 R/W 000XXXX0 69H A/D Control Status 1 ADCS1 R/W 0000000X 6AH A/D Data 0 ADCR0 R 6BH A/D Data 1 ADCR1 R XXXXXX00 6CH ADC Setting 0 ADSR0 R/W 00000000 6D ADC Setting 1 ADSR1 R/W 00000000 6EH Reserved area 6FH ROM Mirror ROMM W 70 to 7FH Reserved area 00000000 A/D Converter ROM Mirror XXXXXXX1 533 APPENDIX Table A-1 I/O map (5/7) Address 80 to 8FH Register Abbreviation Access Peripheral Initial value Reserved for CAN Interface 1. Refer to section about CAN controller 90 to 9AH Reserved area 9BH DMA Descriptor Channel Select DCSR R/W 9CH DMA Status L DSRL R/W 9DH DMA Status H DSRH R/W 9EH Address Match Detection Control Status 0 PACSR0 R/W Address Match Detection 0 00000000 9FH Delayed Interrupt/release DIRR R/W Delayed Interrupt XXXXXXX0 A0H Low-power Mode Control LPMCR W,R/W Low Power Controller 00011000 A1H Clock Selection CKSCR R,R/W Low Power Controller 11111100 DMA 00000000 00000000 DMA 00000000 00000000 A2 to A3H Reserved area A4H DMA Stop Status DSSR R/W A5H Automatic ready function select reg. ARSR W A6H External address output control reg. HACR W A7H Bus control signal selection register ECSR W A8H Watchdog Control WDTC R,W Watchdog Timer XXXXX111 A9H Time Base Timer Control TBTC W,R/W Time Base Timer 1XX00100 AAH Watch Timer Control register WTC R,R/W Watch Timer 1X001000 ABH Reserved area ACH DMA Enable L DERL R/W 0011XX00 External Memory Access 00000000 0000000X 00000000 DMA 534 ADH DMA Enable H DERH R/W AEH Flash Control Status (Flash device only. Otherwise reserved) FMCS R,R/W AFH Reserved area 00000000 Flash Memory 000X0000 APPENDIX A I/O Maps Table A-1 I/O map (6/7) Address Register Abbreviation Access Peripheral Initial value B0H Interrupt control register 00 ICR00 W,R/W 00000111 B1H Interrupt control register 01 ICR01 W,R/W 00000111 B2H Interrupt control register 02 ICR02 W,R/W 00000111 B3H Interrupt control register 03 ICR03 W,R/W 00000111 B4H Interrupt control register 04 ICR04 W,R/W B5H Interrupt control register 05 ICR05 W,R/W 00000111 B6H Interrupt control register 06 ICR06 W,R/W 00000111 B7H Interrupt control register 07 ICR07 W,R/W 00000111 B8H Interrupt control register 08 ICR08 W,R/W 00000111 B9H Interrupt control register 09 ICR09 W,R/W 00000111 BAH Interrupt control register 10 ICR10 W,R/W 00000111 BBH Interrupt control register 11 ICR11 W,R/W 00000111 BCH Interrupt control register 12 ICR12 W,R/W BDH Interrupt control register 13 ICR13 W,R/W 00000111 BEH Interrupt control register 14 ICR14 W,R/W 00000111 BFH Interrupt control register 15 ICR15 W,R/W 00000111 Interrupt controller Interrupt controller 00000111 00000111 C0H to C9H Reserved area CAH External Interrupt Enable 1 ENIR1 R/W 00000000 CBH External Interrupt Request 1 EIRR1 R/W XXXXXXXX CCH External Interrupt Level 1 ELVR1 R/W CDH External Interrupt Level 1 ELVR1 R/W 00000000 CEH External Interrupt 1 Source Select EISSR R/W 00000000 CFH PLL/Subclock Control register PSCCR W External Interrupt 1 PLL 00000000 XXXX0000 535 APPENDIX Table A-1 I/O map (7/7) Address Register Abbreviation Access Peripheral Initial value D0H DMA Buffer Address Pointer L BAPL R/W XXXXXXXX D1H DMA Buffer Address Pointer M BAPM R/W XXXXXXXX D2H DMA Buffer Address Pointer H BAPH R/W D3H DMA Control D4H XXXXXXXX DMA DMACS R/W XXXXXXXX I/O Register Address Pointer L IOAL R/W XXXXXXXX D5H I/O Register Address Pointer H IOAH R/W XXXXXXXX D6H Data Counter L DCTL R/W XXXXXXXX D7H Data Counter H DCTH R/W XXXXXXXX D8H Serial Mode Register SMR2 W,R/W 00000000 D9H Serial Control Register SCR2 W,R/W 00000000 DAH Reception/Transmission Data Register RDR2/TDR2 R/W 00000000 DBH Serial Status Register SSR2 R,R/W 00001000 UART2 DCH Extended Communication Control Reg. ECCR2 R,W,R/W 000000XX DDH Extended Status/Control Register ESCR2 R/W 00000100 DEH Baud Rate Register 0 BGR20 R/W 00000000 DFH Baud Rate Register 1 BGR21 R/W 00000000 E0H to EFH Reserved area F0H to FFH External 536 APPENDIX A I/O Maps ■ I/O map (79XX - 7FXX addresses) Table A-2 I/O map (79XX - 7FXX addresses) (1/5) Address 7900H to 7907H Register Abbreviation Access Peripheral Initial value Reserved area 7908H Reload L PRLL4 R/W 7909H Reload H PRLH4 R/W 790AH Reload L PRLL5 R/W 790BH Reload H PRLH5 R/W XXXXXXXX 790CH Reload L PRLL6 R/W XXXXXXXX 790DH Reload H PRLH6 R/W 790EH Reload L PRLL7 R/W 790FH Reload H PRLH7 R/W XXXXXXXX 7910H Reload L PRLL8 R/W XXXXXXXX 7911H Reload H PRLH8 R/W 7912H Reload L PRLL9 R/W 7913H Reload H PRLH9 R/W XXXXXXXX 7914H Reload L PRLLA R/W XXXXXXXX 7915H Reload H PRLHA R/W 7916H Reload L PRLLB R/W 7917H Reload H PRLHB R/W 7918H Reload L PRLLC R/W 7919H Reload H PRLHC R/W 791AH Reload L PRLLD R/W 791BH Reload H PRLHD R/W 791CH Reload L PRLLE R/W 791DH Reload H PRLHE R/W 791EH Reload L PRLLF R/W 791FH Reload H PRLHF R/W XXXXXXXX 16-bit Programable Pulse Generator 4/5 16-bit Programable Pulse Generator 6/7 16-bit Programable Pulse Generator 8/9 16-bit Programable Pulse Generator A/B XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 16-bit Programable Pulse Generator C/D 16-bit Programable Pulse Generator C/D XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 16-bit Programable Pulse Generator E/F XXXXXXXX XXXXXXXX XXXXXXXX 537 APPENDIX Table A-2 I/O map (79XX - 7FXX addresses) (2/5) Address Register Abbreviation Access 7920H Input Capture 0 IPCP0 R 7921H Input Capture 0 IPCP0 R Peripheral Initial value XXXXXXXX XXXXXXXX Input Capture 0/1 7922H Input Capture 1 IPCP1 R XXXXXXXX 7923H Input Capture 1 IPCP1 R XXXXXXXX XXXXXXXX 7924H to 7927H Reserved area 7928H Input Capture 4 IPCP4 R 7929H Input Capture 4 IPCP4 R XXXXXXXX Input Capture 4/5 792AH Input Capture 5 IPCP5 R XXXXXXXX 792BH Input Capture 5 IPCP5 R XXXXXXXX 792CH Input Capture 6 IPCP6 R XXXXXXXX 792DH Input Capture 6 IPCP6 R XXXXXXXX Input Capture 6/7 792EH Input Capture 7 IPCP7 R XXXXXXXX 792FH Input Capture 7 IPCP7 R XXXXXXXX XXXXXXXX 7930H to 7937H Reserved area 7938H Output Compare 4 OCCP4 R/W 7939H Output Compare 4 OCCP4 R/W XXXXXXXX Output Compare 4/5 793AH Output Compare 5 OCCP5 R/W XXXXXXXX 793BH Output Compare 5 OCCP5 R/W XXXXXXXX 793CH Output Compare 6 OCCP6 R/W XXXXXXXX 793DH Output Compare 6 OCCP6 R/W XXXXXXXX Output Compare 6/7 793EH Output Compare 7 OCCP7 R/W XXXXXXXX 793FH Output Compare 7 OCCP7 R/W XXXXXXXX 7940H Timer Data 0 TCDT0 R/W 00000000 7941H Timer Data 0 TCDT0 R/W 00000000 I/O Timer 0 538 7942H Timer Control 0 TCCSL0 R/W 00000000 7943H Timer Control 0 TCCSH0 R/W 0XXXXXXX APPENDIX A I/O Maps Table A-2 I/O map (79XX - 7FXX addresses) (3/5) Address Register Abbreviation Access 7944H Timer Data 1 TCDT1 R/W 7945H Timer Data 1 TCDT1 R/W Peripheral Initial value 00000000 00000000 I/O Timer 1 7946H Timer Control 1 TCCSL1 R/W 00000000 7947H Timer Control 1 TCCSH1 R/W 0XXXXXXX TMR0/ TMRLR0 R/W Timer 0/Reload 0 7948H 7949H 794AH Timer 1/Reload 1 794BH 794CH Timer 2/Reload 2 794DH 794EH Timer 3/Reload 3 794FH TMR1/ TMRLR1 TMR2/ TMRLR2 R/W R/W R/W R/W R/W R/W TMR3/ TMRLR3 R/W 16-bit Reload Timer 0 16-bit Reload Timer 1 16-bit Reload Timer 2 16-bit Reload Timer 3 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 7950H Serial Mode Register SMR3 W,R/W 00000000 7951H Serial Control Register SCR3 W,R/W 00000000 7952H Reception/Transmission Data Register RDR3/TDR3 R/W 00000000 7953H Serial Status Register SSR3 R,R/W 00001000 7954H Extended Communication Control Reg. ECCR3 R,W,R/W 000000XX 7955H Extended Status/Control Register ESCR3 R/W 00000100 7956H Baud Rate Register 0 BGR30 R/W 00000000 7957H Baud Rate Register 1 BGR31 R/W 00000000 CDMR R/W 7958H to 796DH UART3 Reserved area 796EH CAN Direct Mode Register 796FH Reserved area CAN clock sync XXXXXXX0 539 APPENDIX Table A-2 I/O map (79XX - 7FXX addresses) (4/5) Address Abbreviation Access Peripheral Initial value 7970H I2C bus status register IBSR0 R 00000000 7971H I2C bus control register IBCR0 W,R/W 00000000 7972H I2C ten bit slave address register ITBAL0 R/W 00000000 ITBAH0 R/W 00000000 ITMKL0 R/W 7973H 7974H 7975H I2C ten bit address mask register ITMKH0 R/W 11111111 I2C Interface 0 00111111 7976H I2C seven bit slave address register ISBA0 R/W 00000000 7977H I2C seven bit address mask register ISMK0 R/W 01111111 7978H I2C data register IDAR0 R/W 00000000 ICCR0 R/W 7979H to 797AH 797BH 797CH to 79DFH Reserved area I2C clock control register I2C Interface 0 00011111 Reserved area 79E0H Program Address Detection 0 PADR0 R/W XXXXXXXX 79E1H Program Address Detection 0 PADR0 R/W XXXXXXXX 79E2H Program Address Detection 0 PADR0 R/W XXXXXXXX 79E3H Program Address Detection 1 PADR1 R/W XXXXXXXX 79E4H Program Address Detection 1 PADR1 R/W 79E5H Program Address Detection 1 PADR1 R/W XXXXXXXX 79E6H Program Address Detection 2 PADR2 R/W XXXXXXXX 79E7H Program Address Detection 2 PADR2 R/W XXXXXXXX 79E8H Program Address Detection 2 PADR2 R/W XXXXXXXX 79E9H to 79EFH 540 Register Reserved area Address Match Detection 0 XXXXXXXX APPENDIX A I/O Maps Table A-2 I/O map (79XX - 7FXX addresses) (5/5) Address Register Abbreviation Access 79F0H Program Address Detection 3 PADR3 R/W XXXXXXXX 79F1H Program Address Detection 3 PADR3 R/W XXXXXXXX 79F2H Program Address Detection 3 PADR3 R/W XXXXXXXX 79F3H Program Address Detection 4 PADR4 R/W XXXXXXXX 79F4H Program Address Detection 4 PADR4 R/W 79F5H Program Address Detection 4 PADR4 R/W XXXXXXXX 79F6H Program Address Detection 5 PADR5 R/W XXXXXXXX 79F7H Program Address Detection 5 PADR5 R/W XXXXXXXX 79F8H Program Address Detection 5 PADR5 R/W XXXXXXXX 79F9H to 7BFFH Reserved area 7C00H to 7CFFH Reserved for CAN Interface 1. Refer to section about CAN controller 7D00H to 7DFFH Reserved for CAN Interface 1. Refer to section about CAN controller 7E00H to 7FFFH Reserved area Peripheral Address Match Detection 1 Initial value XXXXXXXX Note: Any write access to reserved addresses in I/O map should not be performed. A read access to reserved address results in reading "X". ● Explanation of write and read R/W: Both read and write enabled R: Only read enabled W: Only write enabled ● Explanation of initial values 0: The initial value of this bit is "0". 1: The initial value of this bit is "1". X: The initial value of this bit is undefined. 541 APPENDIX APPENDIX B Instructions Appendix B describes the instructions used by the F2MC-16LX. B.1 Instruction Types B.2 Addressing B.3 Direct Addressing B.4 Indirect Addressing B.5 Execution Cycle Count B.6 Effective address field B.7 How to Read the Instruction List B.8 F2MC-16LX Instruction List B.9 Instruction Map 542 APPENDIX B Instructions B.1 Instruction Types The F2MC-16LX supports 351 types of instructions. Addressing is enabled by using an effective address field of each instruction or using the instruction code itself. ■ Instruction types The F2MC-16LX supports the following 351 types of instructions: • 41 transfer instructions (byte) • 38 transfer instructions (word or long word) • 42 addition/subtraction instructions (byte, word, or long word) • 12 increment/decrement instructions (byte, word, or long word) • 11 comparison instructions (byte, word, or long word) • 11 unsigned multiplication/division instructions (word or long word) • 11 signed multiplication/division instructions (word or long word) • 39 logic instructions (byte or word) • 6 logic instructions (long word) • 6 sign inversion instructions (byte or word) • 1 normalization instruction (long word) • 18 shift instructions (byte, word, or long word) • 50 branch instructions • 6 accumulator operation instructions (byte or word) • 28 other control instructions (byte, word, or long word) • 21 bit operation instructions • 10 string instructions 543 APPENDIX B.2 Addressing With the F2MC-16LX, the address format is determined by the instruction effective address field or the instruction code itself (implied). When the address format is determined by the instruction code itself, specify an address in accordance with the instruction code used. Some instructions permit the user to select several types of addressing. ■ Addressing The F2MC-16LX supports the following 23 types of addressing: 544 • Immediate (#imm) • Register direct • Direct branch address (addr16) • Physical direct branch address (addr24) • I/O direct (io) • Abbreviated direct address (dir) • Direct address (addr16) • I/O direct bit address (io:bp) • Abbreviated direct bit address (dir:bp) • Direct bit address (addr16:bp) • Vector address (#vct) • Register indirect (@RWj j = 0 to 3) • Register indirect with post increment (@RWj+ j = 0 to 3) • Register indirect with displacement (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3) • Long register indirect with displacement (@RLi + disp8 i = 0 to 3) • Program counter indirect with displacement (@PC + disp16) • Register indirect with base index (@RW0 + RW7, @RW1 + RW7) • Program counter relative branch address (rel) • Register list (rlst) • Accumulator indirect (@A) • Accumulator indirect branch address (@A) • Indirectly-specified branch address (@ear) • Indirectly-specified branch address (@eam) APPENDIX B Instructions ■ Effective address field Table B.2-1 lists the address formats specified by the effective address field. Table B.2-1 Effective address field Code Representation 00 R0 RW0 RL0 01 R1 RW1 (RL0) 02 R2 RW2 RL1 03 R3 RW3 (RL1) 04 R4 RW4 RL2 05 R5 RW5 (RL2) 06 R6 RW6 RL3 07 R7 RW7 (RL3) 08 @RW0 09 @RW1 Address format Register direct: Individual parts correspond to the byte, word, and long word types in order from the left. Default bank None DTB DTB Register indirect 0A @RW2 ADB 0B @RW3 SPB 0C @RW0+ DTB 0D @RW1+ DTB Register indirect with post increment 0E @RW2+ ADB 0F @RW3+ SPB 10 @RW0+disp8 DTB 11 @RW1+disp8 DTB Register indirect with 8-bit displacement 12 @RW2+disp8 ADB 13 @RW3+disp8 SPB 14 @RW4+disp8 DTB 15 @RW5+disp8 DTB Register indirect with 8-bit displacement 16 @RW6+disp8 ADB 17 @RW7+disp8 SPB 18 @RW0+disp16 DTB 19 @RW1+disp16 DTB Register indirect with 16-bit displacement 1A @RW2+disp16 ADB 1B @RW3+disp16 SPB 1C @RW0+RW7 1D @RW1+RW7 1E @PC+disp16 1F addr16 DTB Register indirect with index Register indirect with index PC indirect with 16-bit displacement Direct address DTB PCB DTB 545 APPENDIX B.3 Direct Addressing An operand value, register, or address is specified explicitly in direct addressing mode. ■ Direct addressing ● Immediate addressing (#imm) Specify an operand value explicitly (#imm4/ #imm8/ #imm16/ #imm32). Figure B.3-1 Example of immediate addressing (#imm) MOVW A, #01212H (This instruction stores the operand value in A.) Before execution A 2233 4455 After execution A 4 4 5 5 1 2 1 2 (Some instructions transfer AL to AH.) ● Register direct addressing Specify a register explicitly as an operand. Table B.3-1 lists the registers that can be specified. Figure B.3-2 shows an example of register direct addressing. Table B.3-1 Direct addressing registers General-purpose register Special-purpose register Byte R0, R1, R2, R3, R4, R5, R6, R7 Word RW0, RW1, RW2, RW3, RW4, R5W, RW6, RW7 Long word RL0, RL1, RL2, RL3 Accumulator A, AL Pointer SP * Bank PCB, DTB, USB, SSB, ADB Page DPR Control PS, CCR, RP, ILM *: One of the user stack pointer (USP) and system stack pointer (SSP) is selected and used depending on the value of the S flag bit in the condition code register (CCR). For branch instructions, the program counter (PC) is not specified in an instruction operand but is specified implicitly. 546 APPENDIX B Instructions Figure B.3-2 Example of register direct addressing MOV R0, A (This instruction transfers the eight low-order bits of A to the general-purpose register R0.) Before execution A 0716 2534 After execution A 0716 2564 Memory space R0 ?? Memory space R0 34 ● Direct branch addressing (addr16) Specify an offset explicitly for the branch destination address. The size of the offset is 16 bits, which indicates the branch destination in the logical address space. Direct branch addressing is used for an unconditional branch, subroutine call, or software interrupt instruction. Bits 23 to 16 of the address are specified by the program bank register (PCB). Figure B.3-3 Example of direct branch addressing (addr16) JMP 3B20H (This instruction causes an unconditional branch by direct branch addressing in a bank.) Before execution After execution PC 3 C 2 0 PC 3 B 2 0 PCB 4 F Memory space 4F3C22H 4F3C21H 4F3C20H 3B 20 62 4F3B20H Next instruction JMP 3B20H PCB 4 F 547 APPENDIX ● Physical direct branch addressing (addr24) Specify an offset explicitly for the branch destination address. The size of the offset is 24 bits. Physical direct branch addressing is used for unconditional branch, subroutine call, or software interrupt instruction. Figure B.3-4 Example of direct branch addressing (addr24) JMPP 333B20H (This instruction causes an unconditional branch by direct branch 24-bit addressing.) Before execution PC 3 C 2 0 PC 3 B 2 0 After execution PCB 4 F Memory space 4F3C23H 4F3C22H 4F3C21H 4F3C20H 33 3B 20 63 333B20H Next instruction JMPP 333B20H PCB 3 3 ● I/O direct addressing (io) Specify an 8-bit offset explicitly for the memory address in an operand. The I/O address space in the physical address space from 000000H to 0000FFH is accessed regardless of the data bank register (DTB) and direct page register (DPR). A bank select prefix for bank addressing is invalid if specified before an instruction using I/O direct addressing. Figure B.3-5 Example of I/O direct addressing (io) MOVW A, i:0C0H (This instruction reads data by I/O direct addressing and stores it in A.) Before execution A 0716 2534 Memory space 0000C1H 0000C0H After execution 548 A 2534 FFEE FF EE APPENDIX B Instructions ● Abbreviated direct addressing (dir) Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register (DTB). Figure B.3-6 Example of abbreviated direct addressing (dir) MOVW S;20H, A (This instruction writes the contents of the eight low-order bits of A in abbreviated direct addressing mode.) Before execution A 4455 66 After execution A DTB 7 7 4455 66 Memory space 1212 776620H 1212 DTB 7 7 ?? Memory space 12 776620H ● Direct addressing (addr16) Specify the 16 low-order bits of a memory address explicitly in an operand. Address bits 16 to 23 are specified by the data bank register (DTB). A prefix instruction for access space addressing is invalid for this mode of addressing. Figure B.3-7 Example of direct addressing (addr16) MOVW A, 3B20H (This instruction reads data by direct addressing and stores it in A.) Before execution A Memory space 2 0 2 0 A A B B DTB 5 5 After execution A AABB 0123 553B21H 553B20H 01 23 DTB 5 5 549 APPENDIX ● I/O direct bit addressing (io:bp) Specify bits in physical addresses 000000H to 0000FFH explicitly. Bit positions are indicated by ":bp", where the larger number indicates the most significant bit (MSB) and the lower number indicates the least significant bit (LSB). Figure B.3-8 Example of I/O direct bit addressing (io:bp) SETB I:0C1H:0 (This instruction sets bits by I/O direct bit addressing.) Memory space Before execution 0000C1H 00 After execution 0000C1H 01 ● Abbreviated direct bit addressing (dir:bp) Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register (DTB). Bit positions are indicated by ":bp", where the larger number indicates the most significant bit (MSB) and the lower number indicates the least significant bit (LSB). Figure B.3-9 Example of abbreviated direct bit addressing (dir:bp) SETB S:10H:0 (This instruction sets bits by abbreviated direct bit addressing.) Memory space Before execution DTB 5 5 DPR 6 6 556610H 00 Memory space After execution DTB 5 5 DPR 6 6 556610H 01 ● Direct bit addressing (addr16:bp) Specify arbitrary bits in 64 kilobytes explicitly. Address bits 16 to 23 are specified by the data bank register (DTB). Bit positions are indicated by ":bp", where the larger number indicates the most significant bit (MSB) and the lower number indicates the least significant bit (LSB). Figure B.3-10 Example of direct bit addressing (addr16:bp) SETB 2222H:0 (This instruction sets bits by direct bit addressing.) Memory space Before execution DTB 5 5 552222H 00 Memory space After execution 550 DTB 5 5 552222H 01 APPENDIX B Instructions ● Vector Addressing (#vct) Specify vector data in an operand to indicate the branch destination address. There are two sizes for vector numbers: 4 bits and 8 bits. Vector addressing is used for a subroutine call or software interrupt instruction. Figure B.3-11 Example of vector addressing (#vct) CALLV #15 (This instruction causes a branch to the address indicated by the interrupt vector specified in an operand.) Before execution PC PCB F F After execution PC Memory space 0000 FFFFE1H FFFFE0H D0 00 FFC000H EF D000 PCB F F CALLV #15 Table B.3-2 CALLV vector list Instruction Vector address L Vector address H CALLV #0 XXFFFEH XXFFFFH CALLV #1 XXFFFCH XXFFFDH CALLV #2 XXFFFAH XXFFFBH CALLV #3 XXFFF8H XXFFF9H CALLV #4 XXFFF6H XXFFF7H CALLV #5 XXFFF4H XXFFF5H CALLV #6 XXFFF2H XXFFF3H CALLV #7 XXFFF0H XXFFF1H CALLV #8 XXFFEEH XXFFEFH CALLV #9 XXFFECH XXFFEDH CALLV #10 XXFFEAH XXFFEBH CALLV #11 XXFFE8H XXFFE9H CALLV #12 XXFFE6H XXFFE7H CALLV #13 XXFFE4H XXFFE5H CALLV #14 XXFFE2H XXFFE3H CALLV #15 XXFFE0H XXFFE1H Note: A PCB register value is set in XX. Note: When the program bank register (PCB) is FFH, the vector area overlaps the vector area of INT #vct8 (#0 to #7). Use vector addressing carefully (see Table B.3-2). 551 APPENDIX B.4 Indirect Addressing In indirect addressing mode, an address is specified indirectly by the address data of an operand. ■ Indirect addressing ● Register indirect addressing (@RWj j = 0 to 3) Memory is accessed using the contents of general-purpose register RWj as an address. Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 is used, or additional data bank register (ADB) when RW2 is used. Figure B.4-1 Example of register indirect addressing (@RWj j = 0 to 3) MOVW A, @RW1 (This instruction reads data by register indirect addressing and stores it in A.) Before execution A 0716 2534 RW1 D 3 0 F DTB 7 8 After execution A Memory space 78D310H 78D30FH FF EE 2534 FFEE RW1 D 3 0 F DTB 7 8 ● Register indirect addressing with post increment (@RWj+ j = 0 to 3) Memory is accessed using the contents of general-purpose register RWj as an address. After operand operation, RWj is incremented by the operand size (1 for a byte, 2 for a word, or 4 for a long word). Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 is used, or additional data bank register (ADB) when RW2 is used. If the post increment results in the address of the register that specifies the increment, the incremented value is referenced after that. In this case, if the next instruction is a write instruction, priority is given to writing by an instruction and, therefore, the register that would be incremented becomes write data. 552 APPENDIX B Instructions Figure B.4-2 Example of register indirect addressing with post increment (@RWj+ j = 0 to 3) MOVW A, @RW1+ (This instruction reads data by register indirect addressing with post increment and stores it in A.) Before execution A 0716 2534 Memory space RW1 D 3 0 F DTB 7 8 After execution A 78D310H 78D30FH FF EE 2534 FFEE RW1 D 3 1 1 DTB 7 8 ● Register indirect addressing with offset (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3) Memory is accessed using the address obtained by adding an offset to the contents of general-purpose register RWj. Two types of offset, byte and word offsets, are used. They are added as signed numeric values. Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0, RW1, RW4, or RW5 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 or RW7 is used, or additional data bank register (ADB) when RW2 or RW6 is used. Figure B.4-3 Example of register indirect addressing with offset (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3) MOVW A, @RW1+10H (This instruction reads data by register indirect addressing with an offset and stores it in A.) Before execution A 0716 2534 Memory space RW1 D 3 0 F DTB 7 8 78D320H 78D31FH FF EE (+10H) After execution A 2534 FFEE RW1 D 3 0 F DTB 7 8 ● Long register indirect addressing with offset (@RLi + disp8 i = 0 to 3) Memory is accessed using the address that is the 24 low-order bits obtained by adding an offset to the contents of general-purpose register RLi. The offset is 8-bits long and is added as a signed numeric value. Figure B.4-4 Example of long register indirect addressing with offset (@RLi + disp8 i = 0 to 3) MOVW A, @RL2+25H (This instruction reads data by long register indirect addressing with an offset and stores it in A.) Before execution A RL2 0716 2534 F382 4B02 Memory space 824B28H 824B27H FF EE (+25H) After execution A 2534 FFEE RL2 F382 4B02 553 APPENDIX ● Program counter indirect addressing with offset (@PC + disp16) Memory is accessed using the address indicated by (instruction address + 4 + disp16). The offset is one word long. Address bits 16 to 23 are specified by the program bank register (PCB). Note that the operand address of each of the following instructions is not deemed to be (next instruction address + disp16): • DBNZ eam, rel • DWBNZ eam, rel • CBNE eam, #imm8, rel • CWBNE eam, #imm16, rel • MOV eam, #imm8 • MOVW eam, #imm16 Figure B.4-5 Example of program counter indirect addressing with offset (@PC + disp16) MOVW A, @PC+20H (This instruction reads data by program counter indirect addressing with a offset and stores it in A.) Before execution A 0716 2534 PCB C 5 PC 4 5 5 6 After execution A 2534 FFEE PCB C 5 PC 4 5 5 A Memory space C5457BH C5457AH FF EE C5455AH +20H C54559H +4 C54558H C54557H C54556H 00 20 9E 73 MOVW A, @PC+20H ● Register indirect addressing with base index (@RW0 + RW7, @RW1 + RW7) Memory is accessed using the address determined by adding RW0 or RW1 to the contents of generalpurpose register RW7. Address bits 16 to 23 are indicated by the data bank register (DTB). Figure B.4-6 Example of register indirect addressing with base index (@RW0 + RW7, @RW1 + RW7) MOVW A, @RW1+RW7 (This instruction reads data by register indirect addressing with a base index and stores it in A.) Before execution A 0716 RW1 D 3 0 F 2534 DTB 7 8 + RW7 0 1 0 1 After execution A 2534 FFEE RW1 D 3 0 F RW7 0 1 0 1 554 DTB 7 8 Memory space 78D411H 78D410H FF EE APPENDIX B Instructions ● Program counter relative branch addressing (rel) The address of the branch destination is a value determined by adding an 8-bit offset to the program counter (PC) value. If the result of addition exceeds 16 bits, bank register incrementing or decrementing is not performed and the excess part is ignored, and therefore the address is contained within a 64-kilobyte bank. This addressing is used for both conditional and unconditional branch instructions. Address bits 16 to 23 are indicated by the program bank register (PCB). Figure B.4-7 Example of program counter relative branch addressing (rel) BRA 10H (This instruction causes an unconditional relative branch.) Before execution PC After execution PC 3C20 3C32 Memory space PCB 4 F PCB 4 F 4F3C32H Next instruction 4F3C21H 4F3C20H 10 60 BRA 10H ● Register list (rlst) Specify a register to be pushed onto or popped from a stack. Figure B.4-8 Configuration of the register list MSB LSB RW7 RW6 RW5 RW4 RW3 RW2 RW1 RW0 A register is selected when the corresponding bit is 1 and deselected when the bit is 0. 555 APPENDIX Figure B.4-9 Example of register list (rlist) POPW RW0, RW4 (This instruction transfers memory data indicated by the SP to multiple word registers indicated by the register list.) SP 34FA SP RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7 RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7 SP 02 01 04 03 Memory space Memory space SP 34FEH 34FDH 34FCH 34FBH 34FAH 04 03 02 01 34FE 04 03 02 01 34FEH 34FDH 34FCH 34FBH 34FAH After execution Before execution ● Accumulator indirect addressing (@A) Memory is accessed using the address indicated by the contents of the low-order bytes (16 bits) of the accumulator (AL). Address bits 16 to 23 are specified by a mnemonic in the data bank register (DTB). Figure B.4-10 Example of accumulator indirect addressing (@A) MOVW A, @A (This instruction reads data by accumulator indirect addressing and stores it in A.) Before execution A 0716 2534 DTB B B After execution A 0716 FFEE DTB B B 556 Memory space BB2535H BB2534H FF EE APPENDIX B Instructions ● Accumulator indirect branch addressing (@A) The address of the branch destination is the content (16 bits) of the low-order bytes (AL) of the accumulator. It indicates the branch destination in the bank address space. Address bits 16 to 23 are specified by the program bank register (PCB). For the Jump Context (JCTX) instruction, however, address bits 16 to 23 are specified by the data bank register (DTB). This addressing is used for unconditional branch instructions. Figure B.4-11 Example of accumulator indirect branch addressing (@A) JMP @A (This instruction causes an unconditional branch by accumulator indirect branch addressing.) Before execution PC 3C20 PCB 4 F A 6677 3B20 PC 3B20 PCB 4 F Memory space 4F3C20H 4F3B20H After execution A 61 JMP @A Next instruction 6677 3B20 ● Indirect specification branch addressing (@ear) The address of the branch destination is the word data at the address indicated by ear. Figure B.4-12 Example of indirect specification branch addressing (@ear) JMP @@RW0 (This instruction causes an unconditional branch by register indirect addressing.) Before execution 3C20 PCB 4 F PW0 7 F 4 8 DTB 2 1 PC Memory space 4F3C21H 4F3C20H 4F3B20H After execution 3B20 PCB 4 F PW0 7 F 4 8 DTB 2 1 PC 217F49H 217F48H 08 73 JMP @@RW0 Next instruction 3B 20 557 APPENDIX ● Indirect specification branch addressing (@eam) The address of the branch destination is the word data at the address indicated by eam. Figure B.4-13 Example of indirect specification branch addressing (@eam) JMP @RW0 (This instruction causes an unconditional branch by register indirect addressing.) Before execution PC 3C20 PCB 4 F 4F3C21H 4F3C20H PW0 3 B 2 0 After execution PC 3B20 PW0 3 B 2 0 558 Memory space PCB 4 F 4F3B20H 00 73 JMP @RW0 Next instruction APPENDIX B Instructions B.5 Execution Cycle Count The number of cycles required for instruction execution (execution cycle count) is obtained by adding the number of cycles required for each instruction, "correction value" determined by the condition, and the number of cycles for instruction fetch. ■ Execution cycle count The number of cycles required for instruction execution (execution cycle count) is obtained by adding the number of cycles required for each instruction, "correction value" determined by the condition, and the number of cycles for instruction fetch. In the mode of fetching an instruction from memory such as internal ROM connected to a 16-bit bus, the program fetches the instruction being executed in word increments. Therefore, intervening in data access increases the execution cycle count. Similarly, in the mode of fetching an instruction from memory connected to an 8-bit external bus, the program fetches every byte of an instruction being executed. Therefore, intervening in data access increases the execution cycle count. In CPU intermittent operation mode, access to a general-purpose register, internal ROM, internal RAM, internal I/O, or external data bus causes the clock to the CPU to halt for the cycle count specified by the CG0 and CG1 bits of the low power consumption mode control register. Therefore, for the cycle count required for instruction execution in CPU intermittent operation mode, add the "access count x cycle count for the halt" as a correction value to the normal execution count. 559 APPENDIX ■ Calculating the execution cycle count Table B.5-1 lists execution cycle counts and Table B.5-2 and Table B.5-3 summarize correction value data. Table B.5-1 Execution cycle counts in each addressing mode (a) * Code Operand 00 | 07 Ri Rwi RLi 08 | 0B Register access count in each addressing mode See the instruction list. See the instruction list. @RWj 2 1 0C | 0F @RWj+ 4 2 10 | 17 @RWi+disp8 2 1 18 | 1B @RWi+disp16 2 1 1C 1D 1E 1F @RW0+RW7 @RW1+RW7 @PC+disp16 addr16 4 4 2 1 2 2 0 0 *: (a) is used for 560 Execution cycle count in each addressing mode (cycle count) and B (correction value) in "B.8 F2MC-16LX Instruction List". APPENDIX B Instructions Table B.5-2 Cycle count correction values for counting execution cycles (b) byte * Operand (c) word * (d) long * Cycle count Access count Cycle count Access count Cycle count Access count Internal register +0 1 +0 1 +0 2 Internal memory Even address +0 1 +0 1 +0 2 Internal memory Odd address +0 1 +2 2 +4 4 External data bus 16-bit even address +1 1 +1 1 +2 2 External data bus 16-bit odd address +1 1 +4 2 +8 4 External data bus 8-bits +1 1 +4 2 +8 4 *: (b), (c), and (d) are used for Instruction List". (cycle count) and B (correction value) in "B.8 F2MC-16LX Note: When an external data bus is used, the cycle counts during which an instruction is made to wait by ready input or automatic ready must also be added. Table B.5-3 Cycle count correction values for counting instruction fetch cycles Instruction Byte boundary Word boundary Internal memory - +2 External data bus 16-bits - +3 External data bus 8-bits +3 - Note: • When an external data bus is used, the cycle counts during which an instruction is made to wait by ready input or automatic ready must also be added. • Actually, instruction execution is not delayed by every instruction fetch. Therefore, use the correction values to calculate the worst case. 561 APPENDIX B.6 Effective address field Table B.6-1 shows the effective address field. ■ Effective Address Field Table B.6-1 Effective address field Code Representation Address format Byte count of extended address part * Register direct: Individual parts correspond to the byte, word, and long word types in order from the left. - Register indirect 0 Register indirect with post increment 0 Register indirect with 8-bit displacement 1 Register indirect with 16-bit displacement 2 00 01 R0 R1 RW0 RW1 RL0 (RL0) 02 03 R2 R3 RW2 RW3 RL1 (RL1) 04 05 R4 R5 RW4 RW5 RL2 (RL2) 06 07 R6 R7 RW6 RW7 RL3 (RL3) 08 09 @RW0 @RW1 0A 0B @RW2 @RW3 0C 0D @RW0+ @RW1+ 0E 0F @RW2+ @RW3+ 10 11 @RW0+disp8 @RW1+disp8 12 13 @RW2+disp8 @RW3+disp8 14 15 @RW4+disp8 @RW5+disp8 16 17 @RW6+disp8 @RW7+disp8 18 19 @RW0+disp16 @RW1+disp16 1A 1B @RW2+disp16 @RW3+disp16 1C 1D @RW0+RW7 @RW1+RW7 Register indirect with index Register indirect with index 0 0 1E 1F @PC+disp16 addr16 PC indirect with 16-bit displacement Direct address 2 2 *: Each byte count of the extended address part applies to + in the # (byte count) column in "B.8 F2MC-16LX Instruction List". 562 APPENDIX B Instructions B.7 How to Read the Instruction List Table B.7-1 describes the items used in the F2MC-16LX Instruction List, and Table B.7-2 describes the symbols used in the same list. ■ Description of instruction presentation items and symbols Table B.7-1 Description of items in the instruction list Item Mnemonic # Description Uppercase, symbol: Represented as is in the assembler. Lowercase: Rewritten in the assembler. Number of following lowercase: Indicates bit length in the instruction. Indicates the number of bytes. Indicates the number of cycles. See Table B.2-1 for the alphabetical letters in items. RG B Operation Indicates the number of times a register access is performed during instruction execution. The number is used to calculate the correction value for CPU intermittent operation. Indicates the correction value used to calculate the actual number of cycles during instruction execution. The actual number of cycles during instruction execution can be determined by adding the value in the column to this value. Indicates the instruction operation. LH Indicates the special operation for bits 15 to 08 of the accumulator. Z: Transfers 0. X: Transfers after sign extension. -: No transfer AH Indicates the special operation for the 16 high-order bits of the accumulator. *: Transfers from AL to AH. -: No transfer Z: Transfers 00 to AH. X: Transfers 00H or FFH to AH after AL sign extension. 563 APPENDIX Table B.7-1 Description of items in the instruction list (Continued) Item Description I Each indicates the state of each flag: I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero), V (overflow), C (carry). *: Changes upon instruction execution. -: No change Z: Set upon instruction execution. X: Reset upon instruction execution. S T N Z V C RMW Indicates whether the instruction is a Read Modify Write instruction (reading data from memory by the I instruction and writing the result to memory). *: Read Modify Write instruction -: Not Read Modify Write instruction Note: Cannot be used for an address that has different meanings between read and write operations. Table B.7-2 Explanation on symbols in the instruction List Symbol A 564 Explanation The bit length used varies depending on the 32-bit accumulator instruction. Byte: Low-order 8 bits of byte AL Word: 16 bits of word AL Long word: 32 bits of AL and AH AH 16 high-order bits of A AL 16 low-order bits of A SP Stack pointer (USP or SSP) PC Program counter PCB Program bank register DTB Data bank register ADB Additional data bank register SSB System stack bank register USB User stack bank register SPB Current stack bank register (SSB or USB) DPR Direct page register brg1 DTB, ADB, SSB, USB, DPR, PCB, SPB brg2 DTB, ADB, SSB, USB, DPR, SPB APPENDIX B Instructions Table B.7-2 Explanation on symbols in the instruction List (Continued) Symbol Ri Explanation R0, R1, R2, R3, R4, R5, R6, R7 RWi RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7 RWj RW0, RW1, RW2, RW3 RLi RL0, RL1, RL2, RL3 dir Abbreviated direct addressing addr16 Direct addressing addr24 Physical direct addressing ad24 0-15 Bits 0 to 15 of addr24 ad24 16-23 Bits 16 to 23 of addr24 io I/O area (000000H to 0000FFH) #imm4 4-bit immediate data #imm8 8-bit immediate data #imm16 16-bit immediate data #imm32 32-bit immediate data ext (imm8) 16-bit data obtained by sign extension of 8-bit immediate data disp8 8-bit displacement disp16 16-bit displacement bp Bit offset vct4 Vector number (0 to 15) vct8 Vector number (0 to 255) ( )b Bit address rel PC relative branch ear Effective addressing (code 00 to 07) eam Effective addressing (code 08 to 1F) rlst Register list 565 APPENDIX B.8 F2MC-16LX Instruction List Table B.8-1 to Table B.8-18 list the instructions used by the F2MC-16LX. ■ F2MC-16LX instruction list Table B.8-1 41 Transfer instructions (byte) Mnemonic # MOV A,dir MOV A,addr16 MOV A,Ri MOV A,ear MOV A,eam MOV A,io MOV A,#imm8 MOV A,@A MOV A,@RLi+disp8 MOVN A,#imm4 MOVX A,dir MOVX A,addr16 MOVX A,Ri MOVX A,ear MOVX A,eam MOVX A,io MOVX A,#imm8 MOVX A,@A MOVX A,@RWi+disp8 MOVX A,@RLi+disp8 MOV dir,A MOV addr16,A MOV Ri,A MOV ear,A MOV eam,A MOV io,A MOV @RLi+disp8,A MOV Ri,ear MOV Ri,eam MOV ear,Ri MOV eam,Ri MOV Ri,#imm8 MOV io,#imm8 MOV dir,#imm8 MOV ear,#imm8 MOV eam,#imm8 MOV @AL,AH / MOV @A,T XCH A,ear XCH A,eam XCH Ri,ear XCH Ri,eam 2 3 1 2 2+ 2 2 2 3 1 2 3 2 2 2+ 2 2 2 2 3 2 3 1 2 2+ 2 3 2 2+ 2 2+ 2 3 3 3 3+ 2 2 2+ 2 2+ RG 3 4 2 2 3 + (a) 3 2 3 10 1 3 4 2 2 3 + (a) 3 2 3 5 10 3 4 2 2 3 + (a) 3 10 3 4 + (a) 4 5 + (a) 2 5 5 2 4 + (a) 3 4 5 + (a) 7 9 + (a) 0 0 1 1 0 0 0 0 2 0 0 0 1 1 0 0 0 0 1 2 0 0 1 1 0 0 2 2 1 2 1 1 0 0 1 0 0 2 0 4 2 B (b) (b) 0 0 (b) (b) 0 (b) (b) 0 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) 0 0 (b) (b) (b) 0 (b) 0 (b) 0 (b) (b) 0 (b) (b) 0 2 x (b) 0 2 x (b) Operation byte (A) <-- (dir) byte (A) <-- (addr16) byte (A) <-- (Ri) byte (A) <-- (ear) byte (A) <-- (eam) byte (A) <-- (io) byte (A) <-- imm8 byte (A) <-- ((A)) byte (A) <-- ((RLi)+disp8) byte (A) <-- imm4 byte (A) <-- (dir) byte (A) <-- (addr16) byte (A) <-- (Ri) byte (A) <-- (ear) byte (A) <-- (eam) byte (A) <-- (io) byte (A) <-- imm8 byte (A) <-- ((A)) byte (A) <-- ((RWi)+disp8) byte (A) <-- ((RLi)+disp8 byte (dir) <-- (A) byte (addr16) <-- (A) byte (Ri) <-- (A) byte (ear) <-- (A) byte (eam) <-- (A) byte (io) <-- (A) byte ((RLi)+disp8) <-- (A) byte (Ri) <-- (ear) byte (Ri) <-- (eam) byte (ear) <-- (Ri) byte (eam) <-- (Ri) byte (Ri) <-- imm8 byte (io) <-- imm8 byte (dir) <-- imm8 byte (ear) <-- imm8 byte (eam) <-- imm8 byte ((A)) <-- (AH) byte (A) <--> (ear) byte (A) <--> (eam) byte (Ri) <--> (ear) byte (Ri) <--> (eam) L H A H I S T N Z V C R M W Z Z Z Z Z Z Z Z Z Z X X X X X X X X X X Z Z - * * * * * * * * * * * * * * * * * * - - - * * * * * * * * * R - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - * * * * * * * * * * * * * * * * * * * * * * * * - - - - Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. 566 APPENDIX B Instructions Table B.8-2 38 Transfer instructions (byte) Mnemonic # MOVW A,dir MOVW A,addr16 MOVW A,SP MOVW A,RWi MOVW A,ear MOVW A,eam MOVW A,io MOVW A,@A MOVW A,#imm16 MOVW A,@RWi+disp8 MOVW A,@RLi+disp8 MOVW dir,A MOVW addr16,A MOVW SP,A MOVW RWi,A MOVW ear,A MOVW eam,A MOVW io,A MOVW @RWi+disp8,A MOVW @RLi+disp8,A MOVW RWi,ear MOVW MOVW ear,Rwi MOVW eam,Rwi MOVW RWi,#imm16 MOVW io,#imm16 MOVW ear,#imm16 MOVW eam,#imm16 MOVW @AL,AH / MOVW @A,T XCHW A,ear XCHW A,eam XCHW RWi, ear XCHW RWi, eam MOVL A,ear MOVL A,eam MOVL A,#imm32 MOVL ear,A MOVL eam,A 2 3 3 1 2 2+ 2 2 3 2 3 2 3 1 1 2 2+ 2 2 3 2 2+ 2 2+ 3 4 4 4+ 2 2 2+ 2 2+ 2 2+ 5 2 2+ RG 3 4 1 2 2 3 + (a) 3 3 2 5 10 3 4 1 2 2 3 + (a) 3 5 10 3 4 + (a) 4 5 + (a) 2 5 2 4 + (a) 3 4 5 + (a) 7 9 + (a) 4 5 + (a) 3 4 5 + (a) 0 0 0 1 1 0 0 0 2 1 2 0 0 0 1 1 0 0 1 2 2 1 2 1 1 0 1 0 0 2 0 4 2 2 0 0 2 0 B (c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) (c) (c) 0 0 0 (c) (c) (c) (c) 0 (c) 0 (c) 0 (c) 0 (c) (c) 0 2 x (c) 0 2 x (c) 0 (d) 0 0 (d) Operation word (A) <-- (dir) word (A) <-- (addr16) word (A) <-- (SP) word (A) <-- (RWi) word (A) <-- (ear) word (A) <-- (eam) word (A) <-- (io) word (A) <-- ((A)) word (A) <-- imm16 word (A) <-- ((RWi)+disp8) word (A) <-- ((RLi)+disp8) word (dir) <-- (A) word (addr16) <-- (A) word (SP) <-- (A) word (RWi) <-- (A) word (ear) <-- (A) word (eam) <-- (A) word (io) <-- (A) word ((RWi)+disp8) <-- (A) word ((RLi)+disp8) <-- (A) word (RWi) <-- (ear) word (RWi) <-- (eam) word (ear) <-- (RWi) word (eam) <-- (RWi) word (RWi) <-- imm16 word (io) <-- imm16 word (ear) <-- imm16 word (eam) <-- imm16 word ((A)) <-- (AH) word (A) <--> (ear) word (A) <-- >(eam) word (RWi) <--> (ear) word (RWi) <--> (eam) long (A) <-- (ear) long (A) <-- (eam) long (A) <-- imm32 long (ear1) <-- (A) long(eam1) <-- (A) L H A H I S T N Z V C R M W - * * * * * * * * * * - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - - Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. 567 APPENDIX Table B.8-3 42 Addition/subtraction instructions (byte, word, long word) Mnemonic # RG B ADD ADD ADD ADD ADD ADD ADDC ADDC ADDC ADDDC A,#imm8 A,dir A,ear A,eam ear,A eam,A A A,ear A,eam A 2 2 2 2+ 2 2+ 1 2 2+ 1 2 5 3 4 + (a) 3 5 + (a) 2 3 4 + (a) 3 0 0 1 0 2 0 0 1 0 0 0 (b) 0 (b) 0 2 x (b) 0 0 (b) 0 SUB SUB SUB SUB SUB SUB SUBC SUBC SUBC SUBDC A,#imm8 A,dir A,ear A,eam ear,A eam,A A A,ear A,eam A 2 2 2 2+ 2 2+ 1 2 2+ 1 2 5 3 4 + (a) 3 5 + (a) 2 3 4 + (a) 3 0 0 1 0 2 0 0 1 0 0 0 (b) 0 (b) 0 2 x (b) 0 0 (b) 0 ADDW ADDW ADDW ADDW ADDW ADDW ADDCW ADDCW SUBW SUBW SUBW SUBW SUBW SUBW SUBCW SUBCW ADDL ADDL ADDL SUBL SUBL SUBL A A,ear A,eam A,#imm16 ear,A eam,A A,ear A,eam A A,ear A,eam A,#imm16 ear,A eam,A A,ear A,eam A,ear A,eam A,#imm32 A,ear A,eam A,#imm32 1 2 2+ 3 2 2+ 2 2+ 1 2 2+ 3 2 2+ 2 2+ 2 2+ 5 2 2+ 5 2 3 4+(a) 2 3 5+(a) 3 4+(a) 2 3 4+(a) 2 3 5+(a) 3 4+(a) 6 7+(a) 4 6 7+(a) 4 0 1 0 0 2 0 1 0 0 1 0 0 2 0 1 0 2 0 0 2 0 0 0 0 (c) 0 0 2 x (c) 0 (c) 0 0 (c) 0 0 2 x (c) 0 (c) 0 (d) 0 0 (d) 0 Operation byte (A) <-- (A) + imm8 byte (A) <-- (A) + (dir) byte (A) <-- (A) + (ear) byte (A) <-- (A) + (eam) byte (ear) <-- (ear) + (A) byte (eam) <-- (eam) + (A) byte (A) <-- (AH) + (AL) + (C) byte (A) <-- (A) + (ear)+ (C) byte (A) <-- (A) + (eam)+ (C) byte (A) <-- (AH) + (AL) + (C) (decimal) byte (A) <-- (A) - imm8 byte (A) <-- (A) - (dir) byte (A) <-- (A) - (ear) byte (A) <-- (A) - (eam) byte (ear) <-- (ear) - (A) byte (eam) <-- (eam) - (A) byte (A) <-- (AH) - (AL) - (C) byte (A) <-- (A) - (ear) - (C) byte (A) <-- (A) - (eam) - (C) byte (A) <-- (AH) - (AL) - (C) (decimal) word (A) <-- (AH) + (AL) word (A) <-- (A) + (ear) word (A) <-- (A) + (eam) word (A) <-- (A) + imm16 word (ear) <-- (ear) + (A) word (eam) <-- (eam) + (A) word (A) <-- (A) + (ear) + (C) word (A) <-- (A) + (eam) + (C) word (A) <-- (AH) - (AL) word (A) <-- (A) - (ear) word (A) <-- (A) - (eam) word (A) <-- (A) - imm16 word (ear) <-- (ear) - (A) word (eam) <-- (eam) - (A) word (A) <-- (A) - (ear) - (C) word (A) <-- (A) - (eam) - (C) long (A) <-- (A) + (ear) long (A) <-- (A) + (eam) long (A) <-- (A) + imm32 long (A) <-- (A) - (ear) long (A) <-- (A) - (eam) long (A) <-- (A) - imm32 L H A H I S T N Z V C R M W Z Z Z Z Z Z Z Z Z - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - Z Z Z Z Z Z Z Z - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. 568 APPENDIX B Instructions Table B.8-4 12 Increment/decrement instructions (byte, word, long word) Mnemonic # RG B Operation L H A H I S T N Z V C R M W INC ear 2 3 2 0 byte (ear) <-- (ear) + 1 - - - - - * * * - - INC eam 2+ 5+(a) 0 2 x (b) byte (eam) <-- (eam) + 1 - - - - - * * * - * DEC ear 2 3 2 0 byte (ear) <-- (ear) - 1 - - - - - * * * - - DEC eam 2+ 5+(a) 0 2 x (b) byte (eam) <-- (eam) - 1 - - - - - * * * - * INCW ear 2 3 2 0 word (ear) <-- (ear) + 1 - - - - - * * * - - INCW eam 2+ 5+(a) 0 2 x (c) word (eam) <-- (eam) + 1 - - - - - * * * - * DECW ear 2 3 2 0 word (ear) <-- (ear) - 1 - - - - - * * * - - DECW eam 2+ 5+(a) 0 2 x (c) word (eam) <-- (eam) - 1 - - - - - * * * - * INCL ear 2 7 4 0 long (ear) <-- (ear) + 1 - - - - - * * * - - INCL eam 2+ 9+(a) 0 2 x (d) long (eam) <-- (eam) + 1 - - - - - * * * - * DECL ear 2 7 4 0 long (ear) <-- (ear) - 1 - - - - - * * * - - DECL eam 2+ 9+(a) 0 2 x (d) long (eam) <-- (eam) - 1 - - - - - * * * - * Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. Table B.8-5 11 Compare instructions (byte, word, long word) Mnemonic # RG B Operation L H A H I S T N Z V C R M W CMP A 1 1 0 0 byte (AH) - (AL) - - - - - * * * * - CMP A,ear 2 2 1 0 byte (A) - (ear) - - - - - * * * * - CMP A,eam 2+ 3+(a) 0 (b) byte (A) - (eam) - - - - - * * * * - CMP A,#imm8 2 2 0 0 byte (A) - imm8 - - - - - * * * * - CMPW A 1 1 0 0 word (AH) - (AL) - - - - - * * * * - CMPW A,ear 2 2 1 0 word (A) - (ear) - - - - - * * * * - CMPW A,eam 2+ 3+(a) 0 (c) word (A) - (eam) - - - - - * * * * - CMPW A,#imm16 3 2 0 0 word (A) - imm16 - - - - - * * * * - CMPL A,ear 2 6 2 0 long (A) - (ear) - - - - - * * * * - CMPL A,eam 2+ 7+(a) 0 (d) long (A) - (eam) - - - - - * * * * - CMPL A,#imm32 5 3 0 0 long (A) - imm32 - - - - - * * * * - Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. 569 APPENDIX Table B.8-6 11 Unsigned multiplication/division instructions (word, long word) Mnemonic # RG B Operation L H A H I S T N Z V C R M W DIVU A 1 *1 0 0 word (AH) / byte (AL) quotient --> byte (AL) remainder --> byte (AH) - - - - - - - * * - DIVU A,ear 2 *2 1 0 word (A) / byte (ear) quotient --> byte (A) remainder --> byte (ear) - - - - - - - * * - DIVU A,eam 2+ *3 0 *6 word (A) / byte (eam) quotient --> byte (A) remainder --> byte (eam) - - - - - - - * * - DIVUW A,ear 2 *4 1 0 long (A) / word (ear) quotient --> word (A) remainder --> word (ear) - - - - - - - * * - DIVUW A,eam 2+ *5 0 *7 long (A) / word (eam) quotient --> word (A) remainder --> word (eam) - - - - - - - * * - MULL A 1 *8 0 0 byte (AH) * byte (AL) --> word (A) - - - - - - - - - - MULL A,ear 2 *9 1 0 byte (A) * byte (ear) --> word (A) - - - - - - - - - - MULL A,eam 2+ *10 0 (b) byte (A) * byte (eam) --> word (A) - - - - - - - - - - MULEY A 1 *11 0 0 word (AH) * word (AL) --> Long (A) - - - - - - - - - - MULEY A,ear 2 *12 1 0 word (A) * word (ear) --> Long (A) - - - - - - - - - - MULEY A,eam 2+ *13 0 (c) word (A) * word (eam) --> Long (A) - - - - - - - - - - *1: 3: Division by 0 7: Overflow 15: Normal *2: 4: Division by 0 8: Overflow 16: Normal *3: 6+(a): Division by 0 9+(a): Overflow 19+(a): Normal *4: 4: Division by 0 7: Overflow 22: Normal *5: 6+(a): Division by 0 8+(a): Overflow 26+(a): Normal *6: (b): Division by 0 or overflow 2 x (b): Normal *7: (c): Division by 0 or overflow 2 x (c): Normal *8: 3: Byte (AH) is 0. 7: Byte (AH) is not 0. *9: 4: Byte (ear) is 0. 8: Byte (ear) is not 0. *10: 5+(a): Byte (eam) is 0, 9+(a): Byte (eam) is not 0. *11: 3: Word (AH) is 0. 11: Word (AH) is not 0. *12: 4: Word (ear) is 0. 12: Word (ear) is not 0. *13: 5+(a): Word (eam) is 0. 13+(a): Word (eam) is not 0. Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. 570 APPENDIX B Instructions Table B.8-7 11 Signed multiplication/division instructions (word, long word) Mnemonic # RG B Operation L H A H I S T N Z V C R M W DIV A 2 *1 0 0 word (AH) / byte (AL) quotient --> byte (AL) remainder --> byte (AH) Z - - - - - - * * - DIV A,ear 2 *2 1 0 word (A) / byte (ear) quotient --> byte (A) remainder --> byte (ear) Z - - - - - - * * - DIV A,eam 2+ *3 0 *6 word (A) / byte (eam) quotient --> byte (A) remainder --> byte (eam) Z - - - - - - * * - DIVW A,ear 2 *4 1 0 long (A) / word (ear) quotient --> word (A) remainder --> word (ear) - - - - - - - * * - DIVW A,eam 2+ *5 0 *7 long (A) / word (eam) quotient --> word (A) remainder --> word (eam) - - - - - - - * * - MUL A 2 *8 0 0 byte (AH) * byte (AL) --> word (A) - - - - - - - - - - MUL A,ear 2 *9 1 0 byte (A) * byte (ear) --> word (A) - - - - - - - - - - MUL A,eam 2+ *10 0 (b) byte (A) * byte (eam) --> word (A) - - - - - - - - - - MULW A 2 *11 0 0 word (AH) * word (AL) --> Long (A) - - - - - - - - - - MULW A,ear 2 *12 1 0 word (A) * word (ear) --> Long (A) - - - - - - - - - - MULW A,eam 2+ *13 0 (c) word (A) * word (eam) --> Long (A) - - - - - - - - - - *1: *2: *3: *4: 3: Division by 0, 8 or 18: Overflow, 18: Normal 4: Division by 0, 11 or 22: Overflow, 23: Normal 5+(a): Division by 0, 12+(a) or 23+(a): Overflow, 24+(a): Normal When dividend is positive; 4: Division by 0, 12 or 30: Overflow, 31: Normal When dividend is negative; 4: Division by 0, 12 or 31: Overflow, 32: Normal *5: When dividend is positive; 5+(a): Division by 0, 12+(a) or 31+(a): Overflow, 32+(a): Normal When dividend is negative; 5+(a): Division by 0, 12+(a) or 32+(a): Overflow, 33+(a): Normal *6: (b): Division by 0 or overflow, 2 x (b): Normal *7: (c): Division by 0 or overflow, 2 x (c): Normal *8: 3: Byte (AH) is 0, 12: result is positive, 13: result is negative *9: 4: Byte (ear) is 0, 13: result is positive, 14: result is negative *10: 5+(a): Byte (eam) is 0, 14+(a): result is positive, 15+(a): result is negative *11: 3: Word (AH) is 0, 16: result is positive, 19: result is negative *12: 4: Word (ear) is 0, 17: result is positive, 20: result is negative *13: 5+(a): Word (eam) is 0, 18+(a): result is positive, 21+(a): result is negative Notes: • The execution cycle count found when an overflow occurs in a DIV or DIVW instruction may be a preoperation count or a post-operation count depending on the detection timing. • When an overflow occurs with DIV or DIVW instruction, the contents of the AL are destroyed. • See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. 571 APPENDIX Table B.8-8 39 Logic 1 instructions (byte, word) Mnemonic # RG B Operation L H A H I S T N Z V C R M W - AND A,#imm8 2 2 0 0 byte (A) <-- (A) and imm8 - - - - - * * R - AND A,ear 2 3 1 0 byte (A) <-- (A) and (ear) - - - - - * * R - - AND A,eam 2+ 4+(a) 0 (b) byte (A) <-- (A) and (eam) - - - - - * * R - - AND ear,A 2 3 2 0 byte (ear) <-- (ear) and (A) - - - - - * * R - - AND eam,A 2+ 5+(a) 0 2 x (b) byte (eam) <-- (eam) and (A) - - - - - * * R - * OR A,#imm8 2 2 0 0 byte (A) <-- (A) or imm8 - - - - - * * R - - OR A,ear 2 3 1 0 byte (A) <-- (A) or (ear) - - - - - * * R - - OR A,eam 2+ 4+(a) 0 (b) byte (A) <-- (A) or (eam) - - - - - * * R - - OR ear,A 2 3 2 0 byte (ear) <-- (ear) or (A) - - - - - * * R - - OR eam,A 2+ 5+(a) 0 2 x (b) byte (eam) <-- (eam) or (A) - - - - - * * R - * XOR A,#imm8 2 2 0 0 byte (A) <-- (A) xor imm8 - - - - - * * R - - XOR A,ear 2 3 1 0 byte (A) <-- (A) xor (ear) - - - - - * * R - - XOR A,eam 2+ 4+(a) 0 (b) byte (A) <-- (A) xor (eam) - - - - - * * R - - XOR ear,A 2 3 2 0 byte (ear) <-- (ear) xor (A) - - - - - * * R - - XOR eam,A 2+ 5+(a) 0 2 x (b) byte (eam) <-- (eam) xor (A) - - - - - * * R - * NOT A 1 2 0 0 byte (A) <-- not (A) - - - - - * * R - - NOT ear 2 3 2 0 byte (ear) <-- not (ear) - - - - - * * R - - NOT eam 2+ 5+(a) 0 2 x (b) byte (eam) <-- not (eam) - - - - - * * R - * ANDW A 1 2 0 0 word (A) <-- (AH) and (A) - - - - - * * R - - ANDW A,#imm16 3 2 0 0 word (A) <-- (A) and imm16 - - - - - * * R - - ANDW A,ear 2 3 1 0 word (A) <-- (A) and (ear) - - - - - * * R - - ANDW A,eam 2+ 4+(a) 0 (c) word (A) <-- (A) and (eam) - - - - - * * R - - ANDW ear,A 2 3 2 0 word (ear) <-- (ear) and (A) - - - - - * * R - - ANDW eam,A 2+ 5+(a) 0 2 x (c) word (eam) <-- (eam) and (A) - - - - - * * R - * - ORW A 1 2 0 0 word (A) <-- (AH) or (A) - - - - - * * R - ORW A,#imm16 3 2 0 0 word (A) <-- (A) or imm16 - - - - - * * R - - ORW A,ear 2 3 1 0 word (A) <-- (A) or (ear) - - - - - * * R - - ORW A,eam 2+ 4+(a) 0 (c) word (A) <-- (A) or (eam) - - - - - * * R - - ORW ear,A 2 3 2 0 word (ear) <-- (ear) or (A) - - - - - * * R - - ORW eam,A 2+ 5+(a) 0 2 x (c) word (eam) <-- (eam) or (A) - - - - - * * R - * - XORW A 1 2 0 0 word (A) <-- (AH) xor (A) - - - - - * * R - XORW A,#imm16 3 2 0 0 word (A) <-- (A) xor imm16 - - - - - * * R - - XORW A,ear 2 3 1 0 word (A) <-- (A) xor (ear) - - - - - * * R - - XORW A,eam 2+ 4+(a) 0 (c) word (A) <-- (A) xor (eam) - - - - - * * R - - XORW ear,A 2 3 2 0 word (ear) <-- (ear) xor (A) - - - - - * * R - - XORW eam,A 2+ 5+(a) 0 2 x (c) word (eam) <-- (eam) xor (A) - - - - - * * R - * NOTW A 1 2 0 0 word (A) <-- not (A) - - - - - * * R - - NOTW ear 2 3 2 0 word (ear) <-- not (ear) - - - - - * * R - - NOTW eam 2+ 5+(a) 0 2 x (c) word (eam) <-- not (eam) - - - - - * * R - * Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. 572 APPENDIX B Instructions Table B.8-9 6 Logic 2 instructions (long word) Mnemonic # RG B Operation L H A H I S T N Z V C R M W ANDL A,ear 2 6 2 0 long (A) <-- (A) and (ear) - - - - - * * R - - ANDL A,eam 2+ 7+(a) 0 (d) long (A) <-- (A) and (eam) - - - - - * * R - - ORL A,ear 2 6 2 0 long (A) <-- (A) or (ear) - - - - - * * R - - ORL A,eam 2+ 7+(a) 0 (d) long (A) <-- (A) or (eam) - - - - - * * R - - XORL A,ear 2 6 2 0 long (A) <-- (A) xor (ear) - - - - - * * R - - XORL A,eam 2+ 7+(a) 0 (d) long (A) <-- (A) xor (eam) - - - - - * * R - - Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. Table B.8-10 6 Sign inversion instructions (byte, word) Mnemonic # RG 0 B 0 Operation byte (A) <-- 0 - (A) L H A H I S T N Z V C R M W X - - - - * * * * - NEG A 1 2 NEG ear 2 3 2 0 byte (ear) <-- 0 - (ear) - - - - - * * * * - NEG eam 2+ 5+(a) 0 2 x (b) byte (eam) <-- 0 - (eam) - - - - - * * * * * NEGW A 1 2 0 0 word (A) <-- 0 - (A) - - - - - * * * * - NEGW ear 2 3 2 0 word (ear) <-- 0 - (ear) - - - - - * * * * - NEGW eam 2+ 5+(a) 0 2 x (c) word (eam) <-- 0 - (eam) - - - - - * * * * * Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. Table B.8-11 1 Normalization instruction (long word) NRML Mnemonic # A,R0 2 *1 RG B Operation L H A H I S T N Z V C R M W 1 0 long (A) <-- Shifts to the position where '1' is set for the first time. byte (RD) <-- Shift count at that time - - - - - - * - - - *1 : 4 when all accumulators have a value of 0; otherwise, 6+(R0) 573 APPENDIX Table B.8-12 18 Shift instructions (byte, word, long word) Mnemonic # RG B Operation L H A H I S T N Z V C R M W RORC A 2 2 0 0 byte (A) <-- With right rotation carry - - - - - * * - * - ROLC A 2 2 0 0 byte (A) <-- With left rotation carry - - - - - * * - * - RORC ear 2 3 2 0 byte (ear) <-- With right rotation carry - - - - - * * - * - RORC eam 2+ 5+(a) 0 2 x (b) byte (eam) <-- With right rotation carry - - - - - * * - * * ROLC ear 2 3 2 0 byte (ear) <-- With left rotation carry - - - - - * * - * - ROLC eam 2+ 5+(a) 0 2 x (b) byte (eam) <-- With left rotation carry - - - - - * * - * * ASR A,R0 2 *1 1 0 byte (A) <-- Arithmetic right shift (A, 1 bit) - - - - - * * - * - LSR A,R0 2 *1 1 0 byte (A) <-- Logical right barrel shift (A, R0) - - - - - * * - * - LSL A,R0 2 *1 1 0 byte (A) <-- Logical left barrel shift (A, R0) - - - - - * * - * - ASRW A 1 2 0 0 word (A) <-- Arithmetic right shift (A, 1 bit) - - - - * * * - * - LSRW A/SHRW A 1 2 0 0 word (A) <-- Logical right shift (A, 1 bit) - - - - * R * - * - LSLW A/SHLW A 1 2 0 0 word (A) <-- Logical left shift (A, 1 bit) - - - - - * * - * - ASRW A,R0 2 *1 1 0 word (A) <-- Arithmetic right barrel shift (A, R0) - - - - * * * - * - LSRW A,R0 2 *1 1 0 word (A) <-- Logical right barrel shift (A, R0) - - - - * * * - * - LSLW A,R0 2 *1 1 0 word (A) <-- Logical left barrel shift (A, R0) - - - - - * * - * - ASRL A,R0 2 *2 1 0 long (A) <-- Arithmetic right barrel shift (A, R0) - - - - * * * - * - LSRL A,R0 2 *2 1 0 long (A) <-- Logical right barrel shift (A, R0) - - - - * * * - * - LSLL A,R0 2 *2 1 0 long (A) <-- Logical left barrel shift (A, R0) - - - - - * * - * - *1: 6 when R0 is 0; otherwise, 5 + (R0) *2: 6 when R0 is 0; otherwise, 6 + (R0) Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. 574 APPENDIX B Instructions Table B.8-13 31 Branch 1 instructions Mnemonic # RG B Operation L H A H I S T N Z V C R M W BZ/BEQ rel 2 *1 0 0 Branch on (Z) = 1 - - - - - - - - - - BNZ/BNE rel 2 *1 0 0 Branch on (Z) = 0 - - - - - - - - - - BC/BLO rel 2 *1 0 0 Branch on (C) = 1 - - - - - - - - - - BNC/BHS rel 2 *1 0 0 Branch on (C) = 0 - - - - - - - - - - BN rel 2 *1 0 0 Branch on (N) = 1 - - - - - - - - - - BP rel 2 *1 0 0 Branch on (N) = 0 - - - - - - - - - - BV rel 2 *1 0 0 Branch on (V) = 1 - - - - - - - - - - BNV rel 2 *1 0 0 Branch on (V) = 0 - - - - - - - - - - BT rel 2 *1 0 0 Branch on (T) = 1 - - - - - - - - - - BNT rel 2 *1 0 0 Branch on (T) = 0 - - - - - - - - - - BLT rel 2 *1 0 0 Branch on (V) nor (N) = 1 - - - - - - - - - - BGE rel 2 *1 0 0 Branch on (V) nor (N) = 0 - - - - - - - - - - BLE rel 2 *1 0 0 Branch on ((V) xor (N)) or (Z) = 1 - - - - - - - - - - BGT rel 2 *1 0 0 Branch on ((V) xor (N)) or (Z) = 0 - - - - - - - - - - BLS rel 2 *1 0 0 Branch on (C) or (Z) = 1 - - - - - - - - - - BHI rel 2 *1 0 0 Branch on (C) or (Z) = 0 - - - - - - - - - - BRA rel 2 *1 0 0 Unconditional branch - - - - - - - - - - JMP @A 1 2 0 0 word (PC) <-- (A) - - - - - - - - - - JMP addr16 3 3 0 0 word (PC) <-- addr16 - - - - - - - - - - JMP @ear 2 3 1 0 word (PC) <-- (ear) - - - - - - - - - - JMP @eam 2+ 4+(a) 0 (c) word (PC) <-- (eam) - - - - - - - - - - JMPP @ear *3 2 5 2 0 word (PC) <-- (ear), (PCB) <-- (ear+2) - - - - - - - - - - JMPP @eam *3 2+ 6+(a) 0 (d) word (PC) <-- (eam), (PCB) <-- (eam+2) - - - - - - - - - - JMPP addr24 4 4 0 0 word (PC) <-- ad24 0-15, (PCB) <-- ad24 16-23 - - - - - - - - - - CALL @ear *4 2 6 1 (c) word (PC) <-- (ear) - - - - - - - - - - CALL addr16 *5 2+ 7+(a) 0 2 x (c) word (PC) <-- (eam) - - - - - - - - - - CALL @eam *4 3 6 0 (c) word (PC) <-- addr16 - - - - - - - - - - CALLV #vct4 *5 1 7 0 2 x (c) Vector call instruction - - - - - - - - - - CALLP @ear *6 2 10 2 2 x (c) word (PC) <-- (ear)0-15, (PCB) <-- (ear)16-23 - - - - - - - - - - CALLP @eam *6 2+ 11+(a) 0 *2 word (PC) <-- (eam)0-15, (PCB) <-- (eam)16-23 - - - - - - - - - - CALLP addr24 *7 4 10 0 2 x (c) word (PC) <-- addr0-15, (PCB) <-- addr16-23 - - - - - - - - - - *1: 4 when a branch is made; otherwise, 3 *2: 3 x (c) + (b) *3: Read (word) of branch destination address *4: W: Save to stack (word) R: Read (word) of branch destination address *5: Save to stack (word) *6: W: Save to stack (long word), R: Read (long word) of branch destination address *7: Save to stack (long word) Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. 575 APPENDIX Table B.8-14 19 Branch 2 instructions Mnemonic # RG B Operation L A H H I S T N Z V C R M W CBNE A,#imm8,rel 3 *1 0 0 Branch on byte (A) not equal to imm8 - - - - - * * * * - CWBNE A,#imm16,rel 4 *1 0 0 Branch on word (A) not equal to imm16 - - - - - * * * * - CBNE ear,#imm8,rel 4 *2 1 0 Branch on byte (ear) not equal to imm8 - - - - - * * * * - CBNE eam,#imm8,rel *9 4+ *3 0 (b) Branch on byte (eam) not equal to imm8 - - - - - * * * * - CWBNE ear,#imm16,rel 5 *4 1 0 Branch on word (ear) not equal to imm16 - - - - - * * * * - CWBNE eam,#imm16,rel*9 5+ *3 0 (c) Branch on word (eam) not equal to imm16 - - - - - * * * * DBNZ ear,rel 3 *5 2 0 Branch on byte (ear) = (ear) - 1, (ear) not equal to 0 - - - - - * * * - - DBNZ eam,rel 3+ *6 2 2 x (b) Branch on byte (eam) = (eam) - 1, (eam) not equal to 0 - - - - - * * * - * DWBNZ ear,rel 3 *5 2 0 Branch on word (ear) = (ear) - 1, (ear) not equal to 0 - - - - - * * * - - DWBNZ eam,rel 3+ *6 2 2 x (c) Branch on word (eam) = (eam) - 1, (eam) not equal to 0 - - - - - * * * - * INT #vct8 2 20 0 8 x (c) Software interrupt - - R S - - - - - - INT addr16 3 16 0 6 x (c) Software interrupt - - R S - - - - - - INTP addr24 4 17 0 6 x (c) Software interrupt - - R S - - - - - - 1 20 0 8 x (c) Software interrupt - - R S - - - - - - 1 *8 0 *7 Return from interrupt - - * * * * * * * - 2 6 0 (c) Saves the old frame pointer in the stack upon entering the function, then sets the new frame pointer and reserves the local pointer area. - - - - - - - - - - 1 5 0 (c) Recovers the old frame pointer from the stack upon exiting the function. - - - - - - - - - - INT9 RETI LINK #imm8 UNLINK RET *10 1 4 0 (c) Return from subroutine - - - - - - - - - - RETP *11 1 6 0 (d) Return from subroutine - - - - - - - - - - *1: 5 when a branch is made; otherwise, 4 *2: 13 when a branch is made; otherwise, 12 *3: 7+(a) when a branch is made; otherwise, 6+(a) *4: 8 when a branch is made; otherwise, 7 *5: 7 when a branch is made; otherwise, 6 *6: 8+(a) when a branch is made; otherwise, 7+(a) *7: 3 x (b) + 2 x (c) when jumping to the next interruption request; 6 x (c) when returning from the current interruption *8: 15 when jumping to the next interruption request; 17 when returning from the current interruption *9: Do not use RWj+ addressing mode with a CBNE or CWBNE instruction. *10: Return from stack (word) *11: Return from stack (long word) Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. 576 APPENDIX B Instructions Table B.8-15 28 Other control instructions (byte, word, long word) Mnemonic # RG B Operation L H A H I S T N Z V C R M W PUSHW A 1 4 0 (c) word (SP) <-- (SP) - 2, ((SP)) <-- (A) - - - - - - - - - - PUSHW AH 1 4 0 (c) word (SP) <-- (SP) - 2, ((SP)) <-- (AH) - - - - - - - - - - PUSHW PS 1 4 0 (c) word (SP) <-- (SP) - 2, ((SP)) <-- (PS) - - - - - - - - - - PUSHW rlst 2 *3 *5 *4 (SP) <-- (SP) - 2n, ((SP)) <-- (rlst) - - - - - - - - - - POPW A 1 3 0 (c) word (A) <-- ((SP)), (SP) <-- (SP) + 2 - * - - - - - - - - POPW AH 1 3 0 (c) word (AH) <-- ((SP)), (SP) <-- (SP) + 2 - - - - - - - - - - POPW PS 1 4 0 (c) word (PS) <-- ((SP)), (SP) <-- (SP) + 2 - - * * * * * * * - POPW rlst 2 *2 *5 *4 (rlst) <-- ((SP)), (SP) <-- (SP) - - - - - - - - - - JCTX @A 1 14 0 6 x (c) Context switch instruction - - * * * * * * * - AND CCR,#imm8 2 3 0 0 byte (CCR) <-- (CCR) and imm8 - - * * * * * * * - OR CCR,#imm8 2 3 0 0 byte (CCR) <-- (CCR) or imm8 - - * * * * * * * - MOV RP,#imm8 2 2 0 0 byte (RP) <-- imm8 - - - - - - - - - - MOV ILM,#imm8 2 2 0 0 byte (ILM) <-- imm8 - - - - - - - - - - MOVEA RWi,ear 2 3 1 0 word (RWi) <-- ear - - - - - - - - - - MOVEA RWi,eam 2+ 2+(a) 1 0 word (RWi) <-- eam - - - - - - - - - - MOVEA A,ear 2 1 0 0 word (A) <-- ear - * - - - - - - - - MOVEA A,eam 2+ 1+(a) 0 0 word (A) <-- eam - * - - - - - - - - ADDSP #imm8 2 3 0 0 word (SP) <-- ext(imm8) - - - - - - - - - - ADDSP #imm16 3 3 0 0 word (SP) <-- imm16 - - - - - - - - - - MOV A,brg1 2 *1 0 0 byte (A) <-- (brg1) Z * - - - * * - - - MOV brg2,A - 2 1 0 0 byte (brg2) <-- (A) - - - - - * * - - NOP 1 1 0 0 No operation - - - - - - - - - - ADB 1 1 0 0 Prefix code for AD space access - - - - - - - - - - DTB 1 1 0 0 Prefix code for DT space access - - - - - - - - - PCB 1 1 0 0 Prefix code for PC space access - - - - - - - - - - SPB 1 1 0 0 Prefix code for SP space access - - - - - - - - - - NCC 1 1 0 0 Prefix code for flag no-change - - - - - - - - - - CMR 1 1 0 0 Prefix code for common register bank - - - - - - - - - - *1: PCB, ADB, SSB, USB, SPB: 1, DTB, DPR: 2 *2: 7 + 3 x (POP count) + 2 x (POP last register number), 7 when RLST = 0 (no transfer register) *3: 29 + 3 x (PUSH count) - 3 x (PUSH last register number), 8 when RLST = 0 (no transfer register) *4: (POP count) x (c) or (PUSH count) x (c) *5: (POP count) or (PUSH count) Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. 577 APPENDIX Table B.8-16 21 Bit operand instructions Mnemonic # RG B Operation L H A H I S T N Z V C R M W MOVB A,dir:bp 3 5 0 (b) byte (A) <-- (dir:bp)b Z * - - - * * - - - MOVB A,addr16:bp 4 5 0 (b) byte (A) <-- (addr16:bp)b Z * - - - * * - - - MOVB A,io:bp 3 4 0 (b) byte (A) <-- (io:bp)b Z * - - - * * - - - MOVB dir:bp,A 3 7 0 2 x (b) bit (dir:bp)b <-- (A) - - - - - * * - - * MOVB addr16:bp,A 4 7 0 2 x (b) bit (addr16:bp)b <-- (A) - - - - - * * - - * MOVB io:bp,A 3 6 0 2 x (b) bit (io:bp)b <-- (A) - - - - - * * - - * SETB dir:bp 3 7 0 2 x (b) bit (dir:bp)b <-- 1 - - - - - - - - - * SETB addr16:bp 4 7 0 2 x (b) bit (addr16:bp)b <-- 1 - - - - - - - - - * SETB io:bp 3 7 0 2 x (b) bit (io:bp)b <-- 1 - - - - - - - - - * CLRB dir:bp 3 7 0 2 x (b) bit (dir:bp)b <-- 0 - - - - - - - - - * CLRB addr16:bp 4 7 0 2 x (b) bit (addr16:bp)b <-- 0 - - - - - - - - - * CLRB io:bp 3 7 0 2 x (b) bit (io:bp)b <-- 0 - - - - - - - - - * BBC dir:bp,rel 4 *1 0 (b) Branch on (dir:bp) b = 0 - - - - - - * - - - BBC addr16:bp,rel 5 *1 0 (b) Branch on (addr16:bp) b = 0 - - - - - - * - - - BBC io:bp,rel 4 *2 0 (b) Branch on (io:bp) b = 0 - - - - - - * - - - BBS dir:bp,rel 4 *1 0 (b) Branch on (dir:bp) b = 1 - - - - - - * - - - BBS addr16:bp,rel 5 *1 0 (b) Branch on (addr16:bp) b = 1 - - - - - - * - - - BBS io:bp,rel 4 *1 0 (b) Branch on (io:bp) b = 1 - - - - - - * - - - SBBS addr16:bp,rel 5 *3 0 2 x (b) Branch on (addr16:bp) b = 1, bit = 1 - - - - - - * - - * WBTS io:bp 3 *4 0 *5 Waits until (io:bp) b = 1 - - - - - - - - - - WBTC io:bp 3 *4 0 *5 Waits until (io:bp) b = 0 - - - - - - - - - - I S T N Z V C R M W *1: 8 when a branch is made; otherwise, 7 *2: 7 when a branch is made; otherwise, 6 *3: 10 when the condition is met; otherwise, 9 *4: Undefined count *5: Until the condition is met Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. Table B.8-17 6 Accumulator operation instructions (byte, word) Mnemonic # RG B Operation L H A H SWAP 1 3 0 0 byte (A)0-7 <--> (A)8-15 - - - - - - - - - - SWAPW 1 2 0 0 word (AH) <--> (AL) - * - - - - - - - - EXT 1 1 0 0 Byte sign extension X - - - - * * - - - EXTW 1 2 0 0 Word sign extension - X - - - * * - - - ZEXT 1 1 0 0 Byte zero extension Z - - - - R * - - - ZEXTW 1 1 0 0 Word zero extension - z - - - R * - - - 578 APPENDIX B Instructions Table B.8-18 10 String instructions Mnemonic # RG B Operation L H A H I S T N Z V C R M W MOVS / MOVSI 2 *2 *5 *3 byte transfer @AH+ <-- @AL+, counter = RW0 - - - - - - - - - - MOVSD 2 *2 *5 *3 byte transfer @AH- <-- @AL-, counter = RW0 - - - - - - - - - - SCEQ / SCEQI 2 *1 *5 *4 byte search @AH+ <-- AL, counter RW0 - - - - - * * * * - SCEQD 2 *1 *5 *4 byte search @AH- <-- AL, counter RW0 - - - - - * * * * - FILS / FILSI 2 6m+6 *5 *3 byte fill @AH+ <-- AL, counter RW0 - - - - - * * - - - MOVSW / MOVSWI 2 *2 *5 *6 word transfer @AH+ <-- @AL+, counter = RW0 - - - - - - - - - - MOVSWD 2 *2 *5 *6 word transfer @AH- <-- @AL-, counter = RW0 - - - - - - - - - - SCWEQ / SCWEQI 2 *1 *5 *7 word search @AH+ - AL, counter = RW0 - - - - - * * * * - SCWEQD 2 *1 *5 *7 word search @AH- - AL, counter = RW0 - - - - - * * * * - FILSW / FILSWI 2 6m+6 *5 *6 word fill @AH+ <-- AL, counter = RW0 - - - - - * * - - - *1: 5 when RW0 is 0, 4 + 7 x (RW0) when the counter expires, or 7n + 5 when a match occurs *2: 5 when RW0 is 0; otherwise, 4 + 8 x (RW0) *3: (b) x (RW0) + (b) x (RW0) When the source and destination access different areas, calculate the (b) item individually. *4: (b) x n *5: 2 x (RW0) *6: (c) x (RW0) + (c) x (RW0) When the source and destination access different areas, calculate the (c) item individually. *7: (c) x n Note: m: RW0 value (counter value), n: Loop count See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. 579 APPENDIX B.9 Instruction Map Each F2MC-16LX instruction code consists of 1 or 2 bytes. Therefore, the instruction map consists of multiple pages. Table B.9-2 to Table B.9-21 summarize the F2MC-16LX instruction map. ■ Structure of instruction map Figure B.9-1 Structure of instruction map Basic page map : Byte 1 Bit operation instructions Character string operation instructions 2-byte instructions ea instructions x 9 : Byte 2 An instruction such as the NOP instruction that ends in one byte is completed within the basic page. An instruction such as the MOVS instruction that requires two bytes recognizes the existence of byte 2 when it references byte 1, and can check the following one byte by referencing the map for byte 2. Figure B.9-2 shows the correspondence between an actual instruction code and instruction map. 580 APPENDIX B Instructions Figure B.9-2 Correspondence between actual instruction code and instruction map Some instructions do not contain byte 2. Length varies depending on the instruction. Byte 1 Instruction code Byte 2 Operand Operand ... [Basic page map] XY +Z [Extended page map] * UV +W *: The extended page map is a generic name of maps for bit operation instructions, character string operation instructions, 2-byte instructions, and ea instructions. Actually, there are multiple extended page maps for each type of instructions. An example of an instruction code is shown in Table B.9-1. Table B.9-1 Example of an instruction code Byte 1 (from basic page map) Byte 2 (from extended page map) NOP 00 +0=00 - AND A, #8 30 +4=34 - MOV A, ADB 60 +F=6F 00 +0=00 @RW2+d8, #8rel 70 +0=70 F0 +2=F2 Instruction 581 582 2-byte instruction Character string operation instruction Bit operation instruction Ri,ea ea instruction 9 ea instruction 8 ea instruction 7 ea instruction 6 ea instruction 5 ea instruction 4 ea instruction 3 ea instruction 2 ea instruction 1 APPENDIX Table B.9-2 Basic page map APPENDIX B Instructions Table B.9-3 Bit operation instruction map (first byte = 6CH) 583 APPENDIX Table B.9-4 Character string operation instruction map (first byte = 6EH) 584 APPENDIX B Instructions A A DIVU MULW MUL A Table B.9-5 2-byte instruction map (first byte = 6FH) 585 586 Use prohibited Use prohibited Use prohibited Use prohibited Use prohibited Use prohibited Use prohibited Use prohibited APPENDIX Table B.9-6 ea instruction 1 (first byte = 70H) APPENDIX B Instructions Table B.9-7 ea instruction 2 (first byte = 71H) 587 APPENDIX Table B.9-8 ea instruction 3 (first byte = 72H) 588 APPENDIX B Instructions Table B.9-9 ea instruction 4 (first byte = 73H) 589 APPENDIX Table B.9-10 ea instruction 5 (first byte = 74H) 590 APPENDIX B Instructions Table B.9-11 ea instruction 6 (first byte = 75H) 591 APPENDIX Table B.9-12 ea instruction 7 (first byte = 76H) 592 APPENDIX B Instructions Table B.9-13 ea instruction 8 (first byte = 77H) 593 APPENDIX Table B.9-14 ea instruction 9 (first byte = 78H) 594 APPENDIX B Instructions Table B.9-15 MOVEA RWi, ea instruction (first byte = 79H) 595 APPENDIX Table B.9-16 MOV Ri, ea instruction (first byte = 7AH) 596 APPENDIX B Instructions Table B.9-17 MOVW RWi, ea instruction (first byte = 7BH) 597 APPENDIX Table B.9-18 MOV ea, Ri instruction (first byte = 7CH) 598 APPENDIX B Instructions Table B.9-19 MOVW ea, Rwi instruction (first byte = 7DH) 599 APPENDIX Table B.9-20 XCH Ri, ea instruction (first byte = 7EH) 600 APPENDIX B Instructions Table B.9-21 XCHW RWi, ea instruction (first byte = 7FH) 601 APPENDIX APPENDIX C Timing Diagrams in Flash Memory Mode Each timing diagram for the external pins of the Flash devices in MB90350 series during Flash Memory mode is shown below. ■ Data read by read access Figure C-1 Timing diagram for read access tRC Address stable AQ16 to AQ0 tACC CE tDF tOE OE tOEH WE tOH tCE High impedance DQ7 to DQ0 602 High impedance Output defined APPENDIX C Timing Diagrams in Flash Memory Mode ■ Write, data polling, read (WE control) Figure C-2 Write, data polling, read (WE control) Third bus cycle AQ18 to AQ0 Data polling FXAAAA H PA tWC tAS PA tRC tAH CE tGHWL OE tWP tWHWH1 WE tCS DQ7 to DQ0 tOE tWPH tDF tDH A0H PD DQ7 DOU T tDS tOH 5.0 V PA: Write address PD: Write data DQ7: Reverse output of write data DOUT: Output of write data tCE Note: • Describes the last 2-bus cycle of 4-bus cycle sequences. • "Fx" in "FxAAAA" described as address is any of 4/5/6/7 (MB90F342), 1/2/3/4/5/6/7 (MB90F343), 0/1/ 2/3/4/5/6/7 (MB90F345) or 6/7 (MB90F346A). 603 APPENDIX ■ Write, data polling, read (CE control) Figure C-3 Timing diagram for write access (CE control) Third bus cycle Data polling FXAAAA H AQ18 to AQ0 PA tWC tAS PA tAH tWH WE tGHWL OE tCP tWHWH1 CE tCPH tWS tDH A0H PD DQ7 DOU T DQ7 to DQ0 tDS 5.0 V PA: Write address PD: Write data DQ7: Reverse output of write data DOUT: Output of write data Note: • Describes the last 2-bus cycle of 4-bus cycle sequences. • "Fx" in "FxAAAA" described as address is any of 4/5/6/7 (MB90F342), 1/2/3/4/5/6/7 (MB90F343), 0/1/ 2/3/4/5/6/7 (MB90F345) or 6/7 (MB90F346A). 604 APPENDIX C Timing Diagrams in Flash Memory Mode ■ Chip erase/sector erase command sequence Figure C-4 Timing diagram for write access (chip erasing/sector erasing) tAS AQ18 to AQ0 FXAAAAH tAH 75555H FXAAAAH FXAAAAH FX5555 H SA CE tGHWL OE tWP WE tWPH tCS DQ7 to DQ0 tDH AAH 55H 80H AAH 55H 10H/30H tDS VCC tVCS Note: • Describes the last 2-bus cycle of 4-bus cycle sequences. • "Fx" in "FxAAAA" described as address is any of 4/5/6/7 (MB90F342), 1/2/3/4/5/6/7 (MB90F343), 0/1/ 2/3/4/5/6/7 (MB90F345) or 6/7 (MB90F346A). 605 APPENDIX ■ Data polling Figure C-5 Timing diagram for data polling tCH CE tOE tDF OE tOEH WE tCE tOH * DQ7 DQ7 High impedance DQ7 = Valid data tWHWH1 or tWHWH2 DQ6 to DQ0 DQ6 to DQ0 = Valid data DQ6 to DQ0 = Invalid tOE Note: DQ7 is valid data (The device terminates automatic operation). ■ Toggle bit Figure C-6 Timing diagram for toggle bit CE tOE H WE tOES OE * Data (DQ7 to DQ0) DQ6 = Toggle DQ6 = Toggle DQ6 = Stop toggling tOE Note: DQ6 stops toggling (The device terminates automatic operation). 606 DQ7 to DQ0 = Valid APPENDIX C Timing Diagrams in Flash Memory Mode ■ RY/BY timing during writing/erasing Figure C-7 Timing diagram for output of RY/BY signal during writing/erasing CE Rising edge of last write pulse WE Writing or erasing RY/BY tBUSY ■ RST and RY/BY timing Figure C-8 Timing diagram for output of RY/BY signal at hardware reset CE RY/BY tRP RST tReady 607 APPENDIX ■ Enable sector protect/verify sector protect Figure C-9 Enable sector protect/verify sector protect AQ18 to AQ9 SAx AQ8, AQ2, and AQ1 SAy (AQ8, AQ2, AQ1) = (0, 1, 0) MD0 12 V 5V MD2 12 V 5V tVLHT tVLHT OE WE tWPP tOESP CE tCSP DQ7 to DQ0 01H SAx: First sector address SAy: Next sector address 608 tOE APPENDIX C Timing Diagrams in Flash Memory Mode ■ Temporary sector protect cancellation Figure C-10 Temporary sector protect cancellation MD1 12 V 5V 5V CE WE tVLHT Write/erase command sequence RY/BY 609 APPENDIX APPENDIX D List of Interrupt Vectors The interrupt vector table to be referenced for interrupt processing is allocated to FFFC00H to FFFFFFH in the memory area and also used for software interrupts. ■ List of interrupt vectors Table D-1 lists the interrupt vectors for the MB90350 series. Table D-1 Interrupt vectors (1/2) Interrupt request Interrupt cause Interrupt control register Number Address Vector address L Vector address H Vector address bank Mode register INT 0 * -- -- -- FFFFFCH FFFFFDH FFFFFEH Unused INT 1 * -- -- -- FFFFF8H FFFFF9H FFFFFAH Unused -- -- -- . . . . . . . . . . . . -- -- -- FFFFE0H FFFFE1H FFFFE2H Unused . . . INT 7 * INT 8 Reset -- -- FFFFDCH FFFFDDH FFFFDEH FFFFDFH INT 9 INT9 instruction -- -- FFFFD8H FFFFD9H FFFFDAH Unused INT 10 Exception -- -- FFFFD4H FFFFD5H FFFFD6H Unused INT 11 CAN0 RX FFFFD1H FFFFD2H Unused 0000B0H FFFFD0H ICR00 FFFFCCH FFFFCDH FFFFCEH Unused FFFFC8H FFFFC9H FFFFCAH Unused FFFFC4H FFFFC5H FFFFC6H Unused FFFFC0H FFFFC1H FFFFC2H Unused FFFFBCH FFFFBDH FFFFBEH Unused FFFFB8H FFFFB9H FFFFBAH Unused FFFFB4H FFFFB5H FFFFB6H Unused FFFFB0H FFFFB1H FFFFB2H Unused FFFFACH FFFFADH FFFFAEH Unused FFFFA8H FFFFA9H FFFFAAH Unused FFFFA4H FFFFA5H FFFFA6H Unused FFFFA0H FFFFA1H FFFFA2H Unused FFFF9CH FFFF9DH FFFF9EH Unused FFFF98H FFFF99H FFFF9AH Unused FFFF94H FFFF95H FFFF96H Unused INT 12 CAN0 TX/NS INT 13 CAN1 RX / Input Capture6 ICR01 INT 14 CAN1 TX/NS /Input Caputer7 INT 15 CAN2 RX / I2C0 ICR02 INT 16 CAN2 TX/NS INT 17 16-bit ReloadTimer0 ICR03 INT 18 16-bit ReloadTimer1 INT 19 16-bit ReloadTimer2 ICR04 INT 20 16-bit ReloadTimer3 INT 21 PPG 0/1/4/5 ICR05 INT 22 PPG 2/3/6/7 INT 23 PPG 8/9/C/D ICR06 INT 24 PPG A/B/E/F INT 25 Time Base Timer ICR07 INT 26 610 External Interrupt 0-3/8-11 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H APPENDIX D List of Interrupt Vectors Table D-1 Interrupt vectors (2/2) Interrupt request INT 27 Interrupt cause Interrupt control register Number Address ICR08 0000B8H Watch Timer INT 28 External Interrupt 4-7/12-15 INT 29 A/D Converter ICR09 INT 30 I/O Timer 0/1 INT 31 Input Capture 4/5 / I2C1 ICR10 INT 32 Output Compare 0/1/4/5 INT 33 Input Capture 0-3 ICR11 INT 34 Output Compare 2/3/6/7 INT 35 UART 0 RX ICR12 INT 36 UART 0 TX INT 37 UART 1 RX / UART3 RX ICR13 INT 38 UART 1 TX / UART 3 TX INT 39 UART 2 RX / UART 4 RX ICR14 INT 40 UART 2 TX / UART 4 TX INT 41 Flash Memory ICR15 INT 42 Delayed Interrupt 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH Vector address L Vector address H Vector address bank Mode register FFFF90H FFFF91H FFFF92H Unused FFFF8CH FFFF8DH FFFF8EH Unused FFFF88H FFFF89H FFFF8AH Unused FFFF84H FFFF85H FFFF86H Unused FFFF80H FFFF81H FFFF82H Unused FFFF7CH FFFF7DH FFFF7EH Unused FFFF78H FFFF79H FFFF7AH Unused FFFF74H FFFF75H FFFF76H Unused FFFF70H FFFF71H FFFF72H Unused FFFF6CH FFFF6DH FFFF6EH Unused FFFF68H FFFF69H FFFF6AH Unused FFFF64H FFFF65H FFFF66H Unused FFFF60H FFFF61H FFFF62H Unused FFFF5CH FFFF5DH FFFF5EH Unused FFFF58H FFFF59H FFFF5AH Unused FFFF54H FFFF55H FFFF56H Unused -- -- -- FFFF50H FFFF51H FFFF52H Unused -- -- -- . . . . . . . . . . . . INT 254 -- -- -- FFFC04H FFFC05H FFFC06H Unused INT 255 -- -- -- FFFC00H FFFC01H FFFC02H Unused INT 43 . . . *: When PCB is FFH, the vector area for the CALLV instruction is the same as that for INT #vct8 (#0 to #7). Care must be taken when using the vector for the CALLV instruction. 611 APPENDIX ■ Interrupt causes, interrupt vectors, and interrupt control registers Table D-2 summarizes the relationships among the interrupt causes, interrupt vectors, and interrupt control registers of the MB90350 series. Table D-2 Interrupt causes, interrupt vectors, and interrupt control registers (1/2) Interrupt cause EI2 OS clear DMA channel number Interrupt vector Interrupt control register Number Address Number Address Reset N - #08 FFFFDCH - - INT9 instruction N - #09 FFFFD8H - - Exception N - #10 FFFFD4H - - CAN 0 RX N - #11 FFFFD0H ICR00 N - #12 FFFFCCH 0000B0H CAN 0 TX/NS CAN 1 RX / Input Capture 6 N - #13 FFFFC8H ICR01 N - #14 FFFFC4H 0000B1H CAN 1 TX/NS / Input Capture 7 CAN 2 RX / I2C0 N - #15 FFFFC0H ICR02 0000B2H CAN 2 TX/NS N - #16 FFFFBCH 16-bit Reload Timer 0 Y1 0 #17 FFFFB8H ICR03 Y1 1 #18 FFFFB4H 0000B3H 16-bit Reload Timer 1 16-bit Reload Timer 2 Y1 2 #19 FFFFB0H ICR04 Y1 - #20 FFFFACH 0000B4H 16-bit Reload Timer 3 PPG 0/1/4/5 N - #21 FFFFA8H ICR05 N - #22 FFFFA4H 0000B5H PPG 2/3/6/7 PPG 8/9/C/D N - #23 FFFFA0H ICR06 N - #24 FFFF9CH 0000B6H PPG A/B/E/F Time Base Timer N - #25 FFFF98H ICR07 Y1 3 #26 FFFF94H 0000B7H External Interrupt 0-3, 8-11 Watch Timer N - #27 FFFF90H ICR08 Y1 4 #28 FFFF8CH 0000B8H External Interrupt 4-7, 12-15 A/D Converter Y1 5 #29 FFFF88H ICR09 N - #30 FFFF84H 0000B9H I/O Timer 0 / I/O Timer 1 612 APPENDIX D List of Interrupt Vectors Table D-2 Interrupt causes, interrupt vectors, and interrupt control registers (2/2) Interrupt cause 2 EI OS clear DMA channel number Interrupt vector Number Address Input Capture 4/5 / I2C1 Y1 6 #31 FFFF80H Output Compare 0/1/4/5 Y1 7 #32 FFFF7CH Input Capture 0-3 Y1 8 #33 FFFF78H Output Compare 2/3/6/7 Y1 9 #34 FFFF74H UART 0 RX Y2 10 #35 FFFF70H UART 0 TX Y1 11 #36 FFFF6CH UART 1 RX / UART 3 RX Y2 12 #37 FFFF68H UART 1 TX / UART 3 TX Y1 13 #38 FFFF64H UART 2 RX / UART 4 RX Y2 14 #39 FFFF60H UART 2 TX / UART 4 TX Y1 15 #40 FFFF5CH Flash Memory N - #41 FFFF58H Delayed interrupt N - #42 FFFF54H Interrupt control register Number Address ICR10 0000BAH ICR11 0000BBH ICR12 0000BCH ICR13 0000BDH ICR14 0000BEH ICR15 0000BFH Y1: An EI2OS interrupt clear signal or EI2OS register read access clears the interrupt request flag. Y2: An EI2OS interrupt clear signal or EI2OS register read access clears the interrupt request flag. A stop request is issued. N: An EI2OS interrupt clear signal does not clear the interrupt request flag. Note: For a peripheral module having two interrupt causes for one interrupt number, an EI2OS interrupt clear signal clears both interrupt request flags. When EI2OS ends, an EI2OS clear signal is sent to every interrupt flag assigned to each interrupt number. EI2OS is activated when one of two interrupts assigned to an interrupt control register (ICR) is caused while EI2OS is enabled. This means that an EI2OS descriptor that should essentially be specific to each interrupt cause is shared by two interrupts. Therefore, while one interrupt is enabled, the other interrupt must be disabled. 613 APPENDIX 614 INDEX INDEX The index follows on the next page. This is listed in alphabetic order. 615 INDEX Index Symbol A µDMAC µDMAC functions.............................................. 78 A Numerics 16-bit free-running timer 16-bit free-running timer................................... 212 16-bit free-running timer 0 and 1 ....................... 214 16-bit free-running timer block diagram ............. 216 16-bit free-running timer operation .................... 221 16-bit I/O timer Block diagram of 16-bit I/O timer ...................... 213 16-bit reload register Register layout of 16-bit timer register (TMR)/16-bit reload register (TMRLR) ..................... 250 16-bit reload timer 16-bit reload timer register ................................ 246 Internal clock operation of 16-bit reload timer..... 251 Outline of 16-bit reload timer (with event count function)............................................. 244 Output pin functions of 16-bit reload timer ......... 254 Underflow operation of 16-bit reload timer ......... 253 16-bit timer register Register layout of 16-bit timer register (TMR)/16-bit reload register (TMRLR) ..................... 250 1M-bit flash memory 1M-bit flash memory features............................ 482 Programming example of 1M-bit flash memory .......................................................... 512 Sector configuration of the 1M-bit flash memory .......................................................... 483 24-bit operand 24-bit operand specification ................................ 28 8/16-bit PPG 8/16-bit PPG interrupts ..................................... 280 8/16-bit PPG output operation ........................... 277 8/16-bit PPG registers....................................... 268 Block diagram of 8/16-bit PPG.......................... 266 Controlling pin output of 8/16-bit PPG pulses .......................................................... 279 Function of 8/16-bit PPG .................................. 264 Initial values of 8/16-bit PPG hardware .............. 281 Operation modes of 8/16-bit PPG ...................... 276 Operations of 8/16-bit PPG ............................... 276 Relationship between 8/16-bit PPG reload value and pulse width ......................................... 277 Selecting a count clock for 8/16-bit PPG ............278 616 Accumulator (A)................................................ 35 A/D converter Block diagram of A/D converter........................ 298 Features of A/D converter................................. 296 Registers for A/D converter .............................. 299 Acceptance filter Acceptance filtering ......................................... 457 Setting acceptance filter.................................... 460 Acceptance mask registers Acceptance mask registers 0 and 1 (AMR0 and AMR1) .............................................. 447 Acceptance mask select register Acceptance mask select register (AMSR)........... 445 Accumulator Accumulator (A)................................................ 35 Acknowledgement Acknowledgement ........................................... 405 ADCR0 Data register (ADCR0,ADCR1) ........................ 305 ADCR1 Data register (ADCR0,ADCR1) ........................ 305 ADCS0 Control Status Register (ADCS0) ...................... 300 ADCS1 Control Status Register (ADCS1) ...................... 302 Address match detection function Block diagram of the address match detection function ......................................................... 470 Operation of the address match detection function ......................................................... 473 System configuration example of the address match detection function ............................... 474 Addressing Addressing ...................................................... 544 ADSR Setting Register (ADSR) .................................. 306 Alternative mode Alternative mode ............................................. 485 AMR Acceptance mask registers 0 and 1 (AMR0 and AMR1) .............................................. 447 AMSR Acceptance mask select register (AMSR)........... 445 Analog input enable register Analog input enable register.............................. 296 INDEX Analog input enable registers Analog input enable registers ............................ 195 Arbitration Arbitration....................................................... 404 ARSR Automatic Ready Function Selection Register (ARSR) ............................................. 175 Asynchronous LIN mode Operation in asynchronous LIN mode (operation mode 3) .............................. 364 Asynchronous mode Operation in asynchronous mode....................... 359 Automatic Ready Function Selection Register Automatic Ready Function Selection Register (ARSR) ............................................. 175 B Bank addressing Bank addressing types ........................................ 29 Bank select Bank select prefix .............................................. 43 BAP Buffer address pointer (BAP) ........................ 72, 91 Basic configuration Basic configuration of MB90F352/C(S) serial programming connection .................... 518 Baud rate Calculating the baud rate .................................. 352 Suggested division ratios for different machine speeds and baud rates..................................... 353 UART baud rate selection................................. 350 Baud rate generator register Baud rate generator register (BGRn0/n1)............ 343 Baud rate/reload counter register Baud rate/reload counter register ....................... 343 BGRn Baud rate generator register (BGRn0/n1)............ 343 Bidirectional communication Bidirectional communication function................ 368 Bit timing Setting bit timing ............................................. 460 Bit timing register Bit timing register (BTR).................................. 430 Bit timing register (BTR) contents ..................... 430 Block Diagram Block Diagram of Pull-up Control Register (PUCR) .......................................................... 194 Block Diagram of the Clock Generation Block .......................................................... 105 Block Diagram of the Low-Power Consumption Control Circuit.................................... 137 Block Diagram of Watch Timer......................... 258 Block diagram 16-bit free-running timer block diagram..............216 Block diagram of 16-bit I/O timer ......................213 Block diagram of 8/16-bit PPG ..........................266 Block diagram of A/D converter ........................298 Block diagram of CAN controller.......................411 Block diagram of delayed interrupt.......................98 Block diagram of DTP/external interrupts ...........284 Block diagram of Flash/Mask ROM version............6 Block diagram of LIN-UART ............................325 Block diagram of MB90V340(S) ...........................5 Block diagram of ROM mirroring module ..........478 Block diagram of the address match detection function ..........................................................470 Block diagram of the entire flash memory...........483 Block diagram of the external reset pin ...............126 Block diagram of timebase timer........................200 Input capture block diagram ..............................235 Watchdog timer block diagram ..........................206 BTR Bit timing register (BTR) ..................................430 Bit timing register (BTR) contents......................430 Buffer address pointer Buffer address pointer (BAP).........................72, 91 Bus control register Bus control register (IBCR) ...............................387 Bus control register (IBCR) contents ..................389 Bus Control Signal Selection Register Bus Control Signal Selection Register (ECSR) ..........................................................178 Bus Mode Memory Space in Each Bus Mode......................171 Bus operation stop Conditions for canceling bus operation stop (HALT=0) .........................................426 Conditions for setting bus operation stop (HALT=1) ..........................................................426 State during bus operation stop (HALT=1)..........426 Bus Pin Control Circuit External Memory Access (Bus Pin Control Circuit) ..........................................................173 Bus status register Bus status register (IBSR) .................................384 Bus status register (IBSR) contents.....................385 BVAL Caution for disabling message buffers by BVAL bits ..........................................................468 BVALR Message buffer valid register (BVALR)..............433 C CAN controller Block diagram of CAN controller.......................411 617 INDEX Canceling a transmission request from the CAN controller ........................................... 455 Completing transmission of the CAN controller .......................................................... 455 Features of CAN controller ............................... 410 Reception flowchart of the CAN controller ......... 459 Starting transmission of the CAN controller........ 455 Transmission flowchart of the CAN controller .... 456 CAN direct mode register CAN direct mode register (CDMR).................... 467 CAN direct mode register contents..................... 467 CCR Condition code register (CCR)............................. 37 CDMR CAN direct mode register (CDMR).................... 467 CE control Write,data polling,read (CE control)...................604 Chip erase Chip erase/sector erase command sequence ........ 605 CKSCR Configuration of the Clock Selection Register (CKSCR)........................................... 108 Clock Clock prescaler settings .................................... 401 Clocks............................................................. 102 Clock control register Clock control register (ICCR)............................ 400 Clock control register (ICCR) contents............... 400 Clock frequency Common machine clock frequencies .................. 402 Oscillating clock frequency and serial clock input frequency........................................... 520 Clock Generation Block Diagram of the Clock Generation Block .......................................................... 105 Clock Mode Clock Mode Transition ..................................... 114 Clock Selection Register Clock Selection Registers.................................. 107 Configuration of the Clock Selection Register (CKSCR)........................................... 108 CMOD Sample output waveform when CMOD[1:0]= "00B" .......................................................... 230 CMR Common register bank prefix (CMR) ................... 44 Command sequence table Command sequence table.................................. 489 Common machine Common machine clock frequencies .................. 402 Common register bank prefix Common register bank prefix (CMR) ................... 44 Condition code register Condition code register (CCR)............................. 37 618 Connection method Inter-CPU connection method ........................... 357 Continuous mode Continuous mode ............................................. 310 Example of starting of EI2OS in continuous mode ......................................................... 315 Control Status Register Control status register....................................... 237 Control Status Register (ADCS0) ...................... 300 Control Status Register (ADCS1) ...................... 302 Control status register (CSR) (lower) ................. 421 Control status register (CSR) (upper) ................. 423 Control status register (CSR-lower) contents ...... 422 Control status register (CSR-upper) contents ...... 424 Control status register of free-running timer (lower) ......................................................... 218 Control status register of output compare (lower byte) ......................................................... 225 Control status register of output compare (upper byte) ......................................................... 227 Conversion Conversion using EI2OS................................... 312 Converted-data Converted-data protection function .................... 319 Count clock Selecting a count clock for 8/16-bit PPG ............ 278 Counter operation state Counter operation state..................................... 255 Counting Counting example ............................................ 354 CPU CPU Intermittent Operating Mode ..................... 135 CPU Intermittent Operation Mode ..................... 143 CPU Operating Modes and Current Consumption ......................................................... 134 Inter-CPU connection method ........................... 357 Outline of CPU memory space ............................ 25 Outline of the CPU............................................. 24 CSR Control status register (CSR) (lower) ................. 421 Control status register (CSR) (upper) ................. 423 Control status register (CSR-lower) contents ...... 422 Control status register (CSR-upper) contents ...... 424 Current Consumption CPU Operating Modes and Current Consumption ......................................................... 134 D Data Counter Value in Data Counter ........................................ 87 Data counter Data counter (DCT) ..................................... 71, 87 Data direction register Data direction register ...................................... 192 INDEX Data frame Processing for reception of data frame and remote frame ................................................. 458 Data polling Data polling..................................................... 606 Write,data polling,read (CE control) .................. 604 Write,data polling,read (WE control) ................. 603 Data polling flag Data polling flag (DQ7).................................... 493 Data read Data read by read access ................................... 602 Data register Data register (ADCR0,ADCR1) ........................ 305 Data register (IDAR) ........................................ 399 Data register contents ....................................... 399 Data register of free-running timer..................... 217 Data register x (x=0 to 15) (DTRx) .................... 453 List of message buffers (DLC registers and data registers)......... 417 Data Transfer Data Transfer Cycle Count (internal transfer) ....... 95 DCSR DMA descriptor channel specification register (DCSR) ............................................... 80 DCT Data counter (DCT)...................................... 71, 87 DDWR Configuration of DMA Descriptor window register (DDWR) .............................................. 85 Delayed interrupt Block diagram of delayed interrupt ...................... 98 Delayed interrupt cause issuance/cancellation register (DIRR:delayed interrupt request register) ............................................................ 99 Delayed interrupt occurrence............................. 100 DER DMA enable register (DER)................................ 84 Descriptor Extended intelligent I/O service descriptor (ISD) ............................................................ 71 Device Handling the device............................................ 20 Different blocks Explanation of the different blocks .................... 326 Direct addressing Direct addressing ............................................. 546 DIRR Delayed interrupt cause issuance/cancellation register (DIRR:delayed interrupt request register) ............................................................ 99 DLC register DLC register x (x=0 to 15) (DLCRx) ................. 452 List of message buffers (DLC registers and data registers)......... 417 DLCRx DLC register x (x=0 to 15) (DLCRx)..................452 DMA Intelligent I/O service (EI2OS) function,DMA and interrupts ............................................244 DMA control register DMA control register (DMACS)..........................89 DMA descriptor channel specification register DMA descriptor channel specification register (DCSR) ...............................................80 DMA Descriptor window register Configuration of DMA Descriptor window register (DDWR) ..............................................85 DMA enable register DMA enable register (DER) ................................84 DMA status register DMA status register (DSR)..................................82 DMA stop status register DMA stop status register (DSSR).........................83 DMAC DMAC Operation ...............................................92 DMACS DMA control register (DMACS)..........................89 DQ2 Toggle bit-2 flag (DQ2) ....................................498 DQ3 Sector erase timer Flag (DQ3)............................497 DQ5 Timing limit exceeded flag (DQ5)......................496 DQ6 Toggle bit flag (DQ6) .......................................495 DQ7 Data polling flag (DQ7) ....................................493 DSR DMA status register (DSR)..................................82 DSSR DMA stop status register (DSSR).........................83 DTP Block diagram of DTP/external interrupts ...........284 Interrupt/DTP enable register (ENIR:External interrupt request enable register) ..........286 Interrupt/DTP flags (EIRR:External interrupt request register) ..............................................286 Notes on using DTP/external interrupts...............292 Outline of DTP/external interrupts .....................284 Switching between external interrupt and DTP requests.......................................291 DTP/external interrupts Block diagram of DTP/external interrupts ...........284 Outline of DTP/external interrupts .....................284 DTRx Data register x (x=0 to 15) (DTRx).....................453 619 INDEX E ECCR Extended communication control register (ECCR) .......................................................... 341 ECSR Bus Control Signal Selection Register (ECSR) .......................................................... 178 Effective Address Field Effective Address Field............................. 545, 562 EI2OS Conversion using EI2OS ................................... 312 EI2OS operation flow ......................................... 74 Example of flow of data protection function (when EI2OS is used) .................................... 320 Example of starting of EI2OS in continuous mode .......................................................... 315 Example of starting of EI2OS in single mode ......313 Example of starting of EI2OS in stop mode......... 317 Extended intelligent I/O service (EI2OS) ........52, 69 Intelligent I/O service (EI2OS) function,DMA and interrupts ............................................244 LIN-UART interrupts and EI2OS....................... 346 UART EI2OS functions .................................... 346 UART interrupt and EI2OS ............................... 324 EI2OS status register EI2OS status register (ISCS)................................ 73 EIRR Interrupt/DTP flags (EIRR:External interrupt request register).............................................. 286 ENIR Interrupt/DTP enable register (ENIR:External interrupt request enable register) .......... 286 Erase Chip erase/sector erase command sequence ........ 605 Restarting erasing of flash memory sectors ......... 508 Suspending erasing of flash memory sectors ....... 507 Erasing optional data Erasing optional data (erasing sectors) in the flash memory.............................................. 505 Erasing sectors Erasing optional data (erasing sectors) in the flash memory.............................................. 505 Erasing sectors in the flash memory ...................505 ESCR Extended status/control register (ESCR) ............. 339 Event count Outline of 16-bit reload timer (with event count function)............................................. 244 Exceptions Exceptions......................................................... 54 Execution cycle Execution cycle count....................................... 559 620 Extended communication control register Extended communication control register (ECCR) ......................................................... 341 Extended intelligent I/O service Extended intelligent I/O service (EI2OS) ........ 52, 69 Extended intelligent I/O service descriptor (ISD) ........................................................... 71 Extended status/control register Extended status/control register (ESCR)............. 339 External Address Output Control Register External Address Output Control Register (HACR) ......................................................... 177 External Clock Connection of an Oscillator or an External Clock to the Microcontroller................................... 119 Using external clock......................................... 354 External interrupt Block diagram of DTP/external interrupts .......... 284 External interrupt operation .............................. 289 Notes on using DTP/external interrupts.............. 292 Outline of DTP/external interrupts..................... 284 Switching between external interrupt and DTP requests ...................................... 291 External interrupt request enable register Interrupt/DTP enable register (ENIR:External interrupt request enable register).......... 286 External interrupt request register Interrupt/DTP flags (EIRR:External interrupt request register) ............................................. 286 External Memory External Memory Access (Bus Pin Control Circuit) ......................................................... 173 External Memory Access Control Signal............ 181 External Memory Access Registers.................... 174 External reset Block diagram of the external reset pin .............. 126 F F2MC-16LX F2MC-16LX instruction list .............................. 566 Features Features .............................................................. 3 Fetch timing Sample of input capture fetch timing.................. 241 Filter Acceptance filtering ......................................... 457 Setting acceptance filter.................................... 460 Flag change disable prefix Flag change disable prefix (NCC)........................ 44 Flash memory 1M-bit flash memory features ........................... 482 Block diagram of the entire flash memory .......... 483 Detailed explanation of flash memory write/erase ......................................................... 500 INDEX Erasing all data in the flash memory (erasing chips) .......................................................... 504 Erasing optional data (erasing sectors) in the flash memory.............................................. 505 Erasing sectors in the flash memory ................... 505 Flash memory control signals ............................ 485 Flash memory mode ......................................... 485 Notes on using flash memory ............................ 509 Programming example of 1M-bit flash memory .......................................................... 512 Restarting erasing of flash memory sectors......... 508 Sector configuration of the 1M-bit flash memory .......................................................... 483 Setting the flash memory to the read/reset state .......................................................... 501 Suspending erasing of flash memory sectors ....... 507 Writing data to the flash memory....................... 502 Writing to the flash memory.............................. 502 Writing to/erasing flash memory ....................... 482 Flash memory control status register Flash memory control status register (FMCS) .................................................. 482, 487 Flash microcomputer programmer Example of minimum connection to the flash microcomputer programmer (power ..... 527 Example of minimum connection to the flash microcomputer programmer (user power supply used) .................... 525 Flash/Mask ROM Block diagram of Flash/Mask ROM version ........... 6 Flow charts Programming flow charts.................................. 406 FMCS Flash memory control status register (FMCS) .................................................. 482, 487 Frame format Setting frame format......................................... 460 Free-running timer 16-bit free-running timer................................... 212 16-bit free-running timer 0 and 1 ....................... 214 16-bit free-running timer block diagram ............. 216 16-bit free-running timer operation .................... 221 Control status register of free-running timer (lower) .......................................................... 218 Data register of free-running timer..................... 217 H HACR External Address Output Control Register (HACR) .......................................................... 177 Hardware interrupt Hardware interrupt operation............................... 63 Hardware interrupts...................................... 50, 62 Occurrence and release of hardware interrupt ....... 64 Structure of hardware interrupt ............................ 62 Hardware sequence flags Hardware sequence flags ...................................491 Hold Function Hold Function ..................................................185 I I/O I/O area .............................................................26 I/O maps (00XX addresses) ...............................530 I/O port I/O port registers...............................................189 I/O ports ..........................................................188 I/O register address pointer I/O register address pointer (IOA) ........................88 I/O timer Block diagram of 16-bit I/O timer ......................213 2 I C Interface I2C Interface registers .......................................382 IBCR Bus control register (IBCR) ...............................387 Bus control register (IBCR) contents ..................389 IBSR Bus status register (IBSR) .................................384 Bus status register (IBSR) contents.....................385 ICCR Clock control register (ICCR) ............................400 Clock control register (ICCR) contents ...............400 ICE Input capture edge register (ICE01,ICE23,ICE45,ICE67)...............239 ICR Interrupt control register (ICR) ............................57 ID Setting ID ........................................................460 ID register ID register x (x=0 to 15) (IDRx).........................450 List of message buffers (ID registers) .................414 IDAR Data register (IDAR).........................................399 IDE register IDE register (IDER)..........................................434 IDER IDE register (IDER)..........................................434 IDRx ID register x (x=0 to 15) (IDRx).........................450 Indirect addressing Indirect addressing............................................552 Input capture Input capture ....................................................235 Input capture (2 channels per one module) ..........213 Input capture block diagram ..............................235 Sample of input capture fetch timing ..................241 621 INDEX Input capture data register Input capture data register ................................. 236 Input capture edge register Input capture edge register (ICE01,ICE23,ICE45,ICE67) .............. 239 Input level select register Input level select register................................... 196 Input-output circuits Input-output circuits ........................................... 16 Instruction Interrupt disable instructions ............................... 46 Restrictions on interrupt disable instructions and prefix instructions.................................. 46 Instruction list F2MC-16LX instruction list............................... 566 Instruction map Structure of instruction map .............................. 580 Instruction presentation Description of instruction presentation items and symbols.............................................. 563 Instruction types Instruction types............................................... 543 INT SCC,MSS and INT bit competition .................... 390 Intelligent I/O service Intelligent I/O service (EI2OS) function,DMA and interrupts ............................................244 Inter-CPU Inter-CPU connection method ........................... 357 Internal clock Internal clock operation of 16-bit reload timer..... 251 Internal transfer Data Transfer Cycle Count (internal transfer)........ 95 Interrupt 8/16-bit PPG interrupts ..................................... 280 Hardware interrupts ............................................ 50 Intelligent I/O service (EI2OS) function,DMA and interrupts ............................................244 Interrupt disable instructions ............................... 46 Interrupt flow..................................................... 60 Interval interrupt function ................................. 203 LIN-UART interrupts ....................................... 344 LIN-UART interrupts and EI2OS....................... 346 Reception interrupt generation and flag set timing .......................................................... 347 Software interrupts ............................................. 51 Structure of hardware interrupt ............................ 62 Switching to a Standby Mode and Interrupt ........ 163 Transmission interrupt generation and flag set timing .......................................................... 348 Transmission interrupt request generation timing .......................................................... 348 UART interrupt and EI2OS ............................... 324 622 Interrupt control Interrupt causes,interrupt vectors,and interrupt control registers ............................................. 612 Interrupt control register Interrupt control register (ICR)............................ 57 Interrupt disable Restrictions on interrupt disable instructions and prefix instructions ................................. 46 Interrupt vector Interrupt causes,interrupt vectors,and interrupt control registers ............................................. 612 Interrupt vector .................................................. 55 List of interrupt vectors .............................. 67, 610 Interrupt/DTP enable register Interrupt/DTP enable register (ENIR:External interrupt request enable register).......... 286 Interrupt/DTP flags Interrupt/DTP flags (EIRR:External interrupt request register) ............................................. 286 Interval interrupt Interval interrupt function ................................. 203 IOA I/O register address pointer (IOA) ....................... 88 ISCS EI2OS status register (ISCS) ............................... 73 ISD Extended intelligent I/O service descriptor (ISD) ........................................................... 71 ISMK Seven bit slave address mask register (ISMK) ......................................................... 397 ITBA Ten bit slave address register (ITBA)................. 394 Ten bit slave address register (ITBA) contents ......................................................... 394 ITMK Ten bit address mask register (ITMK)................ 395 Ten bit address mask register (ITMK) contents ......................................................... 395 L Last event indicator register Last event indicator register (LEIR) ................... 427 Last event indicator register (LEIR) contents ...... 428 LEIR Last event indicator register (LEIR) ................... 427 Last event indicator register (LEIR) contents ...... 428 LIN LIN-master-slave communication function......... 373 LIN-master-slave communication LIN-master-slave communication function......... 373 LIN-UART Block diagram of LIN-UART ........................... 325 INDEX LIN-UART functions ....................................... 322 LIN-UART interrupts ....................................... 344 LIN-UART interrupts and EI2OS ...................... 346 LIN-UART pins............................................... 329 LIN-UART registers ........................................ 330 Low-Power Consumption Block Diagram of the Low-Power Consumption Control Circuit................................... 137 Low-power consumption mode Setting low-power consumption mode ............... 460 Low-Power Consumption mode Control Register Low-Power Consumption Mode Control Register (LPMCR) ........................................... 140 Notes on accessing the Low-Power Consumption mode Control Register (LPMCR) to switch the Standby Mode .............................. 164 LPMCR Low-Power Consumption Mode Control Register (LPMCR) ........................................... 140 Notes on accessing the Low-Power Consumption made Control Register (LPMCR) to switch the Standby Mode ............................... 164 LQFP-64 Pin assignments (LQFP-64) .................................. 7 M Machine Clock Machine Clock ................................................ 115 Machine speeds Suggested division ratios for different machine speeds and baud rates..................................... 353 Main Clock Mode Main Clock Mode,PLL Clock Mode and subclock Mode ................................................. 114 Master LIN-master-slave communication function ......... 373 Master-slave communication function................ 370 UART as master device .................................... 374 Master-slave communication Master-slave communication function................ 370 MB90F352 Basic configuration of MB90F352/C(S) serial programming connection .................... 518 MB90V340(S) Block diagram of MB90V340(S)........................... 5 Memory Access Modes Memory Access Modes .................................... 168 Memory Space Memory Space in Each Bus Mode ..................... 171 Multi-byte data allocation in memory space.......... 31 Outline of CPU memory space ............................ 25 Message buffer Caution for disabling message buffers by BVAL bits .......................................................... 468 List of message buffers (DLC registers and data registers).............................................417 List of message buffers (ID registers) .................414 Message buffer control registers.........................420 Message buffers .......................................420, 449 Procedure for reception by message buffer (x) ..........................................................463 Procedure for transmission by message buffer (x) ..........................................................461 Setting configuration of multi-level message buffer ..........................................................465 Message buffer control registers Message buffer control registers.........................420 Message buffer valid register Message buffer valid register (BVALR)..............433 Minimum connection Example of minimum connection to the flash microcomputer programmer (power......527 Example of minimum connection to the flash microcomputer programmer (user power supply used) ......................525 Mode Data Mode Data .......................................................170 Status of pins after mode data is read ..................132 Mode fetch Mode fetch.......................................................128 Mode pin Mode pins................................................127, 169 MSS SCC,MSS and INT bit competition ....................390 Multi-byte data Accessing multi-byte data....................................31 Multi-byte data allocation in memory space ..........31 Multi-level Setting configuration of multi-level message buffer ..........................................................465 Multiple interrupts Multiple interrupts ..............................................66 Multiplier Selection of a PLL Clock Multiplier ...................115 N NCC Flag change disable prefix (NCC) ........................44 O Operand 24-bit operand specification.................................28 Operation Operation in asynchronous LIN mode (operation mode 3) ..............................................364 Operation enable bit Operation enable bit..........................................358 623 INDEX Oscillation Stabilization Wait Oscillation stabilization wait and reset state ........ 125 Oscillation Stabilization Wait Interval ................ 118 Oscillation Stabilization Wait Time Oscillation Stabilization Wait Time.................... 164 Reset causes and oscillation stabilization wait times .......................................................... 124 Oscillator Connection of an Oscillator or an External Clock to the Microcontroller ................................... 119 Output compare Control status register of output compare (lower byte) .......................................................... 225 Control status register of output compare (upper byte) .......................................................... 227 Output compare................................................ 223 Output compare (2 channels per one module) .......................................................... 212 Output compare register.................................... 224 Overall control registers List of overall control registers .......................... 412 Overall control registers.................................... 420 P Package Package dimensions.............................................. 9 PADR Program address detection registers (PADR0 to PADR5) ............................................. 471 PC Program counter (PC) ......................................... 40 Pin assignments Pin assignments (LQFP-64)................................... 7 Pin functions Pin functions...................................................... 10 PLL Clock Selection of a PLL Clock Multiplier...................115 PLL Clock Mode Main Clock Mode,PLL Clock Mode and subclock Mode ................................................. 114 PLL/Subclock Control Register Configuration of the PLL/Subclock Control Register (PSCCR) ............................................112 Port data register Port data register .............................................. 190 PPG 8/16-bit PPG interrupts ..................................... 280 8/16-bit PPG output operation ........................... 277 8/16-bit PPG registers....................................... 268 Block diagram of 8/16-bit PPG.......................... 266 Controlling pin output of 8/16-bit PPG pulses .......................................................... 279 Function of 8/16-bit PPG .................................. 264 Initial values of 8/16-bit PPG hardware .............. 281 624 Operation modes of 8/16-bit PPG ...................... 276 Operations of 8/16-bit PPG ............................... 276 Relationship between 8/16-bit PPG reload value and pulse width......................................... 277 Selecting a count clock for 8/16-bit PPG ............ 278 PPG0 operation mode control register PPG0 operation mode control register (PPGC8) ......................................................... 269 PPG1 operation mode control register PPG1 operation mode control register (PPGC9) ......................................................... 271 PPG8/9 PPG8/9 clock select register (PPG89) ................ 273 PPG8/9 clock select register PPG8/9 clock select register (PPG89) ................ 273 PPGC8 PPG0 operation mode control register (PPGC8) ......................................................... 269 PPGC9 PPG1 operation mode control register (PPGC9) ......................................................... 271 Prefix instructions Restrictions on interrupt disable instructions and prefix instructions ................................. 46 Prescaler Clock prescaler settings .................................... 401 Prescaler settings ............................................. 431 PRLH Reload register (PRLL/PRLH) .......................... 275 PRLL Reload register (PRLL/PRLH) .......................... 275 Processor status Processor status (PS) .......................................... 37 Product overview Product overview ................................................. 2 Program address detection registers Program address detection registers (PADR0 to PADR5)............................ 471 Program counter Program counter (PC)......................................... 40 Programmable restart Programmable restart ....................................... 355 Protection function Converted-data protection function .................... 319 Example of flow of data protection function (when EI2OS is used) .................................... 320 PS Processor status (PS) .......................................... 37 PSCCR Configuration of the PLL/Subclock Control Register (PSCCR) ............................................ 112 PUCR Block Diagram of Pull-up Control Register (PUCR) ......................................................... 194 INDEX Pull-up Control Register (PUCR) ...................... 194 Pull-up Control Register Block Diagram of Pull-up Control Register (PUCR) .......................................................... 194 Pull-up Control Register (PUCR) ...................... 194 Pulse width Relationship between 8/16-bit PPG reload value and pulse width ......................................... 277 R RAM RAM area ......................................................... 26 RCR Reception complete register (RCR).................... 441 RDR Reception and transmission data registers (RDR/TDR) .......................................................... 337 Ready Function Ready Function................................................ 183 Receive and transmit error counters Receive and transmit error counters (RTEC)....... 429 Receive and transmit error counters (RTEC) contents .......................................................... 429 Receive overrun Receive overrun............................................... 458 Receive overrun register Receive overrun register (ROVRR) ................... 443 Received message Storing received message.................................. 457 Reception Completing reception ....................................... 458 Procedure for reception by message buffer (x) .......................................................... 463 Processing for reception of data frame and remote frame ................................................. 458 Reception flowchart of the CAN controller......... 459 Reception interrupt generation and flag set timing .......................................................... 347 Reception and transmission data registers Reception and transmission data registers (RDR/TDR) .......................................................... 337 Reception complete register Reception complete register (RCR).................... 441 Reception interrupt enable register Reception interrupt enable register (RIER) ......... 444 Register 16-bit reload timer register................................ 246 8/16-bit PPG registers....................................... 268 External Memory Access Registers.................... 174 I/O port registers .............................................. 189 I2C Interface registers....................................... 382 Interrupt causes,interrupt vectors,and interrupt control registers ............................................. 612 LIN-UART registers ........................................ 330 Output compare register ....................................224 Registers for A/D converter ...............................299 Registers List .....................................................79 Ten bit address mask register (ITMK).................395 Watch Timer Register .......................................258 Register bank Register bank .....................................................41 Register bank pointer Register bank pointer (RP) ..................................38 Reload register Register layout of 16-bit timer register (TMR)/16-bit reload register (TMRLR)......................250 Reload register (PRLL/PRLH) ...........................275 Reload timer 16-bit reload timer register ................................246 Internal clock operation of 16-bit reload timer ..........................................................251 Outline of 16-bit reload timer (with event count function) .............................................244 Output pin functions of 16-bit reload timer..........254 Underflow operation of 16-bit reload timer .........253 Reload value Relationship between 8/16-bit PPG reload value and pulse width..........................................277 Remote frame Processing for reception of data frame and remote frame..................................................458 Remote frame receiving wait register Remote frame receiving wait register (RFWTR) ..........................................................437 Remote request receiving register Remote request receiving register (RRTRR)........442 Reset Causes of a reset...............................................122 Notes about reset cause bits ...............................130 Oscillation stabilization wait and reset state.........125 Overview of reset operation ...............................127 Reset cause bits ................................................129 Reset causes and oscillation stabilization wait times ..........................................................124 Status of pins during a reset ...............................132 RFWTR Remote frame receiving wait register (RFWTR) ..........................................................437 RIER Reception interrupt enable register (RIER)..........444 ROM mirroring module Block diagram of ROM mirroring module ..........478 ROM mirroring register ROM mirroring register (ROMM) ......................479 ROMM ROM mirroring register (ROMM) ......................479 ROVRR Receive overrun register (ROVRR) ....................443 625 INDEX RP Register bank pointer (RP) .................................. 38 RRTRR Remote request receiving register (RRTRR) ....... 442 RST RST and RY/BY timing .................................... 607 RTEC Receive and transmit error counters (RTEC) ....... 429 Receive and transmit error counters (RTEC) contents .......................................................... 429 RY/BY RST and RY/BY timing .................................... 607 RY/BY timing during writing/erasing................. 607 S Sample output waveform Sample output waveform when CMOD[1:0]="00B" .......................................................... 230 SCC SCC,MSS and INT bit competition .................... 390 SCR Serial control register (SCR).............................. 331 Sector configuration Sector configuration of the 1M-bit flash memory .......................................................... 483 Sector erase Chip erase/sector erase command sequence ........ 605 Sector erase timer Flag Sector erase timer Flag (DQ3) ........................... 497 Sector protect Enable sector protect/verify sector protect .......... 608 Temporary sector protect cancellation ................ 609 Serial clock input frequency Oscillating clock frequency and serial clock input frequency ........................................... 520 Serial control register Serial control register (SCR).............................. 331 Serial mode register Serial mode register (SMR) ............................... 333 Serial programming connection Basic configuration of MB90F352/C(S) serial programming connection..................... 518 Example of serial programming connection (power supplied from the programmer)............. 523 Example of serial programming connection (user power supply used).............................. 521 Serial status register Serial status register (SSR)................................ 335 Setting Register Setting Register (ADSR)................................... 306 Seven bit slave address mask register Seven bit slave address mask register (ISMK) ..... 397 Seven bit slave address mask register contents .... 398 626 Seven bit slave address register Seven bit slave address register ......................... 397 Seven bit slave address register contents ............ 397 Signal mode Signal mode .................................................... 358 Single Chip Mode Status of Each Pin in the Single Chip Mode........ 158 Single mode Example of starting of EI2OS in single mode...... 313 Single mode 1/2............................................... 310 Slave Addressing slaves ............................................ 404 LIN-master-slave communication function......... 373 Master-slave communication function................ 370 UART as slave device ...................................... 375 Slave address Slave address detection..................................... 403 Slave address masking...................................... 404 Sleep Mode Release of Sleep Mode ..................................... 146 Switching to Sleep Mode .................................. 146 SMR Serial mode register (SMR)............................... 333 Software interrupt Software interrupt operation................................ 67 Software interrupts....................................... 51, 67 Structure of software interrupts ........................... 67 Special registers Special registers................................................. 32 SSP User stack pointer (USP) and system stack pointer (SSP) ................................................... 36 SSR Serial status register (SSR)................................ 335 Standby Mode Operation Status during Standby Mode .............. 144 Standby Mode ................................................. 135 Switching to a Standby Mode and Interrupt ........ 163 Start conditions Start conditions................................................ 403 Status Change Diagram Status Change Diagram .................................... 156 Stop conditions Stop conditions ................................................ 403 Stop Mode Example of starting of EI2OS in stop mode ........ 317 Stop mode ....................................................... 310 Switching to the Stop Mode .............................. 153 Subclock Mode Main Clock Mode,PLL Clock Mode and subclock Mode ................................................. 114 Suggested division ratios Suggested division ratios for different machine speeds and baud rates..................................... 353 INDEX Switching Switching to the Stop Mode .............................. 153 Switching to the Watch Mode ........................... 151 Synchronization Synchronization methods.................................. 358 Synchronous mode Operation in synchronous mode (operation mode 2) .......................................................... 361 System configuration System configuration example of the address match detection function ............................... 474 System stack pointer User stack pointer (USP) and system stack pointer (SSP) ................................................... 36 T TBTC Timebase timer control register (TBTC)............. 201 TCANR Transmission cancel register (TCANR) .............. 438 TCR Transmission complete register (TCR) ............... 439 TDR Reception and transmission data registers (RDR/TDR) .......................................................... 337 Temporary sector protect Temporary sector protect cancellation................ 609 Ten bit address mask Ten bit address mask register (ITMK)................ 395 Ten bit address mask register Ten bit address mask register (ITMK) contents .......................................................... 395 Ten bit slave address register Ten bit slave address register (ITBA) ................. 394 Ten bit slave address register (ITBA) contents .... 394 TIER Transmission interrupt enable register (TIER)..... 440 Timebase counter Timebase counter ............................................. 203 Timebase counter clear ..................................... 203 Timebase timer Block diagram of timebase timer ....................... 200 Outline of timebase timer.................................. 200 Timebase timer control register Timebase timer control register (TBTC)............. 201 Timebase Timer Mode Release of Timebase Timer Mode...................... 149 Switching to the Timebase Timer Mode ............. 149 Timer control register Register contents of timer control register (TMCSR) .......................................................... 247 Register layout of timer control register (TMCSR) .......................................................... 247 Timer register Register layout of 16-bit timer register (TMR)/16-bit reload register (TMRLR)......................250 Timing limit exceeded flag Timing limit exceeded flag (DQ5)......................496 TMCSR Register contents of timer control register (TMCSR) ..........................................................247 Register layout of timer control register (TMCSR) ..........................................................247 TMR Register layout of 16-bit timer register (TMR)/16-bit reload register (TMRLR)......................250 TMRLR Register layout of 16-bit timer register (TMR)/16-bit reload register (TMRLR)......................250 Toggle bit Toggle bit ........................................................606 Toggle bit flag Toggle bit flag (DQ6) .......................................495 Toggle bit-2 flag Toggle bit-2 flag (DQ2) ....................................498 Transition Clock Mode Transition......................................114 Transmission Canceling a transmission request from the CAN controller ............................................455 Completing transmission of the CAN controller ..........................................................455 Procedure for transmission by message buffer (x) ..........................................................461 Starting transmission of the CAN controller ........455 Transmission flowchart of the CAN controller ..........................................................456 Transmission interrupt generation and flag set timing ..........................................................348 Transmission interrupt request generation timing ..........................................................348 Transmission cancel register Transmission cancel register (TCANR)...............438 Transmission complete register Transmission complete register (TCR)................439 Transmission interrupt enable register Transmission interrupt enable register (TIER) .....440 Transmission request register Transmission request register (TREQR)..............435 Transmission RTR register Transmission RTR register (TRTRR) .................436 TREQR Transmission request register (TREQR)..............435 TRTRR Transmission RTR register (TRTRR) .................436 627 INDEX U UART Notes on using UART....................................... 376 Operation of UART.......................................... 357 UART as master device .................................... 374 UART as slave device....................................... 375 UART baud rate selection ................................. 350 UART direct pin access .................................... 367 UART EI2OS functions .................................... 346 UART interrupt and EI2OS ............................... 324 UART operation modes .................................... 323 Undefined instruction Exception due to execution of an undefined instruction ............................................................ 96 Execution of an undefined instruction .................. 96 Underflow operation Underflow operation of 16-bit reload timer ......... 253 User power supply Example of serial programming connection (user power supply used).............................. 521 628 User stack pointer User stack pointer (USP) and system stack pointer (SSP) ................................................... 36 USP User stack pointer (USP) and system stack pointer (SSP) ................................................... 36 W Watch Mode Switching to the Watch Mode ........................... 151 Watch Timer Block Diagram of Watch Timer ........................ 258 Watch Timer ................................................... 261 Watch Timer Register ...................................... 258 Watch Timer Control Register Watch Timer Control Register (WTC) ............... 259 Watchdog timer Setting Operation Clock of Watchdog timer ....... 261 Watchdog timer block diagram.......................... 206 WE control Write,data polling,read (WE control) ................. 603 WTC Watch Timer Control Register (WTC) ............... 259 CM44-10132-1E FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL F2MC-16LX 16-BIT MICROCONTROLLER MB90350 Series HARDWARE MANUAL March 2005 the first edition Published FUJITSU LIMITED Edited Business Promotion Dept. Electronic Devices