FUJITSU MICROELECTRONICS CM44-10111-3E CONTROLLER MANUAL 2 TM F MC -16LX 16-BIT MICROCONTROLLER MB90580C Series HARDWARE MANUAL 2 TM F MC -16LX 16-BIT MICROCONTROLLER MB90580C Series HARDWARE MANUAL The information for microcontroller supports is shown in the following homepage. Be sure to refer to the "Check Sheet" for the latest cautions on development. "Check Sheet" is seen at the following support page "Check Sheet" lists the minimal requirement items to be checked to prevent problems beforehand in system development. http://edevice.fujitsu.com/micom/en-support/ FUJITSU MICROELECTRONICS LIMITED PREFACE ■ Objective and Intended Reader Thank you for your continued preference for Fujitsu semiconductor products. The MB90580C Series was developed as general-purpose version of the F2MC-16LX Series, which is a proprietary 16-bit single-chip microcontroller that supports application-specific ICs (ASICs). This manual is intended for engineers who design products using this semiconductor. Consult this manual for information on the functions and operations of the MB90580C Series. ■ Trademark F2MC is the abbreviation of FUJITSU Flexible Microcontroller. Other system and product names in this manual are trademarks of respective companies or organizations. The symbols ™ and ® are sometimes omitted in this manual. ■ Structure of This Manual This manual consists of the following 26 chapters: Chapter 1 "OVERVIEW" This chapter describes the configuration of the MB90580C series models and gives an outline of each model. Chapter 2 "CPU" This chapter describes the functions and operation of the CPU. Chapter 3 "INTERRUPTS" This chapter describes the features and operation of interrupts. Chapter 4 "GENERATING AND RESETTING CLOCKS" This chapter describes clock and reset functions and operations. Chapter 5 "LOW-POWER CONSUMPTION CONTROL CIRCUIT" This chapter describes the functions and operation of the low-power consumption control circuit. Chapter 6 "MEMORY ACCESS MODES" This chapter describes the functions and operations of memory access modes. Chapter 7 "I/O PORTS" This chapter describes the functions and operations of I/O ports. Chapter 8 "TIME-BASED TIMER" This chapter describes the functions and operations of the time-based timer. Chapter 9 "WATCHDOG TIMER" This chapter describes the functions and operations of the watchdog timer. i Chapter 10 "WATCH TIMER" This chapter describes the functions and operations of the watch timer. Chapter 11 "PWC TIMER" This chapter describes the functions and operations of the PWC timer. Chapter 12 "16-BIT I/O TIMER" This chapter describes the functions and operations of the 16-bit I/O timer. Chapter 13 "16-BIT RELOAD TIMER (WITH THE EVENT COUNT FUNCTION)" This chapter gives an overview of the 16-bit reload timer (with the event count function) and explains its functions. Chapter 14 "8/16-BIT PPG" This chapter describes the function and operation of the 8/16-bit PPG. Chapter 15 "DTP/EXTERNAL INTERRUPT CIRCUIT" This chapter describes the function and operation of the DTP/external interrupt circuit. Chapter 16 "DELAYED INTERRUPT GENERATING MODULE" This chapter describes the function and operation of the delayed interrupt generating module. Chapter 17 "A/D CONVERTER" This chapter describes the functions and provides an overview of the A/D converter. Chapter 18 "D/A CONVERTER" This chapter explains the functions and operation of the D/A converter. Chapter 19 "COMMUNICATION PRESCALER REGISTER" This chapter describes the functions and overview of the communication prescaler register. Chapter 20 "UART" This chapter describes the UART functions and operations. Chapter 21 "IEBusTM CONTROLLER" This chapter describes the functions and operation of the IEBusTM controller. Chapter 22 "CLOCK MONITOR FUNCTION" This chapter describes the functions and operation of the clock monitor. Chapter 23 "ADDRESS MATCH DETECTION FUNCTION" This chapter describes the address match detection function and operation. Chapter 24 "ROM MIRROR FUNCTION SELECTION MODULE" This chapter describes the functions and operations of the ROM mirror function selection module. Chapter 25 "1M-BIT FLASH MEMORY" This chapter describes the functions and operations of the 1M-bit flash memory. Chapter 26 "EXAMPLE OF MB90F583C/CA SERIAL PROGRAMMING CONNECTION" This chapter provides examples of serial programming connection using the flash microcomputer programmer manufactured by YDC corporation. ii Appendix The appendix describes the I/O map and instructions. • • • • • • • The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any thirdparty's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Copyright ©2004-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved. iii iv CONTENTS CHAPTER 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 OVERVIEW ................................................................................................... 1 Features ................................................................................................................................................ 2 Models Available .................................................................................................................................... 5 Block Diagram for MB90580C Series .................................................................................................... 6 Package Dimensions ............................................................................................................................. 7 Pin Layout .............................................................................................................................................. 9 Pin Functions ....................................................................................................................................... 11 I/O Circuit Formats ............................................................................................................................... 19 Precautions on Handling of Device ...................................................................................................... 22 CHAPTER 2 CPU ............................................................................................................. 27 2.1 Memory Space ..................................................................................................................................... 28 2.2 Addressing ........................................................................................................................................... 29 2.2.1 Allocating Multiple-byte Data in a Memory Space .......................................................................... 32 2.3 Dedicated Registers ............................................................................................................................ 33 2.3.1 Accumulator (A) .............................................................................................................................. 35 2.3.2 User Stack Pointer (USP) and System Stack Pointer (SSP) .......................................................... 37 2.3.3 Processor Status (PS) .................................................................................................................... 38 2.3.4 Program Counter (PC) .................................................................................................................... 41 2.3.5 Direct Page Register (DPR) ........................................................................................................... 42 2.3.6 Bank Registers ............................................................................................................................... 43 2.4 General-purpose Registers .................................................................................................................. 44 2.5 Prefix Codes ........................................................................................................................................ 46 2.6 Interrupt Suppression Instructions and Prefix Codes .......................................................................... 49 2.7 Notes on Use of the DIV A, Ri and DIVW A, RWi Instructions ............................................................ 51 CHAPTER 3 INTERRUPTS .............................................................................................. 53 3.1 Overview of Interrupts .......................................................................................................................... 54 3.2 Interrupt Causes .................................................................................................................................. 55 3.3 Interrupt Vectors .................................................................................................................................. 57 3.4 Hardware Interrupts ............................................................................................................................. 59 3.4.1 Operation of Hardware Interrupts ................................................................................................... 62 3.4.2 Operating Flow for Hardware Interrupts ......................................................................................... 64 3.4.3 Example of Procedure for Using Hardware Interrupts .................................................................... 65 3.5 Software Interrupts .............................................................................................................................. 66 3.6 Expanded Intelligent I/O Service (EI2OS) ............................................................................................ 68 3.6.1 Interrupt Control Register (ICR) ...................................................................................................... 70 3.6.2 Expanded Intelligent I/O Service Descriptor (ISD) ......................................................................... 73 3.6.3 Operation of the Expanded Intelligent I/O Service (EI2OS) ............................................................ 77 3.6.4 Execution Time of the Expanded Intelligent I/O Service (EI2OS) ................................................... 79 3.7 Exceptions because of Executing Undefined Instructions ................................................................... 81 CHAPTER 4 4.1 GENERATING AND RESETTING CLOCKS .............................................. 83 Clock Generator ................................................................................................................................... 84 v 4.2 4.3 Reset Causes ..................................................................................................................................... 85 Operation after a Reset is Released ................................................................................................... 87 CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT ............................... 91 5.1 Overview of the Low-power Consumption Control Circuit .................................................................. 92 5.2 Low-power Consumption Mode Control Register (LPMCR) ............................................................... 95 5.3 Clock Selection Register (CKSCR) ..................................................................................................... 97 5.4 Operation of the Low-power Consumption Control Circuit ................................................................ 100 5.4.1 Sleep Mode .................................................................................................................................. 102 5.4.2 Pseudo Watch Mode ................................................................................................................... 103 5.4.3 Watch Mode ................................................................................................................................. 104 5.4.4 Stop Mode ................................................................................................................................... 105 5.4.5 Hardware Standby Mode ............................................................................................................. 106 5.5 Intermittent CPU Operation Function ................................................................................................ 107 5.6 Setting the Oscillation Stabilization Time for the Main Clock ............................................................ 108 5.7 Switching the Machine Clock ............................................................................................................ 109 5.8 Status Transition ............................................................................................................................... 113 5.9 Status Transition Diagrams for Low Power-Consumption Modes .................................................... 119 CHAPTER 6 MEMORY ACCESS MODES .................................................................... 127 6.1 Memory Access Mode Overview ...................................................................................................... 6.1.1 Mode Pins .................................................................................................................................... 6.1.2 Mode Data ................................................................................................................................... 6.1.3 Memory Space for Each Bus Mode ............................................................................................. 6.2 External Memory Access (External Bus Pin Control Circuit) ............................................................ 6.2.1 Registers for External Memory Access (External Bus Pin Control Circuit) .................................. 6.2.2 Automatic Ready Function Selection Register (ARSR) ............................................................... 6.2.3 External Address Output Control Register (HACR) ..................................................................... 6.2.4 Bus Control Signal Selection Register (ECSR) ............................................................................ 6.3 Operation of the External Memory Access Control Signals .............................................................. 6.3.1 Ready Function ............................................................................................................................ 6.3.2 Hold Function ............................................................................................................................... CHAPTER 7 I/O PORTS ................................................................................................ 147 7.1 I/O Port Overview .............................................................................................................................. 7.2 I/O Port Block Diagram ..................................................................................................................... 7.3 I/O Port Registers ............................................................................................................................. 7.3.1 Port Data Registers (PDRx) ......................................................................................................... 7.3.2 Port Data Direction Registers (DDRx) ......................................................................................... 7.3.3 Port 4 Output Pin Register (ODR4) .............................................................................................. 7.3.4 Input Pull-up Resistor Setting Registers (RDR0, RDR1, and RDR6) .......................................... 7.3.5 Port 5 Analog Input Enable Register (ADER) .............................................................................. CHAPTER 8 8.1 8.2 8.3 128 129 130 131 134 135 136 138 139 142 144 146 148 149 151 153 154 156 157 158 TIME-BASED TIMER ................................................................................ 159 Overview of the Time-Based Timer .................................................................................................. 160 Time-Based Timer Control Register (TBTC) ..................................................................................... 162 Time-Based Timer Operations .......................................................................................................... 164 vi CHAPTER 9 9.1 9.2 9.3 WATCHDOG TIMER ................................................................................. 165 Overview of the Watchdog Timer ...................................................................................................... 166 Watchdog Timer Control Register (WDTC) ....................................................................................... 168 Watchdog Timer Operations .............................................................................................................. 171 CHAPTER 10 WATCH TIMER ......................................................................................... 173 10.1 Overview of the Watch Timer ............................................................................................................ 174 10.2 Watch Timer Control Register (WTC) ................................................................................................ 176 10.3 Watch Timer Operations .................................................................................................................... 178 CHAPTER 11 PWC TIMER .............................................................................................. 179 11.1 Overview of the PWC Timer .............................................................................................................. 180 11.2 PWC Timer Block Diagram ................................................................................................................ 181 11.3 PWC Timer Registers ........................................................................................................................ 182 11.3.1 PWC control status register (PWCSR) ......................................................................................... 184 11.3.2 PWC data buffer register (PWCR) ................................................................................................ 190 11.3.3 Division rate control register (DIVR) ............................................................................................. 191 11.3.4 PWC noise filter register (RNCR) ................................................................................................. 192 11.4 PWC Timer Operations ...................................................................................................................... 194 11.4.1 Count clock selection .................................................................................................................... 197 11.4.2 Operation mode selection ............................................................................................................. 198 11.4.3 Starting and stopping the timer and pulse-width measurement and clearing the timer ................ 200 11.5 Details of Timer Mode Operation ....................................................................................................... 202 11.6 Flowchart of Timer Mode Operation .................................................................................................. 204 11.7 Details of Pulse Width Measurement Mode Operation ...................................................................... 205 11.7.1 Measurement mode and measurement operation ........................................................................ 208 11.7.2 Flowchart of pulse-width measurement operation ........................................................................ 211 11.8 Notes on Handling the PWC Timer .................................................................................................... 212 CHAPTER 12 16-BIT I/O TIMER ...................................................................................... 215 12.1 Overview of the 16-Bit I/O Timer ....................................................................................................... 216 12.2 16-Bit I/O Timer Block Diagram ........................................................................................................ 218 12.3 16-Bit I/O Timer Registers ................................................................................................................. 219 12.3.1 16-bit Free-run Timer .................................................................................................................... 221 12.3.2 Output Compare ........................................................................................................................... 225 12.3.3 Input Capture ................................................................................................................................ 229 12.4 16-Bit Free-Run Timer Operations .................................................................................................... 231 12.5 16-Bit Output Compare Operations ................................................................................................... 233 12.6 16-Bit Input Capture Operations ........................................................................................................ 236 CHAPTER 13 16-BIT RELOAD TIMER (WITH THE EVENT COUNT FUNCTION) ........ 239 13.1 Overview of the 16-Bit Reload Timer (with the Event Count Function) ............................................. 240 13.2 Registers of the 16-Bit Reload Timer (with the Event Count Function) ............................................. 241 13.2.1 Timer Control Status Register (TMCSR) ...................................................................................... 242 13.2.2 16-bit Timer Register (TMR) and 16-bit Reload Register (TMRLR) ............................................. 245 13.3 Clock Operations ............................................................................................................................... 246 13.4 Underflow Operation .......................................................................................................................... 247 13.5 I/O Pin Functions (for the Internal Clock Mode) ................................................................................. 248 vii 13.6 Counter Operation Statuses ............................................................................................................. 250 CHAPTER 14 8/16-BIT PPG ............................................................................................ 251 14.1 Overview of the 8/16-Bit PPG ........................................................................................................... 14.2 Block Diagrams of the 8/16-Bit PPG ................................................................................................. 14.3 Registers in the 8/16-Bit PPG ........................................................................................................... 14.3.1 PPG0 Operation Mode Control Register (PPGC0) ...................................................................... 14.3.2 PPG1 Operation Mode Control Register (PPGC1) ...................................................................... 14.3.3 PPG0/1 Output Pin Control Register (PPGOE) ........................................................................... 14.3.4 Reload Registers (PRLL/PRLH) .................................................................................................. 14.4 8/16-Bit PPG Operation .................................................................................................................... 14.4.1 8/16-bit PPG Operation Modes .................................................................................................... 14.4.2 PPG Output Operation ................................................................................................................. 14.4.3 Selecting a Count Clock .............................................................................................................. 14.4.4 Controlling Pulse Output on Pins ................................................................................................. 14.4.5 Write Timing for the Reload Registers ......................................................................................... 252 253 255 256 258 261 263 264 266 267 269 270 271 CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT .................................................. 273 15.1 15.2 15.3 15.4 Overview of the DTP/External Interrupt Circuit ................................................................................. Registers in the DTP/External Interrupt Circuit ................................................................................. Operation of DTP/External Interrupt Circuit ...................................................................................... Notes on Using the DTP/External Interrupt Circuit ........................................................................... 274 276 278 281 CHAPTER 16 DELAYED INTERRUPT GENERATING MODULE .................................. 283 16.1 Overview of the Delayed Interrupt Generating Module ..................................................................... 284 16.2 Operation of the Delayed Interrupt Generating Module .................................................................... 285 CHAPTER 17 A/D CONVERTER ..................................................................................... 287 17.1 Overview of the A/D Converter ......................................................................................................... 17.2 A/D Converter Block Diagram ........................................................................................................... 17.3 Resisters of the A/D Converter ......................................................................................................... 17.3.1 Control Status Registers (ADCS1 and ADCS2) ........................................................................... 17.3.2 Data Register (ADCR1 and ADCR2) ........................................................................................... 17.4 Operation of A/D Converter .............................................................................................................. 17.4.1 Example of EI2OS Activation in Single Mode .............................................................................. 17.4.2 Example of EI2OS Activation in Successive Mode ...................................................................... 17.4.3 Example of EI2OS Activation in Pause Mode .............................................................................. 17.5 Conversion Data Protection Function ............................................................................................... 288 290 291 292 297 299 301 303 305 307 CHAPTER 18 D/A CONVERTER ..................................................................................... 309 18.1 Overview of D/A Converter ............................................................................................................... 310 18.2 D/A Converter Registers ................................................................................................................... 312 18.3 Operation of D/A Converter .............................................................................................................. 314 CHAPTER 19 COMMUNICATION PRESCALER REGISTER ......................................... 315 19.1 Overview of Communication Prescaler Register .............................................................................. 316 19.2 Operation of Communication Prescaler Register .............................................................................. 318 viii CHAPTER 20 UART ......................................................................................................... 319 20.1 Overview of UART ............................................................................................................................. 320 20.2 UART Block Diagram ......................................................................................................................... 321 20.3 UART Registers ................................................................................................................................. 322 20.3.1 Serial Mode Register (SMR0 to 4) ................................................................................................ 323 20.3.2 Serial Control Register (SCR0 to 4) ............................................................................................ 326 20.3.3 Serial Input Data Register (SIDR0 to 4) and Serial Output Data Register (SODR0 to 4) ............. 329 20.3.4 Serial Status Register (SSR0 to 4) ............................................................................................... 330 20.4 UART Operations .............................................................................................................................. 333 20.4.1 UART Clock Selection .................................................................................................................. 334 20.4.2 Asynchronous (Start-stop Synchronous) Mode ............................................................................ 336 20.4.3 CLK-synchronous Mode ............................................................................................................... 338 20.4.4 Occurrence of Interrupt and Flag Setting Timing .......................................................................... 340 20.5 Application of UART (During Operation in Mode 1) ........................................................................... 343 CHAPTER 21 IEBusTM CONTROLLER ......................................................................... 345 21.1 Overview of IEBusTM Controller ....................................................................................................... 346 21.2 Block Diagram for IEBusTM Controller .............................................................................................. 347 21.3 Registers of IEBusTM Controller ....................................................................................................... 348 21.3.1 Local Address Set Registers (MAWH and HAWL) ....................................................................... 351 21.3.2 Slave Address Set Registers (SAWH and SAWL) ....................................................................... 352 21.3.3 Broadcast Control Bit Set Register (DCWR) ................................................................................ 353 21.3.4 Text Length Bit Set Register (DEWR) .......................................................................................... 355 21.3.5 Command Register (Higher 8 Bits) (CMRH) ................................................................................ 356 21.3.6 Command Register (Lower 8 Bits) (CMRL) .................................................................................. 358 21.3.7 Status Register (Higher 8 Bits) (STRH) ........................................................................................ 361 21.3.8 Status Register (Lower 8 Bits) (STRL) ......................................................................................... 363 21.3.9 Lock Read Registers (LRRH and LRRL) ...................................................................................... 365 21.3.10 Master Address Read Registers (MARH and MARL) ................................................................... 366 21.3.11 Broadcast Control Bit Read Register (DCRR) .............................................................................. 367 21.3.12 Text Length Bit Read Register (Lower 8 Bits) (DERR) ................................................................. 368 21.3.13 Read Data Buffer (RDB) ............................................................................................................... 369 21.3.14 Write Data Buffer (WDB) .............................................................................................................. 370 21.4 IEBusTM Transmission Control ......................................................................................................... 371 21.5 IEBusTM Reception Control .............................................................................................................. 374 21.6 Communication Control Status .......................................................................................................... 376 21.7 Examples of the Flows of Main and Interrupt Processing Routines for IEBusTM Controller ............. 379 21.7.1 Initialization Routine ..................................................................................................................... 380 21.7.2 Master Transmission Routine ....................................................................................................... 381 21.7.3 Slave Data Transmission Routine ................................................................................................ 382 21.7.4 Master Reception Routine ............................................................................................................ 383 21.8 IEBusTM Controller Operation at Transmission ................................................................................ 386 21.9 IEBusTM Protocol Operation ............................................................................................................. 390 21.10 Transmission Protocol ....................................................................................................................... 393 21.10.1 Header in Transmission Protocol Signal Format .......................................................................... 394 21.10.2 Master Address Field in Transmission Protocol Signal Format .................................................... 395 21.10.3 Slave Address Field in Transmission Protocol Signal Format ...................................................... 396 21.10.4 Control Field in Transmission Protocol Signal Format ................................................................. 397 ix 21.10.5 Text Length Field ......................................................................................................................... 21.10.6 Data Field .................................................................................................................................... 21.10.7 Parity Bit ...................................................................................................................................... 21.10.8 Acknowledgment Bit .................................................................................................................... 21.11 Transmission Data ............................................................................................................................ 21.12 Bit Format ......................................................................................................................................... 398 399 400 401 403 407 CHAPTER 22 CLOCK MONITOR FUNCTION ................................................................ 409 22.1 Overview of the Clock Monitor Functions ......................................................................................... 410 22.2 Clock Output Permission Register (CLKR) ....................................................................................... 411 CHAPTER 23 ADDRESS MATCH DETECTION FUNCTION .......................................... 413 23.1 23.2 23.3 23.4 Overview of the Address Match Detection Function ......................................................................... Registers of the Address Match Detection Function ......................................................................... Operation of the Address Match Detection Function ........................................................................ Example of the Address Match Detection Function .......................................................................... 414 415 417 418 CHAPTER 24 ROM MIRROR FUNCTION SELECTION MODULE ................................. 421 24.1 Overview of the ROM Mirror Function Selection Module .................................................................. 422 24.2 ROM Mirror Function Selection Register (ROMM) ........................................................................... 423 CHAPTER 25 1M-BIT FLASH MEMORY ........................................................................ 425 25.1 Overview of the 1M-Bit Flash Memory .............................................................................................. 25.2 Sector Configuration of the Flash Memory ....................................................................................... 25.3 Flash Memory Control Status Register (FMCS) ............................................................................... 25.4 Activating the Automatic Algorithm of the Flash Memory ................................................................. 25.5 Confirming the Automatic Algorithm Execution Status ..................................................................... 25.5.1 Data Polling Flag (DQ7) ............................................................................................................... 25.5.2 Toggle Bit Flag (DQ6) .................................................................................................................. 25.5.3 Timing Limit Excess Flag (DQ5) .................................................................................................. 25.5.4 Sector Deletion Timer Flag (DQ3) ............................................................................................... 25.5.5 Toggle Bit 2 Flag (DQ2) ............................................................................................................... 25.6 Detailed Explanations of Flash Memory Writing and Deletion .......................................................... 25.6.1 Setting the Flash Memory in the Read or Reset Status ............................................................... 25.6.2 Writing Data in the Flash Memory ................................................................................................ 25.6.3 Deleting all Data Items from the Flash Memory (Chip Deletion) .................................................. 25.6.4 Deleting any Data Item from the Flash Memory (Sector Deletion) .............................................. 25.6.5 Temporarily Stopping the Sector Deletion from the Flash Memory ............................................ 25.6.6 Restarting the Flash Memory Sector Deletion ............................................................................. 25.7 Example of the 1M-Bit Flash Memory Program ................................................................................ 426 427 428 430 432 434 436 438 439 440 442 443 444 446 447 449 450 451 CHAPTER 26 EXAMPLE OF MB90F583C/CA SERIAL PROGRAMMING CONNECTION ................................................................................................................... 457 26.1 26.2 26.3 26.4 Basic Configuration of MB90F583C/CA Serial Programming Connection ........................................ 458 Example of Serial Programming Connection (When User Power Supply Is Used) .......................... 462 Example of Serial Programming Connection (When Power is Supplied from a Programmer) ......... 464 Example of Minimum Connection with the Flash Microcomputer Programmer (When User Power Supply is Used) ............................................................................................................................................. 466 x 26.5 Example of Minimum Connection with the Flash Microcomputer Programmer (When Power is Supplied from a Programmer) .......................................................................................................................... 468 APPENDIX .......................................................................................................................... 471 APPENDIX A I/O Map ................................................................................................................................. 472 APPENDIX B Instructions ............................................................................................................................ 480 B.1 Instruction Types ............................................................................................................................. 481 B.2 Addressing ...................................................................................................................................... 482 B.3 Direct Addressing ............................................................................................................................ 484 B.4 Indirect Addressing ......................................................................................................................... 490 B.5 Execution Cycle Count .................................................................................................................... 498 B.6 Effective Address Field ................................................................................................................... 501 B.7 How to Read the Instruction List ..................................................................................................... 502 B.8 F2MC-16LX Instruction List ............................................................................................................. 505 B.9 Instruction Map ................................................................................................................................ 519 INDEX ................................................................................................................................. 541 xi xii Main changes in this edition Page 480 to 540 Changes (For details, refer to main body.) Changed the entire part of "APPENDIX B Instructions" The vertical lines marked in the left side of the page show the changes. xiii xiv CHAPTER 1 OVERVIEW This chapter describes the configuration of the MB90580C series models and gives an outline of each model. 1.1 "Features" 1.2 "Models Available" 1.3 "Block Diagram for MB90580C Series" 1.4 "Package Dimensions" 1.5 "Pin Layout" 1.6 "Pin Functions" 1.7 "I/O Circuit Formats" 1.8 "Precautions on Handling of Device" 1 CHAPTER 1 OVERVIEW 1.1 Features The MB90580C series is a Fujitsu’s general-purpose 16-bit microcontroller designed for the process control on products for private use and other equipment that require high-speed realtime processing. The MB90580C series inherits the AT architecture of the F2MC series as the instruction set and features additional instructions conforming to high-level language, extended addressing modes, reinforced multiplication and division instructions, and enhanced bit processing. Mounting of a 32-bit accumulator enables the MB90580C series to process long-word data. A built-in IEBusTM Controller simplifies communication with other devices. With these features, the MB90580C series matches component-type audio equipment and VTR systems. ■ Features of MB90580C Series ❍ Minimum execution time 62.5 ns at 4 MHz, 4 times multiplied (PLL clock multiplication system) ❍ Maximum memory space • 16 Mbyte • Linear bank access ❍ Instruction set optimized for use of controllers • Data types that can be handled: Bit, byte, word, and long word • Standard addressing modes: 23 modes • Reinforced high-accuracy arithmetic operations due to the use of 32-bit accumulator • Multiplication and division operations of signed numerics and extended RETI instructions ❍ Instruction set conforming to high-level language (C language) and multitask • Use of system stack pointer • Symmetry of instruction set and barrel shift instructions ❍ Program patch function (2-address pointer) ❍ Increase in execution speed with 4-byte queue ❍ Reinforced interrupt functions 2 • Programmable setting of eight priority levels • Eight external interrupt inputs 1.1 Features ❍ Data transfer functions independent of the CPU • Extended intelligent I/O service with up to 16 channels • Eight DTP request inputs ❍ Internal ROM • Flash ROM: 128 Kbytes • Mask ROM: 128 Kbytes (MB90583C/CA) or 64 Kbytes (MB90587C/CA) ❍ Internal RAM • Flash RAM: 6 Kbytes • Mask ROM: 6 Kbytes (MB90583C/CA) or 4 Kbytes (MB90587C/CA) ❍ General-purpose ports Up to 77 ports (including 22 ports allowing input pull-up resistance setting and 8 ports allowing output open-drain setting) ❍ IEBusTM Controller* Three data transfer rates available for selection: • Mode 0: 3.9 kbps (16 bytes per frame) • Mode 1: 17.0 kbps (32 bytes per frame) • Mode 2: 26.0 kbps (128 bytes per frame) *: IEBusTM Controller is a trademark of NEC Corporation. ❍ A/D converter (RC successive approximation type): 8 channels • Resolution: 8 or 10 bits • Conversion time: 34.7 μs(minimum) at 12 MHz ❍ D/A converter: 2 channels • Resolution: 8 bits • Setting time: 12.5 μs ❍ UART: 5 channels ❍ 8/16-bit PPG: 1 channel PPG with mode switching function to switch between 8 bits by 2 channels and 16 bits by 1 channel ❍ 16-bit reload timer: 3 channels ❍ 16-bit PWC timer: 1 channel PWC timer with noise filter mounted and usable for pulse width counter ❍ 16-bit I/O timers • Input capture timer: 4 channels 3 CHAPTER 1 OVERVIEW • Output compare timer: 2 channels • Free-run timer: 1 channel ❍ Built-in clock generator ❍ Time base counter and watchdog timer: 18 bits ❍ Built-in clock monitor function ❍ Low power consumption modes • Sleep • Stop • Hardware standby mode • Intermittent CPU operation mode ❍ Package 4 • LQFP-100 • QFP-100 1.2 Models Available 1.2 Models Available Table 1.2-1 "MB90580C Series Models" lists the available models of the MB90580C series. Functions other than ROM and RAM capacity and clocks are common to all models. The MB90587C/CA does not have the IEBus TM Controller. ■ Models Available Table 1.2-1 MB90580C Series Models Item MB90583C MB90583CA MB90587C MB90587CA MB90F583C MB90F583CA MB90V580B ROM capacity Mask ROM Mask ROM 128 Kbytes 128 Kbytes Mask ROM Mask ROM 64 Kbytes 64 Kbytes FLASH ROM FLASH ROM 128 Kbytes 128 Kbytes RAM capacity 6 Kbytes 4 Kbytes 6 Kbytes 6 Kbytes 6 Kbytes Clock Two clocks One clock system system Two clocks One clock system system Two clocks system One clock system Two clocks system IEBusTM controller Available None Available Available Available Dedicated power supply for emulator* - 6 Kbytes Available - 4 Kbytes None - - - - - None *: Setting of DIP switch S2 for using the emulation pod MB2145-507. For details, see Section 2.7 "Dedicated Power Pin for Emulator" in the Hardware Manual for MB2145-507. Note: For the evaluation device, use the MB90V580B. Also, if the one clock system is used, equip X0A and X1A with clocks from the tool side. 5 CHAPTER 1 OVERVIEW 1.3 Block Diagram for MB90580C Series Figure 1.3-1 "Block Diagram for MB90580C Series" is a block diagram for the MB90580C series. ■ Block Diagram for MB90580C Series Figure 1.3-1 Block Diagram for MB90580C Series X0,X1 X0A,X1A 6 RST HST P10 to 17/AD08 to 15 P20 to 27/A16 to 23 8 CMOS I/O port A CMOS I/O port 4 UART 2ch 3 2 PWC timer 16bit 1ch P97/POT CMOS I/O port 9 Communication prescaler 1ch UART 1ch 2 External interrupt CMOS I/O port 8 2 UART 2ch 3 CMOS I/O port 5 TM IEBus Controller (*1) 8 2 P63,64/ PPG1,0 P65/CKOT SIN2,SOT2, SCK2/P60 to 62 P80-87/ IRQ0 to 7 P71,P72 CMOS I/O port 7 D/A converter (8 bits) 2ch 2 P73,P74 /DA00,DA01 DVRH DVSS Model for evaluation: MB90V580B This model does not have internal ROM. Internal RAM capacity is 6 Kbytes. Common internal peripherals are used. Package type is PGA-256C-A02. P00 to P07 (8 channels): Equipped with the registers usable as input pull-up resistors P10 to P17 (8 channels): Equipped with the registers usable as input pull-up resistors P60 to P65 (6 channels): Equipped with the registers usable as input pull-up resistors P40 to P47 (8 channels): Equipped with the registers usable as open drains *1: On the MB90587C/CA, the IEBusTM Controller is replaced with another controller and TX and RX are replaced with N and C, respectively. 6 2 3 Communication prescaler 2ch P94 to P95/ TOT1,2/ OUT0,1 P96/PWC CMOS I/O port 6 8 P90 to 92/ TIN0,2/ IN0 to 2 Noise filter Clock monitor A/D converter (8/10 dit) PA0 to 2 P93/ TOT0/ IN3 16bit reload timer 3ch 8/16 bit PPG 1ch 8 AVCC AVRH,L AVSS 3 3 I/O timers 16bit ICU 4ch 16bit OCU 2ch 16-bit free-run timer CMOS I/O port 2 Communication prescaler 2ch ADTG/P46 TX RX ROM CMOS I/O port 3 3 SIN1,SOT1,SCK1/ P40 to P42 3 SIN1,SOT1,SCK1/ P43 to P45 SIN4,SOT4,SCK4 P54-P56/ AN4-AN6 Interrupt controller CMOS I/O port 1 8 P47 P53/AN3,P57/AN7 RAM CMOS I/O port 0 8 P30/ALE P31/RD P32/WRL/WR P33/WRH P34/HRQ P35/HAK P36/RDY P37/CLK SIN3,SOT3,SCK3 P50-P52/ AN0-AN2 CPU F2MC16LX series core F2 MC16-LXbus P00 to 07/AD00 to 07 Clock controller Other terminals MOD2 to 0 C, VCC, VSS 1.4 Package Dimensions 1.4 Package Dimensions Figure 1.4-1 "Outside Dimensions of FPT-100P-M05 (LQFP-100)" shows the outside dimensions of the FPT-100P-M05 (LQFP-100) package. Figure 1.4-2 "Outside Dimensions of FPT-100P-M06 (QFP-100)" shows the outside dimensions of the FPT100P-M06 (QFP-100) package. Note that the dimensions shown below are reference dimensions. For formal dimensions of each package, contact us. ■ Outside Dimensions of FPT-100P-M05 Package Figure 1.4-1 Outside Dimensions of FPT-100P-M05 (LQFP-100) 100-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 14.0 × 14.0 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.65g Code (Reference) P-LFQFP100-14×14-0.50 (FPT-100P-M05) 100-pin plastic LQFP (FPT-100P-M05) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 16.00±0.20(.630±.008)SQ *14.00±0.10(.551±.004)SQ 75 51 76 50 0.08(.003) Details of "A" part +0.20 100 26 2 0.50(.020) C 2003 FUJITSU LIMITED F100007S-c-4-6 5 0.20±0.05 (.008±.002) 0.08(.003) M 0.10±0.10 (.004±.004) (Stand off) 0˚~8˚ "A" 1 +.008 1.50 –0.10 .059 –.004 (Mounting height) INDEX 0.145±0.055 (.0057±.0022) 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.25(.010) Dimensions in mm (inches). Note: The values in parentheses are reference values. 7 CHAPTER 1 OVERVIEW ■ Outside Dimensions of FPT-100P-M06 Package Figure 1.4-2 Outside Dimensions of FPT-100P-M06 (QFP-100) 100-pin plastic QFP Lead pitch 0.65 mm Package width × package length 14.00 × 20.00 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 3.35 mm MAX Code (Reference) P-QFP100-14×20-0.65 (FPT-100P-M06) 100-pin plastic QFP (FPT-100P-M06) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 23.90±0.40(.941±.016) * 20.00±0.20(.787±.008) 80 51 81 50 0.10(.004) 17.90±0.40 (.705±.016) *14.00±0.20 (.551±.008) INDEX Details of "A" part 100 1 30 0.65(.026) "A" C 8 0.25(.010) +0.35 3.00 –0.20 +.014 .118 –.008 (Mounting height) 0~8˚ 31 2002 FUJITSU LIMITED F100008S-c-5-5 0.32±0.05 (.013±.002) 0.13(.005) M 0.17±0.06 (.007±.002) 0.80±0.20 (.031±.008) 0.88±0.15 (.035±.006) 0.25±0.20 (.010±.008) (Stand off) Dimensions in mm (inches). Note: The values in parentheses are reference values. 1.5 Pin Layout 1.5 Pin Layout Figure 1.5-1 "Pin Layout of FTP-100P-M05" shows the pin layout of the FTP-100P-M05. Figure 1.5-2 "Pin Layout of FPT-100P-M06" shows the pin layout of the FTP-100P-M06. ■ Pin Layout of FTP-100P-M05 Vss Vcc Figure 1.5-1 Pin Layout of FTP-100P-M05 RST LQFP - 100 P31/RD Vss P32/WRL/WR P33/WRH P34/HRQ P35/HAK MB90580C series * * (TOP VIEW) FPT-100P-M05 Vcc HST Vss AVss AVcc DVss /SCK4 /SOT4 /SIN4 /SCK3 /SOT3 /SIN3 *: On the MB90587C/CA, RX and TX are replaced with N and C, respectively. 9 CHAPTER 1 OVERVIEW ■ Pin Layout of FPT-100P-M06 Vss Vcc Figure 1.5-2 Pin Layout of FPT-100P-M06 RST P31/RD Vss P32/WRL/WR P33/WRH QFP - 100 P94/TOT1/OUT0 MB90580C series P35/HAK (TOP VIEW) Vss P54/AN4/SIN4 P55/AN5/SOT4 P56/AN6/SCK4 AVss P50/AN0/SIN3 P51/AN1/SOT3 P52/AN2/SCK3 AVcc DVss FPT-100P-M06 *: On the MB90587C/CA, RX and TX are replaced with N and C, respectively. 10 * * 1.6 Pin Functions 1.6 Pin Functions Table 1.6-1 "Pin Functions" lists the pin functions of the MB90580C series. The alphabetic letters shown in the "Circuit format" column of Table 1.6-1 "Pin Functions" correspond to those shown in the "Classification" column of Table 1.7-1 "I/O Circuit Types". ■ Pin Functions Table 1.6-1 Pin Functions QFP LQFP Pin name Circuit format 82 80 X0 A Oscillation output pin 83 81 X1 A Oscillation output pin 52 50 HST C Hardware standby input pin 77 75 RST B Reset input pin P00 to P07 85 to 92 D (CMOS/H) 83 to 90 P10 to P17 1 to 8 D (CMOS/H) 91 to 98 General-purpose I/O ports Pull-up resistors can be assigned to these pins by the setting (RD07 to RD00 = 1) of pull-up resistor setting register (RDR0). (When these pins are set for output, the setting [D07 to D00 = 1] of register DDR0 is invalid.) In external bus mode, these pins operate (as AD00 to AD07) to input or output the lower byte of data or output the lower byte of address. AD00 to AD07 93 to 100 Function General-purpose I/O ports Pull-up resistors can be assigned to these pins by the setting (RD17 to RD10 = 1) of pull-up resistor setting register (RDR1). (When these pins are set for output, the setting [D17 to D10 = 1] of register DDR1 is invalid.) AD08 to AD15 In external bus mode with bus width of 16 bits, these pins operate (as AD08 to AD15) to input or output the higher byte of data or output the middle byte of address. P20 to P27 General-purpose I/O ports In external bus mode, these pins operate as pins A16 to A23 when the corresponding bits of register HACR are 0. F (CMOS/H) 99 to 6 A16 to A23 In external bus mode, these pins operate (as A16 to A23) to output the higher byte of address when the corresponding bits of register HACR are 0. 11 CHAPTER 1 OVERVIEW Table 1.6-1 Pin Functions (Continued) QFP LQFP Pin name Circuit format P30 9 10 12 13 F (CMOS/H) 7 In external bus mode, this pin operates to output the address input enable signal (ALE). P31 General-purpose I/O port. In external bus mode, this pin operates as the RD pin. F (CMOS/H) RD In external bus mode, this pin operates to output the read strobe signal (RD). P32 General-purpose I/O port. In external bus mode, this pin operates as the WRL/WR pin when the WRE bit is 1. WRL F (CMOS/H) WRL is used for strobe write for the lower 8 bits of the data bus in 16-bit access mode. WR is used for strobe write for 8 bits of the data bus in 8-bit access mode. P33 General-purpose I/O port. In external bus mode with bus width of 16 bits, this pin operates as the WRH pin when the WRE bit of register EPCR is 1. F (CMOS/H) 11 In external bus mode, this pin operates to output the higher bit of data strobe signal (WRH). P34 15 16 F (CMOS/H) 12 General-purpose I/O port. In external bus mode, this pin operates as the HRQ pin when the HDE bit of register EPCR is 1. HRQ In external bus mode, this pin operates to input the hold request signal (HRQ). P35 General-purpose I/O port. In external bus mode, this pin operates as the HAK pin when the HDE bit of register EPCR is 1. F (CMOS/H) 13 HAK In external bus mode, this pin operates to output the hold acknowledge signal (HAK). P36 General-purpose I/O port. In external bus mode, this pin operates to input the external ready signal (RDY) when the RYE bit of register EPCR is 1. F (CMOS/H) 14 RDY 12 In external bus mode, this pin operates to output the lower bit of data strobe signal (WRL/WR). WR WRH 14 General-purpose I/O port. In external bus mode, this pin operates as the ALE pin. ALE 8 10 Function In external bus mode, this pin operates to input the external ready signal (RDY). 1.6 Pin Functions Table 1.6-1 Pin Functions (Continued) QFP LQFP Pin name Circuit format P37 17 18 19 F (CMOS/H) 15 In external bus mode, this pin operates to output the machine cycle clock signal (CLK). P40 General-purpose I/O port. This pin operates as an open-drain output port when the OD40 bit of open drain control setting register (ODR4) is 1. (When these pins are set for input, the setting [D40 bit = 1] of register ODR4 is invalid.) E (CMOS/H) 16 SIN0 Serial data input (SIN0) pin for UART0 This pin is used for input occasionally during the input operation by UART0. Output from this pin by another function must be disabled except for intentional use. P41 General-purpose I/O port. This pin operates as an open-drain output port when the OD41 bit of open drain control setting register (ODR4) is 1. (When these pins are set for input, the setting [D41 bit = 1] of register DDR4 is invalid.) E (CMOS/H) 17 Serial data output (SOT0) pin for UART0 Function of this pin is valid when the serial data output from UART0 is enabled. P42 E (CMOS/H) 18 P43 E (CMOS/H) 19 SIN1 General-purpose I/O port. This pin operates as an open-drain output port when the OD42 bit of open drain control setting register (ODR4) is 1. (When these pins are set for input, the setting [D42 bit = 1] of register DDR4 is invalid.) Serial data I/O (SCK0) pin for UART0 Function of this pin is valid when the clock output from UART0 is enabled. SCK0 21 General-purpose I/O port. In external bus mode, this pin operates as the CLK pin when the CKE bit of register EPCR is 1. CLK SOT0 20 Function General-purpose I/O port. This pin operates as an open-drain output port when the OD43 bit of open drain control setting register (ODR4) is 1. (When these pins are set for input, the setting [D43 bit = 1] of register DDR4 is invalid.) Serial data input (SIN1) pin for UART1 This pin is used for input occasionally during the input operation by UART1. Output from this pin by another function must be disabled except for intentional use. 13 CHAPTER 1 OVERVIEW Table 1.6-1 Pin Functions (Continued) QFP LQFP Pin name Circuit format P44 22 E (CMOS/H) 20 P45 E (CMOS/H) 22 P46 23 E (CMOS/H) ADTG 26 24 P47 E (CMOS/H) SIN3 Serial data input (SIN3) pin for UART3 This pin is used for input occasionally during the input operation by UART3. Output from this pin by another function must be disabled except for intentional use. P51 General-purpose I/O port. 37 SOT3 14 Analog input (AN0) pin for A/D converter G (CMOS/H) AN1 39 General-purpose I/O port. This pin operates as an open-drain output port when the OD47 bit of open drain control setting register (ODR4) is 1. (When these pins are set for input, the setting [D47 bit = 0] of register DDR4 is invalid.) General-purpose I/O port. AN0 36 General-purpose I/O port. This pin operates as an open-drain output port when the OD46 bit of open drain control setting register (ODR4) is 1. (When these pins are set for input, the setting [D46 bit = 0] of register DDR4 is invalid.) External trigger input (ADTG) pin for A/D converter P50 38 General-purpose I/O port. This pin operates as an open-drain output port when the OD45 bit of open drain control setting register (ODR4) is 1. (When these pins are set for input, the setting [D45 bit = 0] of register DDR4 is invalid.) Serial clock I/O (SCK1) pin for UART1 Function of this pin is valid when the clock output from UART1 is enabled. SCK1 25 General-purpose I/O port. This pin operates as an open-drain output port when the OD44 bit of open drain control setting register (ODR4) is 1. (When these pins are set for input, the setting [D44 bit = 1] of register DDR4 is invalid.) Serial data output (SOT1) pin for UART1 Function of this pin is valid when the serial data output from UART1 is enabled. SOT1 24 Function G (CMOS/H) Analog input (AN1) pin for A/D converter Serial data output (SOT3) pin for UART3 Function of this pin is valid when the serial data output from UART3 is enabled. 1.6 Pin Functions Table 1.6-1 Pin Functions (Continued) QFP LQFP Pin name Circuit format General-purpose I/O port. P52 AN2 40 38 41 39 SCK3 P53 AN3 G (CMOS/H) G (CMOS/H) AN4 42 P55 General-purpose I/O port. SOT4 AN6 G (CMOS/H) 43 44 P57 AN7 G (CMOS/H) G (CMOS/H) 27 25 C - 28 26 P71 F (CMOS/H) 29 27 P72 F (CMOS/H) P73 32 H (CMOS/H) 30 DAO0 Analog input (AN5) pin for A/D converter Serial data output (SOT4) pin for UART4 Function of this pin is valid when the serial data output from UART4 is enabled. General-purpose I/O port. SCK4 46 Analog input (AN3) pin for A/D converter SIN4 P56 45 General-purpose I/O port. Serial data input (SIN4) pin for UART4 This pin is used for input occasionally during the input operation by UART4. Output from this pin by another function must be disabled except for intentional use. AN5 44 Serial clock I/O (SCK3) pin for UART3 Function of this pin is valid when the clock output from UART3 is enabled. Analog input (AN4) pin for A/D converter G (CMOS/H) 41 Analog input (AN2) pin for A/D converter General-purpose I/O port. P54 43 Function Analog input (AN6) pin for A/D converter Serial clock output (SCK4) pin for UART4 Function of this pin is valid when the clock output from UART4 is enabled. General-purpose I/O port. Analog input (AN7) pin for A/D converter Pin to connect 0.1 μF capacitor to regulate supplied power voltage General-purpose I/O port. General-purpose I/O port General-purpose I/O port This pin operates as a D/A converter output pin (DA00) when the DAE0 bit of D/A control register (DACR) is 1. D/A converter output 0 (DAO0) pin 15 CHAPTER 1 OVERVIEW Table 1.6-1 Pin Functions (Continued) QFP LQFP Pin name Circuit format P74 33 H (CMOS/H) 31 DAO1 P80 47 45 IRQ0 P81 48 46 IRQ1 P82 53 51 IRQ2 P83 54 52 IRQ3 P84 55 53 IRQ4 P85 56 54 IRQ5 P86 57 55 IRQ6 P87 58 56 IRQ7 F (CMOS/H) F (CMOS/H) F (CMOS/H) F (CMOS/H) F (CMOS/H) F (CMOS/H) F (CMOS/H) F (CMOS/H) 60 D (CMOS/H) 57 General-purpose I/O port External interrupt request 0 (IRQ0) pin General-purpose I/O port External interrupt request 1 (IRQ1) pin General-purpose I/O port External interrupt request 2 (IRQ2) pin General-purpose I/O port External interrupt request 3 (IRQ3) pin General-purpose I/O port External interrupt request 4 (IRQ4) pin General-purpose I/O port External interrupt request 5 (IRQ5) pin General-purpose I/O port External interrupt request 6 (IRQ6) pin General-purpose I/O port External interrupt request 7 (IRQ7) pin General-purpose I/O port A pull-up resistor can be assigned to this pin by the setting (RD60 = 1) of pull-up resistor setting register (RDR6). (When this pin set for output, the setting [D60 = 1] of register DDR6 is invalid.) SIN2 Serial data input (SIN2) pin for UART2 This pin is used for input occasionally during the input operation by UART2. Output from this pin by another function must be disabled except for intentional use. P61 General-purpose I/O port A pull-up resistor can be assigned to this pin by the setting (RD61 = 1) of pull-up resistor setting register (RDR6). (When this pin set for output, the setting [D61 = 1] of register DDR6 is invalid.) D (CMOS/H) 58 SOT2 16 General-purpose I/O port This pin operates as a D/A converter output pin (DA01) when the DAE1 bit of D/A control register (DACR) is 1. D/A converter output 1 (DAO1) pin P60 59 Function Serial data output (SOT2) pin for UART2 Function of this pin is valid when the serial data output from UART2 is enabled. 1.6 Pin Functions Table 1.6-1 Pin Functions (Continued) QFP LQFP Pin name Circuit format P62 61 D (CMOS/H) 59 P63 D (CMOS/H) 60 P64 D (CMOS/H) 61 P65 D (CMOS/H) 62 65 63 TX* I 66 64 RX* J (CMOS) P90 to P92 65 to 67 TIN0 to TIN2 IN0 to IN2 General-purpose I/O port A pull-up resistor can be assigned to this pin by the setting (RD65 = 1) of pull-up resistor setting register (RDR6). (When this pin set for output, the setting [D65 = 1] of register RDR6 is invalid.) This pin operates to output CKOT signal when CKOT is valid. CKOT 67 to 69 General-purpose I/O port A pull-up resistor can be assigned to this pin by the setting (RD64 = 1) of pull-up resistor setting register (RDR6). (When this pin set for output, the setting [D64 = 1] of register DDR6 is invalid.) This pin operates to output PPG0 signal when PPG is valid. PPG0 64 General-purpose I/O port A pull-up resistor can be assigned to this pin by the setting (RD63 = 1) of pull-up resistor setting register (RDR6). (When this pin set for output, the setting [D63 = 1] of register DDR6 is invalid.) This pin operates to output PPG1 signal when PPG is valid. PPG1 63 General-purpose I/O port A pull-up resistor can be assigned to this pin by the setting (RD62 = 1) of pull-up resistor setting register (RDR6). (When this pin set for output, the setting [D62 = 1] of register DDR6 is invalid.) Serial clock output (SCK2) pin for UART2 Function of this pin is valid when the clock output from UART2 is enabled. SCK2 62 Function This pin operates to output IEBusTM signal. This pin operates to input IEBusTM signal. General-purpose I/O port F (CMOS/H) Event input pins for reload timers 0, 1, and 2 These pins are used for input continuously during the input from reload timers. Output to this pin from other functions must be disabled except for intentional use. Trigger input pins for input capture channels 0 to 2 17 CHAPTER 1 OVERVIEW Table 1.6-1 Pin Functions (Continued) QFP LQFP Pin name Circuit format General-purpose I/O port P93 70 68 TOTO F (CMOS/H) IN3 71,72 69,70 General-purpose I/O port. F (CMOS/H) OUT0, OUT1 71 PWC General-purpose I/O port. F (CMOS/H) P97 74 72 POT 73,74 This pin operates to input PWC signal when the PWC timer is valid. General-purpose I/O port. F (CMOS/H) F 75,76 Reload timer output pins This pin function is applied for the output from reload timers 1 and 2. Event output pins for output compare channels 0 and 1 P96 73 Reload timer output pin This pin function is applied for the output from reload timer 0. Trigger input pin for input capture channel 3 P94,P95 TOT1, TOT2 Function This pin operates to output PWC signal when the PWC timer is valid. General-purpose I/O port. PA0,PA1 (CMOS/H) F 78 76 General-purpose I/O port. PA2 (CMOS/H) 79 77 X1A A Oscillation input. For the one clock system, leave it open. 80 78 X0A A Oscillation input. For the one clock system, perform external pull-down processing. 34 32 AVCC - A/D converter power supply pin 37 35 AVSS - A/D converter power supply pin 35 33 AVRH - External reference power supply pin for A/D converter 36 34 AVRL - External reference power supply pin for A/D converter 30 28 DVRH - External reference power supply pin for D/A converter 31 29 DVSS - External reference power supply pin for D/A converter 49 to 51 47 to 49 MD0 to MD2 C Input pins for operation mode specification These pins are connected directly to VCC or VSS. 23,84 21,82 VCC - Power supply (5 V) input pins 11,42,81 9,40,79 VSS - Power supply (0 V) input pins *1: On the MB90587C/CA, RX and TX are replaced with N and C, respectively. 18 1.7 I/O Circuit Formats 1.7 I/O Circuit Formats Table 1.7-1 "I/O Circuit Types" shows the formats of I/O circuits. The alphabetic letters shown in the "Classification" column of Table 1.7-1 "I/O Circuit Types" correspond to those shown in the "Circuit format" column of Table 1.6-1 "Pin Functions". ■ I/O Circuit Types Table 1.7-1 I/O Circuit Types Classification Circuit Remark • Oscillation feedback resistor: About 1 MΩ (High speed oscillator) About 10 MΩ (Low speed oscillator) • Hysteresis input with pull-up resistor Pull-up resistor: About 50 kΩ • Hysteresis input X1,X1A Oscillation feed back resistor A Clock input X0,X0A HARD,SOFT STANDBY CONTROL B R (pull-up) R C R 19 CHAPTER 1 OVERVIEW Table 1.7-1 I/O Circuit Types (Continued) Classification Circuit Remark • Pull-up resistor control P-ch • • Input with pull-up resistor control CMOS level output Hysteresis input with standby control Pull-up resistor: About 50 kΩ N-ch D R Standby control signal • • Open drain control signal • CMOS level output Hysteresis input with standby control Open drain control signal E R Standby control signal • • CMOS level output Hysteresis input with standby control • • CMOS level output Hysteresis input with standby control Analog input P-ch N-ch F R Standby control signal P-ch • N-ch G R Standby control signal 20 Analog input 1.7 I/O Circuit Formats Table 1.7-1 I/O Circuit Types (Continued) Classification Circuit Remark • • • CMOS level output Hysteresis input with standby control DA output • CMOS level output • CMOS input with standby control P-ch N-ch H P-ch DA output N-ch R Standby control signal P-ch I N-ch R J Standby control signal 21 CHAPTER 1 OVERVIEW 1.8 Precautions on Handling of Device Take special care for the following points when handling and operating the device: • Prevention of latchup • Treatment of unused input pins • Treatment of A/D converter power supply pins • Treatment of D/A converter power supply pins • • • • • • • • Treatment of TX and RX pins when IEBusTM is not used Power supply pins Using REALOS Startup of power Use of subclock mode and external clock Indeterminate outputs from ports 0 and 1 Notes on the use of "DIV A, Ri" and "DIVW A Rwi" instructions Stabilization of supply voltage ■ Precautions on the Handling of the Device ❍ Prevention of latchup Latchup may occur on a CMOS IC chip if: • a voltage higher than VCC or lower than VSS is applied to an input or output pin, • a voltage over the rated voltage is applied between VCC and VSS. • voltage AVCC is supplied before voltage VCC. An latchup increases remarkably the supply current that may cause an device overheat destruction. ❍ Treatment of unused pins Unused input pins left open may cause abnormal operation, or latch up leading to permanent damage. Unused input pins should be pulled up or pulled down through at least 2 kΩ resistance. Unused input/output pins may be left open in output state, but if such pins are in input state they should be handled in the same way as input pins. ❍ Treatment of A/D converter power supply pins If the A/D converter is not used, make connections of its power supply pins so that AVCC is equal to VCC and AVSS is equal to AVRH, AVRL, and VSS. ❍ Treatment of D/A converter power supply pins If the D/A converter is not used, make connections of its power supply pins so that DVRH is equal to VSS and DVSS is equal to VSS. 22 1.8 Precautions on Handling of Device ❍ Treatment of TX and RX pins when IEBusTM is not used If IEBus is not used, connect a pull-down resistor to the TX pin and a pull-down or pull-up resistor to the RX pin. ❍ Power supply pins The device is designed to connect those VCC and VSS pins that must be at the same potential in the device to prevent malfunctions, including latchup. When using the device, connect all the VCC and VSS pins externally to the power supply and ground to reduce unnecessary radiation, prevent the incorrect operation of strobe signals due to a rise of ground level, and keep to the standard for total output power. ❍ Using REALOS The use of EI2OS is not passible with the REALOS real time operating system. ❍ Startup of power To prevent a malfunction in the internal step-down circuit, be sure that the voltage start-up time after the power is turned on is at least 50 μs (between 0.2 and 2.7 V). Figure 1.8-1 Treatment of Power Supply Pins (VCC and VSS) Vcc Vss Vcc Vss MB90580C series Vcc Vss Vcc Vss Vss Vcc ❍ Use of subclock mode and external clock Even if the subclock mode is not used, connect oscillators to pins X0A and X1A. When using external clock, drive only pin X0 and leave pin X1 open. (See Figure 1.8-2 "Use of External Clock".) Figure 1.8-2 Use of external clock MB90580C series X0 OPEN X1 23 CHAPTER 1 OVERVIEW ❍ Indeterminate outputs from ports 0 and 1 During oscillation setting time of step-down circuit (during a power-on reset) after the power is turned on, the outputs from ports 0 and 1 become following state. • If RST pin is "H", the outputs become indeterminate. • If RST pin is "L", the outputs become high-impedance. Pay attention to the port output timing shown as follow Figure 1.8-3 Indeterminate output from ports 0 and 1 (RST pin is "H") Oscillation setting time Power-on reset Vcc (Power-supply pin) PONR (power-on reset) signal RST (external asynchronous reset) signal RST (internal reset) signal Oscillation clock signal KA (internal operation clock A) signal KB (internal operation clock B) signal PORT (port output) signal Period of indeterminated *1: Power-on reset time: Period of "clock frequency *2: Oscillation setting time: Period of "clock frequency 217 " (Clock frequency of 16 MHz: 8.19 ms) 218 " (Clock frequency of 16 MHz: 16.38ms) Figure 1.8-4 High-impedance output from ports 0 and 1 (RST pin is "L") Oscillation setting time Power-on reset Vcc (Power-supply pin) PONR (power-on reset) signal RST (external asynchronous reset) signal RST (internal reset) signal Oscillation clock signal KA (internal operation clock A) signal KB (internal operation clock B) signal PORT (port output) signal High-impedance *1: Power-on reset time: Period of "clock frequency *2: Oscillation setting time: Period of "clock frequency 24 17 2 " (Clock frequency of 16 MHz: 8.19 ms) 218 " (Clock frequency of 16 MHz: 16.38ms) 1.8 Precautions on Handling of Device ❍ Notes on the use of "DIV A, Ri" and "DIVW A Rwi" instructions The remainder obtained as the result of the execution of the signed division instructions "DIV A, Ri" and "DIVW A, RWi" is determined by the bank register and stored in the address containing the memory bank set by the bank register. For details, see Section 2.7 " Notes on Use of the DIV A, Ri and DIVW A, RWi Instructions". Also, for information on bank registers, see Section 2.3.6 "Bank Registers". ❍ Stabilization of supply voltage A sudden change in the supply voltage may cause the device to malfunction even within the specified Vcc supply voltage operation range. Therefore, the Vcc supply voltage should be stabilized. For reference, supply voltage should be controlled so that Vcc ripple variations (peak-to-peak values) at commercial frequencies (50 to 60Hz) fall below 10% of the standard Vcc supply voltage and the coefficient of fluctuation does not exceed 0.1 V/ms at instantaneous power switching. ❍ Notes on the during operation of PLL clock mode If the PLL clock mode is selected, the microcontroller attempt to be working with the selfoscillating circuit even when there is no external oscillator or external colck input is stopped. Performance of this operation, however, cannot be guaranteed. 25 CHAPTER 1 OVERVIEW 26 CHAPTER 2 CPU This chapter describes the functions and operation of the CPU. 2.1 "Memory Space" 2.2 "Addressing" 2.3 "Dedicated Registers" 2.4 "General-purpose Registers" 2.5 "Prefix Codes" 2.6 "Interrupt Suppression Instructions and Prefix Codes" 2.7 "Notes on Use of the DIV A, Ri and DIVW A, RWi Instructions" 27 CHAPTER 2 CPU 2.1 Memory Space The F2MC-16LX CPU core is a 16-bit CPU that was designed for applications requiring high-speed real-time processing in the areas welfare and car-mounted products. The F2MC-16LX instruction set is designed for controller applications and enables highspeed and high-efficiency processing of various types of control. In addition to 16-bit data processing, the F2MC-16LX can perform 32-bit data processing because it contains an internal 32-bit accumulator. The maximum size of the memory space is 16 MB (expandable) and can be accessed by the linear or the bank method. The instruction system was enhanced based on the F2MC-8 A-T architecture by adding high-level language support instructions, expanding the addressing modes, and enhancing the multiplication and division instructions and provides substantial bit processing capabilities. ■ Memory Space All data/program I/O channels managed by the F2MC-16LX CPU are allocated in the 16 MB memory space of the F2MC-16LX CPU. Specifying these addresses via the 24-bit address bus enables the CPU to access each of the resources. Figure 2.1-1 Example of the Relationship between the F2MC-16LX System and the Memory Map FFFFFFH F2MC-16LX Program FF8000H Data 810000H Data area CPU Interrupt Peripheral circuit [Device] Generalpurpose port 800000H 0000C0H 0000B0H 000020H 000000H 28 Program area Interrupt controller Peripheral circuit General-purpose port 2.2 Addressing 2.2 Addressing The following two methods can be used to specify addresses of the F2MC-16LX • Linear method: All 24 bits of the address are specified in the instructions. • Bank method: The higher 8 bits of an address are specified by the bank register associated with an application, while only the lower 16 bits of the address are specified by the instruction. ■ Linear Addressing Methods The linear addressing methods can be classified into the following two types: • 24-bit operand specification: A 24-bit address is directly specified by an operand. • 32-bit register indirect specification: The lower 24 bits of the 32-bit general-purpose register are used as an address. Figure 2.2-1 Example of the 24-bit Operand Specification in the Linear Addressing Method JMPP 123456H Old program counter + program bank 17452DH 17 452D JMPP 123456H 123456H New program counter + program bank 12 Next instruction 3456 Figure 2.2-2 Example of the 32-bit Register-Indirect Specification in the Linear Addressing Method MOV A,@RL1+7 Old AL XXXX 090700H 3A +7 RL1 (Higher 8 bits are ignored.) New AL 240906F9 003A ■ Addressing by the Bank Method The bank method divides the 16 MB memory space into 256 banks of each 64 KB and specifies the bank associated with each space using the following five bank registers: 29 CHAPTER 2 CPU ❍ Program bank register (PCB): Initial reset value FFH The 64 KB bank specified by PCB is called program (PC) space. The program space mainly contains instruction codes, the vector table, and immediate data. ❍ Data bank register (DTB): Initial reset value 00H The 64 KB bank specified by DTB is called data (DT) space. The data space mainly contains readable and writable data as well as the control and data registers for external and internal resources. ❍ Initial reset value 00H of the user stack bank register (USB) and initial reset value00H of the system stack bank register (SSB) The 64 KB bank specified by USB or SSB is called stack (SP) space. The stack space is accessed when a stack is used to save the contents of a register during the execution of a push or pop instruction or an interrupt. The space to be used depends on the S flag in the condition code register. ❍ Additional bank register (ADB): Initial reset value 00H The 64 KB bank specified by ADB is called additional (AD) space. The additional space mainly contains data that overflowed from the DT space. To increase instruction code efficiency, a default space is determined for instructions of each addressing mode, as listed in Table 2.2-1 "Default Spaces and Addressing Mode". To use a non-default space when using an addressing mode, specify the prefix code associated with the bank before the instruction. This makes it possible to access any bank space that is associated with the prefix code. DTB, USB, SSB, and ADB are initialized to 00H by a reset. PCB is initialized to a value specified by the reset vector. After the reset, the DT, SP, or AD space is allocated in bank 00H (000000H-00FFFFH). The PC space is allocated in the bank specified by the reset vector. Table 2.2-1 Default Spaces and Addressing Mode Default space Addressing mode Program space PC-indirect, program access, branch system Data space Addressing mode via @RW0, @RW1, @RW4, and @RW5, @A, addr16, dir Stack space Addressing mode via PUSHW, POPW, @RW3, and @RW7 Additional space Addressing mode via @RW2 and @RW6 Figure 2.2-3 "Example of the Physical Addresses of Each Space" is an example of memory space divided into register banks. 30 2.2 Addressing Figure 2.2-3 Example of the Physical Addresses of Each Space FFFFFFH Program space FF0000H FFH : PCB (program bank register) B3H : ADB (additional bank register) 92H : USB (user stack bank register) 68H : DTB (data bank register) 4BH : SSB (system stack bank register) B3FFFFH Additional space B30000H Physical 92FFFFH addresses 920000H User stack space 68FFFFH Data space 680000H 4BFFFFH 4B0000H System stack space 000000H 31 CHAPTER 2 CPU 2.2.1 Allocating Multiple-byte Data in a Memory Space In a memory space, the lower eight bits of multiple-byte data are stored at address n. The remaining bits are stored at the addresses n + 1, n + 2, n + 3, ... in that order. ■ Allocating Multiple-byte Data in a Memory Space As shown in Figure 2.2-4 "Example of Allocating Multiple-byte Data in a Memory Space" data is written to memory in ascending order of addresses. Therefore, if the data is 32 bit long, the lower 16 bits are first transferred and the higher 16 bits are transferred subsequently. If a reset signal is input immediately after the lower data is written, the higher data may not be written. Therefore, to correctly retain the data, a reset signal must be input after the higher data is written. Figure 2.2-4 Example of Allocating Multiple-byte Data in a Memory Space MSB H LSB 01010101 11001100 11111111 00010100 01010101 11001100 11111111 Address n 00010100 L ■ Access of Multiple-byte Data As shown in Figure 2.2-5 "Example of Accessing Multiple-byte Data (Execution of MOVWA, 080FFFFH" all accesses are basically made within a bank. For an instruction that accesses multiple-byte data, the next address after address FFFFH is 0000H in the same bank. Figure 2.2-5 Example of Accessing Multiple-byte Data (Execution of MOVWA, 080FFFFH) H AL before execution 80FFFFH 01H 800000H 23H AL after execution L 32 ?? ?? 23H 01H 2.3 Dedicated Registers 2.3 Dedicated Registers Dedicated registers are implemented in the CPU by dedicated hardware. The application of these registers is restricted by the CPU architecture. ■ Dedicated Registers Dedicated registers are implemented in the CPU by dedicated hardware. The application of these registers is restricted by the CPU architecture. The F2MC-16LX supports the following 13 dedicated registers: ❍ Accumulator (A=AH:AL) Two 16-bit accumulators (can be used as a single accumulator containing a total of 32 bits). ❍ User stack pointer (USP) A 16-bit pointer to the user stack area. ❍ System stack pointer (SSP) A 16-bit pointer to the system stack area. ❍ Processor status (PS) A 16-bit register indicating the system status. ❍ Program counter (PC) 16-bit register for the address at which the program is stored. ❍ Program bank register (PCB) An 8-bit register indicating the PC space. ❍ Data bank register (DTB) An 8-bit register indicating the DT space. ❍ User stack bank register (USB) An 8-bit register indicating the user stack space. ❍ System stack bank register (SSB) An 8-bit register indicating the system stack space. ❍ Additional bank register (ADB) An 8-bit register indicating the AD space. 33 CHAPTER 2 CPU ❍ Direct page register (DPR) An 8-bit register indicating the direct page. Figure 2.3-1 Dedicated Registers AH Accumulator AL USP User stack pointer SSP System stack pointer PS Processor status PC Program counter DPR Direct page register PCB Program bank register DTB Data bank register USB User stack bank register SSB System stack bank register ADB Additional data bank register 8bit 16bit 32bit 34 2.3 Dedicated Registers 2.3.1 Accumulator (A) The accumulator (A) consists of the two 16-bit arithmetic operation registers AH and AL. It is used as temporary storage for arithmetic operation results or for data transfer. When AH and AL are used for 32-bit data processing, they are connected. Only AL is used for word processing of 16-bit data or byte processing of 8-bit data. ■ Accumulator (A) Data in the accumulator (A) can be used for arithmetic operations with data in the memory and registers (Ri, RWi, and RLi). As with the F2MC-8L, when the F2MC-16LX transfers data to the AL that is not longer than a single word, the data in AL before the transfer is automatically transferred to the AH (data retention function). In other words, processing efficiency can be increased by using the data retention function and AL-AH arithmetic operations. Figure 2.3-2 Example of 32-bit Data Transfer MOVL A,@RW1+6 (This instruction reads long-word data at the address obtained by adding the contents of RW1 to the 8-bit offset, and stores the read contents in A.) MSB A before execution XXXXH XXXXH DTB A after execution 8F74H 2B52H AH AL A6H Memory space A61540H 8FH 74H A6153EH 2BH 52H RW1 15H 38H LSB +6 Figure 2.3-3 Example of AL-AH Transfer MOVW A,@RW1+6 (This instruction reads word data at the address obtained by adding the contents of RW1 to the 8-bit offset and stores the read contents in A.) MSB A before execution XXXXH 1234H DTB A after execution 1234H 2B52H AH AL A6H Memory space A61540H 8FH 74H A6153EH 2BH 52H RW1 15H 38H LSB +6 35 CHAPTER 2 CPU As shown in Figure 2.3-4 "Example of Zero Extension" when data is transferred to the AL that is not longer than a byte, it is expanded to 16 bits by signs or zeros and stored in AL. The data in the AL can also be handled both as word or byte data. If an arithmetic operation instruction for byte processing is executed, the higher eight bits of AL before the arithmetic operations are ignored. All higher eight bits of the arithmetic operation result are set to 0. The accumulator (A) is not initialized by a reset. Immediately after a reset, its value becomes undefined . Figure 2.3-4 Example of Zero Extension MOV A,3 000 H (This instruction expands the contents at address 3000 by adding zeros, and stores the result in the AL.) MSB Memory space A before execution XXXXH 2456H DTB A after execution 2456H 0088H AH AL B53000H 77H LSB 88H B5H Figure 2.3-5 Example of Sign Extension MOVX A, 3000H (This instruction expands the data at address 3000H with signs, and stores the result in the AL.) Memory space MSB A before execution XXXXH 2456H DTB A after execution 36 2456H FF88H AH AL B53000H B5H 77H 88H LSB 2.3 Dedicated Registers 2.3.2 User Stack Pointer (USP) and System Stack Pointer (SSP) The user stack pointer (USP) and system stack pointer (SSP) are 16-bit registers, and indicate an address for data saving and return during execution of a push or pop instruction or a subroutine. ■ User Stack Pointer (USP) and System Stack Pointer (SSP) The user stack pointer (USP) and system stack pointer (SSP) are used by stack instructions. However, if the S flag for the processor status is 0, the USP register becomes valid. If the S flag is 1, the SSP register becomes valid (see Figure 2.3-6 "Stack Operation Instructions and Stack Pointers (Example of PUSHW A when the S Flag is 0)" and Figure 2.3-7 "Stack Operation Instructions and Stack Pointers (Example of PUSHW A when the S Flag is 1)"). If an interrupt is accepted, the S flag is set. In other words, register saving at an interrupt always occurs in the memory area indicated by the SSP. The SSP is used for stack processing by an interrupt routine. The USP is used for stack processing by a routine other than an interrupt routine. If it is unnecessary to split the stack space, use only the SSP. SSP --> SSB, USP --> USB indicate the higher eight bits of an address for stack processing. USP and SSP are not initialized by a reset and their values become undefined in that case. Figure 2.3-6 Stack Operation Instructions and Stack Pointers (Example of PUSHW A when the S Flag is 0) MSB Before execution AL A624H S flag After execution AL 0 A624H S flag 0 USB C6H USP F328H SSB 56H SSP 1234H USB C6H USP F326H SSB 56H SSP 1234H C6F326H LSB XX XX The user stack is used because the S flag is 0. C6F326H A6H 24H Figure 2.3-7 Stack Operation Instructions and Stack Pointers (Example of PUSHW A when the S Flag is 1) Before execution AL S flag After execution AL S flag A624H 1 A624H 1 USB C6H USP F328H SSB 56H SSP 1234H USB C6H USP F328H SSB 56H SSP 1232H 561232H XX XX 561232H A6H 24H The system stack is used because the S flag is 1. Note: As a general rule, use an even-numbered address as the value for the stack pointer. 37 CHAPTER 2 CPU 2.3.3 Processor Status (PS) The processor status (PS) consists of bits for controlling CPU operations and bits indicating the CPU status. ■ Processor Status (PS) The higher bytes of the processor status (PS) consist of the register bank pointer (RP), which indicates the starting address of the register bank, and the interrupt level mask register (ILM). The lower bytes of the PS consist of the condition code register (CCR) formed by flags to be set or reset by instruction execution results or interrupts. Figure 2.3-8 Structure of the Processor Status (PS) 15 PS Initial value 13 12 8 7 ILM 0 RP 0 0 0 CCR 0 0 0 0 0 0 1xxxxx x: Undefined value ■ Condition Code Register (CCR) Figure 2.3-9 Configuration of the Condition Code Register (CCR) 7 Initial value 6 5 4 3 2 1 0 I S T N Z V C : CCR 0 1 x x x x x x: Undefined value ❍ Interrupt enable flag (I) An interrupt is enabled when I is 1 for all interrupt requests other than a software interrupt. If I is 0, the interrupt is masked and I is cleared at a reset. ❍ Stack flag (S) When S is 0, the USP becomes effective as the stack operation pointer. If S is 1, SSP becomes effective. S is set when an interrupt is accepted or a reset is made. ❍ Sticky bit flag (T) This flag is 1 if the data shifted out from the carry contains at least one 1 after a logical right or arithmetic right shift instruction is executed. In other cases, the flag is 0. The flag is also 0 when the shift amount is 0. ❍ Negative flag (N) This flag is set when the MSB of the arithmetic operation result is 1. It is cleared if this MSB is 0. 38 2.3 Dedicated Registers ❍ Zero flag (Z) This flag is set when all arithmetic operation results are 0. It is cleared in other cases. ❍ Overflow flag (V) This flag is set when an overflow occurs to indicate a signed numeric value as a result of an arithmetic operation. It is cleared if no overflow occurs. ❍ Carry flag (C) This flag is set when a carry-up or carry-down is generated from the MSB as a result of an arithmetic operation. It is cleared if no carry-up or carry-down occurs. ■ Register Bank Pointer (RP) The register bank pointer (RP) indicates the relationship between the general-purpose register of the F2MC-16LX and its internal RAM address. The RP indicates the first memory address of the register bank which is currently used by the conversion expression [000180H + (RP)*10H]. The RP consists of five bits and can have a value from 00H to 1FH. It can also assign a register bank in the memory area 000180H to 00037FH. However, when the memory in this range is not internal RAM, the register cannot be used as a general-purpose register. The contents of RP are all initialized to 0 by a reset. From the viewpoint of an instruction, it is possible to transfer an 8-bit immediate value to the RP, but only the lower five bits of the data are actually used. Figure 2.3-10 Structure of the Register Bank Pointer (RP) Initial value B4 B3 B2 B1 B0 0 0 0 0 0 : RP 39 CHAPTER 2 CPU ■ Interrupt Level Mask Register (ILM) The interrupt level mask register (ILM) consists of three bits that indicate the level of the CPU interrupt mask. Only interrupt requests whose levels are higher than the level indicated by these three bits are accepted. As shown in Figure 2.3-1 "Dedicated Registers" level 0 is defined as the highest and level 7 is defined as the lowest. In order that an interrupt is accepted, a value which is smaller than the value retained by the current ILM must be requested. When the interrupt is accepted, its level value is stored in the ILM, and any subsequent interrupt with equal or lower priority is not accepted. The contents of ILM are all initialized to 0 by a reset. From the viewpoint of the instruction, it is possible to transfer an 8-bit immediate value to the ILM, but only the lower three bits of the data are actually used. Figure 2.3-11 Structure of the Interrupt Level Register (ILM) ILM2 Initial value 0 ILM1 0 ILM 0 : ILM 0 Table 2.3-1 Level Hierarchy of the Levels Indicated by the Interrupt Level Mask Register (ILM) 40 ILM2 ILM1 ILM0 Level value Level of interrupts to be allowed 0 0 0 0 Interrupt prohibited 0 0 1 1 0 only 0 1 0 2 Level value of less than 1 0 1 1 3 Level value of less than 2 1 0 0 4 Level value of less than 3 1 0 1 5 Level value of less than 4 1 1 0 6 Level value of less than 5 1 1 1 7 Level value of less than 6 2.3 Dedicated Registers 2.3.4 Program Counter (PC) The program counter (PC) is a 16-bit counter that indicates the lower 16 bits of the memory address for the instruction code to be executed by the CPU. The higher 8-bit of the address are indicated by the PCB. ■ Program Counter (PC) The program counter (PC) is updated by conditional branch instructions, subroutine call instructions, interrupts, or resets. It can also be used as the base pointer to an operand access. Figure 2.3-12 Structure of the Program Counter PCB FE PC ABCD FEABCD Next instruction to be executed 41 CHAPTER 2 CPU 2.3.5 Direct Page Register (DPR) The direct page register (DPR) specifies an operand between addr8 and addr15 when a direct addressing instruction is executed. DPR is eight bits long and is initialized to 01H by a reset. DPR can be read or written by an instruction. ■ Direct Page Register (DPR) Figure 2.3-13 "Generating a Physical Address by Direct Addressing" shows physical address generation by direct addressing. Figure 2.3-13 Generating a Physical Address by Direct Addressing DTB register MSB 24-bit physical address 42 DPR register Direct address in an instruction LSB 2.3 Dedicated Registers 2.3.6 Bank Registers Bank registers can be classified into the following five types: • Program counter bank register (PCB) <initial value: value of the reset vector> • Data bank register (DTB) <initial value: 00H> • User stack bank register (USB) <initial value: 00H> • System stack bank register (SSB) <initial value: 00H> • Additional data bank register (ADB) <initial value: 00H> ■ Bank Registers Bank registers indicate the memory banks in which the PC space, DT space, SP space (user), SP space (system), and AD space are allocated. All the bank registers are of byte length, and the PCB is initialized to "00H" by a reset vector. Non-PCB bank registers are readable and writable. The PCB is readable but not writable. The PCB is rewritten at an interrupt or when a JMPP, CALLP, RETP, RETI, or RETF instruction which branches to all of the 16 MB space is executed. For register operations, see Section 2.1 "Memory Space". 43 CHAPTER 2 CPU 2.4 General-purpose Registers General-purpose registers are the same as dedicated registers in the sense that they coexist with the RAM in the address space of the CPU and that they can be accessed without specifying an address. Similar to ordinary memory, the user can specify the use of general-purpose registers. ■ General-purpose Registers The general-purpose registers of the F2MC-16LX are located at 000180H to 00037FH (maximum) of the RAM. The register bank pointer (RP) specifies the portion of the previously mentioned register bank currently used. Each bank contains the three types of registers listed below. These registers are not independent but have the following relationship as shown in Figure 2.4-1 "General-purpose Registers". • R0 to R7: 8-bit general-purpose registers • RW0 to RW7: 16-bit general-purpose registers • RL0 to RL3: 32-bit general-purpose registers Figure 2.4-1 General-purpose Registers MSB LSB 16bit 000180 + RP*10 Low RW0 RL0 First address of the general-purpose register RW1 RW2 RL1 RW3 R1 R0 RW4 R3 R2 RW5 R5 R4 RW6 R7 R6 RW7 RL2 RL3 High The relationship between higher and lower bytes of the byte and word registers can be expressed by the following expression: PW(i+4)=R(i x 2+1) x 256+R(i x 2)[i=0 to 3] The relationship between the higher and lower bytes of the RLi and RW can be expressed by the following expression: RL(i)=RW(i x 2+1) x 65536+RW(i x 2)[i=0 to 3] 44 2.4 General-purpose Registers ■ Register Banks A register bank consists of eight words. As with ordinary RAM, the contents of the register bank are not initialized by a reset and the status before the reset is retained. However, the values contained in the register bank are undefined at power-on. As shown in Table 2.4-1 "Functions of Register Banks" register banks can be used as generalpurpose registers in the type of byte registers R0 to R7, word registers RW0 to RW7, and long word registers RL0 to RL3. They can also be used for arithmetic operations to store an instruction or a pointer. Table 2.4-2 "Relationship between Resister in Resister Bank" shows the relationship of registers in a register bank. Table 2.4-1 Functions of Register Banks Register Function R0 to R7 Used as operands of instructions. Note R0 is also used as a barrel shift counter and normalize instruction counter. RW0 to RW7 Used as pointers and operands of instructions. Note RW0 is also used as a string instruction counter. RL0 to RL3 Used as long pointers and operands of instructions. Table 2.4-2 Relationship between Resister in Resister Bank RW0 RL0 RW1 RW2 RL1 RW3 R0 RW4 R1 RL2 R2 RW5 R3 R4 RW6 R5 RL3 R6 RW7 R7 45 CHAPTER 2 CPU 2.5 Prefix Codes Prefix codes can be classified into three types: bank selection prefixes, common register bank prefixes, and flag change suppression prefixes. Adding these prefix codes at the front of instructions can change a part of the operation. ■ Bank Selection Prefixes The memory space to be used at data access is determined for each addressing mode. By adding bank selection prefixes at the front of an instruction, the memory space for data access by an instruction can be freely selected regardless of the addressing mode. Table 2.5-1 "Bank Selection Prefixes" lists the bank selection prefixes and the memory spaces selected by them. Table 2.5-1 Bank Selection Prefixes Bank selection prefix Selected space PCB Program counter space DTB Data space ADB Additional space SPB The system stack space or user stack space is used depending on the contents of the stack flag at that time. However, note the following in connection with using bank selection prefixes for the following instructions: ❍ String instructions [MOVS, MOVSW, SCEQ, SCWEQ, FILS, and FILSW] Use the bank register specified by the operand regardless of whether there is a prefix. ❍ Stack operation instructions [PUSHW, POPW] Use SSB or USB according to the S flag regardless of whether there is a prefix. ❍ I/O access instructions [MOV A, io/MOV io, A/MOVX A, io/MOVW A, io/MOVW io, A/MOV io, #imm8 MOVW io, #imm16 / MOVB A, io:bp / MOVB io:bp, A / SETB io:bp / CLRB io:bp BBC io:bp, rel / BBS io:bp, rel / WBTC, WBTS] The I/O space of a bank is used, regardless of whether there is a prefix. ❍ Flag change instructions [AND CCR, #imm8, OR CCR, #imm8] The operation of the instruction itself is as normal, however, the prefix has an effect on the next instruction. ❍ POPW ps The SSB or the USB is used according to the S flag regardless of whether there is a prefix. The prefix has an effect on the next instruction. 46 2.5 Prefix Codes ❍ MOV ILM, #imm8 The operation of the instruction itself is normal, however, the prefix has an effect on the next instruction. ❍ RETI SSB is used regardless of whether there is a prefix. ■ Common Register Bank Prefix (CMR) To simplify the data exchange between multiple tasks, a relatively easy means of accessing the same register bank regardless of the RP value at that time is required. Adding the common register bank prefix (CMR) in front of instructions that access this register bank simplifies all register access of the instruction to common banks between 000180H and 00018FH (register bank selected when RP = 0) regardless of the current RP value. However, note the following remark about instructions when using the common register bank prefix (CMR): ❍ String instructions [MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW] If an interrupt is requested during the execution of a string instruction to which a prefix code has been added, a malfunction occurs after the return from the interrupt because the prefix has become invalid. Therefore, do not add the CMR prefix to the above string instructions. ❍ Flag change instructions [AND CCR, #imm8/OR CCR, #imm8/POPW PS] The operation of these instructions is normal, but the prefix has an effect on the next instruction. ❍ MOV ILM, #imm8 The operation of this instruction is normal, but the prefix has an effect on the next instruction. 47 CHAPTER 2 CPU ■ Flag Change Suppression Prefix (NCC) To suppress a flag change, use the flag change suppression prefix code (NCC). By placing the prefix code in front of the instruction to suppress an unwanted flag change, a flag change during the execution of the instruction can be suppressed. However, note the following remarks about instructions when using the flag change suppression prefix (NCC): ❍ String instructions [MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW] If an interrupt request occurs during execution of a string instruction to which a prefix code was added, a malfunction occurs after the return from the interrupt because the prefix has become invalid. Therefore, do not add the NCC prefix to the above string instructions. ❍ Flag change instruction [AND CCR, #imm8/OR CCR, #imm8/POPW PS] The operation of these instructions is normal, but the prefix has an effect on the next instruction. ❍ Interrupt instructions [INT #vct8/INT9/INT addr16/INTP addr24/RETI] CCR changes according to the instruction specifications regardless of whether there is a prefix. ❍ JCTX @A CCR changes according to the instruction specifications regardless of whether there is a prefix. ❍ MOV ILM, #imm8 The operation of this instructions is normal, but the prefix has an effect on the next instruction. 48 2.6 Interrupt Suppression Instructions and Prefix Codes 2.6 Interrupt Suppression Instructions and Prefix Codes The following 10 types of interrupt suppression instructions do not detect whether there is a hardware interrupt request and ignore any such interrupt request. - MOV ILM, #imm8 - OR CCR, #imm8 - AND CCR,#imm8 - POPW PS - PCB - SPB - NCC - ADB - CMR - DTB ■ Interrupt Suppression Instructions As shown in Figure 2.6-1 "Interrupt Suppression Instructions" assume that a valid hardware interrupt request is issued during the execution of an interrupt suppression instruction. This interrupt will only be processed in an instruction other than an interrupt suppression instruction and after the present interrupt suppression instruction. Figure 2.6-1 Interrupt Suppression Instructions Interrupt suppression instruction Ordinary instruction Interrupt request generation Acceptance of interrupt ■ Restrictions on Interrupt Suppression and Prefix Instructions As shown in Figure 2.6-2 "Interrupt Suppression Instructions and Prefix Codes" if a prefix code is added in front of the interrupt suppression instruction, the effect of the prefix code expands to the first instruction other than the interrupt suppression instruction itself after the prefix code. Figure 2.6-2 Interrupt Suppression Instructions and Prefix Codes Interrupt suppression instruction MOV A, FFH CCR:XXX10XX NCC MOV ILM,#imm8 ADD A, 01H CCR:XXX10XX CCR does not change due to NCC. 49 CHAPTER 2 CPU ■ In the Case of Consecutive Prefix Codes As shown in Figure 2.6-3 "Consecutive Prefix Codes" when conflicting prefix codes are specified consecutively, only the last prefix code is valid. In the figure below, PCB, ADB, DTB, and SPB are conflicting prefix codes. Figure 2.6-3 Consecutive Prefix Codes Prefix code ADB DTB PCB ADD A, 01H Prefix code PCB becomes valid. 50 2.7 Notes on Use of the DIV A, Ri and DIVW A, RWi Instructions 2.7 Notes on Use of the DIV A, Ri and DIVW A, RWi Instructions If the DIV A, Ri and DIVW A, RWi instructions are used, set the bank registers to "00H". ■ Notes on use of the DIV A, Ri and DIVW A, RWi instructions Table 2.7-1 Notes on use of the DIV A, Ri and DIVW A, RWi instructions (i=0 to 7) Instruction DIV A, R0 Name of the bank register that is affected when the instruction at left is executed DTB Remainder storage address (DTB: Upper 8 bits) + (0180H + RP x 10H + 8H: Lower 16 bits) DIV A, R1 (DTB: Upper 8 bits) + (0180H + RP x 10H + 9H: Lower 16 bits) DIV A, R4 (DTB: Upper 8 bits) + (0180H + RP x 10H + CH: Lower 16 bits) DIV A, R5 (DTB: Upper 8 bits) + (0180H + RP x 10H + DH: Lower 16 bits) DIVW A, RW0 (DTB: Upper 8 bits) + (0180H + RP x 10H + 0H: Lower 16 bits) DIVW A, RW1 (DTB: Upper 8 bits) + (0180H + RP x 10H + 2H: Lower 16 bits) DIVW A, RW4 (DTB: Upper 8 bits) + (0180H + RP x 10H + 8H: Lower 16 bits) DIVW A, RW5 (DTB: Upper 8 bits) + (0180H + RP x 10H + AH: Lower 16 bits) DIV A, R2 ADB (ADB: Upper 8 bits) + (0180H + RP x 10H + AH: Lower 16 bits) DIV A, R6 (ADB: Upper 8 bits) + (0180H + RP x 10H + EH: Lower 16 bits) DIVW A, RW2 (ADB: Upper 8 bits) + (0180H + RP x 10H + 4H: Lower 16 bits) DIVW A, RW6 (ADB: Upper 8 bits) + (0180H + RP x 10H + EH: Lower 16 bits) DIV A, R3 DIV A, R7 USB SSB*1 (USB*2: Upper 8 bits) + (0180H + RP x 10H + BH: Lower 16 bits) (USB*2: Upper 8 bits) + (0180H + RP x 10H + FH: Lower 16 bits) DIVW A, RW3 (USB*2: Upper 8 bits) + (0180H + RP x 10H + 6H: Lower 16 bits) DIVW A, RW7 (USB*2: Upper 8 bits) + (0180H + RP x 10H + EH: Lower 16 bits) *1: Depending on the S bit in the CCR register *2: If the S bit in the CCR register is zero The values of the bank registers (DTB, ADB, USB, SSB) are "00H", the remainder of the division result is stored in the register of the instruction operand. If the value of the bank register is other than "00H", the upper 8-bit address is specified by the bank register corresponding to the register of the instruction operand, while the lower 16-bit address becomes the same address of that of the instruction operand. The remainder is stored in the register of the bank specified by the upper eight bits. 51 CHAPTER 2 CPU Example If DIV A, R0 is executed where DTB="053H" and RP="03H", the address of R0 is "0001B8H" from "0180H"+RP ("03H") x "10H" + "08H" (address equivalent to R0). Here, since the bank register specified in DIV A, R0 is the data bank register (DTB), the remainder is stored at "05301B8H", which is obtained by prefixing the above address with bank address "053H". (For information on the Ri and RWi registers, Section 2.4 "Generalpurpose Registers". ■ Avoiding being subject to the notes To enable the user to develop programs that are not covered by the notes on the use of DIV A, Ri and DIVW A, RWi instructions, Fujitsu provides modified compilers that do not generate the instructions in Table 2.7-1 "Notes on use of the DIV A, Ri and DIVW A, RWi instructions (i=0 to 7)" and assemblers that add the function of replacing the instructions in Table 2.7-1 with an equivalent instruction string. Use the following compiler and assembler. • Compiler • • Assembler • 52 cc907 V02L06 and later versions and fcc907s V30L02 and later versions asm907a V03L04 and later versions and fasm907s V30L04 (Rev. 300004) and later versions CHAPTER 3 INTERRUPTS This chapter describes the features and operation of interrupts. 3.1 "Overview of Interrupts" 3.2 "Interrupt Causes" 3.3 "Interrupt Vectors" 3.4 "Hardware Interrupts" 3.5 "Software Interrupts" 3.6 "Expanded Intelligent I/O Service (EI2OS)" 3.7 "Exceptions because of Executing Undefined Instructions" 53 CHAPTER 3 INTERRUPTS 3.1 Overview of Interrupts F2MC-16LX provides interrupt features for suspending the currently executed processing when a certain event occurs and transferring the control to another predefined program. ■ Overview of Interrupts The provided interrupt features can be classified into four types: 54 • Hardware interrupts: Interrupt due to an event of an internal resource • Software interrupts: Interrupt due to an event because of a software instruction • Extended intelligent I/O service (EI2OS): Transfer processing due to an event of an internal resource • Exception: Suspension due to an exceptional operation 3.2 Interrupt Causes 3.2 Interrupt Causes Table 3.2-1 "Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers" lists interrupt causes, interrupt vectors, and interrupt control registers. ■ Interrupt Causes Table 3.2-1 Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers Interrupt cause EI2OS clear Interrupt vector Interrupt control register Number Address Number Address Reset N #08 FFFFDCH - - INT9 instruction N #09 FFFFD8H - - Exception N #10 FFFFD4H - - A/D converter Y #11 FFFFD0H ICR00 Time base timer N #12 FFFFCCH 0000B0H DTP0 (external interrupt #0)/ end of UART3 reception Y #13 FFFFC8H ICR01 DTP1 (external interrupt #1)/ end of UART4 reception Y #14 FFFFC4H 0000B1H DTP2 (external interrupt #2)/ end of UART3 transmission Y #15 FFFFC0H ICR02 DTP3 (external interrupt #3)/ end of UART4 transmission Y #16 FFFFBCH 0000B2H DTP4 to DTP7 (external interrupts #4 to #7) Y #17 FFFFB8H ICR03 Output compare (channel 1) matching (I/O timer) Y #18 FFFFB4H 0000B3H End of UART2 reception Y #19 FFFFB0H ICR04 End of UART1 reception Y #20 FFFFACH 0000B4H Input capture (channel 3) fetching (I/O timer) Y #21 FFFFA8H ICR05 Input capture (channel 2) fetching (I/O timer) Y #22 FFFFA4H 0000B5H Input capture (channel 1) fetching (I/O timer) Y #23 FFFFA0H ICR06 Input capture (channel 0) fetching (I/O timer) Y #24 FFFF9CH 0000B6H 55 CHAPTER 3 INTERRUPTS Table 3.2-1 Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers (Continued) Interrupt cause EI2OS clear Interrupt vector Number Address Interrupt control register Number Address ICR07 0000B7H ICR08 0000B8H ICR09 0000B9H ICR10 0000BAH ICR11 0000BBH 8/16-bit PPG0 counter borrow N #25 FFFF98H 16-bit reload timer 2 to 0 Y #26 FFFF94H Watch prescaler N #27 FFFF90H Output compare (channel 0) matching (I/O timer) Y #28 FFFF8CH End of UART2 transmission Y #29 FFFF88H End of measurement by PWC timer/PWC timer overflow Y #30 FFFF84H End of UART1 transmission Y #31 FFFF80H 16-bit free-run timer (I/O timer) overflow Y #32 FFFF7CH End of UART0 transmission Y #33 FFFF78H 8/16-bit PPG1 counter borrow N #34 FFFF74H End of IEBus reception y #35 FFFF70H ICR12 0000BCH Start of IEBus transmission y #37 FFFF68H ICR13 0000BDH End of UART0 reception y #39 FFFF60H ICR14 0000BEH Flash memory status N #41 FFFF58H ICR15 Delay interrupt N #42 FFFF54H 0000BFH y: An interrupt request flag is cleared by the EI2OS interrupt clear signal. There is a stop request. Y: An interrupt request flag is cleared by the EI2OS interrupt clear signal. N: An interrupt request flag is not cleared by the EI2OS interrupt clear signal. Note: If a resource has two possible interrupt causes with the same interrupt number, both interrupt request flags for the two interrupt causes are cleared by an EI2OS interrupt clear signal. Therefore, if the E2OS feature is used for one interrupt cause, the other interrupt feature cannot be used. To resolve this, set the interrupt request permission bit to 0 and use software polling. 56 3.3 Interrupt Vectors 3.3 Interrupt Vectors Table 3.3-1 "List of Interrupt Vectors" shows lists the interrupt vectors. ■ Interrupt Vectors Table 3.3-1 List of Interrupt Vectors Software interrupt instruction Vector address L Vector address M Vector address H Mode register Interrupt No. INT 0 FFFFFCH FFFFFDH FFFFFEH Not used #0 : : : : : : INT 7 FFFFE0H FFFFE1H FFFFE2H Not used #7 None INT 8 FFFFDCH FFFFDDH FFFFDEH FFFFDF #8 (RESET vector) INT 9 FFFFD8H FFFFD9H FFFFDAH Not used #9 None INT 10 FFFFD4H FFFFD5H FFFFD6H Not used #10 <Exception> INT11 FFFFD0H FFFFD1H FFFFD2H Not used #11 A/D converter INT 12 FFFFCCH FFFFCDH FFFFCEH Not used #12 Time base timer INT 13 FFFFC8H FFFFC9H FFFFCAH Not used #13 DTP0 (external interrupt #0)/end of UART3 reception INT 14 FFFFC4H FFFFC5H FFFFC6H Not used #14 DTP1 (external interrupt #1)/end of UART4 reception INT 15 FFFFC0H FFFFC1H FFFFC2H Not used #15 DTP2 (external interrupt #2)/end of UART3 transmission INT 16 FFFFBCH FFFFBDH FFFFBEH Not used #16 DTP3 (external interrupt #3)/end of UART4 transmission INT 17 FFFFB8H FFFFB9H FFFFBAH Not used #17 DTP4 to DTP7 (external interrupt #4 to 7) INT 18 FFFFB4H FFFFB5H FFFFB6H Not used #18 Output compare (channel 1) matching (I/O timer) INT 19 FFFFB0H FFFFB1H FFFFB2H Not used #19 End of UART2 reception INT 20 FFFFACH FFFFADH FFFFAEH Not used #20 End of UART1 reception INT 21 FFFFA8H FFFFA9H FFFFAAH Not used #21 Input capture (channel 3) fetching (I/O timer) Hardware interrupt None : 57 CHAPTER 3 INTERRUPTS Table 3.3-1 List of Interrupt Vectors (Continued) Software interrupt instruction Vector address L Vector address M Vector address H Mode register Interrupt No. INT 22 FFFFA4H FFFFA5H FFFFA6H Not used #22 Input capture (channel 2) fetching (I/O timer) INT 23 FFFFA0H FFFFA1H FFFFA2H Not used #23 Input capture (channel 1) fetching (I/O timer) INT 24 FFFF9CH FFFF9DH FFFF9EH Not used #24 Input capture (channel 0) fetching (I/O timer) INT 25 FFFF98H FFFF99H FFFF9AH Not used #25 8/16-bit PPG0 counter borrow INT 26 FFFF94H FFFF95H FFFF96H Not used #26 16-bit reload timer 2 to 0 INT 27 FFFF90H FFFF91H FFFF92H Not used #27 Watch prescaler INT 28 FFFF8CH FFFF8DH FFFF8EH Not used #28 Output compare (channel 0) matching (I/O timer) INT 29 FFFF88H FFFF89H FFFF8AH Not used #29 End of UART2 transmission INT 30 FFFF84H FFFF85H FFFF86H Not used #30 End of measurement by PWC timer/PWC timer overflow INT 31 FFFF80H FFFF81H FFFF82H Not used #31 End of UART1 transmission INT 32 FFFF7CH FFFF7DH FFFF7EH Not used #32 16-bit free-run timer (I/O timer) overflow INT 33 FFFF78H FFFF79H FFFF7AH Not used #33 End of UART0 transmission INT 34 FFFF74H FFFF75H FFFF76H Not used #34 8/16-bit PPG1 counter borrow INT 35 FFFF70H FFFF71H FFFF72H Not used #35 End of IEBus reception INT 37 FFFF68H FFFF69H FFFF6AH Not used #37 Start of IEBus transmission INT 38 FFFF64H FFFF65H FFFF66H Not used #38 None INT 39 FFFF60H FFFF61H FFFF62H Not used #39 End of UART0 reception INT 41 FFFF58H FFFF59H FFFF5AH Not used #41 Flash memory status INT 42 FFFF54H FFFF55H FFFF56H Not used #42 Delay interrupt : : : : : : INT 254 FFFC04H FFFC05H FFFC06H Not used #254 None INT 255 FFFC00H FFFC01H FFFC02H Not used #255 None 58 Hardware interrupt : 3.4 Hardware Interrupts 3.4 Hardware Interrupts A hardware interrupt suspends the program the CPU is executing in response to an interrupt request signal from an internal resource and transfers the control to a program that the user has defined for interrupt processing. ■ Overview of Hardware Interrupts A hardware interrupt occurs after comparing the interrupt level for an interrupt request with the interrupt level mask register (ILM) in the PS of the CPU and after referencing the contents of the I flag in the PS by hardware if the interrupt condition is satisfied. The CPU performs one of the following operations when a hardware interrupt occurs: • Saving data to the system stack of the PC, PS, AH, AL, PCB, DTB, ADB, and DPR registers in the CPU. • Setting the ILM in the PS register. The ILM is automatically set to the same level as the currently requesting interrupt level. • Incorporating the contents of the corresponding interrupt vector and branching to the interrupt vector. ■ Structure of Hardware Interrupts The processing related to a hardware interrupt can be classified into the following three structure elements: ❍ Internal Resources Interrupt permission bit, interrupt request bit: Control interrupt requests from a resource. ❍ Interrupt Controller ICR: Assigns an interrupt level, and evaluates the priority among simultaneous interrupt requests. ❍ CPU I and ILM: Compare the request interrupt level with the current level and distinguish between interrupt permission statuses. Microcode: Contains the steps for interrupt processing. The status of an internal resource is defined by the relevant resource control register, the status of the interrupt controller is defined by ICR, and the status of the CPU is defined by the value of CCR. For using a hardware interrupt, it is necessary to define these three structure parts in advance on the software level. For information on ICR, see the section entitled, "Expanded Intelligent I/O Service Interrupt Control Register (ICR)". The table of interrupt vectors referenced during interrupt processing is allocated to FFFC00H to FFFFFFH, and is shared by hardware and software interrupts. 59 CHAPTER 3 INTERRUPTS ■ Hardware Interrupt Request during Writing to the Internal Resource Area No hardware interrupt requests are accepted during writing to the internal resource area. This was implemented to prevent CPU malfunctions due to interrupt conflicts in connection with overwriting the interrupt control registers for each resource. The internal resource area represents the area allocated to the control register or data register of the internal resource rather than the I/O addressing area of 000000H to 0000FFH. Figure 3.4-1 Hardware Interrupt Request During Writing to the Internal Resource Area Write instruction to the internal resource area MOV A,#08 MOV io,A An interrupt request occurs MOV A,2000H No branching to the interrupt. Interrupt processing Branching to the interrupt ■ Interrupt Stop Instruction The F2MC-16LX is provided with an interrupt stop instruction that disables the detection of hardware interrupt requests. (See Section 2.6 "Interrupt Suppression Instructions and Prefix Codes".) ■ Multiple Interrupts The F2MC-16LX CPU supports multiple interrupts. If an interrupt with a higher level than a currently processed interrupt occurs, control is transferred to the interrupt with the higher level after finishing the currently executed instruction. After completing the execution of this interrupt, the control returns to the execution of the previous interrupt. If an interrupt with the same or a lower level occurs during interrupt processing, the new interrupt is put on hold until the currently processed interrupt is completed, unless the contents of the ILM are changed or the respective interrupt levels change by an instruction to change the I flag. The extended intelligent I/O service cannot be started multiple times simultaneously. While one instance of the extended intelligent I/O service is being processed, all other interrupt requests and extended intelligent I/O service requests are put on hold. 60 3.4 Hardware Interrupts ■ Saving a Register to the Stack Figure 3.4-2 Registers Saved to the Stack Word (16 bits) MSB LSB H SSP (Value of SSP before an interrupt occurs) A H A L D P R A D B D P B P C B P C P S SSP (Value of SSP after an interrupt occurs) L ■ Notes on the Use of Hardware Interrupts To avoid a malfunction during a hardware interrupt, it is necessary to clear the interrupt request flag before exiting the corresponding interrupt routine. When a specific register is read, interrupt request flags that refer to certain resources are cleared automatically. In this case, these registers are read and the interrupt request flag is cleared before exiting the interrupt routine. 61 CHAPTER 3 INTERRUPTS 3.4.1 Operation of Hardware Interrupts The internal resources for providing the hardware interrupt request feature include the interrupt request flag and interrupt permission flag. The interrupt request flag indicates whether an interrupt request is present. The interrupt permission flag indicates whether an interrupt request to the CPU by the corresponding internal resource is present. The interrupt request flag is set when a specific event occurs in an internal resource. Depending on permission by the interrupt permission flag, the resource generates an interrupt request to the interrupt controller. ■ Operations of Hardware Interrupts The interrupt controller compares the interrupt levels (ILs) in the ICR for all interrupt requests received at the same time, selects the request with the highest level (in other words, the value of the respective IL is lowest), and reports it to the CPU. If multiple requests have the same level, the request with the lowest interrupt number is prioritized. The relationship between interrupt requests and the ICR depends on the hardware. The CPU compares the received interrupt level (IL) with the ILM in the PS register. When the interrupt level (IL) is lower than the ILM and the I bit in the PS register is set to 1, the microcode for interrupt processing is processed after finishing the current instruction. At the beginning of processing the microcode for interrupt processing, the ISE bit in the ICR of the interrupt controller is referenced. After confirming that the ISE bit is set to 0 (this means an interrupt), the main part of interrupt processing is started. During the main part of interrupt processing, the 12 bytes of PS, PC, PCB, DTB, ADB, DPR, and A are saved to the memory area indicated by SSB and SSP. Three bytes from the interrupt vector are then loaded to PC and PCB. Branch processing is performed by updating the ILM in the PS to the level of the received interrupt request and setting the S flag to 1. Consequently, the instruction to be executed next is the interrupt processing program defined by the user. Figure 3.4-3 Occurrence and Release of Hardware Interrupts Register file F2MC-16LX bus Microcode F2MC-16LX PS ILM Check IR (6) (5) Comparison device (4) CPU AND Cause FF (7) (2) (1) Peripherals Interrupt level IL Peripherals Level comparison device (3) Permission FF 62 I Interrupt controller PS: Processor status I: Interrupt permission flag ILM: Interrupt level mask register IR: Instruction register 3.4 Hardware Interrupts The meanings of the items 1 to7 in Figure 3.4-3 "Occurrence and Release of Hardware Interrupts" are described below: 1. An interrupt cause occurs in one of the peripherals. 2. The interrupt permission bit in the peripheral device is referenced. If interrupt permission is set, an interrupt request from the peripheral to the interrupt controller is generated. 3. The interrupt controller that receives an interrupt request, evaluates the priority of simultaneous interrupt requests, and transfers the interrupt level corresponding to the relevant interrupt request to the CPU. 4. The CPU compares the interrupt level requested from the interrupt controller with the ILM bit in the processor status register. 5. When the comparison shows a higher priority level than for the currently processed interrupt, the content of the I flag in the same processor status register is checked. 6. When the check in 5 shows that the I flag is in interrupt permission status, the ILM bit is set to the requested level so that interrupt processing is performed immediately after the currently executed instruction is completed. Thereafter, control is transferred to the interrupt processing routine. 7. The interrupt request ends when the interrupt cause of item 1 is cleared by the interrupt processing routine defined by the user. The execution time for the interrupt processing steps performed by the CPU in item 6 and 7 is listed below. The time it takes to transfer to the interrupt sequence differs depending on the address to which the stack pointer points. ❍ Time required for the interrupt processing by CPU Delay before the CPU starts an interrupt sequence (The CPU does not start the interrupt sequence in the middle of the execution of an instruction.) ❍ Time required to execute an interrupt sequence Interrupt start : 24 + 6 times machine cycles according to Table 3.4-1 "Corrective Value of the Number of Cycles for Interrupt Processing" Interrupt recover: 15 + 6 times machine cycles according to Table 3.4-1 "Corrective Value of the Number of Cycles for Interrupt Processing" (RETI instruction) Table 3.4-1 Corrective Value of the Number of Cycles for Interrupt Processing Address to which the stack pointer points Corrective value of the number of cycles External area 8-bit data bus +4 External area even-numbered address +1 External area odd-numbered address +4 Internal area even-numbered address 0 Internal area odd-numbered address +2 63 CHAPTER 3 INTERRUPTS 3.4.2 Operating Flow for Hardware Interrupts Figure 3.4-4 "Operating Flow for Hardware Interrupts" shows the flow of operation for hardware interrupts. ■ Operating Flow for Hardware Interrupts Figure 3.4-4 Operating Flow for Hardware Interrupts I: Flag in CCR ILM: Level register in the CPU IF: Interrupt request of an internal resource IE: Interrupt enable flag of an internal resource ISE: EI2OS enable flag IL: Interrupt request level of an internal resource S: Flag in CCR I & IF & IE =1 AND ILM > IL YES NO NO YES ISE = 1 The next instruction is loaded and decoded PS, PC, PCB, DTB, ADB, DPR, and A is saved to the stack of SSP. Then ILM = IL. The extended intelligent I/O service is processed YES INT instruction NO PS, PC, PCB, DTB, ADB, DPR, and A is saved to the stack of SSP. Then I = 0, ILM = IL. A normal instruction is executed NO Repeating instructions of string system is completed YES PC is updated 64 S 1 The interrupt vector is loaded 3.4 Hardware Interrupts 3.4.3 Example of Procedure for Using Hardware Interrupts Figure 3.4-5 "Example of Procedure for Using Hardware Interrupts" shows an example of a procedure for using hardware interrupts. ■ Example of Procedure for Using Hardware Interrupts Figure 3.4-5 Example of Procedure for Using Hardware Interrupts Start (1) The system stack area is set (2) The internal resource is initialized (3) The ICR in the interrupt controller is set (4) The start of operations for the internal resource is set. The interrupt permission bit is set to permission. (5) ILM and I in PS are set Interrupt processing program Stack processing The control branches to the interrupt vector. (7) Processing by hardware (8) Processing for the interrupt of the internal resource (9) An interrupt cause is cleared (10) Interrupt recovery instruction (RETI) An interrupt (6) request occurs. The usage of the items 1 to 10 in Figure 3.4-5 "Example of Procedure for Using Hardware Interrupts" is as follows: 1. The system stack area is set. 2. The internal resource for generating an interrupt request is initialized. 3. The ICR in the interrupt controller is set. 4. The internal resource is set to start operation status. The interrupt permission bit is set to permission. 5. The ILM and I flags in the CPU are set in such a way that an interrupt is accepted. 6. A hardware interrupt request occurs due to an internal resource interrupt. 7. The respective register is saved by the interrupt processing hardware and the control branches to the interrupt processing program. 8. The processing for preventing interrupts in the internal resource is performed by the interrupt processing program. 9. The interrupt request of the internal resource circuit is released. 10.The interrupt recovery instruction is executed and the control is returned to the program that was executed before the branch. 65 CHAPTER 3 INTERRUPTS 3.5 Software Interrupts Software interrupts transfer the control from the execution of the program that is currently executed by the CPU to a program for interrupt processing that was defined by the user for this specific instruction. ■ Overview of Software Interrupts A software interrupt occurs when a software interrupt instruction is executed. performs one of the following types of processing when a software interrupt occurs: The CPU • Saving data of the PC, PS, AH, AL, PCB, DTB, ADB, and DPR registers in the CPU to the system stack. • Setting the I flag of the PS register. This automatically prohibits further interrupts. • Determining the value of the corresponding interrupt vector and branching the control to a processing according to the value. A software interrupt request issued by an INT instruction does not include an interrupt request flag or permission flag. Software interrupt requests are always issued due to the execution of an INT instruction. The INT instruction does not include an interrupt level. Therefore, the INT instruction does not update the ILM. The INT instruction clears the I flag and puts subsequent interrupt requests on hold. ■ Structure of Software Interrupts All software interrupts are processed by the CPU. ❍ CPU • Microcode: Interrupt processing step If a software interrupt is issued, it is necessary to execute the corresponding instruction. As shown in Table 3.3-1 "List of Interrupt Vectors" software interrupts share the interrupt vector area with hardware interrupts. For example, interrupt request number INT 13 is used to indicate not only external interrupt #0/end of UART3 reception as a hardware interrupt cause but also INT #13 as a software interrupt cause. Therefore, external interrupt #0/end of UART3 reception and INT #13 call the same interrupt processing routine. ■ Operation of Software Interrupts Execution of the microcode for software interrupt processing is started when the CPU loads and executes a software interrupt instruction. The microcode for software interrupt processing saves 12 bytes (PS, PC, PCB, DTB, ADB, DPR, and A) to the memory area indicated by SSB and SSP. Three bytes from the interrupt vector are then stored to PC and PCB according to the microcode. The I flag is reset (set to 0) and the S flag is set to 1. Consequently, the interrupt processing program defined by the user application program is executed next. 66 3.5 Software Interrupts Figure 3.5-1 Occurrence and Release of Software Interrupts (1) PS F2MC-16LX bus Register file I (2) Microcode F 2 M C - 1 6 LX C P U S B unit IR Queue Fetch PS: Processor status I: Interrupt permission flag ILM: Interrupt level mask register IR: Instruction register B unit: Bus interface unit Save Instruction bus RAM The meanings of the items 1 to 3 in Figure 3.5-1 "Occurrence and Release of Software Interrupts" are as follows: 1. The software interrupt instruction is executed. 2. The internal special CPU register defined by the register file is saved according to the microcode for the software interrupt instruction. 3. The interrupt processing ends by the RETI instruction in the user's interrupt processing routine. ■ Notes on Software Interrupts If the program bank register (PCB) is FFH, the vector area of the CALLV instruction overlaps to the table of the INT #vct8 instruction. When designing software, be sure that the CALLV instruction never uses the same address as the INT #vct8 instruction. 67 CHAPTER 3 INTERRUPTS 3.6 Expanded Intelligent I/O Service (EI2OS) The expanded intelligent I/O service (EI2OS), which automatically transfers data between an I/O and memory, is a hardware interrupt handling program. Interrupt handling programs ordinarily transfer data between I/O and memory, but the EI2OS can also transfer such data as DMA mode. However, the use of EI2OS is not passible with the REALOS real time operating system. ■ Overview of the Expanded Intelligent I/O Service (EI2OS) The expanded intelligent I/O service (EI2OS) provides the following advantages over conventional interrupt handling programs: • Reduction of the total program size because a transfer program does not have to be generated. • Improving the transfer rate, because as internal registers are not used for transfer, they do not have to be saved. • Avoiding unnecessary data transfers, because the I/O system can stop the transfer. • Capability of selecting increment, decrement, or non-updating of a buffer address • Capability of selecting increment, decrement, or non-updating of an I/O register address (at updating of a buffer address) Upon completion of the EI2OS, the CPU automatically branches to the interrupt handling routine after setting a termination condition. Therefore, the user can determine the type of the termination condition. The hardware for implementing the EI2OS is structured in two separate blocks, each of which contains the following register and descriptor: ❍ Interrupt control register This register is located in the interrupt controller and indicates an ISD address. ❍ Expanded intelligent I/O service descriptor This descriptor is located in RAM and contains information on the transfer mode, the I/O address, the number of transfers, and the buffer address. 68 3.6 Expanded Intelligent I/O Service (EI2OS) Figure 3.6-1 Overview of the Expanded Intelligent I/O Service Memory space by IOA I/O register ..................... I/O register Peripheral CPU Interrupt request (1) (3) (3) ISD by ICS (2) Interrupt control register Interrupt controller by BAP (4) Buffer by DCT (1) I/O requests a transfer. (2) The interrupt controller selects a descriptor. (3) The transfer source and destination are read from the descriptor. (4) Data is transferred between the I/O and the memory. (5) The interrupt factor is automatically cleared. Notes: - The area that can be specified by IOA is 000000H to 00FFFFH. - The area that can be specified by BAP is 000000H to FFFFFFH. - The maximum number of transfers that can be specified in DTC is 65536. ■ Configuration of the Expanded Intelligent I/O Service (EI2OS) The mechanism of the EI2OS consists of the following four parts: ❍ Built-in resources • Interrupt enable bit and interrupt request bit: Control interrupt requests from resources. ❍ Interrupt controller • ICR: Assigns levels to interrupts, determines a priority of simultaneously requested interrupts, and selects EI2OS operation. ❍ CPU • I and ILM: Compare the requested interrupt level against the current level and determine the status of interrupt capability. • Micro-code: for EI2OS processing step ❍ RAM • Descriptor: Describes the transfer information for the EI2OS. 69 CHAPTER 3 INTERRUPTS 3.6.1 Interrupt Control Register (ICR) The interrupt control register is located in the interrupt controller, which corresponds to all I/Os that support interrupt functions. The interrupt control register has the following three functions: • Specifying an interrupt level for the corresponding peripheral resource. • Selecting whether the interrupts of the corresponding peripheral should be handled as normal interrupts or by the expanded intelligent I/O service. • Selecting a channel for the expanded intelligent I/O service. Do not access this register with read-modify-write instructions, as this may cause a malfunction. ■ Interrupt Control Register (ICR) Figure 3.6-2 Interrupt Control Register (ICR) Interrupt control register (ICR) 15/7 14/6 13/5 12/4 11/3 10/2 Address: B0H to BFH ICS3 ICS2 ICS1 ICS0 ISE IL2 IL1 IL0 (W) (0) (W) (0) (W) (0) (W) (0) (W) (0) (W) (1) (W) (1) (W) (1) 15/7 14/6 13/5 12/4 11/3 10/2 S1 S0 ISE IL2 IL1 IL0 (R) (0) (R) (1) (R) (1) (R) (1) Read/write Initial value Address: B0H to BFH Read/write Initial value (-) (X) (-) (X) (R) (0) (R) (0) 9/1 9/1 8/0 8/0 Bit No. When writing Bit No. When reading Note: ICS3 to ICS0 are effective only when the EI2OS is executed. Set the ISE to 1 when executing the EI2OS, and to 0 otherwise. When the EI2OS is not executed, ICS3 to ICS0 may have any value. ICS1 and ICS0 are effective only during writing, while S1 and S0 are effective only during reading. [Bits 15 to 12 and 7 to 4] ICS3 to ICS0 (EI2OS channel selection bits) The bits ICS3 to ICS0 are the channel selection bits for EI2OS. These bits are write only and specify a channel for the EI2OS. The value in these bits determines the address of an expanded intelligent I/O service descriptor in the memory. The ICS is initialized to 0000 by a reset. 70 3.6 Expanded Intelligent I/O Service (EI2OS) Table 3.6-1 ICS3 to ICS0 (EI2OS Channel Selection Bits) ICS3 ICS2 ICS1 ICS0 Channel to be selected Descriptor address 0 0 0 0 0 000100H 0 0 0 1 1 000108H 0 0 1 0 2 000110H 0 0 1 1 3 000118H 0 1 0 0 4 000120H 0 1 0 1 5 000128H 0 1 1 0 6 000130H 0 1 1 1 7 000138H 1 0 0 0 8 000140H 1 0 0 1 9 000148H 1 0 1 0 10 000150H 1 0 1 1 11 000158H 1 1 0 0 12 000160H 1 1 0 1 13 000168H 1 1 1 0 14 000170H 1 1 1 1 15 000178H [Bits 13, 12, 5, and 4] S0 and S1 (EI2OS status bits) S0 and S1 are the EI2OS termination status bits. S0 and S1 are read only and allow to determine the termination condition for the termination of the EI2OS. They are initialized to 00 by a reset. Table 3.6-2 Termination Conditions within the Status of the Expanded Intelligent I/O Service S1 S0 Termination condition 0 0 During operation of the EI2OS or when not executing it 0 1 Stopped by count-out 1 0 Reserved 1 1 Stopped by request from a built-in resource 71 CHAPTER 3 INTERRUPTS [Bits 11 and 3] ISE (EI2OS enable bits) The ISE bit specifies whether the EI2OS can be used. If this bit is 1 when an interrupt request occurs, the EI2OS is executed; if it is 0, the interrupt sequence is executed instead. Also, when the EI2OS is terminated by a count-out or request from the built-in resource, the ISE bit becomes 0. When a corresponding built-in resource does not support the EI2OS function, set the ISE by software to 0. This bit is readable and writable and is initialized to 0 by a reset. [Bits 10 to 8 and 2 to 0] IL0, IL1, and IL2 (Interrupt level setting bits) The IL0, IL1, and IL2 bits specify an interrupt level. These bits specify the interrupt level of the corresponding built-in resource. readable and writable. They are initialized to level 7 (no interrupt) by a reset. Table 3.6-3 Level Settings of Interrupt Level Set Bits 72 IL2 IL1 IL0 Interrupt level 0 0 0 0 (Highest interrupt level) 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 (Lowest interrupt level) 1 1 1 7 (No interrupt) They are 3.6 Expanded Intelligent I/O Service (EI2OS) 3.6.2 Expanded Intelligent I/O Service Descriptor (ISD) The expanded intelligent I/O service descriptor is located in internal RAM between 000100H and 00017FH. The descriptor contains: • Control data for data transfer • Status data • A buffer address pointer ■ Expanded Intelligent I/O Service Descriptor (ISD) The expanded intelligent I/O service descriptor (ISD) is located in internal RAM between 000100H and 00017FH. The descriptor contains: • Control data for data transfer • Status data • A buffer address pointer Figure 3.6-3 "Structure of the Expanded Intelligent I/O Service Descriptor" shows the structure of the expanded intelligent I/O service descriptor. Figure 3.6-3 Structure of the Expanded Intelligent I/O Service Descriptor Eight high-order bits of the data counter (DCTH) H Eight low-order bits of the data counter (DCTL) Eight high-order bits of the I/O address pointer (IOAH) Eight low-order bits of the I/O address pointer (IOAL) EI2OS status (ISCS) Eight high-order bits of the buffer address pointer (BAPH) 000100H + 8 x ICS ISD head address Eight medium-order bits of the buffer address pointer (BAPM) Eight low-order bits of the buffer address pointer (BAPL) L 73 CHAPTER 3 INTERRUPTS ■ Data Counter (DCT) The DCT is a 16-bit register that functions as a counter of the number of transferred data elements. This counter is decremented by one before the transfer of a data element. When this counter becomes 0, the EI2OS terminates. Figure 3.6-4 Structure of the Data Counter (DTC) High-order byte of the data counter Initial value Low-order byte of the data counter Initial value 9 8 Bit No. B10 B09 B08 DCTH (X) (X) (X) 15 14 13 12 11 10 B15 B14 B13 B12 B11 (X) (X) (X) (X) (X) 7 6 B07 (X) 5 B06 (X) 4 B05 3 B04 (X) 2 B03 (X) 1 B02 (X) B01 (X) Bit No. 0 DCTL B00 (X) (X) ■ I/O Register Address Pointer (IOA) The I/O register address pointer (IOA) is a 16-bit register that indicates the lower address (A15 to A0) of the I/O register that transfers data to or from the buffer. Because the upper part of the register address (A23 to A16) is all 0s, the pointer can specify any I/O register between 000000H and 00FFFFH. Figure 3.6-5 Structure of the I/O Register Address Pointer (IOA) High-order byte of the I/O address pointer Initial value Low-order byte of the I/O address pointer 8 Bit No. A10 A09 A08 IOAH (X) (X) (X) 14 13 12 11 10 A15 A14 A13 A12 A11 (X) (X) (X) (X) (X) 7 Initial value 9 15 6 5 4 3 2 1 Bit No. 0 A07 A06 A05 A04 A03 A02 A01 A00 (X) (X) (X) (X) (X) (X) (X) (X) IOAL ■ EI2OS Status Register (ISCS) The EI2OS status register (ISCS) is an eight-bit register that indicates an updating mode (increment or decrement), the format of transferred data (byte or word), and the data transfer direction between the buffer address pointer and the I/O register address pointer. Also, this register indicates whether the buffer address pointer and I/O register address pointer has been updated or left unchanged. Figure 3.6-6 Configuration of EI2OS Status Register (ISCS) EI2OS status register (ISCS) 7 6 5 Reserved Reserved Reserved Read/write Initial value (-) (X) (-) (X) (-) (X) 4 3 2 1 IF BW BF DIR SE (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) [Bits 7 to 5] Reserved bits. Always set these bits to 0 when setting the ISCS. 74 0 Bit No. 3.6 Expanded Intelligent I/O Service (EI2OS) [Bit 4] IF The IF bit indicates whether the I/O register address pointer has been updated or fixed. Table 3.6-4 Updated/unchanged Specification Bit for the I/O Register Address Pointer (IF) IF Function 0 The I/O register address pointer is updated (incremented) after data transfer. 1 The I/O register address pointer is fixed after data transfer. [Bit 3] BW The BW bit indicates the transfer data length. Table 3.6-5 Bit Specifying the Transfer Data Length (BW) BW Function 0 Byte 1 Word [Bit 2] BF The BF bit specifies whether the buffer address pointer has been updated or fixed. Table 3.6-6 Updated/unchanged Specification Bit for Buffer Address Pointer (BF) BF Function 0 The buffer address pointer is updated incremonted after data transfer. 1 The buffer address pointer is fixed after data transfer. Note: When the buffer address pointer is updated, only the lower 16 bits change. [Bit 1] DIR The DIR bit indicates the direction of the data transfer. Table 3.6-7 Setting of the Data Transfer Direction Bit (DIR) DIR Setting 0 I/O address pointer ---> Buffer address pointer 1 Buffer address pointer ---> B/O address pointer 75 CHAPTER 3 INTERRUPTS [Bit 0] SE The SE bit controls the termination of the expanded intelligent I/O service by requests from the built-in resource. Table 3.6-8 EI2OS Termination Control Bit SE Setting 0 Service is terminated by a request from the built-in resource. 1 Service is not terminated by a request from the built-in resource. ■ Buffer Address Pointer (BAP) The buffer address pointer is a 24-bit register for storing the address to be used next by the EI2OS. A separate BAP exists for each channel of the EI2OS, so each channel of EI2OS can transfer data to any address within the 16 MB space. Note: When the BF bit of ISCS is set to "0" (update), only the lower 16 bits of BAP change while BAPH does not change. 76 3.6 Expanded Intelligent I/O Service (EI2OS) 3.6.3 Operation of the Expanded Intelligent I/O Service (EI2OS) Figure 3.6-7 "Operational Flow of the Extended Intelligent I/O Service (EI2OS)" shows the operational flow of the expanded intelligent I/O service (EI2OS), while Figure 3.6-8 "Procedural Flow of the Expanded Intelligent I/O Service (EI2OS)" shows the procedural flow of the expanded intelligent I/O service (EI2OS). ■ Operational Flow of the Expanded Intelligent I/O Service (EI2OS) Figure 3.6-7 Operational Flow of the Extended Intelligent I/O Service (EI2OS) An interrupt request is issued from a built-in resource. ISE=1 NO BAP: Buffer address pointer IOA: I/O register address pointer ISD: EI2OS descriptor ISCS: EI2OS status DCT: Data counter ISE: EI2OS enable bit S1 and S0: EI2OS termination status YES Read ISD/ISCS Interrupt sequence YES Termination request from the built-in resource YES DIR=1 NO Data specified by IOA (data transfer) Memory specified by BAP IF=0 NO BF=0 NO Decrement DCT DCT=00 NO YES SE=1 NO NO Data specified by BAP (data transfer) Memory specified by IOA YES The updated value depends on the BW. Update IOA YES The updated value depends on the BW. Update BAP (-1) YES Set 01 to S1 and S0 Set 11 to S1 and S0 Set 00 to S1 and S0 Clear the interrupt request from the resource Return to CPU operation Set ISE to 0 (clear) Interrupt sequence 77 CHAPTER 3 INTERRUPTS Figure 3.6-8 Procedural Flow of the Expanded Intelligent I/O Service (EI2OS) Processing by software Processing by hardware Start System stack area setting Initial setting EI2OS descriptor setting Initial setting of built-in resource Setting of ICR in the interrupt controller Setting for start of operating the built-in resource Setting of interrupt enable bit Setting ILM and I in the PS Executing the user program S1,S0= '00' (Interrupt request) and (ISE = 1) Data transfer No Determine whether to branch to an interrupt depending on a count-out or request from the resource Branch to interrupt vector Yes Reset of expanded intelligent I/O service (Including channel switching) Data processing in the buffer RETI 78 S1,S0= '01' or S1,S0= '11' 3.6 Expanded Intelligent I/O Service (EI2OS) 3.6.4 Execution Time of the Expanded Intelligent I/O Service (EI2OS) The execution time of the expanded intelligent I/O service (EI2OS) can be structured into three types: • During data transfer (while no termination condition is satisfied) • At a termination request from the resource • At a count-out ■ Execution Time of the Expanded Intelligent I/O Service (EI2OS) ❍ During data transfer (while no termination condition is satisfied) (Table 3.6-9 "Execution Time of EI2OS During Data Transfer" + Table 3.6-10 "Compensation Value for data Transfer in the Execution Time of EI2OS") machine cycles Table 3.6-9 Execution Time of EI2OS During Data Transfer Bit SE of ISCS Set "0" I/O address pointer Set "1" Fixed Updated Fixed Updated Fixed 32 34 33 35 Updated 34 36 35 37 Buffer address pointer ❍ In case of a termination request from the resource (36 + 6 x Table 3.4-1 "Corrective Value of the Number of Cycles for Interrupt Processing") machine cycles 79 CHAPTER 3 INTERRUPTS ❍ In case of a count-out (Table 3.6-9 "Execution Time of EI2OS During Data Transfer" + Table 3.6-10 "Compensation Value for data Transfer in the Execution Time of EI2OS" + (21 + 6 x Table 3.4-1 "Corrective Value of the Number of Cycles for Interrupt Processing")) machine cycles Table 3.6-10 Compensation Value for data Transfer in the Execution Time of EI2OS Internal access External access I/O address pointer Buffer address pointer Odd B/even 8/odd Internal access B/even 0 +2 +1 +4 Odd +2 +4 +3 +6 External access B/even +1 +3 +2 +5 8/odd +4 +6 +5 +8 B: Byte data transfer 8: Word transfer for 8-bit external bus Even: Word transfer for even address Odd: Word transfer for odd address 80 B/even 3.7 Exceptions because of Executing Undefined Instructions 3.7 Exceptions because of Executing Undefined Instructions When an undefined instruction is executed in the F2MC-16LX, an exception occurs and exception processing is initiated. The exception processing is basically the same as the processing for an interrupt. When an exception within the instructions is detected, the control is transferred from normal processing to exception processing. Generally, exception processing is a result of an unpredicted operation. Therefore, use it only for debugging, for software recovery in an emergency, and similar cases. ■ Occurrence of Exceptions because of Executing Undefined Instructions The F2MC-16LX handles all codes not defined in the instruction map as undefined instructions. When an undefined instruction is executed, the same type of processing as for the software interrupt instruction, "INT 10", is performed. In other words, after saving the contents of AL, AH, DPR, DTB, ADB, PCB, PC, and PS to the system stack, the control sets the I flag to 0, sets the S flag to 1, and then branches to the routine specified by the vector of interrupt number 10. The PC contents saved to the stack consist of the address where the undefined instruction is stored. If an undefined code was detected for an instruction code of two or more bytes, the PC value indicates the address where the undefined code is stored. Therefore, it is possible but ineffectual to recover the system with an RETI instruction because the same exception will occur again. 81 CHAPTER 3 INTERRUPTS 82 CHAPTER 4 GENERATING AND RESETTING CLOCKS This chapter describes clock and reset functions and operations. 4.1 "Clock Generator" 4.2 "Reset Causes" 4.3 "Operation after a Reset Is Released" 83 CHAPTER 4 GENERATING AND RESETTING CLOCKS 4.1 Clock Generator The clock generator controls internal clock operations such as the sleep, watch, and stop modes and the PLL clock multiplication function. This internal clock is called the machine clock. One cycle of the machine clock is used as a machine cycle. The clock generated by OSC oscillation is called the main clock. The clock generated by internal VCO oscillation is called the PLL clock. ■ Notes as to the Clock Generator When the operating voltage is 5 V, the OSC oscillation frequency range is from 3 to 16 MHz, but the maximum operating frequency of the CPU and peripheral circuits is 16 MHz. If the frequency generated by the specified multiplication factor exceeds the maximum operating frequency, the CPU and peripheral resource circuits do not operate normally. For example, if the OSC oscillation frequency is 16 MHz, only 1 can be specified as the multiplication factor. The minimum operating frequency of VCO oscillation is 4 MHz. Any frequency less than this frequency cannot be specified. Figure 4.1-1 Clock Generator Block Diagram S Reset S Interrupt HST Transition to the watch or sleep mode Q Q Machine clock Machine clock selection R R S Transition to the stop mode Q R 1 2 3 4 PLL multiplication Oscillation stabilization time selection Time-based timer 1/2 X0 / X1 1/2048 1/4 1/4 1/8 Watchdog interval selection Monitoring timer Watchdog reset 84 4.2 Reset Causes 4.2 Reset Causes The five types of reset causes are as follows: • Occurrence of a power-on reset • Release of the hardware standby state • Watchdog timer overflow • Occurrence of an external reset request by the RST pin • Occurrence of a reset request by software ■ Reset Causes When the stop mode is released or a power-on reset occurs, operation starts after the oscillation stabilization time has elapsed. When a reset cause occurs, the F2MC-16LX immediately stops executing the current processing and enters the reset release wait state. The machine clock and watchdog function initial states differ depending on the reset cause. The reset cause bits in the watchdog control register can be checked to determine the reset cause. Note: Because the external reset input is sampled in synchronization with the internal clock in other than the stop mode, no reset input is accepted when the externally supplied clock stops. When the external bus is used and a reset cause occurs, the address generated by each device during reset is undefined. External bus access signals such as RD and WR become inactive. Table 4.2-1 Reset Causes Machine clock Reset at sub clock at PLL clock Watch-dog timer Main clock * Stop Yes Cause Oscillation stabilization wait Power-on When the power is turned on Main clock * Hardware standby "L" level input to HST pin Main clock * Main clock * Stop Yes Watch-dog timer Watch-dog timer overflow Main clock * Main clock * Stop Yes External pin "L" level input to RST pin Main clock * or PLL clock PLL clock Previous status maintained No Software 0 written to the RST bit in the LPMCR register Main clock * or PLL clock PLL clock Previous status maintained No *: fOSC/2 (fOSC: the source oscillation) • When the reset input is received in the stop or hardware standby mode, the oscillation stabilization time is required for any reset cause. • The oscillation stabilization time required for a power-on reset is fixed to 218 cycles of OSC oscillation. The oscillation stabilization time required for another reset is determined by WS1 and WS0 in the clock selection register. 85 CHAPTER 4 GENERATING AND RESETTING CLOCKS There is a flip-flop corresponding to each reset cause. The status of each flip-flop can be checked by reading the watchdog control register. To identify the reset cause after releasing a reset, processing must be branched to an appropriate program after the value read from the watchdog control register is processed by software. Figure 4.2-1 Reset Cause Bit Block Diagram HST pin HST=L Power-on RST pin H RST bit set External reset request detection circuit Hardware standby release detection circuit Power-on detection circuit Not cleared periodically RST=L Watchdog timer reset detection circuit LPMCR.RST bit write detection circuit WTC register S S R R F/F F/F S R R S R S F/F Delay circuit F/F F/F WTC register read F2MC-16LX internal bus When multiple reset causes occur, the corresponding reset cause bits in the watchdog control register are set. When external reset request and watchdog reset occur simultaneously, both the ERST and WRST bits are set to 1. This rule does not apply to a power-on reset. Because when the PONR bit is 1, the values of other bits do not indicate normal reset causes, a software program must be created that ignores the values of other bits when the PONR bit is 1. Table 4.2-2 Correspondence between the Reset Causes and the Values of the Reset Cause Bits Reset cause PONR STBR WRST ERST SRST Power-on 1 - - - - Hardware standby * 1 * * * Watchdog timer * * 1 * * External pin * * * 1 * RST bit * * * * 1 *: The value before reset is retained. Note: The reset cause bits are cleared only when the watchdog control register is read. The reset cause bit corresponding to a reset cause that occurred once remains set to 1 when another reset cause occurs. For the configuration of the watchdog control register and the reset cause bits, see Chapter 9 "WATCHDOG TIMER". 86 4.3 Operation after a Reset is Released 4.3 Operation after a Reset is Released When a reset cause is removed, the F2MC-16LX immediately outputs the address at which the reset vector is stored and fetches the reset vector and mode data. A 4-byte area at FFFFDCH to FFFFDFH is allocated for the reset vector and mode data. The reset vector and mode data are transferred to corresponding registers by hardware after the reset is released. ■ Operation after a Reset is Released Use the mode pins to specify the internal ROM or external memory from which to read the reset vector and mode data. Because when the external vector mode is specified using the mode pins, the reset vector and mode data are read from the external memory not the internal ROM, when the microcontroller is to be used in the single chip mode or internal ROM and external bus mode, it is recommended to specify the internal vector mode using the mode pins. The bus mode after reading the reset vector and mode data is specified by mode data. Figure 4.3-1 Locations and Destinations of the Reset Vector and of Mode Data F2MC-16LX core Mode Memory space register FFFFDF Mode data FFFFDE Bits 23 to 16 of the reset vector FFFFDD Bits 15 to 8 of the reset vector FFFFDC Bits 7 to 0 of the reset vector Micro ROM Reset sequence PCB PC Note: The contents of the mode register are undefined immediately after reset. Store desired mode data in memory space in advance to ensure that a write operation can always be performed. 87 CHAPTER 4 GENERATING AND RESETTING CLOCKS ■ Registers not Initialized by Reset Input This microcontroller contains registers initialized only by a power-on reset. Table 4.3-1 "Registers not Initialized by Reset Input" lists registers not initialized by each reset cause. Table 4.3-1 Registers not Initialized by Reset Input CKSCR WTC LPMCR Type of reset WS1 WS0 MCS CS1 CS0 WDCS CG1 CG0 Software reset (Only RST is used.) N N N N N N N N Watchdog reset N N Y N N N Y Y Power-on reset Y Y Y Y Y Y Y Y Main mode N N Y N N N Y Y Sub mode Y Y Y Y Y Y Y Y Hardware standby WS1 and WS0: Set the oscillation stabilization time for the main clock. MCS: Specifies the machine clock (0 = PLL clock or 1 = main clock). CS1 and CS0: Set the multiplication factor for the PLL clock. WDCS: Specifies the input clock source for the watchdog timer (0 = watch timer or 1 = time base timer). Y: Initialized N: Not initialized In particular, handle the MCS bit carefully because it sets the machine clock. For example, if power-on does not satisfy the power-on reset specification, no power-on reset occurs. For this reason, the internal operating frequency may become outside the valid operation range, because MCS is not initialized, and the microcontroller may not operate normally. If the CPU crashes for some reason and MCS, CS1, or CS0 is rewritten, the internal operating frequency may also become outside the valid operation range. The microcontroller may not be able to recover normally from this status by RST input only (however, if the internal watchdog state occurs, MCS is initialized and the microcontroller operates normally). When either of the above cases occurs, use of HST plus RST (connecting HST and RST with a jumper) is recommended. Table 4.3-2 "Registers not Initialized by Reset Input" lists registers that are not initialized by reset input using HST plus RST. Note that the operation status after the reset is released differs depending on the reset input type, HST plus RST reset input, or only RST input, as listed in Table 4.3-2 "Registers not Initialized by Reset Input". Table 4.3-2 Registers not Initialized by Reset Input CKSCR WTC LPMCR Type of reset HST + RST WS1 WS0 MCS CS1 CS0 WDCS CG1 CG0 Main mode N N Y N N N Y Y Sub mode * Y Y Y Y Y Y Y Y Y: Initialized N: Not initialized *: Including the sub mode transition period. 88 4.3 Operation after a Reset is Released Figure 4.3-2 Operation Transition by Reset Input [Operation Transition by Reset Input] Reset input (RST, HST + RST) A. Oscillation status Oscillating Status Main Oscillating Sub Oscillating Only RST used (HST ="H") Main HST + RST used Oscillating Stopped Waiting for main clock oscillation stabilization Main clock operation enabled Waiting for subclock oscillation stabilization Sub Subclock operation enabled B. Execution timing (L: Stop, H: Start) Only RST used (HST ="H") HST + RST used Main clock mode Oscillation stabilization time set before reset input 2 main clock cycles when subclock mode requested. During the main clock operation, writing to SCS bits is possible. Subclock mode 216 cycles of subclock oscillation (32 kHz) (about 2 s) Power-on reset Vcc (power supply) Oscillating Power-on reset Main Sub Status Oscillating Stopped Waiting for main clock oscillation stabilization Main clock operation enabled Waiting for subclock oscillation stabilization Subclock operation enabled Oscillation stabilization time of 218main clock cycles Main mode Sub mode 2 main clock cycles when subclock mode requested. During the main clock operation, writing to SCS bits is possible. 216 cycles of subclock oscillation (32 kHz) (about 2 s) 89 CHAPTER 4 GENERATING AND RESETTING CLOCKS 90 CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT This chapter describes the functions and operation of the low-power consumption control circuit (intermittent CPU operation function, oscillation stabilization time, and clock multiplication function). 5.1 "Overview of the Low-power Consumption Control Circuit" 5.2 "Low-power Consumption Mode Control Register (LPMCR)" 5.3 "Clock Selection Register (CKSCR)" 5.4 "Operation of the Low-power Consumption Control Circuit" 5.5 "Intermittent CPU Operation Function" 5.6 "Setting the Oscillation Stabilization Time for the Main Clock" 5.7 "Switching the Machine Clock" 5.8 "Status Transition" 5.9 "Status Transition Diagrams for Low Power-Consumption Modes" 91 CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT 5.1 Overview of the Low-power Consumption Control Circuit The operating modes are as follows: • PLL clock mode • PLL sleep mode • PLL watch mode • Pseudo watch mode • Main clock mode • Main sleep mode • Stop mode • Sub clock mode • Sub sleep mode • Watch mode • Hardware standby mode Operating modes other than the PLL clock mode are classified as low-power consumption modes. ■ Overview of the Low-power Consumption Control Circuit ❍ Main clock mode and main sleep mode The microcontroller only operates using the oscillation clock (OSC oscillation). The main clock is used as the operating clock and the PLL clock (VCO oscillation) is stopped. ❍ PLL sleep mode and main sleep mode Only the CPU operating clock is stopped. Clocks other than the CPU clock are operating. ❍ Watch mode Only the time-based timer is operating. ❍ Stop mode and hardware standby mode Oscillation is stopped. Data can be retained with the lowest power consumption. The intermittent CPU operation function intermittently operates the clock supplied to the CPU when registers, internal memory, internal peripherals, and the external bus are accessed. Processing can be performed with low-power consumption because the CPU execution speed is lowered by the above intermittent operation while supplying the internal peripherals with a high-speed clock. A PLL clock multiplication factor can be selected among 1, 2, 3, and 4 using the CS1 and CS0 bits in the clock selection register. The WS1 and WS0 bits can be used to set the oscillation stabilization time for the main clock required when the stop or hardware standby mode is released. 92 5.1 Overview of the Low-power Consumption Control Circuit Note: When the clock mode is switched, do not switch to low power consumption mode and other clock mode before this switching is completed. Confirm the completion of clock mode switching by referring to the MCM and SCM bits of the clock selection register (CKSCR). If the mode is switched to another clock mode or low power consumption mode before completion of switching, the mode may not be switched. Figure 5.1-1 Registers in the Low-power Consumption Control Circuit Low-power consumption mode control register Address: 0000A0H 7 6 5 4 STP SLP SPL RST Read/write Initial value (W) (0) (W) (0) (R/W) (0) (W) (1) Clock selection register Address: 0000A1H Read/write Initial value 3 2 1 0 TMD CG1 CG0 - (-) (1) (R/W) (0) (R/W) (0) (-) (0) 15 14 13 12 11 10 9 8 SCM MCM WS1 WS0 SCS MCS CS1 CS0 (-) (1) (R) (1) (R/W) (1) (R/W) (1) (-) (1) (R/W) (1) Bit No. LPMCR Bit No. CKSCR (R/W) (R/W) (0) (0) 93 CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT ■ Block Diagram of the Low-power Consumption Control Circuit Figure 5.1-2 Block Diagram of the Low-power Consumption Control Circuit and Clock Generator 1/4 Subclock switch controller 1/2 PLL multiplication circuit diveding by 4 Subclock (oscillation by OSC) diveding by 2 Main clock (oscillation by OSC) CPU clock generator 0/9/17/33 Intermittent cycle selection 1/4 CPU clock selector F2MC-16LX bus CPU clock Cycle count selector for intermittent CPU operation Peripheral clock generator Stopping of main clock OSC Stopping of subclock OSC Standby control circuit Release Peripheral clock HST activation HST pin 10 Oscillation stabilization time selector 2 Clock input 213 215 Time-based timer 217* Pin high-impedance controller Internal reset generator 1/2 Interrupt request or RST Pin Hi-z RST pin Internal RST To the watchdog timer *: It is set to 218 when the power is turned on. 94 5.2 Low-power Consumption Mode Control Register (LPMCR) 5.2 Low-power Consumption Mode Control Register (LPMCR) The low-power consumption mode control register (LPMCR) sets various types of power consumption-related operating modes together with the clock selection register. ■ Low-power Consumption Mode Control Register (LPMCR) Figure 5.2-1 Register in the Low-power Consumption Control Circuit Low-power consumption mode control register Address: 0000A0H 7 6 5 4 3 2 STP SLP SPL RST TMD CG1 Read/write Initial value (W) (0) (W) (0) (R/W) (0) (W) (1) (R/W) (R/W) (1) (0) 1 Bit No. 0 CG0 Reserved (R/W) (0) LPMCR (-) (0) ❍ Notes on Accessing the low-power Consumption Mode Control Register Writing the low-power consumption mode control register causes a transition to a low-power consumption mode (stop or sleep mode). Use an instruction listed in Table 5.2-1 "Instructions to be used to Cause A Transition to a Low-power Consumption Mode" for such a transition. Causing a transition to a low-power consumption mode using another instruction may result in a malfunction. Any instruction can be used to control a function of the low-power consumption mode control register other than the function that causes the transition to a low-power consumption mode. Write word data in the low-power consumption mode control register at an even address. A transition to the low-power consumption mode by writing data at an odd address may result in a malfunction. Table 5.2-1 Instructions to be used to Cause A Transition to a Low-power Consumption Mode MOV io,#imm8 MOV io,A MOV @RLi+disp8,A MOVW io,#imm16 MOVW io,A MOVW @RLi+disp8,A SETB io : bp CLRB io : bp MOV dir,#imm8 MOV dir,A MOV eam,#imm8 MOV addr16,A MOV eam,Ri MOV eam,A MOVW dir,#imm16 MOVW dir,A MOVW eam,#imm16 MOVW addr16,A MOVW eam,RWi MOVW eam,A SETB dir : bp CLRB dir : bp SETB addr16 : bp CLRB addr16 : bp [Bit 7] STP Writing 1 to the STP bit causes a transition to the pseudo watch mode (CKSCR:MCS = 0 & SCS=1) or the stop mode (CKSCR:MCS=1 or SCS=0). Writing 0 performs no operation. When a reset occurs or the watch or stop mode is released, this bit is cleared to 0. This bit is a write-only bit. The read value is always 0. 95 CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT [Bit 6] SLP Writing 1 in SLP causes a transition to the sleep mode. Writing 0 performs no operation. When a reset occurs or the sleep or stop mode is released, this bit is cleared to 0. Writing 1 to the STP and SLP bits simultaneously causes a transition to the pseudo watch mode or the stop mode. This bit is a write-only bit. The read value is always 0. [Bit 5] SPL When SPL is 0, the external pin levels are retained in the watch or stop mode. When it is 1, the external pins are set to high impedance in the watch or stop mode. When a reset occurs, this bit is cleared to 0. This bit is a read/write bit. [Bit 4] RST Writing 0 in the RST bit generates the internal reset signal for three machine cycles. Writing 1 performs no operation. When this bit is read, the value is 1. [Bit 3] TMD Two clocks system Writing 0 in the TMD bit causes a transition to the watch mode. Writing 1 in this bit creates no operation. When a reset occurs or the watch or stop mode is released, this bit is cleared to 0. This bit is a write-only bit. The read value is always 1. One clock system Always write 1. [Bits 2 and 1] CG1 and CG0 The CG1 and CG0 bits set the temporary stop cycle count for the intermittent CPU operation function. When a reset occurs as a result of power-on, hardware standby, or watchdog, these bits are initialized to 00 but are not initialized by a reset caused by another reset cause. These bits are read/write bits. The intermittent CPU operation function stops the clock supplied to the CPU for the specified time and delays the start of the internal bus cycle in the following case: When registers, internal memory, internal peripherals, and the external bus are accessed Processing can be performed with low-power consumption because the CPU execution speed is lowered by supplying the internal peripherals with a high-speed clock. [Bit 0] Reserved This bit must be set to "0". Table 5.2-2 Settings of the Low Power-Consumption Mode Control Register (CG1 and CG0 Bits) 96 CG1 CG0 Temporary stop cycle count for the CPU clock 0 0 0 cycle (CPU clock = peripheral clock) 0 1 9 cycles (CPU clock:periperal clock = 1:about 3 to 4) 1 0 17 cycles (CPU clock:periperal clock = 1:about 5 to 6) 1 1 33 cycles (CPU clock:periperal clock = 1:about 9 to 10) 5.3 Clock Selection Register (CKSCR) 5.3 Clock Selection Register (CKSCR) The clock selection register (CKSCR) sets and controls the CPU machine clock and sets the oscillation stabilization time required at power-on or oscillation recovery. ■ Clock Selection Register (CKSCR) Figure 5.3-1 Clock Selection Register (CKSCR) Clock selection register 15 14 13 12 11 10 9 8 Address: 0000A1H SCM MCM WS1 WS0 SCS MCS CS1 CS0 Read/write Initial value (R) (1) (R) (1) (R/W) (1) (R/W) (1) (R/W) (R/W) (1) (1) Bit No. CKSCR (R/W) (R/W) (0) (0) [Bit 15] SCM Two clocks system The SCM bit indicates whether the main clock or the subclock is selected as the machine clock. When this bit is 0, it indicates that the subclock is selected. When this bit is 1, it indicates that the main clock is selected. When the SCS bit is 0 and the SCM bit is 1, this is an indication that the machine clock is being switched from the main clock to the subclock. When the SCS bit is 1 and the SCM bit is 0, this is an indication that the machine clock is being switched from the subclock to the main clock. One clock system The read value is always 1. [Bit 14] MCM This bit indicates whether the main or the PLL clock is selected as the machine clock. When this bit is 0, it indicates that the PLL clock is selected. When this bit is 1, it indicates that the main clock is selected. If the MCS bit is 0 and the MCM bit is 1, this is an indication of the PLL clock oscillation stabilization wait time. Also, the oscillation stabilization wait time of the PLL clock is fixed at 213 main clock cycles. [Bits 13 and 12] WS1 and WS0 The WS1 and WS0 bits set the oscillation stabilization time for the main clock to be applied after the stop or hardware standby mode is released. These bits are initialized to 11 by a power-on reset but are not initialized by a reset caused by another reset cause. They are read/write bits. Table 5.3-1 Settings of Clock Selection Register (WS1 and WS0 Bits) WS1 WS0 0 0 Oscillation stabilization time (OSC oscillation: 4 MHz) 210/Fch : About 256 μs (210 OSC oscillation cycles) 97 CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT Table 5.3-1 Settings of Clock Selection Register (WS1 and WS0 Bits) WS1 WS0 Oscillation stabilization time (OSC oscillation: 4 MHz) 0 1 About 2.05 ms (213 OSC oscillation cycles) 1 0 About 8.19 ms (215 OSC oscillation cycles) 1 1 About 32.77 ms (217 OSC oscillation cycles)(*1) *1: Approx. 65.54 ms (218counts of source oscillation) at power-on. [Bit 11] SCS Two clocks system The SCS bit indicates whether the main clock or the subclock is used as the machine clock. If this bit is 0, the subclock is selected. If 0 is written when the bit is 1, the mode is switched to the subclock mode by synchronizing with the subclock (about 130 μs). If 1 is written when the bit is 0, the oscillation stabilization wait time of the main clock is generated and the timebase timer is cleared automatically. If SCS and MCS are both 0, SCS has priority and the subclock is selected. One clock system Always write 1. [Bit 10] MCS MCS specifies whether the main or the PLL clock is to be selected as the machine clock. Writing 0 selects the PLL clock. Writing 1 selects the main clock. When this bit is 1, writing 0 automatically clears the time-based timer to generate the oscillation stabilization time for the PLL clock. The TBOF bit in the time-based timer control register is also cleared. The oscillation stabilization time for the PLL clock is fixed to 213 main clock cycles. (When the OSC oscillation frequency is 4 MHz, the oscillation stabilization time is about 2 ms.) The clock obtained by dividing the main clock by 2 is used as the operating clock when the main clock is selected. (When the OSC oscillation frequency is 4 MHz, the operating clock frequency is 2 MHz.) Note: The oscillation stabilization wait time of the subclock (about 2 s) is generated when the power is turned on or the stop mode is canceled. Thus, if the mode is switched from the main clock mode to the subclock mode during this period, an oscillation stabilization wait time is generated. Before writing 0 in the MCS bit when it is 1, set the TBIE bit or CPU ILM bit so that the timebased timer interrupt is masked. For eight machine cycles after 1 is written in the MCS bit, 0 may not be able to be written in this bit. Write 0 after eight machine cycles. [Bits 9 and 8] CS1 and CS0 CS1 and CS0 select a multiplication factor for the PLL clock. They are not initialized when a reset caused by an external pin, the RST bit, or watchdog occurs or if the hardware standby mode is released but are initialized to 00 by a power-on reset. When the MCS bit is 0, write operation is suppressed. Set the MCS bit to 1 (main clock mode), then write the CS bits. These bits are read/write bits. 98 5.3 Clock Selection Register (CKSCR) Table 5.3-2 Settings of Clock Selection Register (CS1 and CS0 Bits) Internal operating clock (obtained by multiplying OSC oscillation by the multiplication factor) CS1 CS0 Multiplication factor 0 0 0 When the OSC oscillation frequency is 4 MHz When the OSC oscillation frequency is 8 MHz When the OSC oscillation frequency is 16 MHz 1 Setting prohibited 8 MHz 16 MHz 1 2 8 MHz 16 MHz Setting prohibited 1 0 3 12 MHz Setting prohibited Setting prohibited 1 1 4 16 MHz Setting prohibited Setting prohibited Note: When the operating voltage is 5 V, the OSC oscillation frequency range is from 3 to 16 MHz, but the maximum operating frequency of the CPU and peripheral circuits is 16 MHz. If the frequency generated by the specified multiplication factor exceeds the maximum operating frequency, the CPU and peripheral circuits do not operate normally. For example, the OSC oscillation frequency is 16 MHz, only 1 can be specified as the multiplication factor. The minimum operating frequency of VCO oscillation is 4 MHz. Any frequency less than this frequency cannot be specified. Figure 5.3-2 Relationships between the OSC Oscillation Frequency and Internal Operating Clock Frequency Internal operating clock frequency [MHz] Multiplication Multiplication Multiplication Multiplication factor of 4 factor of 3 factor of 1 factor of 2 No multiplication factor 16 12 8 4 3 4 8 16 24 32 OSC oscillation frequency [MHz] 99 CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT 5.4 Operation of the Low-power Consumption Control Circuit Table 5.4-1 "Operating States in the Low-power Consumption Mode" lists the operating states in the low-power consumption mode. ■ Operation of the Low-power Consumption Control Circuit Table 5.4-1 Operating States in the Low-power Consumption Mode (Two clock system) Transition condition Subclock oscillation Main clock oscillation Machine clock CPU Peripherals Pins Released by Subclock mode*1 SCS=0 MCS=x Operating Stopped Operating Operating Operating Operating Reset interrupt Subclock sleep mode*1 SCS=0 MCS=x SLP=1 Operating Stopped Operating Stopped Operating Operating Reset interrupt Main clock sleep mode SCS=1 MCS=1 SLP=1 Operating Operating Operating Stopped Operating Operating Reset interrupt PLL clock sleep mode SCS=1 MCS=0 SLP=1 Operating Operating Operating Stopped Operating Operating Reset interrupt Pseudo watch mode (SPL=0) SCS=1 MCS=0 SLP=1 Operating Operating Stopped Stopped Stopped Retained Reset interrupt*2 Stop mode (SPL=1) SCS=1 MCS=0 STP=1 Operating Operating Stopped Stopped Stopped Hi-z Reset interrupt*2 Watch mode (SPL=0) SCS=x MCS=x TMD=0 Operating Stopped Stopped Stopped Stopped Retained Reset interrupt*3 Watch mode (SPL=1) SCS=x MCS=x TMD=0 Operating Stopped Stopped Stopped Stopped Hi-z Reset interrupt*3 Stop mode (SPL=0) MCS=1 or SCS=0 STP=1 Stopped Stopped Stopped Stopped Stopped Retained Reset interrupt*4 Stop mode (SPL=1) MCS=1 or SCS=0 STP=1 Stopped Stopped Stopped Stopped Stopped Hi-z Reset interrupt*4 Hardware standby mode HST=L Stopped Stopped Stopped Stopped Stopped Hi-z HST=H *1: *2: *3: *4: 100 Do not set this for the one clock system. Watch prescaler, time-base timer, and external interrupt Watch prescaler and external interrupt External interrupt 5.4 Operation of the Low-power Consumption Control Circuit Table 5.4-2 Low Power Consumption Mode Operating Status (one clock system) Transition condition Subclock oscillation Main clock oscillation Machine clock CPU Peripherals Pins Released by Main sleep SCS=1 MCS=1 SLP=1 - Operating Operating Stopped Operating Operating External reset interrupt POLL sleep SCS=1 MCS=0 SLP=1 - Operating Operating Stopped Operating Operating External reset interrupt Pseudo watch (SPL=0) SCS=1 MCS=0 STP=1 - Operating Stopped Stopped Stopped Retained External reset interrupt*5 Pseudo watch (SPL=1) SCS=1 MCS=0 STP=1 - Operating Stopped Stopped Stopped Hi-z External reset interrupt*5 Stop (SPL=0) SCS=1 MCS=1 STP=1 - Stopped Stopped Stopped Stopped Retained External reset interrupt*6 Stop (SPL=1) SCS=1 MCS=1 STP=1 - Stopped Stopped Stopped Stopped Hi-z External reset interrupt*6 - Stopped Stopped Stopped Stopped Hi-z HST=H Hardware standby HST=L *5: Time-base timer and external interrupt *6: External interrupt 101 CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT 5.4.1 Sleep Mode In the sleep mode, only the clock supplied to the CPU is stopped. The CPU stops, but the peripheral circuits continue operation. ■ Transition to the Sleep Mode Writing 1 in the SLP and TMD bits of the low power-consumption mode control register and 0 in the STP bit of the same register causes the standby control circuit to enter the sleep mode. If an interrupt request occurs when 1 is written in the SLP bit, the standby control circuit does not enter the sleep mode. If the CPU is in the interrupt disabled state, it executes the next instruction; if the CPU is in the interrupt enabled state, it immediately branches to the interrupt processing routine. In the sleep mode, the dedicated registers, e.g., accumulator, and the internal RAM retain their contents. Even in the sleep mode, the external bus hold function operates and enters the hold state when a hold request is received. ■ Releasing the Sleep Mode The low-power consumption control circuit cancels the sleep mode by resetting or generating an interrupt request. ❍ Return by resetting The circuit is initialized to the main clock mode by inputting a reset ❍ Return by an interrupt If a peripheral circuit or another device generates an interrupt request at an interrupt level higher than 7 in sleep mode, the low-power consumption control circuit cancels sleep mode. After sleep mode is cancelled, the interrupt is processed in the same way as are ordinary interrupts. If an interrupt is accepted by the settings of I flag of the condition code register (CCR), interrupt level mask register (ILM), and interrupt control register (ICR), the CPU executes interrupt processing. If an interrupt is not accepted, the CPU continues processing starting with the instruction following the one specifying sleep mode. 102 5.4 Operation of the Low-power Consumption Control Circuit 5.4.2 Pseudo Watch Mode In the pseudo watch mode, all clock operations other than source clock oscillation (of the main clock and subclock), watch timer, and time base timer is stopped. Also, most chip functions stop. Whether retaining the status of each I/O pin set immediately before the transition to the pseudo watch mode or setting each I/O pin to high impedance can be specified. Use the SLP bit of the low power-consumption mode control register (LPMCR) for this specification. ■ Transition to the Pseudo Watch Mode Writing 1 in the SCS bit of the clock selection register (CKSCR), 0 in the MCS bit of the same register, 1 in the TMD bit of the low power-consumption mode control register, and 1 in the STP bit of the same register causes the standby control circuit to enter the pseudo watch mode. If an interrupt request occurs when 1 is written in the STP bit, the standby control circuit does not enter the pseudo watch mode. In the pseudo watch mode, the internal RAM and dedicated registers, e.g., accumulator, retain their contents. ■ Releasing the Pseudo Watch Mode The standby control circuit releases the pseudo watch mode when a reset signal is input or an interrupt occurs. ❍ Return by external reset The circuit is initialized to main clock mode by an external reset. ❍ Return by an interrupt If a watch prescaler, time-base timer, or external interrupt generates an interrupt request at an interrupt level higher than 7 in pseudo watch mode, the low-power consumption control circuit cancels pseudo watch mode. After the pseudo watch mode is released, the interrupt is processed in a normal way. If an interrupt is accepted by the settings of I flag of the condition code register (CCR), interrupt level mask register (ILM), and interrupt control register (ICR), the CPU executes interrupt processing. If an interrupt is not accepted, the CPU continues processing starting with the next instruction before the system entered pseudo watch mode. 103 CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT 5.4.3 Watch Mode In the watch mode, all clock operations other than subclock oscillation and the watch timer is stopped. Most chip functions stop. Whether to retain the status of each I/O pin set immediately before the transition to the watch mode or to set each I/O pin to high impedance can be specified. Use the SPL bit of the low power-consumption mode control register (LPMCR) for this specification. However, the watch mode cannot be used in the one clock system. ■ Transition to the Watch Mode Writing 0 in the TMD bit of the low power-consumption mode control register causes the standby control circuit to enter the watch mode. If an interrupt request occurs when 1 is written in the TMD bit, the standby control circuit does not enter the watch mode. In the watch mode, dedicated registers, e.g., accumulator, and the internal RAM retain their contents. In the watch mode, the external bus hold function stops. If a hold request is input, it is not accepted. If a hold request is input during a transition to the watch mode, the HAK signal may not become low with the bus set to high impedance. ■ Releasing the Watch Mode The standby control circuit releases the watch mode when a reset signal is input or an interrupt occurs. ❍ Return by resetting If watch mode is cancelled by a reset factor, the low-power consumption control circuit first cancels watch mode, then enters the oscillation stabilization wait reset state. The reset sequence is executed after expiration of the oscillation stabilization wait time. ❍ Return by an interrupt If a watch prescaler or external interrupt generates an interrupt request at an interrupt level higher than 7 in watch mode, the low-power consumption control circuit cancels watch mode and enters the subclock mode immediately. After the low-power consumption control circuit enters subclock mode, the interrupt is processed in the same way as are ordinary interrupts. If an interrupt is accepted by the settings of I flag of the condition code register (CCR), interrupt level mask register (ILM), and interrupt control register (ICR), the CPU executes interrupt processing. If an interrupt is not accepted, the CPU continues processing starting with the next instruction before the system entered watch mode. Note: Normally, an interrupt is executed after execution of the instruction following the one specifying watch mode. If the transition to watch mode and the acceptance of the external bus hold request occur simultaneously, however, transition to interrupt processing might occur before the next instruction is executed. 104 5.4 Operation of the Low-power Consumption Control Circuit 5.4.4 Stop Mode In the stop mode, all clock oscillation (subclock and main clock) is stopped and all chip functions stop. Therefore, data can be retained with the lowest power consumption. Whether to retain the status of each I/O pin set immediately before the transition to the stop mode or to set each I/O pin to high impedance can be specified. Use the SPL bit of the low power-consumption mode control register (LPMCR) for this specification. ■ Transition to the Stop Mode Writing 0 in the SCS bit of the clock selection register (CKSCR), 1 in the MCS bit of the same register, and 1 in the STP bit of the low power-consumption mode control register (LPMCR) causes the standby control circuit to enter the stop mode. If an interrupt request may occur when 1 is written in the STP bit, the standby control circuit does not enter the stop mode. In the stop mode, dedicated registers, e.g., accumulator, and the internal RAM retain their contents. ■ Releasing the Stop Mode The standby control circuit releases the stop mode when a reset signal is input or an interrupt occurs. When returning from the stop mode, the oscillation of the operating clock has stopped, so the low-power consumption control circuit first enters the oscillation stabilization wait time, then cancels the stop mode. ❍ Cancel by resetting If stop mode is cancelled by a reset factor, the low-power consumption control circuit first cancels stop mode, then enters the oscillation stabilization wait reset state. The reset sequence is executed after expiration of the oscillation stabilization wait time. ❍ Cancel by an interrupt If an external interrupt generates an interrupt request at an interrupt level higher than 7 in stop mode, the low-power consumption control circuit cancels stop mode. After stop mode is cancelled, the interrupt is processed in the same way as are ordinary interrupts after the expiration of the oscillation stabilization wait time of the main clock. This time is specified by the oscillation stabilization wait time selection bits (WS1, WS0) of the clock selection register (CKSCR). If an interrupt is accepted by the settings of I flag of the condition code register (CCR), interrupt level mask register (ILM), and interrupt control register (ICR), the CPU executes interrupt processing. If an interrupt is not accepted, the CPU continues processing starting with the next instruction before the system entered stop mode. Note: Normally, an interrupt is executed after execution of the instruction following the one specifying stop mode. If the transition to stop mode and the acceptance of the external bus hold request occur simultaneously, however, transition to interrupt processing might occur before the next instruction is executed. 105 CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT 5.4.5 Hardware Standby Mode In the hardware standby mode, when the HST pin is low, oscillation is stopped and all I/O pins are set to high impedance regardless of other statuses including resets. ■ Transition to the Hardware Standby Mode In any state, driving the HST pin low can set the standby control circuit to the hardware standby mode. In the hardware standby mode, the contents of internal RAM are retained, but the dedicated registers such as the accumulator are initialized. ■ Releasing the Hardware Standby Mode The hardware standby mode can be released only using the HST pin. When the HST pin is driven high, the standby control circuit releases the hardware standby mode, enables the internal reset signal, then enters the oscillation stabilization wait state. When the oscillation stabilization time has elapsed, the standby control circuit releases the internal reset. The CPU then starts execution from the reset sequence. 106 5.5 Intermittent CPU Operation Function 5.5 Intermittent CPU Operation Function The intermittent CPU operation function stops the clock supplied to the CPU for the specified time and delays the start of the internal bus cycle in the following case: • When registers, internal memory (ROM, RAM, I/O, and resources), and the external bus are accessed ■ Intermittent CPU Operation Function The intermittent CPU operation function can be used to perform processing with low-power consumption because the CPU execution speed is lowered by supplying the internal resources with a high-speed clock. Use the CG1 and CG0 bits to select the temporary stop cycle count for the clock supplied to the CPU. The external bus operation itself is performed using the same clock as the resources. The execution time required when the intermittent CPU operation function is used can be obtained as follows: • Add to the normal execution time the compensation value obtained by multiplying the number of accesses to registers, internal memory, internal resources, and the external bus by the temporary stop cycle count. Figure 5.5-1 Intermittent CPU Operation Resources clock CPU clock Temporary stop cycles during intermittent operation Internal bus start cycle 107 CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT 5.6 Setting the Oscillation Stabilization Time for the Main Clock Use the WS1 and WS0 bits in the CKSCR register to select the oscillation stabilization time required when the stop or hardware standby mode is released. Select the oscillation stabilization time according to the types and characteristics of the oscillator and the oscillation element connected to the X0 and X1 pins. ■ Setting the Oscillation Stabilization Time for the Main Clock Resets other than a power-on reset do not initialize these bits. These bits are initialized to 11B when a power-on reset occurs. For this reason, the oscillation stabilization time at power-on is about 218 OSC oscillation cycles. 108 5.7 Switching the Machine Clock 5.7 Switching the Machine Clock This section explains how to switch and initialize the machine clock. However, subclocks cannot be used with the one clock system. ■ Switching between the Main and PLL Clocks Writing to the MCS bit of the CKSCR register switches the machine clock between the main and the PLL clocks. Rewriting the MCS bit from 1 to 0 switches the machine clock from the main clock to the PLL clock after the PLL clock oscillation stabilization time (213 machine clock cycles) passes. Rewriting the MCS bit from 0 to 1 switches the machine clock from the PLL clock to the main clock when a PLL clock edge coincides with a main clock edge (1 to 8 PLL clock cycles after). The machine clock is not switched immediately after rewriting the MCS bit. Therefore, reference the MCM bit and check that the machine bit has been switched when operating each peripheral depending on the machine clock. ■ Switching between the Main Clock and Subclock Writing to the SCS bit of the CKSCR register switches the machine clock between the main clock and the subclock. Rewriting the SCS bit from 1 to 0 switches the machine clock from the main clock to the subclock by synchronizing with subclock (about 130μs). Rewriting the SCS bit from 0 to 1 switches the machine clock from the subclock to the main clock after the main clock oscillation stabilization time passes. The machine clock is not switched immediately after rewriting the SCS bit. Therefore, reference the SCM bit and check that the machine bit has been switched when operating each peripheral depending on the machine clock. Note: When the clock mode is switched, do not switch to low power consumption mode and other clock mode before this switching is completed. Confirm the completion of clock mode switching by referring to the MCM and SCM bits of the clock selection register (CKSCR). If the mode is switched to another clock mode or low power consumption mode before completion of switching, the mode may not be switched. ■ Initializing the Machine Clock The MCS and SCS bits cannot be initialized by a reset that uses the RST external reset pin or the RST bit. The MCS and SCS bits are initialized to "1" by any other reset. 109 CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT ■ Initializing the Machine Clock The MCS and SCS bits are not initialized by any reset cause from an external pin or by the RST bit. These bits are initialized to 1 by other reset causes. Figure 5.7-1 "Transition of Clock Selection Status (1) (Two clocks system No.1)" to Figure 5.7-3 "Transition of Clock Selection Status (3) (One Clock System)" show the transition of clock selection status. Figure 5.7-1 Transition of Clock Selection Status (1) (Two clocks system No.1) Power-on Main clock Main clock MCS MCS B B Main clock MCS B SUBclock Main clock MCS MCS B B Main clock MCS B Main clock Subclock 0 MCS Main clock MCS B (1) (2) (3) (4) (5) (6) (7) (8) (9) 110 PLL multiplication factor: 1 MCS B PLL multiplication factor: 2 MCS B PLL multiplication factor: 3 MCS B PLL multiplication factor: 4 MCS B The MCS bit is cleared and the SCS bit is set. The PLL clock oscillation stabilization time has passed and CS1 and CS0 are 00B. The PLL clock oscillation stabilization time has passed and CS1 and CS0 are 01B. The PLL clock oscillation stabilization time has passed and CS1 and CS0 are 10B. The PLL clock oscillation stabilization time has passed and CS1 and CS0 are 11B. The MCS bit is set and the SCS bit is cleared. The PLL clock is synchronized with the main clock and the SCS bit is 1. The PLL clock is synchronized with the main clock and the SCS bit is 0. The main clock oscillation stabilization time has passed and the MCS bit is 0. 5.7 Switching the Machine Clock Figure 5.7-2 Transition of Clock Selection Status (2) (Two clocks system No.2) Power-on Main clock Main clock MCS Subclock MCS Subclock MCS=X Subclock Main clock MCS=X Subclock MCS=X B Main clock MCS B (1) (2) (3) (4) (5) (6) The SCS bit is cleared. A subclock edge is detected. The SCS bit is set. The main clock oscillation stabilization time has passed and the MCS bit is 1. The PLL clock is synchronized with the main clock and the SCS bit is 0. The main clock oscillation stabilization time has passed and the MCS bit is 0. 111 CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT Figure 5.7-3 Transition of Clock Selection Status (3) (One Clock System) Power-on Main clock SCS = 1, MCS = 1 SCM = 1, MCM = 1 CS1/0 = xxB (1) (6) Main clock PLLx SCS = 1, MCS = 0 SCM = 1, MCM = 1 CS1/0 = xxB (7) (7) (7) (2) (3) PLL multiplication Main clock factor: 1 SCS = 1, MCS = 1 SCM = 1, MCM = 0 CS1/0 = 00'B PLL multiplication Main clock factor: 2 SCS = 1, MCS = 1 SCM = 1, MCM = 0 CS1/0 = 01'B (6) (4) (6) PLL multiplication factor: 1 SCS = 1, MCS = 0 SCM = 1, MCM = 0 CS1/0 = 00'B PLL multiplication factor: 2 SCS = 1, MCS = 0 SCM = 1, MCM = 0 CS1/0 = 01'B (7) PLL multiplication Main clock factor: 3 SCS = 1, MCS = 1 SCM = 1, MCM = 0 CS1/0 = 10'B PLL multiplication Main clock factor: 4 SCS = 1, MCS = 1 SCM = 1, MCM = 0 CS1/0 = 11'B (1) (2) (3) (4) (5) (6) (7) 112 The The The The The The The (5) (6) (6) PLL multiplication factor: 3 SCS = 1, MCS = 0 SCM = 1, MCM = 0 CS1/0 = 10'B PLL multiplication factor: 4 SCS = 1, MCS = 0 SCM = 1, MCM = 0 CS1/0 = 11'B MCS bit is cleared and the SCS bit is set. PLL clock oscillation stabilization time has passed and CS1 and CS0 PLL clock oscillation stabilization time has passed and CS1 and CS0 PLL clock oscillation stabilization time has passed and CS1 and CS0 PLL clock oscillation stabilization time has passed and CS1 and CS0 MCS bit is set. PLL clock is synchronized with the main clock and the SCS bit is 1. are are are are 00B. 01B. 10B. 10B. 5.8 Status Transition 5.8 Status Transition Lists the conditions for status transition. ■ Status Transition Table 5.8-1 Conditions for Status Transition (Two Clocks System) Status before transition Power-on Main clock oscillation stabilization Transition condition Status after transition 01 Main clock oscillation stabilization time has passed. Main clock mode 05 Main clock oscillation stabilization time has passed. Main clock mode 06 0 is written in SCS. MS transition mode 07 1 is written in SCS and 0 is written in MCS. MP transition mode 31 1 is written in TMD, 0 is written in STP, and 1 is written in SLP. Main clock sleep mode 32 0 is written in TMD. Transition to watch mode with main clock 33 1 is written in TMD and STP. Main clock stop mode 21 0 is written in SCS. PS transition mode 20 1 is written in SCS and MCS. PM transition mode 59 1 is written in TMD, 0 is written in STP, and 1 is written in SLP. PLL clock sleep mode 58 0 is written in TMD. Transition to watch mode with PLL clock (P) 57 1 is written in TMD and STP. Transition to pseudo watch mode 10 1 is written in SCS and MCS. SM transition mode 12 1 is written in SCS and MCS. SP transition mode 11 Reset is activated. Main clock oscillation stabilization 42 1 is written in TMD, 0 is written in STP, and 1 is written in SLP. Subclock sleep mode 43 0 is written in TMD. Subclock mode 44 1 is written in TMD and STP. Subclock stop mode Main clock mode PLL clock mode Subclock mode 113 CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT Table 5.8-1 Conditions for Status Transition (Two Clocks System) (Continued) Status before transition Transition condition Status after transition 13 Timing to switch from PLL clock to main clock is reached. Main clock mode 38 1 is written in TMD, 0 is written in STP, and 1 is written in SLP. Sleep mode for PM transition 39 0 is written in TMD and timing to switch from PLL clock to main clock is reached. Transition to watch mode with main clock 40 1 is written in TMD and STP and timing to switch from PLL clock to main clock is reached. Main clock stop mode 02 Main clock oscillation stabilization time has passed. Main clock mode 03 Reset is activated or interrupt is generated. Main clock oscillation stabilization 04 0 is written in SCS. Subclock mode 27 1 is written in TMD, 0 is written in STP, and 1 is written in SLP. Sleep mode for SM transition 28 0 is written in TMD and main clock oscillation stabilization time has passed. Watch mode with main clock 29 1 is written in TMD and STP and main clock oscillation stabilization time has passed. Main clock stop mode 16 PLL clock oscillation stabilization time has passed. PLL clock mode 14 1 is written in SCS and MCS. Main clock mode 15 0 is written in SCS. MS transition mode 68 1 is written in TMD, 0 is written in STP, and 1 is written in SLP. Sleep mode for MP transition 70 0 is written in TMD. Transition to watch mode with PLL clock (M) 69 1 is written in TMD and STP. Pseudo watch mode PM transition mode SM transition mode MP transition mode 114 5.8 Status Transition Table 5.8-1 Conditions for Status Transition (Two Clocks System) (Continued) Status before transition SP transition mode Transition condition 17 Main clock oscillation stabilization time has passed. MP transition mode 18 1 is written in MCS. SM transition mode 19 Reset is activated. Main clock oscillation stabilization 75 1 is written in TMD, 0 is written in STP, and 1 is written in SLP. Sleep mode for SP transition 76 0 is written in TMD. Watch mode with PLL clock 78 1 is written in TMD and STP and main clock oscillation stabilization time has passed. Pseudo watch mode 09 Timing to switch from main clock to subclock is reached. Subclock mode 08 Reset is activated. Main clock mode 51 1 is written in TMD, 0 is written in STP, and 1 is written in SLP. Sleep mode for MS transition 52 0 is written in TMD and timing to switch from main clock to subclock is reached. Watch mode with subclock 53 1 is written in TMD and STP and timing to switch from main clock to subclock is reached. Subclock mode 23 Timing to switch from PLL clock to main clock is reached. MS transition mode 22 1 is written in SCS. PM transition mode 56 1 is written in TMD, 0 is written in STP, and 1 is written in SLP. Sleep mode for PS transition 26 Interrupt is generated or reset is activated. Main clock mode 24 Main clock oscillation stabilization time has passed. Sleep mode with main clock 25 Interrupt is generated or reset is activated. SM transition mode 34 PLL clock oscillation stabilization time has passed. Main clock sleep mode 35 Interrupt is generated or reset is activated. PM transition mode 63 Interrupt is generated or reset is activated. PLL clock mode 66 PLL clock oscillation stabilization time has passed. PLL clock sleep mode 67 Interrupt is generated or reset is activated. MP transition mode MS transition mode PS transition mode Main clock sleep mode Sleep mode for SM transition Sleep mode for PM transition PLL clock sleep mode Status after transition Sleep mode for MP transition 115 CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT Table 5.8-1 Conditions for Status Transition (Two Clocks System) (Continued) Status before transition Transition condition Status after transition 73 Main clock oscillation stabilization time has passed. Sleep mode for MP transition 74 Interrupt is generated or reset is activated. SP transition mode 46 Interrupt is generated or reset is activated. Subclock mode 49 Timing to switch from main clock to subclock is reached. Subclock sleep mode 50 Interrupt is generated or reset is activated. MS transition mode 54 Timing to switch from PLL clock to main clock is reached. Sleep mode for MS transition 55 Interrupt is generated or reset is activated. PS transition mode 30 Interrupt is generated or reset is activated. SM transition mode 36 Timing to switch from main clock to subclock is reached. Watch mode with main clock 37 Interrupt is generated or reset is activated. Main clock mode Watch mode with PLL clock 77 Interrupt is generated or reset is activated. SP transition mode Transition to watch mode with PLL clock (M) 72 Timing to switch from main clock to subclock is reached. Watch mode with PLL clock 71 Interrupt is generated or reset is activated. MP transition mode 65 Timing to switch from PLL clock to main clock is reached. Transition to watch mode with PLL clock (M) 64 Interrupt is generated or reset is activated. PLL clock mode 47 Interrupt is generated or reset is activated. Subclock mode 41 Interrupt is generated or reset is activated. Main clock oscillation stabilization 62 Interrupt is generated or reset is activated. MP transition mode 61 Timing to switch from PLL clock to main clock is reached. Pseudo watch mode 60 Interrupt is generated or reset is activated. PLL clock mode 48 Interrupt is generated. Subclock mode 79 Reset is activated. Main clock oscillation stabilization Sleep mode for SP transition Subclock sleep mode Sleep mode for MS transition Sleep mode for PS transition Watch mode with main clock Transition to watch mode with main clock Transition to watch mode with PLL clock (P) Watch mode with subclock Main clock stop mode Pseudo watch mode Transition to watch Pseudo with main clock Subclock stop mode 116 5.8 Status Transition Table 5.8-1 Conditions for Status Transition (Two Clocks System) (Continued) Status before transition Subclock oscillation stabilization Transition condition Status after transition 45 Subclock oscillation stabilization time has passed. Subclock mode 80 Reset is activated. Main clock oscillation stabilization MCS: MCS bit (clock selection register) (When MCS is 0, the clock mode is selected.) SCS: SCS bit (clock selection register) (When SCS is 0, the subclock mode is selected.) STP: STP bit (low power-consumption mode register) (When STP is 0, the stop is selected.) SLP: SLP bit (low power-consumption mode register) (When SLP is 0, the sleep mode is selected.) TMD: TMD bit (low power-consumption mode register) (When TMD is 0, the watch mode is selected.) MCM: MCM bit (clock selection register) (When MCM is 0, the PLL clock is used.) SCM: SCM bit (clock selection register) (When SCM is 0, the subclock is used.) SCD: Bit to stop subclock (When SCD is 1, subclock oscillation is stopped.) MCD: Bit to stop main clock (When MCD is 1, main clock oscillation is stopped.) PCD: Bit to stop PLL clock (When PCD is 1, PLL clock oscillation is stopped.) Table 5.8-2 Conditions for Status Transition (One Clock System) Status before transition Transition condition Status after transition Power-on 01 Main oscillation stabilization time end Main mode Main oscillation stabilization 05 Main oscillation stabilization time end Main mode 07 SCS=1, MCS=0 write MP transition mode 31 TMD=1, STP=0, SLP=1 write Main sleep 33 TMD=1, STP=1 write Main stop 20 SCS=1, MCS=1 write PM transition mode 59 TMD=1, STP=0, SLP=1 write PLL sleep 57 TMD=1, STP=1 write Pseudo watch transition 13 PLL/main switching timing wait end Main mode 38 TMD=1, STP=0, SLP=1 write PM transition sleep 40 TMD=1, STP=1 write & PLL to main switching timing wait end Main stop 16 PLL oscillation stabilization wait time end PLL mode 14 SCS=1, MCS=1 write Main mode 68 TMD=1, STP=0, SLP=1 write MP transition sleep 69 TMD=1, STP=1 write Pseudo watch mode 26 Interrupt or reset activation Main mode Main mode PLL mode PM transition mode MP transition mode Main sleep 117 CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT Table 5.8-2 Conditions for Status Transition (One Clock System) (Continued) Status before transition PM transition sleep Transition condition Status after transition 34 PLL/main switching timing wait end Main sleep 35 Interrupt or reset activation PM transition mode PLL sleep 63 Interrupt or reset activation PLL mode MP transition sleep 66 PLL oscillation stabilization wait time end PLL sleep 67 Interrupt or reset activation MP transition mode Main stop 41 Interrupt or reset activation Main oscillation stabilization Pseudo watch 62 Interrupt or reset activation MP transition mode Pseudo watch transition 61 PLL/main switching timing wait end Pseudo watch mode 60 Interrupt or reset activation PLL mode MCS: MCS bit (clock selection register) (If MCS is 0, the clock mode is selected.) STP: STP bit (low-power consumption mode register) (If STP is 0, the stop mode is selected.) SLP: SLP bit (low-power consumption mode register) (If SLP is 0, the sleep mode is selected.) MCM: MCM bit (clock selection register) (If MCM is 0, the PLL clock is operating.) MCD: Bit to stop main clock (If MCD is 1, main clock oscillation is stopped.) PCD: Bit to stop PLL clock (If PCD is 1, PLL clock oscillation is stopped.) 118 5.9 Status Transition Diagrams for Low Power-Consumption Modes 5.9 Status Transition Diagrams for Low Power-Consumption Modes Figure 5.9-1 "Status Transition in the Low Power-Consumption Mode (Two clocks system) (1)" to Figure 5.9-7 "Status Transition in the Low Power-Consumption Mode (One Clock System) (3)" show the status transition in the low power-consumption mode. ■ Status Transition in the Low Power-Consumption Mode (Two Clocks System) In Figure 5.9-1 "Status Transition in the Low Power-Consumption Mode (1)" to Figure 5.9-4 "Status Transition in the Low Power-Consumption Mode (4)" the events that occur at the same time are shown as if occurring in steps for easy understanding. In actual operation, each transition of status is performed momentarily. For example, if MCS is set to 1 and SLP is set to 1 simultaneously in PLL clock mode, the status transition diagram indicates the transition in which PLL clock mode first changes to PM transition mode, then changes to PM transition sleep. In actual operation, however, PLL clock mode changes to PM transition sleep immediately. Another example is the transition from the subclock sleep mode to main clock oscillation stabilization. The figures show that the subclock sleep mode changes to the subclock mode once, then changes to main clock oscillation stabilization. In actual operation, the subclock sleep mode changes to main clock oscillation stabilization momentarily. Note: When the clock mode is switched, do not switch to low power consumption mode and other clock mode before this switching is completed. Confirm the completion of clock mode switching by referring to the MCM and SCM bits of the clock selection register (CKSCR). If the mode is switched to another clock mode or low power consumption mode before completion of switching, the mode may not be switched. 119 CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT Figure 5.9-1 Status Transition in the Low Power-Consumption Mode (Two clocks system) (1) Power-on reset SM transition mode Main clock mode MS transition mode PM transition mode MP transition mode PLL mode 120 Main clock oscillation stabilization Subclock mode SP transition mode PS transition mode 5.9 Status Transition Diagrams for Low Power-Consumption Modes Figure 5.9-2 Status Transition in the Low Power-Consumption Mode (Two clocks system) (2) Sleep mode for SM transition Main clock sleep mode SM transition mode Watch mode with main clock Sleep mode for PM transition Transition to watch mode with main clock PM transition mode Main clock stop mode Main clock mode Main clock oscillation stabilization 121 CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT Figure 5.9-3 Status Transition in the Low Power-Consumption Mode (Two clocks system) (3) Subclock mode Subclock oscillation stabilization Main clock oscillation stabilization Subclock sleep mode Watch mode with subclock Subclock stop mode Sleep mode for MS transition MS transition mode Sleep mode for PM transition 122 PM transition mode 5.9 Status Transition Diagrams for Low Power-Consumption Modes Figure 5.9-4 Status Transition in the Low Power-Consumption Mode (Two clocks system) (4) PLL clock mode Transition to pseudo watch mode Pseudo watch mode Transition to watch mode with PLL clock (P) PLL clock sleep mode Sleep mode for MS transition MP transition mode Transition to watch mode with PLL clock (M) Sleep mode for SP transition SP transition mode Watch mode with PLL clock 123 CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT ■ Status Transition in the Low-Power Consumption Mode (One Clock System) Figure 5.9-5 Status Transition in the Low-Power Consumption Mode (One Clock System) (1) Power-on reset SCS=1,MCS=1 STP=0,SLP=0 TMD=1 SCM=1,MCM=1 SCD=0,MCD=0 PCD=1 Main oscillation stabilization time SCS=1,MCS=1 STP=0,SLP=0 TMD=1 SCM=1,MCM=1 SCD=0,MCD=0 PCD=1 05 01 Main mode SCS=1,MCS=1 STP=0,SLP=0 TMD=1 SCM=1,MCM=1 SCD=0,MCD=0 PCD=1 07 13 PM transition mode SCS=1,MCS=1 STP=0,SLP=0 TMD=1 SCM=1,MCM=0 SCD=0,MCD=0 PCD=0 14 MP transition mode SCS=1,MCS=0 STP=0,SLP=0 TMD=1 SCM=1,MCM=1 SCD=0,MCD=0 PCD=0 16 20 PLL mode SCS=1,MCS=0 STP=0,SLP=0 TMD=1 SCM=1,MCM=0 SCD=0,MCD=0 PCD=0 124 5.9 Status Transition Diagrams for Low Power-Consumption Modes Figure 5.9-6 Status Transition in the Low-Power Consumption Mode (One Clock System) (2) Main sleep SCS=1,MCS=1 STP=0,SLP=1 TMD=1 SCM=1,MCM=1 SCD=0,MCD=0 PCD=1 26 31 Main mode SCS=1,MCS=1 STP=0,SLP=0 TMD=1 SCM=1,MCM=1 SCD=0,MCD=0 PCD=1 33 34 05 PM transition sleep SCS=1,MCS=1 STP=0,SLP=1 TMD=1 SCM=1,MCM=0 SCD=0,MCD=0 PCD=0 Main oscillation stabilization time SCS=1,MCS=1 STP=0,SLP=0 TMD=1 SCM=1,MCM=1 SCD=0,MCD=0 PCD=1 35 38 PM transition mode SCS=1,MCS=1 STP=0,SLP=0 TMD=1 SCM=1,MCM=0 SCD=0,MCD=0 PCD=0 40 Main stop SCS=1,MCS=1 STP=1,SLP=0 TMD=1 SCM=1,MCM=1 SCD=1,MCD=1 PCD=1 41 125 CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT Figure 5.9-7 Status Transition in the Low-Power Consumption Mode (One Clock System) (3) PLL mode SCS=1,MCS=0 STP=0,SLP=0 TMD=1 SCM=1,MCM=0 SCD=0,MCD=0 PCD=0 57 60 Pseudo watch transition SCS=1,MCS=0 STP=1,SLP=0 TMD=1 SCM=1,MCM=1 SCD=0,MCD=0 PCD=1 61 62 Pseudo watch mode SCS=1,MCS=0 STP=1,SLP=0 TMD=1 SCM=1,MCM=1 SCD=0,MCD=0 PCD=1 59 63 PLL sleep SCS=1,MCS=0 STP=0,SLP=1 TMD=1 SCM=1,MCM=0 SCD=0,MCD=0 PCD=0 16 69 66 MS transition sleep SCS=1,MCS=0 STP=0,SLP=1 TMD=1 SCM=1,MCM=1 SCD=0,MCD=0 67 PCD=0 68 MP transition mode SCS=1,MCS=0 STP=0,SLP=0 TMD=1 SCM=1,MCM=1 SCD=0,MCD=0 PCD=0 Note: In attempting to switch the clock mode, do not attempt to switch to another clock mode or low-power consumption mode until the first switching is completed. The MCM bit of the clock selection register (CKSCR) indicates that switching is completed. If the mode is switched to another clock mode or low-power consumption mode before compietion of switching, the mode may not be swiched. 126 CHAPTER 6 MEMORY ACCESS MODES This chapter describes the functions and operations of memory access modes. 6.1 "Memory Access Mode Overview" 6.2 "External Memory Access (External Bus Pin Control Circuit)" 6.3 "Operation of the External Memory Access Control Signals" 127 CHAPTER 6 MEMORY ACCESS MODES 6.1 Memory Access Mode Overview The F2MC-16LX provides various types of modes for the access system and access area. ■ Memory Access Mode Overview Table 6.1-1 Memory Access Modes Operating mode RUN Flash memory write Bus mode Access mode (external data bus width) Single chip - Internal ROM, external bus 8 bits 16 bits 8 bits External ROM, external bus 16 bits - - ❍ Operating mode In an operating mode, the device operation state is controlled. The operating mode is specified by mode setting pins (MDx) and the M1 and M0 bits of mode data. By selecting an operating mode, ordinary operation can be activated and flash memory can be written. ❍ Bus mode In a bus mode, the operations of the internal ROM and external access function are controlled. A bus mode is specified by mode setting pins (MDx) and an Mx bit in mode data. The mode setting pins (MDx) specify a bus mode for reading reset vector and mode data. An Mx bit in mode data specifies a bus mode for normal operation. ❍ Access mode In an access mode, the external data bus width is controlled. An access mode is specified by mode setting pins (MDx) and the S0 bit in mode data. Selecting an access mode specifies 8 bits or 16 bits as the external data bus width. 128 6.1 Memory Access Mode Overview 6.1.1 Mode Pins Modes can be specified by setting three external pins MD2 to MD0 in combination as shown in Table 6.1-2 "Relationships between Mode Pins and Set Modes". ■ Mode Pin Settings and Corresponding Modes Table 6.1-2 Relationships between Mode Pins and Set Modes Mode pin setting Mode Reset vector access area External data bus width Remark MD2 MD1 MD0 0 0 0 External vector mode 0 External 8 bits - 0 0 1 External vector mode 1 External 16 bits Reset vector access with 16bit bus width 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 Flash memory serial programming - - - 1 1 1 Flash memory mode - - Mode for use of a parallel writer Cannot be specified. Internal vector mode Internal (Mode data) Controlled by mode data after reset sequence Cannot be specified. Note: • Even if external vector mode 0 is selected, the initial values of IOBS and LMBS of the bus control selection register are set to 0. Therefore, a 16-bit width is available in areas 0000C0H to 0000FFH and 002000H to 7FFFFFH. To specify an 8-bit width for the areas, write 1 in IOBS and LMBS of the bus control selection register. In the external vector mode 1, the HMBS bit is set to 0 and access is performed with a 16-bit bus width. • Data cannot be written only by setting the flash memory serial programming mode by mode pins. Other pins must be set. For details, see the example of flash memory serial programming connection. 129 CHAPTER 6 MEMORY ACCESS MODES 6.1.2 Mode Data Mode data is stored in FFFFDFH in main storage to control CPU operation. This data is fetched during execution of a reset sequence and stored in the mode register in the device. Only the reset sequence can change the value of the mode register. The setting of this register is valid after the reset sequence. Set the reserved bits to 0. ■ Mode Data Figure 6.1-1 Mode Data Configuration Mode data Address:FFFFDFH 7 6 M1 M0 5 4 Reserved Reserved 3 2 SO 1 0 Bit No. Reserved Reserved Reserved [Bits 7 and 6] M1 and M0 (bus mode setting bits) The M1 and M0 bits specify an operating mode after termination of the reset sequence. Table 6.1-3 "Function of M1 and M0 (Bus Mode Setting Bits)" shows the relationships between the settings of M1 and M0 bits and functions. Table 6.1-3 Function of M1 and M0 (Bus Mode Setting Bits) M1 M0 Function 0 0 Single-chip mode 0 1 Internal ROM, external bus mode 1 0 External ROM, external bus mode 1 1 Setting is inhibited. [Bit 3] S0 (access mode setting bit) The S0 bit specifies a bus mode and access mode after termination of the reset sequence. Table 6.1-4 "Function of S0 (Access Mode Setting Bit)" shows the relationships between the settings of S0 bit and functions. Table 6.1-4 Function of S0 (Access Mode Setting Bit) S0 130 Function 0 External 8-bit data bus mode 1 External 16-bit data bus mode 6.1 Memory Access Mode Overview 6.1.3 Memory Space for Each Bus Mode Figure 6.1-2 "Relationships between Access Areas and Physical Addresses in Each Bus Modes" shows the correspondence between access areas and physical addresses depending on the bus mode specification. ■ Memory Space for Each Bus Mode As shown in Figure 6.1-2 "Relationships between Access Areas and Physical Addresses in Each Bus Modes" the ROM image of an FF bank can be seen in high-order bits of a 00 bank. This makes the small model of the C compiler effective. Low-order 16 bits are designed to provide the same effect so that tables in the ROM can be referenced without "far" specification in pointer declaration. For example, if 00C000H is accessed, the ROM contents in FFC000H are accessed. Because the ROM area in the FF bank exceeds 48K bytes, the entire image of the FF bank cannot be stored in the 00 bank. Therefore, ROM data in FF4000H to FFFFFFH can be seen in the image in 004000H to 00FFFFH, and so it is recommended that the ROM data table be stored in the area from FF4000H to FFFFFFH. See Chapter 23 "ADDRESS MATCH DETECTION FUNCTION" when ROM without the mirror function is selected. 131 CHAPTER 6 MEMORY ACCESS MODES Figure 6.1-2 Relationships between Access Areas and Physical Addresses in Each Bus Modes FFFFFFH ROM area ROM area ROM area (FF bank image) ROM area (FF bank image) Address #1 FC0000H 010000H Address #2 : Internal 004000H : External 002000H Address #3 RAM 000100H 0000C0H RAM Register Peripheral 000000H RAM Register Peripheral Single-chip with the mirror function : Not accessed Register Peripheral Internal ROM external bus with the mirror function External ROM external bus Part number Address #1 Address #2 Address #3 MB90583C/CA FE00000H 004000H 001900H MB90F583C/CA FE00000H 004000H 001900H MB90587C/CA FF00000H 004000H 001100H MB90V580B (FE00000H) 004000H 001900H ■ Recommended Setting Sample of Memory Space for Each Bus Mode Table 6.1-5 "Example of Recommended Setting of Mode Pins and Mode Data" shows a recommended setting sample of mode pins and mode data. Table 6.1-5 Example of Recommended Setting of Mode Pins and Mode Data Mode setting 132 MD2 MD1 MD0 M1 M0 S0 Single chip 0 1 1 0 0 x Internal ROM, external 16-bit bus 0 1 1 0 1 1 Internal ROM, external 8-bit bus 0 1 1 0 1 0 External ROM, external 16-bit bus, vector 16-bus width 0 0 1 1 0 1 External ROM, external 8-bit bus 0 0 0 1 0 0 6.1 Memory Access Mode Overview The signals input to and output from the external pins related to memory access modes are dependent on the mode. Table 6.1-6 Operation of External Pins Related to Modes Function Pin External bus extension Single chip 8 bits P07 to P00 P17 to P10 Port 16 bits AD07 to 00 A15 to 08 AD15 to 08 P27 to P20 A23 to 16 * P30 ALE P31 RD P32 WR WRL * P33 Port WRH * P34 HRQ * P35 HAK * P36 RDY * P37 CLK * *: The address high output pins, WR, WRL, WRH, HRQ, HAK, RDY, and CLK can be used as ports by function selection. For details, see Section 6.2 "External Memory Access (External Bus Pin Control Circuit)". 133 CHAPTER 6 MEMORY ACCESS MODES 6.2 External Memory Access (External Bus Pin Control Circuit) The external bus pin control circuit controls external bus pins used to expand the address/data buses of the CPU outside. ■ External Memory Access (External Bus Pin Control Circuit) To access memory/peripheral circuits installed outside the device, the F2MC-16LX supplies the following address/data/control signals: • CLK (P37): Machine cycle clock (KBP) output pin • RDY (P36): External ready input pin • WRH (P33): Write signal for high-order eight bits of the data bus • WRL (P32): Write signal for low-order eight bits of the data bus • RD (P31): Read signal • ALE (P30): Address latch enable signal ■ Block Diagram of External Memory Access (External Bus Pin Control Circuit) Figure 6.2-1 "Block Diagram of External Memory Access (External Bus Pin Control Circuit" shows a block diagram of external memory access (external bus pin control circuit). Figure 6.2-1 Block Diagram of External Memory Access (External Bus Pin Control Circuit) P3 P2 P1 P3 P0 P0 data P0 direction RB Data control Address control Access control 134 Access control P0 6.2 External Memory Access (External Bus Pin Control Circuit) 6.2.1 Registers for External Memory Access (External Bus Pin Control Circuit) External memory access (external bus pin control circuit) has the following three types of registers: • Automatic ready function selection register • External address output control register • Bus control signal selection register ■ Registers for External Memory Access (External Bus Pin Control Circuit) Figure 6.2-2 Registers for External Memory Access (External Bus Pin Control Circuit) Automatic ready function selection register 15 14 IOR1 IOR0 (W) (0) (W) (0) (W) (1) (W) (1) (-) (-) (-) (-) (W) (0) (W) (0) External address output control register 7 6 5 4 3 2 1 0 Address:0000A6H E23 E22 E21 E20 E19 E18 E17 E16 (W) (0) (W) (0) (W) (0) (W) (0) (W) (0) (W) (0) (W) (0) (W) (0) 15 14 13 12 11 10 9 8 CKE RYE HDE (W) (0) (W) (0) (W) (0) Address:0000A5H Read/write Initial value Read/write Initial value Bus control signal selection register Address:0000A7H Read/write Initial value 13 12 11 10 HMR1 HMR0 8 LMR1 LMR0 IOBS HMBS WRE (W) (0) 9 (W) (0) (W) (0) LMBS (W) (0) Bit No. ARSR Bit No. HACR Bit No. ECSR (-) (-) 135 CHAPTER 6 MEMORY ACCESS MODES 6.2.2 Automatic Ready Function Selection Register (ARSR) This register sets the automatic wait time of memory access for each area at external access. ■ Automatic Ready Function Selection Register (ARSR) Figure 6.2-3 Configuration of the Automatic Ready Function Selection Register Automatic ready function selection register 15 14 Address:0000A5H IOR1 IOR0 Read/write Initial value (W) (0) (W) (0) 13 12 11 10 HMR1 HMR0 (W) (1) (W) (1) 9 8 LMR1 LMR0 (-) (-) (-) (-) (W) (0) Bit No. ARSR (W) (0) [Bits 15 and 14] IOR1 and IOR0 The IOR1 and IOR0 bits specify an automatic wait function for external access to area 0000C0H to 0000FFH. IOR1 and IOR0 bits are combined as listed in Table 6.2-1 "Function of IOR1 and IOR0 (Automatic Wait Function Specification Bits)". Table 6.2-1 Function of IOR1 and IOR0 (Automatic Wait Function Specification Bits) IOR1 IOR0 Function 0 0 Prohibits automatic wait. [Initial value*] 0 1 Insert automatic 1-machine cycle wait at external access. 1 0 Insert automatic 2-machine cycle wait at external access. 1 1 Insert automatic 3-machine cycle wait at external access. *: The initial value is 00B. [Bits 13 and 12] HMR1 and HMR0 The HMR1 and HMR0 bits specify an automatic wait function for external access to area 800000H to FFFFFFH. HMR1 and HMR0 bits are combined as listed in Table 6.2-2 "Function of HMR1 and HMR0 (Automatic Wait Function Specification Bits)". Table 6.2-2 Function of HMR1 and HMR0 (Automatic Wait Function Specification Bits) HMR1 HMR0 0 0 Prohibits automatic wait. 0 1 Insert automatic 1-machine cycle wait at external access. 1 0 Insert automatic 2-machine cycle wait at external access. 1 1 Insert automatic 3-machine cycle wait at external access. [Initial value*] *: The initial value is 11B. 136 Function 6.2 External Memory Access (External Bus Pin Control Circuit) [Bits 9 and 8] LMR1 and LMR0 The LMR1 and LMR0 bits specify an automatic wait function for external access to area 002000H to 7FFFFFH. LMR1 and LMR0 bits are combined as listed in Table 6.2-3 "Function of LMR1 and LMR0 (Automatic Wait Function Specification Bits)". Table 6.2-3 Function of LMR1 and LMR0 (Automatic Wait Function Specification Bits) LMR1 LMR0 Function 0 0 Prohibits automatic wait. [Initial value*] 0 1 Insert automatic 1-machine cycle wait at external access. 1 0 Insert automatic 2-machine cycle wait at external access. 1 1 Insert automatic 3-machine cycle wait at external access. *: The initial value is 00B. 137 CHAPTER 6 MEMORY ACCESS MODES 6.2.3 External Address Output Control Register (HACR) This register controls external output of address output pins (A23 to A16). Respective bits correspond to address output pins A23 to A16 and control the address output pins as shown in Figure 6.2-4 "Configuration of the External Address Output Control Register". ■ External Address Output Control Register (HACR) Figure 6.2-4 Configuration of the External Address Output Control Register External address output control register Address:0000A6H Read/write Initial value 7 6 5 4 3 2 1 0 E23 E22 E21 E20 E19 E18 E17 E16 (W) (0) (W) (0) (W) (0) (W) (0) (W) (0) (W) (0) (W) (0) (W) (0) Bit No. HACR The HACR register cannot be accessed when the device is in the single-chip mode. In this mode, all pins function as I/O port pins regardless of the value of this register. All bits of this register are dedicated to writing. For reading, all bits are set to 1. When using the bits for address output, set the port-2 data direction register (DDR2) to 0. Table 6.2-4 Function of the External Address Output Control Register (E16 to E23 bits) E16 to 23 138 Function 0 The corresponding pin acts as an address output pin (AXX). [Initial value] 1 The corresponding pin acts as an I/O port pin (PXX). 6.2 External Memory Access (External Bus Pin Control Circuit) 6.2.4 Bus Control Signal Selection Register (ECSR) This register sets a control function of bus operation in an external bus mode. This register cannot be accessed when the device is in the single-chip mode. In this mode, all pins function as I/O port pins regardless of the value of this register. All bits of this register are dedicated to writing. For reading, all bits are set to 1. ■ Bus Control Signal Selection Register (ECSR) Figure 6.2-5 Configuration of the Bus Control Signal Selection Register Control signal selection register 15 14 13 Address:0000A7H CKE RYE HDE Read/write Initial value (W) (0) (W) (0) (W) (0) 12 11 10 9 Bit No. 8 IOBS HMBS WRE LMBS (W) (0) (W) (0) (W) (0) (W) (0) ECSR (-) (-) [Bit 15] CKE The CKE bit controls output of the external clock (CLK) as listed in Table 6.2-5 "Function of CKE (External Clock (CLK) Output Control Bit)". Table 6.2-5 Function of CKE (External Clock (CLK) Output Control Bit) CKE Function 0 I/O port (P37) operation (Prohibits clock output.)[Initial value] 1 Enables clock signal (CLK) output. [Bit 14] RYE The RYE bit controls input of the external ready (RDY) as listed in Table 6.2-6 "Function of RYE (External Ready (RDY) Input Control Bit)". Table 6.2-6 Function of RYE (External Ready (RDY) Input Control Bit) RDY Function 0 I/O port (P36) operation (Prohibits external RDY input.)[Initial value] 1 Enables external ready (RDY) input. [Bit 13] HDE The HDE bit enables input/output of hold-related pins. The HDE bit controls hold request input (HRQ) and hold acknowledge output (HAK) as listed in Table 6.2-7 "Function of HDE 139 CHAPTER 6 MEMORY ACCESS MODES (Input/Output Enable Bit Of Hold Related Pins)". Table 6.2-7 Function of HDE (Input/Output Enable Bit Of Hold Related Pins) HDE Function 0 I/O port (P35 and P34) operation (Prohibits hold function input/output.)[Initial value] 1 Enables input of hold request (HRQ)/output of hold acknowledge (HAK). [Bit 12] IOBS The IOBS bit specifies a bus size for external access to the area 0000C0H to 0000FFH in an external 16-bit data bus mode. This bit controls the size as listed in Table 6.2-8 "Function of IOBS (Bus Size Specification Bit)". Table 6.2-8 Function of IOBS (Bus Size Specification Bit) IOBS Function 0 16-bit bus access [Initial value*] 1 8-bit bus access *: The IOBS bit is cleared to 0 by reset. [Bit 11] HMBS The HMBS bit specifies a bus size for external access to the area 800000H to FFFFFFH in an external 16-bit data bus mode. This bit controls the size as listed in Table 6.2-9 "Function of HMBS (Bus Size Specification Bit)". Table 6.2-9 Function of HMBS (Bus Size Specification Bit) HMBS Function 0 16-bit bus access [Initial value] 1 8-bit bus access [Bit 10] WRE The WRE bit controls output of the external write signal (in a 16-bit bus mode, the WRH and WRL pins and in an 8-bit bus mode, the WR pin) as listed in Table 6.2-10 "Function of WRE (External Write Signal Output Control Bit)". In an external 8-bit data bus mode, P33 operates as an I/O port pin regardless of the set value of this bit. Table 6.2-10 Function of WRE (External Write Signal Output Control Bit) WRE Function 0 I/O port (P33, P32) operation (Prohibits write signal output.) [Initial value*] 1 Enables output of the write strobe signal (WRH and WRL or only WR) *: The WRE bit is cleared to 0 by reset. 140 6.2 External Memory Access (External Bus Pin Control Circuit) [Bit 9] LMBS The LMBS bit specifies a bus size for external access to the area 002000H to 7FFFFFH in an external 16-bit data bus mode. This bit controls the size as listed in Table 6.2-11 "Function of LMBS (Bus Size Specification Bit)". Table 6.2-11 Function of LMBS (Bus Size Specification Bit) LMBS Function 0 16-bit bus access [Initial value*] 1 8-bit bus access *: The LMBS bit is cleared to 0 by reset. Note: In a 16-bit bus mode, to enable the WRH and WRL functions by the WRE bit, set P33 and P32 to the input mode (set bits 3 and 2 of DDR3 to 0). In an 8-bit bus mode, to enable the WR function by the WRE bit, set P32 to the input mode (set bit 2 of DDR3 to 0). When the RYE or HDE bit enables RDY or HRQ to be input respectively, the I/O port function of the port pin is validated. Set the bit corresponding to the port pin in DDR3 to 0 (input mode). 141 CHAPTER 6 MEMORY ACCESS MODES 6.3 Operation of the External Memory Access Control Signals External memory is accessed at intervals of three cycles when the ready function is not used. Eight-bit bus access in an external 16-bit bus mode enables 8-bit peripheral chips to be read and written if 8-bit peripheral chips and 16-bit peripheral chips are connected to the external bus together. ■ External Memory Access Control Signal Because 8-bit bus access is executed using low-order eight bits of the data bus, connect an 8bit peripheral chip to low-order eight bits of the data bus. The access that is executed in an external 16-bit bus mode, 16-bit bus access or 8-bit bus access, is specified by the HMBS, LMBS, and IOBS of the EPCR. In some cases, address output and ALE assert output are performed and RD/WR/WRL/WRH are not asserted not to perform an actual bus operation. Do not execute access of peripheral circuit chips by the ALE signal only. Figure 6.3-1 "Timing Chart of External Memory Access (in an External 8-Bit Bus Mode)" shows the timing chart of external memory access (in an external 8-bit bus mode). Figure 6.3-2 "Timing Chart of External Memory Access (in an External 16-Bit Bus Mode)" shows the timing chart of external memory access (in an external 16-bit bus mode). Figure 6.3-1 Timing Chart of External Memory Access (in an External 8-Bit Bus Mode) Read Write Read P37/CLK P33/WRH (Port data) P32/WRL/WR P31/RD P30/ALE P27 to 20/A23 to 16 Read address Write address Read address P17 to 10/A15 to 08 Read address Write address Read address P07 to 00/AD07 to 00 Read address Write address Read address Read data 142 Write data 6.3 Operation of the External Memory Access Control Signals Figure 6.3-2 Timing Chart of External Memory Access (in an External 16-Bit Bus Mode) 8-bit bus byte read Even-numbered address byte read 8-bit bus byte write Even-numbered address byte write P27 to 20/A23 to 16 Read address Write address P17 to 10/AD15 to 08 Read address P07 to 00/AD07 to 00 Read address P37/CLK P33/WRH P32/WRL/WR P31/RD P30/ALE Invalid Read address Write address (Not defined) Read address Write address Read data Read address Write data Odd-numbered address byte read Odd-numbered address byte write P27 to 20/A23 to 16 Read address Write address Read address P17 to 10/AD15 to 08 Read address Write address Read address P07 to 00/AD07 to 00 Read address P37/CLK P33/WRH P32/WRL/WR P31/RD P30/ALE Even-numbered address word read Invalid Write address (Not defined) Read address Read data Write data Even-numbered address word write P37/CLK P33/WRH P32/WRL/WR P31/RD P30/ALE P27 to 20/A23 to 16 Read address Write address Read address P17 to 10/AD15 to 08 Read address Write address Read address P07 to 00/AD07 to 00 Read address Write address Read address Read data Write data Design external circuits so that data is always read in units of words length. Access to low-speed memory and peripheral circuits is enabled by setting of the P36/RYD pin or the automatic ready function selection register (ARSR). 143 CHAPTER 6 MEMORY ACCESS MODES 6.3.1 Ready Function Access to low-speed memory and peripheral circuits is enabled by setting of the P36/ RDY pin or the automatic ready function selection register (ARSR). If the RYE bit of the bus control signal selection register (EPCR) is set to 1, control enters a wait cycle during access to an external area as long as the low level is input to the P36/RDY pin. Thus, an access cycle can be expanded. ■ Ready Function Figure 6.3-3 Ready Timing Chart Even-numbered address word read Even-numbered address word write P37/CLK P33/WRH P32/WRL/WR P31/RD P30/ALE P27 to 20/A23 to 16 Read addrress Write address P17 to 10/AD15 to 08 Read addrress Write address P07 to 00/AD07 to 00 Read addrress Write address P36/RDY Read addrress RDY pin fetch Read data Even-numbered address word write Even-numbered address word read P37/CLK P33/WRH P32/WRL/WR P31/RD P30/ALE P27 to 20/A23 to 16 Write address Read address P17 to 10/AD15 to 08 Write address Read address P07 to 00/AD07 to 00 Write address Read address Write data Cycle expanded by the auto ready function 144 Write data 6.3 Operation of the External Memory Access Control Signals The F2MC-16LX installs two types of the auto ready function. The auto ready function for external memory can expand an access cycle by inserting one to three wait cycles automatically using no external circuit in the following cases: The external area at low-order addresses 002000H to 7FFFFFH is accessed and the external area at high-order addresses 800000H to FFFFFFH is accessed. This function is activated by setting the LMR1 and LMR0 bits (low-order address external area) of the ARSR and the HMR1 and HMR0 bits (high-order address external area) of the ARSR. Additionally, the F2MC-16LX installs the auto ready function for external I/O independently from the auto ready function for external memory. This function expands an access cycle by inserting one to three wait cycles automatically with no external circuit at access to the external area in addresses 0000C0H to 0000FFH. This function is activated by setting the IOR1 and IOR0 bits of the ARSR. For the auto ready function for external memory and for external I/O, the wait cycle continues as is if the RYE bit of the EPCR is set to 1 and the low level is input to the P36/RDY pin after the wait cycle applied by the auto ready function terminates. 145 CHAPTER 6 MEMORY ACCESS MODES 6.3.2 Hold Function If the HDE bit in the bus control signal selection register (EPCR) is set to 1, the external bus hold function specified by the P34/HRQ and P35/HAK bits is enabled. ■ Hold Function If the high level is applied to the P34/HRQ pin, the hold state is set up at termination of a CPU instruction (for a string instruction, at termination of 1-element data processing). The P35/HAK pin outputs the low level to place the following pins in a high-impedance state: • Address output: P27/A23 to P20/A16 • Address/data I/O: P17/AD15 to P00/AD00 • Bus control signal: P30/ALE, P31/RD, P32/WRL/WR, P33/WRH Thus, an external bus can be used from a device external circuit. When the low level is input to the P34/HRQ pin, the P35/HAK pin outputs the high-level, thereby restoring the external pin state and restarting the CPU operation. In the stop status, hold request input is not accepted. Figure 6.3-4 "Hold Timing (in an External Bus 16-Bit Mode)" shows the hold timing (in an external 16-bit bus mode). Figure 6.3-4 Hold Timing (in an External Bus 16-Bit Mode) Read cycle Hold cycle Write cycle P37/CLK P34/HRQ P35/HAK P33/WRH P32/WRL/WR P31/RD P30/ALE P27 to 20/A23 to 16 (Address) (Address) P17 to 10/AD15 to 08 (Address) P07 to 00/AD07 to 00 (Address) Read data 146 Write data CHAPTER 7 I/O PORTS This chapter describes the functions and operations of I/O ports. 7.1 "I/O Port Overview" 7.2 "I/O Port Block Diagram" 7.3 "I/O Port Registers" 147 CHAPTER 7 I/O PORTS 7.1 I/O Port Overview Input or output can be specified for each pin in a port by the data direction register if the corresponding peripheral circuit is specified not to use the pin. If the data register is read while the pin is set to input, the level value of the pin is read. If the data register is read while the pin is set to output, the data register latch value is read. The same is true for read during read modify write. ■ I/O Port Overview If the data register is read while the pin is used for control output, the level output as control output is read regardless of the value of the data direction register. When a read modify write instruction (such as a bit set instruction) is used for setting output data in the data register in advance to change input setting to output setting, note the following point: The input data, not the data register latch value, is read from the pin. Ports 0 to A serve as input ports if the data direction register in each I/O port is 0 and as output ports if it is 1. The MB90580C series also uses port 0 to 3 as external bus pins. Therefore, use of these ports is limited in an external bus mode. For ports 2 and 3, some bits can be used as port pins by function selection even in an external bus mode. For details, see Section 6.2 "External Memory Access (External Bus Pin Control Circuit)". 148 7.2 I/O Port Block Diagram 7.2 I/O Port Block Diagram Figure 7.2-1 "Parallel Port Block Diagram (Ports 2, 3, 7, 8, 9, and A)" to Figure 7.2-2 "Parallel Port Block Diagram (Port 4)" show the following I/O port block diagrams. ■ I/O Port Block Diagram Figure 7.2-1 I/O Port Block Diagram (Ports 0, 1, and 6) Internal data bus RDR Data register read Data register Pin Data register write Data direction register Data direction register write Standby control (SPL=1) Data direction register read Figure 7.2-2 I/O Port Block Diagram (Ports 2, 3, 7, 8, 9, and A) Internal data bus Data register read Data register Pin Data register write Data direction register Data direction register write Data direction register read 149 CHAPTER 7 I/O PORTS Figure 7.2-3 I/O Port Block Diagram (Port 4) Pin register Internal data bus Data register read Data register Pin Data register write Data direction register Data direction register write Data direction register read Standby control (SPL=1) Figure 7.2-4 I/O Port Block Diagram (Port 5) Internal data bus ADER Data register read Data register Pin Data register write Data direction register Data direction register write Standby control (SPL=1) Data direction register read 150 7.3 I/O Port Registers 7.3 I/O Port Registers The five I/O port registers are as follows: • Port data registers (PDRx) • Port data direction registers (DDRx) • Output pin register (ODR4) • Input resistor registers (RDR0 and RDR1) • Analog input enable register (ADER) ■ I/O Port Registers Figure 7.3-1 I/O Port Registers (to next page) 15/ 7 14/6 13/5 12/4 11/3 10/2 9/1 8/0 000 H Address: 000 P07 P06 P05 P04 P03 P02 P01 P00 Port 0 data register (PDR0) Address: 000 001 H P17 P16 P15 P14 P13 P12 P11 P10 Port 1 data register (PDR1) Address: 000 002 H P27 P26 P25 P24 P23 P22 P21 P20 Port 2 data register (PDR2) Address: 000 003 H P37 P36 P35 P34 P33 P32 P31 P30 Port 3 data register (PDR3) Address: 000 004 H P47 P46 P45 P44 P43 P42 P41 P40 Port 4 data register (PDR4) Address: 000 005 H P57 P56 P55 P54 P53 P52 P51 P50 Port 5 data register (PDR5) P65 P64 P63 P62 P61 P60 Port 6 data register (PDR6) P74 P73 P72 P71 Bit 006 H Address: 000 007 H Address: 000 Port 7 data register (PDR7) 008 H Address: 000 P87 P86 P85 P84 P83 P82 P81 P80 Port 8 data register (PDR8) Address: 000 009 H P97 P96 P95 P94 P93 P92 P91 P90 Port 9 data register (PDR9) PA2 PA1 PA0 Port A data register (PDRA) Address: 000 00A H Bit 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0 010 H Address: 000 D07 D06 D05 D04 D03 D02 D01 D00 Port 0 data direction register (DDR0) 011 H Address: 000 D17 D16 D15 D14 D13 D12 D11 D10 Port 1 data direction register (DDR1) Address: 000 012 H D27 D26 D25 D24 D23 D22 D21 D20 Port 2 data direction register (DDR2) 013 H Address: 000 D37 D36 D35 D34 D33 D32 D31 D30 Port 3 data direction register (DDR3) 014 H Address: 000 D47 D46 D45 D44 D43 D42 D41 D40 Port 4 data direction register (DDR4) Address: 000 015 H D57 D56 D55 D54 D53 D52 D51 D50 Port 5 data direction register (DDR5) D65 D64 D63 D62 D61 D60 Port 6 data direction register (DDR6) D74 D73 D72 D71 Address: 000 016 H 017 H Address: 000 Port 7 data direction register (DDR7) 018 H Address: 000 D87 D86 D85 D84 D83 D82 D81 P80 Port 8 data direction register (DDR8) 019 H Address: 000 D97 D96 D95 D94 D93 D92 D91 D90 Port 9 data direction register (DDR9) DA 2 DA1 PA0 Port A data direction register (DDRA) 01A H Address: 000 151 CHAPTER 7 I/O PORTS 15 14 13 12 11 10 9 8 OD47 OD46 OD45 OD44 OD43 OD42 OD41 OD40 7 6 5 4 3 2 1 0 Address: 00001C H ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 Bit 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0 Address: 00008C H RD07 RD06 RD05 RD04 RD03 RD02 RD01 RD00 Port 0 input resistor register (RDR0) Address: 00008DH RD17 RD16 RD15 RD14 RD13 RD12 RD11 RD10 Port 1 input resistor register (RDR1) RD65 RD64 RD63 RD62 RD61 RD60 Port 6 input resistor register (RDR6) Bit Address: 00001B H Bit Address: 00008EH 152 Port 4 output pin register (ODR4) Port 5 analog input enable register (ADER) 7.3 I/O Port Registers 7.3.1 Port Data Registers (PDRx) Pin statuses are read by port data registers (PDRx). ■ Port Data Register (PDRx) Figure 7.3-2 Port Data Register PDR0 Address: 000000H 7 6 5 4 3 2 1 0 P07 P06 P05 P04 P03 P02 P01 P00 PDR1 Address: 000001H 15 14 13 12 11 10 9 8 P17 P16 P15 P14 P13 P12 P11 P10 7 6 5 4 3 2 1 0 P27 P26 P25 P24 P23 P22 P21 P20 PDR2 Address: 000002H PDR3 Address: 000003H 15 14 13 12 11 10 9 8 P37 P36 P35 P34 P33 P32 P31 P30 PDR4 Address: 000004H 7 6 5 4 3 2 1 0 P47 P46 P45 P44 P43 P42 P41 P40 PDR5 Address: 000005H 15 14 13 12 11 10 9 8 P57 P56 P55 P54 P53 P52 P51 P50 7 6 5 4 3 2 1 0 P65 P64 P63 P62 P61 P60 8 PDR6 Address: 000006H PDR7 Address: 000007H 15 14 13 12 11 10 9 P74 P73 P72 P71 7 6 5 4 3 2 1 0 P87 P86 P85 P84 P83 P82 P81 P80 PDR9 Address: 000009H 15 14 13 12 11 10 9 8 P97 P96 P95 P94 P93 P92 P91 P90 7 6 5 4 3 2 1 0 PA2 PA1 PA0 Access XXXXXXXXB R/W XXXXXXXXB R/W XXXXXXXXB R/W XXXXXXXXB R/W XXXXXXXXB R/W 11111111B R/W --XXXXXXB ---XXXX-B PDR8 Address: 000010H PDRA Address: 00000AH Initial value R/W R/W XXXXXXXXB R/W XXXXXXXXB R/W -----XXXB R/W Note: Note that the operation of input port R/W differs from that of memory R/W. Input mode - Read: The level of a corresponding pin is read. - Write: An output latch is written. Output mode - Read: The data register latch value is read. - Write: Output to a corresponding pin 153 CHAPTER 7 I/O PORTS 7.3.2 Port Data Direction Registers (DDRx) In a port data direction register (DDRx), a bit sets the I/O direction of its corresponding pin. If the bit corresponding to a port (pin) is set to 1, the port becomes an output port (pin). If the bit is set to 0, the port becomes an input port (pin). ■ Port Data Direction Register (DDRx) Figure 7.3-3 Port Data Direction Register (DDRx) DDR0 Address: 000010H 7 6 5 4 3 2 1 0 D07 D06 D05 D04 D03 D02 D01 D00 DDR1 Address: 000011H 15 14 13 12 11 10 9 8 D17 D16 D15 D14 D13 D12 D11 D10 DDR2 Address: 000012H 7 6 5 4 3 2 1 0 D27 D26 D25 D24 D23 D22 D21 D20 15 14 13 12 11 10 9 8 D37 D36 D35 D34 D33 D32 D31 D30 DDR3 Address: 000013H DDR4 Address: 000014H 7 6 5 4 3 2 1 0 D47 D46 D45 D44 D43 D42 D41 D40 DDR5 Address: 000015H 15 14 13 12 11 10 9 8 D57 D56 D55 D54 D53 D52 D51 D50 7 6 DDR6 Address: 000016H DDR7 Address: 000017H 14 4 3 2 1 0 D64 D63 D62 D61 D60 8 13 12 11 10 9 D74 D73 D72 D71 DDR8 Address: 000018H 7 6 5 4 3 2 1 0 D87 D86 D85 D84 D83 D82 D81 D80 DDR9 Address: 000019H 15 14 13 12 11 10 9 8 D97 D96 D95 D94 D93 D92 D91 D90 7 6 5 4 3 2 1 0 DA2 DA1 DA0 DDRA Address: 00001AH 154 15 5 D65 Initial value Access 00000000B R/W 00000000B R/W 00000000B R/W 00000000B R/W 00000000B R/W 00000000B R/W --000000B R/W ---0000-B R/W 00000000B R/W 00000000B R/W -----000B R/W 7.3 I/O Port Registers A port data direction register (DDRx) controls each pin as listed in Table 7.3-1 "Function of a Port Data Direction Register (DDRx)" when the pin functions as a port pin. Table 7.3-1 Function of a Port Data Direction Register (DDRx) DDRx Function 0 Input mode [initial value] 1 Output mode Note: When using as a resource input, specify 0 (input mode). 155 CHAPTER 7 I/O PORTS 7.3.3 Port 4 Output Pin Register (ODR4) The Port 4 output pin register (ODR4) controls open-drain in an output mode. ■ Port 4 Output Pin Register (ODR4) Figure 7.3-4 Port 4 Output Pin Register (ODR4) 15 14 13 12 11 10 9 8 OD47 OD46 OD45 OD44 OD43 OD42 OD41 OD40 Bit Address:00001BH Port 4 output pin register (ODR4) Initial value: 0000000H Table 7.3-2 Function of the Output Pin Register (ODR4) ODR4 Function 0 Sets the port as a standard output port in an output mode. [Initial value] 1 Sets the port as the open-drain output port in an output mode. Note: This register has no meaning in an input mode. (Output Hi-z) The data direction register (DDR) determines the I/O mode. 156 7.3 I/O Port Registers 7.3.4 Input Pull-up Resistor Setting Registers (RDR0, RDR1, and RDR6) An input pull-up resistor setting register (RDR0, RDR1, and RDR6) controls a pull-up resistor in an input mode. ■ Input Pull-up Resistor Setting Registers (RDR0, RDR1, and RDR6) Figure 7.3-5 Input Pull-up Resistor Setting Registers (RDR0, RDR1, and RDR6) Bit Address:00008CH Bit Address:00008DH Bit Address:00008EH 7 6 5 4 3 2 1 0 RD07 RD06 RD05 RD04 RD03 RD02 RD01 RD00 15 16 15 14 13 12 11 10 RD17 RD16 RD15 RD14 RD13 RD12 RD1 RD10 Port 1 input pull-up resistor setting register (RDR1) Initial value: 00000000B 7 6 5 4 3 2 1 RD67 RD66 RD65 RD64 RD63 RD62 RD61 RD60 Port 6 input pull-up resistor setting register (RDR6) Initial value: 00000000B Port 0 input pull-up resistor setting register (RDR0) Initial value: 00000000B Table 7.3-3 Function of the Input Pull-up Resistor Setting Registers (RDR0, RDR1, and RDR6) RDR0,1,6 Function 0 Without a pull-up resistor in an input mode [initial value] 1 With a pull-up resistor in an input mode Note: These registers have no meaning in an output mode. (Without a pull-up resistor) The data direction register (DDR) determines the I/O mode. The pull-up resistor is not provided during hardware standby and stop (SPL = 1)(high impedance). This function is prohibited in an external bus mode. Do not write this register. 157 CHAPTER 7 I/O PORTS 7.3.5 Port 5 Analog Input Enable Register (ADER) The Port 5 analog input enable register (ADER) controls each pin of port 5 as listed in Table 7.3-4 "Port 5 Analog Input Enable Register (ADER)". ■ Port 5 Analog Input Enable Register (ADER) Figure 7.3-6 Port 5 Analog Input Enable Register (ADER) 7 6 5 4 3 2 1 0 ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 R/W R/W R/W R/W R/W R/W R/W R/W Bit Address:00001CH Port 5 analog input enable register (ADER) Initial value: 11111111B Table 7.3-4 Port 5 Analog Input Enable Register (ADER) ADER Setting 0 Port input mode 1 Analog input mode [initial value] Note: If a middle-level signal is input in the port input mode, an input leakage current flows. Therefore, set the analog input mode for analog input. 158 CHAPTER 8 TIME-BASED TIMER This chapter describes the functions and operations of the time-based timer. 8.1 "Overview of the Time-Based Timer" 8.2 "Time-Based Timer Control Register (TBTC)" 8.3 "Time-Based Timer Operations" 159 CHAPTER 8 TIME-BASED TIMER 8.1 Overview of the Time-Based Timer The time-based timer consists of an 18-bit timer and a circuit for controlling interval interrupts and uses oscillation clocks regardless of the MCS bit in CKSCR. ■ Time-based Timer Register Figure 8.1-1 Time-based Timer Register Time-based timer control register 15 Address:0000A9H Read/write Initial value 160 14 13 Reserved (-) (1) (-) (-) (-) (-) 12 11 10 9 8 TBIE TBOF TBR TBC1 TBC0 (R/W) (R/W) (0) (0) (W) (1) (R/W) (R/W) (0) (0) Bit No. TBTC 8.1 Overview of the Time-Based Timer ■ Time-based Timer Block Diagram Figure 8.1-2 Time-based Timer Block Diagram Main clock TBTC TBC1 Selector TBC0 Clock input 2 12 2 14 Time-based timer 2 16 2 19 14 19 12 TBTRES 2 2 2 16 2 TBR TBIE AND Q TBOF S R Time base interrupt WDTC Selector 2-bit counter OF CLR Selector 2 910 2 11 2 12 2 13 2 14 2 15 2 WT1 WT0 Watchdog reset generation circuit CLR To the WDGRST internal reset generation circuit WTE F2MC-16LX bus WTC WDCS AND SCE Q S R WTC2 WTC1 WTC0 WTR WTIE WTOF WTRES AND Q S R 210 2 13 214 215 Clock timer Clock input Subclock/4 Clock interrupt WDTC PONR From power-on generation STBR From the hardware standby control circuit WRST ERST From RST pin SRST From the RST bit of the LPMCR register 161 CHAPTER 8 TIME-BASED TIMER 8.2 Time-Based Timer Control Register (TBTC) The time-based timer control register (TBTC) can control time-based timer interrupts and can clear the time base counter. ■ Time-based Timer Control Register (TBTC) Figure 8.2-1 Configuration of the Time-based Timer Control Register (TBTC) Time-based timer control register 15 Address:0000A9H 14 13 Reserved Read/write Initial value (-) (1) (-) (-) (-) (-) 12 11 TBIE TBOF (R/W) (R/W) (0) (0) 10 9 TBR TBC1 (W) (1) 8 TBC0 Bit No. TBTC (R/W) (R/W) (0) (0) Note: Because access by read modify instructions causes malfunctions, do not use the read modify instructions to obtain access. [Bit 15] Reserved Bit 15 is reserved. To set TBTC, this bit must be set to 1. [Bit 12] TBIE TBIE is used to enable an interval interrupt to be generated by the time-based timer. When this bit is 1, an interrupt is enabled. When it is 0, the interrupt is disabled. It is initialized to 0 by reset and is readable and writable. [Bit 11] TBOF TBOF is a flag for requesting a time-based timer interrupt. An interrupt occurs when the TBIE bit is 1 and TBOF is set to 1. TBOF is set to 1 for each interval set by the TBC1 and TBC0 bits. It is cleared by writing 0, the transition to the hardware standby mode or stop mode, or reset. Writing 1 is meaningless. Value 1 is read during reading by read modify write instructions. [Bit 10] TBR The TBR bit is used to clear all bits of the time-based timer counter to 0. The time base counter is cleared by writing 0. Writing 1 is meaningless. During reading, 1 is read. Note: To clear the TBOF bit, mask a time-based timer interrupt by the TBIE bit or CPU ILM bit. 162 8.2 Time-Based Timer Control Register (TBTC) [Bits 9 and 8] TBC1 and TBC0 TBC1 and TBC0 bits are used to set an interval of the time-based timer. These bits are initialized to 00 by reset and are readable and writable. Table 8.2-1 Interval times and number of cycles for TBC1 and TBC0 TBC1 TBC0 Interval time for oscillation 4MHz Number of oscillation clock (oscillation) cycles 0 0 1.024 ms 212 0 1 4.096 ms 214 1 0 16.384 ms 216 1 1 131.072 ms 219 163 CHAPTER 8 TIME-BASED TIMER 8.3 Time-Based Timer Operations The time-based timer functions as a timer for waiting for an oscillation stabilization time of a watchdog timer clock source, main clock, and PLL clock and as an interval timer for generating an interrupt in a given cycle. ■ Time-based Timer Operations The time-based timer consists of an 18-bit counter for counting oscillation inputs that are the origin for creating machine clocks. The timer continues the count operation while oscillation is input. The time base counter is cleared by power-on reset, a transition to the stop mode or hardware standby mode, a transition from the main clock to the PLL clock by the MCS bit in the CKSCR register, or by writing 0 in the TBR bit of the TBTC register. The watchdog timer and interval interrupts that use time-based timer outputs are influenced by time-based timer clear. ■ Interval Interrupt Function This function generates an interrupt in a give cycle with a carry signal of the time base counter. The TBOF flag is set for each interval time set by TBC1 and TBC0 bits in the TBTC register. This flag is set on the basis of the time the time-based timer was last cleared. When the main clock mode changes to the PLL clock mode, the time-based timer is cleared because the time-based timer is used to wait for the oscillation stabilization of the PLL clock. When the stop mode or hardware standby mode is entered, the TBOF flag is cleared simultaneously with mode transition because the time-based timer is used to wait for the oscillation stabilization time at return. 164 CHAPTER 9 WATCHDOG TIMER This chapter describes the functions and operations of the watchdog timer. 9.1 "Overview of the Watchdog Timer" 9.2 "Watchdog Timer Control Register (WDTC)" 9.3 "Watchdog Timer Operations" 165 CHAPTER 9 WATCHDOG TIMER 9.1 Overview of the Watchdog Timer The watchdog timer consists of the 2-bit watchdog counter which uses a carry signal of the 18-bit time-based timer as a clock source, the control register, and the watchdog reset control section. ■ Watchdog Timer Register Figure 9.1-1 Watchdog Timer Register Watchdog control register Address:0000A8H Read/write Initial value 166 7 6 PONR STBR (R) (X) (R) (X) 5 4 3 2 1 0 WRST ERST SRST WTE WT1 WT0 (R) (X) (R) (X) (W) (1) (W) (1) (W) (1) (R) (X) Bit No. WDTC 9.1 Overview of the Watchdog Timer ■ Watchdog Timer Block Diagram Figure 9.1-2 Watchdog Timer Block Diagram Main clock TBTC TBC1 Selector TBC0 Clock input 2 12 2 14 16 Time-based timer 2 2 19 14 19 12 TBTRES 2 2 2 16 2 TBR TBIE AND Q TBOF S R Time base interrupt WDTC WT1 Selector WT0 2-bit counter CLR OF Watchdog reset generation circuit CLR To the WDGRST internal reset generation circuit WTE F2MC-16LX bus WTC WDCS AND SCE Q S R WTC2 WTC1 WTC0 Selector WTR WTIE WTOF 29 2 10 2 11 2 12 2 13 2 14 2 15 WTRES AND Q S R 210 2 13 214 215 Clock timer Clock input Subclock/4 Clock interrupt WDTC PONR STBR From power-on generation From the hardware standby control circuit WRST ERST From RST pin SRST From the RST bit of the LPMCR register 167 CHAPTER 9 WATCHDOG TIMER 9.2 Watchdog Timer Control Register (WDTC) The watchdog timer control register (WDTC) activates and clears the watchdog timer and displays a reset cause. ■ Watchdog Timer Control Register (WDTC) Figure 9.2-1 Watchdog Timer Control Register (WDTC) Watchdog control register 7 6 PONR STBR Address:0000A8H Read/write Initial value (R) (X) (R) (X) 5 4 3 2 1 0 WRST ERST SRST WTE WT1 WT0 (R) (X) (R) (X) (W) (1) (W) (1) (W) (1) (R) (X) Bit No. WDTC Note: Because access by read modify instructions causes malfunctions, do not use the read modify instructions to obtain access. [Bits 7 to 3] PONR, STBR, WRST, ERST, and SRST These bits are flags for indicating reset sources and are set by each reset as shown in Table 9.2-1 "PONR, STBR, WRST, ERST, and SRST (for Sources of Resets)". After the WDTC register read operation, all bits are cleared to 0. The WDTC register is a read-only register. Note that because the bit contents are not predictable when they indicate a reset cause other than power-on, software programs should be designed so that bits other than the PONR bit will be ignored when the PONR bit is 1. Table 9.2-1 PONR, STBR, WRST, ERST, and SRST (for Sources of Resets) Reset cause PONR STBR WRST ERST SRST Power-on 1 - - - - Hardware standby * 1 * * * Watchdog timer * * 1 * * External pin * * * 1 * RST bit * * * * 1 *: Retains the previous value. [Bit 2] WTE When the watchdog timer stops and 0 is written in WTE, the watchdog timer becomes operable. Second and subsequent 0 writings clear the watchdog timer counter. Writing 1 does not result in an operation. The watchdog timer stops by power-on, hardware standby, or reset by the watchdog timer. Value 1 is read at reading. 168 9.2 Watchdog Timer Control Register (WDTC) [Bits 1 and 0] WT1 and WT0 Two clocks system: WT1 and WT0 bits are used to select an interval time of the watchdog timer. Only data written during watchdog timer activation is valid. Data written at operation other than watchdog timer activation is ignored. These bits are writable only. Note that the clock to be input to the watchdog timer is selected according to the WDCS bit of the WTC register. Table 9.2-2 "WT1 and WT0 (Interval Time Selection Bits) of Two Clocks System" lists the interval time settings by the WT1 and WT0 bits. Table 9.2-2 WT1 and WT0 (Interval Time Selection Bits) of Two Clocks System WDCS WT1 WT0 Interval time (for oscillation clock frequency 4 MHz) Minimum Maximum (*) 1 0 0 About 3.58 ms About 4.61 ms 1 0 1 About 14.33 ms About 18.43 ms 1 1 0 About 57.23 ms About 73.73 ms 1 1 1 About 458.75 ms About 589.82 ms 0 0 0 About 0.457 s About 0.576 s 0 0 1 About 3.584 s About 4.608 s 0 1 0 About 7.168 s About 9.216 s 0 1 1 About 14.336 s About 18.432 s *: The maximum values of interval time are applied when the time base counter is not reset during the watchdog timer operation. 169 CHAPTER 9 WATCHDOG TIMER One clock system: Bits WT1 and WT0 are used to select an interval time for the watchdog timer. Only data written during Watchdog timer activation is valid. Data written at other times is ignored. These bits are write only. Table 9.2-3 "WT1 and WT0 (Interval Time Selection Bits) of One Clock System" lists the interval times set by bits WT1 and WT0. Table 9.2-3 WT1 and WT0 (Interval Time Selection Bits) of One Clock System Interval time (for oscillation clock frequency 4 MHz) WDCS WT1 WT0 Minimum Maximum (*) 1 0 0 About 3.58 ms About 4.61 ms 1 0 1 About 14.33 ms About 18.43 ms 1 1 0 About 57.23 ms About 73.73 ms 1 1 1 About 458.75 ms About 589.82 ms *: The maximum values of interval time are applied when the time base counter is not reset during the watchdog timer operation. 170 9.3 Watchdog Timer Operations 9.3 Watchdog Timer Operations The watchdog timer function can detect a program crash. The watchdog timer requests a reset if 0 is not written in the WTE bit of the WDTC register within the specified time due to a program crash. ■ Activating the Watchdog Timer The watchdog timer is activated by writing 0 in the WTE bit of the WDTC register while the watchdog timer stops. At the same time, the reset generation interval of the watchdog timer is set by WT1 and WT0 bits. Only data at this activation is valid for interval setting. ■ Preventing a Watchdog Timer Reset When the watchdog timer is started, the 2-bit watchdog counter must be cleared periodically in the program. In effect, 0 must be periodically written in the WTE bit of the WDTC register. The watchdog counter consists of a 2-bit counter that uses a carry signal of the time-based timer as a clock source. Therefore, if the time-based timer is cleared, the watchdog reset generation time may become longer than the specified time. Figure 9.3-1 Watchdog Timer Operations Time-base Watchdog 00 01 10 00 01 10 11 00 WTE write Watchdog start Watchdog clear Watchdog reset generation ■ Stopping the Watchdog Once the watchdog timer is started, it is only initialized by power-on, hardware standby, or a reset with the watchdog and is put in stop status. The watchdog counter is cleared by a reset with an external pin or software, though the watchdog function does not stop. ■ Clearing the Watchdog Timer The watchdog timer is cleared by a write to the WTE bit, the reset generation, a transition to the sleep or stop mode, or the hold acknowledge signal. 171 CHAPTER 9 WATCHDOG TIMER 172 CHAPTER 10 WATCH TIMER This chapter describes the functions and operations of the watch timer. The watch timer cannot be used for the one clock system. 10.1 "Overview of the Watch Timer" 10.2 "Watch Timer Control Register (WTC)" 10.3 "Watch Timer Operations" 173 CHAPTER 10 WATCH TIMER 10.1 Overview of the Watch Timer The watch timer functions as a clock source for the watchdog timer, a timer to wait for subclock oscillation stabilization time, and an interval timer to generate interrupts at specified intervals. ■ Watch Timer Control Register Figure 10.1-1 Watch Timer Control Register (WTC) Watch timer control register 7 Address: 0000AAH Read/write Initial value 174 6 WDCS SCE (R/W) (1) (R) (X) 5 4 3 WTIE WTOF WTR (R/W) (R/W) (0) (0) 2 1 0 WTC2 WTC1 WTC0 (R/W) (R/W) (0) (0) (R/W) (R/W) (0) (0) Bit No. WTC 10.1 Overview of the Watch Timer ■ Watch Timer Block Diagram Figure 10.1-2 Watch Timer Block Diagram Main clock TBTC TBC1 Selector TBC0 TBR TBIE AND TBOF Q Clock input 212 214 Time-based timer 2 16 2 18 TBTRES 212 214 216 219 S R Time base interrupt WDTC WT1 Selector 2 F MC-16LX bus WT0 2-bit counter OF CLR Watchdog reset generation circuit CLR WTE WDGRST To internal reset generation circuit WTC WDCS SCE AND Q S R WTC2 WTC1 WTC0 WTR WTIE Selector 29 2 10 2 11 2 12 2 13 2 14 2 15 210 2 13 214 Watch timer WTRES AND Q S R 215 Clock input Subclock/4 WTOF Clock interrupt WDTC PONR STBR WRST ERST SRST From power-on generation From hardware standby control circuit RST pin From RST bit of LPMCR register 175 CHAPTER 10 WATCH TIMER 10.2 Watch Timer Control Register (WTC) The watch timer control register (WTC) can select a clock signal, control interrupts and their intervals, and clear the watch timer counter. ■ Watch Timer Control Register (WTC) Figure 10.2-1 Watch Timer Control Register (WTC) Watch timer control register 7 Address: 0000AAH Read/write Initial value 6 WDCS SCE (R/W) (1) (R) (X) 5 4 3 WTIE WTOF WTR (R/W) (R/W) (0) (0) 2 1 0 WTC2 WTC1 WTC0 (R/W) (R/W) (0) (0) Bit No. WTC (R/W) (R/W) (0) (0) [Bit 7] WDCS The WDCS bit is used to select the clock signal from the watch timer or the clock signal from the time base timer as the input clock for the watchdog timer when the main clock or PLL clock is selected as the clock source. When this bit is 0, the clock signal from the watch timer is selected. When this bit is 1, the clock signal from the time base timer is selected. In the subclock mode, select the output of the watch timer with the WDCS bit setting to "0". If the mode transits to the subclock mode with the WDCS bit setting to "1", the watchdog timer stops. This bit is initialized to 1 by power-on reset. Note: When the WDCS bit is set to 1, the watchdog timer counter may run because time base timer output and watch timer output are asynchronous. To prevent this, when the WDCS bit is set to 1, clear the watchdog timer before and after the clock mode is changed. [Bit 6] SCE The SCE bit indicates the progress of subclock oscillation stabilization. When this bit is 0, subclock oscillation stabilization is in progress. The oscillation stabilization time is fixed to 216 cycles (for subclock). This bit is initialized to 0 by power-on reset or when the device is stopped. [Bit 5] WTIE The WTIE bit is used to enable or disable the interval interrupt by the watch timer. When this bit is 1, the interval interrupt is enabled. When this bit is 0, the interval interrupt is disabled. This bit is readable and writable and is initialized to 0 by reset. [Bit 4] WTOF The WTOF bit is a flag to request a watch timer interrupt. An interrupt request is generated when the WTIE bit is 1 and the WTOF bit is 1. The WTOF bit is set to 1 at the interval specified by the WTC2 to WTC0 bits. The WTOF bit is cleared by writing 0 in the bit, transition to the stop or hardware standby mode, or reset. Writing 1 in this bit is ignored. When this bit is read by a read, modify, or write instruction, the read value is always 1. 176 10.2 Watch Timer Control Register (WTC) [Bit 3] WTR The WTR bit is used to clear all bits of the watch timer counter to 0. Writing 0 in the WTR bit clears the clock counter. Writing 1 in the WTR bit is ignored. When the WTR bit is read, the read value is always 1. [Bits 2 to 0] WTC2, WTC1, and WTC0 The WTC2, WTC1, and WTC0 bits are used to set an interval for the watch timer. Interval settings are shown in Table 10.2-1 "Selection of watch timer interval". These bits are readable and writable and are initialized to 000 by reset. When writing a value in these bits, clear the bit 4 (WTOF). Table 10.2-1 Selection of watch timer interval WTC2 WTC1 WTC0 Interval (*) 0 0 0 62.5 ms 0 0 1 125.0 ms 0 1 0 250 ms 0 1 1 500 ms 1 0 0 1.0 s 1 0 1 2.000 s 1 1 0 4.000 s 1 1 1 - *: The interval is a value with the subclock at 32 kHz. 177 CHAPTER 10 WATCH TIMER 10.3 Watch Timer Operations The watch timer functions as a clock source for the watchdog timer, a timer to wait for subclock oscillation stabilization time, and an interval timer to generate interrupts at specified intervals. ■ Operations The watch timer has a 15-bit counter to count the source oscillation inputs that are used to generate subclock signals. The watch timer continues the counting operation while source oscillation inputs continue. The watch timer is cleared by power-on reset, transition to the stop or hardware standby mode, or writing 0 in the WTR bit of the WTC register. Clearance of the watch timer affects the watchdog counter and the interval interrupt function, which use watch timer output. ■ Interval Interrupt Function The interval interrupt function generates an interrupt at specified intervals with a carry signal of the clock counter. The WTOF flag is set at each interval set by the WTC2 to WTC0 bits of the WTC register. The timing of flag setting is based on the time when the watch timer was last cleared. When the device enters the stop or hardware standby mode, the WTOF flag is cleared at the same time as the mode transition because the watch timer is used to wait for the end of subclock oscillation stabilization time when restoring. ■ Setting Operation Clock for Watchdog Timer The clock source of the watchdog timer can be set by the WDCS bit in the watch timer control register (WTC). When the subclock is used for machine clock, select the watch timer output with the WDCS bit setting to "0". If the mode transits to the subclock mode with the WDCS bit setting to "1", the watchdog timer stops. 178 CHAPTER 11 PWC TIMER This chapter describes the functions and operations of the PWC timer. 11.1 "Overview of the PWC Timer" 11.2 "PWC Timer Block Diagram" 11.3 "PWC Timer Registers" 11.4 "PWC Timer Operations" 11.5 "Details of Timer Mode Operation" 11.6 "Flowchart of Timer Mode Operation" 11.7 "Details of Pulse Width Measurement Mode Operation" 11.8 "Notes on Handling the PWC Timer" 179 CHAPTER 11 PWC TIMER 11.1 Overview of the PWC Timer The PWC timer (pulse-width measurement) is the multifunction 16-bit up counter with the reload function and also has a function that calculates the pulse width of the input signal. The PWC timer consists of a 16-bit counter, an input pulse divider, a division rate control register, a count input pin, a pulse output pin, and a 16-bit control register. ■ Characteristics of PWC Timer The PWC timer has the following characteristics: ❍ Timer function • Generates an interrupt request at the specified time interval. • Outputs the pulse signal that is synchronized with the timer period. • Selects the counter clock from three internal clocks. ❍ Pulse-width measurement function • Measures the time between external pulse input events. • Selects the counter clock from three internal clocks. • Count mode • H pulse width (rising edge to falling edge)/L pulse width (falling edge to rising edge) • Rising edge period (rising edge to rising edge)/falling edge period (falling edge to falling edge) • Intermediate edge count (rising or falling edge to falling or rising edge) • Uses the 8-bit input divider to divide the input pulse by 22, 24, 26, and 28 to enable period measurement. • Generates an interrupt request at completion of count. • Selects single count or continuous count. The MB90580C series contains one PWC timer channel. ■ PWC Timer Operation This block is a multifunction timer that is based on the 16-bit up count timer and contains a count input pin and an 8-bit input divider. The block has two main functions, a timer function and a pulse-with measurement function, both of which enable the selection of two types of count clocks. 180 11.2 PWC Timer Block Diagram 11.2 PWC Timer Block Diagram Figure 11.2-1 "PWC Timer Block Diagram" is the PWC timer block diagram. ■ PWC Timer Block Diagram Figure 11.2-1 PWC Timer Block Diagram PWCR read Error detection ERR 16 PWCR Internal clock (machine clock/4) 16 Write enabled Reload Data transfer 16 Overflow Control bit output Flag setting Control circuit Start edge selection Count end edge End edge selection 2 Clock 16-bit up count timer Timer clear 2 F MC-16LX bus 16 2 Count enabled 15 PWCSR ERR 3 SW1 SW0 Divider ON/OFF Noise canceller CKS1 CKS0 8-bit divider Division rate selection 2 Clock divider CKS1, CKS0 Divider clear Edge detection Count start edge Count end interrupt request Overflow interrupt request 2 Overflow PWC EN F.F. POT DIVR 181 CHAPTER 11 PWC TIMER 11.3 PWC Timer Registers This section explains the PWC timer registers. ■ PWC Timer Registers ❍ PWC control status register (high-order byte) 15 Address:000055H Read/write Initial value 14 STRT STOP (R/W) (0) (R/W) (0) 13 12 11 10 9 8 EDIR EDIE OVIR OVIE ERR POUT (R) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R) (0) (R/W) (0) 2 1 0 Bit number PWCSR (HIGH) ❍ PWC control status register (low-order byte) 7 Address:000054H Read/write Initial value 6 5 4 CKS1 CKS0 Reserved Reserved (R/W) (0) (R/W) (0) (R/W) (R/W) (0) (0) 3 Bit number S/C MOD2 MOD1 MOD0 PWCSR (LOW) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) ❍ PWC data buffer register (high-order byte) 15 14 13 12 11 10 9 8 Address:000057H Read/write Initial value (R/W) (X) (R/W) (X) (R) (X) (R/W) (X) (R/W) (X) (R) (X) 3 2 (R/W) (R/W) (X) (X) Bit number PWCR (HIGH) ❍ PWC data buffer register (low-order byte) 7 6 5 4 1 0 Address:000056H Read/write Initial value 182 (R/W) (X) (R/W) (X) (R/W) (R/W) (X) (X) (R/W) (X) (R/W) (R/W) (R/W) (X) (X) (X) Bit number PWCR (LOW) 11.3 PWC Timer Registers ❍ Division rate control register 7 6 5 4 3 2 Address:000058H Read/write Initial value (-) (-) (-) (-) 1 0 DIV1 DIV0 (-) (-) (-) (-) (-) (-) (-) (-) 5 4 3 2 1 0 SW1 SW0 EN Bit number DIVR (R/W) (R/W) (0) (0) ❍ PWC noise filter register 7 6 Address:000086H Read/write Initial value (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) Bit number RNCR (R/W) (R/W) (R/W) (0) (0) (0) 183 CHAPTER 11 PWC TIMER 11.3.1 PWC control status register (PWCSR) The PWC control status register (PWCSR) controls the PWC timer operation and reads the PWC timer state. ■ PWC Control Status Register (PWCSR) Figure 11.3-1 "PWC Control Status Register (PWCSR)" shows the register configuration of the PWC control status register (PWCSR). Figure 11.3-1 PWC Control Status Register (PWCSR) 15 Address:000055H Read/write Initial value Address:000054H Read/write Initial value 14 STRT STOP 13 12 11 10 9 8 EDIR EDIE OVIR OVIE ERR POUT (R/W) (0) (R/W) (0) (R) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R) (0) (R/W) (0) 7 6 5 4 3 2 1 0 CKS1 CKS0 Reserved Reserved (R/W) (0) (R/W) (0) (R/W) (R/W) (0) (0) Bit number PWCSR (HIGH) Bit number S/C MOD2 MOD1 MOD0 PWCSR (LOW) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) [Bits 15 and 14] STRT (start) and STOP (stop) STRT (start) and STOP (stop) bits are used to start, restart, and stop the 16-bit up counte timer. When the bits are read, the timer operation status is returned. Table 11.3-1 "Operation Control Functions of STRT and STOP Bits (for write)" lists the functions of the bits to be written and Table 11.3-2 "Operation Status Indication of START and STOP Bits (for read)" lists the functions of the bits to be read. Table 11.3-1 Operation Control Functions of STRT and STOP Bits (for write) 184 STRT STOP Operation status indication 0 0 No function. The operation is not affected. 0 1 Starts or restarts the timer (enables count). Note: The clear bit instruction can be used. 1 0 Stops the timer operation (disables count). Note: The clear bit instruction cannot be used. 1 1 No function. The operation is not affected. 11.3 PWC Timer Registers Table 11.3-2 Operation Status Indication of STRT and STOP Bits (for read) STRT STOP Operation status indication 0 0 Timer stop (the timer is not started or count ends.) (Initial value) 1 1 Timer count operation in progress (counting) After reset, the bits are initialized to 00B. The bits can be read and written. Note that the meanings of bits depend on whether they are read or written. A read modify write instruction always reads the bits as 11B. When the STRT and STOP bits are written to start and stop the timer, a bit manipulation instruction (such as bit clear instruction) can be used. However, when the operation status (which always indicates that the timer is operating, for example) is read, a bit manipulation instruction cannot be used. [Bit 13] EDIR (EnD Interrupt Request) The EDIR flag indicates that measurement terminated in pulse-width measurement mode. When this bit is set to enable an interrupt (bit 12: EDIE = "1"), a measurement termination interrupt request is issued. Cause of setting When pulse-width measurement terminates, the bit is set (PWCR contains the measurement result). Cause of clear Reading PWCR (measurement result) clears the bit. Note: In timer mode, this bit is meaningless. After reset, the bit is initialized to 0. The bit is read only. Writing this bit is meaningless. [Bit 12] EDIE (EnD Interrupt Enable) This bit is used to control a measurement termination interrupt request in pulse-width count mode as follows: 0 Disables output of a measurement termination interrupt request (when EDIR is set, the interrupt is not generated) (initial value). 1 Enables output of a measurement termination interrupt request (when EDIR is set, the interrupt is generated). Note: Always set 0 in timer mode. After reset, the bit is initialized to 0. The bit can be read and written. 185 CHAPTER 11 PWC TIMER [Bit 11] OVIR (Overflow Interrupt Request) This bit is used to specify when the 16-bit up count timer overflows in the range from FFFFH to 0000H. The operation affects all modes. When this bit is set to enable the interrupt (bit 10: OVIE = "1"), a timer overflow interrupt request is generated. Cause of setting When a timer overflow occurs (FFFFH to 0000H), the bit is set. Cause of clear Writing 0 or extended intelligent I/O service clears the bit. After reset, the bit is initialized to 0. The bit can be read and written. However, only writing 0 is valid. Writing 1 is meaningless. A read modify write instruction always reads this bit as 1. Note: In H/L pulse-width count mode, do not use this bit for pulse-width time measurement. [Bit 10] OVIE (OVerflow Interrupt Enable) OVIE is the timer overflow interrupt request control bit. This bit is used to control a timer overflow interrupt request as listed in Table 11.3-3 "OVIE (timer overflow interrupt request control bit)". After reset, the bit is initialized to 0. The bit can be read and written. Table 11.3-3 OVIE (timer overflow interrupt request control bit) OVIE Function 0 Disables output of an overflow interrupt request (when OVIR is set, the interrupt is not generated) (initial value). 1 Enables output of an overflow interrupt request (when OVIR is set, the interrupt is generated). Note: In the H/L pulse-width count mode, set this bit to 0. [Bit 9] ERR (ERRor) The ERR flag is used to execute a continuous count in the pulse-width count mode. This flag indicates that the next count has been completed before the previous count result is read from PWCR. If this state occurs, PWCR is overwritten by new count result and the previous result is lost. The count operation continues regardless of the value of this bit. After reset, the bit is initialized to 0. The bit is read only. Writing to this bit does not change the value. Table 11.3-4 ERR (ERRor) 186 Cause of setting When the count result that has not been read is overwritten by the next result, the bit is set. Cause of clear Reading PWCR (measurement result) clears the bit. 11.3 PWC Timer Registers [Bit 8] POUT (Pulse OUTput) Each time the 16-bit up count timer overflows in the range from FFFFH to 0000H in timer mode, this bit is reversed. In the pulse-width count mode, this bit is meaningless. After reset, the bit is initialized to 0. The bit can be read and written. However, the bit can be written only if the timer stops (both bit 15: STRT and bit 14: STOP are set to 0). If the bit is written during timer operation (both bit 15: STRT and bit 14: STOP are set to 1), the bit value remains unchanged. Table 11.3-5 POUT (Pulse OUTput) Cause of setting When the POUT value is 0 and the timer overflows in the range from FFFFH to 0000H or the timer stops and 1 is written, the bit is set. Cause of clear When the POUT value is 1 and the timer overflows in the range from FFFFH to 0000H or the timer stops and 0 is written, the bit is cleared. The bit is also cleared by reset. [Bits 7 and 6] CKS1 and CKS0 (Clock Select 1 and 0) CKS1 and CKS0 bits are used to select the internal count clock. These bits are used to select the internal count clock as listed in Table 11.3-6 "CKS1 and CKS0 (internal count clock selection bits)". After reset, the bits are initialized to 00B. The bits can be read and written. However, 11B cannot be set. Table 11.3-6 CKS1 and CKS0 (internal count clock selection bits) CKS1 CKS0 Count clock selection 0 0 Machine clock divide by 4 (0.25 μs for machine cycle at 16 MHz) (initial value) 0 1 Machine clock divide by 16 (1.0 μs for machine cycle at 16 MHz) 1 0 Machine clock divide by 32 (2.0 μs for machine cycle at 16 MHz) 1 1 Setting prohibited (undefined) Note: After the timer is started, changing the setting is prohibited. Write these bits before the timer is started or after the timer is stopped. [Bits 5 and 4] Reserved bits (reserved) Bits 5 and 4 are reserved. Always write 00B. 187 CHAPTER 11 PWC TIMER [Bit 3] S/C (Single/Continuous) The S/C bit is used to select the count mode. The count mode is selected as listed in Table 11.3-7 "S/C (count mode selection bit)". After reset, the bit is initialized to 0. The bit can be read and written. Table 11.3-7 S/C (count mode selection bit) S/C Count mode selection Timer mode Pulse-width count mode 0 Single measurement mode (initial value) No reload (one shot) Stop after one measurement 1 Continuous measurement mode Reload (reload timer) Buffer register is valid Continuous measurement: Buffer register is valid Note: After the timer is started, changing the setting is prohibited. Write this bit before the timer is started or after the timer is stopped. [Bits 2, 1, and 0] MOD2, MOD1, and MOD0 (MOD2, 1, and 0) Setting these bits enables selection of the operating mode and the pulse edge that fits the pulse-width count as listed in Table 11.3-8 "MOD2, MOD1, and MOD0 (operation mode/count edge selection bits)". After reset, these bits are initialized to 000B. These bits can be read and written. Table 11.3-8 MOD2, MOD1, and MOD0 (operation mode/count edge selection bits) 188 MOD2 MOD1 MOD0 Operation mode/count edge selection 0 0 0 Timer mode and no pulse output (initial value) 0 0 1 Timer mode and pulse output (POT pin valid): Reload mode only 0 1 0 All edge-to-edge pulse-width measurement mode (rising edge or falling edge to falling edge or rising edge)* 0 1 1 Division period measurement mode (when the input divider is used)* 1 0 0 Rising edge-to-rising edge period measurement mode (rising edge to rising edge)* 1 0 1 H pulse-width measurement mode (rising edge to falling edge)* 1 1 0 L pulse-width measurement mode (falling edge to rising edge)* 1 1 1 Falling edge-to-falling edge period measurement mode (falling edge to falling edge)* 11.3 PWC Timer Registers Note: After the timer is started, changing the setting is prohibited. Write these bits before the timer is started or after the timer is stopped. If the continuous measurement mode is set for the setting marked *, the number of edges are totaled and the divider for the internal count clock is not cleared at the end of count. In all other modes, the divider for the internal count clock is cleared at the end of the count. 189 CHAPTER 11 PWC TIMER 11.3.2 PWC data buffer register (PWCR) The PWC data buffer register (PWCR) has functions that depend on the operation mode of the PWC timer. ■ PWC Data Buffer Register (PWCR) Figure 11.3-2 "PWC Data Buffer Register (PWCR)" shows the register configuration of the PWC data buffer register (PWCR). Figure 11.3-2 PWC Data Buffer Register (PWCR) 15 14 13 12 11 10 9 8 Address:000057H Read/write Initial value (R/W) (X) (R/W) (X) 7 6 (R/W) (R/W) (X) (X) 5 (R/W) (X) 4 3 (R/W) (R/W) (R/W) (X) (X) (X) 2 1 0 Address:000056H Read/write Initial value (R/W) (X) (R/W) (X) (R/W) (R/W) (X) (X) (R/W) (X) (R/W) (R/W) (R/W) (X) (X) (X) Bit number PWCR (HIGH) Bit number PWCR (LOW) ❍ Timer mode In the reload timer operation mode (PWCSR [bit 3] S/C = 1), this register contains the reload value. The register can be read and written. In the single timer operation mode (PWCSR [bit 3] S/C = 0), direct access to this register accesses the up count timer. In this mode, this register can be both read and written. However, the register is written only when the timer stops. The register can always be read and the current timer value is read. ❍ Pulse-width measurement mode (read only) In the continuous measurement mode (PWCSR [bit 3] S/C = 1), this register functions as the buffer register and contains the previous count result. This register is read only, and the register value remains unchanged when written. In the single measurement mode (PWCSR [bit 3] S/C = 0), direct access to this register accesses the up count timer. In this mode, the register is also read only and the register value remains unchanged when written. The register can always be read and the current timer value is read. After the count, the register contains the count results. Note: To access this register, always use the word transfer instruction. After reset, this register is initialized to 0000H. 190 11.3 PWC Timer Registers 11.3.3 Division rate control register (DIVR) The division rate control register (DIVR) is used in the division period measurement mode (PWCSR [bits 2, 1, and 0] MOD2, 1, and 0 = 011). This register has no meaning in other modes. ■ Division Rate Control Register (DIVR) Figure 11.3-3 "Division Rate Control Register (DIVR)" shows the register configuration of the division rate control register (DIVR). Figure 11.3-3 Division Rate Control Register (DIVR) 7 6 5 4 3 2 Address:000058H Read/write Initial value (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) 1 0 DIV1 DIV0 Bit number DIVR (R/W) (R/W) (0) (0) [Bits 1 and 0] DIV1 and DIV0 In the division range measurement mode, this register is used to divide the pulse input from the measurement pin and measure the one-period width after division. The division rate is selected as listed in Table 11.3-9 "Division Rate Selection by DIV1 And DIV0 Bits". After reset, these bits are initialized to 00B. These bits can be read and written. Table 11.3-9 Division Rate Selection by DIV1 And DIV0 Bits DIV1 DIV0 Division rate selection 0 0 22 = divide by 4 (initial value) 0 1 24 = divide by 16 1 0 26 = divide by 64 1 1 28 = divide by 256 Note: After the timer starts, the setting cannot be changed. Write these bits before the timer has started or after the timer has stopped. 191 CHAPTER 11 PWC TIMER 11.3.4 PWC noise filter register (RNCR) The PWC noise filter register (RNCR) uses the PWC noise reduction circuit to reduce noise from the input signal. The high-level and low-level are detected after passing through the noise filter. ■ PWC Noise Filter Register (RNCR) Figure 11.3-4 "PWC Noise Filter Register (RNCR)" shows the register configuration of the PWC noise filter register (RNCR). Figure 11.3-4 PWC Noise Filter Register (RNCR) 7 6 5 4 3 Address:000086H Read/write Initial value (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) 2 1 0 SW1 SW0 EN Bit number RNCR (R/W) (R/W) (R/W) (0) (0) (0) The noise reduction circuit is the digital low-pass filter that is used to reduce the high-frequency component of the input signal. The PWC noise reduction circuit can be used to reduce the noise pulse width specified by the SW bits of the PWC noise filter register. This PWC noise filter register is an 8-bit register and all bits are initialized to 0 at reset. [Bits 2 and 1] SW1 and SW0 SW1 and SW0 are clock mode selection bits that specify the noise pulse width to be reduced. Table 11.3-10 "SW1 and SW0 (clock mode selection bits)" lists the timing when the main clock is 16 MHz. Table 11.3-10 SW1 and SW0 (clock mode selection bits) SW1 SW0 0 0 28/main clock* (16.0μs if the main clock* is 16 MHz) 0 1 212/main clock* (256.0μs if the main clock* is 16 MHz) 1 0 213/main clock* (512.0μs if the main clock* is 16 MHz) 1 1 214/main clock* (1.024ms if the main clock* is 16 MHz) * : OSC oscillation 192 Noise pulse width (Minimum) 11.3 PWC Timer Registers [Bit 0] EN Using the EN bit enables this noise filter function. Table 11.3-11 En Bit Functions EN Function 0 Disables the noise filter function (initial value). 1 Enables the noise filter function. 193 CHAPTER 11 PWC TIMER 11.4 PWC Timer Operations The PWC timer is the multifunction timer based on the 16-bit up count timer and contains the count input pin and 8-bit input divider. The block has two main functions: Timer function and pulse-width count function. Both the timer function and the pulsewidth count function enable the selection of two types of count clocks. ■ Timer Function The timer function is the up count timer that enables selection of the operation in single mode or reload mode. When the timer is started, a timer count is performed at each count clock. When an overflow occurs in the range from FFFFH to 0000H, an interrupt request is issued. If an overflow occurs, the following occurs: - Single mode: Count is discontinued (see Figure 11.4-1 "Timer Operation (single mode)"). - Reload mode: The reload register contents are reloaded to the timer and the count is restarted (see Figure 11.4-2 "Timer Operation (reload mode)"). Figure 11.4-1 Timer Operation (single mode) Timer count value (The solid line indicates the timer count value.) Overflow Overflow FFFFH (Restart is invalid.) Write to PWCR 0000H Timer start OVIR flag setting, Timer stop Timer start OVIR flag setting, Timer stop Time Figure 11.4-2 Timer Operation (reload mode) Timer count value (The solid line indicates the timer count value.) Overflow Overflow Overflow Overflow Overflow FFFFH PWCR write value Reload Reload Reload Reload 0000H OVIR flag setting Reload Reload Write to PWCR Timer start Restart Reload Timer stop POUT bit If the timer is started at L level, the level is not toggled when the timer is restarted (except at the same time as an overflow). 194 Time 11.4 PWC Timer Operations ■ Pulse-width Measurement Function The pulse-width measurement function calculates the time between the specified events related to the input pulse. When this function is activated, a count is started after the specified count start edge is input. If the counter is cleared to 0000H, a count is started when the start edge is detected, then the stop edge is detected. The count value during this period is held in the register as the pulse width. When the measurement terminates or an overflow occurs, an interrupt request can be generated. When the measurement is completed, the following occurs: ❍ Single measurement mode The operation is discontinued (see Figure 11.4-3 "Pulse-width Measurement Operation (single measurement mode, H width measurement mode)"). ❍ Continuous measurement mode The timer value is transferred to the buffer register and the timer is in free-run state until the next edge is input (see Figure 11.4-4 "Pulse-width Measurement Operation (continuous measurement mode, H-width measurement mode)"). Figure 11.4-3 Pulse-width Measurement Operation (single measurement mode, H width measurement mode) (The solid line indicates the timer count value.) PWC input Measured pulse Timer count value FFFFH Timer clear 0000H Start of measurement Timer start Timer stop Time EDIR flag setting (termination of measurement) 195 CHAPTER 11 PWC TIMER Figure 11.4-4 Pulse-width Measurement Operation (continuous measurement mode, H-width measurement mode) The solid line indicates the timer count value.) PWC input Measured pulse Timer count value Overflow FFFFH Data transfer to PWCR Timer clear 0000H Data transfer to PWCR Timer clear Start of measurement Timer start OVIR flag setting Timer start OVIR flag setting Time * EDIR flag setting (termination of measurement) EDIR flag setting *: The timer value during this period is not guaranteed (a timer overflow may result in OVIR being set). 196 11.4 PWC Timer Operations 11.4.1 Count clock selection The timer count clock can be selected from the following three internal clock sources: • Machine cycle/4 • Machine cycle/16 • Machine cycle/32 ■ Count Clock Selection Table 11.4-1 "Count Clock Selection" lists the available clock sources. Table 11.4-1 Count Clock Selection PWCSR/bit7, bit 6: CKS1, 0 Internal count clock selection 00B Machine cycle/4 (0.25 μs when machine cycle = 16 MHz) (inisial value) 01B Machine cycle/16 (1.0 μs when machine cycle = 16 MHz) 10B Machine cycle/32 (2.0 μs when machine cycle = 16 MHz) After the bits are set, machine cycle/4 is selected. Note: Before the timer is started, always select the count clock. 197 CHAPTER 11 PWC TIMER 11.4.2 Operation mode selection Operation modes and count modes are selected according to the setting of PWCSR. ■ Operation Mode Selection The following registers are used to set the selection of operation modes and count modes: ❍ Operation mode setting: PWCSR [bits 2, 1, and 0] MOD2, MOD1, and MOD0 bits Select the timer mode or pulse-width measurement mode to specify control of the count operation. ❍ Count mode setting: PWCSR [bit 3] S/C bit Select single measurement or continuous measurement or reload operation or one-shot operation. Table 11.4-2 "Operation Mode Selection" lists the operation modes selected using the mode setting bits. Table 11.4-2 Operation Mode Selection Operation mode Timer Pulse-width measurement 198 S/C MOD2 MOD1 MOD0 One-shot timer 0 0 0 0 Reload timer 1 0 0 0 Setting prohibited 1 0 0 1 Rising edge or falling edge to rising edge to falling edge All edge-to-edge measurement Single measurement: Buffer invalid 0 0 1 0 Continuous measurement: Buffer valid 1 0 1 0 Division count Divide by 1 to 256 Single measurement: Buffer invalid 0 0 1 1 Continuous measurement: Buffer valid 1 0 1 1 Rising edge to falling edge Rising edge-to-rising edge period measurement Single measurement: Buffer invalid 0 1 0 0 Continuous measurement: Buffer valid 1 1 0 0 Rising edge to falling edge H pulse-width measurement Single measurement: Buffer invalid 0 1 0 1 Continuous measurement: Buffer valid 1 1 0 1 11.4 PWC Timer Operations Table 11.4-2 Operation Mode Selection (Continued) Operation mode Pulse-width measurement S/C MOD2 MOD1 MOD0 Rising edge to falling edge L pulse-width measurement Single measurement: Buffer invalid 0 1 1 0 Continuous measurement: Buffer valid 1 1 1 0 Rising edge to falling edge Falling edge-to-falling edge period measurement Single measurement: Buffer invalid 0 1 1 1 Continuous measurement: Buffer valid 1 1 1 1 After reset, the one-shot timer is selected as an initial value. Note: Before the timer starts, always select the operation mode. 199 CHAPTER 11 PWC TIMER 11.4.3 Starting and stopping the timer and pulse-width measurement and clearing the timer To start, restart, and forcibly stop the timer and pulse-width measurement, use the PWCSR bits 15 and 14 (STRT and STOP). The 16-bit up count timer is cleared to 0000H at reset and when the measurement start edge is detected and the count is started in the pulse-width measurement mode. ■ Starting and Stopping Timer and Pulse-width Measurement Writing 0 to the STRT bit starts or restarts the operation, and writing 0 to the STOP bit stops the operation. However, unless the value written to the two bits is different, none of the bits executes operations. If an instruction (byte or word instruction) other than the bit manipulation instruction is being used, a value is written to the following bit combinations only. Table 11.4-3 Functions of Start and Stop Bits Function STRT STOP Starts and restarts the timer or pulse-width measurement 0 1 Stops the timer or pulse-width measurement 1 0 If a bit manipulation instruction (clear bit instruction) is being used, the hardware automatically writes the above combination of values. The user need not know which value is to be written. ❍ Operation after start • Timer mode: The count operation is started immediately. • Pulse-width measurement mode: Measurement is started after the measurement start edge is input. After the measurement start edge is detected, the 16-bit up count timer is cleared to 0000H and the count is started. ❍ Restarting the timer While the timer operation continues after the timer is started in the timer mode or pulse-width measurement mode, starting the start (writing 0 to the STRT bit) is called timer restart. The operations to be executed during restart are dependent on the following modes: 200 • One-shot mode: The operation is not affected. • Reload timer mode: Reload is executed and the operation is continued. If the timer is restarted when an overflow occurs, the overflow flag (OVIR) is set and the POUT bit is reversed. • Pulse-width measurement mode: In the measurement start edge wait state, the operation is not affected. During measurement, the count stops and the timer state returns to the "measurement start edge wait" state. When the timer is restarted on termination of measurement, the measurement termination flag (EDIR) is set and the measurement results are transferred to PWCR in continuous measurement mode. 11.4 PWC Timer Operations ❍ Stopping the timer In one-shot timer mode or single measurement mode, measurement is automatically discontinued when the timer overflows or at the end of a count. The user need not know if the timer has stopped. However, in other modes, the timer must be stopped. ❍ Checking operation state The previously described STRT and STOP bits function as bits that indicate the operation state of the timer during a read operation. Table 11.4-4 "Functions of Operation State Indication Bits" lists the contents of the indicated values. Table 11.4-4 Functions of Operation State Indication Bits STRT STOP Operation state 0 0 Timer is stopping (except measurement start edge wait state). The bits indicate that the timer has not started or a measurement has terminated. 1 1 Measurement start edge wait state or timer count operation During a read operation, both the STRT bit and the STOP bit have the same value. However, during a read operation using the read modify write instruction (such as bit manipulation instruction), the values of the bits are always 11B. Do not use this instruction to read the values of the bits. ■ Clearing the Timer In the following cases, the 16-bit up count timer is cleared to 0000H. • During reset • When a count has started after the count start edge is detected in the pulse-width measurement mode 201 CHAPTER 11 PWC TIMER 11.5 Details of Timer Mode Operation The timer mode includes the one-shot operation mode and reload operation mode. ■ One-shot Operation Mode When the timer is started in this mode, a count is incremented at each count clock. The timer automatically stops when an overflow occurs from FFFFH to 0000H. If PWCR is set before the timer has started, the count is started from this set value. After overflow, the set value is deleted and the current count value remains in PWCR. Although bit 8 (POUT) of PWCSR is inverted when an overflow occurs, its value is not output from the pin in this mode. This is also true when pulse output mode is specified. ■ Reload Operation Mode When the timer is started in this mode, the reload value in PWCR is set in the timer and the count is incremented at each count clock. If an overflow occurs when the timer counts FFFFH to 0000H, the reload value in PWCR is set in the timer again, the POUT bit (bit 8) of PWCSR is reversed, and the count operation is repeated. The timer does not stop until a value is written to the STOP bit of PWCSR to stop the timer or it is reset. The reload value set in PWCR before the timer is started is stored during a count. When the timer is started or restarted and an overflow occurs, the reload value is always set in the timer. If the value that is set during a count is to be changed, a new reload value becomes valid when the next overflow occurs or the timer is restarted. ■ Timer Value and Reload Value In one-shot operation mode, direct access to PWCR accesses the up-count timer. When a value is written to PWCR, the value is written directly to the timer. When PWCR is read during a count operation, the current timer value is read. If the value is set in PWCR before the timer is started, the timer starts a count from the specified value. In reload operation mode, the up- count timer cannot be accessed and PWCR functions as a reload register (stores the reload value). When the timer is started or restarted and an overflow occurs, the value written to PWCR is always set in the timer. When PWCR is read, the stored reload value is read. The PWCR value and timer value are undefined if the timer is set in one-shot mode after the operation is discontinued in reload mode. Therefore, always set the values before the timer is used. The PWCR value is undefined if the timer is set in reload mode after the operation is forcibly discontinued in one-shot mode. Therefore, always set the value before the timer is used. ■ Interrupt Request Generation During operation in timer mode, an overflow enables the generation of an interrupt request. If the increment of a timer count causes an overflow, the overflow flag is set, an overflow interrupt request is enabled, and an interrupt request is generated. 202 11.5 Details of Timer Mode Operation ■ Timer Period If the timer is started in one-shot mode after 0000H is set in PWCR, a timer overflow occurs and the count is discontinued if the count exceeds 65536. The following formula is used to calculate the time from start to stop of the timer. T1= (65536-n1) t T1 ..... Time n1 ..... Timer t from start to stop ( s) ....... Count value set in PWCR when the timer is started clock period ( s) If the timer is started after 0000H is set in PWCR, a timer overflow occurs every time the count exceeds 65536. The following formula is used to calculate the reload period and the POT pin output pulse period. TR TR= (65536-nR) t TPOUT=TR 2 ........... TPOUT nR t ..... ........... .............. Reload period (overflow period) ( s) POT pin output pulse period ( s) Reload value stored in PWCR Count clock period ( s) ■ Count clock and Maximum Period In timer mode, when 0000H is set in PWCR, the maximum period results. Table 11.5-1 "Count Clock and Period" lists the count clock period and maximum timer period corresponding to the machine cycle (indicated by φ in the table) at 16 MHz. Table 11.5-1 Count Clock and Period Count clock selection Count clock period Maximum timer period When CKS1, 0=00B(φ/4) When CKS1, 0=01B(φ/16) When CKS1, 0=10B(φ/32) 0.25 μs 1 μs 2 μs 16.38 ms 65.5 ms 131.1 ms 203 CHAPTER 11 PWC TIMER 11.6 Flowchart of Timer Mode Operation Figure 11.6-1 "Flowchart of Timer Mode Operation" is the flowchart of timer mode operation. ■ Flowchart of Timer Mode Operation Figure 11.6-1 Flowchart of Timer Mode Operation Setting - Select count clock - Select operation mode and timer mode - Clear interrupt flag - Enable interrupt - Set pulse output initial value Set value in PWCR Restart Reload operation mode Start by STRT bit Single operation mode Reload PWCR value to timer Start count Addition Overflow occurs Set OVIR flag Reverse POUT bit value Start count Addition Overflow occurs Set OVIR flag Reverse POUT bit value Discontinue count Discontinue operation 204 11.7 Details of Pulse Width Measurement Mode Operation 11.7 Details of Pulse Width Measurement Mode Operation The signal for pulse-width measurement is input from the PWC pin. The pulse-width measurement mode includes the single measurement mode in which the count is performed only once and continuous measurement mode in which the pulse width is continuously measured. ■ Single Measurement Mode and Continuous Measurement Mode The differences between the single measurement mode and continuous measurement mode are as follows: ❍ Single Measurement Mode When the first count end edge is input, the timer discontinues the count, the count end flag (EDIR) of PWCSR is set, and the subsequent measurement is not performed. However, if a timer restart is also specified, the timer state changes to measurement start edge wait state. ❍ Continuous Measurement Mode [H/L pulse-width measurement mode] When the count end edge is input, the count end flag (EDIR) of PWCSR is set, the timer count result is transferred to PWCR, and the timer may continue incrementing the count in a free-run state. When the next count start edge is input, the timer is cleared to 0000H and the pulse-width count is started. Note: When the count end edge is input and the timer enters a free-run state, the timer may overflow and the OVIR flag may be set. In the H/L pulse-width measurement mode, do not use the OVIR flag to measure the pulse-width time. [All edge-to-edge pulse-width measurement mode, division period measurement mode, rising edge-to-rising edge measurement mode, and falling edge-to-falling edge measurement mode] When the count end edge (count start edge) is input, the count end flag (EDIR) of PWCSR is set, the timer count result is transferred to PWCR, the timer is cleared to 0000H, and the count is restarted. ■ Measurement Result Data Handling of the measurement result, timer value, and PWCR function varies with the single measurement mode and continuous measurement mode as follows: ❍ Single measurement mode When PWCR is read during timer operation, the current timer value is read. When PWCR is read after termination of measurement, the measurement results are read. 205 CHAPTER 11 PWC TIMER ❍ Continuous measurement mode At termination of measurement, the timer measurement results are transferred to PWCR. When PWCR is read, the previous measurement results are read. While measurement is in progress, the previous measurement results are stored in PWCR. During measurement, the timer value cannot be read. In continuous measurement mode, unless the previous measurement results are read before completion of the next measurement, a new measurement result overwrites the existing value. The error flag (ERR) of PWCSR is set. When PWCR is read, the error flag (ERR) is cleared automatically. ■ Minimum Input Pulse Width The pulse must be input to the pulse-width count input pin (PWC) longer than the following minimum input pulse width. Pulse width: 2 machine cycles (0.125 μs or more for the machine clock at 16 MHz) However, the input pulse that is shorter than the above specification may also be recognized as a valid pulse. ■ Calculating Pulse Width/period The pulse width or pulse period of the measurement object is calculated based on the count result read from PWCR at the end of a count as follows. TW TW=n x t / DIV( s) Measured pulse width or pulse period ( s) n Measurement result contained in PWC t ............. Count clock period ( s) DIV 206 ......... ............ ....... Division rate set in the division rate register (DIVR) (a value of 1 is used in a mode other than the division count mode.) 11.7 Details of Pulse Width Measurement Mode Operation ■ Pulse Width/period Measurement Range The range of the pulse width/period that can be measured depends on the count clock and division rate of an input divider. Table 11.7-1 "Pulse Width Measurement Range" lists the measurement range for the machine cycle (indicated by φ) at 16 MHz. Table 11.7-1 Pulse Width Measurement Range Division rate DIV1, 0 CKS1, 0=00B (φ/4) No division - 0.125 μs to 16.38 ms [0.25 μs] 0.125 μs to 65.5 ms [1.0 μs] 0.125 μs to 131 ms [2.0 μs] Divide-by 4 00B 0.125 μs to 4.10 ms [62.5 ns] 0.125 μs to 16.38 ms [0.25 μs] 0.125 μs to 32.75 ms [500 ns] Divide-by 16 01B 0.125 μs to 1024 μs [15.6 ns] 0.125 μs to 4.10 ms [62.5 ns] 0.125 μs to 8.19 ms [125 ns] Divide-by 64 10B 0.125 μs to 256 μs [3.91 ns] 0.125 μs to 1024 μs [15.6 ns] 0.125 μs to 2.048 ms [31.25 ns] Divide-by 256 11B 0.125 μs to 64 μs [0.98 ns] 0.125 μs to 256 μs [3.91 ns] 0.125 μs to 512 ms [7.81 ns] CKS1, 0=01B (φ/16) CKS1, 0=10B (φ/32) Note: The number in [ ] indicates the resolution per bit. ■ Interrupt Request Generation In the pulse-width measurement mode, the following two interrupt requests can be generated: ❍ Timer overflow interrupt request If an overflow occurs during a count, the overflow flag is set. When the overflow interrupt request is enabled, an interrupt request is generated. ❍ Measurement termination interrupt request When the measurement termination edge is detected, the count end flag (EDIR) of PWCSR is set. If the measurement termination interrupt is enabled, an interrupt request is generated. The measurement termination flag (EDIR) is automatically cleared when PWCR is read. 207 CHAPTER 11 PWC TIMER 11.7.1 Measurement mode and measurement operation The measurement mode can be selected from five different modes. This mode is used to determine the component of the input pulse to be measured. The mode can be used to divide the input pulse at the specified division rate and measure the resulting period to accurately measure the width of a high-frequency pulse. ■ Measurement Mode and Measurement Operation Table 11.7-2 "Measurement Mode Operation" lists measurement mode operations. Table 11.7-2 Measurement Mode Operation Measurement mode H-pulse-width measurement MOD2 MOD1 MOD0 1 0 1 Measurement operation W W Termination of Start of measurement measurement Start Termination of measurement The H-period width is measured. Start of measurement: Termination of measurement: L pulse-width measurement 1 1 When the rising edge is detected When the falling edge is detected 0 W W Termination of Start of measurement measurement Start Termination of measurement The L period width is measured. Start of measurement: Termination of measurement: Rising edge-torising edge period measurement 1 0 When the falling edge is detected When the rising edge is detected 0 W Start of measurement W Termination of measurement Start W Termination Start Termination The rising edge-to-rising edge time is measured. Start of measurement: 208 When the rising edge is detected 11.7 Details of Pulse Width Measurement Mode Operation Table 11.7-2 Measurement Mode Operation (Continued) Measurement mode MOD2 MOD1 MOD0 Falling edge-tofalling edge period measurement 1 1 1 Measurement operation W Start of measurement W Termination of measurement Start W Termination Start Termination The falling edge-to-falling edge time is measured. Start of measurement: Termination of measurement: All edge pulsewidth measurement 0 1 When the falling edge is detected When the falling edge is detected 0 W Start of measurement W Termination of measurement Start W Termination Start Termination The width between continuous input edges is measured. Start of measurement: Termination of measurement: Division measurement 0 1 When the edge is detected When the edge is detected 1 W Start of measurement W Termination of measurement Start W Termination (Divided by 4 in the above example.) The input pulse is divided by the division rate set in the division rate register (DIVR), and the measurement period is obtained as a result. Start of measurement: Termination of measurement: The falling edge is detected after the operation is started. One period of division signal ends. W: Pulse width being measured In all modes, the timer does not start count during the period from the start of measurement to input of measurement start edge. After the measurement start edge is input, the timer is cleared to 0000H, and the count is incremented at each count clock until the measurement termination edge is input. 209 CHAPTER 11 PWC TIMER When the measurement termination edge is input, the following operations are executed: 1. The count end flag (EDIR) of PWCSR is set. 2. The timer stops count operation (except if the timer is restarted at the same time or continuous measurement mode of the H/L pulse-width measurement is used). 3. Continuous measurement mode: The timer value (measurement result) is transferred to PWCR. 4. Single measurement mode: Measurement is terminated (except if the timer is restarted at the same time). If all edge-to-edge pulse-width measurement, period measurement, falling edge-to-falling edge period measurement, or rising edge-to-edge period measurement is done in continuous measurement mode, the termination edge becomes the next measurement start edge. 210 11.7 Details of Pulse Width Measurement Mode Operation 11.7.2 Flowchart of pulse-width measurement operation Figure 11.7-1 "Flowchart of Pulse-width Measurement Mode Operation" is the flowchart of pulse-width measurement mode operation. ■ Flowchart of Pulse-width Measurement Operation Figure 11.7-1 Flowchart of Pulse-width Measurement Mode Operation Setting - Select count clock - Select operation mode and measurement mode - Clear interrupt flag - Enable interrupt - Set pulse output initial value Restart Start by STRT bit Continuous measurement mode Single measurement mode Detect count start edge Detect count start edge Clear timer Clear timer Start Count Start Count Addition Addition Overflow occurs Set OVIR flag Overflow occurs Set OVIR flag Detect count end edge Set EDIR flag Detect count end edge Set EDIR flag Discontinue count* Discontinue count Transfer timer value to PWCR Discontinue operation *: Except continuous measurement mode of H/L pulse-width measurement 211 CHAPTER 11 PWC TIMER 11.8 Notes on Handling the PWC Timer Note the following contents for handling the PWC timer: • Register value change • Measurement termination flag in timer mode • STRT and STOP bits of PWCSR • Timer clear • Clock selection bits • PWCR and timer values when mode is changed • Minimum input pulse width • Division period measurement mode • Restart during operation • Pulse-width measurement mode using continuous measurement mode ■ Register Value Change Changing the following PWCSR bit values is prohibited during timer operation. The bit values are changed only before the timer is started or after the operation is discontinued. [Bits 7 and 6] CKS1 and CKS0: Clock selection bits [Bit 3] S/C: Measurement mode (single or continuous) selection bit [Bits 2, 1, and 0] MOD2, MOD1, and MOD0: Operation mode and measurement edge selection bits Note that the value of pulse output level indication bit (POUT: bit 8) remains unchanged even if the bit is written during timer operation. Changing the DIVR value is prohibited during timer operation. Change the DIVR value before the timer is started or after the operation has stopped. ■ Measurement Termination Flag in Timer Mode In timer mode, the value of the measurement termination interrupt request flag (EDIR) of PWCSR is insignificant. Therefore, always set 0 in the count end interrupt request (EDIE) enable bit of PWCSR. ■ STRT and STOP Bits of PWCSR Note that these two bits are dependent on whether they are read or written (see the details of registers). Note that a read modify write instruction always reads the bits as 11B. A bit manipulation instruction cannot be used to read the operation state. However, a bit manipulation instruction (bit clear instruction) can be used to start or stop the timer by writing the STRT or STOP bit. 212 11.8 Notes on Handling the PWC Timer ■ Timer Clear In the pulse-width measurement mode, the measurement start edge causes the timer to be cleared, and the previous timer data is insignificant. ■ Clock Selection Bits Setting 11B in clock selection bits (bits 7 and 6: CKS1 and CKS0) of PWCSR is prohibited. ■ PWCR and Timer Values when the Mode is Changed The PWCR and timer values are determined when the timer is set in the one-shot mode after the operation is terminated in reload timer mode. Therefore, always set the values after the timer is used. The PWCR value is undefined if the timer is set in reload timer mode after the operation is discontinued in the one-shot mode. Therefore, always set the value before the timer is used. To change the mode from pulse-width measurement mode to timer mode, always set the value in PWCR before the timer has started. ■ Minimum Input Pulse Width Pulse input to the pulse width measurement input pin is controlled as follows: ❍ Minimum pulse width Divide-by 2 of machine cycle (0.125 μs or more for the machine cycle at 16 MHz) ❍ Maximum input frequency Divide-by 4 of machine cycle (4 MHz or less for the machine cycle at 16 MHz) If a pulse width smaller than the above or a frequency larger than the above is input, the timer operation is not guaranteed. A noise violating the above constraint and appearing in the input signal must be reduced. ■ Division Period Measurement Mode When division period measurement mode is used in pulse-width measurement mode, the input pulse is divided. Note that the pulse width calculated from the count result becomes a mean. ■ Restart During Operation If the timer is restarted after the count operation starts, the following operation may occur according to the timing: ❍ If the timer is restarted when an overflow occurs in reload timer mode The timer is restarted but the overflow flag (OVIR) is set and the POUT bit is reversed (that is, the same operation as the normal overflow is executed). ❍ If the timer is restarted when the measurement termination edge is detected in one-shot pulse-width measurement mode The timer is restarted and enters measurement start edge wait state but the measurement termination flag (EDIR) is also set. 213 CHAPTER 11 PWC TIMER ❍ If the timer is restarted when the measurement termination edge is detected in continuous pulse-width measurement mode The timer is restarted and enters the measurement start edge wait state, the count termination flag (EDIR) is set, and the measurement results are transferred to PWCR. To restart the timer during operation, note the above flag operations to generate interrupts and exercise other controls. ■ Pulse-width Measurement Mode Using Continuous Measurement Mode During continuous measurement in this mode, the division circuit for an internal count clock is not cleared, and the number of edges smaller than the count clock is added to the count result. 214 CHAPTER 12 16-BIT I/O TIMER This chapter describes the functions and operations of the 16-bit I/O timer. 12.1 "Overview of the 16-Bit I/O Timer" 12.2 "16-Bit I/O Timer Block Diagram" 12.3 "16-Bit I/O Timer Registers" 12.4 "16-Bit Free-Run Timer Operations" 12.5 "16-Bit Output Compare Operations" 12.6 "16-Bit Input Capture Operations" 215 CHAPTER 12 16-BIT I/O TIMER 12.1 Overview of the 16-Bit I/O Timer The 16-bit I/O timer consists of one 16-bit free-run timer, two output compares, and four input captures. Using this function enables two independent waveforms to be output based on the 16bit free-run timer and also enables an input pulse width and external clock cycle to be measured. ■ 16-bit Free-run Timer (x 1) The 16-bit free-run timer consists of the 16-bit up counter, control register, and prescaler. An output value of this timer counter is used as the basic time (base timer) of the input capture and output compare. ❍ Counter operation clock (selectable from four types) Four types of internal clocks: φ/4, φ/16, φ/64, φ/256 φ: Machine clock ❍ Interrupt An interrupt can be generated by an overflow of a counter value of the 16-bit free-run timer or a compare match with compare register 0. (The compare match requires mode setting.) ❍ Counter value An interrupt can be generated if a counter value of the 16-bit free-run timer overflows or a match with compare register 0 occurs (a compare match can be used according to mode setting). ❍ Initialization A counter value can be initialized to ’0000H’ at reset, software clear, or match with compare register 0. ■ Output Compare (x 2) An output compare module consists of two 16-bit compare registers, compare output latch, and control register. When a 16-bit free-run timer value matches a compare register value, the output level is reversed and an interrupt can be generated. ❍ Two compare registers are operated independently. • Output pin and interrupt flag corresponding to each compare register ❍ An output pin can be controlled by pairing two compare registers. • The polarity of the output pin can be reversed using two compare registers. ❍ An initial value of the output pin can be set. ❍ An interrupt can be generated by a compare match. 216 12.1 Overview of the 16-Bit I/O Timer ■ Input Capture (x 4) An input capture module consists of the capture register and control register corresponding to four independent external input pins. The value of the 16-bit free-run timer can be stored in the capture register. An interrupt is also generated upon detection of an edge of the signal input from an external pin. ❍ An edge of an external input signal can be selected. • Selectable from a rising edge, falling edge, or both edges. ❍ Four input captures can operate independently. ❍ An interrupt can be generated by a valid edge of an external input signal. • The extended intelligent I/O service can be activated by an interrupt of the input capture. 217 CHAPTER 12 16-BIT I/O TIMER 12.2 16-Bit I/O Timer Block Diagram Figure 12.2-1 "16-bit I/O Timer Block Diagram" shows the 16-bit I/O timer block diagram. ■ 16-bit I/O Timer Block Diagram Figure 12.2-1 16-bit I/O Timer Block Diagram Interrupt request IVF IVFE STOP MODE CLR Divider CLK1 CLK0 Comparator 0 Clock 16-bit up counter F2 MC-16LX bus Count value output (T15 to T00) Compare control T Q OTE0 OUT0 OTE1 OUT1 Compare register 0 CMOD Compare control T Q Compare register 1 ICP1 ICP0 ICE1 ICE0 Compare interrupt 0 Control section Compare interrupt 1 Each control block Input capture data register 0/2 IN0/2 Edge detection EG11 EG10 EG01 EG00 Edge detection Input capture data register 1/3 ICP1 ICP0 ICE1 IN1/3 ICE0 Capture interrupt 1/3 Capture interrupt 0/2 218 12.3 16-Bit I/O Timer Registers 12.3 16-Bit I/O Timer Registers The following six 16-bit I/O timer registers are supported: • Timer data register (TCDTH and TCDTL) • Timer control status register (TCCS) • Compare register (OCCP0 and OCCP1) • Compare control status register (OCS0 and OCS1) • Input capture register (IPCP0 to IPCP3) • Control status register (ICS01 and ICS23) ■ 16-bit I/O Timer Registers Figure 12.3-1 16-bit I/O Timer Registers (continued on the next page) High-order byte of the timer data register Address:00006DH Read/write Initial value 15 14 13 12 11 10 9 8 T15 T14 T13 T12 T11 T10 T09 T08 Bit No. TCDTH (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) Low-order byte of the timer data register Address:00006CH Read/write Initial value 7 6 5 4 3 2 1 0 T07 T06 T05 T04 T03 T02 T01 T00 7 (-) (0) High-order byte of the compare register Low-order byte of the compare register Address: ch0 00005AH ch1 00005CH Read/write Initial value 6 IVFE 4 3 2 STOP MODE CLR 1 0 CLK1 CLK0 Bit No. TCCS (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) 15 C15 5 IVF Reserved Read/write Initial value Address: ch0 00005BH ch1 00005DH Read/write Initial value TCDTL (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) Timer control status register Address:00006EH Bit No. 14 C14 13 C13 12 C12 11 C11 10 C10 9 C09 8 Bit No. OCCP0 OCCP1 C08 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) 7 6 5 4 3 2 1 0 C07 C06 C05 C04 C03 C02 C01 C00 Bit No. OCCP0 OCCP1 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) 219 CHAPTER 12 16-BIT I/O TIMER Compare control status register 1 Address: ch1 00005FH Read/write Initial value Compare control status register 0 Address: ch0 00005EH Read/write Initial value High-order byte of the input capture register Address: ch0 000061H ch1 000063H ch2 000065H ch3 000067H Read/write Initial value Low-order byte of the input capture register Address: ch0 000060H ch1 000062H ch2 000064H ch3 000066H Read/write Initial value 15 14 12 11 10 9 Bit No. 8 CMOD OTE1 OTE0 OTD1 OTD0 (-) (-) (-) (-) (-) (-) 7 IOP1 5 IOP0 4 IOE1 3 14 2 IOE0 (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) 15 13 (-) (-) 12 (-) (-) 11 0 CST1 CST0 10 9 CP13 CP12 CP11 CP10 CP09 CP08 (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) 5 4 3 2 1 8 Bit No. High-order IPCP0 High-order IPCP1 High-order IPCP2 High-order IPCP3 0 Bit No. Low-order IPCP0 Low-order IPCP1 Low-order IPCP2 Low-order IPCP3 CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00 (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) 6 5 4 3 2 1 0 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00 ICP1 OCS0 (R/W) (R/W) (0) (0) CP14 6 Bit No. 1 CP15 7 OCS1 (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) 6 High-order byte of the input capture control status register 01 7 Address: 000068H 13 Bit No. ICS01 Read/write Initial value (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) Low-order byte of the input capture control status register 23 7 6 5 4 3 2 1 0 Address: 00006AH Read/write Initial value 220 ICP3 ICP2 ICE3 ICE2 EG31 EG30 EG21 EG20 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) Bit No. ICS23 12.3 16-Bit I/O Timer Registers 12.3.1 16-bit Free-run Timer The following two 16-bit free-run timer registers are supported: • Timer Data register (TCDTH and TCDTL) • Timer Control status register (TCCS) ■ Timer Data Register (TCDTH and TCDTL) The data register can read a count value of the 16-bit free-run timer. The counter value is cleared to 0000H at reset. A timer value can be set by a write to this register and this write operation must be performed during stop (STOP = 1) status. The 16-bit free-run timer is initialized by the following sources: • By a reset • By a clear bit (CLR) of the control status register • By a match between the compare register 0 of the output compare and a timer counter value. (The mode setting is required.) Figure 12.3-2 Timer Data register High-order byte of the timer data register Address:00006DH Read/write Initial value Low-order byte of the timer data register Address:00006CH Read/write Initial value 15 14 13 12 11 10 9 8 Bit No. T15 T14 T13 T12 T11 T10 T09 T08 TCDT (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) 7 6 5 4 3 2 1 0 Bit No. T07 T06 T05 T04 T03 T02 T01 T00 TCDT (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) Note: This register requires word accesses. 221 CHAPTER 12 16-BIT I/O TIMER ■ Timer Control Status Register (TCCS) Figure 12.3-3 Control Status Register Timer control status register 7 Address:00006EH Read/write Initial value Reserved (-) (0) 6 IVF 5 IVFE 4 3 2 STOP MODE CLR 1 0 CLK1 CLK0 Bit No. TCCS (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) [Bit 7] Reserved bit Bit7 is reserved. Set this bit to 0. [Bit 6] IVF IVF is an interrupt request flag of the 16-bit free-run timer. If the 16-bit free-run timer causes an overflow or the counter is cleared with a match with compare register 0 through mode setting, this bit is set to 1. An interrupt is generated if the IVFE bit (bit 5) is set. This bit is cleared by writing 0. Writing 1 is meaningless. Value 1 can be read by a read modify instruction. Table 12.3-1 Function of IVF (Interrupt Request Flag) IVF Function 0 No interrupt request (initial value) 1 Interrupt request [Bit 5] IVFE IVFE is an interrupt enable bit of the 16-bit free-run timer. When this bit is 1, if the IVF bit (bit 6) is set to 1, an interrupt occurs. Table 12.3-2 Function of IVFE (Interrupt Enable Bit) IVFE 222 Function 0 Interrupt disabled (initial value) 1 Interrupt enabled 12.3 16-Bit I/O Timer Registers [Bit 4] STOP The STOP bit is used to stop the 16-bit free-run timer count. When 1 is written, the timer count stops. When 0 is written, the timer count starts. Table 12.3-3 Function of STOP (Count Stop Bit) STOP Function 0 Count enabled (operation) (initial value) 1 Count disabled (stop) Note: If the 16-bit free-run timer count stops, the output compare operation also stops. [Bit 3] MODE The MODE bit is used to set the initialization condition of the 16-bit free-run timer. If this bit is 0, a counter value can be initialized by the reset or CLR bit (bit 2). If it is 1, the counter value can be initialized by the reset, CLR bit (bit 2), or a match with compare register 0 of the output compare. Table 12.3-4 Function of MODE (Initialization Condition Setting Bit) MODE Function 0 Initialization by the reset or clear bit (initial value) 1 Initialization by the reset, clear bit, or match with compare register 0 Note: The counter value is initialized at the change point of the counter value. [Bit 2] CLR The CLR bit is used to initialize an active 16-bit free-run timer value to 0000H. When 1 is written, the counter value is initialized to 0000H. Writing 0 is meaningless. Value 0 is always read. The counter value is initialized at the count value change point. Table 12.3-5 Function of CLR (Initialization Bit) CLR Function 0 Meaningless (initial value) 1 Initializes a counter value to 0000H. Note: To initialize a counter value while the timer is stopped, write 0000H in the data register. 223 CHAPTER 12 16-BIT I/O TIMER [Bits 1 and 0] CLK1 and CLK0 CLK1 and CLK0 bits are used to select a count clock of the 16-bit free-run timer. A clock is updated immediately after the values are written to these bits. Before the values are written to these bits, always stop an output compare operation and input capture operation. Table 12.3-6 CLK1 and CLK0 (Count Clock Selection Bits) CLK1 CLK0 Count clock φ=16MHz φ=8MHz φ=4MHz φ=1MHz 0 0 φ/4 0.25 μs 0.5 μs 1 μs 4 μs 0 1 φ/16 1 μs 2 μs 4 μs 16 μs 1 0 φ/64 4 μs 8 μs 16 μs 64 μs 1 1 φ/256 16 μs 32 μs 64 μs 256 μs φ = machine clock 224 12.3 16-Bit I/O Timer Registers 12.3.2 Output Compare The output compare has the following two registers: • Compare register (OCCP0 and OCCP1) • Control status register (OCS0 and OCS1) ■ Compare Register (OCCP0 and OCCP1) Figure 12.3-4 Compare registers High-order byte of the compare register Address: ch0 00005BH ch1 00005DH Read/write Initial value Low-order byte of the compare register Address: ch0 00005AH ch1 00005CH Read/write Initial value 15 C15 14 C14 13 C13 12 C12 11 C11 10 C10 9 C09 8 Bit No. OCCP0 OCCP1 C08 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) 7 6 5 4 3 2 1 0 C07 C06 C05 C04 C03 C02 C01 C00 Bit No. OCCP0 OCCP1 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) Note: This register requires word accesses. The compare register is a 16-bit register used to make a comparison with the 16-bit free-run timer. An initial value of a register value is undefined. Therefore, set the initial value, then allow the activation. When this register value matches a 16-bit free-run timer value, a compare signal is generated to set the output compare interrupt flag. If output is enabled, the output level associated with the compare register is reversed. 225 CHAPTER 12 16-BIT I/O TIMER ■ Control Status Register (OCS0 to OCS1) Figure 12.3-5 Control Status Register Compare control status register 1 Address: ch1 00005FH Read/write Initial value Compare control status register 0 Address: ch0 00005EH Read/write Initial value 15 14 13 12 11 10 9 Bit No. 8 CMOD OTE1 OTE0 OTD1 OTD0 (-) (-) (-) (-) (-) (-) 7 IOP1 (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) 6 IOP0 OCS1 5 IOE1 4 3 2 IOE0 (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (-) (-) (-) (-) 1 0 CST1 CST0 Bit No. OCS0 (R/W) (R/W) (0) (0) [Bits 15 to 13] Unused bits [Bit 12] CMOD CMOD switches the pin output level reverse operation mode for a compare match when pin output is allowed (OTE1 = 1 or OTE0 = 1). ❍ For CMOD = 0 (initial value) When CMOD is 0 (initial value), the output level of the pin corresponding to the compare register is reversed. • OUT0: Reverses the level by a match with compare register 0. • OUT1: Reverses the level by a match with compare register 1. ❍ For CMOD = 1 When CMOD is 1, the output level of the pin (OUT0) corresponding to the compare register 0 is reversed in the same way as when CMOD is 0. However, the output level of the pin (OUT1) corresponding to the compare register 1 is reversed by either a match with compare register 0 or a match with compare register 1. If values of compare registers 0 and 1 are equal, the operation is the same as when one compare register is used. - OUT0: Reverses the level by a match with compare register 0. - OUT1: Reverses the level by either a match with compare register 0 or a match with compare register 1. [Bits 11 and 10] OTE1 and OTE0 OTE1 and OTE0 bits enable the pin output of the output compare. The initial value of these bits is 0. Table 12.3-7 Function of OTE1 and OTE0 (Pin Output Enable Bits) OTE1, 0 Function 0 Operates as a general-purpose port. [Initial value] 1 Enables the output compare pin output. Note: OTE1 corresponds to output compare 1 and OTE0 to output compare 0. 226 12.3 16-Bit I/O Timer Registers [Bits 9 and 8] OTD1 and OTD0 OTD1 and OTD0 bits are used to change the pin output level when the pin output of the output compare is enabled. The initial value of the compare pin output is 0. Before writing, stop the compare operation. At reading, an output compare pin output value can be read. Table 12.3-8 Function of OTD1 and OTD0 (Pin Output Level Change Bits) OTD1, OTD0 Function 0 Sets the compare pin output to 0. [Initial value] 1 Sets the compare pin output to 1. Note: OTD1 corresponds to output compare 1 and OTD0 corresponds to output compare 0. [Bits 7 and 6] ICP1 and ICP0 ICP1 and ICP0 are output compare interrupt flags. These bits are set to 1 when the compare register matches a 16-bit free-run timer value. When interrupt request bits (ICE1 and ICE0) are enabled, if ICP1 and ICP0 bits are set, an output compare interrupt occurs. These bits are cleared by writing 0. Writing 1 is meaningless. Value 1 can be read by read modify instructions. Table 12.3-9 Function of ICP1 and ICP0 (Output Compare Interrupt Bits) ICP1, ICP0 Function 0 No compare match [initial value] 1 Compare match Note: ICP1 corresponds to output compare 1 and ICP0 to output compare 0. [Bits 5 and 4] ICE1 and ICE0 ICE1 and ICE0 are output compare interrupt enable bits. When these bits are 1, if the interrupt flags (ICP0 and ICP1) are set, an output compare interrupt occurs. Table 12.3-10 Function of ICE1 and ICE0 (Output Compare Interrupt Enable Bits) ICE1, ICE0 Function 0 Disables an output compare interrupt. [Initial value] 1 Enables an output compare interrupt. Note: ICE1 corresponds to output compare 1 and ICE0 to output compare 0. [Bits 3 and 2] Unused bits 227 CHAPTER 12 16-BIT I/O TIMER [Bits 1 and 0] CST1 and CST0 CST1 and CST0 are used to enable the match operation with the 16-bit free-run timer. Table 12.3-11 CST1 and CST0 (for Enabling the Match Operation with the 16-bit Free-run Timer) CST1, CST0 Setting 0 Disables compare operation. [Initial value] 1 Enables compare operation. • Before enabling the compare operation, set a compare register value. Note: CST1 corresponds to output compare 1 and CST0 to output compare 0. Note: The output compare is synchronized with clocks of the 16-bit free-run timer. Therefore, the compare operation stops when the 16-bit free-run timer stops. 228 12.3 16-Bit I/O Timer Registers 12.3.3 Input Capture The input capture has the following two registers: • Input capture data register (IPCP0 to IPCP3) • Control status register (ICS23 and ICS01) ■ Input Capture Data Register (IPCP0 to IPCP3) Input capture data registers (IPCP0 to IPCP3) are used to retain 16-bit free-run timer values when a valid edge of the corresponding external pin input waveform is detected. Figure 12.3-6 Input Capture Data Registers (IPCO0 to IPCO3) High-order byte of the input capture register Address: ch0 000061H ch1 000063H ch2 000065H ch3 000067H Read/write Initial value 15 14 13 12 11 10 9 CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08 (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) Low-order byte of the input capture register Address: ch0 000060H ch1 000062H ch2 000064H ch3 000066H Read/write Initial value 7 6 5 4 3 2 Bit No. High-order High-order High-order High-order 8 1 Bit No. 0 CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00 (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) IPCP0 IPCP1 IPCP2 IPCP3 Low-order Low-order Low-order Low-order IPCP0 IPCP1 IPCP2 IPCP3 Note: Input capture data registers (IPCP0 to IPCP3) require word access. Writing is not possible. ■ Control Status Registers (ICS23 and ICS01) Figure 12.3-7 Control Status Registers (ICS23 and ICS01) Input capture control status register 01 Address: 000068H Read/write Initial value Input capture control status register 23 Address: 00006AH Read/write Initial value 7 6 5 4 3 ICP1 ICP0 ICE1 ICE0 1 0 Bit No. EG01 EG00 ICS01 2 EG11 EG10 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) 7 6 5 4 ICP3 ICP2 ICE3 ICE2 3 EG31 2 EG30 1 EG21 0 EG20 Bit No. ICS23 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) Note: Input capture control status register (ICS23 and ICS01) register requires byte access. 229 CHAPTER 12 16-BIT I/O TIMER [Bits 7, and 6] ICPx (x: channel number) ICPx is an input capture interrupt flag. When the valid edge of an external input pin is detected, this bit is set to 1. When the corresponding interrupt enable bit ICEx is set, an interrupt can be generated by detecting the valid edge. This bit is cleared by writing 0. Writing 1 is meaningless. Value 1 can be read by read modify write instructions. Table 12.3-12 Function of ICPx (Input Capture Interrupt Flag) ICPx Function 0 No valid edge detection (initial value) 1 Valid edge detection [Bits 5, and 4] ICEx (x: channel number) ICEx is an input capture interrupt enable bit. When this bit is 1, if the corresponding interrupt flag ICPx is set, an input capture interrupt occurs. Table 12.3-13 Function of ICEx (Input Capture Interrupt Enable Bit) ICEx Function 0 Interrupt disabled (initial value) 1 Interrupt enabled [Bits 3, 2, 1, and 0] EGx1 and EGx0 (x: channel number) EGx1 and EGx0 bits specify the valid edge polarity of the external input. These bits can also allow an input capture operation. Table 12.3-14 Function of EGx1 and EGx0 (for Specifying a Valid Edge Polarity of the External Output) 230 EGx1 EGx0 Edge detection polarity 0 0 No edge detection (stop) (initial value) 0 1 Rising edge detection 1 0 Falling edge detection 1 1 Both-edge detection 12.4 16-Bit Free-Run Timer Operations 12.4 16-Bit Free-Run Timer Operations The 16-bit free-run timer starts counting from counter value 0000H after the reset is released. This counter value is used as the reference time of the 16-bit output compare and the 16-bit input capture. ■ 16-bit Free-run Timer Operations A counter value is cleared under the following conditions: • An overflow occurs. • A match occurs with the output compare register 0 value. (Mode setting is required.) • Value 1 is written in the CLR bit of the TCCS register during operation. • 0000H is written in the TCDC register during stop. • Reset An interrupt can occur when an overflow occurs or when the counter is cleared by a match with the compare register 0 value. (The compare match interrupt requires mode setting.) Figure 12.4-1 Clearing the Counter by an Overflow Counter value Overflow FFFF BFFF 7FFF 3FFF 0000 Time Reset Interrupt 231 CHAPTER 12 16-BIT I/O TIMER Figure 12.4-2 Clearing the Counter by a Compare Match with output Compare Register 0 Value Counter value FFFF Match Match BFFF 7FFF 3FFF Time 0000 Reset BFFFH Compare register value Interrupt ■ 16-bit Free-run timer Count Timing Counter clear can be executed by reset, software clear, or match with compare register 0. The counter is cleared by reset or software clear. The counter is also cleared by match with compare register 0. Figure 12.4-3 Clear Timing of the Free-run Timer (Match With Compare Register 0) ' ' Compare register value N Compare match Counter value 232 N 0000 12.5 16-Bit Output Compare Operations 12.5 16-Bit Output Compare Operations The 16-bit output compare compares the specified compare register value with a 16-bit free-run timer value. When a match occurs, it can set the interrupt request flag and reverse the output level. ■ 16-bit Output Compare Operations Figure 12.5-1 Example of an Output Waveform when Compare Registers 0 and 1 are Used (When CMOD = 0) Counter value FFFF BFFF 7FFF 3FFF Time 0000 Reset Compare register 0 value Compare register 1 value BFFFH 7FFFH OUT0 OUT1 Compare 0 interrupt Compare 1 interrupt 233 CHAPTER 12 16-BIT I/O TIMER As shown in Figure 12.5-2 "Example of an Output Waveform when Compare Registers 0 and 1 are Used (Initial value of output is 0, CMOD=1)" the output level can be changed by using both compare registers 0 and 1. Figure 12.5-2 Example of an Output Waveform when Compare Registers 0 and 1 are Used (Initial value of output is 0, CMOD = 1) Counter value FFFF BFFF 7FFF 3FFF 0000 Reset BFFFH Compare register 0 value Compare register 1 value 7FFFH Associated with compare 0. Associated with compare 0 and 1. OUT0 OUT1 Compare 0 interrupt Compare 1 interrupt ■ 16-bit Output Compare Timing When a free-run timer value matches the specified compare register value, the output compare can reverse the output value by generating a compare match signal and can then generate an interrupt. When a compare match occurs, the output reverse timing is executed synchronously with the count timing of the counter. Figure 12.5-3 Compare Operation at Compare Register Rewriting N Counter value Compare register 0 value Compare register 0 write M Compare register 1 value M Compare register 1 write 234 N+1 N+2 No match signal is generated. N+3 N+1 N+3 Compare 0 stop Compare 1 stop 12.5 16-Bit Output Compare Operations Figure 12.5-4 Interrupt Timing N+1 N Counter value Compare register value N Compare match Interrupt Figure 12.5-5 Output Pin Change Timing Counter value Compare register value N N N+1 N+1 N Compare match signal Pin output 235 CHAPTER 12 16-BIT I/O TIMER 12.6 16-Bit Input Capture Operations When detecting the specified valid edge, the 16-bit input capture can take a 16-bit freerun timer value in the capture register to generate an interrupt. ■ 16-bit Input Capture Operations Figure 12.6-1 Example of Input Capture Take-in Timings Counter value FFFFH BFFFH 7FFFH 3FFFH Time 0000H Reset IN0 IN1 Example of IN Capture 0 Undefined Capture 1 Undefined Example of capture Undefined 3FFFH 7FFFH BFFFH Capture 0 interrupt Capture 1 interrupt Capture interrupt Capture 0 = rising edge Capture 1 = falling edge Example of capture = both edges (as an example) 236 3FFFH 12.6 16-Bit Input Capture Operations ■ Input Capture Input Timing Figure 12.6-2 Capture Timing for Input Signals Counter value N N+1 Input capture input Valid edge Capture signal Input capture register N+1 Interrupt 237 CHAPTER 12 16-BIT I/O TIMER 238 CHAPTER 13 16-BIT RELOAD TIMER (WITH THE EVENT COUNT FUNCTION) This chapter gives an overview of the 16-bit reload timer (with the event count function) and explains its functions. 13.1 "Overview of the 16-Bit Reload Timer (with the Event Count Function)" 13.2 "Registers of the 16-Bit Reload Timer (with the Event Count Function)" 13.3 "Clock Operations" 13.4 "Underflow Operation" 13.5 "I/O Pin Functions (for the Internal Clock Mode)" 13.6 "Counter Operation Statuses" 239 CHAPTER 13 16-BIT RELOAD TIMER (WITH THE EVENT COUNT FUNCTION) 13.1 Overview of the 16-Bit Reload Timer (with the Event Count Function) The 16-bit reload timer has three channels consisting of a 16-bit down counter, a 16-bit reload register, a input pin (TIN), an output pin (TOT), and a control register. An input clock can be selected from one external clock and three internal clocks. ■ Overview of the 16-bit Reload Timer (with the Event Count Function) In the reload mode, a toggle output waveform is output to the output pin (TOT). In the one-shot mode, a rectangular wave is output to indicate that the count is ongoing. The input pin (TIN) becomes an even input in the event count mode and can be used as a trigger or gate input in the internal clock mode. ■ Block Diagram of the 16-bit Reload Timer (with the Event Count Function) Figure 13.1-1 Block Diagram of the 16-bit Reload Timer (with the Event Count Function) 16 / 16-bit reload register / 8 Reload RELD 16-bit down counter F2MC-16LXBUS / 16 UF OUTE OUTL 2 / OUT CTL. GATE INTE UF CSL1 Clock selector CNTE Clear EI 2 OSCLR TRG CSL0 / 2 Re-trigger Port (TIN) IN CTL EXCK 2 2 2 Prescaler clear Output enabled 3 MOD2 MOD1 Machine clock / MOD0 3 Note: Reload timer channels and UART channels are connected as follows: - Reload timer ch0: UAR0 and UART3 - Reload timer ch1: UART1 and UART4 - Reload timer ch2: UART2 240 IRQ Port (TOT) Serial baud rate (chn) 13.2 Registers of the 16-Bit Reload Timer (with the Event Count Function) 13.2 Registers of the 16-Bit Reload Timer (with the Event Count Function) The 16-bit reload timer (with the event count function) has the following four types of registers: • High-order byte of the timer control status register • Low-order byte of the timer control status register • High-order byte of the 16-bit timer register or high-order byte of the 16-bit reload register • Low-order byte of the 16-bit timer register or low-order byte of the 16-bit reload register ■ Registers of the 16-bit Reload Timer (with the Event Count Function) Figure 13.2-1 Registers of the 16-bit Reload Timer (with the Event Count Function) High-order byte of the timer control status register Address: ch0 000049H ch1 00004DH ch2 000051H Read/write Initial value (-) (-) 15 (-) (-) 14 (-) (-) 13 (-) (-) 12 11 10 9 CSL1 CSL0 MOD2 MOD1 High-order TMCSR0 High-order TMCSR1 High-order TMCSR2 (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) Low-order byte of the timer 7 6 5 4 3 2 1 control status register Address: ch0 000048H ch1 00004CH MOD0 OUTE OUTL RELD INTE UF CNTE TRG ch2 000050H Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (0) (0) (0) High-order byte of the 16-bit timer register or high-order byte of the 16-bit reload register 15 14 Address: ch0 00004BH ch1 00004FH ch2 000053H Read/write Initial value 13 Bit No. 8 12 11 10 9 0 Low-order TMCSR0 Low-order TMCSR1 Low-order TMCSR2 Bit No. 8 (READ) High-order TMR0 High-order TMR1 High-order TMR2 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) Low-order byte of the 16-bit timer register or low-order byte of the 16-bit reload register 7 6 5 4 3 2 1 Address: ch0 00004AH ch1 00004EH ch2 000052H Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (X) (X) (X) (X) (X) (X) (X) (X) Bit No. 0 (WRITE) High-order TMRLR0 High-order TMRLR1 High-order TMRLR2 Bit No. (READ) Low-order TMR0 Low-order TMR1 Low-order TMR2 (WRITE) Low-order TMRLR0 Low-order TMRLR1 Low-order TMRLR2 241 CHAPTER 13 16-BIT RELOAD TIMER (WITH THE EVENT COUNT FUNCTION) 13.2.1 Timer Control Status Register (TMCSR) The timer control status register (TMCSR) controls 16-bit timer operation modes and interrupts. ■ Timer Control Status Register (TMCSR) Figure 13.2-2 Timer Control Status Register (TMCSR) High-order byte of the timer control status register Address: ch0 000049H ch1 00004DH ch2 000051H Read/write Initial value Low-order byte of the timer control status register Address: ch0 000048H ch1 00004CH ch2 000050H Read/write Initial value 15 14 13 12 11 CSL1 (-) (-) (-) (-) (-) (-) (-) (-) 7 6 5 10 9 Bit No. 8 High-order TMCSR0 High-order TMCSR1 High-order TMCSR2 CSL0 MOD2 MOD1 (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) MOD0 OUTE OUTL RELD 4 INTE 3 2 UF CNTE 1 0 TRG Bit No. Low-order TMCSR0 Low-order TMCSR1 Low-order TMCSR2 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) Note: Rewrite a bit other than the UF, CNTE, and TRG bits when CNTE is 0. [Bits 11 and 10] CSL1 and CSL0 CSL1 and CSL0 bits are used to select a count clock. The following table lists the clock sources to be selected: Table 13.2-1 Function of CSL1 and CSL0 (Count clock select bit) Clock source (machine cycle φ = 16 MHz) CSL1 CSL0 0 0 φ/21 (0.125 μs) [Initial value] 0 1 φ/23 (0.5 μs) 1 0 φ/25 (2.0 μs) 1 1 External event count mode [Bits 9, 8, and 7] MOD2, MOD1, and MOD0 MOD2, MOD1, and MOD0 bits are used to set an operation mode and an I/O pin function. When MOD2 = 0, the input pin functions as trigger input. If a valid edge is input, the contents of the reload register are loaded to the counter and the count operation continues. When MOD2 = 1, the gate counter mode is entered. The input pin (TIN) becomes a gate input and the count operation continues only while the valid level is input. The MOD1 and MOD0 bits are used to set a pin function in each mode. 242 13.2 Registers of the 16-Bit Reload Timer (with the Event Count Function) Table 13.2-2 Functions of MOD2, MOD1, and MOD0 (for Setting an Operation Mode and I/O Pin Function) Mode MOD2 MOD1 MOD0 I/O pin function Valid edge, level 0 0 0 Trigger disabled - 0 0 1 Trigger input Rising edge 0 1 0 Falling edge 0 1 1 Both edges 1 x 0 1 x 1 x 0 0 - - 0 1 Trigger input Rising edge 1 0 Falling edge 1 1 Both edges Internal clock mode (CSL0, 1=00B, 01B, 10B) Event count mode (CSL0,1=11B) Gate input L level H level x: Any value [Bit 6] OUTE The OUTE bit enables the output. • When this bit is 0, the TOT pin is used as the general-purpose port. • When this bit is 1, the TOT pin is used as the timer output pin [Bit 5] OUTL The OUTL bit sets the output level of the TOT pin. [Bit 4] RELD (Reload) The RELD bit enables the reload operation. • When this bit is 0, a one-shot operation mode is entered. The count operation stops with the underflow of the counter value from 0000H to FFFFH. • When this bit is 1, a reload mode is entered. An underflow of the counter value from 0000H to FFFFH occurs and, at the same time, the contents of the reload register are loaded to the counter. The count operation continues. Table 13.2-3 Function of RELD (reload operation enable bit) OUTE RELD OUTL Output waveform 0 x x General-purpose port 1 0 0 Output of H level rectangular wave during counting 1 0 1 Output of L level rectangular wave during counting 1 1 0 Toggle output. L level at start of count 1 1 1 Toggle output. H level at start of count x: Any value 243 CHAPTER 13 16-BIT RELOAD TIMER (WITH THE EVENT COUNT FUNCTION) [Bit 3] INTE (INTerrupt Enable) The INTE bit enables a timer interrupt request. When the INTE bit is set to 1, an interrupt request is generated even if the UF bit is changed to 1. When the INTE bit is set to 0, an interrupt request is not generated even if the UF bit is changed to 1. Table 13.2-4 Function of INTE (for Enabling a Timer Iinterrupt Request) INTE Function 0 Interrupt disabled 1 Interrupt enabled [Bit 2] UF (UnderFlow) The UF bit is a timer interrupt request flag. This bit is set to 1 with an underflow of the count value from 0000H to FFFFH. This bit is cleared by writing 0 or by the extended intelligent I/O service. Writing 1 in this bit is meaningless. Value 1 is read at reading by read modify write instructions. [Bit 1] CNTE (CouNT Enable) The CNTE bit enables timer counting. When 1 is written in this bit, an activation trigger wait status is entered. Writing 0 stops the count operation. [Bit 0] TRG (TRiG) The TRG bit triggers software. A software trigger is provided by writing 1, and the contents of the reload register are loaded to the counter. The count operation starts. Writing 0 is meaningless. Value 0 is always read. The trigger input by this register is valid only when CNTE is 1. No operation occurs when CNTE is 0. 244 13.2 Registers of the 16-Bit Reload Timer (with the Event Count Function) 13.2.2 16-bit Timer Register (TMR) and 16-bit Reload Register (TMRLR) The 16-bit timer register (TMR) (at reading) can read a count value of the 16-bit timer. The initial value is undefined. The 16-bit reload register (TMRLR) (at writing) is used to retain the initial value of the count. The initial value is undefined. ■ 16-bit Timer Register (TMR) and 16-bit Reload Register (TMRLR) Figure 13.2-3 16-bit Timer Register (TMR) and 16-bit Reload Register (TMRLR) High-order byte of the 16-bit timer register or high-order byte of the 16-bit reload register 15 14 Address: ch0 00004BH ch1 00004FH ch2 000053H Read/write Initial value 13 12 11 10 9 8 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) Low-order byte of the 16-bit timer register or low-order byte of the 16-bit reload register 7 6 5 4 3 2 1 Address: ch0 00004AH ch1 00004EH ch2 000052H Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (X) (X) (X) (X) (X) (X) (X) (X) 0 Bit No. (READ) High-order TMR0 High-order TMR1 High-order TMR2 (WRITE) High-order TMRLR0 High-order TMRLR1 High-order TMRLR2 Bit No. (READ) Low-order TMR0 Low-order TMR1 Low-order TMR2 (WRITE) Low-order TMRLR0 Low-order TMRLR1 Low-order TMRLR2 Note: Word accesses are required for the 16-bit timer register (TMR) and 16-bit reload register (TMRLR). 245 CHAPTER 13 16-BIT RELOAD TIMER (WITH THE EVENT COUNT FUNCTION) 13.3 Clock Operations When the timer is operated with a divide-by clock of internal clocks, the divide-by clock can be selected, as a clock source, from 21, 23, and 25 divide-by clocks of the machine clock. The external input pin can be used as the trigger or gate input by the register setting. ■ Internal Clock Operations To start the count operation the moment the count is enabled, write 1 in both the CNTE and TRG bits of the control register. The trigger input by the TRG bit is always valid when the timer is in the activation status (CNTE = 1) regardless of an operation mode. The time of T (T: machine cycle) is required from when the trigger of the counter start is input until data of the reload register is loaded to the counter. Figure 13.3-1 Counter Activation and Operation Count clock Reload data Counter 1 1 1 Data load CNTE (bit) TRG (bit) T ■ External Event Count When an external clock is selected, the TIN pin becomes an external event input pin to count the valid edge set by the register. Input a pulse width of at least 4 x T (T: machine cycle) to the TIN pin. 246 13.4 Underflow Operation 13.4 Underflow Operation The 16-bit reload timer (with the event count function) defines the following case as an underflow: when a counter value changes 0000H to FFFFH. Therefore, an underflow occurs with [reload register setting value + 1]. ■ Underflow Operation If an underflow occurs when the RELD bit of the control register is 1, the contents of the reload register are loaded to the counter to continue the count operation. When the RELD bit of the control register is 0, the counter stops with FFFFH. If an underflow occurs, the UF bit of the control register is set. At this time, if the INTE bit is 1, an interrupt request is generated. Figure 13.4-1 Underflow Operation [For RELD = 1] Count clock 0000H Counter Reload data 1 1 1 Data load Underflow set [For RELD = 0] Count clock Counter 0000H FFFFH Underflow set ■ Extended Intelligent I/O Service (EI2OS) Function and Interrupts This timer supports EI2OS. When an underflow occurs, EI2OS can be activated. This product allows EI2OS to be used with both timers. However, because the timer with three channels (ch0-2) is connected to the same interrupt control register (ICRx) in the interrupt controller, ch0 to ch2 cannot be allocated to different EI2OS services. It both timers have different interrupt vectors, they can be allocated to two different interrupt services. However, as previously described, because ch0 to ch2 share the interrupt control register, the same interrupt level applies to three channels. 247 CHAPTER 13 16-BIT RELOAD TIMER (WITH THE EVENT COUNT FUNCTION) 13.5 I/O Pin Functions (for the Internal Clock Mode) If an internal clock is selected as a clock source, the TIN pin can be used as either a trigger or gate input. The output polarity can be set by the OUTL bit of the register. In the reload mode, the TOT pin functions as the toggle output, which is reversed by an underflow. In the oneshot mode, the TOT pin functions as the pulse output, which indicates that the count is ongoing. ■ Input Pin Function (for the Internal Clock Mode) If an internal clock is selected as the clock source, the TIN pin can be used as either a trigger or gate input. If the TIN pin is used as the trigger input, when an active edge is input as shown in Figure 13.51 "Trigger Input Operation" the contents of the reload register are loaded to the counter. After the internal prescaler is cleared, the count operation starts. Input a pulse width of at least 2 x T (T: machine cycle) to TIN. Figure 13.5-1 Trigger Input Operation Count clock TIN At rising edge detection Prescaler clear Counter Reload data 1 1 1 1 Load 2T to 2.5T If the TIN pin is used as the gate input, the count occurs only while the active level set by the MOD0 bit of the control register is input from the TIN pin, as shown in Figure 13.5-2 "Gate Input Operation". At this time, the count clock continues without stopping. The software trigger in the gate mode is possible regardless of the gate level. Input a pulse width of at least 2 x T (T: machine cycle) to the TIN pin. 248 13.5 I/O Pin Functions (for the Internal Clock Mode) Figure 13.5-2 Gate Input Operation Count clock TIN For MOD0 = 1 (count while H is input) 1 Counter 1 1 ■ Output Pin Function The output polarity can be set by the OUTL bit of the register. In the reload mode, the TOT pin functions as the toggle output, which is reversed by an underflow. In the one-shot mode, the TOT pin functions as the pulse output, which indicates that the count is ongoing. Assume that OUTL is 0. In this case, for the toggle output, the initial value is 0. For the oneshot pulse output, 1 is output to indicate that the count is ongoing. When OUTL is set to 1, the output waveform is reversed. Figure 13.5-3 Output Pin Function (1) Start of count Underflow TOUT Reversed with OUTL = 1. General-purpose port CNTE Activation trigger [RELD=1,OUTL=0] Figure 13.5-4 Output Pin Function (2) Underflow TOUT Reversed with OUTL = 1. General-purpose port CNTE Activation trigger Activation trigger wait status [RELD=0,OUTL=0] 249 CHAPTER 13 16-BIT RELOAD TIMER (WITH THE EVENT COUNT FUNCTION) 13.6 Counter Operation Statuses A counter status is determined by the CNTE bit of the control register and the WAIT signal of the internal signal. The following three statuses can be set: • Stop status (STOP status) by CNTE = 0 and WAIT = 1 • Activation trigger wait status (WAIT status) by CNTE = 1 and WAIT = 1 • Operation status (RUN status) by CNTE = 1 and WAIT = 0 ■ Counter Operation Statuses Figure 13.6-1 "Counter Status Transition" shows the counter operation statuses. Figure 13.6-1 Counter Status Transition Reset Status transition by hardware STOP CNTE=0,WAIT=1 Status transition by register access TIN: Input disabled TOUT: General-purpose port Counter: Holds the value at stop. Undefined immediately after the reset. CNTE= '0' WAIT CNTE= '0' CNTE= '1' CNTE= '1' TRG= '0' TRG= '1' CNTE=1,WAIT=1 RUN CNTE=1,WAIT=0 TIN: Only trigger is valid TIN: Functions as TIN TOUT: Initial value is output TOUT: Functions as TOUT Counter: Holds the value at stop. Undefined immediately after the reset until the contents are loaded. Counter: Operation RELD UF TRG= '1' TRG= '1' RELD UF LOAD Activated from TIN 250 CNTE=1,WAIT=0 The contents of the reload register are loaded to the counter. End of load CHAPTER 14 8/16-BIT PPG This chapter describes the function and operation of the 8/16-bit PPG. 14.1 "Overview of the 8/16-Bit PPG" 14.2 "Block Diagrams of the 8/16-Bit PPG" 14.3 "Registers in the 8/16-Bit PPG" 14.4 "8/16-Bit PPG Operation" 251 CHAPTER 14 8/16-BIT PPG 14.1 Overview of the 8/16-Bit PPG The 8/16-bit PPG is an 8/16-bit reload timer module. Based on timer operation, the module performs pulse output control to allow PPG output. ■ Overview of the 8/16-bit PPG The 8/16-bit PPG consists of two 8-bit down counters, four 8-bit reload registers, one 16-bit control registers, two external pulse output pins, and two interrupt outputs. The PPG provides the following functions: ❍ 8-bit PPG output in 2-channel independent operation mode (8-bit PPG 2-ch mode) Allows 2-channel independent PPG output operation. ❍ 16-bit PPG output operation mode (16-bit PPG 1-ch mode) Allows 2-channel 16-bit PPG output operation. ❍ Pair 8-bit-prescaler + 8-bit-PPG mode Allows 8-bit PPG output operation at the specified interval by applying ch0 output to the ch1 clock input. ❍ PPG output operation Outputs a pulse waveform with an arbitrary cycle period and duty cycle. The PPG can also be used as a D/A converter when a circuit is connected externally. 252 14.2 Block Diagrams of the 8/16-Bit PPG 14.2 Block Diagrams of the 8/16-Bit PPG Figure 14.2-1 "Block Diagram of the 8/16-bit PPG (ch0)" shows a block diagram of the 8/16-bit PPG (ch0), and Figure 14.2-2 "Block Diagram of the 8/16-bit PPG (ch1)" shows a block diagram of the 8/16-bit PPG (ch1). ■ Block Diagrams of the 8/16-bit PPG Figure 14.2-1 Block Diagram of the 8/16-bit PPG (ch0) PPG0 output enabled PPG0 Machine clock divided by 16 Machine clock divided by 8 Machine clock divided by 4 Machine clock divided by 2 Machine clock PPG0 output latch Inversion Clear PEN0 Count clock selection IRQ Reload Time-based timer output (oscillation clock divided by 512) L/H selection S RQ PCNT (down counter) ch1: Borrow L/H selector PRLL0 PRLBH0 PIE0 PRLH0 PUF0 Lower data bus Higher data bus PPGC0 (Operation mode control) 253 CHAPTER 14 8/16-BIT PPG Figure 14.2-2 Block Diagram of the 8/16-bit PPG (ch1) PPG1 output enabled PPG1 A/D converter Machine clock divided by 16 Machine clock divided by 8 Machine clock divided by 4 Machine clock divided by 2 Machine clock PPG1 output latch Inversion Count clock selection Clear PEN1 ch0 Borrow S RQ PCNT (down counter) Time-based timer (output oscillation clock divided by 512) L/H selection IRQ Reload L/H selector PRLL1 PRLBH1 PIE PRLH1 PUF Lower data bus Higher data bus PPGC1 (Operation mode control) 254 14.3 Registers in the 8/16-Bit PPG 14.3 Registers in the 8/16-Bit PPG The registers in the 8/16-bit PPG are classified into the following three types: • PPG0/1 operation mode control register • PPG0/1 output control register • Reload register H/L ■ Registers in the 8/16-bit PPG Figure 14.3-1 Registers in the 8/16-bit PPG PPG0 operation mode control register 7 Address :ch0 000044H PEN0 Read/write Initial value (R/W) (0) PPG1 operation mode control register 15 Address :ch1 000045H PEN1 Read/write Initial value 6 (-) (X) (-) (X) 4 3 2 POE0 PIE0 PUF0 1 Bit No. 0 PPGC0 Reserved (R/W) (R/W) (R/W) (0) (0) (0) 14 (R/W) (0) 5 (-) (X) (-) (X) (-) (1) Bit No. 13 12 11 10 9 8 POE1 PIE1 PUF1 MD1 MD0 Reserved (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) PPGC1 (-) (1) PPG0/1 output control register 7 6 5 4 3 2 1 Address :ch0/1 000046H PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 Read/write Initial value (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) Reload register H 15 14 13 12 11 Bit No. 0 Reserved Reserved (-) (0) 10 PPGOE (-) (0) 9 Bit No. 8 Address :ch0 000041H ch1 000043H Read/write Initial value Reload register L PRLH0 PRLH1 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) 7 6 5 4 3 2 1 Address :ch0 000040H ch1 000042H Read/write Initial value 0 Bit No. PRLL0 PRLL1 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) 255 CHAPTER 14 8/16-BIT PPG 14.3.1 PPG0 Operation Mode Control Register (PPGC0) The PPG0 operation mode control register (PPGC0) is used for selection of the operation mode of the 8/16-bit PPG, pin output control, count clock selection, and trigger control. ■ PPG0 Operation Mode Control Register (PPGC0) Figure 14.3-2 PPG0 Operation Mode Control Register (PPGC0) PPG0 operation mode control register 7 Address :ch0 000044H PEN0 Read/write Initial value (R/W) (0) 6 (-) (X) 5 4 3 POE0 PIE0 PUF0 (R/W) (R/W) (R/W) (0) (0) (0) 2 1 0 Reserved (-) (X) (-) (X) Bit No. PPGC0 (-) (1) [Bit 7] PEN0 (PPg ENable) The PEN0 bit selects the start of PPG operation and the operation mode of the PPG as shown in Table 14.3-1 "PEN0 (Operation Enable Bit) Function". Writing 1 to this bit causes the PPG to start counting. This bit is initialized to 0 at reset. This bit can be read and written. Table 14.3-1 PEN0 (Operation Enable Bit) Function PEN0 Function 0 Operation stopped (low level held output) [initial value] 1 PPG operation enabled [Bit 5] POE0 (PPg Output Enable) The POE0 bit controls the pulse output external pin PPG0 as shown in Table 14.3-2 "POE0 (PPG0 Pin Output Enable Bit) Function". This bit is initialized to 0 at reset. This bit can be read and written. Table 14.3-2 POE0 (PPG0 Pin Output Enable Bit) Function POE0 256 Function 0 General-purpose port pin (pulse output disabled) [initial value] 1 PPG0 = pulse output pin (pulse output enabled) 14.3 Registers in the 8/16-Bit PPG [Bit 4] PIE0 (PPG Interrupt Enable) The PIE0 bit enables or disables PPG interrupts as shown in Table 14.3-3 "PIE0 (PPG Interrupt Enable Bit) Function". If this bit is 1, an interrupt request is issued when PUF0 is set to 1. If this bit is 0, no interrupt request is issued. This bit is initialized to 0 at reset. This bit can be read and written. Table 14.3-3 PIE0 (PPG Interrupt Enable Bit) Function PIE0 Function 0 Interrupt disabled [initial value] 1 Interrupt enabled Note: 8-/16-bit PPG timer 0 (PPG0) and 16-bit reload timer share the interrupt control register (ICR07). To use EI2OS with the 16-bit reload timer, disable PPG0 interrupt (PIE bit = 0). [Bit 3] PUF0 (PPG Underflow Flag) The PUF0 bit controls the PPG counter underflow bit as listed in Table 14.3-4 "PUF0 (PPG Counter Underflow Bit) Function". Table 14.3-4 PUF0 (PPG Counter Underflow Bit) Function PUF0 Function 0 PPG counter underflow is not detected [initial value] 1 PPG counter underflow was detected In the 8-bit PPG 2-ch mode and the 8-bit prescaler + 8-bit PPG mode, an underflow occurred when the ch0 counter value changes from 00H to FFH sets the bit to 1. In the 16-bit PPG 1-ch mode, an underflow caused when the ch1/ch0 counter value changes from 0000H to FFFFH sets the bit to 1. This bit is set to 0 by writing 0 to this bit. Writing 1 to this bit has no meaning. At read in read-modify-write operation, 1 is read from this bit. This bit is initialized to 0 at reset. This bit can be read and written. [Bit 0] Reserved bit Bit 0 is a reserved bit. Whenever setting PPGC0, be sure to set this bit to 1. 257 CHAPTER 14 8/16-BIT PPG 14.3.2 PPG1 Operation Mode Control Register (PPGC1) The PPG1 operation mode control register (PPGC1) is used for selection of the operation mode of the 8/16-bit PPG, pin output control, count clock selection, and trigger control. ■ PPG1 Operation Mode Control Register (PPGC1) Figure 14.3-3 PPG1 Operation Mode Control Register (PPGC1) PPG1 operation mode control register 15 Address :ch1 000045H PEN1 Read/write Initial value (R/W) (0) 14 (-) (X) 13 12 11 10 9 8 POE1 PIE1 PUF1 MD1 MD0 Reserved (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) Bit No. PPGC1 (-) (1) [Bit 15] PEN1 (PPg ENable) The PEN1 bit selects the start of PPG operation and the operation mode of the PPG as shown in Table 14.3-5 "Operation Enable Bit (PEN1) Function". Writing 1 to this bit causes the PWM to start counting. This bit is initialized to 0 at reset. This bit can be read and written. Table 14.3-5 Operation Enable Bit (PEN1) Function PEN1 Function 0 Operation stopped (low level held output) [initial value] 1 PPG operation enabled [Bit 13] POE1 (PPg Output Enable) The POE1 bit controls the pulse output external pin PPG1 as shown in Table 14.3-6 "POE1 (PPG1 Pin Output Enable Bit) Function". This bit is initialized to 0 at reset. This bit can be read and written. Table 14.3-6 POE1 (PPG1 Pin Output Enable Bit) Function POE1 258 Function 0 General-purpose port pin (pulse output disabled) [initial value] 1 PPG1 serving as a pulse output pin (pulse output enabled) 14.3 Registers in the 8/16-Bit PPG [Bit 12] PIE1 (PPG Interrupt Enable) The PIE1 bit enables or disables PPG interrupts as shown in Table 14.3-7 "PIE1 (PPG Interrupt Enable Bit) Function". If this bit is 1, an interrupt request is issued when PUF1 is set to 1. If this bit is 0, no interrupt request is issued. A reset initializes this bit to 0. This bit can be read from and written to. Table 14.3-7 PIE1 (PPG Interrupt Enable Bit) Function PIE1 Function 0 Interrupt disabled [initial value] 1 Interrupt enabled Note: 8-/16-bit PPG timer 1 (PPG1) and UART0 transmission completion share the interrupt control register (ICR11). To use EI2OS with UART0 transmission completion, disable the PPG1 interrupt (PIE bit = 0). [Bit 11] PUF1 (PPG Underflow Flag) PUF1 controls the PPG counter underflow bit as listed in Table 14.3-8 "PUF1 (PPG Counter Underflow Bit) Function". In the 8-bit PPG 2-ch mode and the 8-bit prescaler + 8-bit PPG mode, an underflow occurred when the ch1 counter value changes from 00H to FFH sets the bit to 1. In the 16-bit PPG 1ch mode, an underflow caused when the ch1/ch0 counter value changes from 0000H to FFFFH sets the bit to 1. This bit is set to 0 by writing 0 to this bit. Writing 1 to this bit has no meaning. At read in read-modify-write operation, 1 is read from this bit. A reset initializes this bit to 0. This bit can be read from and written to. Table 14.3-8 PUF1 (PPG Counter Underflow Bit) Function PUF1 Function 0 PPG counter underflow is not detected [initial value] 1 PPG counter underflow was detected 259 CHAPTER 14 8/16-BIT PPG [Bits 10 and 9] MD1,MD0 (PPG count Mode) The MD1 and MD0 bits select the operation mode of the PPG timer as shown in Table 14.39 "MD1 and MD0 (Operation Mode Selection Bits) Function". A reset initializes these bits to 00B. These bits can be read from and written to. Table 14.3-9 MD1 and MD0 (Operation Mode Selection Bits) Function MD1 MD0 Operation mode [initial value] 0 0 8-bit PPG 2-ch mode 0 1 8-bit prescaler + 8-bit PPG 1-ch mode 1 0 Reserved (setting inhibited) 1 1 16-bit PPG 1-ch mode Note: Do not set these bits to 10B. When setting these bits to 01B, do not set the PEN0 bit of PPGC0 to 01B and the PEN1 bit of PPGC1 to 01B. It is recommended that the PEN0 and PEN1 bits be set to 11B or 00B at the same time. When setting these bits to 11B, rewrite PPGC0/PPGC1 by a word transfer to set the PEN0 and PEN1 bits to 11B or 00B at the same time. [Bit 8] Reserved bit Bit 8 is a reserved bit. Whenever setting PPGC1, be sure to set this bit to 1. 260 14.3 Registers in the 8/16-Bit PPG 14.3.3 PPG0/1 Output Pin Control Register (PPGOE) The PPG0/1 output pin control register (PPGOE) is an 8-bit control register for 8/16-bit PPG pin output control. ■ PPG0/1 Output Pin Control Register (PPGOE) Figure 14.3-4 PPG0/1 Output Pin Control Register (PPGOE) PPG0/1 output control register 7 Address :ch0/1 000046H 6 5 4 3 2 PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 Read/write Initial value (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) 1 Reserved Reserved (-) (0) Bit No. 0 PPGOE (-) (0) [Bits 7 to 5] PCS2 to PCS0 (PPg Count Select) PCS2 to PCS0 select the operation clock for the ch1 down counter as shown in Table 14.310 "PCS2 to PCS0 (Count Clock Selection Bits) Function". These bits are initialized to 000B at reset. These bits can be read and written. Table 14.3-10 PCS2 to PCS0 (Count Clock Selection Bits) Function PCS2 PCS1 PCS0 Operation mode 0 0 0 Machine clock (62.5 ns, machine clock at 16 MHz) 0 0 1 Machine clock/2 (125 ns, machine clock at 16 MHz) 0 1 0 Machine clock/4 (250 ns, machine clock at 16 MHz) 0 1 1 Machine clock/8 (500 ns, machine clock at 16 MHz) 1 0 0 Machine clock/16 (1 μs, machine clock at 16 MHz) 1 1 1 Clock input from time-based timer (128 μs, source oscillation at 4 MHz) Note: In the 8-bit prescaler + 8-bit PPG mode and in the 16-bit PPG 1-ch mode, the PPG for ch1 operates with the count clock signal received from ch0. Therefore, the settings on PCS bits are ignored. 261 CHAPTER 14 8/16-BIT PPG [Bits 4 to 2] PCM2 to PCM0 (PPg Count Mode) The PCM2 to PCM0 bits select the operation clock of the ch0 down counter as shown in Table 14.3-11 "PCM2 to PCM0 (Count Clock Selection Bits) Function". These bits are initialized to 000B at reset. These bits can be read and written. Table 14.3-11 PCM2 to PCM0 (Count Clock Selection Bits) Function PCM2 PCM1 PCM0 Operation mode 0 0 0 Machine clock (62.5 ns, machine clock at 16 MHz) 0 0 1 Machine clock/2 (125 ns, machine clock at 16 MHz) 0 1 0 Machine clock/4 (250 ns, machine clock at 16 MHz) 0 1 1 Machine clock/8 (500 ns, machine clock at 16 MHz) 1 0 0 Machine clock/16 (1 μs, machine clock at 16 MHz) 1 1 1 Clock input from time-based timer (128 μs, source oscillation at 4 MHz) [Bits 1 and 0] Reserved bits Bits 1 and 0 are reserved bits. Whenever setting PPGE, be sure to set these bits to 0. 262 14.3 Registers in the 8/16-Bit PPG 14.3.4 Reload Registers (PRLL/PRLH) The reload registers (PRLL/PRLH), each consisting of 8 bits, hold a value to be reloaded to the down counter PCNT. ■ Reload Registers (PRLL/PRLH) Figure 14.3-5 Reload Registers (PRLL/PRLH) 15 Reload register H 14 13 12 11 10 9 Bit No. 8 Address :ch0 000041H ch1 000043H PRLH0 PRLH1 Read/write Initial value (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) 7 Reload register L 6 5 4 3 2 1 Address :ch0 000040H ch1 000042H Read/write Initial value 0 Bit No. PRLL0 PRLL1 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) The reload registers (PRLL/PRLH) have the function shown in Table 14.3-12 "Reload Registers (PRLL/PRLH)". Each register can be read from and written to. Table 14.3-12 Reload Registers (PRLL/PRLH) Register name Function PRLL Holds the reload value for lower data. PRLH Holds the reload value for higher data. Note: In the 8-bit prescaler + 8-bit PPG mode, setting different values in PRLL and PRLH for ch1 may vary the PPG waveform on ch1 from cycle to cycle. Therefore, it is recommended that the same value be set in PRLL and PRLH for ch0. 263 CHAPTER 14 8/16-BIT PPG 14.4 8/16-Bit PPG Operation The 8/16-bit PPG contains two 8-bit PPG units and can operate in the 8-bit 2-ch mode and in two other operation modes, including the 8-bit prescaler + 8-bit PPG mode and the 16-bit PPG 1-ch mode, where the two PPG units interact. ■ 8/16-bit PPG Operation For each of the 8-bit PPG units, two 8-bit reload registers (PRLL and PRLH ) are provided for the lower and higher data. The value for the lower data and the value for the higher data written in these registers are alternately reloaded into the 8-bit down counter (PCNT), which counts down on each clock pulse. At a reload operation performed when a borrow is generated in the counter, the pin output (PPG) value is inverted. This operation allows the pin output (PPG) to output a pulse signal with low-level and high-level widths corresponding to the reload register values. Operation is started and restarted by writing an appropriate register bit. The relationship between reload operation and pulse output is shown in Table 14.4-1 "Relationship between Reload Operation and Pulse Output". Table 14.4-1 Relationship between Reload Operation and Pulse Output Reloading Pin output change PRLH --> PCNT PPG0/1 [0 --> 1] Rising edge PRLL --> PCNT PPG0/1 [1 --> 0] Falling edge When the bit 4 (PIE0) bit of the PPGC0 register is 1 and when the bit 12 (PIE1) bit of the PPGC1 register is 1, a borrow from 00H to FFH in each counter (a borrow from 0000H to FFFFH in the 16-bit PPG mode) causes an interrupt request to be output. ■ 8/16-bit PPG Interrupt An interrupt of the 8/16-bit PPG becomes active when the counter counts out the reloaded value, generating a borrow. In the 8-bit PPG 2-ch mode and in the 8-bit prescaler + 8-bit PPG mode, a borrow into each counter causes a relevant interrupt request. In the 16-bit PPG mode, a borrow into the 16-bit counter sets the PUF0 bit and PUF1 bit at the same time. It is recommended that only one of the PIE0 and PIE1 bits be enabled to determine a single interrupt source. It is also recommended that the interrupt source be cleared by resetting the PUF0 bit and PUF1 bit at the same time. 264 14.4 8/16-Bit PPG Operation ■ Initial Values In Hardware Components A reset initializes hardware components of the 8/16-bit PPG as follows: ❍ Registers • PPGC0 --> 0X000XX1B • PPGC1 --> 0X000001B • PPGOE --> 00000000B ❍ Pulse output • PPG0 --> "L" • PPG1 --> "L" • PE0 --> PPG0 output disabled • PE1 --> PPG1 output disabled ❍ Interrupt request • IRQ0 --> "L" • IRQ1 --> "L" Hardware components other than the above are not initialized. 265 CHAPTER 14 8/16-BIT PPG 14.4.1 8/16-bit PPG Operation Modes The following three types of operation modes are available with the 8/16-bit PPG: • 8-bit 2-ch mode • 8-bit prescaler + 8-bit PPG mode • 16-bit PPG 1-ch mode ■ 8/16-bit PPG Operation Modes ❍ 8-bit 2-ch mode In the 2-ch independent mode, two channels of 8-bit PPG unit operate independently of each other. The PPG0 pin is connected to the PPG output of ch0, and the PPG1 pin is connected to the PPG output of ch1. ❍ 8-bit prescaler + 8-bit PPG mode In the 8-bit prescaler + 8-bit PPG mode, an 8-bit PPG waveform can be output by using ch0 as an 8-bit prescaler and counting ch1 with ch0 borrow output. The PPG0 pin is connected to the prescaler output of ch0, and the PPG1 pin is connected to the PPG output of ch1. ❍ 16-bit PPG 1-ch mode In 16-bit PPG 1-ch mode, ch0 and ch1 are connected and used as 16-bit PPG. The PPG0 pin and PPG1 pin are both connected to 16-bit PPG output. 266 14.4 8/16-Bit PPG Operation 14.4.2 PPG Output Operation 8-/16-bit PPG on ch0 is activated and starts counting when 1 is written to bit 7 (PEN0) of the PPGC0 (PWM operation mode control) register. PPG on ch1 is also activated and starts counting when 1 is written to bit 15 (PEN1) of the PPGC1 register. After an operation is started, a counting operation is stopped by writing 0 to bit 7 of PPGC0 or bit 15 of PPGC1. When the counting operation stops, the pulse output is held at the low-level. ■ PPG Output Operation In PPG output operation, observe the following two precautions: • In the 8-bit prescaler + 8-bit PPG mode, do not enable ch1 operation while ch0 is in the stopped state. • In the 16-bit PPG mode, always perform start and stop control by manipulating bit 7 (PEN0) of the PPGC0 register and bit 15 (PEN1) of the PPGC1 register at the same time. Figure 14.4-1 "Output Waveform During PPG Output Operation" shows PPG output operation. During PPG operation, a pulse waveform is output successively at any frequency and any duty ratio (the ratio of the time the pulse wave is at H level to the time the pulse wave is at L level). Once the PPG starts outputting a pulse waveform, it does not stop until the operation is set to stop. Figure 14.4-1 Output Waveform During PPG Output Operation PEN Output pin PPG Start of operation by PEN (starting with the L level) T (Start) (L+1) T (H+1) L: PRLL value H: PRLH value T: Machine clock ( , /2, /4, /8, /16) or input from timer base counter (by clock select in PPG0E) 267 CHAPTER 14 8/16-BIT PPG ■ Relationship between the Reloaded Value and Pulse Width The pulse width of the output pulse signal is obtained by multiplying the value written in the reload register + 1 by the count clock cycle. Note that when the reload register value is 00H during 8-bit PPG operation and when the reload register value is 0000H during 16-bit PPG operation, the pulse width equals one count clock cycle. When the reload register value is FFH during 8-bit PPG operation, the pulse width equals 256 count clock cycles. Similarly, when the reload register value is FFFFH during 16-bit PPG operation, the pulse width equals 65536 count clock cycles. The following expressions are for calculating a pulse width: Pl = T x (L + 1) Ph = T x (H + 1) L: PRLL value H: PRLH value T: Input clock cycle Ph: High-level pulse width Pl: Low-level pulse width 268 14.4 8/16-Bit PPG Operation 14.4.3 Selecting a Count Clock The count clock used for 8-/16-bit PPG operation is supplied from the machine clock and the time-based counter, and six types of count clock inputs can be selected. Bits 4 to 2 (PCM2 to PCM0) of the PPG0E register are used to select the clock for ch0, and bits 7 to S (PCS2 to PCS0) of the PPG0E register are used to select the clock for ch1. The clock signal is selected from the clocks produced by dividing the machine clock by 16 to 1 and the clocks input from the time-based counter. In the 8-bit prescaler + 8-bit PPG mode or 16-bit PPG mode, however, the value of bit 14 (PCS1) of register PPGC1 is invalid. Since PPG on ch1 receives the count clock from ch0, the register becomes invalid. ■ Notes on Selecting a Count Clock When the time-based timer input is used, the first count cycle when PPG operation is triggered and the first count cycle after PPG operation is stopped may be shifted. In addition, when the time-based counter is cleared during operation of this module, a cycle shift may occur. In the 8-bit prescaler + 8-bit PPG mode, when ch0 is operating and ch1 is in the stopped state, starting ch1 may shift the first count cycle. 269 CHAPTER 14 8/16-BIT PPG 14.4.4 Controlling Pulse Output on Pins The pulse output generated by operating this module can be output on external pin PPG0/PPG1. To output the pulse from the external pins, write 1 to the bits corresponding to the pins. Bit 5 (POE0) of the PPGC0 register is used for the PPG0 pin and bit 13 (POE1) of the PPGC1 register is used for the PPG1 pin. When 0 (initial value) is written to these bits, the pulse output does not appear on the external pins. These pins function as a general-purpose port. ■ Controlling Pulse Output on Pins In the 16-bit PPG 1-ch mode, the same waveform is output on PPG0 and PPG1, so the same output can be obtained by enabling the output of either external pin. In the 8-bit prescaler + 8-bit PPG mode, a toggle waveform from the 8-bit prescaler is output on PPG0, and a waveform from the 8-bit PPG is output on PPG1. Figure 14.4-2 "Output Waveforms in 8-bit Prescaler + 8-bit PPG Mode" gives an example of output waveforms in this mode. Figure 14.4-2 Output Waveforms in 8-bit Prescaler + 8-bit PPG Mode Ph0 Pl0 PPG0 PPG1 Ph1 Pl0 Ph0 Pl1 Ph1 = = = = T T T T Pl1 (L0+1) (L0+1) (L0+1) (L0+1) (L1+1) (H1+1) L0: ch0 PPLL value and ch0 PRLH value L1: ch1 PRLL value H1: ch1 PRLH value T: Input clock cycle Ph0: H level pulse width on PPG0 Pl0: L level pulse width on PPG0 Ph1: H level pulse width on PPG1 Pl1: L level pulse width on PPG1 Note: It is recommended that the same value be set in PRLL for ch0 and PRLH for ch1. 270 14.4 8/16-Bit PPG Operation 14.4.5 Write Timing for the Reload Registers In all modes except the 16-bit PPG 1 mode, it is recommended that a word transfer instruction be used to write to the reload registers PRLL and PRLH. If a byte transfer instruction is used twice to write data in these registers, an output with an unpredictable pulse width may result, depending on the write timing. ■ Write Timing for the Reload Registers Figure 14.4-3 Write Timing Chart PPG0 B A B A C (1) B C C D D In the above timing chart, suppose that the PRLL content is rewritten from A to C before (1), and that after (1), the PRLH content is rewritten from B to D. In such a case, a low for count C and a high for count B are output only once because at point (1), the PRL values include C in PRLL and B in PRLH. Similarly, in the 16-bit PPG mode, perform long-word transfer to write data in PRL for ch0 and ch1, or perform word transfer to write data in PRL in order from ch0 to ch1. In this mode, a write to PRLL for ch0 is performed temporarily. After a write to PRL for ch1 has been performed, a write to PRL for ch0 is performed. In modes other than the 16-bit PPG mode, a write to PRL for ch0 and ch1 can be performed separately. Figure 14.4-4 Block Diagram for the PRL Write Portion Data to be written to PRL for ch0 Write for ch0 in other than 16-bit PPG 1 mode Temporary latch PRL for ch0 Data to be written to PRL for ch1 In 16-bit PPG1 mode, data is transferred in synchronism with write for ch1. Write for ch1 PRL for ch1 271 CHAPTER 14 8/16-BIT PPG 272 CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT This chapter describes the function and operation of the DTP/external interrupt circuit. 15.1 "Overview of the DTP/External Interrupt Circuit" 15.2 "Registers in the DTP/External Interrupt Circuit" 15.3 "Operation of DTP/External Interrupt Circuit" 15.4 "Notes on Using the DTP/External Interrupt Circuit" 273 CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT 15.1 Overview of the DTP/External Interrupt Circuit The data transfer peripheral (DTP)/external interrupt circuit is placed between peripheral devices and the F2MC-16LX CPU. The DTP/external interrupt circuit receives DMA requests or interrupt requests issued from external peripheral devices and posts these requests to the F2MC-16LX CPU to initiate extended intelligent I/O service or interrupt processing. For extended intelligent I/O service, two request levels H and L are selectable. For external interrupt requests, four request levels including H, L, a rising edge, and a falling edge are selectable. ■ Registers in the DTP/External Interrupt Circuit Figure 15.1-1 Registers in the DTP/External Interrupt Circuit Interrupt/DTP enable register Address:000030H Read/write Initial value Read/write Initial value 6 5 4 3 2 1 0 EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 15 14 13 12 11 10 ER7 ER6 ER5 ER4 ER3 ER2 Read/write Initial value LB3 Read/write Initial value 274 9 ER1 8 ER0 Bit No. EIRR 6 5 4 3 2 1 0 LA3 LB2 LA2 LB1 LA1 LB0 LA0 Bit No. ELVR (Low) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) High-order byte of the request level setting register 15 Address:000033H ENIR (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) Low-order byte of the request level setting register 7 Address:000032H Bit No. (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) Interrupt/DTP source register Address:000031H 7 LB7 14 13 12 11 10 9 8 LA7 LB6 LA6 LB5 LA5 LB4 LA4 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) Bit No. ELVR (High) 15.1 Overview of the DTP/External Interrupt Circuit ■ Block diagram of the DTP/external interrupt circuit Figure 15.1-2 Block Diagram of the DTP/External Interrupt Circuit F2MC-16LX bus 8 8 8 16 Interrupt/DTP enable register Gate Source F/F Edge-detection circuit 8 Request input Interrupt/DTP source register Request level setting register 275 CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT 15.2 Registers in the DTP/External Interrupt Circuit The ENIR register determines whether to use device pins as DTP/external interrupt request inputs to initiate the function of issuing a request to the interrupt controller. ■ DTP/External Interrupt Enable Register (ENIR) Figure 15.2-1 DTP/External Interrupt Enable Register (ENIR) DTP/external interrupt enable register Address:000030H Read/write Initial value 7 6 5 4 3 2 1 0 EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 Bit No. ENIR (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) When a bit in the DTP/external interrupt enable register (ENIR) is set to 1, the corresponding pin is used as an DTP/external interrupt request input to initiate the function of issuing a request to the interrupt controller. For a pin corresponding to a bit set to 0, an DTP/external interrupt request input source is held, but no request is issued to the interrupt controller. ■ DTP/External Interrupt Source Register (EIRR) Figure 15.2-2 DTP/External Interrupt Source Register (EIRR) DTP/external interrupt source register 15 14 Address:000031H Read/write Initial value ER7 ER6 13 12 11 10 ER5 ER4 ER3 ER2 9 ER1 8 ER0 Bit No. EIRR (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) When the EIRR register is read from, it indicates that a corresponding DTP/external interrupt request is present. When the register is written to, the flip-flop content indicating the request is cleared. When 1 is read from a bit in this register, it indicates that an DTP/external interrupt request is present on the pin corresponding to the bit. When 0 is written to this register, the request flip-flop of the corresponding bit is cleared. Writing 1 to this register causes no operation. At read in read-modify-write operation, 1 is read. Note: If more than one external interrupt request output is enabled (EN7 to EN0 of ENIR are set to 1), clear to 0 only the bit for which the CPU accepted an interrupt (any of bits EN7 to EN0 that are set to 1). Do not clear the other bits without a valid reason. 276 15.2 Registers in the DTP/External Interrupt Circuit ■ Request Level Setting Register (ELVR) Figure 15.2-3 Request Level Setting Register (ELVR) Low-order byte of the request level setting register 7 LB3 Address:000032H Read/write Initial value 6 5 4 3 2 1 0 LA3 LB2 LA2 LB1 LA1 LB0 LA0 LB7 Read/write Initial value ELVR (Low) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) High-order byte of the request level setting register 15 Address:000033H Bit No. 14 13 12 11 10 9 8 LA7 LB6 LA6 LB5 LA5 LB4 LA4 Bit No. ELVR (High) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) The ELVR register is used to select request detection. Two bits are assigned to each pin and correspond to each other as listed in Table 15.2-1 "Operation of the Request Revel Setting Register (ELVR)". If a request must be detected according to the level, the value of the register is kept even if the register is cleared while the input is active. Table 15.2-1 Operation of the Request Revel Setting Register (ELVR) LBx LAx Operation 0 0 Request detected by low level 0 1 Request detected by high level 1 0 Request detected by rising edge 1 1 Request detected by falling edge 277 CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT 15.3 Operation of DTP/External Interrupt Circuit If the request set in the ELVR register is input to the corresponding pin after an external interrupt request is set, the external interrupt issues an interrupt request signal to the interrupt controller. The DTP operation sequence is almost the same as external interrupt operation. In particular, the operation steps until the CPU starts the hardware interrupt processing microprogram are exactly the same. ■ External Interrupt Operation If the request set in the ELVR register is input to the corresponding pin after an external interrupt request is set, the external interrupt issues an interrupt request signal to the interrupt controller. When the priority of the interrupts generated concurrently is identified in the interrupt controller and the interrupt from this resource has the highest priority, the interrupt controller issues an interrupt request to F2MC-16LX CPU. The F2MC-16LX CPU compares the ILM bit of the CCR register in the CPU with the interrupt request. If the request level is higher than the ILM bit setting, the CPU starts the hardware interrupt processing microprogram when the currently executed instruction terminates. Figure 15.3-1 External Interrupt Operation External interrupt/DTP circuit F2MC-16LX CPU Interrupt controller Another request ELVR ICR EIRR ENIR Source IL y y CMP ICR x x CMP ILM INTA With the hardware interrupt processing microprogram, the CPU reads ISE bit information from the interrupt controller to confirm that the request is a request for interrupt processing, then passes control to the interrupt processing microprogram. The interrupt processing microprogram reads the interrupt vector area, issues an interrupt acknowledge signal to the interrupt controller, generates a jump destination address of a macro instruction from a vector, transfers the address to the program counter, and then executes a user-defined interrupt processing program. ■ DTP Operation When the extended intelligent I/O service is activated, the user program first sets the address of a register allocated in the range from 000000H to 0000FFH in the I/O address pointer in the extended intelligent I/O service descriptor. The user program then sets the start address of the memory buffer in the buffer address pointer. The DTP operation sequence is almost the same as external interrupt operation. In particular, the operation steps until the CPU starts the hardware interrupt processing microprogram are exactly the same. For DTP, the content of the ISE bit the CPU reads within the hardware 278 15.3 Operation of DTP/External Interrupt Circuit interrupt processing microprogram indicates DTP, so control is passed to the microprogram for processing extended intelligent I/O service. When the extended intelligent I/O service is initiated, a read or write signal is sent to an addressed external peripheral device to perform a transfer with this chip. The external peripheral device must cancel the interrupt request issued for this chip within three machine cycles after the start of the transfer. When the transfer terminates, an operation such as descriptor update is performed. The interrupt controller then generates a signal for clearing the source of the transfer. When receiving the signal for clearing the transfer source, this resource clears the flip-flop that holds the source and is made ready for another request from a pin. Refer to the MB90500 programming manual for details on extended intelligent I/O service processing. Figure 15.3-2 Timing for Canceling an External Interrupt request when DTP Operation Terminates Interrupt source Rising-edge request or high-level request Internal operation *When extended intelligent I/O service is a transfer from I/O register to memory Descriptor selection and read Read address Address bus pin Write address Read data Data bus pin Write data Read signal Write signal To be canceled within 3 machine cycles Data and address buses Internal bus Register External peripheral device Figure 15.3-3 Schematic of a Sample Interface with an External Peripheral Device INT IRQ To be canceled within 3 machine cycles after the end of a transfer DTP CORE MEMORY MB90580C 279 CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT ■ Switching between an external interrupt request and a DTP request Switching between an external interrupt request and a DTP request is performed by setting the ISE bit of an ICR register for this resource. ICR registers are in the interrupt controller. A separate ICR register is assigned to each pin. When the ISE bit of the ICR for a pin is set to 1, the pin functions as a DTP request. When the ISE bit is set to 0, the pin functions as an external interrupt request. Figure 15.3-4 Switching between an External Interrupt Request and DTP Request Interrupt controller ICR ICR y y 0 x x 1 F2MC-16LXCPU Pin External interrupt/DTP Pin DTP External interrupt 280 15.4 Notes on Using the DTP/External Interrupt Circuit 15.4 Notes on Using the DTP/External Interrupt Circuit When using the DTP/external interrupt circuit, special care must be taken regarding the following four points: • Conditions of peripheral devices connected externally when DTP is used • Return from the standby state • DTP/external interrupt circuit operation procedure • External interrupt request level ■ Conditions of Peripheral Devices Connected Externally when DTP is Used External peripheral devices that DTP can support must automatically clear the request when transfer is performed. In addition, unless a peripheral device can cancel its transfer request within three machine cycles after the start of transfer operation, this resource assumes that another transfer request has occurred. ■ Return from the Standby State When using an external interrupt to perform a return from the standby state of the clock stopped mode, use a H level request as the input request. Using a L level request may cause a malfunction. Using an edge request does not cause a return from the standby state of the clock stopped mode. ■ DTP/External Interrupt Circuit Operation Procedure When setting registers in the DTP/external interrupt circuit, proceed as follows. 1. Disable a target bit in the enable register. 2. Set target bits in the request level setting register. 3. Clear a target bit in the source register. 4. Enable the target bit in the enable register. (Note that in steps 3 and 4, a word may be written to the register at a time.) Before setting registers in this resource, always disable the enable register. Also, before enabling the enable register, always clear the source register to prevent an interrupt source from being generated by mistake during register setting or in the interrupt enable state. 281 CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT ■ External Interrupt Request Level • For an edge-detected request, the pulse width must be at least three machine cycles to detect the input of an edge. • For a level-detected request input, even if an external request is input and is canceled later, the request to the interrupt controller is kept active while the interrupt request is enable (ENIR : EN=1). To cancel the request to the interrupt controller, clear the interrupt request flag bit (EIRR : ER). Figure 15.4-1 Clearing the Interrupt Request Flag Bit (EIRR : ER) during Level Setting Interrupt source Level detection The interrupt request flag bit (EIRR:ER) Enable gate To interrupt controller Source is kept unless cleared. Figure 15.4-2 Interrupt Source and Interrupt Request to the Interrupt Controller when an Interrupt is Enabled Interrupt source (At the high level detection) Canceled Interrupt source Interrupt request to interrupt controller The request is made inactive by clearing the interrupt request flag bit (EIRR:ER). 282 CHAPTER 16 DELAYED INTERRUPT GENERATING MODULE This chapter describes the function and operation of the delayed interrupt generating module. 16.1 "Overview of the Delayed Interrupt Generating Module" 16.2 "Operation of the Delayed Interrupt Generating Module" 283 CHAPTER 16 DELAYED INTERRUPT GENERATING MODULE 16.1 Overview of the Delayed Interrupt Generating Module The delayed interrupt generating module generates an interrupt for task switching. With this module, an interrupt request to the F2MC-16LX CPU can be generated and canceled by software. ■ Register in the Delayed Interrupt Generating Module (DIRR) The delayed interrupt source generation/cancel register (DIRR) controls generation and cancellation of a delayed interrupt request. Writing 1 to this register generates a delayed interrupt request, and writing 0 cancels a delayed interrupt request. After a reset, the register is in the source canceled state. Either 0 or 1 may be written to the unused bit area. For future expansion, it is recommended that the set bit and clear bit instructions be used to access this register. Figure 16.1-1 Delayed Interrupt Source Generation/Cancel Register (DIRR) Delayed interrupt source generation/cancel register 15 14 13 12 Address:00009FH Read/write Initial value 11 10 9 8 R0 (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (R/W) (0) ■ Block Diagram of the Delayed Interrupt Generating Module Figure 16.1-2 Block Diagram of the Delayed Interrupt Generating Module F2MC-16LX bus Delayed interrupt source generation/cancel decoder Source latch 284 Bit No. DIRR 16.2 Operation of the Delayed Interrupt Generating Module 16.2 Operation of the Delayed Interrupt Generating Module When software causes the CPU to write 1 to a bit of the DIRR register, the request latch in the delayed interrupt generating module is set, issuing an interrupt request to the interrupt controller. When this interrupt has higher priority than the other interrupt requests, or when there is no other interrupt request, the interrupt controller issues the interrupt request to the F2MC-16LX CPU. ■ Operation of the Delayed Interrupt Generating Module The F2MC-16LX CPU compares the ILM bit of the CCR register in the CPU with an interrupt request. If the request level is higher than the ILM bit setting, the CPU initiates the hardware interrupt processing microprogram when the currently executed instruction terminates. As a result, the interrupt processing routine for this interrupt is executed. Figure 16.2-1 Description of the Generation of a Delayed Interrupt Delayed interrupt generating module Interrupt controller F MC-16LX CPU WRITE Another request ICR IL y y CMP DIRR ICR x x CMP ILM INTA When 0 is written to an appropriate bit of the DIRR register by the interrupt processing routine, the interrupt source is cleared, and task switching is performed at the same time. ■ Note on Use of the Delayed Interrupt Request Latch The delayed interrupt request latch is set by writing 1 to an appropriate bit in the DIRR register, and the latch is cleared by writing 0 to the same bit. Therefore, software must be created so that a source can be cleared within the interrupt processing routine. Otherwise, when control is returned from interrupt processing, the interrupt processing is started again. 285 CHAPTER 16 DELAYED INTERRUPT GENERATING MODULE 286 CHAPTER 17 A/D CONVERTER This chapter describes the functions and provides an overview of the A/D converter. 17.1 "Overview of the A/D Converter" 17.2 "A/D Converter Block Diagram" 17.3 "Resisters of the A/D Converter" 17.4 "Operation of A/D Converter" 17.5 "Conversion Data Protection Function" 287 CHAPTER 17 A/D CONVERTER 17.1 Overview of the A/D Converter The A/D converter converts analog input voltage into a digital value. ■ Overview of the A/D Converter The A/D converter has the following features: ❍ Conversion time Minimum 34.7 μs per channel (in machine cycle at 12 MHz) ❍ Adoption of RC type successive approximation conversion format with a sample and hold circuit ❍ Resolution of 8 or 10 bits ❍ Analog input to be program-selected from eight channels • Single conversion mode: One channel is selected and converted. • Scan conversion mode: The voltage of continuous multiple channels is converted. Up to eight channels can be programmed. • Continuous conversion mode: The voltage of the specified channels is repeatedly converted. • Pause conversion mode: After the voltage of one channel is converted, the converter pauses and waits for the next activation (enables synchronization with the start of conversion). ❍ Interrupt request at completion of A/D conversion At completion of A/D conversion, an interrupt request of A/D conversion completion for the CPU can be generated. The generation of this interrupt enables the start of EI2OS and the transfer of A/D conversion result data to memory. Therefore, the A/D converter is suitable for continuous processing. ❍ Selection of a startup cause from software, external trigger (falling edge), and timer (rising edge) 288 17.1 Overview of the A/D Converter ■ Cautions on using the A/D converter To start the A/D converter using an external trigger or internal timer, use A/D startup cause bits STS1 and STS0 in the ADCS2 register to set the startup. At this time, confirm that the value entered by the external trigger or internal timer is inactive. If it is active, the A/D converter may start immediately. Set STS1 and STS0 when ADTG = 1 (input) and internal timer (timer 2) = 0 (output). Always set the bit of the ADER register that corresponds to the pin used for analog input to 1. Figure 17.1-1 Setting of pin used for analog input Bit No. Address:00001C Read/write 15 14 13 12 11 10 9 8 ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value 11111111B Each pin of port 5 is controlled as follows: • 0: Port input mode • 1: Analog input mode The pin is set to 1 at reset. 289 CHAPTER 17 A/D CONVERTER 17.2 A/D Converter Block Diagram Figure 17.2-1 "A/D Converter Block Diagram" is the A/D converter block diagram. ■ A/D Converter Block Diagram Figure 17.2-1 A/D Converter Block Diagram AVCC AVRH/AVRL AVSS D/A converter Successive approximation register Compare device F MC-16LX Bus AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Input circuit MPX Decoder 2 Sample and hold circuit Trigger start Data register ADCR1,2 Higher byte of control status register Lower byte of control status register ADCS1,2 ADTG PPGI output Timer start Operation clock Prescaler 290 17.3 Resisters of the A/D Converter 17.3 Resisters of the A/D Converter Figure 17.3-1 "Registers of the A/D Converter" shows the registers of the A/D converter. ■ Registers of the A/D Converter Figure 17.3-1 Registers of the A/D Converter Higher byte of the control status register Address:000037H Read/write Initial value 15 14 BUSY INT Read/write Initial value Higher byte of the data register Address:000039H Read/write Initial value Lower byte of the data register Address:000038H Read/write Initial value 12 INTE 11 PAUS STS1 7 MD1 6 MD0 5 4 Bit No. 10 9 STS0 STRT Reserved (W) (0) (-) (0) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) Lower byte of the control status register Address:000036H 13 3 2 8 1 0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0 ADCS2 Bit No. ADCS1 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) 15 14 13 12 11 10 SELB ST1 ST0 CT1 CT0 (W) (0) (W) (0) (W) (0) (W) (0) (W) (1) (-) (-) 9 8 Bit No. D9 D8 ADCR2 (R) (X) (R) (X) 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) Bit No. ADCR1 291 CHAPTER 17 A/D CONVERTER 17.3.1 Control Status Registers (ADCS1 and ADCS2) The control status registers (ADCS1 and ADCS2) control the A/D converter and display its status. ■ Control Status Registers (ADCS1 and ADCS2) Do not rewrite data to ADCS1 and ADCS2 during A/D conversion. Figure 17.3-2 Control Status Registers (ADCS1 and ADCS2) Higher byte of the control status register Address:000037H Read/write Initial value Lower byte of the control status register Address:000036H Read/write Initial value 15 14 13 BUSY INT 12 INTE 11 PAUS STS1 9 STS0 STRT Reserved (W) (0) (-) (0) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) 7 MD1 6 MD0 5 4 Bit No. 10 3 2 8 1 0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0 ADCS2 Bit No. ADCS1 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) Note: Do not rewrite data to ADCS1 during A/D conversion. [Bit 15] BUSY (Busy flag and stop) ❍ At read: This bit is used to indicate the operation of the A/D converter. This bit is set at activation of A/D conversion and cleared at termination. ❍ At write: If 0 is written to this bit during A/D operation, the A/D conversion is forced to be stopped during successive and pause mode. 1 cannot be written to the operation indication bit. In the read/modify/write (RMW) instruction, 1 is read. In single mode, this bit is cleared at termination of A/D conversion. In successive and pause modes, this bit is not cleared until the converter pauses by writing 0. This bit is initialized to 0 at reset. Note: Do not perform forcible stop and activation with software at the same time (when 0 is written to the BUSY bit, do not write 1 to the STRT bit). [Bit 14] INT (Interrupt) INT is used to display data and is set when the conversion data is written to ADCR. If this bit is set when the Bit 5 (INTE) bit is 1, an interrupt request is generated. If the EI2OS activation is allowed, the EI2OS is activated. Writing 1 is meaningless. This setting is cleared by writing 0 in this bit or with an EI2OS interrupt clear signal. This bit is initialized to 0 at reset. 292 17.3 Resisters of the A/D Converter Note: When clearing this bit by writing 0, confirm that the A/D converter is not under operation. [Bit 13] INTE (INTerrupt Enable) The INTE bit specifies whether or not to allow an interrupt by terminating conversion. Set this bit when using the EI2OS. The EI2OS is activated when an interrupt request is generated. This bit is initialized to 0 at reset. Table 17.3-1 Functions of INTE (interrupt enable or disable specification bit) INTE Function 0 Interrupt prohibited [Initial value] 1 Interrupt allowed [Bit 12] PAUS (a/d converter PAUSe) This bit is set when conversion by the A/D is temporarily stopped. Because there is only one register to store A/D conversion result, when successive conversion is performed, the previous data is destroyed unless it is transferred with the EI2OS. To avoid this problem, new data cannot be stored until the contents of the data register is transferred with the EI2OS. During this transmission, conversion by the A/D pauses. The A/ D converter resumes conversion upon completion of transmission with the EI2OS. This bit is initialized to 0 at reset. Note: This bit is valid only when the EI2OS is used. See the conversion data protection function in the operation description. [Bits 11 and 10] STS1 and STS0 (Start Source select) An A/D activation cause is selected by setting the STS1 and STS0 bits. In mode in which multiple activation causes are selected, the A/D converter is activated by the first-selected cause. When switching the conversion activation causes during A/D operation, confirm that the target activation cause is not selected, because the activation cause is changed upon rewriting. The external pin trigger detects a falling edge. If this bit is rewritten and external pin trigger activation is selected when the external trigger input level is L, the A/D converter may be activated. When the timer is selected, output of 16-bit reload timer 1 (PPG1) is selected. Table 17.3-2 Functions of STS1 and STS0 (A/D Startup Cause Selecting Bits) STS1 STS0 Function 0 0 Activation with software [Initial value] 0 1 Activation with an external pin trigger and software 1 0 Activation with a timer and software 1 1 Activation with an external pin trigger, timer, and software 293 CHAPTER 17 A/D CONVERTER [Bit 9] STRT (StaRT) The A/D is activated by writing 1 to the STRT bit. For reactivation, write 1 again. In pause mode, the A/D is not activated because of its operational function. This bit is initialized to 0 at reset. The byte/word instructions read "1". The read-modify-write type instructions read "0". Note: Do not perform forcible stop and activation with software at the same time (when 1 is written to the STRT bit, do not write 0 to the BUSY bit). [Bit 8] Reserved bit Bit 8 is reserved. When setting ADCS1, always set 0. [Bits 7 and 6] MD1 and MD0 (a/d converter MoDe set) The MD1 and MD0 bits are used to set the operation mode of the A/D converter. Table 17.3-3 Operation Modes of MD1 and MD0 MD1 MD0 Operation mode 0 0 Single mode, reactivation during operation is always possible [Initial value] 0 1 Single mode, reactivation during operation is not possible 1 0 Successive mode, reactivation during operation is not possible 1 1 Pause mode, reactivation during operation is not possible ❍ Single mode Performs A/D conversions successively from the setting channels between ANS2 and ANS0 to the setting channels between ANE2 and ANE0. The conversion pauses after each conversion. ❍ Successive mode Performs A/D conversions repeatedly from the setting channels between ANS2 and ANS0 to the setting channels between ANE2 and ANE0. ❍ Pause mode Performs A/D conversions by one channel from the setting channels between ANS2 and ANS0 to the setting channel between ANE2 and ANE0 and pauses. Conversion is resumed by the generation of an activation cause. These bits are initialized to 00 at reset. Note: - If A/D conversion is activated in successive or pause mode, the conversion is repeated until it is stopped by the BUSY bit. - The conversion is stopped by writing 0 to the BUSY bit. - Reactivation is not possible during single, successive, and pause modes and this is true for activation by timer, external trigger, or software. [Bits 5, 4, and 3] ANS2, ANS1, and ANS0 (Analog Start channel set) The ANS2, ANS1, and ANS0 bits set the start channel of A/D conversion. When the A/D converter is activated, A/D conversion starts from the channel selected by this bit. 294 17.3 Resisters of the A/D Converter Table 17.3-4 Start Channel of the ANS2, ANS1, and ANS0 Bits ANS2 ANS1 ANS0 Start channel 0 0 0 AN0 [Initial value] 0 0 1 AN1 0 1 0 AN2 0 1 1 AN3 1 0 0 AN4 1 0 1 AN5 1 1 0 AN6 1 1 1 AN7 Note: When this bit group is read, conversion channel numbers can be read during A/D conversion. While A/D conversion is stopped, however, the previously A/D converted channel numbers are read. Even if values are set in this register, the previously A/D converted values are read instead of the set values until A/D conversion is started. The values read by these bits are the previous conversion channel numbers until A/D conversion is started. These bits are initialized to 000B at reset. [Bits 2, 1, and 0] ANE2, ANE1, and ANE0 (ANalog End channel set) The end channel of A/D conversion is set by ANE2, ANE1, and ANE0 bits. Table 17.3-5 End Channel of ANE2, ANE1, and ANE0 bits ANE2 ANE1 ANE0 End channel 0 0 0 AN0 [Initial value] 0 0 1 AN1 0 1 0 AN2 0 1 1 AN3 1 0 0 AN4 1 0 1 AN5 1 1 0 AN6 1 1 1 AN7 Note: - Setting the same channel as ANE2 to ANE0 and ANS2 to ANS0 selects one-channel conversion (single conversion). - In successive mode or pause mode, the conversion returns to the start channel specified by ANS2 to ANS0 at completion of conversion of the channels specified by ANE2 to ANE0. - If the ANS value is smaller than the ANE value, conversion starts from the ANS channel. When channels up to channel 7 are converted, the conversion returns to channel 0 and 295 CHAPTER 17 A/D CONVERTER channels up to ANE channel are converted. - These bits are initialized to '000B' at reset. Example: Channel setting ANS = 6ch and ANE = 3ch in single mode Conversion is performed in the following sequence: 6ch to 7ch to 0ch to 1ch to 2ch to 3 ch. 296 17.3 Resisters of the A/D Converter 17.3.2 Data Register (ADCR1 and ADCR2) In the data register (ADCR1 and ADCR2), resolution is selected and machine cycle is set. ■ Data Registers (ADCR1 and ADCR2) Figure 17.3-3 Data Registers (ADCR1 and ADCR2) Higher byte of the data register Address:000039H 15 14 13 12 11 SELB ST1 ST0 CT1 CT0 (W) (0) (W) (0) (W) (0) (W) (0) (W) (1) Read/write Initial value Lower byte of the data register Address:000038H Read/write Initial value 9 8 Bit No. D9 D8 ADCR2 (R) (X) (R) (X) 10 (-) (-) 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) Bit No. ADCR1 Note: The value read by ADCR2 is undefined. [Bit 15] SELB The SELB bit is used to select a resolution of 8 or 10 bits. Table 17.3-6 Functions of SELB SELB Resolution 0 10-bit 1 8-bit [Bits 14 and 13] ST1 and ST0 (Sampling Time) The ST1 and ST0 bits set the machine cycle number at sampling. Table 17.3-7 ST1 and ST0 (Machine Cycle Setting Bits at Sampling) ST1 ST0 Machine cycle at sampling 0 0 64 machine cycle 0 1 Reserved 1 0 Reserved 1 1 4096 machine cycle Sampling Time 4 µs/machine clock 16 MHz 256 µs/machine clock 16 MHz 297 CHAPTER 17 A/D CONVERTER [Bits 12 and 11] CT1 and CT0 (Compare Time) The CT1 and CT0 bits set the machine cycle number at compare. Table 17.3-8 CT1 and CT0 (Machine Cycle Number Setting Bits at Compare) CT1 CT0 Machine cycle at compare Compare time 0 0 176 machine cycle 22 µs/machine clock 8 MHz 0 1 352 machine cycle 22 µs/machine clock 16 MHz 1 0 Reserved 1 1 Reserved Note: To set these bits to ’00B’, set the machine clock to up to 8 MHz. [Bits 9 to 0] D9 to D0 D9 to D0 are A/D conversion store registers and digital values of the conversion result are stored. Values in this register are updated whenever a conversion is completed. Usually, the last value of conversion is stored. The registers support the conversion data protection function. See Section 17.4 "Operation of A/D Converter". These registers are undefined at reset. Note: Do not write data to this register during A/D operation. 298 17.4 Operation of A/D Converter 17.4 Operation of A/D Converter The A/D converter is operated using a successive approximation method and has 8- or 10-bits resolution. Because the A/D converter has only one register to store conversion results (8- or 10-bits), the conversion data registers (ADCR0) are updated upon completing conversion. For this reason, the A/D converter alone is not suitable for successive conversion. Therefore, conversion by transferring conversion data to memory using the EI2OS function is recommended. ■ Single Mode In single mode, the A/D converter sequentially converts analog outputs set by ANS and ANE bits and terminates operation when the conversion of the end channel set by the ANE bit is completed. If the start channel and end channel are the same (ANS = ANE), only the channel specified by ANS is converted. [Example] ANS = 000B, ANE = 011B Start --> AN0 --> AN1 --> AN2 --> AN3 --> End ANS = 010B, ANE = 010B Start --> AN2 --> End ■ Successive Mode In successive mode, the A/D converter sequentially converts analog outputs set by ANS and ANE bits, returns to analog outputs by ANS, and continues operation when the conversion of the end channel set by the ANE bit is completed. If the start channel and end channel are the same (ANS = ANE), one-channel conversion specified by ANS is repeated. [Example] ANS = 000B, ANE = 011B Start --> AN0 --> AN1 --> AN2 --> AN3 --> AN0 --> Repeat ANS = 010B, ANE = 010B Start --> AN2 --> AN2 --> AN2 --> Repeat Conversion in successive mode is continued until 0 is written to the BUSY bit. (Writing 0 to the BUSY bit, forced stop of operation) Note that the conversion of data is not completed if the operation is stopped forcibly (In this case, the previous data whose conversion is completed is stored in the conversion register). 299 CHAPTER 17 A/D CONVERTER ■ Pause Mode In pause mode, the A/D converter sequentially converts analog inputs set by the ANS and ANE bits. However, its operation pauses upon conversion of one-channel. To release pausing, reactivate the converter. When the conversion of an end channel set by the ANE bit is completed, the converter returns to the analog input by ANS and continues A/D conversion. If the start channel and end channel are the same (ANS = ANE), the one-channels specified by ANS are converted. [Example] ANS = 000B, ANE = 011B Start --> AN0 --> Stop --> Activate --> AN1 --> Stop --> Activate --> AN2 --> Stop --> Activate --> AN3 --> Stop --> Activate --> AN0 --> Repeat ANS = 010B, ANE = 010B Start --> AN2 --> Stop --> Activate --> AN2 --> Stop --> Activate --> AN2 --> Repeat Only activation causes set by the STS1 and STS0 bits are used in this mode. Using this mode, conversions can be started synchronously. ■ Conversion with the EI2OS Figure 17.4-1 "Example of Flow from Activation of A/D Conversion to Conversion Data Transfer (Successive Mode)" shows an example of the flow from activation of A/D conversion to conversion data transfer (successive mode). Figure 17.4-1 Example of Flow from Activation of A/D Conversion to Conversion Data Transfer (Successive Mode) Activation of A/D conversion Sample and hold Activation of EI2OS Conversion Data transmission Interrupt processing Completion of conversion Interrupt clear Generation of interrupt The portion indicated by 300 is determined by the setting of EI2OS. 17.4 Operation of A/D Converter 17.4.1 Example of EI2OS Activation in Single Mode In single mode, the EI2OS is activated in the following procedure: • Terminate after converting analog input (AN1 to AN3) • Transfer conversion data to the addresses 200H to 205H sequentially • Activate with software • Maximum interrupt level ■ Example of EI2OS Activation in Single Mode Table 17.4-1 Example of EI2OS Activation in Single Mode Setting item Setting of EI2OS Example of programming Description of operation MOV ICR00, #08H Sets the maximum interrupt, activates EI2OS at interrupt, and sets the descriptor address. MOV BAPL, #00H Specifies the transfer destination address of conversion data. MOV BAPM, #02H MOV BAPH, #00H Setting of A/D converter Interrupt sequence MOV ISCS, #18H Specifies word data transfer. After transfer, increments the transfer destination address. Transfers data from I/O to memory and does not terminate transfer by a request from the resource. MOV IOA, #38H Sets the transfer source address (result register of A/D converter). MOV DCT, #03H Transfers data with EI2OS three times. The number of data transfers is the same as the number of conversions. MOV ADCS0, #0BH Specifies single mode, start channel AN1, and end channel AN3. MOV ADCS1, #A2H Specifies activation with software and start of A/D conversion. RETI Specifies return from the interrupt. ICR00: Interrupt control register BAPL: Low-order byte of the buffer address pointer BAPM: Middle-order byte of the buffer address pointer BAPH: high-order byte of the buffer address pointer ISCS: EI2OS status register IOA: I/O address register DCT: Data counter 301 CHAPTER 17 A/D CONVERTER Figure 17.4-2 Example of EI2OS Activation in Single Mode Start activation AN1 Interrupt EI2OS transfer AN2 Interrupt EI2OS transfer AN3 Interrupt EI2OS transfer End Interrupt sequence Parallel processing 302 17.4 Operation of A/D Converter 17.4.2 Example of EI2OS Activation in Successive Mode In successive mode, the EI2OS is activated in the following manner: • Obtain two pieces of conversion data for each channel by converting analog inputs (AN3 to AN5). • Transfer conversion data to the addresses 600H to 60BH sequentially • Start conversion with external edge input • Use maximum interrupt level ■ Example of EI2OS Activation in Successive Mode Table 17.4-2 Example of EI2OS Activation in Successive Mode Setting item Setting of EI2OS Example of programming Description of operation MOV ICR00, #08H Sets the maximum interrupt, activates EI2OS at interrupt, and sets the descriptor address. MOV BAPL, #00H Specifies the transfer destination address of conversion data. MOV BAPM, #06H MOV BAPH, #00H Setting of A/D converter EI2OS termination interrupt sequence MOV ISCS, #18H Specifies word data transfer. After transfer, increments the transfer destination address. Transfers data from I/O to memory, and does not terminate transfer by a request from the resource. MOV I/OA, #38H Sets the transfer source address (result register of A/D converter). MOV DCT, #06H Transfers data with EI2OS six times. Transfers data of 3 channels x 2 statements. MOV ADCS0, #9DH Specifies successive mode, start channel AN3, and end channel AN5. MOV ADCS1, #A4H Specifies activation with external edge and start of A/D conversion. MOV ADCS1, #00H Specifies return from the interrupt. RETI - ICR00: Interrupt control register BAPL: Low-order byte of the buffer address pointer BAPM: Middle-order byte of the buffer address pointer BAPH: high-order byte of the buffer address pointer ISCS: EI2OS status register IOA: I/O address register DCT: Data counter 303 CHAPTER 17 A/D CONVERTER Figure 17.4-3 Example of EI2OS Activation in Successive Mode Start activation AN3 Interrupt EI2OS transfer AN4 Interrupt EI2OS transfer AN5 Interrupt EI2OS transfer After a total of six transmissions Interrupt sequence End 304 17.4 Operation of A/D Converter 17.4.3 Example of EI2OS Activation in Pause Mode In pause mode, the EI2OS is activated in the following manner: • Converts analog input (AN3) 12 times in a certain interval • Transfer conversion data to the addresses 600H to 617H sequentially • Start conversion with external edge input • Use maximum interrupt level ■ Example of EI2OS Activation in Pause Mode Table 17.4-3 Example of EI2OS Activation in Pause Mode Items set Example of programming Description of operation Setting of EI2OS MOV ICR00, #08H Setting of maximum interrupt, activation of EI2OS at interrupt, and setting of descriptor address MOV BAPL, #00H Destination address of conversion data MOV BAPM, #06H MOV BAPH, #00H Setting of A/D converter Interrupt sequence MOV ISCS, #08H Transfers word data and increments destination address after transmission. Transfer from I/O to memory, and does not terminate by a request from a resource. MOV I/OA, #38H Destination address MOV DCT, #OCH Transfers data 12 times with EI2OS. MOV ADCS0, #OBH Pause mode, start channel AN3, end channel AN3 (onechannel conversion) MOV ADCS1, #A4H Activation with external edge, start of A/D converter MOV ADCS1, #00H Recover from interrupt RETI ICR00: Interrupt control register BAPL: Low-order byte of the buffer address pointer BAPM: Middle-order byte of the buffer address pointer BAPH: high-order byte of the buffer address pointer ISCS: EI2OS status register IOA: I/O address register DCT: Data counter 305 CHAPTER 17 A/D CONVERTER Figure 17.4-4 Example of EI2OS Activation in Pause Mode Start activation AN3 Pause Activation with external edge Interrupt EI2OS transfer After 12 transmissions Interrupt sequence End 306 17.5 Conversion Data Protection Function 17.5 Conversion Data Protection Function This A/D converter has the conversion data protection function and features the ability to perform successive conversion using the EI2OS and to secure multiple pieces of data. ■ Conversion Data Protection Function Because there is only one conversion data register, when successive A/D conversion is performed, the conversion data is stored upon completion of each conversion and the previous data is lost. To protect the previous data, this A/D converter pauses without storing new conversion data unless the previous data has been transferred to memory by the EI2OS. The A/D converter is released from the pause when the previous data is transferred to memory by the EI2OS. The A/D converter continues its operation without pause so long as the previous data is transferred to memory. Note: - This function is applied to the INT and INTE bits in the ADCS2 register. - The data protection function works only when the interrupt is allowed (INTE = 1). -- This function does not work when the interrupt is not allowed (INTE = 0). Therefore, in successive A/D conversion, new conversion data is stored successively in the register, destroying previous data. - Also, the INT bit is not cleared if the EI2OS is not used when the interrupt is allowed (INTE = 1). In this case, the data protection function works and the A/D suspends the conversion. The suspension is released by clearing the INT bit in the interrupt sequence. - If the interrupt is disabled when the A/D converter pauses during EI2OS operation, the A/D converter is restarted and the contents of conversion data register may be changed before transfer. Also, the standby data is destroyed if the A/D is restarted during a suspension (pause). 307 CHAPTER 17 A/D CONVERTER Figure 17.5-1 Data Protection Function Flow (when EI2OS is Used) EI2OS setting Activation of A/D successive conversion Completion of first conversion Store in the data register Completion of two conversions Termination of 2 EI OS Activation of EI2OS NO Pause of A/D Note YES Store in the data register YES Termination of 2 EI OS Completion of 3rd conversions Activation of EI2OS Continue Completion of all conversions Activation of EI2OS NO Interrupt routine Completion Stop of A/D Note: - If the converter is reactivated during pause, the conversion data in standby is destroyed. - The flow of the A/D converter in pause is omitted. 308 CHAPTER 18 D/A CONVERTER This chapter explains the functions and operation of the D/A converter. 18.1 "Overview of D/A Converter" 18.2 "D/A Converter Registers" 18.3 "Operation of D/A Converter" 309 CHAPTER 18 D/A CONVERTER 18.1 Overview of D/A Converter This block is the R-2R type D/A converter with a resolution of 8 bits. The D/A converter has two channels. Output control can be executed for two channels using the D/A control registers individually. ■ D/A converter registers D/A converter registers are as follows. Figure 18.1-1 D/A converter registers D/A converter data register 1 15 Bit Address:00003BH Read/write Initial value 14 13 12 DA17 DA16 DA15 DA14 11 10 DA13 DA12 (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (R/W) (0) 9 8 DA11 DA10 DAT1 (R/W) (R/W) (0) (0) D/A converter data register 0 Bit Address:00003AH Read/write Initial value 7 DA07 6 5 4 DA06 DA05 DA04 3 2 DA03 DA02 (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (R/W) (0) 1 0 DA01 DA00 DAT0 (R/W) (R/W) (0) (0) D/A control register 1 Bit Address:00003DH Read/write Initial value 8 15 14 13 12 11 10 9 - - - - - - - (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (R/W) (0) 7 6 5 4 3 2 1 0 - - - - - - (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) DAE1 DACR1 D/A control register 0 Bit Address:00003CH Read/write Initial value 310 DAE0 DACR0 (R/W) (0) 18.1 Overview of D/A Converter ■ D/A converter block diagram Figure 18.1-2 "D/A converter block diagram" is the D/A converter block diagram. Figure 18.1-2 D/A converter block diagram F 2 MC16LX-BUS DA DA DA DA DA DA DA DA 17 16 15 14 13 12 11 10 DA DA DA DA DA DA DA DA 07 06 05 04 03 02 01 00 DVR DVR DA17 DA07 2R 2R R DA16 R DA06 2R 2R R R DA15 DA05 DA11 DA01 2R 2R R DA10 R DA00 2R 2R 2R 2R DAE1 DAE0 Standby control Standby control DA output ch.1 DA output ch.0 311 CHAPTER 18 D/A CONVERTER 18.2 D/A Converter Registers The D/A converter has the following two types of registers: • D/A converter data registers (DAT0 and DAT1) • D/A control registers (DACR0 and DACR1) ■ D/A converter data registers (DAT0 and DAT1) Figure 18.2-1 "D/A converter registers (DAT0 and DAT1)" shows the register configuration of D/A converter registers (DAT0 and DAT1). Figure 18.2-1 D/A converter data registers (DAT0 and DAT1) D/A converter data register 1 15 Bit Address:00003BH Read/write Initial value 14 13 12 DA17 DA16 DA15 DA14 11 10 DA13 DA12 (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (R/W) (0) 9 8 DA11 DA10 DAT1 (R/W) (R/W) (0) (0) D/A converter data register 0 Bit Address:00003AH Read/write Initial value 7 DA07 6 5 4 DA06 DA05 DA04 3 2 DA03 DA02 (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (R/W) (0) 1 DA01 DA00 DAT0 (R/W) (R/W) (0) (0) [Bits 15 to 8] DA17 to DA10 These bits are used to set the output voltage of D/A converter channel 1. These bits are not initialized at reset. These bits can be read and written. [Bits 7 to 0] DA07 to DA00 These bits are used to set the output voltage of D/A converter channel 0. These bits are not initialized at reset. These bits can be read and written. 312 0 18.2 D/A Converter Registers ■ D/A control registers (DACR0 and DACR1) Figure 18.2-2 "D/A control registers (DACR0 and DACR1)" shows the register configuration of D/A control registers (DACR0 and DACR1). Figure 18.2-2 D/A control registers (DACR0 and DACR1) D/A control register 1 Bit Address:00003DH Read/write Initial value 8 15 14 13 12 11 10 9 - - - - - - - (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (R/W) (0) 7 6 5 4 3 2 1 0 - - - - - - (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) DAE1 DACR1 D/A control register 0 Bit Address:00003CH Read/write Initial value DAE0 DACR0 (R/W) (0) [Bits 8 and 0] DAE1 and DAE0 These bits are used to specify whether D/A converter output is enabled or disabled. DAE1 controls channel 1 and DAE0 controls channel 0. Writing 1 to these bits enables D/A output. Setting 0 disables D/A output. These bits are initialized to 0 at reset. These bits can be read and written. 313 CHAPTER 18 D/A CONVERTER 18.3 Operation of D/A Converter To start D/A output, set 1 in the enable bit for the corresponding D/A output channel belonging to the D/A control register (DACR). ■ Operation of D/A converter If D/A output is disabled, the analog switch inserted to the output of each D/A converter channel in series is turned off. In the D/A converter, the bit is cleared to 0 and the direct- current path is shut off. The above is also true in the stop mode. The output voltage of the D/A converter ranges from 0 V to 255/256 x DVR. To change the output voltage range, adjust the DVR voltage externally. The D/A converter output does not have the internal buffer amplifier. The analog switch (= 100 Ω) is inserted to the output in series. To apply load to the output externally, estimate a sufficient stabilising time. Table 18.3-1 "Theoretical values of output voltage of the D/A converter" lists the theoretical values of output voltage of the D/A converter. Table 18.3-1 Theoretical values of output voltage of the D/A converter 314 Value written to DA07 to DA00 and DA17 to DA10 Theoretical value of output voltage 00H 0/256 x DVR (=0 V) 01H 1/256 x DVR 02H 2/256 x DVR : : FDH 253/256 x DVR FEH 254/256 x DVR FFH 255/256 x DVR CHAPTER 19 COMMUNICATION PRESCALER REGISTER This chapter describes the functions and overview of the communication prescaler register. The output of the communication prescaler is used by UART. 19.1 "Overview of Communication Prescaler Register" 19.2 "Operation of Communication Prescaler Register" 315 CHAPTER 19 COMMUNICATION PRESCALER REGISTER 19.1 Overview of Communication Prescaler Register The communication prescaler register (clock division control register) controls the machine clock division. It is designed to assure a constant baud rate for various machine clocks as specified by the user. The output of the communication prescaler is used by the UART. ■ Clock division control register (CDCR) Figure 19.1-1 Clock division control registers [0 to 4] Clock division control registers 0 to 4 Address:00002CH Address:00002EH Address:000034H Address:000087H Address:00008FH Read/write Initial value 15 14 13 12 MD (R/W) (0) (-) (-) (-) (-) (-) (-) 11 10 DIV3 DIV2 9 DIV1 8 DIV0 (R/W) (R/W) (R/W) (R/W) (1) (1) (1) (1) [Bit 15] MD (Machine clock divide moDe select) MD is an operation enable bit of the communication prescaler. Table 19.1-1 Function of MD (Machine clock divide moDe select) Bit MD 316 Function 0 Communication prescaler stops. [Initial value] 1 Communication prescaler operates. Bit No. CDCR0 CDCR1 CDCR2 CDCR3 CDCR4 19.1 Overview of Communication Prescaler Register [Bits 11, 10, 9, 8] DIV3 to DIV 0 (DIVide 3 to 0) DIV3 to DIV0 decide a machine clock dividing ratio. Table 19.1-2 Function of DIV3 to DIV0 Bits DIV3 DIV2 DIV1 DIV0 Dividing ratio 1 1 1 1 Do not use [Initial value] 1 1 1 0 Divide by 2 1 1 0 1 Divide by 3 1 1 0 0 Divide by 4 1 0 1 1 Divide by 5 1 0 1 0 Divide by 6 1 0 0 1 Divide by 7 1 0 0 0 Divide by 8 Note: • In actual use, set the above bits to something other than 1111B. • When changing the dividing ratio, wait for two cycles as the clock stabilizing time before starting communication. Table 19.1-3 Correspondence between Communication Prescaler and Channels in UART Communication prescaler setting Communication prescaler output CDCR 0 UART 0 CDCR 1 UART 1 CDCR 2 UART 2 CDCR 3 UART 3 CDCR 4 UART 4 317 CHAPTER 19 COMMUNICATION PRESCALER REGISTER 19.2 Operation of Communication Prescaler Register Set the clock division control register as listed in Table 19.2-1 "Operation of Communication Prescaler" depending on the machine clock Φ used. See Chapter 20 "UART" for details. ■ Operation of communication prescaler Table 19.2-1 Operation of Communication Prescaler Machine clock φ div DIV3 DIV2 DIV1 DIV0 φ/div 4 MHz 4 1 1 0 0 1 MHz 6 MHz 6 1 0 1 0 8 MHz 8 1 0 0 0 6 MHz 3 1 1 0 1 8 MHz 4 1 1 0 0 10 MHz 5 1 0 1 1 12 MHz 6 1 0 1 0 14 MHz 7 1 0 0 1 16 MHz 8 1 0 0 0 8 MHz 2 1 1 1 0 12MHz 3 1 1 0 1 16MHz 4 1 1 0 0 2 MHz 4 MHz Confirm that φ divided by div does not exceed 4.25 MHz if setting a machine clock and div different than the above. 318 CHAPTER 20 UART This chapter describes the UART functions and operations. 20.1 "Overview of UART" 20.2 "UART Block Diagram" 20.3 "UART Registers" 20.4 "UART Operations" 20.5 "Application of UART (During Operation in Mode 1)" 319 CHAPTER 20 UART 20.1 Overview of UART The UART is a serial I/O port for asynchronous (start-stop synchronous) communication or CLK-synchronous communication. ■ Features of UART The UART has the following features: • Full duplex double buffer • Asynchronous (start-stop synchronous) communication and CLK-synchronous communication • Support of multiprocessor • Built-in dedicated baud rate generator Table 20.1-1 Baud Rate Operation Baud rate (*) Asynchronous 31250/9615/4808/2404/1202 bps CLK-synchronous 2 M/1 M/500 K/250 K/125 K/62.5 Kbps *: Values when internal machine clocks are 6, 8, 10, 12 and 16 MHz. 320 • Free baud rate setting by external clocks • Error detection function (parity, framing, and overrun) • Transfer signal of HRz code 20.2 UART Block Diagram 20.2 UART Block Diagram Figure 20.2-1 "UART Block Diagram" shows a UART block diagram. ■ UART Block Diagram Figure 20.2-1 UART Block Diagram Control signal Receiver interrupt (to CPU) Special baud rate generator 16-bit reload timer channels 0 to 2 SCK0/4 Clock selection circuit Transmitter clock Transmitter interrupt (to CPU) Receiver clock External clock SIN0/4 Receiver control circuit Transmitter control circuit Start bit detection circuit Transmitter start circuit Received bit counter Transmitted bit counter Received parity counter Transmitted parity counter SOT0/4 Receiver state decision circuit Receiver shifter Transmitter shifter End of reception Start of transmission SIDR0 to 4 SODR0 to 4 Receive error signal for EI2OS (to CPU) F2MC-16LX BUS SMR registers 0 to 4 MD1 MD0 CS2 CS1 CS0 SCKE SOE SCR registers 0 to 4 PEN P SBL CL A/D REC RXE TXE SSR registers 0 to 4 PE ORE FRE RDRF TDRE RIE TIE Control signal 321 CHAPTER 20 UART 20.3 UART Registers The following four types of UART registers are available: • Serial mode register • Serial control register • Serial input register/serial output register • Serial status register ■ UART Registers Figure 20.3-1 UART Registers Serial mode register Address:000020H Address:000024H Address:000028H Address:000082H Address:000088H Read/write Initial value Serial control register Address:000021H Address:000025H Address:000029H Address:000083H Address:000089H Read/write Initial value 7 6 5 MD1 MD0 4 CS2 3 CS1 2 CS0 1 Reserved 0 SCKE SOE Bit No. SMR0 to 4 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) 15 14 13 12 11 10 9 PEN P SBL CL A/D REC RXE (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) 8 TXE Bit No. SCR0 to 4 (R/W) (R/W) (R/W) (1) (0) (0) Serial input register/serial output register Address:000022H Address:000026H Address:00002AH Address:000084H Address:00008AH Read/write Initial value Serial status register Address:000023H Address:000027H Address:00002BH Address:000085H Address:00008BH Read/write Initial value 322 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Bit No. SIDR0 to 4 (read) SODR0 to 4 (write) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) 15 14 13 PE ORE FRE (R) (0) (R) (0) (R) (0) 12 11 10 RDRF TDRE (R) (0) (R) (1) 9 RIE (-) (-) 8 TIE (R/W) (R/W) (0) (0) Bit No. SSR0 to 4 20.3 UART Registers 20.3.1 Serial Mode Register (SMR0 to 4) The SMR0 to 4 register specifies a UART operating mode. Set an operating mode when the register is stopping. Do not write anything to the register during operation. ■ Serial Mode Register (SMR0 to 4) Figure 20.3-2 Configuration of Serial Mode Register (SMR) Serial mode register Address:000020H Address:000024H Address:000028H Address:000082H Address:000088H Read/write Initial value 7 6 MD1 MD0 5 CS2 4 CS1 3 2 CS0 Reserved 1 SCKE 0 SOE Bit No. SMR0 to 4 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) [Bits 7 and 6] MD1 and MD0 (MoDe select) MD1 and MD0 bits select a UART operating mode. Table 20.3-1 MD0 and MD1 (Operating Mode Selecting Bits) MD1 MD0 Mode Operating mode 0 0 0 Asynchronous normal mode [Initial value] 0 1 1 Asynchronous multiprocessor mode 1 0 2 CLK-asynchronous mode 1 1 - Do not use Note: The synchronous mode (multiprocessor) of mode 1 is a mode in which multiple slave CPUs are connected to one host CPU. The peripherals are not capable of identifying a receiver data format. Therefore, only the master multiprocessor mode is supported. Also, the parity check function is not available, so set the PEN of the SCR register to 0. [Bits 5 to 3] CS2, CS1, and CS0 (Clock Select) CS2 to CS0 bits select a baud rate clock source. If the communication prescaler is selected, a baud rate is also determined simultaneously. 323 CHAPTER 20 UART Table 20.3-2 CS0 to CS2 (Baud Rate Clock Source Selecting Bits) CS2 CS1 CS0 000B to 100B Clock input Special baud rate generator 1 0 1 Reserved 1 1 0 Internal timer (16-bit reload timer 0) 1 1 1 External clock Note: If the internal timer is selected, the MB90580C series selects three 16-bit reload timers. The UART channels and reload timer channels are as follows: - UART 0ch: Reload timer 0ch - UART 1ch: Reload timer 1ch - UART 2ch: Reload timer 2ch - UART 3ch: Reload timer 0ch - UART 4ch: Reload timer 1ch [Bit 2] Reserved Bit 2 is a reserved bit. Set the bit to 0. [Bit 1] SCKE (SCIK Enable) The SCKE bit specifies whether to use the SCK terminal as a clock input terminal or clock output terminal when communicating in the CLK-synchronous mode (mode 2). Table 20.3-3 Function of SCKE (SCLK Enable) Bit SCKE Function 0 Uses the SCK terminal as a clock input terminal. [Initial value] 1 Uses the SCK terminal as a clock output terminal. Note: An external clock source must be used when the SCK terminal is used as a clock input terminal. The UART channels correspond to the serial clock I/O terminals as follows: - UART 0ch: SCK0 terminal - UART 1ch: SCK1 terminal - UART 2ch: SCK2 terminal - UART 3ch: SCK3 terminal - UART 4ch: SCK4 terminal 324 20.3 UART Registers [Bit 0] SOE (Serial Output Enable) The SOE bit specifies whether the external terminal is used as a serial output terminal (SOT) or an I/O port terminal. Table 20.3-4 Function of SOE (Serial Output Enable) Bit SOE Function 0 Uses the external terminal as a general-purpose I/O port terminal. [Initial value] 1 Uses the external terminal as a serial data output terminal (SOT). Note: The UART channels correspond to the serial data output terminals as follows: - UART 0ch: SOT0 terminal - UART 1ch: SOT1 terminal - UART 2ch: SOT2 terminal - UART 3ch: SOT3 terminal - UART 4ch: SOT4 terminal 325 CHAPTER 20 UART 20.3.2 Serial Control Register (SCR0 to 4) The serial control register (SCR0 to 4) controls a transfer protocol for serial communication. ■ Serial Control Register (SCR0 to 4) Figure 20.3-3 Configuration of Serial Control Register (SCR) Serial control register Address:000021H Address:000025H 15 14 13 12 11 10 9 8 Address:000029H Address:000083H PEN P SBL CL A/D REC RXE TXE Address:000089H Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (1) (0) (0) Bit No. SCR0 to 4 [Bit 15] PEN (Parity Enable) The PEN bit specifies whether to add a parity bit when establishing serial data communication. Table 20.3-5 Function of PEN (Parity Enable) Bit PEN Function 0 No parity [Initial value] 1 Parity Note: A parity bit can be added only in the normal mode (mode 0) of asynchronous (start-stop synchronous) communication modes, not in multiprocessor mode (mode 1) and CLKsynchronous communication mode (mode 2). [Bit 14] P (Parity) The P bit specifies even or odd parity when adding a parity bit for data communication. Table 20.3-6 P (Event/Odd Parity Specification Bit) P Function 0 Even parity [Initial value] 1 Odd parity [Bit 13] SBL (Stop Bit Length) The SBL bit specifies the length of a stop bit, which is a frame end mark used in asynchronous communication. 326 20.3 UART Registers Table 20.3-7 SBL (Stop Bit Length Specification Bit) SBL Function 0 1 stop bit [Initial value] 1 2 stop bits [Bit 12] CL (Character Length) The CL bit specifies the data length of each frame to be transmitted or received. Table 20.3-8 CL (Transmitter or Receiver Data Length Specification Bit) CL Function 0 7-bit data [Initial value] 1 8-bit data Note: 7-bit data can only be processed in the normal synchronous communication mode (mode 0). In multiprocessor mode (mode 1) or CLK-synchronous communication mode (mode 2), specify 8-bit data. [Bit 11] A/D (Address/Data) The A/D bit specifies a data format of a frame to be transmitted in the multiprocessor mode (mode 1) of asynchronous communication modes. Table 20.3-9 Function of A/D (Address/Data) Bit A/D Function 0 Data frame [Initial value] 1 Address frame [Bit 10] REC (Receiver Error Clear) Writing 0 to this bit clears the error flags (PE, ORE, and FRE) of the SSR register. Writing 1 is invalid. The read value is always 1. [Bit 9] RXE (Receiver Enable) The RXE bit controls a UART receive operation. Table 20.3-10 Function of RXE (Receiver Enable) Bit RXE Function 0 Disables a receive operation. [Initial value] 1 Enables a receive operation. Note: If the RXE is set to 0 during the receive operation (while inputting data into the receiver shift register), the receive operation is stopped when the receiving of the frame is completed and the receiver data is stored in the receiver data buffer SIDR register. 327 CHAPTER 20 UART [Bit 8] TXE (Transmitter Enable) The TXE bit controls a UART transmit operation. Table 20.3-11 Function of TXE (Transmitter Enable) Bit TXE Function 0 Disables a transmit operation. [Initial value] 1 Enables a transmit operation. Note: If the TXE is set to 0 during the transmit operation (while outputting data from the transmit register), the transmit operation is stopped after all data is output from the transmitter data buffer SODR register. 328 20.3 UART Registers 20.3.3 Serial Input Data Register (SIDR0 to 4) and Serial Output Data Register (SODR0 to 4) The serial input data register (SIDR0 to 4) and serial output data register (SODR0 to 4) are receiver and transmitter data buffer registers. ■ Configuration of Serial Input Data Register (SIDR0 to 4) and Serial Output Data Register (SODR0 to 4) If SIDR or SODR data is 7 bits long, the high-order 1 bit (D7) becomes invalid. Write data into the SODR register when the TDRE of the SSR register is 1. Figure 20.3-4 Configuration of Serial Input Data Register (SIDR0 to 4) and Serial Output Data Register (SODR0 to 4) Serial input register/serial output register Address:000022H Address:000026H Address:00002AH Address:000084H Address:00008AH Read/write Initial value 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Bit No. SIDR0 to 4 (read) SODR0 to 4 (write) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) Note: Writing data at this address means writing data into the SODR register; reading data at this address means reading data from the SIDR register. 329 CHAPTER 20 UART 20.3.4 Serial Status Register (SSR0 to 4) The serial status register (SSR0 to 4) is comprised of flags that represent the UART operating status. ■ Serial Status Register (SSR0 to 4) Figure 20.3-5 Configuration of Serial Status Register (SSR0 to 4) Serial status register Address:000023H Address:000027H Address:00002BH Address:000085H Address:00008BH Read/write Initial value 15 14 13 PE ORE FRE (R) (0) (R) (0) (R) (0) 12 11 10 RDRF TDRE (R) (0) 9 RIE (R) (1) (-) (-) 8 TIE Bit No. SSR0 to 4 (R/W) (R/W) (0) (0) [Bit 15] PE (Parity Error) The PE bit is an interrupt request flag that is set when a parity error occurs during the receive operation. To clear the flag set once, write 0 into the REC bit (bit 10) of the SCR register. If the bit is set, data in the SIDR register becomes invalid. Table 20.3-12 Function of PE (Parity Error) Bit PE Function 0 No parity error [Initial value] 1 Parity error occurs. [Bit 14] ORE (Over Run Error) The ORE bit is an interrupt request flag that is set when an overrun error occurs during the receive operation. To clear the flag set once, write 0 into the REC bit (bit 10) of the SCR register. If the bit is set, data in the SIDR register becomes invalid. Table 20.3-13 Function of ORE (Over Run Error) ORE Function 0 No overrun error [Initial value] 1 Overrun error occurs. [Bit 13] FRE (FRaming Error) The FRE bit is an interrupt request flag that is set when a framing error occurs during the receive operation. To clear the flag set once, write 0 into the REC bit (bit 10) of the SCR register. If the bit is set, data in the SIDR register becomes invalid. 330 20.3 UART Registers Table 20.3-14 Function of FRE (FRaming Error) FRE Function 0 No framing error [Initial value] 1 Framing error occurs. [Bit 12] RDRF (Receiver Data Register Full) The RDRF bit is an interrupt request flag indicating that the SIDR register is full with receiver data. The bit is set when receiver data is loaded into the SIDR register and automatically cleared when the data is read from the SIDR register. Table 20.3-15 Function of RDRF (Receiver Data Register Full) SIDR Function 0 Register is not full with receiver data. [Initial value] 1 Register is full with receiver data. [Bit 11] TDRE (Transmitter Data Register Empty) The TDRE bit is an interrupt request flag indicating that transmitter data can be written into the SODR register. Once the data is written into the SODR register, the bit is cleared. When the written data is loaded into the transmitter shifter and transfer is started, the bit is set again, indicating the next transmitter data can be written. Table 20.3-16 Function of TDRE (Transmitter Data Register Empty) TDRE Function 0 Transmitter data cannot be written. 1 Transmitter data can be written. [Initial value] [Bit 10] Empty bit [Bit 9] RIE (Receiver Interrupt Enable) The RIE bit controls a receiver interrupt. Table 20.3-17 Function of RIE (Receiver Interrupt Enable) RIE Function 0 Disables an interrupt. [Initial value] 1 Enables an interrupt. Note: Receiver interrupt sources include the occurrence of a PF, ORE, or FRE error and normal reception by RDRF. 331 CHAPTER 20 UART [Bit 8] TIE (Transmitter Interrupt Enable) The TIE bit controls a transmitter interrupt. Table 20.3-18 Function of TIE (Transmitter Interrupt Enable) TIE Function 0 Disables an interrupt. [Initial value] 1 Enables an interrupt. Note: Transmitter interrupt sources include a request to transmit by TDRE. 332 20.4 UART Operations 20.4 UART Operations The UART has operating modes as shown in Table 20.4-1 "UART Operating Modes" that can be switched by setting a value into the SMR and SCR registers. ■ UART Operations Table 20.4-1 UART Operating Modes Mode Parity Data length 0 Yes/No 7 Yes/No 8 1 No 8+1 2 No 8 Operating mode Stop bit length Asynchronous normal mode 1 or 2 bits Asynchronous (start-stop synchronous) multiprocessor mode CLK-synchronous mode - Note: The stop bit length in asynchronous (start-stop synchronous) mode can be specified only for a transmit operation. A receive operation is always 1 bit long. The UART cannot operate in any mode other than the above. Do not attempt a setting. In the CLK-synchronous mode, start and stop bits are added to the data byte. Set a communication mode while the UART is stopping; otherwise, data received or transmitted during the mode setting cannot be guaranteed. ■ Extended Intelligent I/O Services (EI2OS) For EI2OS, see Section 3.6 " Expanded Intelligent I/O Service (EI2OS)". 333 CHAPTER 20 UART 20.4.1 UART Clock Selection The following three kinds of UART clocks can be selected: • Special baud rate generator • Internal timer • External clock ■ Communication Prescaler Table 20.4-2 "Baud Rates (Asynchronous (Start-Stop Synchronous) Mode)" and Table 20.4-3 "Baud Rates (CLK-synchronous Mode)" list the baud rates when the special baud rate generator is selected. See Chapter 19 "COMMUNICATION PRESCALER REGISTER" for details on the formula in the tables. Table 20.4-2 Baud Rates (Asynchronous (Start-Stop Synchronous) Mode) CS2 CS1 CS0 φ/div = 2 MHz φ/div = 4 MHz 0 0 0 9615 bps 19230 bps (φ/div)/(8 x 13 x 2) 0 0 1 4808 bps 9615 bps (φ/div)/(8 x 13 x 22) 0 1 0 2404 bps 4808 bps (φ/div)/(8 x 13 x 23) 0 1 1 1202 bps 2404 bps (φ/div)/(8 x 13 x 24) 1 0 0 31250 bps 62500 bps (φ/div)/ 26 φ: Machine clock Expression for calculation div: Setting of communication prescaler Table 20.4-3 Baud Rates (CLK-synchronous Mode) CS2 CS1 CS0 φ/div = 2 MHz φ/div = 4 MHz 0 0 0 1 Mbps 2 Mbps (φ/div)/2 0 0 1 500 Kbps 1 Mbps (φ/div)/22 0 1 0 250 Kbps 500 Kbps (φ/div)/23 0 1 1 125 Kbps 250 Kbps (φ/div)/ 24 1 0 0 62.5 Kbps 125 Kbps (φ/div)/ 25 φ: Machine clock Expression for calculation div: Setting of communication prescaler ■ Internal timer If the internal timer is selected by setting CS2 to CS0 bits of the SMR register to 110B, the 16-bit timer (timer 0 to 2) is operated in reload mode. The expressions for calculating a baud rate at this time are as follows: Asynchronous (start-stop synchronous) CLK-synchronous 334 (φ/N) / (16 x 2 x (n + 1)) (φ/N) / (2 x (n + 1)) 20.4 UART Operations ❍ φ: Machine clock φ indicates the internal operation frequency of the microcomputer. See Section 5.7 "Switching Machine Clock" for details. ❍ N N indicates the dividing ratio of the count clock source (TMCSR: CSL1 and CSL0) of the internal 16-bit reload timer. Example: N = 8 when CSL1 and CSL0 = '01B' See Section 13.2.1 "Timer control status register (TMCSR)" for details. ❍ n n indicates the reload value of the internal 16-bit reload timer. Table 20.4-4 "Baud Rates and Reload Values" lists the relationship between a baud rate and reload value (decimal) when the machine clock is taken as 7.3728 MHz. Table 20.4-4 Baud Rates and Reload Values Baud rate Reload value Asynchronous N=2 (Machine clock divided by 2) N = 23 (Machine clock divided by 8) 38400 2 - 19200 5 - 9600 11 2 4800 23 5 2400 47 11 1200 95 23 600 191 47 300 383 95 If the internal timer (16-bit reload timers 0 to 2) is selected as a baud rate clock source, the outputs (TOT0 to TOT2) of 16-bit reload timers 0 to 2 have already been connected inside this controller. Therefore, external terminals TOT0 to TOT2 of 16-bit reload timers 0 to 2 do not have to be externally connected to external clock input terminals (SCK0 to SCK4) of UART. The output terminal of 16-bit reload timers 0 to 2 can also be used as an I/O port terminal unless otherwise used. ■ External Clock If the external clock is selected by setting CS2 to CS0 bits of the SMR register to 111B, the baud rates are as follows on the assumption that the frequency is f: Asynchronous (start-stop synchronous): f/16 CLK-synchronous: f However, f is up to 2 MHz. 335 CHAPTER 20 UART 20.4.2 Asynchronous (Start-stop Synchronous) Mode In the asynchronous (start-stop synchronous) mode, transfer data always begins with a start bit (L level data) and ends with a stop bit (H level data). The receiver operation is controlled by the SCR register, and the transmitter operation is controlled by the SODR register. ■ Transfer Data Format The UART handles only data of a NRZ (non return to zero) format. Figure 20.4-1 "Transfer Data Format (Modes 0 and 1)" shows the transfer data format. Figure 20.4-1 Transfer Data Format (Modes 0 and 1) SIN ,SOT 0 Start 1 0 LSB 1 1 0 0 1 0 1 1 MSB Stop A/D Stop (Mode 0) (Mode 1) Transferred data is 01001101B. Transfer data always begins with a start bit (L level data), is transmitted in the data bit length specified by the LSB first and ends with a stop bit (H level data). If the external clock is selected, always enter a clock. In the normal mode (mode 0), the data length can be set to 7 or 8 bits. In the multiprocessor mode (mode 1), however, the data length must be set to 8 bits. Also, no parity bit can be added in the multiprocessor mode. Instead, an A/D bit is always added to data. ■ Receiver Operation If the RXE bit (bit 9) of the SCR register is 1, a receiver operation is always performed. Once a start bit is detected, one-frame data is received according to the data format specified by that register. If an error occurs at the end of one-frame data reception, an error flag is set and the RDRF flag (bit 12) of the SSR register is then set. If the RIE bit (bit 9) of the SSR register is set to 1 simultaneously, a receiver interrupt occurs to the CPU. The flags of the SSR register are checked. If the receiver is normal, data is read from the SIDR register; if an error occurs, take corrective actions accordingly. The RDRF flag is cleared by reading data from the SIDR register. ■ Detecting the start bit Implement the following settings to detect the start bit: 336 • Set the communication line level to H (attach the mark level) before the communication period. • Specify reception permission (RXE=H) while the communication line level is H (mark level). • Do not specify reception permission (RXE=H) for periods other than the communication period (without mark level). Otherwise, data is not received correctly. • After the stop bit is detected (the RDRF flag is set to 1), specify reception inhibition (RXE=L) while the communication line level is H (mark level). 20.4 UART Operations Figure 20.4-2 Normal Operation Communication period Non-communication period Mark level Start bit SIN ST Non-communication period Stop bit Data D0 D1 D0 D1 D2 D3 D4 D5 D6 D7 SP (Sending 01010101b) RXE Receive clock Sampling clock Receive clock (8 pulse) Recognition by the microcontroller ST Generating sampling clocks by dividing the receive clock by 16 D2 D3 D4 D5 D6 D7 SP (Receiving 01010101b) Note that specifying reception permission at the timing shown below obstructs the correct recognition of the input data (SIN) by the microcontroller. • Example of operation if reception permission (RXE=H) is specified while the communication line level is L. Figure 20.4-3 Abnormal Operation Communication period Non-communication period Mark level Start bit SIN (Sending 01010101b) RXE Non-communication period Stop bit Data ST D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 SP SP Receive clock Sampling clock Recognition by the microcontroller ST recognition (Receiving 10101010b) PE,ORE,FRE Occurrence of a reception error ■ Transmitter Operation When 1 is set in the TXE bit (bit 8) of the SSR register, transmitter data is written into the SODR register. When 1 is then written to the TXE bit (bit 8) of the SCR register, the data is transmitted. When the data set in the SODR register is loaded into the transmitter shift register and begins to be transmitted, the TDRE flag is set again and the next transmitter data can be set. If the TIE bit (bit 8) of the SSR register is set to 1 at this time, a transmitter interrupt occurs to the CPU to request the SODR register to set transmitter data. The TDRE flag is cleared once when the data is set to the SODR register. 337 CHAPTER 20 UART 20.4.3 CLK-synchronous Mode In the CLK-synchronous mode, a synchronous clock for receiving data is generated automatically if the internal clock is selected. A one-byte clock must be supplied if the external clock is selected. The start of communication is controlled by the SODR register, and the termination of communication is controlled by the SSR register. ■ Transfer Data Format The UART handles only data in NRZ (non return to zero) format. Figure 20.4-4 "Transfer Data Format (Mode 2)" shows the relationship between the transmitter or receiver clock and data. Figure 20.4-4 Transfer Data Format (Mode 2) SODR write Mark SCLK RXE, TXE SIN, SOT 1 0 1 1 0 0 LSB The transferred data is 01001101B 1 0 MSB (Mode 2) If the internal clock (special baud rate generator or internal reload timer) is selected, a synchronous clock for receiving data is automatically generated when data is transmitted. If the external clock is selected, the transmitter data buffer SODR register of the transmitter UART is checked for data (TDRE flag is 0) and then a one-byte clock must be supplied accurately. Set the mark level to H before and after transmission. Only eight-bit data is valid and no parity bit can be added to data. No errors other than overrun errors are detected because neither start bit nor stop bit is provided. 338 20.4 UART Operations ■ Values set in registers in the CLK-synchronous mode The settings of the control registers used in the CLK-synchronous mode are shown below. Table 20.4-5 Settings of Control Registers Used in CLK-synchronous Mode Register name SMR register SCR register SSR register Bit name Setting MD1, MD0 10 CS2, CS1, CS0 Specifies clock input. SCKE 1 for special baud rate generator or internal timer and 0 for external clock SOE 1 for transmit operation and 0 for receive-only operation PEN 0 P, SBL, A/D Invalid CL 1 REC 0 (for initialization) RXE, TXE Set at least either of the bits to 1. RIE 1 if using an interrupt; otherwise, 0. TIE 0 ■ Start of Communication Communication is started by writing data into the SODR register. Even in the case of a receiveonly operation, it is always necessary to write temporary transmitter data into the SODR register. ■ End of Communication The end of communication can be confirmed by the fact that the RDRF flag of the SSR register is changed to 1. Check the ORE bit of the SSR register to see if communication has been completed normally. 339 CHAPTER 20 UART 20.4.4 Occurrence of Interrupt and Flag Setting Timing The UART has five flags and two interrupt sources. The five flags are PE, ORE, FRE, RDRF, and TDRE. One of the two interrupt sources is for the receiver, and the other is for the transmitter. ■ Five Flags (PE, ORE, FRE, RDRF, and TDRE) and Two Interrupt Sources ❍ PE (Parity error), ORE (Over run error), FRE (Framing error) The PE, ORE, and FRE flags are set when a relevant error occurs during transmission, and cleared when 0 is written to the REC bit of the SCR register. ❍ RDRF This flag is set when receiver data is loaded into the SIDR register, and cleared when data is read from the SIDR register. However, mode 1 is not provided with a parity detection function, and mode 2 is not provided with a parity detection function and a framing error detection function. ❍ TDRE This flag is set when the SODR register is empty and ready to write data, and cleared when data is written into the SODR register. The two interrupt sources are for both receiver and transmitter. During the receive operation, PE, ORE, FRE, or RDRF issues an interrupt request; during the transmit operation, TDRE issues an interrupt request. ■ Interrupt Flag Setting Timing in Operating Modes ❍ During receiver operation in mode 0 The PE, ORE, FRE, or RDRF flag is set when receive transfer is finished and the last stop bit is detected, and an interrupt request to the CPU occurs. When the PE, ORE, or FRE is active, data in the SIDR register becomes invalid. Figure 20.4-5 ORE, FRE, and RDRF Setting Timing (Mode 0) Data PE,ORE,FRE RDRF Receiver interrupt 340 D6 D7 Stop 20.4 UART Operations ❍ During receiver operation in mode 1 The ORE, FRE, or RDRF is set when receive transfer is finished and the last stop bit is detected, and an interrupt request to the CPU occurs. Because of receivable data length of 8 bits, the last 9th bit data indicating an address or data becomes invalid. When the ORE or FRE is active, data in the SIDR register becomes invalid. Figure 20.4-6 ORE, FRE, and RDRF Setting Timing (Mode 1) Data D7 Address/data Stop ORE,FRE RDRF Receiver interrupt ❍ During receiver operation in mode 2 The ORE or RDRF is set when receive transfer is finished and the last data (D7) is detected, and an interrupt request to the CPU occurs. When the ORE is active, data in the SIDR register becomes invalid. Figure 20.4-7 ORE and RDRF Setting Timing (Mode 2) Data D5 D6 D7 ORE RDRF Receiver interrupt ❍ During transmitter operation in modes 0, 1, and 2 The TDRE is cleared when data is written into the SODR register, and set when the data is transferred to the internal shift register and the UART gets ready to write the next data. And an interrupt request to the CPU occurs. When 0 is written into the TXE of the SCR register during the transmitter operation (including RXE in mode 2), the TDRE of the SSR register is set to 1, the transmitter shifter stops and the UART transmitter operation is then disabled. After 0 is written into the TXE of the SCR register during the transmitter operation (including RXE in mode 2), the data written into the SODR register is transmitted before the transmitter stops. 341 CHAPTER 20 UART Figure 20.4-8 TDRE Setting Timing (Modes 0 and 1) Write into SODR TDRE Requests an interrupt to CPU. SOT0 interrupt SOT0 output ST D0 ST: Start bit D1 D2 D3 D0 to D7: Data bit D4 D5 D6 SP: Stop bit D7 SP SP A/D ST D0 D1 D2 D3 AD: Address/data multiplexer Figure 20.4-9 TDRE Setting Timing (mode 2) Write into SODR TDRE Requests an interrupt to CPU. SOT0 interrupt SOT0 output D0 D1 D2 D3 D0 to D7: Data bit 342 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 20.5 Application of UART (During Operation in Mode 1) 20.5 Application of UART (During Operation in Mode 1) Mode 1 is used if multiple slave CPUs are connected to one host CPU. This UART only supports the host communication interface (see Figure 20.5-1 "Example of System Configuration in Mode 1"). ■ Application of UART (During Operation in Mode 1) Figure 20.5-1 Example of System Configuration in Mode 1 SO SI Host CPU SO SI SO SI Slave CPU#0 Slave CPU#1 As shown in Figure 20.5-2 "Communication Flowchart in Mode 1" communication begins once the host CPU transfers address data. The address data means the data when the A/D of the SCR register is 1. This allows one of the slave CPUs to be selected as the receiver for communication with the host CPU. Normally, the data when the A/D of the SCR register is 0 is used. In this mode, the parity check function is not available. Therefore, set the PEN bit of the SCR register to 0. 343 CHAPTER 20 UART Figure 20.5-2 Communication Flowchart in Mode 1 (Host CPU) START Set transfer mode to 1 Set slave CPU selecting data to D0 to D7, and A/D to 1. Then transfer 1 byte. Set A/D to 0 Enable receiver operation Communicate with slave CPU Is communication ended? No Yes Is communication with other slave CPUs established? No Yes Disable receiver operation END 344 CHAPTER 21 IEBusTM CONTROLLER This chapter describes the functions and operation of the IEBusTM controller. Note that the MB90587C/CA model does not have the IEBusTM controller. 21.1 "Overview of IEBusTM Controller" 21.2 "Block Diagram for IIEBusTM Controller" 21.3 "Registers of IEBusTM Controller" 21.4 "IEBusTM Transmission Control" 21.5 "IEBusTM Reception Control" 21.6 "Communication Control Status" 21.7 "Examples of the Flows of Main and Interrupt Processing Routines for IEBusTM Controller" 21.8 "IEBusTM Controller Operation at Transmission" 21.9 "IEBusTM Protocol Operation" 21.10 "Transmission Protocol" 21.11 "Transmission Data" 21.12 "Bit Format" 345 CHAPTER 21 IEBusTM CONTROLLER 21.1 Overview of IEBusTM Controller The Inter-Equipment Bus (IEBusTM) is a small-scale two-wire serial bus interface designed for data transmission between different equipment. IEBusTM is used, for example, as the bus interface for controlling car-mounted equipment. ■ Features of IEBusTM Controller ❍ Multi-master mode All the units connected to IEBusTM can transmit data to each other. ❍ Broadcast function (communication between one unit and multiple units) Group broadcast: Broadcast to a group of units General broadcast: Broadcast to all other units ❍ Selection from three modes using different transmission speeds Internal frequency of IEBusTM 6 MHz 6.29 MHz Mode 0 About 3.9 kbps About 4.1 kbps Mode 1 About 17 kbps About 18 kbps Mode 2 About 26 kbps About 27 kbps ❍ Transmission data buffer 8-byte FIFO ❍ Reception data buffer 8-byte FIFO ❍ Internal operating frequency of CPU (12 MHz or 12.58 MHz) ❍ Frequency accuracy In mode 0 or 1: plus or minus 1.5% In mode 2: plus or minus 0.5% 346 21.2 Block Diagram for IEBusTM Controller 21.2 Block Diagram for IEBusTM Controller Figure 21.2-1 "Block Diagram for IEBusTM Controller" is a block diagram for the IEBusTM controller. ■ Block Diagram for IEBusTM Controller Figure 21.2-1 Block Diagram for IEBusTM Controller Local address set registers Slave address set registers Broadcast control bit set register Master address read registers Broadcast control bit set register Control circuit Text bit read register Lock read registers Read data buffer (8-byte FIFO) Command registers IEBus TM protocol controller Write data buffer (8-byte FIFO) 2 F MC-16LX internal bus Text length bit set register TX RX Status registers Interrupt request signals (transmission and reception) 2 Internal clock (12 or 12.58 MHz) Prescaler 6 MHz/6.29 MHz IEBusTM controller The control circuit of the IEBusTM controller performs the following operations: • Controlling the number of bytes of transmission and reception data • Controlling the maximum number of transmission bytes • Detecting arbitration results • Determining whether to return the acknowledgment of each field • Generating interrupt signals 347 CHAPTER 21 IEBusTM CONTROLLER 21.3 Registers of IEBusTM Controller The IEBusTM controller has the following 18 registers: • Local address set registers H and L • Slave address set registers H and L • Broadcast control bit set register • Broadcast control bit read register • Text length bit set register • Text bit read register • Command registers H and L • Status registers H and L • Lock read registers H and L • Master address read registers H and L • Read data buffer • Write data buffer ■ Registers of IEBusTM Controller Bit Address:000071H Read/write Initial value Bit Address:000070H Read/write Initial value Bit Address:000073H Read/write Initial value Bit Address:000072H Read/write Initial value Bit Address:000075H Read/write Initial value Bit Address:00007FH Read/write Initial value 348 15 14 13 12 11 10 9 8 MA11 MA10 MA09 MA08 Local address set register H (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) MAWH X X X X X X X X Reserved Reserved Reserved Reserved 7 6 5 4 3 2 1 0 MA07 MA06 MA05 MA04 MA03 MA02 MA01 MA00 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) X X X X X X X X 15 14 13 11 10 9 8 SA11 SA10 SA09 SA08 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) X X X X X X X X 7 6 5 4 3 2 1 0 SA07 SA06 SA05 SA04 SA03 SA02 SA01 SA00 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) X X X X X X X X 15 14 13 12 11 10 9 8 C3 C2 C1 C0 DO3 DO2 DO1 DO0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 0 0 0 0 0 0 0 0 14 DO1 (R) 0 13 DO2 (R) 0 MAWL 12 Reserved Reserved Reserved Reserved 15 DO3 (R) 0 Local address set register L 12 DO0 (R) X 11 C3 (R) X 10 C2 (R) X 9 C1 (R) X 8 C0 (R) X Slave address set register H SAWH Slave address set register L SAWL Broadcast control bit set register DCWR Broadcast control bit read register DCRR 21.3 Registers of IEBusTM Controller Bit Address:000074H Read/write Initial value 7 6 5 4 3 2 1 0 DE7 DE6 DE5 DE4 DE3 DE2 DE1 DE0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 0 0 0 0 0 0 0 0 7 DE7 (R) X 6 DE6 (R) X 5 DE5 (R) X 4 DE4 (R) X Bit 15 14 13 12 11 Address:000077H MD1 MD0 PCOM RIE TIE Read/write Initial value (R/W) 0 7 (R/W) 0 6 (R/W) (R/W) 0 0 5 4 (R/W) 0 3 (R/W) (R/W) (R/W) 0 0 X 2 1 0 RXS TXS TIT1 CS1 CS0 Bit (R/W) 1 15 (R/W) 1 14 (R/W) (R/W) 0 0 13 12 (R/W) 0 11 (R/W) (R/W) (R/W) 0 0 0 10 9 8 Address:000079H COM TE PEF ACK RIF TIF TSL EOD (R) 0 7 (R/W) 0 6 (R) X 5 (R) X 4 (R/W) 0 3 (R/W) 0 2 (R) 0 1 (R) 0 0 STRH ST3 ST2 ST1 ST0 Status register L STRL Address:000076H Read/write Initial value Read/write Initial value Bit Address:000078H TIT0 WDBF RDBF WDBE RDBE 2 DE2 (R) X 10 1 DE1 (R) X 0 DE0 (R) X DEWR Bit Address:00007EH Read/write Initial value Bit 3 DE3 (R) X Text length bit set register 9 Text bit read register DERR 8 GOTM GOTS Reserved Command register H RDBC WDBC Command register L Read/write Initial value (R) 0 (R) 0 (R) 1 (R) 1 (R) X (R) X (R) X (R) X Bit 15 14 13 12 11 10 9 8 Reserved Reserved Reserved LOC LD11 LD10 LD09 LD08 (R) 1 7 (R) 1 6 (R) 1 5 (R/W) 0 4 (R) X 3 (R) X 2 (R) X 1 (R) X 0 LD07 LD06 LD05 LD04 LD03 LD02 LD01 LD00 Read/write Initial value (R) X (R) X (R) X (R) X (R) X (R) X (R) X (R) X Bit 15 14 13 12 11 10 9 8 Address:00007BH Read/write Initial value Bit Address:00007AH Address:00007DH Read/write Initial value Reserved Reserved Reserved Reserved (R) 1 (R) 1 (R) 1 (R) 1 MA11 (R) X MA10 MA09 MA08 (R) X CMRH (R) X (R) X CMRL Status register H Lock read register H LRRH Lock read register L LRRL Master address read register H MARH 349 CHAPTER 21 IEBusTM CONTROLLER Bit Address:00007CH 7 6 MA07 MA06 5 4 3 MA05 MA04 MA03 2 1 0 MA02 MA01 MA00 Master address read register L Read/write Initial value (R) X (R) X (R) X (R) X (R) X (R) X (R) X (R) X Bit 15 14 13 12 11 10 9 8 Address:000081H RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 Read data buffer Read/write Initial value (R) X 7 (R) X 6 (R) X 5 (R) X 4 (R) X 3 (R) X 2 (R) X 1 (R) X 0 RDB Address:000080H WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0 Write data buffer Read/write Initial value (W) X (W) X (W) X (W) X (W) X (W) X (W) X (W) X WDB Bit 350 MARL 21.3 Registers of IEBusTM Controller 21.3.1 Local Address Set Registers (MAWH and HAWL) The local address set registers are used to set the address (12 bits) of the local unit. Set the address of the local unit in these registers before the unit is released from the communication-disabled state. ■ Local Address Set Registers (MAWH and MAWL) Figure 21.3-1 "Local Address Set Registers (MAWH and HAWL)" shows the structures of the local address set registers (MAWH and MAWL). The address set in the MAWH and MAWL is used as the master address when the local unit is the master unit or for comparison with the slave address received when the local unit is in a slave unit. Bits 15 to 12 are reserved and must always be 1. unpredictable. The values read from these bits are Figure 21.3-1 Local Address Set Registers (MAWH and HAWL) Bit Address:000071H Read/write Initial value Bit Address:000070H Read/write Initial value 15 14 13 12 11 10 9 8 MA11 MA10 MA09 MA08 Local address set register H (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) MAWH X X X X X X X X Reserved Reserved Reserved Reserved 7 6 5 4 3 2 1 0 MA07 MA06 MA05 MA04 MA03 MA02 MA01 MA00 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) X X X X X X X X Local address set register L MAWL 351 CHAPTER 21 IEBusTM CONTROLLER 21.3.2 Slave Address Set Registers (SAWH and SAWL) The slave address set registers (SAWH and SAWL) are used to set the slave address (12 bits) of the local unit when it is a slave unit. Set the slave address of the local unit in these registers before the unit is released from the communication-disabled state. ■ Slave Address Set Registers (SAWH and SAWL) Figure 21.3-2 "Slave Address Set Registers (SAWH and SAWL)" shows the structures of the slave address set registers (SAWH and SAWL). Bits 15 to 12 are reserved and must always be 1. unpredictable. The values read from these bits are Figure 21.3-2 Slave Address Set Registers (SAWH and SAWL) Bit Address:000073H Read/write Initial value Bit Address:000072H Read/write Initial value 352 15 14 13 12 11 10 9 8 SA11 SA10 SA09 SA08 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) X X X X X X X X Reserved Reserved Reserved Reserved 7 6 5 4 3 2 1 0 SA07 SA06 SA05 SA04 SA03 SA02 SA01 SA00 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) X X X X X X X X Slave address set register H SAWH Slave address set register L SAWL 21.3 Registers of IEBusTM Controller 21.3.3 Broadcast Control Bit Set Register (DCWR) The broadcast control bit set register (DCWR) is used to select a communication mode from broadcast and normal communication and control reading and data locking. ■ Broadcast Control Bit Set Register (DCWR) Figure 21.3-3 Broadcast Control Bit Set Register (DCWR) Bit Address:000075H Read/write Initial value 15 14 13 12 11 10 9 8 C3 C2 C1 C0 DO3 DO2 DO1 DO0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 0 0 0 0 0 0 0 0 Broadcast control bit set register DCWR [Bits 15 to 12] D03 to D00 The D03, D02, D01, and D00 bits are used to select a communication mode from broadcast and normal communication. Broadcast: 0H (0000B) Normal communication: 8H (1000B) Bits 14 to 12 must always be 0. When these bits are read, the read values are always 0. 353 CHAPTER 21 IEBusTM CONTROLLER [Bits 11 to 8] C3 to C0 The C3, C2, C1, and C0 bits are used to set four control bits. Table 21.3-1 Control bit settings Bit 3*1 Bit 2 Bit 1 Bit 0 Function*2 0H 0 0 0 0 Slave status reading 1H 0 0 0 1 Undefined 2H 0 0 1 0 Undefined 3H 0 0 1 1 Data reading and locking 4H 0 1 0 0 Lock address reading (lower 8 bits) 5H 0 1 0 1 Lock address reading (higher 4 bits) 6H 0 1 1 0 Slave status reading and unlocking 7H 0 1 1 1 Data reading 8H 1 0 0 0 Undefined 9H 1 0 0 1 Undefined AH 1 0 1 0 Command writing and locking BH 1 0 1 1 Data writing and locking CH 1 1 0 0 Undefined DH 1 1 0 1 Undefined EH 1 1 1 0 Command writing FH 1 1 1 1 Data writing *1: The value of bit 3 (MSB) determines the direction of transmission of the text length bits in the text length field and the data in the data field. • When bit 3 is 1, data is transmitted from the master unit to the slave unit. • When bit 3 is 0, data is transmitted from the slave unit to the master unit. *2: 3H, 6H, AH, and BH are the control bit settings for locking and unlocking. If an undefined value 1H, 2H, 8H, 9H, CH, or DH is transmitted, no acknowledgment is returned. 354 21.3 Registers of IEBusTM Controller 21.3.4 Text Length Bit Set Register (DEWR) The text length bit set register (DEWR) is used to specify the number of bytes of transmission data (an 8-bit value). The setting in this register is valid only for transmission. ■ Text Length Bit Set Register (DEWR) Figure 21.3-4 Text Length Bit Set Register (DEWR) Bit Address:000074H Read/write Initial value 7 6 5 4 3 2 1 0 DE7 DE6 DE5 DE4 DE3 DE2 DE1 DE0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 0 0 0 0 0 0 0 0 Text length bit set register DEWR Table 21.3-2 "Settings of the Number of Bytes of Transmission Data" lists the settings of the number of bytes of transmission data. Table 21.3-2 Settings of the Number of Bytes of Transmission Data Number of bytes of transmission data Command parameter 1 byte 1H 2 bytes 2H : : 255 bytes FFH 256 bytes 00H ❍ Slave reception of command parameter If one of the following command parameters is received in the control field when the local unit is a slave unit, the number of bytes of transmission data must always be set to 1 byte: • 0H (slave status reading) • 4H (reading of the lower 8 bits of lock address) • 5H (reading of the higher 4 bits of lock address) • 6H (slave status reading and unlocking ❍ Setting of a value over the maximum number of bytes If a value over the maximum number of bytes of transmission data is set, data is transmitted using multiple frames. If it occurs, set the remaining number of bytes of the data to be transmitted in this register for the second and subsequent transmission operations. For the remaining number of bytes, reference the value of the text length bit read register (DERR). 355 CHAPTER 21 IEBusTM CONTROLLER 21.3.5 Command Register (Higher 8 Bits) (CMRH) The command register (higher 8 bits) (CMRH) is used to specify the communication mode and control transmission, reception, and interrupts. ■ Command Register (Higher 8 Bits) (CMRH) Figure 21.3-5 Command Register (Higher 8 Bits) (CMRH) Bit 15 14 13 12 11 10 Address:000077H MD1 MD0 PCOM RIE TIE Read/write Initial value (R/W) 0 (R/W) 0 (R/W) (R/W) 0 0 (R/W) 0 9 8 GOTM GOTS Reserved Command register H (R/W) (R/W) (R/W) 0 0 X CMRH [Bits 15 and 14] MD1 and MD0 The MD1 and MD0 bits are used to specify the communication mode. Table 21.3-3 Communication mode settings MD1 MD0 Communication mode 0 0 Mode 0 0 1 Mode 1 1 0 Mode 2 1 1 Setting inhibited [Bit 13] PCOM The PCOM bit enables or disables communication. Writing 1 in this bit sets the COM flag of the status register to 1 and enables communication. Writing 0 in this bit disables communication. Write 1 in this bit when the COM flag of the status register is 0. [Bit 12] RIE The RIE bit enables reception interrupts. - 0: Disables reception interrupts. - 1: Enables reception interrupts. A reception interrupt occurs when: - the 8-byte RDB is full of received data, - data reception has ended normally, - a frame has ended before the data of the number of data bytes specified by the text length bits has been received, or - the local unit has failed in arbitration and has not been selected as a slave unit by the master unit. 356 21.3 Registers of IEBusTM Controller [Bit 11] TIE The TIE bit enables or disables transmission interrupts. - 0: Disables transmission interrupts. - 1: Enables transmission interrupts. A transmission interrupt occurs when: - the local unit has succeeded in arbitration and set a master address in the master address field during master transmission and remained to be the master unit, - the local unit has received, from the master unit, the control bit value requesting data transmission during slave transmission, - the writable area in WDB has reached the number of bytes set in the TIT1 and TIT0 bits of the command register, - transmission of the number of bytes specified by the text length bits has ended within one frame, or - the data of the number of bytes specified by the text length bits has not been transmitted by one frame and transmission has ended. [Bit 10] GOTM The GOTM bit starts master transmission. After communication is enabled, transmission starts when 1 is written in this bit. Only writing of 1 is valid. Writing of 0 in this bit is invalid. When this bit is read, the read value is always 0. [Bit 9] GOTS The GOTS bit starts slave transmission. To transmit data when the local unit is a slave unit, write 1 in this bit after communication is enabled. Only writing of 1 is valid. Writing of 0 in this bit is invalid. When this bit is read, the read value is always 0. Relationships between the settings of GOTM and GOTS bits are as follows: Table 21.3-4 Settings of GOTM and GOTS bits GOTM GOTS Arbitration Slave transmission Operation 0 0 None Disabled Only reception is possible slave reception. 0 1 None Enabled Slave transmission is possible. The local unit cannot be the master. 1 0 To be done Disabled The local unit can perform only reception if it has failed in arbitration and become a slave. 1 1 To be done Enabled The local unit can perform transmission even if it has failed in arbitration and become a slave. [Bit 8] Reserved Bit 8 is reserved. This bit must always be 1. When this bit is read, the read value is unpredictable. 357 CHAPTER 21 IEBusTM CONTROLLER 21.3.6 Command Register (Lower 8 Bits) (CMRL) The command register (lower 8 bits) (CMRL) is used to set positive or negative logic, interrupt, and internal frequency. ■ Command Register (Lower 8 Bits) (CMRL) Figure 21.3-6 Command Register (Lower 8 Bits) (CMRL) Bit Address:000076H Read/write Initial value 7 6 5 4 3 2 1 0 RXS TXS TIT1 TIT0 CS1 CS0 (R/W) 1 (R/W) 1 (R/W) (R/W) 0 0 (R/W) 0 (R/W) (R/W) (R/W) 0 0 0 RDBC WDBC Command register L CMRL [Bit 7] RXS The RXS bit is used to specify the input polarity of the RX1 pin. Select a polarity according to the specifications of the external driver or receiver to be connected. Table 21.3-5 Specification of RX1 pin polarity RXS RX1 input 0 Positive logic input to RX1 • Logic "1": High level • Logic "0": Low level 1 Negative logic input to RX1 • Logic "1": Low level • Logic "0": High level [Bit 6] TXS The TXS bit is used to specify the output polarity of TX1 pin. Select a polarity according to the specifications of the external driver or receiver to be connected. Table 21.3-6 Specification of TX1 pin polarity TXS 358 TX1 output 0 Positive logic output from TX1 • Logic "1": High level • Logic "0": Low level 1 Negative logic output from TX1 • Logic "1": Low level • Logic "0": High level 21.3 Registers of IEBusTM Controller Note: At reset, the MB90580C series outputs an L level signal from the TX1 pin. If the connected driver or receiver uses the positive logic (enabling operation with an L level signal), an error occurs in the communication between other communication units. The error occurs because the L level signal is kept output after reset until the setting of the TXS bit. To avoid such an error, external circuits must be designed so that an H level signal is input to the connected driver or receiver throughout the period from reset to the setting of the TXS bit. [Bits 5 and 4] TIT1 and TIT0 The TIT1 and TIT0 bits are used to specify the timing of the interrupt that can occur when transmission data is written in the write data buffer. Table 21.3-7 Settings of data transmission interrupt timing TIT1 TIT0 Interrupt timing 0 0 When the writable area is 1 byte or more 0 1 When the writable area is 2 bytes or more 1 0 When the writable area is 4 bytes or more 1 1 When the writable area is 8 bytes [Bits 3 and 2] CS1 and CS0 The CS1 and CS0 bits are used to specify the internal operating frequency of CPU and the internal frequency of IEBusTM as shown in Table 21.3-8 "Settings of CS1 and CS0 bits". Write 0 in both the CS1 and CS0 bits. Table 21.3-8 Settings of CS1 and CS0 bits CS1 CS0 Internal operating frequency of CPU φ Internal frequency of IEBusTM φ Calculation formula 0 0 12 MNz (12.58 MHz) 6 MNz (6.29 MHz) φIE=φ/2 0 1 Setting inhibited - - 1 0 Setting inhibited - - 1 1 Setting inhibited - - Note: Use the formula shown above to calculate the internal operating frequency of CPU and the internal frequency of IEBusTM. The internal frequency of CPU must not exceed the operation assurance range. Frequency accuracy must be plus or minus 1.5% for mode 0 or 1 or plus or minus 0.5% for mode 2. [Bit 1] RDBC Writing 1 in the RDBC bit clears the 8-byte RDB to make the RDB blank (RDBE = 1). When this bit is read, the read value is always 0. 359 CHAPTER 21 IEBusTM CONTROLLER [Bit 0] WDBC Writing 1 in the RDBC bit clears the 8-byte WDB to make the WDB blank (WDBE = 1). When this bit is read, the read value is always 0. If this bit is set to 1 for the transmission of the data exceeding the maximum number of transmission bytes, the data written in the WDB in the preceding frame is invalidated and transmission starts with the data written in the current frame. If this bit is set to 0 in the same case and some of the transmission data written in the preceding frame remains, transmission starts with the remaining data. If transmission has ended in the middle because of a timing error or for other reasons, the data being transmitted when the error occurred is not transmitted but the data following that data is transmitted even if this bit is 0. 360 21.3 Registers of IEBusTM Controller 21.3.7 Status Register (Higher 8 Bits) (STRH) The status register (higher 8 bits) (STRH) indicates the communication status, whether an error has occurred, and whether an interrupt request has been generated. ■ Status Register (Higher 8 Bits) (STRH) Figure 21.3-7 Status Register (Higher 8 Bits) (STRH) 15 14 13 12 11 10 9 8 COM TE PEF ACK RIF TIF TSL EOD (R) 0 (R/W) 0 (R) X (R) X (R/W) 0 (R/W) 0 (R) 0 (R) 0 Bit Address:000079H Read/write Initial value Status register H STRH [Bit 5] COM The COM bit is a flag that indicates the communication status. - 0: Communication is disabled. - 1: Communication is enabled. When this flag is 0, it can be set by writing 1 in the PCOM bit that enables communication. This flag is cleared when communication ends. [Bit 14] TE The TE bit is set when a timing error occurs during communication. This bit is cleared by writing 0. Only writing 0 is valid for this bit. [Bit 13] PEF The PEF bit is set when a parity error is detected. If this bit is set on the receiving unit, the receiving unit does not return an acknowledgment. This bit is cleared when communication is enabled. - 0: No parity error is detected. - 1: A parity error is detected. [Bit 12] ACK During one-to-one communication, the data transmitted or received with the acknowledge bit is set in the ACK bit. The ACK bit is cleared when communication is enabled. - 0: Acknowledgment bit is 0. - 1: Acknowledgment bit is 1. In the case of broadcast, the ACK bit is invalid and the value read from the ACK bit is unpredictable. 361 CHAPTER 21 IEBusTM CONTROLLER [Bit 11] RIF The RIF bit is set to 1 when a reception interrupt occurs. - 0: No reception interrupt occurs. - 1: A reception interrupt occurs. This bit is cleared by writing 0 or intelligent I/O service. Only writing 0 is valid for this bit. [Bit 10] TIF The TIF bit is set to 1 when a transmission interrupt occurs. - 0: No transmission interrupt occurs. - 1: A transmission interrupt occurs. This bit is cleared by writing 0 or intelligent I/O service. Only writing 0 is valid for this bit. [Bit 9] TSL The TSL bit is set when a communication frame ends because the maximum number of transmission bytes has been reached in the data field during data transmission or reception. This bit is cleared when transmission of the next communication frame starts. [Bit 8] EOD The EOD bit is set when a communication frame ends because the maximum number of transmission bytes specified by the text length bits has been reached in the data field during data transmission or reception. When the EOD bit is 1, the relevant communication frame has ended normally. This bit is cleared when transmission of the next communication frame starts. 362 21.3 Registers of IEBusTM Controller 21.3.8 Status Register (Lower 8 Bits) (STRL) The status register (lower 8 bits) (STRL) indicates the status of the write data buffer (WDB) and the read data buffer (RDB). It generates the following four communication statuses: • Master or slave transmission • Master reception • Slave reception mode • Broadcast reception ■ Status Register (Lower 8 Bits) (STRL) Figure 21.3-8 Status Register (Lower 8 Bits) (STRL) Bit Address:000078H Read/write Initial value 7 6 5 4 WDBF RDBF WDBE RDBE (R) 0 (R) 0 (R) 1 (R) 1 3 2 1 0 ST3 ST2 ST1 ST0 Status register L (R) X (R) X (R) X (R) X STRL [Bit 7] WDBF The WDBF bit is a flag that indicates the status of the write data buffer (WDB). This bit is set when WDB is full and cleared when data is transmitted and at least one byte of the WDB area becomes writable. - 0: WDB is not full. - 1: WDB is full. [Bit 6] RDBF The WDBF bit is a flag that indicates the status of the read data buffer (RDB). This bit is set when RDB is full of received data and is cleared when data is read and at least one byte of the RDB area becomes writable. - 0: RDB is not full. - 1: RDB is full. [Bit 5] WDBE The WDBE bit is a flag that indicates the status of the write data buffer (WDB). This bit is set when WDB is empty and is cleared when at least one byte is written in WDB. This bit is also set when 1 is written in the WDBC bit of the command register. - 0: WDB is not empty. - 1: WDB is empty. 363 CHAPTER 21 IEBusTM CONTROLLER [Bit 4] RDBE The RDBE bit is a flag that indicates the status of the read data buffer (RDB). This bit is set when data has been read from RDB and RDB is empty and is cleared when at least one byte of received data is written in RDB. This bit is also set when 1 is written in the RDBC bit of the command register. - 0: RDB is not empty. - 1: RDB is empty. [Bits 3 to 0] ST3 to ST0 The ST3, ST2, ST1, and ST0 bits store the status of the communication in progress and cause an interrupt. The current communication status can be known by reading these four bits. Table 21.3-9 Status flag ST 3 ST 2 ST 1 ST 0 0 0 0 0 0 0 0 1 Mode Status Transmission started. Transmission is in progress. Master or slave transmission 0 0 1 0 Transmission ended normally. 0 0 1 1 Transmission stopped in the middle. 0 1 0 0 Master reception is started. 0 1 0 1 RDB is full of the data received by master reception. 0 1 1 0 0 1 1 1 Master reception ended in the middle. 1 0 0 0 Slave reception is started. 1 0 0 1 RDB is full of the data received by slave reception. Master reception Slave reception mode Master reception ended in the middle. 1 0 1 0 Slave reception ended normally. 1 0 1 1 Slave reception ended in the middle. 1 1 0 0 Broadcast reception started. 1 1 0 1 RDB is full of the data received by broadcast. 1 1 1 0 Broadcast reception ended normally. 1 1 1 1 Broadcast reception ended in the middle. Broadcast reception For the timing of the operation of these bits, see Section 21.6 "Communication Control Status". 364 21.3 Registers of IEBusTM Controller 21.3.9 Lock Read Registers (LRRH and LRRL) The lock read registers (LRRH and LRRL) are used to read the lock status of the local unit. ■ Lock Read Registers (LRRH and LRRL) Figure 21.3-9 Lock Read Registers (LRRH and LRRL) Bit Address:00007BH Read/write Initial value Bit Address:00007AH Read/write Initial value 15 14 13 12 11 10 9 8 Reserved Reserved Reserved LOC LD11 LD10 LD09 LD08 (R) 1 7 (R) 1 6 (R) 1 5 (R/W) 0 4 (R) X 3 (R) X 2 (R) X 1 (R) X 0 LD07 LD06 LD05 LD04 LD03 LD02 LD01 LD00 (R) X (R) X (R) X (R) X (R) X (R) X (R) X (R) X Lock read register H LRRH Lock read register L LRRL [Bits 15 to 13] Reserved Bits 15 to 13 are reserved. The values read from these bits are always 1. [Bit 12] LOC The LOC bit indicates the lock status, that is, whether the local unit is locked by another unit. - 0: The local unit is not locked. - 1: The local unit is locked. Writing 0 in this bit unlocks the local unit. Writing 1 in this bit is invalid. [Bits 11 to 0] LD11 to LD00 The LD11 to LD00 bits indicate the address of the unit that locks the local unit. If the local unit is not locked, the contents of these bits are invalid. Note: IEBusTM provides a lock function to enable connected units to communicate over multiple frames. On the other hand, if a unit that has locked another unit fails without unlocking it, the locked unit will not be able to receive data. To prevent this, the system using the lock function must periodically read the lock read register to monitor the lock status. To unlock the local unit, write 0 in the LOC bit. 365 CHAPTER 21 IEBusTM CONTROLLER 21.3.10 Master Address Read Registers (MARH and MARL) The master address read registers (MARH and MARL) indicate the address of the current master unit. ■ Master Address Read Registers (MARH and MARL) Figure 21.3-10 Master Address Read Registers (MARH and MARL) Bit 15 Address:00007DH 13 12 Reserved Reserved Reserved Reserved Read/write Initial value (R) 1 7 Bit Address:00007CH Read/write Initial value 14 (R) 1 6 MA07 MA06 (R) X (R) X (R) 1 5 (R) 1 4 11 MA11 (R) X 3 MA05 MA04 MA03 (R) X (R) X (R) X 10 9 8 MA10 MA09 MA08 (R) X 2 (R) X 1 (R) X 0 MA02 MA01 MA00 (R) X (R) X (R) X Master address read register H MARH Master address read register L MARL [Bits 15 to 12] Reserved Bits 15 to 12 are reserved. The values read from these bits are always 1. [Bits 11 to 0] MA11 to MA00 The MA11 to MA00 bits indicate the address of the current master unit. If the local unit is the master unit, the local address set in the local address set registers is set in these bits. Address data is set in the master address read registers when arbitration in the master address field ends. 366 21.3 Registers of IEBusTM Controller 21.3.11 Broadcast Control Bit Read Register (DCRR) The broadcast control bit read register (DCRR) indicates the broadcast and control bits received from the master unit. ■ Broadcast Control Bit Read Register (DCRR) Figure 21.3-11 Broadcast Control Bit Read Register (DCRR) Bit Address:00007FH Read/write Initial value 15 DO3 (R) 0 14 DO1 (R) 0 13 DO2 (R) 0 12 DO0 (R) X 11 C3 (R) X 10 C2 (R) X 9 C1 (R) X 8 C0 (R) X Broadcast control bit read register DCRR [Bits 15 to 12] DO3 to DO0 The DO3 to DO0 bits indicate the broadcast bits that are received from the master unit when the local unit is a slave unit. If the local unit is the master unit, the DO3 to DO0 bits indicate the data set in the broadcast bits of the broadcast control bit set register. Broadcast bit data is set in DCRR automatically when it is transmitted or received. - For one-to-one communication: 1H (0001B) - For broadcast: 0H (0000B) The values read from D03 to D01 are always "0". [Bits 11 to 8] C3 to C0 The C3 to C0 bits indicate the control bits received from the master unit. If the local unit is the master unit, the C3 to C0 bits indicate the data set in the control bits of the broadcast control bit set register. Control bit data is set when the control field ends and an acknowledgment is detected. See Table 21.3-1 "Control bit settings". 367 CHAPTER 21 IEBusTM CONTROLLER 21.3.12 Text Length Bit Read Register (Lower 8 Bits) (DERR) The text length bit read register (lower 8 bits) (DERR) indicates the number of bytes of the data to be transmitted or received. When the local unit transmits data, DERR indicates the value set in the text length bit set register. When the local unit receives data, DERR indicates the value received in the text length field. ■ Text Length Bit Read Register (Lower 8 Bits) (DERR) Figure 21.3-12 Text Length Bit Read Register (Lower 8 Bits) (DERR) Bit Address:00007EH Read/write Initial value 7 DE7 (R) X 6 DE6 (R) X 5 DE5 (R) X 4 DE4 (R) X 3 DE3 (R) X 2 DE2 (R) X 1 DE1 (R) X 0 DE0 (R) X Text bit read register DERR Data is set in the text length bit read register (lower 8 bits) (DERR) in the following timing: ❍ In master mode • When the number of bytes of transmission data is written in DEWR • When text length bits are received by master reception • When communication ends ❍ In slave mode • When the number of bytes of transmission data is written in DEWRI • When text length bits are received by slave reception • When communication ends For the values of DERR, see Table 21.3-2 "Settings of the Number of Bytes of Transmission Data". 368 21.3 Registers of IEBusTM Controller 21.3.13 Read Data Buffer (RDB) The read data buffer (RDB) is an 8-byte FIFO buffer to store the data received in the data field. ■ Read Data Buffer (RDB) Figure 21.3-13 "Read Data Buffer (RDB)" shows the bit configuration of the read data buffer (RDB). Figure 21.3-13 Read Data Buffer (RDB) Bit 15 14 13 12 11 10 9 8 Address:000081H RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 Read data buffer Read/write Initial value (R) X (R) X (R) X (R) X (R) X (R) X (R) X (R) X RDB If the 8-byte read data buffer (RDB) becomes full of received data, a reception interrupt occurs. If it occurs, data must be read from the read data buffer. If data is not read before the next data is received, an error occurs. If the error occurs, broadcast communication is stopped or one-toone communication continues reception until received data exceeds the maximum number of bytes of transmission data without returning an acknowledgment. Table 21.3-10 "Time required until next data reception after reception interrupt" lists the time required until the next data is received after RDB has become full. Even if RDB is not full of received data, a reception interrupt occurs when the data of the number of bytes specified by the text length bits or the maximum number of bytes of transmission data has been received. Data must be read from RDB when the reception interrupt occurs. Writing 1 in the RDBC bit of the CMRL register clears the read data buffer. Confirm that the read data buffer is not empty before reading it. Table 21.3-10 Time required until next data reception after reception interrupt Maximum time [μs] Number of cycles Mode 0 1580 19000 Mode 1 400 4800 Mode 2 290 3400 369 CHAPTER 21 IEBusTM CONTROLLER 21.3.14 Write Data Buffer (WDB) The write data buffer (WDB) is an 8-byte FIFO buffer to store the data to be transmitted in the data field. The timing of transmission interrupt can be set in the TIT1 and TIT0 bits of the command register. ■ Write Data Buffer (WDB) Figure 21.3-14 "Write Data Buffer (WDB)" shows the bit configuration of the write data buffer (WDB). Figure 21.3-14 Write Data Buffer (WDB) Bit 7 6 5 4 3 2 1 0 Address:000080H WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0 Write data buffer Read/write Initial value (W) X (W) X (W) X (W) X (W) X (W) X (W) X (W) X WDB If a transmission interrupt is caused by the write data buffer (WDB), the data to be transmitted next must be written in the write data buffer. The written data is transmitted, the write data buffer becomes empty, and there is no more data to be transmitted. In this status, if the data to be transmitted next is not written within the time shown in Table 21.3-11 "Time allowed until next data writing after transmission interrupt" an error occurs and communication is stopped. Writing 1 in the WDBC bit of the CMRL register clears the write data buffer. Data must not be written in the write data buffer when it is full. Confirm that the write data buffer is not full before writing data in it. Table 21.3-11 Time allowed until next data writing after transmission interrupt 370 Maximum time [μs] Number of cycles Mode 0 1580 19000 Mode 1 400 4800 Mode 2 290 3400 21.4 IEBusTM Transmission Control 21.4 IEBusTM Transmission Control There are the following three types of transmission on IEBusTM: • Master transmission • Slave transmission • Transmission of slave status and lock address ■ Master Transmission Master transmission is to transmit data commands from a master unit to a slave unit. When the local unit as the master unit transmits data to a slave unit, AH, BH, EH, or FH must be set in the broadcast control bit set register. 1. The master address is set in the local address set register, the slave address is set in the slave address set register, and broadcast and control bits are set in the broadcast control bit set register. The PCOM bit of the command register is then set to enable communication. 2. When the local unit succeeded in arbitration as the master unit (at the end of master address field), the state code (0H) indicating the start of transmission is set in the ST3 to ST0 bits of the status register and a transmission interrupt is generated. The number of bytes of transmission data is then set in the text bit length set register and transmission data is set in WDB while WDB is being checked to confirm that it is not full. 3. Each time one byte of data is transmitted, the data set in WDB is eliminated by one byte. When the writable area in WDB reaches the number of bytes specified by the TIT1 and TIT0 bits of the command register (that is, a timing of transmission interrupt), a transmission interrupt occurs. At that time, transmission data must be set in WDB if the state code is 1H (data transmission) and WDB is not full. 4. When the data or commands of the number of bytes of transmission data have been transmitted normally, state code "2H" (end of transmission) is set in the ST3 to ST0 bits of the status register and the EOD bit is set, then a transmission interrupt occurs. 5. Transmission of data over the maximum number of bytes or a transmission error may occur and transmission may stop in the middle without the number of bytes set in the text length bit set register transmitted. If it occurs, state code "3H" (transmission stopped in the middle) is set in the ST3 to ST0 bits of the status register and a transmission interrupt occurs. In this case, the TSL, REF, and TE bits of the status register indicate the content of the communication error. If a timing error occurs in transmission and all data cannot be transmitted, the data remaining in WDB can be transmitted by clearing the TE bit and retrying transmission. The retry of transmission starts with the transmission of the data that follows the data transmitted at the time the error occurred. If transmission is to be resumed, 1 must be written in the WDBC bit of the command register to clear WDB. If the master unit fails in arbitration, it enters the slave reception state. If it receives a slave address field and it is not slave reception, slave results or broadcast reception may stop in the middle (status code BH or FH) and a reception interrupt occurs. Because the hardware does not support transmission retry, a program must specify the number of retries and execute those retries. 371 CHAPTER 21 IEBusTM CONTROLLER ■ Slave Transmission Slave transmission is to transmit data from a slave unit to a master unit when the slave unit receives control bit data of 3H or 7H from the master unit. 1. When the slave unit receives control bit data of 3H or 7H from the master unit, state code "0H" (start of transmission) is set in the ST3 to ST0 bits of the status register and a transmission interrupt occurs. The number of bytes of transmission data is then set in the text bit length set register and transmission data is set in WDB while WDB is being checked to confirm that it is not full. (See the notes below.) 2. When transmission of text data is started, state code "1H" (transmission in progress) is set in the ST3 to ST0 bits of the status register and a transmission interrupt occurs. Transmission data is then set in WDB while WDB is being checked to confirm that it is not full. 3. Each time one byte of data is transmitted, the data set in WDB is eliminated by one byte. When the writable area in WDB reaches the number of bytes specified by the TIT1 and TIT0 bits of the command register (that is, a timing of transmission interrupt), a transmission interrupt occurs. At that time, transmission data must be set in WDB if the state code is 1H (data transmission) and WDB is not full. 4. When the data or commands of the number of bytes of transmission data have transmitted normally, state code "2H" (end of transmission) is set in the ST3 to ST0 bits of the status register and the EOD bit is set, then a transmission interrupt occurs. 5. Transmit data over the maximum number of bytes or a transmission error may occur and transmission may stop in the middle without the number of bytes set in the text length bit set register transmitted. If it occurs, state code "3H" (transmission stopped in the middle) is set in the ST3 to ST0 bits of the status register and a transmission interrupt occurs. In this case, the TSL, REF, and TE bits of the status register indicate the content of the communication error. ■ Notes on the Reception of Control Bits from Master Unit The number of bytes of transmission data and transmission data can also be set by the interrupt after reception of control bits. If WDB is empty and transmission data is set first by that interrupt, the time allowed until the next interrupt for text length bit transmission is short. Note the following: 372 • Confirm that WDB is not full before writing data. • When setting the number of bytes of transmission data by that interrupt, set it within the limit time (shown in Table 21.4-1 "Time allowed until setting of the number of bytes of transmission data after transmission interrupt") from that interrupt. If it cannot be set within the limit time, no error occurs but the data of the number of bytes of transmission data set previously is transmitted. If the number of bytes is the initial value, 256 bytes of data are transmitted. • When no transmission data has been set in WDB before that interrupt, set at least one byte of data in WDB within the limit time (shown in Table 21.4-1 "Time allowed until setting of the number of bytes of transmission data after transmission interrupt") from that interrupt. If no data is set within the limit time, WDB is determined to be empty, an error occurs after the text length bits are transmitted, and communication ends. 21.4 IEBusTM Transmission Control Table 21.4-1 Time allowed until setting of the number of bytes of transmission data after transmission interrupt Maximum time [μs] Number of cycles Mode 0 About 158 About 1900 Mode 1 About 40 About 480 Mode 2 About 29 About 350 ■ Transmission of Slave Status and Lock Address When a slave unit receives control bit data of 0H, 4H, 5H, or 6H, the slave unit automatically generates slave status and a lock address and transmits them to the master unit. The slave status and lock address do not have to be set as transmission data in WDB. However, one byte must be set as the number of bytes of transmission data in the text length bit set register for the slave status and lock address. 373 CHAPTER 21 IEBusTM CONTROLLER 21.5 IEBusTM Reception Control There are three types of reception on IEBusTM as follows: • Master reception • Slave reception • Broadcast reception ■ Master Reception Master reception is to receive data, slave status, or lock address from a slave unit. The local unit is designated as the master unit by setting 0H, 3H, 4H, 5H, 6H, or 7H in the control bits. 1. After receiving the control bits, the slave unit transmits the text length bits to the master unit. When the master unit returns an acknowledgment after receiving the text length bits, the number of bytes of reception data is set in the text length bit read register. 2. When the slave unit receives acknowledgment of the master unit transmitted, the slave unit transmits data in the data field. Whenever one byte of data is received, the data is set in RDB. 3. Each time 8 bytes (RDB size) of data are received, state code "5H" (RDB buffer is full) is set in the ST3 to ST0 bits of the status register and a reception interrupt occurs. When the reception interrupt occurs, RDB is read while being checked to confirm that it is not full. 4. When all data of one frame is received and set in RDB, state code "5H" (normal end of reception) is set in the ST3 to ST0 bits of the status register and a reception interrupt occurs. This reception interrupt occurs even if RDB is not full. 5. Reception of data over the maximum number of bytes or a transmission error may occur and reception may stop in the middle without the number of bytes set in the text length bit set register received from the slave unit. If this occurs, state code "7H" (reception stopped in the middle) is set in the ST3 to ST0 bits of the status register and a reception interrupt occurs. ■ Slave Reception The slave unit receives AH, BH, EH, or FH as the control bits from the master unit. Slave reception is to receive data or commands from the master unit. 1. When the slave unit returns an acknowledgment in the text length field, the number of bytes of reception data is set in the text length bit read register. 2. When the slave unit returns the acknowledgment after reception of the text length bits, the master unit transmits data in the data field. Each time one byte of data is received normally, the data is set in RDB. 3. Each time 8 bytes (RDB size) of data are received, state code "9H" (RDB buffer is full) is set in the ST3 to ST0 bits of the status register and a reception interrupt occurs. When the reception interrupt occurs, RDB is read while being checked to confirm that it is not full. 4. After the last data of one frame is received and set in RDB, state code "AH" (normal end of reception) is set in the ST3 to ST0 bits of the status register and a reception interrupt occurs. This reception interrupt occurs even if RDB is not full. 5. Reception of data over the maximum number of bytes or a transmission error may occur and reception may stop in the middle without the number of bytes set in the text length bit set 374 21.5 IEBusTM Reception Control register received from the slave unit. If this occurs, state code "BH" (reception stopped in the middle) is set in the ST3 to ST0 bits of the status register and a reception interrupt occurs. ■ Broadcast Reception 1. When the slave unit returns an acknowledgment in the text length field, the number of bytes of reception data is set in the text length bit read register. 2. When the slave unit returns the acknowledgment after reception of the text length bits, the master unit transmits data in the data field. Each time one byte of data is received normally, the data is set in RDB. 3. Each time 8 bytes (RDB size) of data are received, state code "EH" (RDB buffer is full) is set in the ST3 to ST0 bits of the status register and a reception interrupt occurs. When the reception interrupt occurs, RDB is read while being checked to confirm that it is not full. 4. After the last data of one frame is received and set in RDB, state code "DH" (normal end of reception) is set in the ST3 to ST0 bits of the status register and a reception interrupt occurs. This reception interrupt occurs even if RDB is not full. 5. Reception of data over the maximum number of bytes or a transmission error may occur and reception may stop in the middle without the number of bytes set in the text length bit set register received from the slave unit. If this occurs, state code "FH" (reception stopped in the middle) is set in the ST3 to ST0 bits of the status register and a reception interrupt occurs. For the settings of the ST3 to ST0 bits of the status register, see Section 21.6 "Communication Control Status". 375 CHAPTER 21 IEBusTM CONTROLLER 21.6 Communication Control Status The ST3 to ST0 bits of the status register are used to indicate a status code. When a status code is set in these bits, an interrupt request occurs. During the interrupt, these bits can be read to know the communication status. ■ Master or Slave Transmission (Occurrence of Transmission Interrupt) Table 21.6-1 "Codes in ST3 to ST0 Bits for Master or Slave Transmission" lists the codes that can be set in the ST3 to ST0 bits when the local unit has succeeded in arbitration in the master address field and has become the master unit and transmits data or commands to a slave unit (also in case of broadcast transmission) or when a slave unit transmits data to the master unit. Table 21.6-1 Codes in ST3 to ST0 Bits for Master or Slave Transmission Code name Code Description Start of transmission 0000B This code indicates that master or slave transmission is started. The master and slave modes are different in the timing of the code setting. • Master transmission The code is set when the local unit has ended the master address field and become the master unit. • Slave transmission The code is set when the control bits (0H, 3H, 4H, 5H, 6H, or 7H) requesting data transmission are received from the master unit. Data transmission 0001B This code indicates that the master or slave unit is transmitting data using the data field. This code is set when the transmission of text length bits is started. Normal end of transmission 0010B This code indicates that all the data of the number of bytes specified by the text length bits has been transmitted in one frame. Transmission ended in the middle 0011B This code indicates that communication ended without transmitting all data of the number of bytes specified by the text length bits in one frame. ■ Master Reception (Occurrence of Reception Interrupt) Table 21.6-2 "Codes in ST3 to ST0 Bits for Master Reception" lists the codes that can be set in the ST3 to ST0 bits when the local unit has succeeded in arbitration in the master address field and become the master unit and receives data, status, or lock address from a slave unit (also in case of broadcast reception). 376 21.6 Communication Control Status Table 21.6-2 Codes in ST3 to ST0 Bits for Master Reception Code name Code Description Start of master reception 0100B This code indicates that master reception has started. The code is set when the master unit has received a text length code normally from the slave unit. Data full in master reception 0101B This code indicates that 8 bytes of data has been received and RDB is full. When this code is set, the master unit requests the host controller to read received data from RDB. Normal end of master reception 0110B This code indicates that all the data of the number of bytes specified by the text length bits has been received in one frame. Master reception ended in the middle 0111B This code indicates that communication ended without receiving all the data of the number of bytes specified by the text length bits in one frame. ■ Slave Reception (Occurrence of Reception Interrupt) Table 21.6-3 "Codes in ST3 to ST0 Bits for Slave Reception" lists the codes that can be set in the ST3 to ST0 bits when the local unit as a slave unit receives data or commands from the master unit. Table 21.6-3 Codes in ST3 to ST0 Bits for Slave Reception Code name Code Description Start of slave reception 1000B This code indicates that slave reception is started. The code is set when the slave unit has received a text length code normally from the master unit. Data full in slave reception 1001B This code indicates that 8 bytes of data has been received and RDB is full. When this code is set, the slave unit requests the host controller to read received data from RDB. Normal end of slave reception 1010B This code indicates that all the data of the number of bytes specified by the text length bits has been received in one frame. Slave reception ended in the middle 1011B This code indicates that communication ended without receiving all the data of the number of bytes specified by the text length bits in one frame. 377 CHAPTER 21 IEBusTM CONTROLLER ■ Broadcast Reception (Occurrence of Reception Interrupt) Table 21.6-4 "Codes in ST3 to ST0 Bits for Broadcast Reception" lists the codes that can be set in the ST3 to ST0 bits when the local unit as a slave unit receives data or commands by broadcast from the master unit. Table 21.6-4 Codes in ST3 to ST0 Bits for Broadcast Reception Code name Code Description Start of broadcast reception 1100B This code indicates that broadcast reception has started. The code is set when the slave unit has received a text length code normally from the master unit. Data full in broadcast reception 1101B This code indicates that 8 bytes of data have been received and RDB is full. When this code is set, the slave unit requests the host controller to read received data from RDB. Normal end of broadcast reception 1110B This code indicates that all the data of the number of bytes specified by the text length bits has been received in one frame. Broadcast reception ended in the middle 1111B This code indicates that communication ended without receiving all the data of the number of bytes specified by the text length bits in one frame. 378 21.7 Examples of the Flows of Main and Interrupt Processing Routines for IEBusTM Controller 21.7 Examples of the Flows of Main and Interrupt Processing Routines for IEBusTM Controller This section explains the flows of IEBusTM processing on the MB90580C series with examples. ■ Main Routine Figure 21.7-1 Main Routine Start Initialize IEBusTM Enable IEBusTM operation Execute IEBusTM control End ■ Interrupt Processing Routine Figure 21.7-2 "Interrupt Processing Routine" shows an example of the routine that is executed by the IEBusTM controller when transmission is started or a reception completion interrupt occurs. In this routine, the status code set in the ST3 to ST0 bits of the status register is read, transmission data is written, and received data is read. Figure 21.7-2 Interrupt Processing Routine Start Read status register Higher 2 bits of ST3 to ST0 00B Y Classify status code 01B 10B 11B Is N local unit the master? Master transmission routine(*1) Slave data transmission routine(*2) Master reception routine(*3) Slave reception routine Broadcast reception routine RETI End *1: See Item "Master transmission routine" in Section 20.8, "Examples of the Flows of Processing by IEBusTM Controller." *2: See Item "Slave data transmission routine" in Section 20.8, "Examples of the Flows of Processing by IEBusTM Controller." *3: See Item "Master reception routine" in Section 20.8, "Examples of the Flows of Processing by IEBusTM Controller." 379 CHAPTER 21 IEBusTM CONTROLLER 21.7.1 Initialization Routine Figure 21.7-3 "Initialization Routine" shows the flow of IEBusTM initialization. In this routine, the local address and a slave address are set, data is set in the command register, and communication is enabled. The slave address, broadcast bits, and control bits must be set only when the local unit must be the master unit. ■ Initialization Routine Figure 21.7-3 Initialization Routine Start Set the local address in the local address set register. The local address is used as the master address when the local unit is the master unit or for comparison with the master address when the local unit is a slave unit. Set local address Must local unit be the master unit? N Y Set slave address The slave address must be set only when the local unit must be the master unit. Set the slave address in the slave address set register. Set data in the broadcast bit set and control bit set registers. Set data in broadcast and control bits Initialize the communication mode and other data in the command register. Set data in command register Write 1 in the PCOM bit. Enable communication (*) Is transmission to be done? Y Enable transmission N If only slave reception is required, the GOTM and GOTS bits do not have to be set to enable transmission. Write 1 in the GOTM or GOTS bit. End *: These operations are executed by writing data in the command register. 380 21.7 Examples of the Flows of Main and Interrupt Processing Routines for IEBusTM Controller 21.7.2 Master Transmission Routine Figure 21.7-4 "Master Transmission Routine" shows the flow of the master transmission routine. The master transmission routine is used after communication is enabled when the local unit has succeeded in arbitration and become the master unit and transmits data to a slave unit. This routine is executed when the master transmission state code (higher 2 bits are 00B) is set in the ST3 to ST0 bits of the status register in the interrupt processing routine. ■ Master Transmission Routine Figure 21.7-4 Master Transmission Routine Start Read status register Y ST3-0 (*1) Communication ended in the middle 3H? Processing by hardware N Y ST3-0 0H? Processing by hardware N Set data in control and text length bits (*2) N=0 Y N Processing by hardware WDBF=1? N Y Processing by hardware Setting of Write data in WDB master transmission data (*3) Processing by N=N-1 hardware ST3-0 2H? N Processing by hardware Y Normal end *1: The cause of the end of communication in the middle can be known by reading the TE, REF,and ACK bits of the status register. Because data remains in WDB, the remaining data can be transmitted by retrying the transmission. To clear WDB, write 1 in the WDBC bit of the command register. *2: Do not write data when the WDBF bit is 1. *3: "N" means the number of bytes of master transmission data. 381 CHAPTER 21 IEBusTM CONTROLLER 21.7.3 Slave Data Transmission Routine Figure 21.7-5 "Slave Data Transmission Routine" shows the flow of the slave data transmission routine. The slave data transmission routine is used when the slave unit transmits data to the master unit after the slave unit receives control bits from the master unit. This routine is executed when the slave data transmission state code (higher 2 bits are 00B) is set in the ST3 to ST0 bits of the status register in the interrupt processing routine. ■ Slave Data Transmission Routine Figure 21.7-5 Slave Data Transmission Routine Start Read status register Y ST3-0 (*1) Communication ended in the middle 3H? Processing by hardware N Y ST3-0 0H? Processing by hardware N Set data in text length bits and transmission data in WDB (*2) N=0 N Y WDBF=1? Y N Setting of Write data in WDB slave transmission data (*3) N=N-1 ST3-0 2H? N Y Normal end *1: The cause of the end of communication in the middle can be known by reading the TE, REF, and ACK bits of the status register. Because data remains in WDB, the remaining data can be transmitted by retrying the transmission. To clear WDB, write 1 in the WDBC bit of the command register. *2: Do not write data when the WDBF bit is 1. *3: "N" means the number of bytes of slave transmission data. 382 21.7 Examples of the Flows of Main and Interrupt Processing Routines for IEBusTM Controller 21.7.4 Master Reception Routine The master reception routine is used when the master unit receives data, slave status, or lock address from the slave unit after the master unit has started data transmission. ■ Master Reception Routine The master reception routine consists of the following four routines executed according to the contents of the ST3 to ST0 bits of the status register: ❍ Processing to be performed when status code is "4H" (start of master reception) Figure 21.7-6 "Flow of Processing to Start Master Reception" shows the flow of the processing to be executed when status code is "4H" (start of master reception). This status code is set when the master unit has received the text length bits normally from the slave unit and indicates the start of master reception. (No interrupt occurs.) Figure 21.7-6 Flow of Processing to Start Master Reception Start (*1) Read broadcast bit read, control bit read, and text length bit read registers (*2) Set the number of bytes of master reception data in N Reading of the broadcast bits, control bits, and the number of bytes of master reception data Processing by hardware End *1: The data below does not always have to be read because it is set in each register. However, data must be read before the relevant register is updated. *2: "N" means the number of bytes of master reception data. ❍ Processing to be performed when status code is "5H" (request for reading master reception data) Figure 21.7-7 "Flow of Processing of Master Reception Data Reading" shows the flow of the processing to be executed when status code is "5H" (request for reading master reception data). 383 CHAPTER 21 IEBusTM CONTROLLER Figure 21.7-7 Flow of Processing of Master Reception Data Reading Start Size of master reception buffer (processed by hardware) I=8 I 1 I Processing by hardware (*1) Y RDBE=1? N End Read RDB Reading of master reception data (*2) N 1 N Processing by hardware *1: Do not read RDB when the RDBE bit is 1. *2: "N" means the number of bytes of master reception data. ❍ Processing to be performed when status code is "6H" (normal end of master reception) Figure 21.7-8 "Flow of Processing of the Normal End of Master Reception" shows the flow of the processing to be executed when status code is "6H" (normal end of master reception). Figure 21.7-8 Flow of Processing of the Normal End of Master Reception Start (*1) Read broadcast bit read, control bit read, and text length bit read registers Set the number of bytes of master reception data in N Read RDB Reading of the broadcast bits, control bits, and the number of bytes of master reception data Processing by hardware Reading of master reception data N-1 Processing by hardware RDBE=1? Processing by hardware N (*2) N Y End Processing by hardware *1: The data below does not always have to be read in this stage because it is set in each register. However, data must be read before the next frame starts and the relevant register is updated. *2: Do not read RDB when the RDBE bit is 1. 384 21.7 Examples of the Flows of Main and Interrupt Processing Routines for IEBusTM Controller ❍ Processing to be performed when status code is "7H" (end of master reception in the middle) Figure 21.7-9 "Flow of Processing of the End of Master Reception in the Middle" shows the flow of the processing to be executed when status code is "7H" (end of master reception in the middle). Note that the routines for slave reception and broadcast reception are the same as those for master reception, but the status codes to be used are different. For the status codes, see Section 21.6 "Communication Control Status". Figure 21.7-9 Flow of Processing of the End of Master Reception in the Middle Start (*1) Read broadcast bit read, control bit read, and text length bit read registers Reading of the broadcast bits, control bits, and the number of bytes of master reception data Set the number of bytes of master reception data in N Processing by hardware Read STR H and L (*2) RDBE=1? N Read RDB Y Reading of master reception data End *1: The data below does not always have to be read in this stage because it is set in each register. However, data must be read before the next frame starts and the relevant register is updated. *2: Do not read RDB when the RDBE bit is 1. 385 CHAPTER 21 IEBusTM CONTROLLER 21.8 IEBusTM Controller Operation at Transmission Figure 21.8-1 "Operation when WDBC is set to 1 (on the master for master transmission)" and Figure 21.8-2 "Operation when WDBC is set to 0 (on the master for master transmission)" show the transmission operations over multiple frames. Figure 21.8-3 "Example of Operation at Occurrence of Error on Slave Unit" and Figure 21.8-4 "Example of Operation at Occurrence of Error on Master Unit" show the transmission operations when an error occurs. ■ Transmission Operation over Multiple Frames Figure 21.8-1 Operation when WDBC is set to 1 (on the master for master transmission) Second frame First frame Data Data N-3(04H) Data Start N-2(03H) COM 02H A value is written in DERR. N Writing in DEWR DEWR Transmission buffer N 03H 00H Remaining 2 bytes are transmitted. FEH FFH Newly set data is transmitted. 07H, 06H, 05H, 04H, 03H, 02H, 01H, 00H WDBC FFH, FEH,FDH, FCH, FBH, FAH, F9H 8 bytes of transmission data are written. Each time one byte is transmitted, WDBF is cleared. WDBE WDBF Data N(FFH) 02H Writing in WDB WDB N-1(FFH) Remaining transmission data is 0 bytes. Remaining number of transmission bytes can be read. Reading of DERR DERR Broadcast Master address Slave address Control Text length bit WDB is empty when WDBC is 1. Data is written in WDB until it becomes full. "N" indicates the number of bytes transmitted. Parenthesized value indicates transmission data. 386 21.8 IEBusTM Controller Operation at Transmission Figure 21.8-2 Operation when WDBC is set to 0 (on the master for master transmission) Data First frame Data N-3(04H) Second frame Data N-2(03H) Start COM N WDBE 00H A value is written in DERR. 03H Remaining 2 bytes are transmitted. 02H 01H The data following transmitted data in the preceding frame is transmitted. Writing in WDB WDBC Data N-(01H) N Transmission buffer WDB N-1(02H) 02H Writing in DEWR DEWR Text length bit Remaining transmission data is 0 bytes. Remaining number of transmission bytes can be read. Reading of DERR DERR Broadcast Master address Slave address Control 07H, 06H, 05H, 04H, 03H, 02H, 01H, 00H FFH, FEH,FDH, FCH, FBH Because 3 bytes of previous data remain, 5 bytes of transmission data are written. Each time one byte is transmitted, WDBF is cleared. WDBF Data is written in WBF until it becomes full. * "N" indicates the number of bytes transmitted. Parenthesized value indicates transmission data. * The transmission buffer stores the data to be transmitted next. It can be accessed only by hardware. * For master reception, the timing of setting data in DERR is the same, but the timing of setting data in DEWR and WDB is different (see section 21.5, "IEBusTM Reception Control," and Section 21.6, "Communication Control Status"). 387 CHAPTER 21 IEBusTM CONTROLLER ■ Transmission Operation at Occurrence of Error Figure 21.8-3 "Example of Operation at Occurrence of Error on Slave Unit" shows an example of the master transmission operation in which an error occurs in data in the second byte on the slave unit, the master unit receives NAK, and the master unit transmits subsequent data in the second frame. Figure 21.8-3 Example of Operation at Occurrence of Error on Slave Unit Data is retransmitted until the maximum number of transmission bytes is reached. Text length bit Data 1 (00H) Data 2 (01H) Data 2 (01H) Data field Header Data 2 (01H) Text length bit Data 2 (01H) Data 3 (02H) Communication ends because the maximum number of transmission bytes is reached. <Transmitting unit> COM Transmission buffer WDBC 00H 01H DERR Writing in DEWR 02H 03H Transmission of three bytes is set in DEWR. DERR is read, and the read value is written in DEWR. DERR Value of DERR is set. 00H All data is transmitted normally. Transmission of 3 bytes is set. Communication ends because of error. Because error occurred in the second byte, data is not set in RDB. COM RDB 02H 02H 03H DEWR <Receiving unit> 02H 01H Remaining 2 bytes are transmitted. A value is set in DEWR. 02H WDB is cleared, and data is written in WDB from the second byte of the WDB area. XXH 00H 03H Data is received as text length bits. 02H 01H 02H 02H 00H All data is received normally. Remaining 2 bytes are received. Data is received as text length bits. Figure 21.8-4 "Example of Operation at Occurrence of Error on Master Unit" shows an example of the master transmission operation in which an error occurs in data in the second byte on the master unit and the master unit transmits subsequent data in the second frame. 388 21.8 IEBusTM Controller Operation at Transmission Figure 21.8-4 Example of Operation at Occurrence of Error on Master Unit Data is retransmitted until the maximum number of transmission bytes is reached. Text length bit Data 1 (00H) Data X (XXH) Data X (XXH) Data field Header Data X (XXH) Text length bit Data 2 (01H) Data 3 (02H) Communication ends because of error. <Transmitting unit> COM 00H Transmission buffer WDBC DERR 02H 03H Writing in DEWR Transmission of 3 bytes is set. <Receiving unit> RDB DERR 02H DERR is read, and the read value is written in DEWR. 01H All data is transmitted normally. A value is set in DEWR. 03H DEWR COM 02H 01H WDB is cleared, and data is written in WDB from the second byte of the WDB area. 02H Transmission of 3 bytes is set. Reception continues until the maximum number of transmission bytes is reached. Value of DERR is set. Because error occurred in the second byte, data is not set in RDB. XXH 00H 01H 03H 02H 02H 00H 00H Remaining 2 bytes are received. Data is received as text length bits. All data is received normally. Data is received as text length bits. * The transmission buffer stores the data to be transmitted next. It can be accessed only by hardware. * Among the 8 bytes of RDB, the data to be set first is indicated. * For master reception, the timing of setting data in DERR is the same, but the timing of setting data in DEWR and WDB is different (see section 21.5, "IEBusTM Reception Control," and Section 21.6, "Communication Control Status"). 389 CHAPTER 21 IEBusTM CONTROLLER 21.9 IEBusTM Protocol Operation The Inter-Equipment Bus (IEBusTM) is a small-scale digital data transmission system bus designed for data transmission between different equipment. ■ Overview of IEBusTM Protocol Operation The following gives an overview of the IEBusTM protocol operation: ❍ Communication mode Half-duplex asynchronous communication ❍ Multi-master mode All the units connected to IEBusTM can transmit data to each other. ❍ Broadcast function (communication between one unit and multiple units) • Group broadcast: Broadcast to a group of units • General broadcast: Broadcast to all other units ❍ Selection from three modes using different transmission speeds Table 21.9-1 Transmission speeds by mode of IEBusTM protocol operation Internal frequency of IEBusTM: 6 MHz Internal frequency of IEBusTM: 6.29 MHz Maximum number of transmission bytes (number of bytes per frame) Mode 0 About 3.9 K(bps) About 4.1 K(bps) 16 Mode 1 About 17 K(bps) About 18 K(bps) 32 Mode 2 About 26 K(bps) About 27 K(bps) 128 ❍ Access control Carrier Sense Multiple Access with Collision Detection (CSMA/CD) ❍ Priority for the use of bus 1. Broadcast has priority over normal communication (i.e., communication between a unit and another unit). 2. A unit with a master address has priority over all the other units with higher master addresses. ❍ Scale of communication 390 • Maximum number of units: 50 • Maximum cable length: 150 m (using a twisted-pair cable with resistance of 0.1 Ω/m or less) 21.9 IEBusTM Protocol Operation • • Maximum load capacity: • 8,000 pF (between BUS- and BUS+) at internal frequency of IEBusTM of 6 MHz • 7,100 pF (between BUS- and BUS+) at internal frequency of IEBusTM of 6.29 MHz Terminating resistance: 120 Ω The scale of communication is the one on the system that includes the IEBusTM driver and receiver. ■ Determining the Priority for Using the Bus (Arbitration) A unit connected to IEBusTM executes an operation to use the bus exclusively for the control of other units. This operation is called "arbitration". When multiple units starts transmission at the same time, arbitration is executed to give one of those units the right to use the bus exclusively. By arbitration, the unit that is given the right to use the bus exclusively is determined under the following priority conditions for the exclusive use of the bus: ❍ Priority due to communication type Broadcast (communication between a unit and multiple units) has priority over normal communication (communication between two units). ❍ Priority due to master address When the communication type is the same, a unit with a master address has priority over all the other units with higher master addresses. The master address consists of 12 bits. The unit with master address of 000H has the highest level of priority; the unit with master address of FFFH has the lowest level of priority. ■ Communication Modes IEBusTM supports three communication modes that are different in transmission speed. The table below lists the communication modes, transmission speeds, and the maximum numbers of transmission bytes per frame. Table 21.9-2 Transmission speed and maximum number of transmission bytes in each communication mode Effective transmission speed *1 Communication mode Maximum number of transmission bytes (number of bytes per frame) Internal frequency of IEBusTM *2 Internal frequency of IEBusTM *2 0 16 About 3.9 K(bps) About 4.1 K(bps) 1 32 About 17 K(bps) About 18 K(bps) 2 128 About 26 K(bps) About 27 K(bps) *1: This indicates the effective transmission speed available for the transmission of the maximum number of transmission bytes. *2: For the relation between the internal frequency of IEBusTM and the internal frequency of CPU, see the calculation formula shown in Table 21.3-4 "Settings of GOTM and GOTS bits". 391 CHAPTER 21 IEBusTM CONTROLLER Note: • A communication mode must be selected on each unit connected to IEBusTM before starting communication. If a master unit and a slave unit use different communication modes, normal communication between the units is not possible. • If the internal frequency of IEBusTM set on a unit differs from the one set onanother unit, normal communication between these units is not possible even if the same communication type is used. The same internal frequency must be set on every unit. ■ Communication address On IEBusTM, a unique 12-bit communication address is given to each unit. The communication address consists of the following numbers: • Higher 4 bits: Group number (identifying the group where each unit belongs) • Lower 8 bits: Unit number (identifying each unit in the relevant group) ■ Broadcast In normal communication, a master unit transmits or receives data to/from a slave unit. In broadcast, a master unit transmits data to multiple slave units, and the slave units do not return acknowledgment signals to the master unit. The communication type, broadcast or normal communication, can be selected by the setting of the broadcast control bits. Broadcast is available in two kinds as follows: ❍ Group broadcast Group broadcast transmits data to the slave units having the same group number (higher 4 bits of communication address). ❍ General broadcast General broadcast transmits data to all slave units regardless of their group numbers. Group broadcast and general broadcast can be distinguished by the value of the slave address. 392 21.10 Transmission Protocol 21.10 Transmission Protocol Table 21.10-1 "Transmission protocol signal format" shows the format of transmission protocol signals of IEBusTM. Communication data is transmitted as a series of signals called the "frame". The number of bytes of data that can be transmitted by a frame and transmission speed vary depending on the communication mode. ■ Transmission Protocol Table 21.10-1 Transmission protocol signal format Field name Number of bits Transmission time Header Master address field 1 12 1 Start Broad- Master cast bit bit address 1 Slave address field 12 11 Slave P address P A Control field 4 Text length field 1 1 Control bits P A 8 1 Text length bits Data field 1 8 1 1 Data P A (1 byte) P A 8 1 1 Data (1 byte) P A Mode 0 About 7330 About 1590 x N Mode 1 About 2090 About 410 x N Mode 2 About 1590 About 300 x N P: Parity bit (1 bit) N: Number of data bytes A: Acknowledgment bit (1 bit) 0: ACK 1: NAK * For broadcast, the value of each acknowledgment bit is ignored. 393 CHAPTER 21 IEBusTM CONTROLLER 21.10.1 Header in Transmission Protocol Signal Format The header in the transmission signal format consists of a start bit and a broadcast bit. ■ Start Bit The start bit is the signal to indicate the start of data transmission to other units. A unit that is to start data transmission outputs a low-level signal (start bit) for a specified time, then outputs the next signal (broadcast bit). If a unit has already output the start bit signal when another unit attempts to output its start bit signal, the latter unit stops start bit output and waits until the former unit ends start bit output. In synchronization with the end of start bit output, the latter unit outputs the broadcast bit signal. A unit other than the unit that has started transmission detects the start bit output and enters the receiving state. ■ Broadcast Bit The broadcast bit is used to identify the communication type as either broadcast or normal communication. When the broadcast bit is 0, the communication type is broadcast. When it is 1, the communication type is normal. Broadcast is available in two types, group broadcast and general broadcast, which are distinguishable by the value of the slave address. Because multiple slave units are communication partners in broadcast, the acknowledgment bit in each field is not returned from each slave unit. If two or more units start transmitting frames at the same time, broadcast has priority over normal communication and succeeds in arbitration. 394 21.10 Transmission Protocol 21.10.2 Master Address Field in Transmission Protocol Signal Format The master address field in the transmission signal format determines the master unit. ■ Master Address Field The master address field consists of a 12-bit master address and a parity bit. If two or more units start transmission with the same broadcast bit value at the same time, determination by arbitration is undertaken in the master address field. In the master address field, the local unit compares each bit it outputs with the data on the bus. If the master address the local unit outputs is different from the data on the bus, the local unit determines that it has failed in arbitration, stops transmission, and enters the receiving state. IEBusTM has a wired AND logic. The unit having the lowest master address among the units participated in arbitration (arbitrating master units) succeeds in arbitration. After the units have output 12-bit master addresses, only one unit remains the master unit. The master unit outputs a parity bit (*) to determine the master address for other units, then starts the output of the slave address field. A master address consists of 12 bits, and its output begins with the MSB. *: IEBusTM uses an even parity. The parity bit is set when the master address field contains an odd number of set bits. 395 CHAPTER 21 IEBusTM CONTROLLER 21.10.3 Slave Address Field in Transmission Protocol Signal Format The slave address field in the transmission signal format determines the slave unit. ■ Slave Address Field The slave address field consists of a 12-bit slave address, a parity bit, and an acknowledgment bit. A slave address consists of 12 bits, and its output begins with the MSB. After the output of a 12-bit slave address, the master address outputs a parity bit to avoid incorrect reception of the slave address. The master unit then attempts to detect the acknowledgment signal from the slave unit to confirm that the slave unit exists on the bus. When the master unit detects the acknowledgment signal, it starts the output of the control field. For broadcast, the master unit starts the output of the control field without detecting an acknowledgment signal. The slave unit outputs an acknowledgment signal when it has detected that the slave address transmitted matches its own slave address and that parities for the master address and the slave address are even. If a parity is odd, the slave unit determines that the master or slave address has not been received correctly and does not output an acknowledgment signal. If it occurs, the master unit enters the standby (monitoring) state and communication ends. For broadcast, the slave address is used to identify the broadcast type, group or general broadcast, as follows: • Slave address is FFFH.: General broadcast • Slave address is an address other than FFFH.: Group broadcast The group number applied to a group broadcast is the value set in the higher 4 bits of the slave address. 396 21.10 Transmission Protocol 21.10.4 Control Field in Transmission Protocol Signal Format The control field in the transmission signal format determines the type and direction of the data field. ■ Control Field The control field consists of four control bits, a parity bit, and an acknowledgment bit. The four control bits are output sequentially from the MSB. After the control bits, the parity bit is output. When the slave unit determines that the parity is even and it can execute the function requested by the master unit, it outputs an acknowledgment signal and starts receiving the text length bit field. If the slave unit cannot execute the function requested by the master unit when the parity is even or if the parity is odd, the slave unit does not output an acknowledgment signal and enters the standby state. After confirming the acknowledgment signal, the master unit starts the output of the text length bit field. If the master unit cannot confirm the acknowledgment signal, the master unit enters the standby (monitoring) state and communication ends. For broadcast, the master unit starts the output of the text length bit field without confirming an acknowledgment signal. 397 CHAPTER 21 IEBusTM CONTROLLER 21.10.5 Text Length Field The text length field specifies the number of bytes of transmission data. ■ Text Length Field The text length field consists of eight text length bits, a parity bit, and an acknowledgment bit. The eight text length bits are output sequentially from the MSB. Table 21.10-2 "Settings of text length bits" lists the numbers of bytes of transmission data that can be specified by the text length bits. Table 21.10-2 Settings of text length bits Text length bits (hexadecimal) Number of bytes of transmission data 01H 1 byte 02H 2 bytes : : FFH 255 bytes 00H 256 bytes Remarks: If a value over the maximum number of transmission bytes per frame set by the communication mode is specified, multiple frames are used for communication. If it occurs, the value of the text length bits for the second and subsequent frames will be the remaining number of bytes of transmission data. The operation of the text length bit field is different between master transmission (control bit 3 is 1) and master reception (control bit 3 is 0). ❍ Master transmission The master unit outputs the text length and parity bits. The slave unit outputs an acknowledgment signal when it detects an even parity, then starts receiving the data field. For broadcast, if the parity is odd, the slave unit determines that the text length bits have not been received correctly and enters the standby state without returning an acknowledgment signal. If this occurs, the master unit also enters the standby (monitoring) state, and communication ends. ❍ Master reception The slave unit outputs the text length and parity bits. acknowledgment signal when it detects an even parity. The master unit outputs an If the parity is odd, the master unit determines that the text length bits have not been received correctly and enters the standby state without returning an acknowledgment signal. If this occurs, the slave unit also enters the standby state, and communication ends. 398 21.10 Transmission Protocol 21.10.6 Data Field The data field is used to transmit and receive data according to control bits. ■ Data Field The data field consists of 10-bit sets of eight data bits, a parity bit, and an acknowledgment bit. The eight data bits are output sequentially from the MSB. After the data bits, the parity bit is output by the master unit and the acknowledgment bit is output by the slave unit. For broadcast, only transmission operation of the master unit is performed and acknowledgment signals are ignored. The operation of the data field is different between master transmission and master reception as follows: ❍ Master transmission When the master unit transmits data to the slave unit, the master unit transmits the data and parity bits to the slave unit. When the slave unit receives the data and parity bits and detects that the parity is even and the reception buffer has a space, the slave unit outputs an acknowledgment signal. If the parity is odd or the reception buffer is full, the slave unit rejects the reception of the relevant data and does not output an acknowledgment signal. If the slave unit does not return an acknowledgment signal, the master unit transmits the same data again. The master unit repeats this operation until it detects the acknowledgment signal from the slave unit or the size of data exceeds the maximum number of bytes of transmission data. When the slave unit has detected an even parity and output an acknowledgment signal, the master unit transmits the next data if the next data exists and does not exceeds the maximum number of bytes of transmission data. For broadcast, the slave units do not output an acknowledgment signal, and the master unit transmits data in units of bytes. ❍ Master reception When the master unit receives data from the slave unit, the master unit outputs the synchronization signals corresponding to all bits to be read. The slave unit outputs the data and parity bits to the bus according to the synchronization signals from the master unit. The master unit reads the data and parity bits output by the slave unit and checks the parity. If the parity is odd or the reception buffer is full, the master unit rejects the reception of the relevant data and does not output an acknowledgment signal. The master unit repeats the reading of the same data if the data does not reach the maximum number of bytes of data that can be transmitted in one frame. If the parity is even and the reception buffer has a space, the master unit receives data and returns an acknowledgment signal. The master unit then reads the next data if the data does not reach the maximum number of bytes of data that can be transmitted in one frame. 399 CHAPTER 21 IEBusTM CONTROLLER 21.10.7 Parity Bit The parity bit is used to check whether transmission data is correct. The parity bit is added to the master address, slave address, control, text length, and data bits. ■ Parity Bit IEBusTMuses an even parity. The parity bit is set when the relevant data contains an odd number of set bits. The parity bit is cleared when the relevant data contains an even number of set bits. 400 21.10 Transmission Protocol 21.10.8 Acknowledgment Bit For normal communication (between two units), the acknowledgment bit is added in each of the following positions to check that data has been received normally: • End of slave address field • End of control field • End of text bit field • End of data field ■ Acknowledgment Bit The acknowledgment bit is defined as follows: 0 (ACK): Indicates that transmission data was acknowledged. 1 (NAK): Indicates that transmission data was not acknowledged. ❍ Acknowledgment bit at the end of the slave address field When one of the following conditions is satisfied, the acknowledgment bit at the end of the slave address field is set (NAK) and communication is canceled: • The parity for master address or slave address bits is invalid. • A timing error (bit format error) has occurred. • The specified slave unit is not found. ❍ Acknowledgment bit at the end of control field When one of the following conditions is satisfied, the acknowledgment bit at the end of the control field is set (NAK) and communication is canceled: • The parity for control bits is invalid. • Control bit 3 is 1 (writing operation) although the slave reception buffer (see Note) is not empty. • Control bit data is 3H or 7H although the slave reception buffer (see Note) is empty. • Although the local unit is locked, the control bit data of 3H, 6H, 7H, AH, BH, EH, or FH has been received from a unit other than the locking unit. • Although the local unit is not locked, the control bit data read from the lock address is 4H. • A timing error has occurred. • An undefined value is set in the control bits. Note: For the slave reception buffer, see Item "Reading slave status (SSR) (control bits: 0H or 6H)" of Section 21.11 "Transmission Data". 401 CHAPTER 21 IEBusTM CONTROLLER ❍ Acknowledgment bit at the end of the text length field When one of the following conditions is satisfied, the acknowledgment bit at the end of the text length field is set (NAK): • The parity for text length bits is invalid. • A timing error has occurred. ❍ Acknowledgment bit at the end of the data field When one of the following conditions is satisfied, the acknowledgment bit at the end of the data field is set (NAK): • The parity for data bits is invalid (see Note). • A timing error occurred after the previous output of an acknowledgment bit. • The reception buffer is full and additional data cannot be received [JH1] (see Note). Note: Even in this case, the transmitting unit retries transmission of the relevant data field until the data reaches the maximum number of bytes of data that can be transmitted in one frame. 402 21.11 Transmission Data 21.11 Transmission Data The data field contains the transmission data specified by the control bits. ■ Transmission Data Table 21.11-1 Settings of Control Bits Bit 3*1 Bit 2 Bit 1 Bit 0 Function*2 0H 0 0 0 0 Slave status reading 1H 0 0 0 1 Undefined 2H 0 0 1 0 Undefined 3H 0 0 1 1 Data reading and locking 4H 0 1 0 0 Lock address reading (lower 8 bits) 5H 0 1 0 1 Lock address reading (higher 4 bits) 6H 0 1 1 0 Slave status reading and unlocking 7H 0 1 1 1 Data reading 8H 1 0 0 0 Undefined 9H 1 0 0 1 Undefined AH 1 0 1 0 Command writing and locking BH 1 0 1 1 Data writing and locking CH 1 1 0 0 Undefined DH 1 1 0 1 Undefined EH 1 1 1 0 Command writing FH 1 1 1 1 Data writing *1: The value of bit 3 (MSB) determines the direction of transmission of the text length bits in the text length field and the data in the data field. • When bit 3 is 1, data is transmitted from the master unit to the slave unit. • When bit 3 is 0, data is transmitted from the slave unit to the master unit. *2: 3H, 6H, AH, and BH are control bit settings for locking and unlocking. If an undefined value 1H, 2H, 8H, 9H, CH, or DH is transmitted, no acknowledgment is returned. 403 CHAPTER 21 IEBusTM CONTROLLER When a slave unit has been locked by the master unit, the unit rejects reception of data if the control bit value received from a unit other than the master unit is a value other than those values listed in Table 21.11-2 "Control Fields that can be Received by Locked Slave Units". Then the unit does not output an acknowledgment signal. Table 21.11-2 Control Fields that can be Received by Locked Slave Units Bit 3 Bit 2 Bit 1 Bit 0 Function 0H 0 0 0 0 Slave status reading 4H 0 1 0 0 Lock address reading (lower 8 bits) 5H 0 1 0 1 Lock address reading (higher 4 bits) ■ Reading Slave Status (SSR) (Control Bits: 0H or 6H) The master unit can know why the slave unit did not return the acknowledgment signal (ACK) by reading the slave status (control bit value: 0H or 6H). The slave status of a slave unit is determined in relation to the results of the last communication the slave unit executed. All slave units can provide slave status information. Figure 21.11-1 "Bit Configuration of Slave Status" shows the bit configuration of slave status information. Figure 21.11-1 Bit Configuration of Slave Status MSB Bit 7 404 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Bit 0 21.11 Transmission Data Table 21.11-3 Meanings of Slave Status Bit Bit 0*1 Bit 1*2 Value Meaning 0 The slave transmission buffer is empty. 1 The slave transmission buffer is not empty. 0 The slave reception buffer is not full. 1 The slave reception buffer is full. 0 The unit is not locked. 1 The unit is locked. 0 Always 0 0 Slave transmission is stopped. 1 Slave transmission is enabled. 0 Always 0 00 Mode 0 01 Mode 1 10 Mode 2 11 Setting inhibited Bit 2 Bit 3 Bit 4*3 Bit 5 Bits 6 and 7 These bits indicate the highest level of mode supported by the unit. *4 *1: The slave transmission buffer is the buffer that is accessed when data is read (control bit value: 3H or 7H). It corresponds to the write data buffer (WDB). *2: The slave reception buffer is the buffer that is accessed when data is written (control bit value: 8H, AH, BH, EH, or FH). It corresponds to the read data buffer (WDB). *3: The setting of this bit can be selected by the operation of the PCOM bit of the command register. *4: On the MB90580C series, the setting of these bits is always 10. ■ Transferring Data or Commands (Control Bits: 3H or 7H [Reading] or AH, BH, EH, or FH [Writing]) When the value of control bits is 3H or 7H (data reading), the data stored in the data buffer of the slave unit is read by the master unit. When the value of control bits is BH or FH (data writing) or AE or EH (command writing), the data received by a slave unit is processed according to the operation specifications of the slave unit. Remarks: 1. The user can freely specify the data or command to be transferred depending on the user system. 2. Under specific communication conditions or status, locking is set for the operations indicated by control bit values such as 3H, AH, and BH. 405 CHAPTER 21 IEBusTM CONTROLLER ■ Reading the Lock Address (Control Bits: 4H or 5H) When the value of control bits is 4H or 5H (lock address reading), the 12-bit address of the master unit that issued the relevant lock instruction is read. The address to be read has a onebyte structure as shown in Figure 21.11-2 "Structure of lock address". Figure 21.11-2 Structure of lock address Control bits: 4H Control bits: 5H Lower 8 bits Undefined M SB Higher 4 bits LSB ■ Locking and Unlocking The lock function is used when a unit transmits a message to another unit over multiple frames. A locked unit does not receive data from units other than the unit that locked it. Locking and unlocking are performed as follows: ❍ Locking A slave unit is locked by the master unit when a frame ends without all the data of the number of bytes specified by the text length bits transmitted or received after transmission and reception of the acknowledgment (ACK) for the text length field with a control bit value (3H, AH, or BH) specifying locking. If this occurs, bit 2 (indicating locking) among the slave status bits is set to 1. ❍ Unlocking A slave unit is unlocked by the master unit when all the data of the number of bytes specified by the text length bits was transmitted or received within one frame with a control bit value (3H, AH, or BH) specifying locking or (6H) specifying unlocking. If this occurs, bit 2 (indicating locking) among the slave status bits is cleared to 0. Locking and unlocking are not used for broadcast. 406 21.12 Bit Format 21.12 Bit Format IEBusTM sets synchronization in units of bits. The specifications of the time assigned to the whole bit and the time assigned to each period within each bit is dependent on the type of transmission bit and the type of unit, i.e., master or slave unit. During communication, each unit, master or slave, checks all periods (e.g., preparation, synchronization, and data periods) to determine whether each signal is output for the specified time. If a signal is not output for a specified time, the master or slave unit detects a timing error, stops communication immediately, and enters the standby state. ■ Bit Format Figure 21.12-1 "Bit Format of IEBusTM" shows the bit format of the frame of IEBusTM. Figure 21.12-1 Bit Format of IEBusTM Logic "1" Logic "0" Preparation Synchronizaperiod tion period Data period Stop period Synchroniza- Data tion period period Logic "1": The potential difference between bus wires (BUS+ and BUS- pins) is 20 mV or less (low level). The potential difference between bus wires (BUS+ and BUS- pins) is Logic "0": 120 mV or more (high level). First and following period in which the signal is at low level (logic "1") Preparation period: Synchronization loopback: Next period in which the signal is at high level (logic "0") Period in which the signal indicates a bit value (logic "1" [low level] or Data period: logic "0" [high level]) The synchronization period has almost the same length as the data period. 407 CHAPTER 21 IEBusTM CONTROLLER 408 CHAPTER 22 CLOCK MONITOR FUNCTION This chapter describes the functions and operation of the clock monitor. 22.1 "Overview of the Clock Monitor Functions" 22.2 "Clock Output Permission Register (CLKR)" 409 CHAPTER 22 CLOCK MONITOR FUNCTION 22.1 Overview of the Clock Monitor Functions The clock monitor function is to output from the CKOT pin a divided clock of tke machine clock(clock for monitoring) that is running in main clock , PLL clock, or subclock mode. ■ Block Diagram of the Clock Monitor Functions F2MC-16LX bus Figure 22.1-1 Block Diagram of the Clock Monitor Functions 410 CKEN Machine clock FRQ2 FRQ1 FRQ0 Frequency divider circuit P65/CKOT 22.2 Clock Output Permission Register (CLKR) 22.2 Clock Output Permission Register (CLKR) The bits of the clock output permission register (CLKR) are used for selection of the CKOT output permission and clock output frequency. ■ Clock Output Permission Register (CLKR) Figure 22.2-1 Clock Output Permission Register (CLKR) Clock output permission register 7 6 5 4 Address: 0003EH Read/write Initial value 3 2 CKEN FRQ2 (-) (-) (-) (-) (-) (-) (-) (-) 1 0 FRQ1 FRQ0 Bit No. CLKR (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) [Bit 3] CKEN The CKEN bit is the CKOT output permission bit. Table 22.2-1 Functions of CKEN Bit CKEN Function 0 Normal port 1 CKOT output [Bit 2,1,and 0] FRQ2, FRQ1, and FRQ0 The FRQ2, FRQ1, and FRQ0 bits are used to select the clock output frequency. Table 22.2-2 Functions of the FRQ2, FRQ1, and FRQ0 Bits FRQ2 FRQ1 FRQ0 Output clock φ = 16 MHz φ = 8 MHz φ = 4 MHz φ = 8 kHz 0 0 0 φ/21 125 ns 250 ns 500 ns 250 μs 0 0 1 φ/22 250 ns 500 ns 1 μs 500 μs 0 1 0 φ/23 500 ns 1 μs 2 μs 1 ms 0 1 1 φ/24 1 μs 2 μs 4 μs 2 ms 1 0 0 φ/25 2 μs 4 μs 8 μs 4 ms 1 0 1 φ/26 4 μs 8 μs 16 μs 8 ms 1 1 0 φ/27 8 μs 16 μs 32 μs 16 ms 1 1 1 φ/28 16 μs 32 μs 64 μs 32 ms 411 CHAPTER 22 CLOCK MONITOR FUNCTION 412 CHAPTER 23 ADDRESS MATCH DETECTION FUNCTION This chapter describes the address match detection function and operation. 23.1 "Overview of the Address Match Detection Function" 23.2 "Registers of the Address Match Detection Function" 23.3 "Operation of the Address Match Detection Function" 23.4 "Example of the Address Match Detection Function" 413 CHAPTER 23 ADDRESS MATCH DETECTION FUNCTION 23.1 Overview of the Address Match Detection Function When an address matches the value set in the address detection register, the instruction code to be read by the CPU is replaced with the INT9 instruction code (01H). Consequently, the CPU executes the INT9 instruction when executing a specified instruction. The address match detection function can be achieved using the INT9 interrupt routine for processing. There are two address detection registers, each with an interrupt permission bit. When an address matches the value set in the address detection register and the interrupt permission bit is 1, the instruction code to be read by the CPU is replaced with the INT9 instruction code. ■ Block Diagram of the Address Match Detection Function Address latch Address detection register Permission bit F2MC-16LX bus 414 Comparison Figure 23.1-1 Block Diagram of the Address Match Detection Function INT9 instruction F2MC-16LX CPU core 23.2 Registers of the Address Match Detection Function 23.2 Registers of the Address Match Detection Function The two types of registers for the address match detection function are as follows: • Program address detection registers (PADR0 and PADR1) • Program address detection control status register (PACSR) ■ Program Address Detection Registers (PADR0 and PADR1) The program address detection registers 0 and 1 (PADR0 and PADR1) compare the address with the value written in each register. If they match when the interrupt permission bit corresponding to ADCSR is 1, the CPU is requested to issue the INT9 instruction. When the corresponding interrupt bit is 0, nothing occurs. Figure 23.2-1 Program Address Detection Registers (PADR0 and PADR1) Program address detection registers byte byte byte Access Initial value PADR0 1FF2H/1FF1H/1FF0H R/W Not defined PADR1 1FF5H/1FF4H/1FF3H R/W Not defined Table 23.2-1 "Correspondence between PADR0 and PADR1 Registers and PACSR" lists the correspondence between the program address detection registers (PADR0 and PADR1) and PACSR. Table 23.2-1 Correspondence between PADR0 and PADR1 Registers and PACSR Address detection register Interrupt permission bit PADR0 AD0E PADR1 AD1E ■ Program Address Detection Control Status Register (PACSR) The program address detection control register (PACSR) controls the operation of the address detection function. Figure 23.2-2 Program Address Detection Control Register (PACSR) Program address detection control status register Address: 009EH Read/write Initial value 7 6 5 4 Reserved Reserved Reserved Reserved (-) (0) (-) (0) (-) (0) (-) (0) 3 2 1 0 AD1E Reserved AD0E Reserved (R/W) (0) (-) (0) (R/W) (0) (-) (0) Bit No. PACSR [Bits 7 to 4] Reserved bits Bits 7 to 4 are reserved. Set these bits to 0 before setting PACSR. [Bit 3] AD1E (Address Detect register 1 Enable) The AD1E bit is the operation permission bit of ADR1. When this bit is 1, the address is compared with the PADR1 register. If they match, the INT9 instruction is issued. 415 CHAPTER 23 ADDRESS MATCH DETECTION FUNCTION [Bit 2] Reserved bit Bit 2 is a reserved bit. When PACSR is set, be sure to set bit 2 to 0. [Bit 1] AD0E (Address Detect register 0 Enable) The AD0E bit is the operation permission bit of ADR0. When this bit is 1, the address is compared with the PADR0 register. If they match, the INT9 instruction is issued. [Bit 0] Reserved bit Bit 0 is a reserved bit. When PACSR is set, be sure to set bit 0 to 0. 416 23.3 Operation of the Address Match Detection Function 23.3 Operation of the Address Match Detection Function If the program counter specifies the same address as the address match detection register, the INT9 instruction is executed. The address match detection function can be achieved by processing the INT9 instruction routine. ■ Operation of the Address Match Detection Function There are two address detection registers with a compare enable bit. When the value set in the address detection register and the value of the program counter match and the compare enable bit is set to 1, the CPU executes the INT9 instruction. Note: If the value of the address detection register and the value of the program counter match, the contents of internal data bus is changed to 01H. Consequently, the INT9 instruction is executed. Before changing the contents of the address detection register, always set the compare enable bit to 0. While the compare enable bit is set to 1, changing the contents of the address detection register may result in a malfunction. 417 CHAPTER 23 ADDRESS MATCH DETECTION FUNCTION 23.4 Example of the Address Match Detection Function Figure 23.4-1 "System Configuration Example of the Address Match Detection Function" shows a system configuration example of the address match detection function. Table 23.4-1 "EEPROM Memory Map" lists the EEPROM memory map. ■ System Configuration Example of the Address Match Detection Function Figure 23.4-1 System Configuration Example of the Address Match Detection Function EEPROM MCU F2MC16LX SIN Pull-up resistor Connector (UART) Table 23.4-1 EEPROM Memory Map Address Description 0000H Number of bytes of patch program No.0 (If 0, no program error exists.) 0001H Program address No.0 bits 7 to 0 0002H Program address No.0 bits 15 to 8 0003H Program address No.0 bits 24 to 16 0004H Number of bytes of patch program No.1 (If 0, no program error exists.) 0005H Program address No.1 bits 7 to 0 0006H Program address No.1 bits 15 to 8 0007H Program address No.1 bits 24 to 16 0010H or higher Main body of patch program No. 0 ❍ Initial status EEPROM is set to all 0s. ❍ When a program error occurs: The main body of the patch program and program address are transferred to the MCU through the connector (UART). The MCU writes the information to EEPROM. 418 23.4 Example of the Address Match Detection Function ❍ Reset sequence The MCU reads the value of EEPROM after reset. If the number of bytes of the patch program is not 0, the main body of the patch program is read from EEPROM and written to RAM. The MCU then uses either PADR0 or PADR1 to set the patch address and sets the compare enable bit. If the relocatable patch program is required, the first address of the patched program can be written to the RAM area. In this case, the INT9 routine accesses this user-defined RAM area and jumps to the patched program. ❍ INT9 interrupt The interrupt routine can know the address where the interrupt occurs by checking the value of the stack program counter. The information that has been placed on the stack during the interrupt is discarded. ■ Example of program patch processing Figure 23.4-2 Example of program patch processing MB90580C FFFFFFH Abnormal program PC = address in error ROM External EEPROM Register set for program patch Number of program bytes Address where the interrupt occurs Corrected program Data transfer using UART Corrected program RAM 000000H 419 CHAPTER 23 ADDRESS MATCH DETECTION FUNCTION Figure 23.4-3 Flow of program patch processing Reset Reads 00H of EEPROM INT9 YES 0000H(EEPROM)=0 To patch program JMP 000400H NO Read address 0001H to 0003H (EEPROM) MOV PADR0 (MCU) Execute patch program 000400H to 000480H Read patch program 0010H to 0090H (EEPROM) MOV 000400H to 000480H (MCU) Terminate patch program JMP FF0050H Enable compare MOV PACSR, #02H Execute normal program NO PC=PADR0 YES INT9 MB90580C FFFFFFH FF0050H Abnormal program ROM EEPROM FF0000H FFFFH FE0000H 0090H Patch program 0010H 001100H Stack area 0003H 0002H 0001H 0000H 420 Program address low-order: Program address middle-order: Program address high-order: Number of bytes of the patch program: RAM area 00 00 000480H Patch program RAM 000400H RAM and register area FF 000100H I/O area 80 000000H CHAPTER 24 ROM MIRROR FUNCTION SELECTION MODULE This chapter describes the functions and operations of the ROM mirror function selection module. 24.1 "Overview of the ROM Mirror Function Selection Module" 24.2 "ROM Mirror Function Selection Register (ROMM)" 421 CHAPTER 24 ROM MIRROR FUNCTION SELECTION MODULE 24.1 Overview of the ROM Mirror Function Selection Module By setting a register, the ROM mirror function selection module can determine that bank FF containing the ROM is read in bank 00. ■ Block Diagram of the ROM Mirror Function Selection Module Figure 24.1-1 Block Diagram of the ROM Mirror Function Selection Module F2MC-16LX bus ROM mirror function selection register Address area Address Bank 00 Bank FF Data ROM 422 24.2 ROM Mirror Function Selection Register (ROMM) 24.2 ROM Mirror Function Selection Register (ROMM) Figure 24.2-1 "ROM Mirror Function Selection Register (ROMM)" shows the ROM mirror function selection register (ROMM). ■ ROM Mirror Function Selection Register (ROMM) Figure 24.2-1 ROM Mirror Function Selection Register (ROMM) ROM mirror register 15 14 13 12 11 10 9 Address: 00006F Read/write Initial value 8 MI (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) Bit No. ROMM (W) (1) Note: Do not access this register while the operation in addresses 004000H to 00FFFFH are ongoing. [Bit 8] MI When 1 is written to the MI bit, ROM data in bank FF can be read in bank 00. When 0 is written to this bit, processing such as memory mapping is not executed. This bit is written only. In single-chip mode and internal ROM external bus mode, the memory space is as follows. Note: Addresses FF4000H to FFFFFFH are mirrored to addresses 004000H to 00FFFFH only when the ROM mirror function is activated. Therefore, addresses FF0000H to FF3FFFH are not mirrored to bank 00. Table 24.2-1 Memory Space Address MB90583C/CA MB90F583C/CA MB90V580B MB90587C/CA Address 1 FF0000H FE0000H - FF0000H Address 2 001900H 001900H 001900H 001100H 423 CHAPTER 24 ROM MIRROR FUNCTION SELECTION MODULE Figure 24.2-2 Memory Space in Single-chip Mode Address FFFFFF Address 1 ROM area ROM area 010000 ROM area 004000 002000 Address 2 000100 0000C0 RAM area RAM area I/O area I/O area MI = 1 MI = 0 Internal area 000000 Figure 24.2-3 Memory Space in the Internal ROM External Bus Mode Address FFFFFF ROM area ROM area Address 1 010000 ROM area 004000 002000 Address 2 RAM area RAM area I/O area I/O area MI = 1 MI = 0 000100 0000C0 000000 424 Internal area External bus area CHAPTER 25 1M-BIT FLASH MEMORY This chapter describes the functions and operations of the 1M-bit flash memory. The following three methods are supported to write or delete data for the flash memory: • Parallel programmer • Serial programmer • Executing programs to write/erase data This chapter describes "Executing programs to write/erase data". 25.1 "Overview of the 1M-Bit Flash Memory" 25.2 "Sector Configuration of the Flash Memory" 25.3 "Flash Memory Control Status Register (FMCS)" 25.4 "Activating the Automatic Algorithm of the Flash Memory" 25.5 "Confirming the Automatic Algorithm Execution Status" 25.6 "Detailed Explanations of Flash Memory Writing and Deletion" 25.7 "Example of the 1M-Bit Flash Memory Program" 425 CHAPTER 25 1M-BIT FLASH MEMORY 25.1 Overview of the 1M-Bit Flash Memory The 1M-bit flash memory is allocated in banks FEH to FFH on the CPU memory map. As in mask ROM, it can be subjected to a read access and program access from the CPU using the flash memory interface circuit function. Because data can be written or deleted for the flash memory by instructions from the CPU through the flash memory interface circuit, data can be rewritten in the installation status by control of the internal CPU. This enables programs and data to be improved. Sector operations such as enable and sector protect cannot be used. ■ Features of the 1M-bit Flash Memory • Configuration of the 128 K words x 8 K or 64 K words x 16 bits (16 K + 8 K x 2 + 32 K + 64 K) sector • Automatic program algorithm (Embedded Algorithm: Same as for MBM29LV200) • Function for temporarily stopping deletion and function for restarting it • Detecting the completion of writing and deletion using the data polling and toggle bits • Deleting the completion of writing and deletion using CPU interrupts • Compatibility with the JEDEC standard commands • Enabling data to be deleted for each sector (combining sectors freely) • Number of times of writing or number of times of deletions (minimum): 10,000 • Flash read cycle time (Min.): 2 machine cycles Embedded Algorithm is a trademark of the Advanced Micro Device, Inc. ■ Writing and Deleting Data for the Flash Memory Writing or deletion and reading for the flash memory cannot occur at the same time. In other words, when data is written or deleted for the flash memory, writing only is possible by the following operation without a program access from the flash memory: the program on the flash memory is copied onto the RAM and the RAM is executed. ■ Flash Memory Register ❍ Flash memory control status register (FMCS) Bit No. Address: 0000AEH Read/write Initial value 426 7 6 5 4 3 2 1 0 INTE RDYINT WE RDY Reserved LPM1 Reserved LPM0 (R/W) (0) (R/W) (0) (R/W) (0) (R) (X) (W) (0) (R/W) (0) (W) (0) (R/W) (0) 25.2 Sector Configuration of the Flash Memory 25.2 Sector Configuration of the Flash Memory Figure 25.2-1 "Sector configuration of the 1M-bit flash memory" shows the sector configuration of the flash memory. ■ Sector configuration of the 1M-bit flash memory Figure 25.2-1 "Sector configuration of the 1M-bit flash memory" shows the sector configuration of the 1M-bit flash memory and the high-order and low-order addresses of each sector. For access from the CPU, SA0 is stored in the FE bank register and SA1 to SA4 are stored in the FF bank register. Figure 25.2-1 Sector configuration of the 1M-bit flash memory Flash memory CPU address Programmer address(*) FFFFFFH 7FFFFH FFC000H FFBFFFH 7C000H 7BFFFH FFA000H FF9FFFH 7A000H 79FFFH FF8000H FF7FFFH 78000H 77FFFH FF0000H FEFFFFH 70000H FE0000H 60000H SA4 (16 Kbytes) SA3 (8 Kbytes) SA2 (8 Kbytes) SA1 (32 Kbytes) SA0 (64 Kbytes) 6FFFFH *: A programmer address is associated with a CPU address when data is written in the flash memory by the parallel programmer. This address is used to perform writing or deletion using the generalpurpose programmer. 427 CHAPTER 25 1M-BIT FLASH MEMORY 25.3 Flash Memory Control Status Register (FMCS) The control status register (FMCS) exists in the flash memory interface circuit and is used for flash memory writing and deletion. ■ Control Status Register (FMCS) Bit No. Address: 0000AEH Read/write Initial value 7 6 5 4 3 2 1 0 INTE RDYINT WE RDY Reserved LPM1 Reserved LPM0 (R/W) (0) (R/W) (0) (R/W) (0) (R) (X) (W) (0) (R/W) (0) (W) (0) (R/W) (0) ❍ Bits [Bit 7] INTE (INTerrupt Enable) Used to generate an interrupt to the CPU at the end of flash memory writing or deletion. An interrupt to the CPU occurs when the INTE bit is 1 and RDYINT bit is 1. No interrupt occurs if the INTE bit is 0. 0: Disables an interrupt at the end of writing or deletion. 1: Enables an interrupt at the end of writing or deletion. [Bit 6] RDYINT (ReaDY INTerrupt) Used to indicate the flash memory operation status. This bit is set to 1 after the end of flash memory writing or deletion. Flash memory writing or deletion is impossible while this bit is 0 after flash memory writing or deletion. If this bit is set to 1 after writing or deletion ends, flash memory writing or deletion is possible. This bit is cleared to 0 by writing 0. Writing 1 is ignored. This bit is set to 1 when the automatic algorithm of the flash memory (see Section 25.4 "Activating the Automatic Algorithm of the Flash Memory") ends. Value 1 can be read when the read modify write (RMW) instruction is used. 0: Indicates that writing or deletion is ongoing. 1: Indicates that writing or deletion ends. (Interrupt request generation) [Bit 5] WE (Write Enable) Used to enable writing to the flash memory area. When this bit is 1, writing to the flash memory area is set after the command sequence to banks FC to FF (see Section 25.4 "Activating the Automatic Algorithm of the Flash Memory") is issued. When this bit is 0, no signals for writing and deletion are generated. This bit is used to activate the commands for flash memory writing and deletion. When neither writing nor deletion is executed, it is recommended that this bit always be set to 0 so that no data is written in the flash memory by mistake. 0: Disables flash memory writing and deletion. 428 25.3 Flash Memory Control Status Register (FMCS) 1: Enables flash memory writing and deletion. [Bit 4] RDY (ReaDY) Used to enable flash memory writing or deletion. While this bit is 0, writing and deletion are impossible for the flash memory. In this status, a read command, reset command, and suspend commands such as sector deletion temporary stop can be accepted. 0: Indicates that writing or deletion is ongoing (writing or deletion of the next data is impossible). 1: Indicates that the writing or deletion ends (writing or deletion of the next data is possible). [Bit 3] Reserved bit Reserved for testing. Set this bit to 0 for normal use. [Bits 1] Free bits Set these bits to 0 for normal use. [Bit 2 and 0] LPM1, LPM0 (Low Power Mode) LPM1 and LPM0 bits can be used to control power consumption of the flash memory. However, because the time for access from the CPU to the flash memory is very dependent on the setting, select the setting value according to the operation frequency of the CPU. 01: Low-power consumption mode (operation at internal operation frequency of 4 MHz or less) 10: Low-power consumption mode (operation at internal operation frequency of 8 MHz or less) 11: Low-power consumption mode (operation at internal operation frequency of 12.58 MHz or less) 00: Ordinary power consumption mode (operation at internal operation frequency of 16 MHz or less) Note: The RDYINT and RDY bits do not change at the same time. Create a program so that one or the other is used. Automatic algorithm End timing RDYINT bit RDY bit 1 machine cycle 429 CHAPTER 25 1M-BIT FLASH MEMORY 25.4 Activating the Automatic Algorithm of the Flash Memory To activate the automatic algorithm of the flash memory, the following four types of commands are supported: read, reset, writing, and chip deletion. For the sector deletion, temporary stop and restart can be controlled. ■ Command Sequence Table Table 25.4-1 "Command Sequence Table" lists the commands used for flash memory writing and deletion. All data items to be written in the command register are in byte units. However, write data by word access. In this case, the data for high-order bytes is ignored. Table 25.4-1 Command Sequence Table Command sequence Bus write access 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle Address Data Address Data Address Data Address Data Address Data Address Data Read or Reset (*) 1 FxXXXX XXF0 - - - - - - - - - - Read or Reset (*) 4 FxAAAA XXAA Fx5554 XX55 FxAAAA XXF0 RA RD - - - - Write program 4 FxAAAA XXAA Fx5554 XX55 FxAAAA XXA0 PA (even) PD (word) - - - - Chip deletion 6 FxAAAA XXAA Fx5554 XX55 FxAAAA XX80 FxAAAA XXAA Fx5554 XX55 FxAAAA XX10 6 FxAAAA XXAA Fx5554 XX55 FxAAAA XX80 FxAAAA XXAA Fx5554 XX55 SA (even) XX30 Sector deletion Sector deletion temporary stop Sector deletion restart Auto-select 3 FxAAA Sector deletion temporarily stops by input of address FxXXXX data (xxB0H). After a temporary stop of the sector deletion, deletion starts by the input of address FxXXXX data (xx30H). XXAA Fx5554 XX55 FxAAAA XX90 - - - - - Note: • Address Fx in the table indicates FF or FE. For each operation, use a value of the bank to be accessed. • An address in the table is a value on the CPU memory map. All addresses and data are represented in hexadecimal. However, X is any value. • RA: Read address • PA: Only a write address and even address can be specified. • SA: Sector address. See Section 25.2 "Sector Configuration of the Flash Memory". • RD: Read data • PD: Only write data and word data can be specified. *: Both read and reset commands can reset the flash memory to the read mode. 430 - 25.4 Activating the Automatic Algorithm of the Flash Memory The Auto-select command shown in Table 25.4-1 "Command Sequence Table" is used to know the state of sector protection. When using the Auto-select command, set the address as follows. Table 25.4-2 Address Setting at Auto-select Sector protection AQ13 to AQ16 AQ7 AQ2 AQ1 AQ0 DQ7 to DQ0 Sector Address L H L L CODE* *: When the sector address is protected, the output is "01H". When the sector address is not protected, the output is "00H". 431 CHAPTER 25 1M-BIT FLASH MEMORY 25.5 Confirming the Automatic Algorithm Execution Status To provide the writing or deletion flow with an automatic algorithm, the flash memory contains hardware that notifies an operator of the operating status or of operation completion within the flash memory. This automatic algorithm enables the operating status of the built-in flash memory to be confirmed using the following hardware sequence: ■ Hardware Sequence Flag The hardware sequence flag consists of the 5-bit outputs DQ7, DQ6, DQ5, DQ3, and DQ2 which have functions of the data polling flag (DQ7), toggle bit flag (DQ6), timing limit excess flag (DQ5), sector deletion timer flag (DQ3), and toggle bit 2 flag (DQ2), thereby enabling an operator to confirm whether the end of writing, the end of chip or sector deletion, and deletion code writing are valid. The hardware sequence flag can be referenced by a read access to the address of the target sector within the flash memory after the command sequence (see Table 25.4-1 "Command Sequence" in Section 25.4 "Activating the Automatic Algorithm of the Flash Memory") is set. 25.5-1 "Bit Allocation for the Hardware Sequence Flags" shows the bit allocation for the hardware sequence flags. Table 25.5-1 Bit Allocation for the Hardware Sequence Flags Bit No. 7 6 5 4 3 2 1 0 Hardware sequence flag DQ7 DQ6 DQ5 - DQ3 DQ2 - - To determine whether automatic writing or chip or sector deletion is ongoing, check the hardware sequence flag or the RDY bit of the flash memory control register (FMCS), thereby enabling the operator to determine whether the writing ends. After the writing or deletion is completed, the read or reset status is returned. To create a program, perform the next processing such as data reading after confirming the end of the automatic writing or deletion using either of the flags. The hardware sequence flag can be used to confirm whether the second and subsequent sector deletion code writings are valid. The subsequent sections explain the hardware sequence flags. Table 25.5-2 "Hardware Sequence Flag Functions" lists the hardware sequence flag functions. 432 25.5 Confirming the Automatic Algorithm Execution Status Table 25.5-2 Hardware Sequence Flag Functions DQ7 DQ6 DQ5 DQ3 DQ2 DQ7 --> DATA:7 Toggle --> DATA:6 0 --> DATA:5 0 --> DATA:3 1 --> DATA:2 0 --> 1 Toggle --> Stop 0 --> 1 1 Toggle --> Stop Sector deletion wait --> deletion start 0 Toggle 0 0 --> 1 Toggle Deletion --> temporary stop of sector deletion (Sector being deleted) 0 --> 1 Toggle --> 1 0 1 --> 0 Toggle Temporary stop of sector deletion -> deletion restart (Sector being deleted) 1 --> 0 1 --> Toggle 0 0 --> 1 Toggle Temporary stop of sector deletion ongoing (Sector not being deleted) DATA:7 DATA:6 DATA:5 DATA:3 DATA:2 DQ7 Toggle 1 0 1 0 Toggle 1 1 *1 Status Status change at normal operation Abnormal operation Writing --> writing completion (At write address specification) Chip or sector deletion --> deletion completion Writing Chip or sector deletion operation Note: If the DQ5 outputs "1" (exceed the timing limit), successive reads from a writing or erasing sector cause DQ2 to toggle. DQ2 does not toggle when the successive reads are executed from other sectors. 433 CHAPTER 25 1M-BIT FLASH MEMORY 25.5.1 Data Polling Flag (DQ7) Using the data polling function, the data polling flag (DQ7) notifies an operator that the automatic algorithm execution is ongoing or ends. ■ Data Polling Flag (DQ7) Table 25.5-3 "Status Transition of the Data Polling Flag (Status Changes At Normal Operation" and Table 25.5-4 "Status Transition of the Data Polling Flag (Status Changes at Abnormal Operation)" list the transitions of data polling flag statuses. Table 25.5-3 Status Transition of the Data Polling Flag (Status Changes At Normal Operation) Operation status Writing --> completion DQ7 DQ7 --> DATA:7 Chip or sector deletion --> completion Sector deletion wait --> start Sector deletion --> temporary stop of deletion Sector being deleted Temporary stop of sector deletion --> restart Sector being deleted Temporary stop of sector deletion ongoing Sector not being deleted 0 --> 1 0 0 --> 1 1 --> 0 DATA:7 Table 25.5-4 Status Transition of the Data Polling Flag (Status Changes at Abnormal Operation) Operation status Writing Chip or sector deletion DQ7 DQ7 0 ❍ At writing If a read access is made while the automatic write algorithm is executed, the flash memory outputs the reverse data of bit 7 of the data last written, regardless of the indicated address. If a read access is made when the automatic write algorithm ends, the flash memory outputs bit 7 of the read value of the indicated address. ❍ At chip or sector deletion The flash memory outputs 0 while the chip deletion or sector deletion algorithm is executed if a read access is made from the deleted sector at sector deletion or a read access is made regardless of the indicated address at chip deletion. Similarly, the flash memory outputs 1 at the end of the operation. ❍ At temporary stop of sector deletion The flash memory outputs 1 if a read access is made at temporary stop of sector deletion and the indicated address specifies the sector being deleted. If the indicated address does not specify the sector being deleted, the flash memory outputs bit 7 (DATA:7) of the read value of the indicated address. Referencing this bit together with the toggle bit flag (DQ6) enables the operator to determine whether the sector stops temporarily or which sector is being deleted. 434 25.5 Confirming the Automatic Algorithm Execution Status Note: At activation of the automatic algorithm, a read access to the specified address is ignored. At data reading, other bits can be output when the data polling flag (DQ7) ends. Therefore, after the automatic algorithm ends, data must be read following the read access for which the end of data polling is confirmed. 435 CHAPTER 25 1M-BIT FLASH MEMORY 25.5.2 Toggle Bit Flag (DQ6) Using the toggle bit function, the toggle bit flag (DQ6) informs an operator that the automatic algorithm execution is ongoing or ends, as with the data polling flag (DQ7). ■ Toggle Bit Flag (DQ6) Table 25.5-5 "Status Transition of The Toggle Bit Flag (Status Changes at Normal Operation)" and Table 25.5-6 "Status Transition of the Toggle Bit Flag (Status Changes at Abnormal Operation" show status transitions of the toggle bit flag. Table 25.5-5 Status Transition of The Toggle Bit Flag (Status Changes at Normal Operation) Operation status Writing --> completion Chip or sector deletion --> completion DQ6 Toggle --> DATA:6 Toggle --> Stop Sector deletion wait --> start Sector deletion --> temporary stop of deletion Sector being deleted Temporary stop of sector deletion --> restart Sector being deleted Temporary stop of sector deletion ongoing Sector not being deleted Toggle Toggle --> 1 1 --> Toggle DATA:6 Table 25.5-6 Status Transition of the Toggle Bit Flag (Status Changes at Abnormal Operation) Operation status Writing Chip or sector deletion DQ6 Toggle Toggle ❍ At writing or at chip or sector deletion Assume that read access is made continuously while the automatic write algorithm or chip or sector deletion algorithm is executed. In this case, the flash memory outputs the toggle status in which 1 and 0 are alternately output for each read access, regardless of the indicated address. If read access is made continuously at the end of the automatic write algorithm or chip or sector deletion algorithm, the flash memory stops the toggle operation of bit 6 and outputs bit 6 (DATA:6) of the read value of the indicated address. 436 25.5 Confirming the Automatic Algorithm Execution Status ❍ At temporary stop of sector deletion When a read access is made at temporary stop of sector deletion, the flash memory outputs 1 if the indicated address belongs to the sector being deleted. If the address does not belong to the sector being deleted, the flash memory outputs bit 6 (DATA:6) of the read value of the indicated address. Reference: At writing, if the sector in which an attempt is made to write data is protected against rewriting, the toggle operation ends without rewriting data after the toggle operation of about 2 μs is performed. At deletion, if all selected sectors are protected against rewriting, the toggle bits involve the toggle operation of about 100 μs, and then the read or reset status is returned without rewriting data. 437 CHAPTER 25 1M-BIT FLASH MEMORY 25.5.3 Timing Limit Excess Flag (DQ5) The timing limit excess flag (DQ5) informs the operator that the automatic algorithm execution exceeded the time specified within the flash memory (number of internal pulses). ■ Timing Limit Excess Flag (DQ5) Table 25.5-7 "Status Transition of The Timing Limit Excess Flag (Status Changes at Normal Operation)" and Table 25.5-8 "Status Transition of the Timing Limit Excess Flag (Status Changes at Abnormal Operation)" show status transitions of the timing limit excess flag. Table 25.5-7 Status Transition of The Timing Limit Excess Flag (Status Changes at Normal Operation) Operation status Writing --> completion DQ5 0 --> DATA:5 Chip or sector deletion --> completion Sector deletion wait --> start Sector deletion --> temporary stop of deletion Sector being deleted Temporary stop of sector deletion --> restart Sector being deleted Temporary stop of sector deletion ongoing Sector not being deleted 0 --> 1 0 0 0 DATA:5 Table 25.5-8 Status Transition of the Timing Limit Excess Flag (Status Changes at Abnormal Operation) Operation status Writing Chip or sector deletion DQ5 1 1 ❍ At writing or chip or sector deletion Assume that a read access is made after the automatic algorithm for the writing or chip or sector deletion is activated. The flag outputs 0 when the automatic algorithm execution is within the specified time (required for writing or deletion). It outputs 1 if the automatic algorithm execution exceeds the specified time. This output does not depend on whether the automatic algorithm is being executed or ends; therefore, the operator can determine whether the writing or deletion is successful. In other words, if this flag is 1, and the automatic algorithm is being executed by the data polling function or toggle bit function, the operator is able to recognize that the writing has failed. For example, if an attempt is made to write 1 in the flash memory address in which 0 is already written, a fail occurs. In this case, the flash memory is locked and the automatic algorithm does not end. Therefore, no valid data is output from the data polling flag (DQ7). The toggle bit flag (DQ6) does not stop the toggle operation and the time limit is exceeded. The timing limit excess flag (DQ5) outputs 1. This status indicates that the flash memory is not faulty and that it was not used correctly. If this status occurs, execute the reset command. 438 25.5 Confirming the Automatic Algorithm Execution Status 25.5.4 Sector Deletion Timer Flag (DQ3) The sector deletion timer flag (DQ3) informs an operator whether the sector deletion wait period is ongoing after the sector deletion command is activated. ■ Sector Deletion Timer Flag (DQ3) Table 25.5-9 "Status Transition of the Sector Deletion Timer Flag (Status Changes at Normal Operation)" and Table 25.5-10 "Status Transition of the Sector Deletion Timer Flag (Status Changes at Abnormal Operation)" show status transitions of the sector deletion timer flag. Table 25.5-9 Status Transition of the Sector Deletion Timer Flag (Status Changes at Normal Operation) Operation status Writing --> completion DQ3 0 --> DATA:3 Chip or sector deletion --> completion Sector deletion wait --> start Sector deletion --> temporary stop of deletion Sector being deleted Temporary stop of sector deletion --> restart Sector being deleted Temporary stop of sector deletion ongoing Sector not being deleted 1 0 --> 1 1 --> 0 0 --> 1 DATA:3 Table 25.5-10 Status Transition of the Sector Deletion Timer Flag (Status Changes at Abnormal Operation) Operation status Writing Chip or sector deletion DQ3 0 1 ❍ At sector deletion Assume that a read access is made after the sector deletion command is activated. The flash memory outputs 0 if the sector deletion wait period is ongoing or it outputs 1 if this period is exceeded, regardless of the address indicated by the address signal of the sector for which the command was issued. When the data polling or toggle bit function indicates that the deletion algorithm execution is ongoing, if this flag is 1, the deletion to be internally controlled is starting. Any command other than the subsequent sector deletion code writing or temporary stop of deletion is ignored until the deletion ends. If this flag is 0, the flash memory accepts the writing of the additional sector deletion code. To confirm this, it is recommended to check the status of this flag before the subsequent sector deletion code writing. If the flag status is 1 at the second status check, the deletion code of the added sector may not be accepted. ❍ At sector deletion When a read access is made during temporary stop of sector deletion, the flash memory outputs 1 if the indicated address belongs to the sector being deleted. If it does not belong to the sector being deleted, the flash memory outputs bit 3 (DATA:3) of the read value of the indicated address. 439 CHAPTER 25 1M-BIT FLASH MEMORY 25.5.5 Toggle Bit 2 Flag (DQ2) The toggle bit 2 flag (DQ2) is a flag that uses the toggle bit function to indicate that the sector is in the erase-suspended state. ■ Toggle Bit 2 Flag (DQ2) Table 25.5-11 "Toggle Bit 2 Flag State Transitions (State Change for Normal Operation)" and Table 25.5-12 "Toggle Bit 2 Flag State Transitions (State Change for Abnormal Operation)" list the state transitions of the toggle bit flag. Table 25.5-11 Toggle Bit 2 Flag State Transitions (State Change for Normal Operation) Operating state Write --> Completed Chip/sector erase --> Completed DQ2 1 --> DATA:2 Toggle --> Stop Sector erase wait --> Started Sector erase --> Erase suspend (sector being erased) Sector erase suspend --> Restarted (sector being erased) Sector erase suspended (sector not being erased) Toggle Toggle Toggle DATA:2 Table 25.5-12 Toggle Bit 2 Flag State Transitions (State Change for Abnormal Operation) Operating state Write Chip/sector erase DQ2 1 *1 *1: If the DQ5 outputs "1" (exceed the timing limit), successive reads from a writing or erasing sector cause DQ2 to toggle. DQ2 does not toggle when the successive reads are executed from other sectors. ❍ During a sector erase operation If successive reads are executed during the execution of the chip sector erase algorithm, a flash memory toggles to output "1" and "0" to addresses alternately at every read access regardless of the location indicated by the addresses. If successive reads are executed after the chip sector erase algorithm is completed, the flash memory stops the toggle operation of the bit 2 and outputs the read value of the bit 2 (DATA: 2) to the location indicated by the address. 440 25.5 Confirming the Automatic Algorithm Execution Status ❍ While a sector erase operation is suspended If successive reads are executed while a sector erase operation is suspended, and if the address indicates the sector to be erased, the flash memory toggles to alternately output "1" and "0". If the address indicates the sector is not to be erased, the flash memory outputs the read value of the bit 2 (DATA: 2) to the location indicated by the address. In the erase-suspend-program mode, successive reads from the non-erase suspended sector causes the flash memory to output "1". Both DQ2 and DQ6 are used for detecting an erase-suspended sector (DQ2 toggles, but DQ6 does not). DQ2 is also used for detecting an erasing sector. While erasing a sector, if a read access is executed from the erasing sector, DQ2 toggles. Reference: If all sectors selected for erasing are write-protected, the toggle bit 2 toggles for about 100μs, and then returns to the read/reset mode without writing the data. 441 CHAPTER 25 1M-BIT FLASH MEMORY 25.6 Detailed Explanations of Flash Memory Writing and Deletion This section describes procedures that are provided by issuing commands that activate the automatic algorithm. The procedures are reading and reset, writing, chip deletion, sector deletion, temporary stop of sector deletion, and restart of sector deletion with regard to the flash memory. ■ Detailed Explanation of Flash Memory Writing and Deletion The flash memory can execute the automatic algorithm when the reading, reset, writing, chip deletion, sector deletion, temporary stop of deletion, or restart of deletion performs write cycles for the bus of the command sequence (see Table 25.4-1 "Command Sequence" in Section 25.4 "Activating the Automatic Algorithm of the Flash Memory"). Write cycles for each bus must be performed continuously. The end of the automatic algorithm can be determined by the data polling function. After normal operation, the read or reset status is returned. The subsequent sections explain the operations in the following order: 442 • Setting reading and reset status • Writing data • Deleting all data items (deleting all chips) • Deleting any data item (deleting a sector) • Stopping sector deletion temporarily • Restarting sector deletion 25.6 Detailed Explanations of Flash Memory Writing and Deletion 25.6.1 Setting the Flash Memory in the Read or Reset Status This section describes the procedure for setting the flash memory in the read or reset status by issuing the read or reset command. ■ Setting the Flash Memory to the Read or Reset Status The flash memory can be set to the read or reset status by continuously sending read or reset commands, listed in the command sequence table (see Table 25.4-1 "Command Sequence" in Section 25.4 "Activating the Automatic Algorithm of the Flash Memory"), to the target sector in the flash memory. The read and reset commands have the following two command sequence types: one-bus operation and three-bus operation, though there is no essential difference between the two. The read and reset statuses are initial statuses of the flash memory. At power-on or normal operation of the command, the flash memory is always set to a read and reset status. In these statuses, the system waits for other commands to be input. In the read and reset statuses, data can be read by an ordinary read access. As with the mask ROM, a program access from the CPU is possible. The read and reset commands are not needed to read data at ordinary reading. If a command does not end normally, these commands are used primarily to initialize the automatic algorithm. 443 CHAPTER 25 1M-BIT FLASH MEMORY 25.6.2 Writing Data in the Flash Memory This section describes the procedure for writing data in the flash memory issuing the write command. ■ Writing Data in the Flash Memory The data writing automatic algorithm of the flash memory can be activated by continuously sending the write command, listed in the command sequence table (see Table 25.4-1 "Command Sequence" in Section 25.4 "Activating the Automatic Algorithm of the Flash Memory"), to the target sector in the flash memory. When the data writing to the target address ends in the fourth cycle, the automatic algorithm is activated and the automatic writing starts. ❍ Addressing Only an even address is possible as the write address to be specified in the write data cycle. If an odd address is specified, data cannot be written correctly. In other words, writing to the even address in word data units is required. Writing is possible in any address order and outside the sector boundary. However, only oneword data can be written by one execution of the write command. ❍ Notes on writing data Data 0 cannot be returned to data 1 by writing. If data 1 is written in data 0, the data polling algorithm (DQ7) or toggle operation (DQ6) does not end and the flash memory element is determined to be faulty. The timing limit excess flag (DQ6) assumes an error because the specified writing time is exceeded, or it seems as if data 1 is written. However, if data is read in the read or reset status, data remains 0. Only a deletion operation can set data 0 to 1. During automatic writing, all commands are ignored. Note that if the hardware reset is activated during writing, the data written in the address is not guaranteed. ■ Procedure for Writing Data in the Flash Memory Figure 25.6-1 "Example of the Procedure for Flash Memory Writing" shows an example of the flash memory writing. The status of the automatic algorithm in the flash memory can be determined using the hardware sequence flag (see Section 25.5 "Confirming the Automatic Algorithm Execution Status"). The data polling flag (DQ7) is used to confirm the end of writing. The data to be read for flag checking is read from the address in which the last writing was made. The data polling flag (DQ7) changes when the timing limit excess flag (DQ5) changes. Therefore, even if the timing limit excess flag (DQ5) is 1, the data polling bit flag bit (DQ7) must be rechecked. Similarly, the toggle bit flag (DQ6) stops the toggle operation when the timing limit excess flag bit (DQ5) changes to 1. Therefore, the toggle bit flag (DQ6) must be rechecked. 444 25.6 Detailed Explanations of Flash Memory Writing and Deletion Figure 25.6-1 ExampleoftheProcedureforFlashMemoryWriting Start of writing FMCS: WE (bit 5) Flash memory writing enabled Write command sequence (1) FxAAAA <-- XXAA (2) Fx5554 <-- XX55 (3) FxAAAA <-- XXA0 (4) Write address <-- Write data Internal address reading Data polling (DQ7) Next address Data Data 0 Timing limit (DQ5) 1 Internal address reading Data Data polling (DQ7) Data Write error Last address FMCS: WE (bit 5) Flash memory writing disabled Completion of writing Confirmation by the hardware sequence flag 445 CHAPTER 25 1M-BIT FLASH MEMORY 25.6.3 Deleting all Data Items from the Flash Memory (Chip Deletion) This section describes the procedure for deleting all data items from the flash memory issuing the chip deletion command. ■ Deleting the Data From the Flash Memory (Chip Deletion) All data items can be deleted from the flash memory by continuously sending chip deletion commands, listed in the command sequence table (see Table 25.4-1 "Command Sequence" in Section 25.4 "Activating the Automatic Algorithm of the Flash Memory"), to the target sector within the flash memory. The chip deletion command is executed by six bus operations. The chip deletion starts when the writing in the 6th cycle is completed. Before the chip deletion, the user need not perform writing in the flash memory. During execution of the automatic deletion algorithm, the flash memory performs verification by writing 0 before automatically deleting all cells. 446 25.6 Detailed Explanations of Flash Memory Writing and Deletion 25.6.4 Deleting any Data Item from the Flash Memory (Sector Deletion) This section describes the procedure for deleting a data item from the flash memory (sector deletion) by issuing the sector deletion command. Data can be deleted for each sector and two or more sectors can be specified at the same time. ■ Flash Memory from which any Data Item is Deleted (Sector Deletion) Any sector can be deleted from the flash memory by continuously sending sector deletion commands, listed in the command sequence table (see Table 25.4-1 "Command Sequence" in Section 25.4 "Activating the Automatic Algorithm of the Flash Memory"), to the target sector within the flash memory. ❍ Specifying a sector The sector deletion command is executed by six bus operations. The sector deletion wait of 50 µs starts, in the 6th cycle, by writing the sector deletion code (30H) into any even address that can be accessed within the target sector. To delete two or more sectors, write the deletion code (30H) in the address within the target sector to be deleted in accordance with the above processing. ❍ Notes on specifying two or more sectors The deletion starts when the sector deletion wait period of 50 μs from the writing of the last sector deletion code is completed. In other words, to delete two or more sectors at the same time, the address of the next deletion sector and the deletion code (6th cycle of the command sequence) each must be input within 50 μs. If this limit is exceeded, the address and code may not be accepted. The sector deletion timer (hardware sequence flag DQ3) can be used to check whether the writing of the subsequent sector deletion code is valid. In this case, set the address for reading the sector deletion timer so that it indicates the sector to be deleted. ■ Procedure for Deleting a Sector from the Flash Memory The status of the automatic algorithm within the flash memory can be determined using the hardware sequence flag (see Section 25.5 "Confirming the Automatic Algorithm Execution Status"). Figure 25.6-2 "Example of the Procedure for Deleting a Sector from the Flash Memory" shows an example of the procedure for deleting a flash memory sector. The toggle bit flag (DQ6) is used to confirm the end of deletion. Note that the data to be read for flag checking is read from the sector to be deleted. The toggle bit flag (DQ6) stops the toggle operation when the timing limit excess flag (DQ5) changes to 1. Therefore, even if the timing limit excess flag (DQ5) is 1, the toggle bit flag (DQ6) must be rechecked. Similarly, because the data polling flag (DQ7) changes when the timing limit excess flag (DQ5) changes, it must be rechecked. 447 CHAPTER 25 1M-BIT FLASH MEMORY Figure 25.6-2 Example of the Procedure for Deleting a Sector from the Flash Memory Start of deletion FMCS: WE (bit 5) Flash memory deletion enabled Deletion command sequence (1) FxAAAA <-- XXAA (2) Fx5554 <-- XX55 (3) FxAAAA <-- XX80 (4) FxAAAA <-- XXAA (5) Fx5554 <-- XX55 (6) Code input to deletion sector (30H) Y Is there another deletion sector? N Internal address read 1 Y Next sector Internal address read 2 N Toggle bit (DQ6) Data 1 (DQ6) = data 2 (DQ6) Sector Erase Completed ? Y N 0 Timing limit (DQ5) 1 Internal address read 1 Internal address read 2 N Toggle bit (DQ6) Data 1 (DQ6) = data 2 (DQ6) Y Deletion error Last sector N Y FMCS: WE (bit 5) Flash memory deletion disabled Completion of deletion 448 Confirmation by the hardware sequence flag 25.6 Detailed Explanations of Flash Memory Writing and Deletion 25.6.5 Temporarily Stopping the Sector Deletion from the Flash Memory This section describes the procedure for temporarily stopping the sector deletion from the flash memory by issuing the sector deletion temporary stop command. Data can be read from the sector not being deleted. ■ Temporarily Stopping the Sector Deletion from the Flash Memory The sector deletion from the flash memory can be temporarily stopped by continuously sending sector deletion temporary stop commands, listed in the command sequence table (see Table 25.4-1 "Command Sequence" in Section 25.4 "Activating the Automatic Algorithm of the Flash Memory"), to the flash memory. The sector deletion temporary stop command temporarily stops the sector deletion to enable data to be read from the sector not being deleted. In this status, only reading is possible (writing is not possible). This command is valid only during sector deletion, including deletion wait time, and is ignored during chip deletion or writing. This command is executed by writing the deletion temporary stop code (B0H). However, any address in the flash memory must be indicated. The reexecution of the deletion temporary stop command is ignored for the temporary stop of the deletion. If the sector deletion temporary command is input during the sector deletion wait period, the sector deletion wait ends immediately and deletion is suspended. The deletion stop status is entered. If the deletion temporary stop command is input during sector deletion after the sector deletion wait period, the deletion temporary stop status is entered after the maximum time of 15 μs. 449 CHAPTER 25 1M-BIT FLASH MEMORY 25.6.6 Restarting the Flash Memory Sector Deletion This section describes the procedure for restarting the flash memory sector deletion temporarily stopped by issuing the sector deletion restart command. ■ Restarting the Flash Memory Sector Deletion The sector deletion temporarily stopped can be restarted by continuously sending sector deletion restart commands, listed in the command sequence table (see Table 25.4-1 "Command Sequence" in Section 25.4 "Activating the Automatic Algorithm of the Flash Memory"), to the flash memory. The sector deletion restart command is used to restart the sector deletion from the sector deletion temporary stop status set by the sector deletion temporary stop command. This command is executed by writing the deletion restart command (30H). However, any address in the flash memory area must be indicated. The issuance of the sector deletion restart command is ignored during sector deletion. 450 25.7 Example of the 1M-Bit Flash Memory Program 25.7 Example of the 1M-Bit Flash Memory Program This section provides an example of the 1M-bit flash memory program. ■ Example of the 1M-bit Flash Memory Program NAME FLASHWE TITLE FLASHWE ;------------------------------------------------------------------;1M-bit FLASH sample program ; ;1: Transferring the program (address FFBC00H, sector SA4) ; in FLASH to the RAM (address 000700H) ;2: Executing the program on the RAM ;3: Writing a PDR1 value to FLASH (address FE0000H, sector SA0) ;4: Reading the written value (address FE0000H, sector SA0) and ; outputting it to PDR2 ;5: Deleting the written sector (SA0) ;6: Outputting the deletion data confirmation ; Conditions ; -Number of RAM transfer bytes: 100H (256B) ; -Judgment for the end of writing and deletion ; Judgment with DQ5 (timing limit excess flag) ; Judgment with DQ6 (toggle bit flag) ; Judgment with RDY (FMCS) ; -Error handling ; Outputting Hi to P00 to P07 ; Issuing the reset command ;------------------------------------------------------------------; RESOUS IOSEG ABS=00 ;Definition of the RESOUS I/O ORG 0000H segment PDR0 RB 1 PDR1 RB 1 PDR2 RB 1 PDR3 RB 1 ORG 0010H DDR0 RB 1 DDR1 RB 1 DDR2 RB 1 DDR3 RB 1 ORG 00A1H CKSCR RB 1 ORG 00AEH FMCS RB 1 ORG 006FH ROMM RB 1 RESOUS ENDS ; SSTA SSEG RW 0127H STA_T RW 1 451 CHAPTER 25 1M-BIT FLASH MEMORY SSTA ; DATA ENDS DSEG ABS=0FFH ;FLASH command address ORG 5554H COMADR2 RW 1 ORG 0AAAAH COMADR1 RW 1 DATA ENDS ;///////////////////////////////////////////////////////////// ;Main program (SA1) ;///////////////////////////////////////////////////////////// CODE CSEG START: ;///////////////////////////////////////////////////// ;Initialization ;///////////////////////////////////////////////////// MOV CKSCR,#0BAH ;Setting to threefold MOV RP,#0 MOV A,#!STA_T MOV SSB,A MOVW A,#STA_T MOVW SP,A MOV ROMM,#00H ;Mirror OFF MOV PDR0,#00H ;For error confirmation MOV DDR0,#0FFH MOV PDR1,#00H ;Data input port MOV DDR1,#00H MOV PDR2,#00H ;Data output port MOV DDR2,#0FFH ;/////////////////////////////////////////////////////////// ;The FLASH write deletion program (FFBC00H) is transferred ;to the RAM (address 700H). ;/////////////////////////////////////////////////////////// MOVW A,#0700H ;Transfer destination RAM area MOVW A,#0BC00H ;Transfer source address (program ; location) MOVW RW0,#100H ;Number of bytes to be transferred MOVS ADB,PCB ;100H transfer from FFBC00H to ; 000700H CALLP 000700H ;Jump to the address in which the ; transferred program exists ;///////////////////////////////////////////////////// ;Data output ;///////////////////////////////////////////////////// OUT MOV A,#0FEH MOV ADB,A MOVW RW2,#0000H MOVW A,@RW2+00 MOV PDR2,A END JMP * CODE ENDS ;//////////////////////////////////////////////////////////// ;FLASH write deletion program (SA4) ;//////////////////////////////////////////////////////////// RAMPRG CSEG ABS=0FFH ORG 0BC00H ; //////////////////////////////////////////// 452 25.7 Example of the 1M-Bit Flash Memory Program ; ; ; ; Initialization //////////////////////////////////////////// MOVW RW0,#0500H ;RW0: RAM space for input data acquisition 00:0500 to MOVW RW2,#0000H ;RW2: Flash memory writing address FD:0000 to MOV A,#00H ;DTB change MOV DTB,A ;@RW0 bank specification MOV A,#0FEH ;ADB change 1 MOV ADB,A ;Specification of the bank for the write mode specification address MOV PDR3,#00H ;Switch initialization MOV DDR3,#00H ; WAIT1 BBC PDR3:0,WAIT1 ;PDR3:0 Start of writing with Hi ; ;//////////////////////////////////////////////// ; Writing(SA0) ;//////////////////////////////////////////////// MOV A,PDR1 MOVW @RW0+00,A ;Allocation of PDR1 data in ; the RAM MOV FMCS,#20H ;Write mode setting MOVW ADB:COMADR1,#00AAH ;Flash write command 1 MOVW ADB:COMADR2,#0055H ;Flash write command 2 MOVW ADB:COMADR1,#00A0H ;Flash write command 3 ; MOVW A,@RW0+00 ;Writing of input data (RW0) ; into the flash memory (RW2) MOVW @RW2+00,A WRITE ;Wait time check ; //////////////////////////////////////////////////////////// ; Error when the time limit excess check flag is set and the ; toggle operation is ongoing ; //////////////////////////////////////////////////////////// MOVW A,@RW2+00 AND A,#20H ;DQ5 time limit check BZ NTOW ;Time limit over MOVW A,@RW2+00 ;AH MOVW A,@RW2+00 ;AL XORW A ;XOR of AH and AL (1 if the ; value is different) AND A,#40H ;Is the DQ6 toggle bit ; different? BNZ ERROR ;If it is different, go to ; ERROR. ; /////////////////////////////////////// ; Write end check (FMCS-RDY) ; /////////////////////////////////////// NTOW MOVW A,FMCS AND A,#10H ;Extraction of the FMCS RDY bit (4 bits) BZ WRITE ;Is writing ended? MOV FMCS,#00H ;Release of the write mode ;///////////////////////////////////////////////////// ;Write data output ;///////////////////////////////////////////////////// 453 CHAPTER 25 1M-BIT FLASH MEMORY ; WAIT2 MOVW MOVW MOV RW2,#0000H A,@RW2+00 PDR2,A ;Write data output BBC PDR3:1,WAIT2 ;PDR3:1 Start of the sector deletion with Hi ; ;///////////////////////////////////////////// ;Sector deletion (SA0) ;///////////////////////////////////////////// MOV @RW2+00,#0000H ;Address initialization MOV FMCS,#20H ;Deletion mode setting MOVW ADB:COMADR1,#00AAH ;Flash deletion command 1 MOVW ADB:COMADR2,#0055H ;Flash deletion command 2 MOVW ADB:COMADR1,#0080H ;Flash deletion command 3 MOVW ADB:COMADR1,#00AAH ;Flash deletion command 4 MOVW ADB:COMADR2,#0055H ;Flash deletion command 5 MOV @RW2+00,#0030H ;Issuance of the deletion ; command to the sector to be ; deleted 6 ELS ; Wait time check ; //////////////////////////////////////////////////////////// ; Error when the time limit excess check flag is set and the ; toggle operation is ongoing ; //////////////////////////////////////////////////////////// MOVW A,@RW2+00 AND A,#20H ;DQ5 time limit check BZ NTOE ;Time limit over MOVW A,@RW2+00 ;AH Hi and low are ; alternately output, MOVW A,@RW2+00 ;AL for each reading, ; from DQ6 during ; writing. XORW A ;XOR of AH and AL (1 writing ; (writing ongoing) ; if the DQ6 value is ; different) AND A,#40H ;Is the DQ6 toggle bit Hi? BNZ ERROR ;If it is Hi, go to ERROR. ; /////////////////////////////////////// ; Deletion end check (FMCS-RDY) ; /////////////////////////////////////// NTOE MOVW A,FMCS ; AND A,#10H ;Extraction of the FMCS RDY ; bit (4 bits) BZ ELS ;Is sector deletion ended? MOV FMCS,#00H ;Release of the FLASH ; deletion mode RETP ;Return to the main program ;////////////////////////////////////////////// ;Error ;////////////////////////////////////////////// ERROR MOV ADB:COMADR1,#0F0H ;Reset command (reading ; possible) MOV FMCS,#00H ;Release of the FLASH mode MOV PDR0,#0FFH ;Confirmation of the error ; handling 454 25.7 Example of the 1M-Bit Flash Memory Program RETP ;Return to the main program RAMPRG ENDS ;///////////////////////////////////////////// VECT CSEG ABS=0FFH ORG 0FFDCH DSL START DB 00H VECT ENDS ; END START 455 CHAPTER 25 1M-BIT FLASH MEMORY 456 CHAPTER 26 EXAMPLE OF MB90F583C/CA SERIAL PROGRAMMING CONNECTION This chapter provides examples of serial programming connection using the flash microcomputer programmer manufactured by YDC corporation. 26.1 "Basic Configuration of MB90F583C/CA Serial Programming Connection" 26.2 "Example of Serial Programming Connection (When User Power Supply Is Used)" 26.3 "Example of Serial Programming Connection (When Power Is Supplied from a Programmer)" 26.4 "Example of Minimal Connection with the Flash Microcomputer Programmer (When User Power Supply Is Used)" 26.5 "Example of Minimal Connection with the Flash Microcomputer Programmer (When Power Is Supplied from a Programmer)" 457 CHAPTER 26 EXAMPLE OF MB90F583C/CA SERIAL PROGRAMMING CONNECTION 26.1 Basic Configuration of MB90F583C/CA Serial Programming Connection The MB90F583C/CA supports flash ROM serial onboard programming (Fujitsu standard). This section describes the specifications. ■ Basic Configuration of MB90F583C/CA Serial Programming Connection The AF200 flash microcomputer programmer manufactured by YDC corporation. is used for Fujitsu standard serial onboard programming. Host interface cable (AZ221) General-purpose common cable (AZ210) Flash RS232C microcomputer CLK-synchronous serial MB90F583C/CA programmer user system + memory card Operable in stand alone mode Note: For the functions and operation of the flash microcomputer programmer (AF220/AF210/ AF120/AF110), the general-purpose common cable (AZ210), and the connector, contact YDC corporation. 458 26.1 Basic Configuration of MB90F583C/CA Serial Programming Connection Table 26.1-1 Pins Used for Fujitsu Standard Serial Onboard Programming Pin Function Description MD2, MD1 MD0 Mode pins Programming mode is controlled from the flash microcomputer programmer. X0, X1 Oscillation pin In programming mode, the CPU internal operating clock pulse is generated by multiplying the PLL clock pulse by 1. Therefore, the oscillation clock is available as the internal operating clock. An oscillator used for serial reprogramming oscillates at 3 to 16 MHz. P00, P01 Programming program activation pin - RST Reset pin - SIN0 Serial data input pin SOT0 Serial data output pin SCK0 Serial clock pulse input pin C C pin Capacitor pin for power supply stabilization. Connect a ceramic capacitor of about 0.1 μF externally. VCC Power supply voltage supply pin Connection with the flash microcomputer programmer is not required if the programming voltage (5 V 10%) is supplied from the user system. Be sure not to connect the pin with the user power supply circuit when wiring. VSS GND pin Common to the GND of the flash microcomputer programmer. HST Hardware standby pin Input the H level in serial programming mode. UART is used as CLK synchronization mode. If the P00, SIN, SOT0, and SCK0 pins are used also by the user system, the following control circuit is required. The user circuit can be disconnected by the /TICS signal of the flash microcomputer programmer during serial programming. AF220/AF210/AF120/AF110 programming control pin MB90F583C/CA programming control pin 10 K AF220/AF210/AF120/AF110 /TICS pin User 459 CHAPTER 26 EXAMPLE OF MB90F583C/CA SERIAL PROGRAMMING CONNECTION Sections 26.1 "Basic Configuration of MB90F583C/CA Serial Programming Connection" to 26.5 "Example of Minimal Connection with the Flash Microcomputer Programmer (When Power Is Supplied from a Programmer)" show the following examples of serial programming connections for reference: • Example of serial programming connection (when user power supply is used) • Example of serial programming connection (when power is supplied from a programmer) • Example of minimal connection with the flash microcomputer programmer (when user power supply is used) • Example of minimal connection with the flash microcomputer programmer (when power is supplied from a programmer) ■ Oscillation Clock Frequency and Serial Clock Input Frequency The serial clock frequency that can be entered into the MB90F583C/CA is obtained from the following equation. Change the serial clock input frequency in accordance with the user’s oscillation clock frequency by setting the flash microcomputer programmer. Input-enabling serial clock frequency = 0.125 x oscillation clock frequency Table 26.1-2 Oscillation clock frequency 460 Maximum serial clock frequency that can be entered by the microcomputer Maximum serial clock frequency that can be set by AF220/AF210/ AF120/AF110 Maximum serial clock frequency that can be set by AF200 4 MHz 500 KHz 500 KHz 500 KHz 8 MHz 1 MHz 850 KHz 500 KHz 16 MHz 2 MHz 1.25 MHz 500 KHz 26.1 Basic Configuration of MB90F583C/CA Serial Programming Connection ■ System Configuration of Flash Microcomputer Programmer (Manufactured by YDC Corporation) Table 26.1-3 System Configuration of Flash Microcomputer Programmer (Manufactured by YDC Corporation) Type Main unit Function AF220/AC4P Built-in Ethernet interface model with 100 VAC to 220 VAC power adapter AF210/AC4P Standard model with 100 VAC to 220 VAC power adapter AF120/AC4P Single-key built-in Ethernet interface model with 100 VAC to 220 VAC power adapter AF110/AC4P Single-key model with 100 VAC to 220 VAC power adapter AZ221 Programmer-dedicated RS232C cable for PC/AT AZ210 Standard target probe (a) length: 1 m FF201 Control module for Fujitsu F2MC-16LX flash microcomputer /P2 2-MB PC card (option) flash memory capacity - for 128 KB /P4 4-MB PC card (option) flash memory capacity - for 512 KB Note: Although production of the AF200 flash microcomputer programmer has ended, it can still be used if the control module FF201 is used. The serial programming connection is used in the connection example given in the next section. 461 CHAPTER 26 EXAMPLE OF MB90F583C/CA SERIAL PROGRAMMING CONNECTION 26.2 Example of Serial Programming Connection (When User Power Supply Is Used) Figure 26.2-1 "Example of Serial Programming Connection (when User Power Supply Is Used)" shows an example of serial programming connection when the power supply voltage of the microcomputer is supplied from the user power supply. The value 1 and 0 are input to mode pins MD2 and MD0 from TAUX3 and TMODE of the AF220/AF210/AF120/AF110 programmer. Serial reprogramming mode: MD2, MD1, MD0 = 110. ■ Example of Serial Programming Connection (when User Power Supply is Used) Figure 26.2-1 Example of Serial Programming Connection (when User Power Supply Is Used) AF220/AF210/AF120/AF110 flash microcomputer programmer TAUX3 User system Connector DX10-28S MB90F583C/CA (19) MD2 10 kΩ 10 kΩ MD1 10 kΩ TMODE MD0 X0 (12) 3 MHz to 16 MHz X1 TAUX (23) P00 10 kΩ /TICS (10) User 10 kΩ User HST 10 kΩ /TRES (5) RST 10 kΩ P01 C User TTXD TRXD TCK (13) (27) (6) TVcc (2) GND (7,8, 14,15, 21,22 1,28) SIN0 SOT0 SCK0 Vcc User power supply Pin 14 Pins 4, 9, 11, 17, 18, 20, and 24 to 26 are open. DX10-28S: Right angle type 462 Vss Pin 1 DX10-28S Pin 28 Pin 15 Connector (manufactured by Hirose Electric Co., Ltd.) pin alignment 26.2 Example of Serial Programming Connection (When User Power Supply Is Used) • As with the case in which the P00 pin is also used, the following control circuit is required when the SIN0, SOT0, and SCK0 pins are also used by the user system. (The user circuit can be disconnected by the /TICS signal of the flash microcomputer programmer during serial programming.) AF220/AF210/AF120/AF110 programming control pin MB90F583C/CA programming control pin 10 kΩ AF220/AF210/AF120/AF110 /TICS pin User • Connect the AF220/AF210/AF120/AF110, turning the user power supply off. 463 CHAPTER 26 EXAMPLE OF MB90F583C/CA SERIAL PROGRAMMING CONNECTION 26.3 Example of Serial Programming Connection (When Power is Supplied from a Programmer) Figure 26.3-1 "Example of Serial Programming Connection (when Power is Supplied from a Programmer)" shows an example of serial programming connection when the power supply voltage of the microcomputer is supplied from programmer power supply. The value 1 and 0 are input to mode pins MD2 and MD0 from TAUX3 and TMODE of the AF220/AF210/AF120/AF110 programmer. Serial reprogramming mode: MD2, MD1, MD0 = 110. ■ Example of Serial Programming Connection (when Power is Supplied from a Programmer) Figure 26.3-1 Example of Serial Programming Connection (when Power is Supplied from a Programmer) AF220/AF210/AF120/AF110 flash microcomputer programmer TAUX3 User system Connector DX10-28S MB90F583C/CA (19) MD2 10 kΩ 10 kΩ MD1 10 kΩ TMODE MD0 X0 (12) 3 MHz to 16 MHz X1 TAUX (23) P00 10 kΩ /TICS (10) User 10 kΩ User HST 10 kΩ /TRES (5) RST 10 kΩ P01 C User TTXD TRXD TCK TVcc Vcc TVPP1 GND (13) (27) (6) (2) (3) (16) (7,8, 14,15, 21,22 1,28) Pins 4, 9, 11, 17, 18, 20, and 24 to 26 are open. DX10-28S: Right angle type SIN0 SOT0 SCK0 Vcc User power supply Vss Pin 14 Pin 1 Pin 28 Pin 15 DX10-28S Connector (manufactured by Hirose Electric Co., Ltd.) pin alignment 464 26.3 Example of Serial Programming Connection (When Power is Supplied from a Programmer) • As with the case in which the P00 pin is also used, the following control circuit is required when the SIN0, SOT0, and SCK0 pins are also used by the user system. (The user circuit can be disconnected by the /TICS signal of the flash microcomputer programmer during serial programming.) AF220/AF210/AF120/AF110 programming control pin MB90F583C/CA programming control pin 10 kΩ AF220/AF210/AF120/AF110 /TICS pin User • Connect the AF220/AF210/AF120/AF110, turning the user power supply off. • When programming power supply is supplied from the AF220/AF210/AF120/AF110, be sure not to connect the power supply pin with the user power supply circuit. 465 CHAPTER 26 EXAMPLE OF MB90F583C/CA SERIAL PROGRAMMING CONNECTION 26.4 Example of Minimum Connection with the Flash Microcomputer Programmer (When User Power Supply is Used) Figure 26.4-1 "Example of Minimum Connection with Flash Microcomputer Programmer (when User Power Supply is Used)" shows an example of minimum connection with the flash microcomputer programmer when the power supply voltage of the microcomputer is supplied from the user power supply. Serial reprogramming mode: MD2, MD1, MD0 = 110. ■ Example of Minimum Connection with the Flash Microcomputer Programmer (when User Power Supply is Used) The MD2, MD1, MD0, and P00 pins need not be connected to the flash microcomputer programmer if each pin is connected, as shown below, for flash memory programming. Figure 26.4-1 Example of Minimum Connection with Flash Microcomputer Programmer (when User Power Supply is Used) AF220/AF210/AF120/AF110 flash microcomputer programmer User system Serial reprogramming 1 MB90F583C/CA 10 kΩ MD2 Serial reprogramming 1 10 kΩ 10 kΩ MD1 10 kΩ 10 kΩ Serial reprogramming 0 10 kΩ MD0 X0 3 MHz to 16 MHz X1 P00 10 kΩ Serial reprogramming 0 10 kΩ User circuit Serial reprogramming 1 10 kΩ P01 User circuit HST C Connector DX10-28S /TRES TTXD TRXD TCK TVcc (5) (13) (27) (6) (2) GND (7,8, 14,15, 21,22, 1,28) 10 kΩ RST SIN0 SOT0 SCK0 Vcc User power supply Vss Pin 14 Pins 3, 4, 9 to 12, 16 to 20, and 23 to 26 are open. DX10-28S: Right angle type Pin 1 DX10-28S Pin 28 Pin 15 Connector (manufactured by Hirose Electric Co., Ltd.) pin alignment 466 26.4 Example of Minimum Connection with the Flash Microcomputer Programmer (When User Power Supply is Used) • When the SIN0, SOT0, and SCK0 pins are also used by the user system, the following control circuit is required. (The user circuit can be disconnected by the /TICS signal of the flash microcomputer programmer during serial programming.) AF220/AF210/AF120/AF110 programming control pin MB90F583C/CA programming control pin 10 kΩ AF220/AF210/AF120/AF110 /TICS pin User • Connect the AF220/AF210/AF120/AF110, turning the user power supply off. 467 CHAPTER 26 EXAMPLE OF MB90F583C/CA SERIAL PROGRAMMING CONNECTION 26.5 Example of Minimum Connection with the Flash Microcomputer Programmer (When Power is Supplied from a Programmer) Figure 26.5-1 "Example of Minimum Connection with Flash Microcomputer Programmer (when Power is Supplied from a Programmer)" shows an example of minimum connection with the flash microcomputer programmer when the power supply voltage of the microcomputer is supplied from a programmer. Serial reprogramming mode: MD2, MD1, MD0 = 110. ■ Example of Minimum Connection with the Flash Microcomputer Programmer (when Power is Supplied from a Programmer) The MD2, MD1, MD0, and P00 pins need not be connected to the flash microcomputer programmer if each pin is connected, as shown below, for flash memory programming. Figure 26.5-1 Example of Minimum Connection with Flash Microcomputer Programmer (when Power is Supplied from a Programmer) AF220/AF210/AF120/AF110 flash microcomputer programmer User system Serial reprogramming 1 MB90F583C/CA 10 kΩ MD2 Serial reprogramming 1 10 kΩ 10 kΩ MD1 10 kΩ 10 kΩ Serial reprogramming 0 10 kΩ MD0 3 MHz to 16 MHz X0 X1 P00 10 kΩ Serial reprogramming 0 10 kΩ User circuit Serial reprogramming 1 10 kΩ P01 User circuit HST C Connector DX10-28S /TRES TTXD TRXD TCK TVcc Vcc TVPP1 GND (5) (13) (27) (6) (2) (3) (16) 10 kΩ Vcc (7,8, 14,15, 21,22, 1,28) Pins 3, 4, 9 to 12, 16 to 20, and 23 to 26 are open. RST SIN SOT SCK Vss Pin 14 Pin 1 Pin 28 Pin 15 DX10-28S DX10-28S: Right-angle type Connector (manufactured by Hirose Electric Co., Ltd.) pin alignment 468 26.5 Example of Minimum Connection with the Flash Microcomputer Programmer (When Power is Supplied from a Programmer) • When the SIN0, SOT0, and SCK0 pins are also used by the user system, the following control circuit is required. (The user circuit can be disconnected by the /TICS signal of the flash microcomputer programmer during serial programming.) AF220/AF210/AF120/AF110 programming control pin MB90F583C/CA programming control pin 10 kΩ AF220/AF210/AF120/AF110 /TICS pin User • Connect the AF220/AF210/AF120/AF110, turning the user power supply off. • When programming power supply is supplied from the AF220/AF210/AF120/AF110, be sure not to connect the power supply pin with the user power supply circuit. 469 CHAPTER 26 EXAMPLE OF MB90F583C/CA SERIAL PROGRAMMING CONNECTION 470 APPENDIX The appendix describes the I/O map and instructions. APPENDIX A "I/O Map" APPENDIX B "Instructions" 471 APPENDIX APPENDIX A I/O Map The addresses are assigned to the registers for each resource of this micro controller as follows. ■ I/O Map Table A-1 I/O Map Address Abbreviation Access Resource Initial value 00H Port 0 data register PDR0 R/W Port 0 XXXXXXXXB 01H Port 1 data register PDR1 R/W Port 1 XXXXXXXXB 02H Port 2 data register PDR2 R/W Port 2 XXXXXXXXB 03H Port 3 data register PDR3 R/W Port 3 XXXXXXXXB 04H Port 4 data register PDR4 R/W Port 4 XXXXXXXXB 05H Port 5 data register PDR5 R/W Port 5 11111111B 06H Port 6 data register PDR6 R/W Port 6 --XXXXX-B 07H Port 7 data register PDR7 R/W Port 7 ---XXXX-B 08H Port 8 data register PDR8 R/W Port 8 XXXXXXXXB 09H Port 9 data register PDR9 R/W Port 9 XXXXXXXXB 0AH Port A data register PDRA R/W Port A -----XXXB 0BH to 0FH 472 Register Disabled 10H Port 0 data direction register DDR0 R/W Port 0 00000000B 11H Port 1 data direction register DDR1 R/W Port 1 00000000B 12H Port 2 data direction register DDR2 R/W Port 2 00000000B 13H Port 3 data direction register DDR3 R/W Port 3 00000000B 14H Port 4 data direction register DDR4 R/W Port 4 00000000B 15H Port 5 data direction register DDR5 R/W Port 5 00000000B 16H Port 6 data direction register DDR6 R/W Port 6 --000000B 17H Port 7 data direction register DDR7 R/W Port 7 ---0000-B 18H Port 8 data direction register DDR8 R/W Port 8 00000000B 19H Port 9 data direction register DDR9 R/W Port 9 00000000B 1AH Port A data direction register DDRA R/W Port A -----000B APPENDIX A I/O Map Table A-1 I/O Map (Continued) Address Register Abbreviation Access Resource Initial value 1BH Port 4 output terminal register ODR4 R/W Port 4 00000000B 1CH Port 5 analog input enable register ADER R/W Port 5 and A/D 11111111B 1DH to 1FH Disabled 20H Serial mode register 0 SMR0 R/W 00000000B 21H Serial control register 0 SCR0 R/W 00000100B 22H Serial input /serial output register 0 SIDR0/ SODR0 R/W XXXXXXXXB 23H Serial status register 0 SSR0 R/W 00001-00B 24H Serial mode register 1 SMR1 R/W 00000000B 25H Serial control register 1 SCR1 R/W 00000100B 26H Serial input /serial output register 1 SIDR1/ SODR1 R/W XXXXXXXXB 27H Serial status register 1 SSR1 R/W 000001-00B 28H Serial mode register 2 SMR2 R/W 00000000B 29H Serial control register 2 SCR2 R/W 00000100B 2AH Serial input /serial output register 2 SIDR2/ SODR2 R/W XXXXXXXXB 2BH Serial status register 2 SSR2 R/W 00001-00B 2CH Clock division control register 0 CDCR0 R/W Communication prescaler 0 0---1111B 2DH Disabled 2EH Clock division control register 1 IDCR1 R/W Communication prescaler 1 0---1111B 2FH Disabled 30H Interrupt/DTP enable register ENIR R/W 00000000B 31H Interrupt/DTP cause register EIRR R/W XXXXXXXB 32H Request level setting register (loworder) 33H Request level setting register (highorder) 34H Clock division control register 2 UART0 UART1 UART2 DTP/external interrupt ELVR 00000000B R/W 00000000B CDCR2 R/W Communication prescaler 2 0---1111B 473 APPENDIX Table A-1 I/O Map (Continued) Address Register Abbreviation Access Initial value 35H Disabled 36H Control status register (low-order) ADCS1 R/W 37H Control status register (high-order) ADCS2 R/W 38H Data register (low-order) 39H Data register (high-order) 3AH D/A converter data register 0 DAT0 R/W 3BH D/A converter data register 1 DAT1 R/W 3CH D/A control register 0 DACR0 R/W -------0B 3DH D/A Control register 1 DACR1 R/W -------0B 3EH Clock output enable register CLKR R/W 3FH Disabled 40H Reload register L (ch.0) PRLL0 R/W XXXXXXXXB 41H Reload register H (ch. 0) PRLH0 R/W XXXXXXXXB 42H Reload register L (ch. 1) PRLL1 R/W XXXXXXXXB 43H Reload register H (ch. 1) PRLH1 R/W 00000000B A/D converter ADCR1 00000000B XXXXXXXXB R ADCR2 00001-XXB 00000000B D/A converter Clock monitor function 00000000B ----0000B XXXXXXXXB 8/16 bit PPG 0/1 44H PPG0 operating mode control register PPGC0 R/W 45H PPG1 operating mode control register PPGO1 R/W 0X000001B 46H PPG0 and PPG1 operation output control register PPGOE R/W 00000000B 47H Disabled 48H Timer control status register 0 (loworder) 49H Timer control status register 0 (highorder) 4AH 4BH 16-bit timer register 0/16-bit reload register 0 4CH Timer control status register 1 (loworder) 4DH Timer control status register 1 (highorder) 4FH 16-bit timer register 1/16-bit reload register 1 R/W 16-bit reload timer 0 TMR0/ TMRLR0 ----0000B XXXXXXXXB R/W XXXXXXXXB 00000000B TMCSR1 4EH 0X000XX1B 00000000B TMCSR0 474 Resource R/W 16-bit reload timer 1 TMR1/ TMRLR1 R/W ----0000B XXXXXXXXB XXXXXXXXB APPENDIX A I/O Map Table A-1 I/O Map (Continued) Address Register 50H Lower timer control status register 2 51H Upper timer control status register 2 52H 16-bit timer register 2/16-bit reload register 2 53H 54H PWC control status register (low-order) 55H PWC control status register (high-order) 56H PWC data buffer register (low-order) 57H PWC data buffer register (high-order) 58H Dividing ratio control register 59H Disabled Abbreviation Access TMCSR2 R/W TMR2/ TMRLR2 00000000B 16-bit reload timer 2 R/W XXXXXXXXB XXXXXXXXB R/W 16-bit PWC timer XXXXXXXXB R/W XXXXXXXXB DIVR R/W OCCP0 R/W ------00B XXXXXXXXB 5BH 5CH ----0000B 00000000B PWCR Compare register ch.0 Initial value 00000000B PWCSR 5AH Resource XXXXXXXXB Compare register ch.1 OCCP1 R/W 5DH Output compare (ch.0 to ch.1) XXXXXXXXB XXXXXXXXB 5EH Compare control status register ch.0 OCS0 R/W 0000--00B 5FH Compare control status register ch.1 OCS1 R/W ----0000B Input capture register 0 IPCP0 R 60H XXXXXXXXB 61H 62H XXXXXXXXB Input capture register 1 IPCP1 XXXXXXXXB R 63H 64H XXXXXXXXB Input capture register 2 IPCP2 65H 66H XXXXXXXXB R Input capture (ch.0 to ch.3) Input capture register 3 IPCP3 R 67H XXXXXXXXB XXXXXXXXB XXXXXXXXB 68H Input capture control status register ch.0 and ch.1 69H Disabled 6AH Input capture control status register ch.2 and ch.3 ICS01 R/W 00000000B ICS23 R/W 00000000B 475 APPENDIX Table A-1 I/O Map (Continued) Address 476 Register 6BH Disabled 6CH Timer data register (low-order) 6DH Timer data register (high-order) 6EH Abbreviation Access TCDTL R/W Resource Initial value 00000000B Free-run timer TCDTH R/W 00000000B Timer control status register TCCS R/W 6FH ROM mirror function selection register ROMM W 70H Local address setting register (loworder) MAWL R/W XXXXXXXXB 71H Local address setting register (highorder) MAWH R/W XXXXXXXXB 72H Slave address setting register (loworder) SAWL R/W XXXXXXXXB 73H Slave address setting register (highorder) SAWH R/W XXXXXXXXB 74H Text length bit setting register DEWR R/W 00000000B 75H Broadcast control bit setting register DCWR R/W 00000000B 76H Command register (low-order) CMRL R/W 11000000B 77H Command register (high-order) CMRH R/W 00000000B ROM mirror function -------1B 0000000XB IEBus contoroler 78H Status register (low-order) STRL R 0011XXXXB 79H Status register (high-order) STRH R/W 00XX0000B 7AH Lock read register (low-order) LRRL R XXXXXXXXB 7BH Lock read register (high-order) LRRH R/W 1110XXXXB 7CH Master address read register (loworder) MARL R 7DH Master address read register (highorder) MARH R 1111XXXXB 7EH Text length bit read register DERR R XXXXXXXXB 7FH Broadcast control bit read register DCRR R 000XXXXXB 80H Write data buffer WDB W XXXXXXXXB 81H Read data buffer RDB R XXXXXXXXB 82H Serial mode register 3 SMR3 R/W 00000000B 83H Serial control register 3 SCR3 R/W 00000100B 84H Serial input/serial output register 3 SIDR3/ SODR3 R/W XXXXXXXXB 85H Serial status register 3 SSR3 R/W 00001-00B XXXXXXXXB UART3 APPENDIX A I/O Map Table A-1 I/O Map (Continued) Address Register Abbreviation Access Resource Initial value 86H PWC noise filter register RNCR R/W PWC noise filter -----000B 87H Clock division control register 3 CDCR3 R/W Communicati on prescaler 3 0---1111B 88H Serial mode register 4 SMR4 R/W 00000000B 89H Serial control register 4 SCR4 R/W 00000100B 8AH Serial input/serial output register 4 SIDR4/ SODR4 R/W XXXXXXXXB 8BH Serial status register 4 SSR4 R/W 00001-00B 8CH Port 0 input pull-up resister setting register RDR0 R/W Port 0 00000000B 8DH Port 1 input pull-up resister setting register RDR1 R/W Port 1 00000000B 8EH Port 6 input pull-up resister setting register RDR6 R/W Port 6 --000000B 8FH Clock division control register 4 CDCR4 R/W Communicati on prescaler 4 0---1111B R/W Address match detection function DIRR R/W Delayed interrupt generating module 90H to 9DH UART4 Disabled 9EH Program address detection control/ status register 9FH Delayed interrupt source generation/cancel register A0H Low-power consumption mode control register LPMCR R/W A1H Clock selection register CKSCR R/W W A2H to A4H PACSR Low-power consumption control circuit 00000000B -------0B 0001100-B 11111100B Disabled A5H Automatic ready function selection register ARSR A6H External address output control register HACR W A7H Bus control signal selection register ECSR W 0011-00B External bus pin control circuit 00000000B 0000000-B 477 APPENDIX Table A-1 I/O Map (Continued) Address Register Access Resource Initial value A8H Watchdog control register WDTC R/W Watchdog timer XXXXX111B A9H Time-based timer control register TBTC R/W Time-base timer 1--00100B AAH Clock timer control register WTC R/W Clock timer 1X000000B FMCS R/W Flash interface 000X000B ABH to ADH Disabled AEH Flash memory control status register AFH Disabled B0H Interrupt control register 00 ICR00 R/W 00000111B B1H Interrupt control register 01 ICR01 R/W 00000111B B2H Interrupt control register 02 ICR02 R/W 00000111B B3H Interrupt control register 03 ICR03 R/W 00000111B B4H Interrupt control register 04 ICR04 R/W 00000111B B5H Interrupt control register 05 ICR05 R/W 00000111B B6H Interrupt control register 06 ICR06 R/W 00000111B B7H Interrupt control register 07 ICR07 R/W B8H Interrupt control register 08 ICR08 R/W B9H Interrupt control register 09 ICR09 R/W 00000111B BAH Interrupt control register 10 ICR10 R/W 00000111B BBH Interrupt control register 11 ICR11 R/W 00000111B BCH Interrupt control register 12 ICR12 R/W 00000111B BDH Interrupt control register 13 ICR13 R/W 00000111B BEH Interrupt control register 14 ICR14 R/W 00000111B BFH Interrupt control register 15 ICR15 R/W 00000111B C0H to FFH External area 100H to #H RAM area #H to 1FEFH Reserved area 478 Abbreviation Interrupt controller 00000111B 00000111B APPENDIX A I/O Map Table A-1 I/O Map (Continued) Address Register 1FF0H Program address detection register 0 (low-order) 1FF1H Program address detection register 0 (middle-order) 1FF2H Program address detection register 0 (high-order) R/W 1FF3H Program address detection register 1 (low-order) R/W 1FF4H Program address detection register 1 (middle-order) 1FF5H Program address detection register 1 (high-order) 1FF6H to 1FFFH Abbreviation PADR0 PADR1 Access Resource Initial value R/W XXXXXXXXB R/W XXXXXXXXB Address match detection function XXXXXXXXB XXXXXXXXB R/W XXXXXXXXB R/W XXXXXXXXB Reserved area • Initial values --> 0: 0, 1: 1, X: Not defined, -: Not defined (none) • An area of address 00FFH and smaller addresses is a reserved area. • The border address #H between RAM area and reserved area is dependent on the part number. Note: Values initialized by a reset are described as initial values of writable bits. Note that the values are not read values. Initialization of the LPMCR, CKSCR, and WDTC registers is dependent on the reset type. The initial values, set when initialized, are described. 479 APPENDIX APPENDIX B Instructions APPENDIX B describes the instructions used by the F2MC-16LX. B.1 Instruction Types B.2 Addressing B.3 Direct Addressing B.4 Indirect Addressing B.5 Execution Cycle Count B.6 Effective address field B.7 How to Read the Instruction List B.8 F2MC-16LX Instruction List B.9 Instruction Map Code: CM44-00202-1E 480 APPENDIX B Instructions B.1 Instruction Types The F2MC-16LX supports 351 types of instructions. Addressing is enabled by using an effective address field of each instruction or using the instruction code itself. ■ Instruction Types The F2MC-16LX supports the following 351 types of instructions: • 41 transfer instructions (byte) • 38 transfer instructions (word or long word) • 42 addition/subtraction instructions (byte, word, or long word) • 12 increment/decrement instructions (byte, word, or long word) • 11 comparison instructions (byte, word, or long word) • 11 unsigned multiplication/division instructions (word or long word) • 11 signed multiplication/division instructions (word or long word) • 39 logic instructions (byte or word) • 6 logic instructions (long word) • 6 sign inversion instructions (byte or word) • 1 normalization instruction (long word) • 18 shift instructions (byte, word, or long word) • 50 branch instructions • 6 accumulator operation instructions (byte or word) • 28 other control instructions (byte, word, or long word) • 21 bit operation instructions • 10 string instructions 481 APPENDIX B.2 Addressing With the F2MC-16LX, the address format is determined by the instruction effective address field or the instruction code itself (implied). When the address format is determined by the instruction code itself, specify an address in accordance with the instruction code used. Some instructions permit the user to select several types of addressing. ■ Addressing The F2MC-16LX supports the following 23 types of addressing: 482 • Immediate (#imm) • Register direct • Direct branch address (addr16) • Physical direct branch address (addr24) • I/O direct (io) • Abbreviated direct address (dir) • Direct address (addr16) • I/O direct bit address (io:bp) • Abbreviated direct bit address (dir:bp) • Direct bit address (addr16:bp) • Vector address (#vct) • Register indirect (@RWj j = 0 to 3) • Register indirect with post increment (@RWj+ j = 0 to 3) • Register indirect with displacement (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3) • Long register indirect with displacement (@RLi + disp8 i = 0 to 3) • Program counter indirect with displacement (@PC + disp16) • Register indirect with base index (@RW0 + RW7, @RW1 + RW7) • Program counter relative branch address (rel) • Register list (rlst) • Accumulator indirect (@A) • Accumulator indirect branch address (@A) • Indirectly-specified branch address (@ear) • Indirectly-specified branch address (@eam) APPENDIX B Instructions ■ Effective Address Field Table B.2-1 lists the address formats specified by the effective address field. Table B.2-1 Effective Address Field Code Representation 00 R0 RW0 RL0 01 R1 RW1 (RL0) 02 R2 RW2 RL1 03 R3 RW3 (RL1) 04 R4 RW4 RL2 05 R5 RW5 (RL2) 06 R6 RW6 RL3 07 R7 RW7 (RL3) 08 @RW0 09 @RW1 Address format Default bank Register direct: Individual parts correspond to the byte, word, and long word types in order from the left. None DTB DTB Register indirect 0A @RW2 ADB 0B @RW3 SPB 0C @RW0+ DTB 0D @RW1+ DTB Register indirect with post increment 0E @RW2+ ADB 0F @RW3+ SPB 10 @RW0+disp8 DTB 11 @RW1+disp8 DTB Register indirect with 8-bit displacement 12 @RW2+disp8 ADB 13 @RW3+disp8 SPB 14 @RW4+disp8 DTB 15 @RW5+disp8 DTB Register indirect with 8-bit displacement 16 @RW6+disp8 ADB 17 @RW7+disp8 SPB 18 @RW0+disp16 DTB 19 @RW1+disp16 DTB Register indirect with 16-bit displacement 1A @RW2+disp16 ADB 1B @RW3+disp16 SPB 1C @RW0+RW7 Register indirect with index DTB 1D @RW1+RW7 Register indirect with index DTB 1E @PC+disp16 PC indirect with 16-bit displacement PCB 1F addr16 Direct address DTB 483 APPENDIX B Instructions B.3 Direct Addressing An operand value, register, or address is specified explicitly in direct addressing mode. ■ Direct Addressing ● Immediate addressing (#imm) Specify an operand value explicitly (#imm4/ #imm8/ #imm16/ #imm32). Figure B.3-1 Example of Immediate Addressing (#imm) MOVW A, #01212H (This instruction stores the operand value in A.) Before execution A 2233 4455 After execution A 4455 1 2 1 2 (Some instructions transfer AL to AH.) ● Register direct addressing Specify a register explicitly as an operand. Table B.3-1 lists the registers that can be specified. Figure B.3-2 shows an example of register direct addressing. Table B.3-1 Direct Addressing Registers General-purpose register Special-purpose register Byte R0, R1, R2, R3, R4, R5, R6, R7 Word RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7 Long word RL0, RL1, RL2, RL3 Accumulator A, AL Pointer SP * Bank PCB, DTB, USB, SSB, ADB Page DPR Control PS, CCR, RP, ILM *: One of the user stack pointer (USP) and system stack pointer (SSP) is selected and used depending on the value of the S flag bit in the condition code register (CCR). For branch instructions, the program counter (PC) is not specified in an instruction operand but is specified implicitly. 484 APPENDIX B Instructions Figure B.3-2 Example of Register Direct Addressing MOV R0, A (This instruction transfers the eight low-order bits of A to the generalpurpose register R0.) Before execution A 0716 2534 Memory space R0 After execution A 0716 2564 ?? Memory space R0 34 ● Direct branch addressing (addr16) Specify an offset explicitly for the branch destination address. The size of the offset is 16 bits, which indicates the branch destination in the logical address space. Direct branch addressing is used for an unconditional branch, subroutine call, or software interrupt instruction. Bit23 to bit16 of the address are specified by the program counter bank register (PCB). Figure B.3-3 Example of Direct Branch Addressing (addr16) JMP 3B20H (This instruction causes an unconditional branch by direct branch addressing in a bank.) Before execution After execution PC 3 C 2 0 PC 3 B 2 0 PCB 4 F PCB 4 F Memory space 4F3B20H Next instruction 4F3C20H 62 4F3C21H 20 4F3C22H 3B JMP 3B20H 485 APPENDIX B Instructions ● Physical direct branch addressing (addr24) Specify an offset explicitly for the branch destination address. The size of the offset is 24 bits. Physical direct branch addressing is used for unconditional branch, subroutine call, or software interrupt instruction. Figure B.3-4 Example of Direct Branch Addressing (addr24) JMPP 333B20H (This instruction causes an unconditional branch by direct branch 24-bit addressing.) Before execution After execution PC 3 C 2 0 PC 3 B 2 0 PCB 4 F PCB 3 3 Memory space 333B20H Next instruction 4F3C20H 63 4F3C21H 20 4F3C22H 3B 4F3C23H 33 JMPP 333B20H ● I/O direct addressing (io) Specify an 8-bit offset explicitly for the memory address in an operand. The I/O address space in the physical address space from 000000H to 0000FFH is accessed regardless of the data bank register (DTB) and direct page register (DPR). A bank select prefix for bank addressing is invalid if specified before an instruction using I/O direct addressing. Figure B.3-5 Example of I/O Direct Addressing (io) MOVW A, i : 0C0H (This instruction reads data by I/O direct addressing and stores it in A.) Before execution After execution 486 A 0716 2534 A 2534 FFEE Memory space 0000C0H EE 0000C1H FF APPENDIX B Instructions ● Abbreviated direct addressing (dir) Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register (DTB). Figure B.3-6 Example of Abbreviated Direct Addressing (dir) MOV S : 20H, A (This instruction writes the contents of the eight low-order bits of A in abbreviated direct addressing mode.) Before execution A 4455 DPR 6 6 After execution A 4455 DPR 6 6 1212 DTB 7 7 Memory space 776620H 1212 DTB 7 7 ?? Memory space 776620H 12 ● Direct addressing (addr16) Specify the 16 low-order bits of a memory address explicitly in an operand. Address bits 16 to 23 are specified by the data bank register (DTB). A prefix instruction for access space addressing is invalid for this mode of addressing. Figure B.3-7 Example of Direct Addressing (addr16) MOVW A, 3B20H (This instruction reads data by direct addressing and stores it in A.) Before execution After execution A 2020 A AABB AABB 0123 DTB 5 5 Memory space 553B21H 01 553B20H 23 DTB 5 5 487 APPENDIX B Instructions ● I/O direct bit addressing (io:bp) Specify bits in physical addresses 000000H to 0000FFH explicitly. Bit positions are indicated by ":bp", where the larger number indicates the most significant bit (MSB) and the lower number indicates the least significant bit (LSB). Figure B.3-8 Example of I/O Direct Bit Addressing (io:bp) SETB i : 0C1H : 0 (This instruction sets bits by I/O direct bit addressing.) Memory space Before execution 0000C1H 00 Memory space After execution 0000C1H 01 ● Abbreviated direct bit addressing (dir:bp) Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register (DTB). Bit positions are indicated by ":bp", where the larger number indicates the most significant bit (MSB) and the lower number indicates the least significant bit (LSB). Figure B.3-9 Example of Abbreviated Direct Bit Addressing (dir:bp) SETB S : 10H : 0 (This instruction sets bits by abbreviated direct bit addressing.) Memory space Before execution DTB 5 5 DPR 6 6 556610H 00 Memory space After execution DTB 5 5 DPR 6 6 556610H 01 ● Direct bit addressing (addr16:bp) Specify arbitrary bits in 64 kilobytes explicitly. Address bits 16 to 23 are specified by the data bank register (DTB). Bit positions are indicated by ":bp", where the larger number indicates the most significant bit (MSB) and the lower number indicates the least significant bit (LSB). Figure B.3-10 Example of Direct Bit Addressing (addr16:bp) SETB 2222H : 0 (This instruction sets bits by direct bit addressing.) Memory space Before execution DTB 5 5 552222H 00 Memory space After execution 488 DTB 5 5 552222H 01 APPENDIX B Instructions ● Vector Addressing (#vct) Specify vector data in an operand to indicate the branch destination address. There are two sizes for vector numbers: 4 bits and 8 bits. Vector addressing is used for a subroutine call or software interrupt instruction. Figure B.3-11 Example of Vector Addressing (#vct) CALLV #15 (This instruction causes a branch to the address indicated by the interrupt vector specified in an operand.) Before execution PC 0 0 0 0 Memory space PCB F F After execution FFC000H EF FFFFE0H 00 FFFFE1H D0 CALLV #15 PC D 0 0 0 PCB F F Table B.3-2 CALLV Vector List Instruction Vector address L Vector address H CALLV #0 XXFFFEH XXFFFFH CALLV #1 XXFFFCH XXFFFDH CALLV #2 XXFFFAH XXFFFBH CALLV #3 XXFFF8H XXFFF9H CALLV #4 XXFFF6H XXFFF7H CALLV #5 XXFFF4H XXFFF5H CALLV #6 XXFFF2H XXFFF3H CALLV #7 XXFFF0H XXFFF1H CALLV #8 XXFFEEH XXFFEFH CALLV #9 XXFFECH XXFFEDH CALLV #10 XXFFEAH XXFFEBH CALLV #11 XXFFE8H XXFFE9H CALLV #12 XXFFE6H XXFFE7H CALLV #13 XXFFE4H XXFFE5H CALLV #14 XXFFE2H XXFFE3H CALLV #15 XXFFE0H XXFFE1H Note: A PCB register value is set in XX. Note: When the program counter bank register (PCB) is FFH, the vector area overlaps the vector area of INT #vct8 (#0 to #7). Use vector addressing carefully (see Table B.3-2). 489 APPENDIX B Instructions B.4 Indirect Addressing In indirect addressing mode, an address is specified indirectly by the address data of an operand. ■ Indirect Addressing ● Register indirect addressing (@RWj j = 0 to 3) Memory is accessed using the contents of general-purpose register RWj as an address. Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 is used, or additional data bank register (ADB) when RW2 is used. Figure B.4-1 Example of Register Indirect Addressing (@RWj j = 0 to 3) MOVW A, @RW1 (This instruction reads data by register indirect addressing and stores it in A.) Before execution A 0716 2534 Memory space RW1 D 3 0 F After execution DTB 7 8 78D30FH EE 78D310H FF A 2534 FFEE RW1 D 3 0 F DTB 7 8 ● Register indirect addressing with post increment (@RWj+ j = 0 to 3) Memory is accessed using the contents of general-purpose register RWj as an address. After operand operation, RWj is incremented by the operand size (1 for a byte, 2 for a word, or 4 for a long word). Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 is used, or additional data bank register (ADB) when RW2 is used. If the post increment results in the address of the register that specifies the increment, the incremented value is referenced after that. In this case, if the next instruction is a write instruction, priority is given to writing by an instruction and, therefore, the register that would be incremented becomes write data. 490 APPENDIX B Instructions Figure B.4-2 Example of Register Indirect Addressing with Post Increment (@RWj+ j = 0 to 3) MOVW A, @RW1+ (This instruction reads data by register indirect addressing with post increment and stores it in A.) Before execution A 0716 2534 Memory space RW1 D 3 0 F After execution DTB 7 8 78D30FH EE 78D310H FF A 2534 FFEE RW1 D 3 1 1 DTB 7 8 ● Register indirect addressing with offset (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3) Memory is accessed using the address obtained by adding an offset to the contents of general-purpose register RWj. Two types of offset, byte and word offsets, are used. They are added as signed numeric values. Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0, RW1, RW4, or RW5 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 or RW7 is used, or additional data bank register (ADB) when RW2 or RW6 is used. Figure B.4-3 Example of Register Indirect Addressing with Offset (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3) MOVW A, @RW1+10H (This instruction reads data by register indirect addressing with an offset and stores it in A.) Before execution A 0716 2534 (+10H) RW1 D 3 0 F After execution DTB 7 8 Memory space 78D31FH EE 78D320H FF A 2534 FFEE RW1 D 3 0 F DTB 7 8 491 APPENDIX B Instructions ● Long register indirect addressing with offset (@RLi + disp8 i = 0 to 3) Memory is accessed using the address that is the 24 low-order bits obtained by adding an offset to the contents of general-purpose register RLi. The offset is 8-bits long and is added as a signed numeric value. Figure B.4-4 Example of Long Register Indirect Addressing with Offset (@RLi + disp8 i = 0 to 3) MOVW A, @RL2+25H (This instruction reads data by long register indirect addressing with an offset and stores it in A.) Before execution A 0716 2534 (+25H) RL2 F 3 8 2 After execution 4B02 Memory space 824B27H EE 824B28H FF A 2534 FFEE RL2 F 3 8 2 4B02 ● Program counter indirect addressing with offset (@PC + disp16) Memory is accessed using the address indicated by (instruction address + 4 + disp16). The offset is one word long. Address bits 16 to 23 are specified by the program counter bank register (PCB). Note that the operand address of each of the following instructions is not deemed to be (next instruction address + disp16): • DBNZ eam, rel • DWBNZ eam, rel • CBNE eam, #imm8, rel • CWBNE eam, #imm16, rel • MOV eam, #imm8 • MOVW eam, #imm16 Figure B.4-5 Example of Program Counter Indirect Addressing with Offset (@PC + disp16) MOVW A, @PC+20H (This instruction reads data by program counter indirect addressing with an offset and stores it in A.) Before execution A 0716 2534 Memory space PCB C 5 PC 4 5 5 6 After execution A 2534 FFEE PCB C 5 PC 4 5 5 A 492 +4 C54556H 73 C54557H 9E C54558H 20 C54559H 00 C5455AH . . . +20H C5457AH EE C5457BH FF MOVW A, @PC+20H APPENDIX B Instructions ● Register indirect addressing with base index (@RW0 + RW7, @RW1 + RW7) Memory is accessed using the address determined by adding RW0 or RW1 to the contents of generalpurpose register RW7. Address bits 16 to 23 are indicated by the data bank register (DTB). Figure B.4-6 Example of Register Indirect Addressing with Base Index (@RW0 + RW7, @RW1 + RW7) MOVW A, @RW1+RW7 (This instruction reads data by register indirect addressing with a base index and stores it in A.) Before execution A 0716 RW1 D 3 0 F WR7 0 1 0 1 After execution A 2534 RW1 D 3 0 F 2534 + DTB 7 8 Memory space 78D410H EE 78D411H FF FFEE DTB 7 8 WR7 0 1 0 1 493 APPENDIX B Instructions ● Program counter relative branch addressing (rel) The address of the branch destination is a value determined by adding an 8-bit offset to the program counter (PC) value. If the result of addition exceeds 16 bits, bank register incrementing or decrementing is not performed and the excess part is ignored, and therefore the address is contained within a 64-kilobyte bank. This addressing is used for both conditional and unconditional branch instructions. Address bits 16 to 23 are indicated by the program counter bank register (PCB). Figure B.4-7 Example of Program Counter Relative Branch Addressing (rel) BRA 10H (This instruction causes an unconditional relative branch.) Before execution After execution PC 3 C 2 0 PC 3 C 3 2 PCB 4 F PCB 4 F Memory space 4F3C32H Next instruction 4F3C21H 10 4F3C20H 60 BRA 10H ● Register list (rlst) Specify a register to be pushed onto or popped from a stack. Figure B.4-8 Configuration of the Register List MSB LSB RW7 RW6 RW5 RW4 RW3 RW2 RW1 RW0 A register is selected when the corresponding bit is 1 and deselected when the bit is 0. 494 APPENDIX B Instructions Figure B.4-9 Example of Register List (rlist) POPW, RW0, RW4 (This instruction transfers memory data indicated by the SP to multiple word registers indicated by the register list.) SP 34FA SP 34FE RW0 ×× ×× RW0 02 01 RW1 ×× ×× RW1 ×× ×× RW2 ×× ×× RW2 ×× ×× RW3 ×× ×× RW3 ×× ×× RW4 ×× ×× RW4 04 03 RW5 ×× ×× RW5 ×× ×× RW6 ×× ×× RW6 ×× ×× RW7 ×× ×× RW7 ×× ×× Memory space SP Memory space 01 34FAH 01 34FAH 02 34FBH 02 34FBH 03 34FCH 03 34FCH 04 34FDH 04 34FEH 34FDH SP Before execution 34FEH After execution ● Accumulator indirect addressing (@A) Memory is accessed using the address indicated by the contents of the low-order bytes (16 bits) of the accumulator (AL). Address bits 16 to 23 are specified by a mnemonic in the data bank register (DTB). Figure B.4-10 Example of Accumulator Indirect Addressing (@A) MOVW A, @A (This instruction reads data by accumulator indirect addressing and stores it in A.) Before execution A 0716 2534 DTB B B After execution A 0716 Memory space BB2534H EE BB2535H FF FFEE DTB B B 495 APPENDIX B Instructions ● Accumulator indirect branch addressing (@A) The address of the branch destination is the content (16 bits) of the low-order bytes (AL) of the accumulator. It indicates the branch destination in the bank address space. Address bits 16 to 23 are specified by the program counter bank register (PCB). For the Jump Context (JCTX) instruction, however, address bits 16 to 23 are specified by the data bank register (DTB). This addressing is used for unconditional branch instructions. Figure B.4-11 Example of Accumulator Indirect Branch Addressing (@A) JMP @A (This instruction causes an unconditional branch by accumulator indirect branch addressing.) Before execution PC 3 C 2 0 A 6677 After execution PC 3 B 2 0 A 6677 PCB 4 F 3B20 Memory space 4F3B20H Next instruction 4F3C20H 61 JMP @A PCB 4 F 3B20 ● Indirect specification branch addressing (@ear) The address of the branch destination is the word data at the address indicated by ear. Figure B.4-12 Example of Indirect Specification Branch Addressing (@ear) JMP @@RW0 (This instruction causes an unconditional branch by register indirect addressing.) Before execution After execution PC 3 C 2 0 PCB 4 F RW0 7 F 4 8 DTB 2 1 PC 3 B 2 0 RW0 7 F 4 8 496 PCB 4 F DTB 2 1 Memory space 217F48H 20 217F49H 3B 4F3B20H Next instruction 4F3C20H 73 4F3C21H 08 JMP @@RW0 APPENDIX B Instructions ● Indirect specification branch addressing (@eam) The address of the branch destination is the word data at the address indicated by eam. Figure B.4-13 Example of Indirect Specification Branch Addressing (@eam) JMP @RW0 (This instruction causes an unconditional branch by register indirect addressing.) Before execution PC 3 C 2 0 PCB 4 F RW0 3 B 2 0 After execution PC 3 B 2 0 PCB 4 F Memory space 4F3B20H Next instruction 4F3C20H 73 4F3C21H 00 JMP @RW0 RW0 3 B 2 0 497 APPENDIX B Instructions B.5 Execution Cycle Count The number of cycles required for instruction execution (execution cycle count) is obtained by adding the number of cycles required for each instruction, "correction value" determined by the condition, and the number of cycles for instruction fetch. ■ Execution Cycle Count The number of cycles required for instruction execution (execution cycle count) is obtained by adding the number of cycles required for each instruction, "correction value" determined by the condition, and the number of cycles for instruction fetch. In the mode of fetching an instruction from memory such as internal ROM connected to a 16-bit bus, the program fetches the instruction being executed in word increments. Therefore, intervening in data access increases the execution cycle count. Similarly, in the mode of fetching an instruction from memory connected to an 8-bit external bus, the program fetches every byte of an instruction being executed. Therefore, intervening in data access increases the execution cycle count. In CPU intermittent operation mode, access to a general-purpose register, internal ROM, internal RAM, internal I/O, or external data bus causes the clock to the CPU to halt for the cycle count specified by the CG0 and CG1 bits of the low power consumption mode control register. Therefore, for the cycle count required for instruction execution in CPU intermittent operation mode, add the "access count x cycle count for the halt" as a correction value to the normal execution count. 498 APPENDIX B Instructions ■ Calculating the Execution Cycle Count Table B.5-1 lists execution cycle counts and Table B.5-2 and Table B.5-3 summarize correction value data. Table B.5-1 Execution Cycle Counts in Each Addressing Mode (a) * Code Operand 00 | 07 Ri Rwi RLi 08 | 0B Execution cycle count in each addressing mode Register access count in each addressing mode See the instruction list. See the instruction list. @RWj 2 1 0C | 0F @RWj+ 4 2 10 | 17 @RWi+disp8 2 1 18 | 1B @RWi+disp16 2 1 1C 1D 1E 1F @RW0+RW7 @RW1+RW7 @PC+disp16 addr16 4 4 2 1 2 2 0 0 *: (a) is used for ~ (cycle count) and B (correction value) in "B.8 F2MC-16LX Instruction List". 499 APPENDIX B Instructions Table B.5-2 Cycle Count Correction Values for Counting Execution Cycles (b) byte * Operand (c) word * (d) long * Cycle count Access count Cycle count Access count Cycle count Access count Internal register +0 1 +0 1 +0 2 Internal memory Even address +0 1 +0 1 +0 2 Internal memory Odd address +0 1 +2 2 +4 4 External data bus 16-bit even address +1 1 +1 1 +2 2 External data bus 16-bit odd address +1 1 +4 2 +8 4 External data bus 8-bits +1 1 +4 2 +8 4 *: (b), (c), and (d) are used for ~ (cycle count) and B (correction value) in "B.8 F2MC-16LX Instruction List". Note: When an external data bus is used, the cycle counts during which an instruction is made to wait by ready input or automatic ready must also be added. Table B.5-3 Cycle Count Correction Values for Counting Instruction Fetch Cycles Instruction Byte boundary Word boundary Internal memory - +2 External data bus 16-bits - +3 External data bus 8-bits +3 - Notes: • When an external data bus is used, the cycle counts during which an instruction is made to wait by ready input or automatic ready must also be added. • Actually, instruction execution is not delayed by every instruction fetch. Therefore, use the correction values to calculate the worst case. 500 APPENDIX B Instructions B.6 Effective address field Table B.6-1 shows the effective address field. ■ Effective Address Field Table B.6-1 Effective Address Field Code Representation 00 R0 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F R1 RW1 R2 RW2 R3 RW3 R4 RW4 R5 RW5 R6 RW6 R7 RW7 @RW0 @RW1 @RW2 @RW3 @RW0+ @RW1+ @RW2+ @RW3+ @RW0+disp8 @RW1+disp8 @RW2+disp8 @RW3+disp8 @RW4+disp8 @RW5+disp8 @RW6+disp8 @RW7+disp8 @RW0+disp16 @RW1+disp16 @RW2+disp16 @RW3+disp16 @RW0+RW7 @RW1+RW7 @PC+disp16 addr16 RW0 Address format Byte count of extended address part * Register direct: Individual parts correspond to the byte, word, and long word types in order from the left. - Register indirect 0 Register indirect with post increment 0 Register indirect with 8-bit displacement 1 Register indirect with 16-bit displacement 2 Register indirect with index Register indirect with index PC indirect with 16-bit displacement Direct address 0 0 2 2 RL0 (RL0) RL1 (RL1) RL2 (RL2) RL3 (RL3) *1: Each byte count of the extended address part applies to + in the # (byte count) column in "B.8 F2MC-16LX Instruction List". 501 APPENDIX B Instructions B.7 How to Read the Instruction List Table B.7-1 describes the items used in "B.8 F2MC-16LX Instruction List", and Table B.7-2 describes the symbols used in the same list. ■ Description of Instruction Presentation Items and Symbols Table B.7-1 Description of Items in the Instruction List (1/2) Item Mnemonic Uppercase, symbol: Represented as is in the assembler. Lowercase: Rewritten in the assembler. Number of following lowercase: Indicates bit length in the instruction. # Indicates the number of bytes. ~ Indicates the number of cycles. See Table B.2-1 for the alphabetical letters in items. RG B Operation Indicates the number of times a register access is performed during instruction execution. The number is used to calculate the correction value for CPU intermittent operation. Indicates the correction value used to calculate the actual number of cycles during instruction execution. The actual number of cycles during instruction execution can be determined by adding the value in the ~ column to this value. Indicates the instruction operation. LH Indicates the special operation for bit15 to bit08 of the accumulator. Z: Transfers 0. X: Transfers after sign extension. -: No transfer AH Indicates the special operation for the 16 high-order bits of the accumulator. *: Transfers from AL to AH. -: No transfer Z: Transfers 00 to AH. X: Transfers 00H or FFH to AH after AL sign extension. I S T N Z V C 502 Description Each indicates the state of each flag: I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero), V (overflow), C (carry). *: Changes upon instruction execution. -: No change S: Set upon instruction execution. R: Reset upon instruction execution. APPENDIX B Instructions Table B.7-1 Description of Items in the Instruction List (1/2) Item Description RMW Indicates whether the instruction is a Read Modify Write instruction (reading data from memory by the I instruction and writing the result to memory). *: Read Modify Write instruction -: Not Read Modify Write instruction Note: Cannot be used for an address that has different meanings between read and write operations. Table B.7-2 Explanation on Symbols in the Instruction List (1/2) Symbol A Explanation The bit length used varies depending on the 32-bit accumulator instruction. Byte: Low-order 8 bits of byte AL Word: 16 bits of word AL Long word: 32 bits of AL and AH AH 16 high-order bits of A AL 16 low-order bits of A SP Stack pointer (USP or SSP) PC Program counter PCB program counter bank register DTB Data bank register ADB Additional data bank register SSB System stack bank register USB User stack bank register SPB Current stack bank register (SSB or USB) DPR Direct page register brg1 DTB, ADB, SSB, USB, DPR, PCB, SPB brg2 DTB, ADB, SSB, USB, DPR, SPB Ri R0, R1, R2, R3, R4, R5, R6, R7 RWi RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7 RWj RW0, RW1, RW2, RW3 RLi RL0, RL1, RL2, RL3 dir Abbreviated direct addressing addr16 Direct addressing addr24 Physical direct addressing ad24 0-15 Bit0 to bit15 of addr24 503 APPENDIX B Instructions Table B.7-2 Explanation on Symbols in the Instruction List (1/2) Symbol ad24 16-23 io Bit16 to bit23 of addr24 I/O area (000000H to 0000FFH) #imm4 4-bit immediate data #imm8 8-bit immediate data #imm16 16-bit immediate data #imm32 32-bit immediate data ext (imm8) 16-bit data obtained by sign extension of 8-bit immediate data disp8 8-bit displacement disp16 16-bit displacement bp 504 Explanation Bit offset vct4 Vector number (0 to 15) vct8 Vector number (0 to 255) ( )b Bit address rel PC relative branch ear Effective addressing (code 00 to 07) eam Effective addressing (code 08 to 1F) rlst Register list APPENDIX B Instructions B.8 F2MC-16LX Instruction List Table B.8-1 to Table B.8-18 list the instructions used by the F2MC-16LX. ■ F2MC-16LX Instruction List Table B.8-1 41 Transfer Instructions (Byte) Mnemonic MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVN MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV XCH XCH XCH XCH A,dir A,addr16 A,Ri A,ear A,eam A,io A,#imm8 A,@A A,@RLi+disp8 A,#imm4 A,dir A,addr16 A,Ri A,ear A,eam A,io A,#imm8 A,@A A,@RWi+disp8 A,@RLi+disp8 dir,A addr16,A Ri,A ear,A eam,A io,A @RLi+disp8,A Ri,ear Ri,eam ear,Ri eam,Ri Ri,#imm8 io,#imm8 dir,#imm8 ear,#imm8 eam,#imm8 @AL,AH A,ear A,eam Ri,ear Ri,eam # ~ RG B 2 3 1 2 2+ 2 2 2 3 1 2 3 2 2 2+ 2 2 2 2 3 2 3 1 2 2+ 2 3 2 2+ 2 2+ 2 3 3 3 3+ 2 2 2+ 2 2+ 3 4 2 2 3 + (a) 3 2 3 10 1 3 4 2 2 3 + (a) 3 2 3 5 10 3 4 2 2 3 + (a) 3 10 3 4 + (a) 4 5 + (a) 2 5 5 2 4 + (a) 3 4 5 + (a) 7 9 + (a) 0 0 1 1 0 0 0 0 2 0 0 0 1 1 0 0 0 0 1 2 0 0 1 1 0 0 2 2 1 2 1 1 0 0 1 0 0 2 0 4 2 (b) (b) 0 0 (b) (b) 0 (b) (b) 0 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) 0 0 (b) (b) (b) 0 (b) 0 (b) 0 (b) (b) 0 (b) (b) 0 2 × (b) 0 2 × (b) Operation byte (A) ← (dir) byte (A) ← (addr16) byte (A) ← (Ri) byte (A) ← (ear) byte (A) ← (eam) byte (A) ← (io) byte (A) ← imm8 byte (A) ← ((A)) byte (A) ← ((RLi)+disp8) byte (A) ← imm4 byte (A) ← (dir) byte (A) ← (addr16) byte (A) ← (Ri) byte (A) ← (ear) byte (A) ← (eam) byte (A) ← (io) byte (A) ← imm8 byte (A) ← ((A)) byte (A) ← ((RWi)+disp8) byte (A) ← ((RLi)+disp8) byte (dir) ← (A) byte (addr16) ← (A) byte (Ri) ← (A) byte (ear) ← (A) byte (eam) ← (A) byte (io) ← (A) byte ((RLi)+disp8) ← (A) byte (Ri) ← (ear) byte (Ri) ← (eam) byte (ear) ← (Ri) byte (eam) ← (Ri) byte (Ri) ← imm8 byte (io) ← imm8 byte (dir) ← imm8 byte (ear) ← imm8 byte (eam) ← imm8 byte ((A)) ← (AH) byte (A) ↔ (ear) byte (A) ↔ (eam) byte (Ri) ↔ (ear) byte (Ri) ↔ (eam) LH AH I S T N Z V C RMW Z Z Z Z Z Z Z Z Z Z X X X X X X X X X X Z Z - * * * * * * * * * * * * * * * * * * - - - - * * * * * * * * * R * * * * * * * * * * * * * * * * * * * * * * * * - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - - - Note: See Table B.5-1 and Table B.5-2 for information on (a) and (b) in the table. 505 APPENDIX B Instructions Table B.8-2 38 Transfer Instructions (Word, Long Word) Mnemonic MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW XCHW XCHW XCHW XCHW MOVL MOVL MOVL MOVL MOVL A,dir A,addr16 A,SP A,RWi A,ear A,eam A,io A,@A A,#imm16 A,@RWi+disp8 A,@RLi+disp8 dir,A addr16,A SP,A RWi,A ear,A eam,A io,A @RWi+disp8,A @RLi+disp8,A RWi,ear RWi,eam ear,RWi eam,RWi RWi,#imm16 io,#imm16 ear,#imm16 eam,#imm16 @AL,AH A,ear A,eam RWi, ear RWi, eam A,ear A,eam A,#imm32 ear,A eam,A # ~ RG B 2 3 1 1 2 2+ 2 2 3 2 3 2 3 1 1 2 2+ 2 2 3 2 2+ 2 2+ 3 4 4 4+ 2 2 2+ 2 2+ 2 2+ 5 2 2+ 3 4 1 2 2 3 + (a) 3 3 2 5 10 3 4 1 2 2 3 + (a) 3 5 10 3 4 + (a) 4 5 + (a) 2 5 2 4 + (a) 3 4 5 + (a) 7 9 + (a) 4 5 + (a) 3 4 5 + (a) 0 0 0 1 1 0 0 0 0 1 2 0 0 0 1 1 0 0 1 2 2 1 2 1 1 0 1 0 0 2 0 4 2 2 0 0 2 0 (c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) (c) (c) 0 0 0 (c) (c) (c) (c) 0 (c) 0 (c) 0 (c) 0 (c) (c) 0 2 × (c) 0 2 × (c) 0 (d) 0 0 (d) Operation word (A) ← (dir) word (A) ← (addr16) word (A) ← (SP) word (A) ← (RWi) word (A) ← (ear) word (A) ← (eam) word (A) ← (io) word (A) ← ((A)) word (A) ← imm16 word (A) ← ((RWi)+disp8) word (A) ← ((RLi)+disp8) word (dir) ← (A) word (addr16) ← (A) word (SP) ← (A) word (RWi) ← (A) word (ear) ← (A) word (eam) ← (A) word (io) ← (A) word ((RWi)+disp8) ← (A) word ((RLi)+disp8) ← (A) word (RWi) ← (ear) word (RWi) ← (eam) word (ear) ← (RWi) word (eam) ← (RWi) word (RWi) ← imm16 word (io) ← imm16 word (ear) ← imm16 word (eam) ← imm16 word ((A)) ← (AH) word (A) ↔ (ear) word (A) ↔ (eam) word (RWi) ↔ (ear) word (RWi) ↔ (eam) long (A) ← (ear) long (A) ← (eam) long (A) ← imm32 long (ear) ← (A) long(eam) ← (A) LH AH I S T N Z V C RMW - * * * * * * * * * * - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - - Note: See Table B.5-1 and Table B.5-2 for information on (a), (c), and (d) in the table. 506 APPENDIX B Instructions Table B.8-3 42 Addition/Subtraction Instructions (Byte, Word, Long Word) Mnemonic # ~ RG B ADD ADD ADD ADD ADD ADD ADDC ADDC ADDC ADDDC A,#imm8 A,dir A,ear A,eam ear,A eam,A A A,ear A,eam A 2 2 2 2+ 2 2+ 1 2 2+ 1 2 5 3 4 + (a) 3 5 + (a) 2 3 4 + (a) 3 0 0 1 0 2 0 0 1 0 0 0 (b) 0 (b) 0 2 × (b) 0 0 (b) 0 SUB SUB SUB SUB SUB SUB SUBC SUBC SUBC SUBDC A,#imm8 A,dir A,ear A,eam ear,A eam,A A A,ear A,eam A 2 2 2 2+ 2 2+ 1 2 2+ 1 2 5 3 4 + (a) 3 5 + (a) 2 3 4 + (a) 3 0 0 1 0 2 0 0 1 0 0 0 (b) 0 (b) 0 2 × (b) 0 0 (b) 0 ADDW ADDW ADDW ADDW ADDW ADDW ADDCW ADDCW SUBW SUBW SUBW SUBW SUBW SUBW SUBCW SUBCW ADDL ADDL ADDL SUBL SUBL SUBL A A,ear A,eam A,#imm16 ear,A eam,A A,ear A,eam A A,ear A,eam A,#imm16 ear,A eam,A A,ear A,eam A,ear A,eam A,#imm32 A,ear A,eam A,#imm32 1 2 2+ 3 2 2+ 2 2+ 1 2 2+ 3 2 2+ 2 2+ 2 2+ 5 2 2+ 5 2 3 4+(a) 2 3 5+(a) 3 4+(a) 2 3 4+(a) 2 3 5+(a) 3 4+(a) 6 7+(a) 4 6 7+(a) 4 0 1 0 0 2 0 1 0 0 1 0 0 2 0 1 0 2 0 0 2 0 0 0 0 (c) 0 0 2 × (c) 0 (c) 0 0 (c) 0 0 2 × (c) 0 (c) 0 (d) 0 0 (d) 0 Operation byte (A) ← (A) + imm8 byte (A) ← (A) + (dir) byte (A) ← (A) + (ear) byte (A) ← (A) + (eam) byte (ear) ← (ear) + (A) byte (eam) ← (eam) + (A) byte (A) ← (AH) + (AL) + (C) byte (A) ← (A) + (ear)+ (C) byte (A) ← (A) + (eam)+ (C) byte (A) ← (AH) + (AL) + (C) (decimal) byte (A) ← (A) - imm8 byte (A) ← (A) - (dir) byte (A) ← (A) - (ear) byte (A) ← (A) - (eam) byte (ear) ← (ear) - (A) byte (eam) ← (eam) - (A) byte (A) ← (AH) - (AL) - (C) byte (A) ← (A) - (ear) - (C) byte (A) ← (A) - (eam) - (C) byte (A) ← (AH) - (AL) - (C) (decimal) word (A) ← (AH) + (AL) word (A) ← (A) + (ear) word (A) ← (A) + (eam) word (A) ← (A) + imm16 word (ear) ← (ear) + (A) word (eam) ← (eam) + (A) word (A) ← (A) + (ear) + (C) word (A) ← (A) + (eam) + (C) word (A) ← (AH) - (AL) word (A) ← (A) - (ear) word (A) ← (A) - (eam) word (A) ← (A) - imm16 word (ear) ← (ear) - (A) word (eam) ← (eam) - (A) word (A) ← (A) - (ear) - (C) word (A) ← (A) - (eam) - (C) long (A) ← (A) + (ear) long (A) ← (A) + (eam) long (A) ← (A) + imm32 long (A) ← (A) - (ear) long (A) ← (A) - (eam) long (A) ← (A) - imm32 LH AH I S T N Z V C RMW Z Z Z Z Z Z Z Z Z - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - Z Z Z Z Z Z Z Z - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. 507 APPENDIX B Instructions Table B.8-4 12 Increment/decrement Instructions (Byte, Word, Long Word) # ~ RG B INC Mnemonic ear 2 3 2 0 INC eam 2+ 5+(a) 0 2 × (b) DEC ear 2 3 2 0 DEC eam 2+ 5+(a) 0 2 × (b) INCW ear 2 3 2 0 INCW eam 2+ 5+(a) 0 2 × (c) DECW ear 2 3 2 0 DECW eam 2+ 5+(a) 0 2 × (c) INCL ear 2 7 4 0 INCL eam 2+ 9+(a) 0 2 × (d) DECL ear 2 7 4 0 DECL eam 2+ 9+(a) 0 2 × (d) LH AH I S T N Z V C byte (ear) ← (ear) + 1 Operation - - - - - * * * - RMW - byte (eam) ← (eam) + 1 - - - - - * * * - * byte (ear) ← (ear) - 1 - - - - - * * * - - byte (eam) ← (eam) - 1 - - - - - * * * - * word (ear) ← (ear) + 1 - - - - - * * * - - word (eam) ← (eam) + 1 - - - - - * * * - * word (ear) ← (ear) - 1 - - - - - * * * - - word (eam) ← (eam) - 1 - - - - - * * * - * long (ear) ← (ear) + 1 - - - - - * * * - - long (eam) ← (eam) + 1 - - - - - * * * - * long (ear) ← (ear) - 1 - - - - - * * * - - long (eam) ← (eam) - 1 - - - - - * * * - * Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. Table B.8-5 11 Compare Instructions (Byte, Word, Long Word) Mnemonic # ~ RG B Operation LH AH I S T N Z V C RMW CMP A 1 1 0 0 byte (AH) - (AL) - - - - - * * * * - CMP A,ear 2 2 1 0 byte (A) - (ear) - - - - - * * * * - CMP A,eam 2+ 3+(a) 0 (b) byte (A) - (eam) - - - - - * * * * - CMP A,#imm8 2 2 0 0 byte (A) - imm8 - - - - - * * * * - CMPW A 1 1 0 0 word (AH) - (AL) - - - - - * * * * - CMPW A,ear 2 2 1 0 word (A) - (ear) - - - - - * * * * - CMPW A,eam 2+ 3+(a) 0 (c) word (A) - (eam) - - - - - * * * * - CMPW A,#imm16 3 2 0 0 word (A) - imm16 - - - - - * * * * - CMPL A,ear 2 6 2 0 long (A) - (ear) - - - - - * * * * - CMPL A,eam 2+ 7+(a) 0 (d) long (A) - (eam) - - - - - * * * * - CMPL A,#imm32 5 3 0 0 long (A) - imm32 - - - - - * * * * - Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. 508 APPENDIX B Instructions Table B.8-6 11 Unsigned Multiplication/Division Instructions (Word, Long Word) # ~ RG B LH AH I S T N Z V C RMW DIVU Mnemonic A 1 *1 0 0 word (AH) / byte (AL) quotient → byte (AL) remainder → byte (AH) Operation - - - - - - - * * - DIVU A,ear 2 *2 1 0 word (A) / byte (ear) quotient → byte (A) remainder → byte (ear) - - - - - - - * * - DIVU A,eam 2+ *3 0 *6 word (A) / byte (eam) quotient → byte (A) remainder → byte (eam) - - - - - - - * * - DIVUW A,ear 2 *4 1 0 long (A) / word (ear) quotient → word (A) remainder → word (ear) - - - - - - - * * - DIVUW A,eam 2+ *5 0 *7 long (A) / word (eam) quotient → word (A) remainder → word (eam) - - - - - - - * * - MULU A 1 *8 0 0 byte (AH) * byte (AL) → word (A) - - - - - - - - - - MULU A,ear 2 *9 1 0 byte (A) * byte (ear) → word (A) - - - - - - - - - - MULU A,eam 2+ *10 0 (b) byte (A) * byte (eam) → word (A) - - - - - - - - - - MULUW A 1 *11 0 0 word (AH) * word (AL) → Long (A) - - - - - - - - - - MULUW A,ear 2 *12 1 0 word (A) * word (ear) → Long (A) - - - - - - - - - - MULUW A,eam 2+ *13 0 (c) word (A) * word (eam) → Long (A) - - - - - - - - - - *1: 3: Division by 0 7: Overflow 15: Normal *2: 4: Division by 0 8: Overflow 16: Normal *3: 6+(a): Division by 0 9+(a): Overflow 19+(a): Normal *4: 4: Division by 0 7: Overflow 22: Normal *5: 6+(a): Division by 0 8+(a): Overflow 26+(a): Normal *6: (b): Division by 0 or overflow 2 × (b): Normal *7: (c): Division by 0 or overflow 2 × (c): Normal *8: 3: Byte (AH) is 0. 7: Byte (AH) is not 0. *9: 4: Byte (ear) is 0. 8: Byte (ear) is not 0. *10: 5+(a): Byte (eam) is 0, 9+(a): Byte (eam) is not 0. *11: 3: Word (AH) is 0. 11: Word (AH) is not 0. *12: 4: Word (ear) is 0. 12: Word (ear) is not 0. *13: 5+(a): Word (eam) is 0. 13+(a): Word (eam) is not 0. Note: See Table B.5-1 and Table B.5-2 for information on (a) to (c) in the table. 509 APPENDIX B Instructions Table B.8-7 11 Signed Multiplication/Division Instructions (Word, Long Word) # ~ RG B LH AH I S T N Z V C RMW DIV Mnemonic A 2 *1 0 0 word (AH) / byte (AL) quotient → byte (AL) remainder → byte (AH) Operation Z - - - - - - * * - DIV A,ear 2 *2 1 0 word (A) / byte (ear) quotient → byte (A) remainder → byte (ear) Z - - - - - - * * - DIV A,eam 2+ *3 0 *6 word (A) / byte (eam) quotient → byte (A) remainder → byte (eam) Z - - - - - - * * - DIVW A,ear 2 *4 1 0 long (A) / word (ear) quotient → word (A) remainder → word (ear) - - - - - - - * * - DIVW A,eam 2+ *5 0 *7 long (A) / word (eam) quotient → word (A) remainder → word (eam) - - - - - - - * * - MUL A 2 *8 0 0 byte (AH) * byte (AL) → word (A) - - - - - - - - - - MUL A,ear 2 *9 1 0 byte (A) * byte (ear) → word (A) - - - - - - - - - - MUL A,eam 2+ *10 0 (b) byte (A) * byte (eam) → word (A) - - - - - - - - - - MULW A 2 *11 0 0 word (AH) * word (AL) → Long (A) - - - - - - - - - - MULW A,ear 2 *12 1 0 word (A) * word (ear) → Long (A) - - - - - - - - - - MULW A,eam 2+ *13 0 (c) word (A) * word (eam) → Long (A) - - - - - - - - - - *1: *2: *3: *4: 3: Division by 0, 8 or 18: Overflow, 18: Normal 4: Division by 0, 11 or 22: Overflow, 23: Normal 5+(a): Division by 0, 12+(a) or 23+(a): Overflow, 24+(a): Normal When dividend is positive; 4: Division by 0, 12 or 30: Overflow, 31: Normal When dividend is negative; 4: Division by 0, 12 or 31: Overflow, 32: Normal *5: When dividend is positive; 5+(a): Division by 0, 12+(a) or 31+(a): Overflow, 32+(a): Normal When dividend is negative; 5+(a): Division by 0, 12+(a) or 32+(a): Overflow, 33+(a): Normal *6: (b): Division by 0 or overflow, 2 × (b): Normal *7: (c): Division by 0 or overflow, 2 × (c): Normal *8: 3: Byte (AH) is 0, 12: result is positive, 13: result is negative *9: 4: Byte (ear) is 0, 13: result is positive, 14: result is negative *10: 5+(a): Byte (eam) is 0, 14+(a): result is positive, 15+(a): result is negative *11: 3: Word (AH) is 0, 16: result is positive, 19: result is negative *12: 4: Word (ear) is 0, 17: result is positive, 20: result is negative *13: 5+(a): Word (eam) is 0, 18+(a): result is positive, 21+(a): result is negative Notes: • The execution cycle count found when an overflow occurs in a DIV or DIVW instruction may be a pre-operation count or a post-operation count depending on the detection timing. • When an overflow occurs with DIV or DIVW instruction, the contents of the AL are destroyed. • See Table B.5-1 and Table B.5-2 for information on (a) to (c) in the table. 510 APPENDIX B Instructions Table B.8-8 39 Logic 1 Instructions (Byte, Word) Mnemonic # ~ RG B Operation LH AH I S T N Z V C AND A,#imm8 2 2 0 0 byte (A) ← (A) and imm8 - - - - - * * R - RMW - AND A,ear 2 3 1 0 byte (A) ← (A) and (ear) - - - - - * * R - - AND A,eam 2+ 4+(a) 0 (b) byte (A) ← (A) and (eam) - - - - - * * R - AND ear,A 2 3 2 0 byte (ear) ← (ear) and (A) - - - - - * * R - - AND eam,A 2+ 5+(a) 0 2 × (b) byte (eam) ← (eam) and (A) - - - - - * * R - * OR A,#imm8 2 2 0 0 byte (A) ← (A) or imm8 - - - - - * * R - - OR A,ear 2 3 1 0 byte (A) ← (A) or (ear) - - - - - * * R - - OR A,eam 2+ 4+(a) 0 (b) byte (A) ← (A) or (eam) - - - - - * * R - - OR ear,A 2 3 2 0 byte (ear) ← (ear) or (A) - - - - - * * R - - OR eam,A 2+ 5+(a) 0 2 × (b) byte (eam) ← (eam) or (A) - - - - - * * R - * XOR A,#imm8 2 2 0 0 byte (A) ← (A) xor imm8 - - - - - * * R - - XOR A,ear 2 3 1 0 byte (A) ← (A) xor (ear) - - - - - * * R - - XOR A,eam 2+ 4+(a) 0 (b) byte (A) ← (A) xor (eam) - - - - - * * R - - XOR ear,A 2 3 2 0 byte (ear) ← (ear) xor (A) - - - - - * * R - - XOR eam,A 2+ 5+(a) 0 2 × (b) byte (eam) ← (eam) xor (A) - - - - - * * R - * NOT A 1 2 0 0 byte (A) ← not (A) - - - - - * * R - - NOT ear 2 3 2 0 byte (ear) ← not (ear) - - - - - * * R - - NOT eam 2+ 5+(a) 0 2 × (b) byte (eam) ← not (eam) - - - - - * * R - * ANDW A 1 2 0 0 word (A) ← (AH) and (A) - - - - - * * R - - ANDW A,#imm16 3 2 0 0 word (A) ← (A) and imm16 - - - - - * * R - - ANDW A,ear 2 3 1 0 word (A) ← (A) and (ear) - - - - - * * R - - ANDW A,eam 2+ 4+(a) 0 (c) word (A) ← (A) and (eam) - - - - - * * R - - ANDW ear,A 2 3 2 0 word (ear) ← (ear) and (A) - - - - - * * R - - ANDW eam,A 2+ 5+(a) 0 2 × (c) word (eam) ← (eam) and (A) - - - - - * * R - * ORW A 1 2 0 0 word (A) ← (AH) or (A) - - - - - * * R - - ORW A,#imm16 3 2 0 0 word (A) ← (A) or imm16 - - - - - * * R - - ORW A,ear 2 3 1 0 word (A) ← (A) or (ear) - - - - - * * R - - ORW A,eam 2+ 4+(a) 0 (c) word (A) ← (A) or (eam) - - - - - * * R - - ORW ear,A 2 3 2 0 word (ear) ← (ear) or (A) - - - - - * * R - - ORW eam,A 2+ 5+(a) 0 2 × (c) word (eam) ← (eam) or (A) - - - - - * * R - * XORW A 1 2 0 0 word (A) ← (AH) xor (A) - - - - - * * R - - XORW A,#imm16 3 2 0 0 word (A) ← (A) xor imm16 - - - - - * * R - - XORW A,ear 2 3 1 0 word (A) ← (A) xor (ear) - - - - - * * R - - XORW A,eam 2+ 4+(a) 0 (c) word (A) ← (A) xor (eam) - - - - - * * R - - XORW ear,A 2 3 2 0 word (ear) ← (ear) xor (A) - - - - - * * R - - XORW eam,A 2+ 5+(a) 0 2 × (c) word (eam) ← (eam) xor (A) - - - - - * * R - * NOTW A 1 2 0 0 word (A) ← not (A) - - - - - * * R - - NOTW ear 2 3 2 0 word (ear) ← not (ear) - - - - - * * R - - NOTW eam 2+ 5+(a) 0 2 × (c) word (eam) ← not (eam) - - - - - * * R - * Note: See Table B.5-1 and Table B.5-2 for information on (a) to (c) in the table. 511 APPENDIX B Instructions Table B.8-9 6 Logic 2 Instructions (Long Word) Mnemonic # ~ RG B LH AH I S T N Z V C RMW ANDL A,ear 2 6 2 0 long (A) ← (A) and (ear) Operation - - - - - * * R - - ANDL A,eam 2+ 7+(a) 0 (d) long (A) ← (A) and (eam) - - - - - * * R - - ORL A,ear 2 6 2 0 long (A) ← (A) or (ear) - - - - - * * R - - ORL A,eam 2+ 7+(a) 0 (d) long (A) ← (A) or (eam) - - - - - * * R - - XORL A,ear 2 6 2 0 long (A) ← (A) xor (ear) - - - - - * * R - - XORL A,eam 2+ 7+(a) 0 (d) long (A) ← (A) xor (eam) - - - - - * * R - - Note: See Table B.5-1 and Table B.5-2 for information on (a) and (d) in the table. Table B.8-10 6 Sign Inversion Instructions (Byte, Word) Mnemonic NEG A # ~ RG B 1 2 0 0 byte (A) ← 0 - (A) byte (ear) ← 0 - (ear) - - - - - * * * * - byte (eam) ← 0 - (eam) - - - - - * * * * * word (A) ← 0 - (A) - - - - - * * * * - word (ear) ← 0 - (ear) - - - - - * * * * - word (eam) ← 0 - (eam) - - - - - * * * * * NEG ear 2 3 2 0 NEG eam 2+ 5+(a) 0 2 × (b) NEGW A 1 2 0 0 NEGW ear 2 3 2 0 NEGW eam 2+ 5+(a) 0 2 × (c) Operation LH AH I S T N Z V C RMW X - - - - * * * * - Note: See Table B.5-1 and Table B.5-2 for information on (a) to (c) in the table. Table B.8-11 1 Normalization Instruction (Long Word) Mnemonic NRML A,R0 # ~ RG B 2 *1 1 0 Operation long (A) ← Shift left to the position where '1' is set for the first time. byte (R0) ← Shift count at that time *1: 4 when all accumulators have a value of 0; otherwise, 6+(R0) 512 LH AH I S T N Z V C RMW - - - - - - * - - - APPENDIX B Instructions Table B.8-12 18 Shift Instructions (Byte, Word, Long Word) # ~ RG B LH AH I S T N Z V C RMW RORC Mnemonic A 2 2 0 0 byte (A) ← Right rotation with carry Operation - - - - - * * - * - ROLC A 2 2 0 0 byte (A) ← Right rotation with carry - - - - - * * - * - RORC ear 2 3 2 0 byte (ear) ← Right rotation with carry - - - - - * * - * - RORC eam 2+ 5+(a) 0 2 × (b) byte (eam) ← Right rotation with carry - - - - - * * - * * ROLC ear 2 3 2 0 byte (ear) ← Left rotation with carry - - - - - * * - * - ROLC eam 2+ 5+(a) 0 2 × (b) byte (eam) ← Left rotation with carry - - - - - * * - * * - ASR A,R0 2 *1 1 0 byte (A) ← Arithmetic right shift (A, 1 bit) - - - - * * * - * LSR A,R0 2 *1 1 0 byte (A) ← Logical right barrel shift (A, R0) - - - - * * * - * - LSL A,R0 2 *1 1 0 byte (A) ← Logical left barrel shift (A, R0) - - - - - * * - * - ASRW A 1 2 0 0 word (A) ← Arithmetic right shift (A, 1 bit) - - - - * * * - * - LSRW A/SHRW A 1 2 0 0 word (A) ← Logical right shift (A, 1 bit) - - - - * R * - * - LSLW A/SHLW A 1 2 0 0 word (A) ← Logical left shift (A, 1 bit) - - - - - * * - * - ASRW A,R0 2 *1 1 0 word (A) ← Arithmetic right barrel shift (A, R0) - - - - * * * - * LSRW A,R0 2 *1 1 0 word (A) ← Logical right barrel shift (A, R0) - - - - * * * - * - LSLW A,R0 2 *1 1 0 word (A) ← Logical left barrel shift (A, R0) - - - - - * * - * - ASRL A,R0 2 *2 1 0 long (A) ← Arithmetic right barrel shift (A, R0) - - - - * * * - * - LSRL A,R0 2 *2 1 0 long (A) ← Logical right barrel shift (A, R0) - - - - * * * - * - LSLL A,R0 2 *2 1 0 long (A) ← Logical left barrel shift (A, R0) - - - - - * * - * - *1: 6 when R0 is 0; otherwise, 5 + (R0) *2: 6 when R0 is 0; otherwise, 6 + (R0) Note: See Table B.5-1 and Table B.5-2 for information on (a) and (b) in the table. 513 APPENDIX B Instructions Table B.8-13 31 Branch 1 Instructions # ~ RG B LH AH I S T N Z V C BZ/BEQ Mnemonic rel 2 *1 0 0 Branch on (Z) = 1 Operation - - - - - - - - - - BNZ/ BNE rel 2 *1 0 0 Branch on (Z) = 0 - - - - - - - - - - BC/BLO rel 2 *1 0 0 Branch on (C) = 1 - - - - - - - - - - BNC/ BHS rel 2 *1 0 0 Branch on (C) = 0 - - - - - - - - - - BN rel 2 *1 0 0 Branch on (N) = 1 - - - - - - - - - - BP rel 2 *1 0 0 Branch on (N) = 0 - - - - - - - - - - BV rel 2 *1 0 0 Branch on (V) = 1 - - - - - - - - - - BNV rel 2 *1 0 0 Branch on (V) = 0 - - - - - - - - - - BT rel 2 *1 0 0 Branch on (T) = 1 - - - - - - - - - - BNT rel 2 *1 0 0 Branch on (T) = 0 - - - - - - - - - - BLT rel 2 *1 0 0 Branch on (V) xor (N) = 1 - - - - - - - - - - BGE rel 2 *1 0 0 Branch on (V) xor (N) = 0 - - - - - - - - - - BLE rel 2 *1 0 0 Branch on ((V) xor (N)) or (Z) = 1 - - - - - - - - - - BGT rel 2 *1 0 0 Branch on ((V) xor (N)) or (Z) = 0 - - - - - - - - - - BLS rel 2 *1 0 0 Branch on (C) or (Z) = 1 - - - - - - - - - - BHI rel 2 *1 0 0 Branch on (C) or (Z) = 0 - - - - - - - - - - BRA rel 2 *1 0 0 Unconditional branch - - - - - - - - - - JMP @A 1 2 0 0 word (PC) ← (A) - - - - - - - - - - JMP addr16 3 3 0 0 word (PC) ← addr16 - - - - - - - - - - JMP @ear 2 3 1 0 word (PC) ← (ear) - - - - - - - - - - JMP @eam 2+ 4+(a) 0 (c) word (PC) ← (eam) - - - - - - - - - - JMPP @ear *3 2 5 2 0 word (PC) ← (ear), (PCB) ← (ear+2) - - - - - - - - - - JMPP @eam *3 2+ 6+(a) 0 (d) word (PC) ← (eam), (PCB) ← (eam+2) - - - - - - - - - - JMPP addr24 4 4 0 0 word (PC) ← ad24 0-15, (PCB) ← ad24 16-23 - - - - - - - - - - CALL @ear *4 2 6 1 (c) word (PC) ← (ear) - - - - - - - - - - CALL @eam *4 2+ 7+(a) 0 2 × (c) word (PC) ← (eam) - - - - - - - - - - CALL addr16 *5 3 6 0 (c) word (PC) ← addr16 - - - - - - - - - - CALLV #vct4 *5 1 7 0 2 × (c) Vector call instruction - - - - - - - - - - CALLP @ear *6 2 10 2 2 × (c) word (PC) ← (ear), (PCB) ← (ear+2) - - - - - - - - - - CALLP @eam *6 2+ 11+(a) 0 *2 word (PC) ← (eam), (PCB) ← (eam+2) - - - - - - - - - - CALLP addr24 *7 4 10 0 2 × (c) word (PC) ← ad24 0-15, (PCB) ← ad24 16-23 - - - - - - - - - - *1: 4 when a branch is made; otherwise, 3 *2: 3 × (c) + (b) *3: Read (word) of branch destination address *4: W: Save to stack (word) R: Read (word) of branch destination address *5: Save to stack (word) *6: W: Save to stack (long word), R: Read (long word) of branch destination address *7: Save to stack (long word) Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. 514 RMW APPENDIX B Instructions Table B.8-14 19 Branch 2 Instructions Mnemonic # ~ RG B LH AH I S T N Z V C CBNE A,#imm8,rel 3 *1 0 0 Branch on byte (A) not equal to imm8 Operation - - - - - * * * * RMW - CWBNE A,#imm16,rel 4 *1 0 0 Branch on word (A) not equal to imm16 - - - - - * * * * - CBNE ear,#imm8,rel 4 *2 1 0 Branch on byte (ear) not equal to imm8 - - - - - * * * * - CBNE eam,#imm8,rel *9 4+ *3 0 (b) Branch on byte (eam) not equal to imm8 - - - - - * * * * - CWBNE ear,#imm16,rel 5 *4 1 0 Branch on word (ear) not equal to imm16 - - - - - * * * * - CWBNE eam,#imm16,rel*9 5+ *3 0 (c) Branch on word (eam) not equal to imm16 - - - - - * * * * - byte (ear) ← (ear) - 1, Branch on (ear) not equal to 0 - - - - - * * * - - - - - - - * * * - * - - - - - * * * - - - - - - - * * * - * DBNZ ear,rel 3 *5 2 DBNZ eam,rel 3+ *6 2 DWBNZ ear,rel 3 *5 2 DWBNZ eam,rel 3+ *6 2 0 2 × (b) byte (eam) ← (eam) - 1, Branch on (eam) not equal to 0 0 word (ear) ← (ear) - 1, Branch on (ear) not equal to 0 2 × (c) word (eam) ← (eam) - 1, Branch on (eam) not equal to 0 INT #vct8 2 20 0 8 × (c) Software interrupt - - R S - - - - - - INT addr16 3 16 0 6 × (c) Software interrupt - - R S - - - - - - INTP addr24 4 17 0 6 × (c) Software interrupt - - R S - - - - - - 1 20 0 8 × (c) Software interrupt - - R S - - - - - - 1 *8 0 *7 Return from interrupt - - * * * * * * * - 2 6 0 (c) Saves the old frame pointer in the stack upon entering the function, then sets the new frame pointer and reserves the local pointer area. - - - - - - - - - - 1 5 0 (c) Recovers the old frame pointer from the stack upon exiting the function. - - - - - - - - - - INT9 RETI LINK #imm8 UNLINK RET *10 1 4 0 (c) Return from subroutine - - - - - - - - - - RETP *11 1 6 0 (d) Return from subroutine - - - - - - - - - - *1: 5 when a branch is made; otherwise, 4 *2: 13 when a branch is made; otherwise, 12 *3: 7+(a) when a branch is made; otherwise, 6+(a) *4: 8 when a branch is made; otherwise, 7 *5: 7 when a branch is made; otherwise, 6 *6: 8+(a) when a branch is made; otherwise, 7+(a) *7: 3 × (b) + 2 × (c) when jumping to the next interruption request; 6 × (c) when returning from the current interruption *8: 15 when jumping to the next interruption request; 17 when returning from the current interruption *9: Do not use RWj+ addressing mode with a CBNE or CWBNE instruction. *10: Return from stack (word) *11: Return from stack (long word) Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. 515 APPENDIX B Instructions Table B.8-15 28 Other Control Instructions (Byte, Word, Long Word) # ~ RG B LH AH I S T N Z V C RMW PUSHW Mnemonic A 1 4 0 (c) word (SP) ← (SP) - 2, ((SP)) ← (A) Operation - - - - - - - - - - PUSHW AH 1 4 0 (c) word (SP) ← (SP) - 2, ((SP)) ← (AH) - - - - - - - - - - PUSHW PS 1 4 0 (c) word (SP) ← (SP) - 2, ((SP)) ← (PS) - - - - - - - - - - PUSHW rlst 2 *3 *5 *4 (SP) ← (SP) - 2n, ((SP)) ← (rlst) - - - - - - - - - - POPW A 1 3 0 (c) word (A) ← ((SP)), (SP) ← (SP) + 2 - * - - - - - - - - POPW AH 1 3 0 (c) word (AH) ← ((SP)), (SP) ← (SP) + 2 - - - - - - - - - - POPW PS 1 4 0 (c) word (PS) ← ((SP)), (SP) ← (SP) + 2 - - * * * * * * * - POPW rlst 2 *2 *5 *4 (rlst) ← ((SP)), (SP) ← (SP) + 2n - - - - - - - - - - JCTX @A 1 14 0 6 × (c) Context switch instruction - - * * * * * * * - AND CCR,#imm8 2 3 0 0 byte (CCR) ← (CCR) and imm8 - - * * * * * * * - OR CCR,#imm8 2 3 0 0 byte (CCR) ← (CCR) or imm8 - - * * * * * * * - MOV RP,#imm8 2 2 0 0 byte (RP) ← imm8 - - - - - - - - - - MOV ILM,#imm8 2 2 0 0 byte (ILM) ← imm8 - - - - - - - - - - MOVEA RWi,ear 2 3 1 0 word (RWi) ← ear - - - - - - - - - - MOVEA RWi,eam 2+ 2+(a) 1 0 word (RWi) ← eam - - - - - - - - - - MOVEA A,ear 2 1 0 0 word (A) ← ear - * - - - - - - - - MOVEA A,eam 2+ 1+(a) 0 0 word (A) ← eam - * - - - - - - - - ADDSP #imm8 2 3 0 0 word (SP) ← (SP) + ext(imm8) - - - - - - - - - - ADDSP #imm16 3 3 0 0 word (SP) ← (SP) + imm16 - - - - - - - - - - MOV A,brg1 2 *1 0 0 byte (A) ← (brg1) Z * - - - * * - - - MOV brg2,A 2 1 0 0 byte (brg2) ← (A) - - - - - * * - - - NOP 1 1 0 0 No operation - - - - - - - - - - ADB 1 1 0 0 Prefix code for AD space access - - - - - - - - - - DTB 1 1 0 0 Prefix code for DT space access - - - - - - - - - - PCB 1 1 0 0 Prefix code for PC space access - - - - - - - - - - SPB 1 1 0 0 Prefix code for SP space access - - - - - - - - - - NCC 1 1 0 0 Prefix code for flag no-change - - - - - - - - - - CMR 1 1 0 0 Prefix code for common register bank - - - - - - - - - - *1: PCB, ADB, SSB, USB, SPB: 1, DTB, DPR: 2 *2: 7 + 3 × (POP count) + 2 × (POP last register number), 7 when RLST = 0 (no transfer register) *3: 29 + 3 × (PUSH count) - 3 × (PUSH last register number), 8 when RLST = 0 (no transfer register) *4: (POP count) × (c) or (PUSH count) × (c) *5: (POP count) or (PUSH count) Note: See Table B.5-1 and Table B.5-2 for information on (a) and (c) in the table. 516 APPENDIX B Instructions Table B.8-16 21 Bit Operand Instructions Mnemonic # ~ RG B LH AH I S T N Z V C RMW MOVB A,dir:bp 3 5 0 (b) byte (A) ← (dir:bp)b Operation Z * - - - * * - - - MOVB A,addr16:bp 4 5 0 (b) byte (A) ← (addr16:bp)b Z * - - - * * - - - MOVB A,io:bp 3 4 0 (b) byte (A) ← (io:bp)b Z * - - - * * - - - MOVB dir:bp,A 3 7 0 2 × (b) bit (dir:bp)b ← (A) - - - - - * * - - * MOVB addr16:bp,A 4 7 0 2 × (b) bit (addr16:bp)b ← (A) - - - - - * * - - * MOVB io:bp,A 3 6 0 2 × (b) bit (io:bp)b ← (A) - - - - - * * - - * SETB dir:bp 3 7 0 2 × (b) bit (dir:bp)b ← 1 - - - - - - - - - * SETB addr16:bp 4 7 0 2 × (b) bit (addr16:bp)b ← 1 - - - - - - - - - * SETB io:bp 3 7 0 2 × (b) bit (io:bp)b ← 1 - - - - - - - - - * CLRB dir:bp 3 7 0 2 × (b) bit (dir:bp)b ← 0 - - - - - - - - - * CLRB addr16:bp 4 7 0 2 × (b) bit (addr16:bp)b ← 0 - - - - - - - - - * CLRB io:bp 3 7 0 2 × (b) bit (io:bp)b ← 0 - - - - - - - - - * BBC dir:bp,rel 4 *1 0 (b) Branch on (dir:bp) b = 0 - - - - - - * - - - BBC addr16:bp,rel 5 *1 0 (b) Branch on (addr16:bp) b = 0 - - - - - - * - - - BBC io:bp,rel 4 *2 0 (b) Branch on (io:bp) b = 0 - - - - - - * - - - BBS dir:bp,rel 4 *1 0 (b) Branch on (dir:bp) b = 1 - - - - - - * - - - BBS addr16:bp,rel 5 *1 0 (b) Branch on (addr16:bp) b = 1 - - - - - - * - - BBS io:bp,rel 4 *2 0 (b) Branch on (io:bp) b = 1 - - - - - - * - - - SBBS addr16:bp,rel 5 *3 0 2 × (b) Branch on (addr16:bp) b = 1, bit (addr16:bp) b ← 1 - - - - - - * - - * WBTS io:bp 3 *4 0 *5 Waits until (io:bp) b = 1 - - - - - - - - - - WBTC io:bp 3 *4 0 *5 Waits until (io:bp) b = 0 - - - - - - - - - - AH I S T N Z V C RMW *1: 8 when a branch is made; otherwise, 7 *2: 7 when a branch is made; otherwise, 6 *3: 10 when the condition is met; otherwise, 9 *4: Undefined count *5: Until the condition is met Note: See Table B.5-1 and Table B.5-2 for information on (b) in the table. Table B.8-17 6 Accumulator Operation Instructions (Byte, Word) Mnemonic # ~ RG B Operation LH SWAP 1 3 0 0 byte (A)0-7 ↔ (A)8-15 - - - - - - - - - - SWAPW 1 2 0 0 word (AH) ↔ (AL) - * - - - - - - - - EXT 1 1 0 0 Byte sign extension X - - - - * * - - - EXTW 1 2 0 0 Word sign extension - X - - - * * - - - ZEXT 1 1 0 0 Byte zero extension Z - - - - R * - - - ZEXTW 1 1 0 0 Word zero extension - Z - - - R * - - - 517 APPENDIX B Instructions Table B.8-18 10 String Instructions Mnemonic MOVS / MOVSI # ~ RG B 2 *2 *5 *3 LH AH I S T N Z V C RMW byte transfer @AH+ ← @AL+, counter = RW0 Operation - - - - - - - - - - MOVSD 2 *2 *5 *3 byte transfer @AH- ← @AL-, counter = RW0 - - - - - - - - - - SCEQ / SCEQI 2 *1 *8 *4 byte search @AH+ ← AL, counter = RW0 - - - - - * * * * - SCEQD 2 *1 *8 *4 byte search @AH- ← AL, counter = RW0 - - - - - * * * * FILS / FILSI 2 6m+6 *8 *3 byte fill @AH+ ← AL, counter = RW0 - - - - - * * - - - MOVSW / MOVSWI 2 *2 *5 *6 word transfer @AH+ ← @AL+, counter = RW0 - - - - - - - - - - MOVSWD 2 *2 *5 *6 word transfer @AH- ← @AL-, counter = RW0 - - - - - - - - - - SCWEQ / SCWEQI 2 *1 *8 *7 word search @AH+ - AL, counter = RW0 - - - - - * * * * - SCWEQD 2 *1 *8 *7 word search @AH- - AL, counter = RW0 - - - - - * * * * - FILSW / FILSWI 2 6m+6 *8 *6 word fill @AH+ ← AL, counter = RW0 - - - - - * * - - - *1: 5 when RW0 is 0, 4 + 7 × (RW0) when the counter expires, or 7n + 5 when a match occurs *2: 5 when RW0 is 0; otherwise, 4 + 8 × (RW0) *3: (b) × (RW0) + (b) × (RW0) When the source and destination access different areas, calculate the (b) item individually. *4: (b) × n *5: 2 × (b) × (RW0) *6: (c) × (RW0) + (c) × (RW0) When the source and destination access different areas, calculate the (c) item individually. *7: (c) × n *8: (b) × (RW0) Note: m: RW0 value (counter value), n: Loop count See Table B.5-1 and Table B.5-2 for information on (b) and (c) in the table. 518 APPENDIX B Instructions B.9 Instruction Map Each F2MC-16LX instruction code consists of 1 or 2 bytes. Therefore, the instruction map consists of multiple pages. Table B.9-2 to Table B.9-21 summarize the F2MC-16LX instruction map. ■ Structure of Instruction Map Figure B.9-1 Structure of Instruction Map Basic page map Bit operation instructions Character string operation instructions 2-byte instructions : Byte 1 ea instructions × 9 : Byte 2 An instruction such as the NOP instruction that ends in one byte is completed within the basic page. An instruction such as the MOVS instruction that requires two bytes recognizes the existence of byte 2 when it references byte 1, and can check the following one byte by referencing the map for byte 2. Figure B.9-2 shows the correspondence between an actual instruction code and instruction map. 519 APPENDIX B Instructions Figure B.9-2 Correspondence between Actual Instruction Code and Instruction Map Some instructions do not contain byte 2. Instruction code Length varies depending on the instruction. Byte 1 Byte 2 Operand Operand ... [Basic page map] XY +Z [Extended page map]* UV +W *: The extended page map is a generic name of maps for bit operation instructions, character string operation instructions, 2-byte instructions, and ea instructions. Actually, there are multiple extended page maps for each type of instructions. An example of an instruction code is shown in Table B.9-1. Table B.9-1 Example of an Instruction Code Byte 1 (from basic page map) Byte 2 (from extended page map) NOP 00 +0=00 - AND A, #8 30 +4=34 - MOV A, ADB 60 +F=6F 00 +0=00 @RW2+d8, #8, rel 70 +0=70 F0 +2=F2 Instruction 520 +F +E +D +C +B +A +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 A SWAP ADDSP ADB SPB #8 CMP A, #8 A, #8 dir, A A, dir io, A A, io JMP BRA 60 MULU DIVU ea @A instruction 2 A MOVW MOVX RET SP, A A, addr16 MOVW MOVW RETP A, SP io, #16 ea instruction 8 ea instruction 7 MOVX MOVX CALLP ea A, #8 A, dir A, io addr24 instruction 6 A, #8 A0 B0 C0 E0 rel rel LSRW ASRW LSLW A A A XORW ORW ANDW MOVW ea, RWi Bit operation MOV A instruction ea, Ri ORW PUSHW POPW A, #16 AH AH ANDW PUSHW POPW A, #16 A MOVW RWi, ea A PUSHW POPW 2-byte XCHW rlst rlst instruction RWi, ea Character XORW PUSHW POPW XCH operation A A, #16 PS PS string Ri, ea instruction A A ADDSP MULUW NOTW #16 A SWAPW ZEXTW EXTW CMPW MOVL MOVW RETI A A, #16 A, #32 addr16, A BHI BLS BGT BLE rel rel rel rel rel rel CMPL CMPW A A, #32 BGE rel rel rel rel rel NEGW BNT BT BNV BV BP BN BNC/BHS rel BC/BLO BNZ/BNE rel BZ/BEQ BLT #4 F0 MOV MOV CBNE A, CWBNE A, MOVW MOVW INTP MOV RP, #8 ILM, #8 #8, rel #16, rel A, #16 A,addr16 addr24 Ri, ea A D0 rel SUBL SUBW A, #32 NOT XOR 90 ADDW MOVW MOVW INT ea MOVW MOVW MOVW MOV A, MOVW A A, #16 A, dir A, io #vct8 instruction 9 A, RWi RWi, A RWi, #16 @RWi+d8 @RWi+d8, A A A OR OR CCR, #8 80 ea MOV MOV MOV MOV MOVX A, MOV CALL rel instruction 1 A, Ri Ri, A Ri, #8 A, Ri @RWi+d8 A, #4 70 MOV JMP ea A, addr16 addr16 instruction 3 MOV MOV 50 MOVX MOV JMPP ea A, #8 addr16, A addr24 instruction 4 MOV MOV MOV 40 SUBW MOVW MOVW INT MOVEA A, #16 dir, A io, A addr16 RWi, ea UNLINK A A A, #8 A, #8 SUBC SUB ADD 30 AND AND MOV MOV CALL ea CCR, #8 A, #8 dir, #8 io, #8 addr16 instruction 5 CMP A A, dir A, dir ADDC SUB ADD 20 LINK ADDL ADDW #imm8 A, #32 ZEXT DTB @A EXT JCTX PCB A SUBDC ADDDC NEG NCC INT9 A CMR 10 NOP 00 APPENDIX B Instructions Table B.9-2 Basic Page Map 521 522 +F +E +D +C +B +A +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 10 MOVB io:bp, A 20 30 CLRB io:bp 40 50 SETB io:bp 60 70 BBC io;bp, rel 80 90 BBS io:bp, rel A0 B0 MOVB MOVB A, MOVB MOVB CLRB CLRB SETB SETB BBC BBC BBS BBS A, dir:bp addr16:bp dir:bp, A addr16:bp,A dir:bp addr16:bp dir:bp addr16:bp dir:bp, rel addr16:bp,rel dir:bp, rel addr16:bp,rel MOVB A, io:bp 00 WBTS io:bp C0 D0 WBTC io:bp E0 SBBS addr16:bp F0 APPENDIX B Instructions Table B.9-3 Bit Operation Instruction Map (First Byte = 6CH) MOVSI MOVSD PCB, PCB PCB, DTB PCB, ADB PCB, SPB DTB, PCB DTB, DTB DTB, ADB DTB, SPB ADB, PCB ADB, DTB ADB, ADB ADB, SPB SPB, PCB SPB, DTB SPB, ADB SPB, SPB +1 +2 +3 +4 +5 +6 +7 +8 +9 +A +B +C +D +E +F 10 +0 00 MOVSWI 20 MOVSWD 30 40 50 60 70 90 A0 B0 C0 SPB ADB DTB SPB ADB DTB SPB ADB DTB SPB ADB DTB SPB ADB DTB SCEQI SCEQD SCWEQI SCWEQD FILSI PCB PCB PCB PCB PCB 80 D0 FILSI SPB ADB DTB PCB E0 F0 APPENDIX B Instructions Table B.9-4 Character String Operation Instruction Map (First Byte = 6EH) 523 524 LSLW LSLL LSL MOVW MOVW A, R0 A, R0 A, R0 @RL2+d8, A A, @RL2+d8 MOVW MOVW NRML A, @A @AL, AH A, R0 ASRW ASRL ASR MOVW MOVW A, R0 A, R0 A, R0 @RL3+d8, A A, @RL3+d8 LSRW LSRL LSR A, R0 A, R0 A, R0 +D +E +F MOVW MOVW @RL1+d8, A A, @RL1+d8 MOVW MOVW @RL0+d8, A A, @RL0+d8 +C +B +A +9 +8 A MOV MOV MOVX MOV MOV A, PCB A, @A A, @RL3+d8 @RL3+d8, A A, @RL3+d8 +6 ROLC MOV MOV A, @A @AL, AH +5 A MOV MOV MOVX MOV MOV A, DPR DPR, A A, @RL2+d8 @RL2+d8, A A, @RL2+d8 +4 ROLC MOV MOV A, USB USB, A +3 +7 MOV MOV MOVX MOV MOV A, SSB SSB, A A, @RL1+d8 @RL1+d8, A A, @RL1+d8 +2 40 MOV MOV A, ADB ADB, A 30 +1 20 MOV MOV MOVX MOV MOV A, DTB DTB, A A, @RL0+d8 @RL0+d8, A A, @RL0+d8 10 +0 00 50 DIVU MULW MUL 60 A A A 70 80 90 A0 B0 C0 D0 E0 F0 APPENDIX B Instructions Table B.9-5 2-byte Instruction Map (First Byte = 6FH) 50 90 B0 D0 @RW1, @RW1+d16 CMPL CMPL A, ANDL ANDL A, ORL ORL A, XORL XORL A, #16, rel #16, rel A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 @RW2, @RW2+d16 CMPL CMPL A, ANDL ANDL A, ORL ORL A, XORL XORL A, #16, rel #16, rel A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 @RW3, @RW3+d16 CMPL CMPL A, ANDL ANDL A, ORL ORL A, XORL XORL A, #16, rel #16, rel A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 SUBL SUBL A, A, RL2 @RW5+d8 SUBL SUBL A, A, RL3 @RW6+d8 SUBL SUBL A, A, RL3 @RW7+d8 ADDL ADDL A, A, RL2 @RW5+d8 ADDL ADDL A, A, RL3 @RW6+d8 ADDL ADDL A, A, RL3 @RW7+d8 ADDL ADDL A, SUBL SUBL A, A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 ADDL ADDL A, SUBL SUBL A, A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 ADDL ADDL A, SUBL SUBL A, A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 ADDL ADDL A, SUBL SUBL A, A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 ADDL ADDL A, SUBL SUBL A, Use @RW0+RW7 CMPL CMPL A, ANDL ANDL A, ORL ORL A, XORL XORL A, Use @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 prohibited #16, rel A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 prohibited ,#8, rel ADDL ADDL A, SUBL SUBL A, Use @RW1+RW7 CMPL CMPL A, ANDL ANDL A, ORL ORL A, XORL XORL A, Use @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 prohibited #16, rel A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 prohibited ,#8, rel ADDL ADDL A, A,@RW2+ @PC+d16 ADDL ADDL A, SUBL SUBL A, Use A,@RW3+ addr16 A,@RW3+ addr16 prohibited +5 +6 +7 +8 +9 +A +B +C +D +E +F SUBL SUBL A, A,@RW2+ @PC+d16 @RW0, @RW0+d16 CMPL CMPL A, ANDL ANDL A, ORL ORL A, XORL XORL A, #16, rel #16, rel A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 SUBL SUBL A, A, RL2 @RW4+d8 Use prohibited ANDL ANDL A, A,@RW2+ @PC+d16 ANDL ANDL A, A, RL3 @RW7+d8 ANDL ANDL A, A, RL3 @RW6+d8 ANDL ANDL A, A, RL2 @RW5+d8 ANDL ANDL A, A, RL2 @RW4+d8 ORL ORL A, A,@RW2+ @PC+d16 ORL ORL A, A, RL3 @RW7+d8 ORL ORL A, A, RL3 @RW6+d8 ORL ORL A, A, RL2 @RW5+d8 ORL ORL A, A, RL2 @RW4+d8 XORL XORL A, A,@RW2+ @PC+d16 XORL XORL A, A, RL3 @RW7+d8 XORL XORL A, A, RL3 @RW6+d8 XORL XORL A, A, RL2 @RW5+d8 XORL XORL A, A, RL2 @RW4+d8 XORL XORL A, A, RL1 @RW3+d8 addr16, ,#8, rel Use @PC+d16, prohibited ,#8, rel @RW3, @RW3+d16 #8, rel ,#8, rel @RW2, @RW2+d16 #8, rel ,#8, rel @RW1, @RW1+d16 #8, rel ,#8, rel @RW0, @RW0+d16 #8, rel ,#8, rel R7, @RW7+d8, #8, rel #8, rel R6, @RW6+d8, #8, rel #8, rel R5, @RW5+d8, #8, rel #8, rel R4, @RW4+d8, #8, rel #8, rel R3, @RW3+d8, #8, rel #8, rel addr16, CMPL CMPL A, ANDL ANDL A, ORL ORL A, XORL XORL A, Use #16, rel A,@RW3+ addr16 A,@RW3+ addr16 A,@RW3+ addr16 A,@RW3+ addr16 prohibited @PC+d16, CMPL CMPL A, #16, rel A,@RW2+ @PC+d16 RW7, @RW7+d8 CMPL CMPL A, #16, rel #16, rel A, RL3 @RW7+d8 RW6, @RW6+d8 CMPL CMPL A, #16, rel #16, rel A, RL3 @RW6+d8 RW5, @RW5+d8 CMPL CMPL A, #16, rel #16, rel A, RL2 @RW5+d8 RW4, @RW4+d8 CMPL CMPL A, #16, rel #16, rel A, RL2 @RW4+d8 ORL ORL A, A, RL1 @RW3+d8 R2, @RW2+d8, #8, rel #8, rel R1, @RW1+d8, #8, rel #8, rel ADDL ADDL A, A, RL2 @RW4+d8 ANDL ANDL A, A, RL1 @RW3+d8 XORL XORL A, A, RL1 @RW2+d8 XORL XORL A, A, RL0 @RW1+d8 +4 RW3, @RW3+d8 CMPL CMPL A, #16, rel #16, rel A, RL1 @RW3+d8 ORL ORL A, A, RL1 @RW2+d8 ORL ORL A, A, RL0 @RW1+d8 SUBL SUBL A, A, RL1 @RW3+d8 ANDL ANDL A, A, RL1 @RW2+d8 ANDL ANDL A, A, RL0 @RW1+d8 ADDL ADDL A, A, RL1 @RW3+d8 RW2, @RW2+d8 CMPL CMPL A, #16, rel #16, rel A, RL1 @RW2+d8 RW1, @RW1+d8 CMPL CMPL A, #16, rel #16, rel A, RL0 @RW1+d8 +3 CBNE ↓ F0 R0, @RW0+d8, #8, rel #8, rel CBNE ↓ E0 SUBL SUBL A, A, RL1 @RW2+d8 XORL XORL A, A, RL0 @RW0+d8 C0 ADDL ADDL A, A, RL1 @RW2+d8 ORL ORL A, A, RL0 @RW0+d8 A0 +2 ANDL ANDL A, A, RL0 @RW0+d8 80 SUBL SUBL A, A, RL0 @RW1+d8 70 ADDL ADDL A, A, RL0 @RW1+d8 60 RW0, @RW0+d8 CMPL CMPL A, #16, rel #16, rel A, RL0 @RW0+d8 CWBNE ↓ CWBNE ↓ 40 +1 30 +0 20 SUBL SUBL A, A, RL0 @RW0+d8 10 ADDL ADDL A, A, RL0 @RW0+d8 00 APPENDIX B Instructions Table B.9-6 ea Instruction 1 (First Byte = 70H) 525 526 JMPP JMPP CALLP CALLP INCL INCL DECL DECL MOVL MOVL A, MOVL MOVL MOV MOV MOVEA MOVEA A, @RL3 @@RW7+d8 @RL3 @@RW7+d8 RL3 @RW7+d8 RL3 @RW7+d8 A, RL3 @RW7+d8 RL3, A @RW7+d8,A R7, #8 @RW7+d8,#8 A, RW7 @RW7+d8 JMPP JMPP @ CALLP CALLP @ INCL INCL DECL DECL MOVL MOVL A, MOVL MOVL MOV MOV MOVEA MOVEA A, @@RW0 @RW0+d16 @@RW0 @RW0+d16 @RW0 @RW0+d16 @RW0 @RW0+d16 A,@RW0 @RW0+d16 @RW0,A @RW0+d16,A @RW0, #8 @RW0+d16,#8 A,@RW0 @RW0+d16 JMPP JMPP @ CALLP CALLP @ INCL INCL DECL DECL MOVL MOVL A, MOVL MOVL MOV MOV MOVEA MOVEA A, @@RW1 @RW1+d16 @@RW1 @RW1+d16 @RW1 @RW1+d16 @RW1 @RW1+d16 A,@RW1 @RW1+d16 @RW1,A @RW1+d16,A @RW1, #8 @RW1+d16,#8 A,@RW1 @RW1+d16 JMPP JMPP @ CALLP CALLP @ INCL INCL DECL DECL MOVL MOVL A, MOVL MOVL MOV MOV MOVEA MOVEA A, @@RW2 @RW2+d16 @@RW2 @RW2+d16 @RW2 @RW2+d16 @RW2 @RW2+d16 A,@RW2 @RW2+d16 @RW2,A @RW2+d16,A @RW2, #8 @RW2+d16,#8 A,@RW2 @RW2+d16 JMPP JMPP @ CALLP CALLP @ INCL INCL DECL DECL MOVL MOVL A, MOVL MOVL MOV MOV MOVEA MOVEA A, @@RW3 @RW3+d16 @@RW3 @RW3+d16 @RW3 @RW3+d16 @RW3 @RW3+d16 A,@RW3 @RW3+d16 @RW3,A @RW3+d16,A @RW3, #8 @RW3+d16,#8 A,@RW3 @RW3+d16 JMPP JMPP @ CALLP CALLP @ INCL INCL DECL DECL MOVL MOVL A, MOVL MOVL MOV MOV MOVEA MOVEA A, @@RW0+ @RW0+RW7 @@RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 @RW0+,A @RW0+RW7,A @RW0+, #8 @RW0+RW7,#8 A,@RW0+ @RW0+RW7 JMPP JMPP @ CALLP CALLP @ INCL INCL DECL DECL MOVL MOVL A, MOVL MOVL MOV MOV MOVEA MOVEA A, @@RW1+ @RW1+RW7 @@RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 @RW1+,A @RW1+RW7,A @RW1+, #8 @RW1+RW7,#8 A,@RW1+ @RW1+RW7 JMPP JMPP CALLP CALLP INCL INCL DECL DECL MOVL MOVL A, MOVL MOVL MOV MOV MOVEA MOVEA A, @@RW2+ @@PC+d16 @@RW2+ @@PC+d16 @RW2+ @PC+d16 @RW2+ @PC+d16 A,@RW2+ @PC+d16 @RW2+,A @PC+d16, A @RW2+, #8 @PC+d16, #8 A,@RW2+ @PC+d16 JMPP JMPP CALLP CALLP INCL INCL DECL DECL MOVL MOVL A, MOVL MOVL MOV MOV MOVEA MOVEA A, @@RW3+ @addr16 @@RW3+ @addr16 @RW3+ addr16 @RW3+ addr16 A,@RW3+ addr16 @RW3+,A addr16, A @RW3+, #8 addr16, #8 A,@RW3+ addr16 +8 +9 +A +B +C +D +E +F F0 +7 E0 JMPP JMPP CALLP CALLP INCL INCL DECL DECL MOVL MOVL A, MOVL MOVL MOV MOV MOVEA MOVEA A, @RL3 @@RW6+d8 @RL3 @@RW6+d8 RL3 @RW6+d8 RL3 @RW6+d8 A, RL3 @RW6+d8 RL3, A @RW6+d8,A R6, #8 @RW6+d8,#8 A, RW6 @RW6+d8 D0 +6 C0 JMPP JMPP CALLP CALLP INCL INCL DECL DECL MOVL MOVL A, MOVL MOVL MOV MOV MOVEA MOVEA A, @RL2 @@RW5+d8 @RL2 @@RW5+d8 RL2 @RW5+d8 RL2 @RW5+d8 A, RL2 @RW5+d8 RL2, A @RW5+d8,A R5, #8 @RW5+d8,#8 A, RW5 @RW5+d8 B0 +5 A0 JMPP JMPP CALLP CALLP INCL INCL DECL DECL MOVL MOVL A, MOVL MOVL MOV MOV MOVEA MOVEA A, @RL2 @@RW4+d8 @RL2 @@RW4+d8 RL2 @RW4+d8 RL2 @RW4+d8 A, RL2 @RW4+d8 RL2, A @RW4+d8,A R4, #8 @RW4+d8,#8 A, RW4 @RW4+d8 90 +4 80 JMPP JMPP CALLP CALLP INCL INCL DECL DECL MOVL MOVL A, MOVL MOVL MOV MOV MOVEA MOVEA A, @RL1 @@RW3+d8 @RL1 @@RW3+d8 RL1 @RW3+d8 RL1 @RW3+d8 A, RL1 @RW3+d8 RL1, A @RW3+d8,A R3, #8 @RW3+d8,#8 A, RW3 @RW3+d8 70 +3 60 JMPP JMPP CALLP CALLP INCL INCL DECL DECL MOVL MOVL A, MOVL MOVL MOV MOV MOVEA MOVEA A, @RL1 @@RW2+d8 @RL1 @@RW2+d8 RL1 @RW2+d8 RL1 @RW2+d8 A, RL1 @RW2+d8 RL1, A @RW2+d8,A R2, #8 @RW2+d8,#8 A, RW2 @RW2+d8 50 +2 40 JMPP JMPP CALLP CALLP INCL INCL DECL DECL MOVL MOVL A, MOVL MOVL MOV MOV MOVEA MOVEA A, @RL0 @@RW1+d8 @RL0 @@RW1+d8 RL0 @RW1+d8 RL0 @RW1+d8 A, RL0 @RW1+d8 RL0, A @RW1+d8,A R1, #8 @RW1+d8,#8 A, RW1 @RW1+d8 30 +1 20 JMPP JMPP CALLP CALLP INCL INCL DECL DECL MOVL MOVL A, MOVL MOVL MOV MOV MOVEA MOVEA A, @RL0 @@RW0+d8 @RL0 @@RW0+d8 RL0 @RW0+d8 RL0 @RW0+d8 A, RL0 @RW0+d8 RL0, A @RW0+d8,A R0, #8 @RW0+d8,#8 A, RW0 @RW0+d8 10 +0 00 APPENDIX B Instructions Table B.9-7 ea Instruction 2 (First Byte = 71H) D0 E0 F0 ROLC ROLC RORC RORC INC INC DEC DEC MOV MOV A, MOV MOV MOVX MOVX A, XCH XCH A, @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 ROLC ROLC RORC RORC INC INC DEC DEC MOV MOV A, MOV MOV MOVX MOVX A, XCH XCH A, @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 ROLC ROLC RORC RORC INC INC DEC DEC MOV MOV A, MOV MOV MOVX MOVX A, XCH XCH A, @RW2+ @PC+d16 @RW2+ @PC+d16 @RW2+ @PC+d16 @RW2+ @PC+d16 A,@RW2+ @PC+d16 @RW2+, A @PC+d16, A A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 ROLC ROLC RORC RORC INC INC DEC DEC MOV MOV A, MOV MOV MOVX MOVX A, XCH XCH A, @RW3+ addr16 @RW3+ addr16 @RW3+ addr16 @RW3+ addr16 A,@RW3+ addr16 @RW3+, A addr16, A A,@RW3+ addr16 A,@RW3+ addr16 +D +E +F DEC MOV MOV A, MOV MOV MOVX MOVX A, XCH XCH A, R7 @RW7+d8 A, R7 @RW7+d8 R7, A @RW7+d8,A A, R7 @RW7+d8 A, R7 @RW7+d8 DEC MOV MOV A, MOV MOV MOVX MOVX A, XCH XCH A, R6 @RW6+d8 A, R6 @RW6+d8 R6, A @RW6+d8,A A, R6 @RW6+d8 A, R6 @RW6+d8 DEC MOV MOV A, MOV MOV MOVX MOVX A, XCH XCH A, R5 @RW5+d8 A, R5 @RW5+d8 R5, A @RW5+d8,A A, R5 @RW5+d8 A, R5 @RW5+d8 DEC MOV MOV A, MOV MOV MOVX MOVX A, XCH XCH A, R4 @RW4+d8 A, R4 @RW4+d8 R4, A @RW4+d8,A A, R4 @RW4+d8 A, R4 @RW4+d8 DEC MOV MOV A, MOV MOV MOVX MOVX A, XCH XCH A, R3 @RW3+d8 A, R3 @RW3+d8 R3, A @RW3+d8,A A, R3 @RW3+d8 A, R3 @RW3+d8 DEC MOV MOV A, MOV MOV MOVX MOVX A, XCH XCH A, R2 @RW2+d8 A, R2 @RW2+d8 R2, A @RW2+d8,A A, R2 @RW2+d8 A, R2 @RW2+d8 DEC MOV MOV A, MOV MOV MOVX MOVX A, XCH XCH A, R1 @RW1+d8 A, R1 @RW1+d8 R1, A @RW1+d8,A A, R1 @RW1+d8 A, R1 @RW1+d8 +C INC DEC R7 @RW7+d8 C0 ROLC ROLC RORC RORC INC INC DEC DEC MOV MOV A, MOV MOV MOVX MOVX A, XCH XCH A, @RW3 @RW3+d16 @RW3 @RW3+d16 @RW3 @RW3+d16 @RW3 @RW3+d16 A,@RW3 @RW3+d16 @RW3, A @RW3+d16,A A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 ROLC RORC RORC INC R7 @RW7+d8 R7 @RW7+d8 ROLC INC DEC R6 @RW6+d8 B0 +B ROLC RORC RORC INC R6 @RW6+d8 R6 @RW6+d8 ROLC INC DEC R5 @RW5+d8 A0 ROLC ROLC RORC RORC INC INC DEC DEC MOV MOV A, MOV MOV MOVX MOVX A, XCH XCH A, @RW2 @RW2+d16 @RW2 @RW2+d16 @RW2 @RW2+d16 @RW2 @RW2+d16 A,@RW2 @RW2+d16 @RW2, A @RW2+d16,A A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 ROLC RORC RORC INC R5 @RW5+d8 R5 @RW5+d8 ROLC INC DEC R4 @RW4+d8 90 +A ROLC RORC RORC INC R4 @RW4+d8 R4 @RW4+d8 ROLC INC DEC R3 @RW3+d8 INC DEC R2 @RW2+d8 INC DEC R1 @RW1+d8 80 DEC MOV MOV A, MOV MOV MOVX MOVX A, XCH XCH A, R0 @RW0+d8 A, R0 @RW0+d8 R0, A @RW0+d8,A A, R0 @RW0+d8 A, R0 @RW0+d8 70 ROLC ROLC RORC RORC INC INC DEC DEC MOV MOV A, MOV MOV MOVX MOVX A, XCH XCH A, @RW1 @RW1+d16 @RW1 @RW1+d16 @RW1 @RW1+d16 @RW1 @RW1+d16 A,@RW1 @RW1+d16 @RW1, A @RW1+d16,A A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 ROLC RORC RORC INC R3 @RW3+d8 R3 @RW3+d8 ROLC 60 INC DEC R0 @RW0+d8 50 +9 ROLC RORC RORC INC R2 @RW2+d8 R2 @RW2+d8 ROLC 40 ROLC ROLC RORC RORC INC INC DEC DEC MOV MOV A, MOV MOV MOVX MOVX A, XCH XCH A, @RW0 @RW0+d16 @RW0 @RW0+d16 @RW0 @RW0+d16 @RW0 @RW0+d16 A,@RW0 @RW0+d16 @RW0, A @RW0+d16,A A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 ROLC RORC RORC INC R1 @RW1+d8 R1 @RW1+d8 ROLC 30 ROLC RORC RORC INC R0 @RW0+d8 R0 @RW0+d8 20 ROLC 10 +8 +7 +6 +5 +4 +3 +2 +1 +0 00 APPENDIX B Instructions Table B.9-8 ea Instruction 3 (First Byte = 72H) 527 528 JMP JMP @ CALL CALL @ INCW INCW @ DECW DECW MOVW MOVW A, MOVW MOVW MOVW MOVW XCHW XCHW A, @@RW3 @RW3+d16 @@RW3 @RW3+d16 @RW3 @RW3+d16 @RW3 @RW3+d16 A,@RW3 @RW3+d16 @RW3, A @RW3+d16,A @RW3, #16 @RW3+d16,#16 A,@RW3 @RW3+d16 +B JMP JMP CALL CALL INCW INCW DECW DECW MOVW MOVW A, MOVW MOVW MOVW MOVW XCHW XCHW A, @@RW3+ @addr16 @@RW3+ @addr16 @RW3+ addr16 @RW3+ addr16 A,@RW3+ addr16 @RW3+, A addr16, A @RW3+, #16 addr16, #16 A,@RW3+ addr16 INCW @ +F INCW JMP JMP CALL CALL INCW INCW DECW DECW MOVW MOVW A, MOVW MOVW MOVW MOVW XCHW XCHW A, @@RW2+ @@PC+d16 @@RW2+ @@PC+d16 @RW2+ @@PC+d16 @RW2+ @PC+d16 A,@RW2+ @PC+d16 @RW2+, A @PC+d16, A @RW2+, #16 @PC+d16, #16 A,@RW2+ @PC+d16 CALL @ +E CALL DECW DECW MOVW MOVW A, MOVW MOVW MOVW MOVW XCHW XCHW A, @RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A @RW1+, #16 @RW1+RW7,#16 A,@RW1+ @RW1+RW7 XCHW XCHW A, A, RW7 @RW7+d8 XCHW XCHW A, A, RW6 @RW6+d8 XCHW XCHW A, A, RW5 @RW5+d8 +D @@RW1+ @RW1+RW7 @@RW1+ @RW1+RW7 @RW1+ @RW1+RW7 INCW @ MOVW MOVW RW7, #16 @RW7+d8,#16 MOVW MOVW RW6, #16 @RW6+d8,#16 MOVW MOVW RW5, #16 @RW5+d8,#16 XCHW XCHW A, A, RW4 @RW4+d8 DECW DECW MOVW MOVW A, MOVW MOVW MOVW MOVW XCHW XCHW A, @RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A @RW0+, #16 @RW0+RW7,#16 A,@RW0+ @RW0+RW7 INCW INCW INCW DECW DECW MOVW MOVW A, MOVW MOVW RW7 @RW7+d8 RW7 @RW7+d8 A, RW7 @RW7+d8 RW7, A @RW7+d8,A INCW INCW DECW DECW MOVW MOVW A, MOVW MOVW RW6 @RW6+d8 RW6 @RW6+d8 A, RW6 @RW6+d8 RW6, A @RW6+d8,A INCW INCW DECW DECW MOVW MOVW A, MOVW MOVW RW5 @RW5+d8 RW5 @RW5+d8 A, RW5 @RW5+d8 RW5, A @RW5+d8,A MOVW MOVW RW4, #16 @RW4+d8,#16 +C @@RW0+ @RW0+RW7 @@RW0+ @RW0+RW7 @RW0+ @RW0+RW7 JMP @ JMP JMP @ CALL CALL @ INCW INCW @ DECW DECW MOVW MOVW A, MOVW MOVW MOVW MOVW XCHW XCHW A, @@RW2 @RW2+d16 @@RW2 @RW2+d16 @RW2 @RW2+d16 @RW2 @RW2+d16 A,@RW2 @RW2+d16 @RW2, A @RW2+d16,A @RW2, #16 @RW2+d16,#16 A,@RW2 @RW2+d16 +A JMP JMP JMP @ CALL CALL @ INCW INCW @ DECW DECW MOVW MOVW A, MOVW MOVW MOVW MOVW XCHW XCHW A, @@RW1 @RW1+d16 @@RW1 @RW1+d16 @RW1 @RW1+d16 @RW1 @RW1+d16 A,@RW1 @RW1+d16 @RW1, A @RW1+d16,A @RW1, #16 @RW1+d16,#16 A,@RW1 @RW1+d16 +9 CALL @ JMP JMP @ CALL CALL @ INCW INCW @ DECW DECW MOVW MOVW A, MOVW MOVW MOVW MOVW XCHW XCHW A, @@RW0 @RW0+d16 @@RW0 @RW0+d16 @RW0 @RW0+d16 @RW0 @RW0+d16 A,@RW0 @RW0+d16 @RW0,A @RW0+d16,A @RW0, #16 @RW0+d16,#16 A,@RW0 @RW0+d16 +8 CALL CALL CALL RW7 @@RW7+d8 JMP JMP @RW7 @@RW7+d8 +7 JMP @ CALL CALL RW6 @@RW6+d8 JMP JMP @RW6 @@RW6+d8 +6 JMP CALL CALL RW5 @@RW5+d8 JMP JMP @RW5 @@RW5+d8 +5 INCW INCW DECW DECW MOVW MOVW A, MOVW MOVW RW4 @RW4+d8 RW4 @RW4+d8 A, RW4 @RW4+d8 RW4, A @RW4+d8,A XCHW XCHW A, A, RW3 @RW3+d8 XCHW XCHW A, A, RW2 @RW2+d8 XCHW XCHW A, A, RW1 @RW1+d8 CALL CALL RW4 @@RW4+d8 MOVW MOVW RW3, #16 @RW3+d8,#16 MOVW MOVW RW2, #16 @RW2+d8,#16 MOVW MOVW RW1, #16 @RW1+d8,#16 JMP JMP @RW4 @@RW4+d8 INCW INCW DECW DECW MOVW MOVW A, MOVW MOVW RW3 @RW3+d8 RW3 @RW3+d8 A, RW3 @RW3+d8 RW3, A @RW3+d8,A INCW INCW DECW DECW MOVW MOVW A, MOVW MOVW RW2 @RW2+d8 RW2 @RW2+d8 A, RW2 @RW2+d8 RW2, A @RW2+d8,A INCW INCW DECW DECW MOVW MOVW A, MOVW MOVW RW1 @RW1+d8 RW1 @RW1+d8 A, RW1 @RW1+d8 RW1, A @RW1+d8,A +4 F0 XCHW XCHW A, A, RW0 @RW0+d8 E0 CALL CALL RW3 @@RW3+d8 D0 MOVW MOVW RW0, #16 @RW0+d8,#16 C0 JMP JMP @RW3 @@RW3+d8 B0 +3 A0 CALL CALL RW2 @@RW2+d8 90 JMP JMP @RW2 @@RW2+d8 80 +2 70 CALL CALL RW1 @@RW1+d8 60 JMP JMP @RW1 @@RW1+d8 50 INCW INCW DECW DECW MOVW MOVW A, MOVW MOVW RW0 @RW0+d8 RW0 @RW0+d8 A, RW0 @RW0+d8 RW0, A @RW0+d8,A 40 +1 30 CALL CALL RW0 @@RW0+d8 20 JMP JMP @RW0 @@RW0+d8 10 +0 00 APPENDIX B Instructions Table B.9-9 ea Instruction 4 (First Byte = 73H) ADD A, SUB SUB SUB ADDC A, ADDC A, ADDC ADDC A, A, CMP CMP CMP CMP A, A, A, AND AND AND AND AND AND A, A, A, OR OR A, XOR XOR A, DBNZ DBNZ @ A,@RW2+ @PC+d16, A,@RW2+ @PC+d16 @RW2+, r PC+d16, r +F A,@RW3+ ADD ADD SUB SUB ADDC ADDC CMP CMP AND AND OR OR XOR XOR DBNZ DBNZ A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 @RW3+, r addr16, r +E A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 ADD SUB CMP XOR XOR A, DBNZ DBNZ @R A,@RW1+ @RW1+RW7 @RW1+, r W1+RW7, r A, CMP OR OR A, A,@RW1+ @RW1+RW7 ADD ADD ADDC A, +D A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 ADDC XOR XOR A, DBNZ DBNZ @R A,@RW0+ @RW0+RW7 @RW0+, r W0+RW7, r A, OR OR A, A,@RW0+ @RW0+RW7 SUB +C A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 SUB XOR XOR A, DBNZ DBNZ @R A,@RW3 @RW3+d16 @RW3, r W3+d16, r ADD ADD A, SUB SUB A, ADDC ADDC A, CMP CMP A, AND AND A, OR OR A, A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 +B A, XOR XOR A, DBNZ DBNZ @R A,@RW2 @RW2+d16 @RW2, r W2+d16, r ADD ADD A, SUB SUB A, ADDC ADDC A, CMP CMP A, AND AND A, OR OR A, A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 +A ADD XOR XOR A, DBNZ DBNZ @R A,@RW1 @RW1+d16 @RW1, r W1+d16, r ADD ADD A, SUB SUB A, ADDC ADDC A, CMP CMP A, AND AND A, OR OR A, A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 +9 ADD XOR XOR A, DBNZ DBNZ @R A,@RW0 @RW0+d16 @RW0, r W0+d16, r ADD ADD A, SUB SUB A, ADDC ADDC A, CMP CMP A, AND AND A, OR OR A, A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 ADD A, SUB SUB A, ADDC ADDC A, CMP CMP A, AND AND A, OR OR A, XOR XOR A, DBNZ DBNZ @ A, R7 @RW7+d8 A, R7 @RW7+d8 A, R7 @RW7+d8 A, R7 @RW7+d8 A, R7 @RW7+d8 A, R7 @RW7+d8 A, R7 @RW7+d8 R7, r RW7+d8, r ADD F0 ADD A, SUB SUB A, ADDC ADDC A, CMP CMP A, AND AND A, OR OR A, XOR XOR A, DBNZ DBNZ @ A, R6 @RW6+d8 A, R6 @RW6+d8 A, R6 @RW6+d8 A, R6 @RW6+d8 A, R6 @RW6+d8 A, R6 @RW6+d8 A, R6 @RW6+d8 R6, r RW6+d8, r E0 ADD D0 ADD A, SUB SUB A, ADDC ADDC A, CMP CMP A, AND AND A, OR OR A, XOR XOR A, DBNZ DBNZ @ A, R5 @RW5+d8 A, R5 @RW5+d8 A, R5 @RW5+d8 A, R5 @RW5+d8 A, R5 @RW5+d8 A, R5 @RW5+d8 A, R5 @RW5+d8 R5, r RW5+d8, r C0 ADD B0 ADD A, SUB SUB A, ADDC ADDC A, CMP CMP A, AND AND A, OR OR A, XOR XOR A, DBNZ DBNZ @ A, R4 @RW4+d8 A, R4 @RW4+d8 A, R4 @RW4+d8 A, R4 @RW4+d8 A, R4 @RW4+d8 A, R4 @RW4+d8 A, R4 @RW4+d8 R4, r RW4+d8, r A0 ADD 90 ADD A, SUB SUB A, ADDC ADDC A, CMP CMP A, AND AND A, OR OR A, XOR XOR A, DBNZ DBNZ @ A, R3 @RW3+d8 A, R3 @RW3+d8 A, R3 @RW3+d8 A, R3 @RW3+d8 A, R3 @RW3+d8 A, R3 @RW3+d8 A, R3 @RW3+d8 R3, r RW3+d8, r 80 ADD 70 ADD A, SUB SUB A, ADDC ADDC A, CMP CMP A, AND AND A, OR OR A, XOR XOR A, DBNZ DBNZ @ A, R2 @RW2+d8 A, R2 @RW2+d8 A, R2 @RW2+d8 A, R2 @RW2+d8 A, R2 @RW2+d8 A, R2 @RW2+d8 A, R2 @RW2+d8 R2, r RW2+d8, r 60 ADD 50 ADD A, SUB SUB A, ADDC ADDC A, CMP CMP A, AND AND A, OR OR A, XOR XOR A, DBNZ DBNZ @ A, R1 @RW1+d8 A, R1 @RW1+d8 A, R1 @RW1+d8 A, R1 @RW1+d8 A, R1 @RW1+d8 A, R1 @RW1+d8 A, R1 @RW1+d8 R1, r RW1+d8, r 40 ADD 30 ADD A, SUB SUB A, ADDC ADDC A, CMP CMP A, AND AND A, OR OR A, XOR XOR A, DBNZ DBNZ @ A, R0 @RW0+d8 A, R0 @RW0+d8 A, R0 @RW0+d8 A, R0 @RW0+d8 A, R0 @RW0+d8 A, R0 @RW0+d8 A, R0 @RW0+d8 R0, r RW0+d8, r 20 ADD 10 +8 +7 +6 +5 +4 +3 +2 +1 +0 00 APPENDIX B Instructions Table B.9-10 ea Instruction 5 (First Byte = 74H) 529 530 NOT NOT R2 @RW2+d8 SUB SUB SUB SUB ADD SUB SUB @RW1+RW7,A @RW1+, A @RW1+RW7,A ADD @R @RW0+RW7,A @RW0+, A @RW0+RW7,A ADD @R +F ADD ADD @RW3+, A addr16, A SUB SUB @RW3+, A addr16, A +E @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A ADD +D @RW1+, A ADD +C @RW0+, A ADD NOT NOT @RW1+ @RW1+RW7 NOT NOT @RW0+ @RW0+RW7 SUBC SUBC A, NEG NEG A, AND AND A,@RW3+ addr16 @RW3+ addr16 @RW3+, A addr16, A OR OR @RW3+, A addr16, A XOR XOR @RW3+, A addr16, A NOT NOT @RW3+ addr16 SUBC SUBC A, NEG NEG A, AND AND OR OR XOR XOR NOT NOT A,@RW2+ @PC+d16 @RW2+ @PC+d16 @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A @RW2+ @PC+d16 SUBC SUBC A, NEG NEG A, AND AND OR OR XOR XOR A,@RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A SUBC SUBC A, NEG NEG A, AND AND OR OR XOR XOR A,@RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A NOT NOT @RW3 @RW3+d16 ADD ADD @R SUB SUB SUBC SUBC A, NEG NEG A, AND AND OR OR XOR XOR @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A A, @RW3 @RW3+d16 @RW3 @RW3+d16 @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A +B XOR NOT NOT R7, A @RW7+d8, A R7 @RW7+d8 XOR NOT NOT R6, A @RW6+d8, A R6 @RW6+d8 XOR NOT NOT R5, A @RW5+d8, A R5 @RW5+d8 XOR NOT NOT R4, A @RW4+d8, A R4 @RW4+d8 XOR NOT NOT R3, A @RW3+d8, A R3 @RW3+d8 XOR R2, A @RW2+d8,A XOR NOT NOT R1, A @RW1+d8, A R1 @RW1+d8 NOT NOT @RW2 @RW2+d16 XOR F0 ADD ADD @R SUB SUB SUBC SUBC A, NEG NEG A, AND AND OR OR XOR XOR @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A A, @RW2 @RW2+d16 @RW2 @RW2+d16 @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A NEG A, AND AND OR OR R7 @RW7+d8 R7, A @RW7+d8, A R7, A @RW7+d8, A XOR XOR XOR XOR XOR XOR E0 XOR NOT NOT R0, A @RW0+d8, A R0 @RW0+d8 D0 +A ADD SUB SUB SUBC SUBC A, NEG R7, A @RW7+d8, A R7, A @RW7+d8, A A, R7 @RW7+d8 ADD NEG A, AND AND OR OR R6 @RW6+d8 R6, A @RW6+d8, A R6, A @RW6+d8, A NEG A, AND AND OR OR R5 @RW5+d8 R5, A @RW5+d8, A R5, A @RW5+d8, A NEG A, AND AND OR OR R4 @RW4+d8 R4, A @RW4+d8, A R4, A @RW4+d8, A NEG A, AND AND OR OR R3 @RW3+d8 R3, A @RW3+d8, A R3, A @RW3+d8, A NEG A, AND AND OR OR R2 @RW2+d8 R2, A @RW2+d8,A R2, A @RW2+d8,A NEG A, AND AND OR OR R1 @RW1+d8 R1, A @RW1+d8, A R1, A @RW1+d8, A XOR C0 NOT NOT @RW1 @RW1+d16 ADD SUB SUB SUBC SUBC A, NEG R6, A @RW6+d8, A R6, A @RW6+d8, A A, R6 @RW6+d8 ADD B0 ADD ADD @R SUB SUB SUBC SUBC A, NEG NEG A, AND AND OR OR XOR XOR @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A A, @RW1 @RW1+d16 @RW1 @RW1+d16 @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A ADD SUB SUB SUBC SUBC A, NEG R5, A @RW5+d8, A R5, A @RW5+d8, A A, R5 @RW5+d8 ADD A0 +9 ADD SUB SUB SUBC SUBC A, NEG R4, A @RW4+d8, A R4, A @RW4+d8, A A, R4 @RW4+d8 ADD 90 NOT NOT @RW0 @RW0+d16 ADD SUB SUB SUBC SUBC A, NEG R3, A @RW3+d8, A R3, A @RW3+d8, A A, R3 @RW3+d8 ADD 80 NEG A, AND AND OR OR R0 @RW0+d8 R0, A @RW0+d8, A R0, A @RW0+d8, A 70 ADD ADD SUB SUB SUBC SUBC A, NEG NEG A, AND AND OR OR XOR XOR @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A A, @RW0 @RW0+d16 @RW0 @RW0+d16 @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A ADD SUB SUB SUBC SUBC A, NEG R2, A @RW2+d8,A R2, A @RW2+d8,A A, R2 @RW2+d8 60 ADD 50 ADD SUB SUB SUBC SUBC A, NEG R1, A @RW1+d8, A R1, A @RW1+d8, A A, R1 @RW1+d8 40 ADD 30 ADD SUB SUB SUBC SUBC A, NEG R0, A @RW0+d8, A R0, A @RW0+d8, A A, R0 @RW0+d8 20 ADD 10 +8 +7 +6 +5 +4 +3 +2 +1 +0 00 APPENDIX B Instructions Table B.9-11 ea Instruction 6 (First Byte = 75H) ADDW A, SUBW ADDW ADDCW CMPW ADDCW A, CMPW ADDCW A, ANDW CMPW A, ANDW CMPW A, ORW ORW ANDW A, ORW ANDW A, ANDW A, ORW ORW ORW A, A, A, XORW XORW A, DWBNZ DWBNZ +F A,@RW3+ ADDW ADDW A, SUBW SUBW A, ADDCW ADDCW A, CMPW CMPW A, ANDW ANDW A, ORW ORW A, XORW XORW A, DWBNZ DWBNZ addr 16 A,@RW3+ addr 16 A,@RW3+ addr 16 A,@RW3+ addr 16 A,@RW3+ addr 16 A,@RW3+ addr16 A,@RW3+ addr 16 @RW3+, r addr16, r +E A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16, A,@RW2+ @PC+d16 @RW2+, r @PC+d16,r SUBW A, ADDCW SUBW A, ANDW XORW XORW A, DWBNZ DWBNZ A,@RW1+ @RW1+RW7 @RW1+, r @RW1+RW7,r SUBW ADDW A, ADDW CMPW A, +D A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 CMPW XORW XORW A, DWBNZ DWBNZ A,@RW0+ @RW0+RW7 @RW0+, r @RW0+RW7,r ADDCW A, +C A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 ADDCW XORW XORW A, DWBNZ DWBNZ A,@RW3 @RW3+d16 @RW3, r @RW3+d16,r ADDW ADDW A, SUBW SUBW A, ADDCW ADDCW A, CMPW CMPW A, ANDW ANDW A, ORW ORW A, A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 +B SUBW A, XORW XORW A, DWBNZ DWBNZ A,@RW2 @RW2+d16 @RW2, r @RW2+d16,r ADDW ADDW A, SUBW SUBW A, ADDCW ADDCW A, CMPW CMPW A, ANDW ANDW A, ORW ORW A, A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 +A SUBW XORW XORW A, DWBNZ DWBNZ A,@RW1 @RW1+d16 @RW1, r @RW1+d16,r ADDW ADDW A, SUBW SUBW A, ADDCW ADDCW A, CMPW CMPW A, ANDW ANDW A, ORW ORW A, A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 +9 ADDW A, XORW XORW A, DWBNZ DWBNZ A,@RW0 @RW0+d16 @RW0, r @RW0+d16,r ADDW ADDW A, SUBW SUBW A, ADDCW ADDCW A, CMPW CMPW A, ANDW ANDW A, ORW ORW A, A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 +8 ADDW ADDW ADDW A, SUBW SUBW A, ADDCW ADDCW A, CMPW CMPW A, ANDW ANDW A, ORW ORW A, XORW XORW A, DWBNZ DWBNZ A, RW7 @RW7+d8 A, RW7 @RW7+d8 A, RW7 @RW7+d8 A, RW7 @RW7+d8 A, RW7 @RW7+d8 A, RW7 @RW7+d8 A, RW7 @RW7+d8 RW7, r @RW7+d8,r F0 +7 E0 ADDW ADDW A, SUBW SUBW A, ADDCW ADDCW A, CMPW CMPW A, ANDW ANDW A, ORW ORW A, XORW XORW A, DWBNZ DWBNZ A, RW6 @RW6+d8 A, RW6 @RW6+d8 A, RW6 @RW6+d8 A, RW6 @RW6+d8 A, RW6 @RW6+d8 A, RW6 @RW6+d8 A, RW6 @RW6+d8 RW6, r @RW6+d8,r D0 +6 C0 ADDW ADDW A, SUBW SUBW A, ADDCW ADDCW A, CMPW CMPW A, ANDW ANDW A, ORW ORW A, XORW XORW A, DWBNZ DWBNZ A, RW5 @RW5+d8 A, RW5 @RW5+d8 A, RW5 @RW5+d8 A, RW5 @RW5+d8 A, RW5 @RW5+d8 A, RW5 @RW5+d8 A, RW5 @RW5+d8 RW5, r @RW5+d8,r B0 +5 A0 ADDW ADDW A, SUBW SUBW A, ADDCW ADDCW A, CMPW CMPW A, ANDW ANDW A, ORW ORW A, XORW XORW A, DWBNZ DWBNZ A, RW4 @RW4+d8 A, RW4 @RW4+d8 A, RW4 @RW4+d8 A, RW4 @RW4+d8 A, RW4 @RW4+d8 A, RW4 @RW4+d8 A, RW4 @RW4+d8 RW4, r @RW4+d8,r 90 +4 80 ADDW ADDW A, SUBW SUBW A, ADDCW ADDCW A, CMPW CMPW A, ANDW ANDW A, ORW ORW A, XORW XORW A, DWBNZ DWBNZ A, RW3 @RW3+d8 A, RW3 @RW3+d8 A, RW3 @RW3+d8 A, RW3 @RW3+d8 A, RW3 @RW3+d8 A, RW3 @RW3+d8 A, RW3 @RW3+d8 RW3, r @RW3+d8,r 70 +3 60 ADDW ADDW A, SUBW SUBW A, ADDCW ADDCW A, CMPW CMPW A, ANDW ANDW A, ORW ORW A, XORW XORW A, DWBNZ DWBNZ A, RW2 @RW2+d8 A, RW2 @RW2+d8 A, RW2 @RW2+d8 A, RW2 @RW2+d8 A, RW2 @RW2+d8 A, RW2 @RW2+d8 A, RW2 @RW2+d8 RW2, r @RW2+d8,r 50 +2 40 ADDW ADDW A, SUBW SUBW A, ADDCW ADDCW A, CMPW CMPW A, ANDW ANDW A, ORW ORW A, XORW XORW A, DWBNZ DWBNZ A, RW1 @RW1+d8 A, RW1 @RW1+d8 A, RW1 @RW1+d8 A, RW1 @RW1+d8 A, RW1 @RW1+d8 A, RW1 @RW1+d8 A, RW1 @RW1+d8 RW1, r @RW1+d8,r 30 +1 20 ADDW ADDW A, SUBW SUBW A, ADDCW ADDCW A, CMPW CMPW A, ANDW ANDW A, ORW ORW A, XORW XORW A, DWBNZ DWBNZ A, RW0 @RW0+d8 A, RW0 @RW0+d8 A, RW0 @RW0+d8 A, RW0 @RW0+d8 A, RW0 @RW0+d8 A, RW0 @RW0+d8 A, RW0 @RW0+d8 RW0, r @RW0+d8,r 10 +0 00 APPENDIX B Instructions Table B.9-12 ea Instruction 7 (First Byte = 76H) 531 532 NEGW NEGW ANDW ANDW ORW ORW XORW XORW NOTW NOTW @RW3 @RW3+d16 @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A @RW3 @RW3+d16 SUBW SUBW @RW3+, A addr16, A ADDW ADDW @RW3+, A addr16, A +F SUBCW SUBCW A, NEGW NEGW ANDW ANDW A,@RW3+ addr16 @RW3+ addr16 @RW3+, A addr16, A ORW ORW @RW3+, A addr16, A XORW XORW @RW3+, A addr16, A NOTW NOTW @RW3+ addr16 SUBCW SUBCW A, NEGW NEGW ANDW ANDW ORW ORW XORW XORW NOTW NOTW A,@RW2+ @PC+d16 @RW2+ @PC+d16 @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A @RW2+ @PC+d16 SUBW SUBW @RW2+, A @PC+d16,A ADDW ADDW @RW2+, A @PC+d16,A +E SUBCW A, ADDW ADDW SUBW SUBW SUBCW SUBCW A, NEGW NEGW ANDW ANDW ORW ORW XORW XORW NOTW NOTW @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A A,@RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A @RW1+ @RW1+RW7 SUBCW +D SUBW SUBCW A, ADDW ADDW SUBW SUBW SUBCW SUBCW A, NEGW NEGW ANDW ANDW ORW ORW XORW XORW NOTW NOTW @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A A,@RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A @RW0+ @RW0+RW7 SUBW SUBCW +C ADDW ADDW SUBW SUBCW A, +B @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A A, @RW3 @RW3+d16 SUBW SUBCW NEGW NEGW ANDW ANDW ORW ORW XORW XORW NOTW NOTW @RW2 @RW2+d16 @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A @RW2 @RW2+d16 ADDW ADDW SUBW +A @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A A, @RW2 @RW2+d16 SUBW NEGW NEGW ANDW ANDW ORW ORW XORW XORW NOTW NOTW @RW1 @RW1+d16 @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A @RW1 @RW1+d16 ADDW ADDW SUBCW A, +9 @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A A, @RW1 @RW1+d16 SUBCW NEGW NEGW ANDW ANDW ORW ORW XORW XORW NOTW NOTW @RW0 @RW0+d16 @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A @RW0 @RW0+d16 SUBW NOTW NOTW RW7 @RW7+d8 NOTW NOTW RW6 @RW6+d8 NOTW NOTW RW5 @RW5+d8 +8 @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A A, @RW0 @RW0+d16 SUBW XORW XORW RW7, A @RW7+d8, A ADDW ADDW SUBW SUBW SUBCW SUBCW A, NEGW NEGW ANDW ANDW ORW ORW RW7, A @RW7+d8, A RW7, A @RW7+d8, A A, RW7 @RW7+d8 RW7 @RW7+d8 RW7, A @RW7+d8, A RW7, A @RW7+d8, A +7 ADDW XORW XORW RW6, A @RW6+d8, A ADDW ADDW SUBW SUBW SUBCW SUBCW A, NEGW NEGW ANDW ANDW ORW ORW RW6, A @RW6+d8, A RW6, A @RW6+d8, A A, RW6 @RW6+d8 RW6 @RW6+d8 RW6, A @RW6+d8, A RW6, A @RW6+d8, A +6 ADDW XORW XORW RW5, A @RW5+d8, A ADDW ADDW SUBW SUBW SUBCW SUBCW A, NEGW NEGW ANDW ANDW ORW ORW RW5, A @RW5+d8, A RW5, A @RW5+d8, A A, RW5 @RW5+d8 RW5 @RW5+d8 RW5, A @RW5+d8, A RW5, A @RW5+d8, A +5 NOTW NOTW RW4 @RW4+d8 XORW XORW RW4, A @RW4+d8, A ADDW ADDW SUBW SUBW SUBCW SUBCW A, NEGW NEGW ANDW ANDW ORW ORW RW4, A @RW4+d8, A RW4, A @RW4+d8, A A, RW4 @RW4+d8 RW4 @RW4+d8 RW4, A @RW4+d8, A RW4, A @RW4+d8, A +4 F0 NOTW NOTW RW0 @RW0+d8 E0 NOTW NOTW RW3 @RW3+d8 D0 XORW XORW RW3, A @RW3+d8, A C0 ADDW ADDW SUBW SUBW SUBCW SUBCW A, NEGW NEGW ANDW ANDW ORW ORW RW3, A @RW3+d8, A RW3, A @RW3+d8, A A, RW3 @RW3+d8 RW3 @RW3+d8 RW3, A @RW3+d8, A RW3, A @RW3+d8, A B0 +3 A0 NOTW NOTW RW2 @RW2+d8 90 ADDW ADDW SUBW SUBW SUBCW SUBCW A, NEGW NEGW ANDW ANDW ORW ORW XORW XORW RW2, A @RW2+d8,A RW2, A @RW2+d8,A A, RW2 @RW2+d8 RW2 @RW2+d8 RW2, A @RW2+d8,A RW2, A @RW2+d8,A RW2, A @RW2+d8,A 80 +2 70 NOTW NOTW RW1 @RW1+d8 60 XORW XORW RW1, A @RW1+d8, A 50 ADDW ADDW SUBW SUBW SUBCW SUBCW A, NEGW NEGW ANDW ANDW ORW ORW RW1, A @RW1+d8, A RW1, A @RW1+d8, A A, RW1 @RW1+d8 RW1 @RW1+d8 RW1, A @RW1+d8, A RW1, A @RW1+d8, A 40 +1 30 XORW XORW RW0, A @RW0+d8, A 20 ADDW ADDW SUBW SUBW SUBCW SUBCW A, NEGW NEGW ANDW ANDW ORW ORW RW0, A @RW0+d8, A RW0, A @RW0+d8, A A, RW0 @RW0+d8 RW0 @RW0+d8 RW0, A @RW0+d8, A RW0, A @RW0+d8, A 10 +0 00 APPENDIX B Instructions Table B.9-13 ea Instruction 8 (First Byte = 77H) DIV DIV A, DIVW DIVW A, A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 DIV DIV A, DIVW DIVW A, A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 MUL MUL A, MULW MULW A, DIVU DIVU A, DIVUW DIVUW A, A, @RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 MUL MUL A, MULW MULW A, DIVU DIVU A, DIVUW DIVUW A, A, @RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 MUL MUL A, MULW MULW A, DIVU DIVU A, DIVUW DIVUW A, A, @RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 MULU MULU A, MULUW MULUW A, A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 MULU MULU A, MULUW MULUW A, A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 MULU MULU A, MULUW MULUW A, A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 MULU MULU A, MULUW MULUW A, MUL MUL A, MULW MULW A, DIVU DIVU A, DIVUW DIVUW A, A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 MULU MULU A, MULUW MULUW A, MUL MUL A, MULW MULW A, DIVU DIVU A, DIVUW DIVUW A, A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 MULU MULU A, MULUW MULUW A, MUL MUL A, MULW MULW A, DIVU DIVU A, DIVUW DIVUW A, DIV DIV A, DIVW DIVW A, A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 +9 +A +B +C +D +E +F A, @RW3+ MULU DIV DIV A, DIVW DIVW A, A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 MUL MUL A, MULW MULW A, DIVU DIVU A, DIVUW DIVUW A, A, @RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 MULU MULU A, MULUW MULUW A, A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 +8 MULU A, MULUW MULUW A, MUL MUL A, MULW MULW A, DIVU DIVU A, DIVUW DIVUW A, DIV DIV addr16 A,@RW3+ addr16 A,@RW3+ addr16 A,@RW3+ addr16 A,@RW3+ addr16 A,@RW3+ addr16 A,@RW3+ A, DIVW DIVW A, addr16 A,@RW3+ addr16 DIV DIV A, DIVW DIVW A, A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 DIV DIV A, DIVW DIVW A, A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 DIV DIV A, DIVW DIVW A, A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 MULU MULU A, MULUW MULUW A, MUL MUL A, MULW MULW A, DIVU DIVU A, DIVUW DIVUW A, DIV DIV A, DIVW DIVW A, A, R7 @RW7+d8 A, RW7 @RW7+d8 A, R7 @RW7+d8 A, RW7 @RW7+d8 A, R7 @RW7+d8 A, RW7 @RW7+d8 A, R7 @RW7+d8 A, RW7 @RW7+d8 F0 +7 E0 MULU MULU A, MULUW MULUW A, MUL MUL A, MULW MULW A, DIVU DIVU A, DIVUW DIVUW A, DIV DIV A, DIVW DIVW A, A, R6 @RW6+d8 A, RW6 @RW6+d8 A, R6 @RW6+d8 A, RW6 @RW6+d8 A, R6 @RW6+d8 A, RW6 @RW6+d8 A, R6 @RW6+d8 A, RW6 @RW6+d8 D0 +6 C0 MULU MULU A, MULUW MULUW A, MUL MUL A, MULW MULW A, DIVU DIVU A, DIVUW DIVUW A, DIV DIV A, DIVW DIVW A, A, R5 @RW5+d8 A, RW5 @RW5+d8 A, R5 @RW5+d8 A, RW5 @RW5+d8 A, R5 @RW5+d8 A, RW5 @RW5+d8 A, R5 @RW5+d8 A, RW5 @RW5+d8 B0 +5 A0 MULU MULU A, MULUW MULUW A, MUL MUL A, MULW MULW A, DIVU DIVU A, DIVUW DIVUW A, DIV DIV A, DIVW DIVW A, A, R4 @RW4+d8 A, RW4 @RW4+d8 A, R4 @RW4+d8 A, RW4 @RW4+d8 A, R4 @RW4+d8 A, RW4 @RW4+d8 A, R4 @RW4+d8 A, RW4 @RW4+d8 90 +4 80 MULU MULU A, MULUW MULUW A, MUL MUL A, MULW MULW A, DIVU DIVU A, DIVUW DIVUW A, DIV DIV A, DIVW DIVW A, A, R3 @RW3+d8 A, RW3 @RW3+d8 A, R3 @RW3+d8 A, RW3 @RW3+d8 A, R3 @RW3+d8 A, RW3 @RW3+d8 A, R3 @RW3+d8 A, RW3 @RW3+d8 70 +3 60 MULU MULU A, MULUW MULUW A, MUL MUL A, MULW MULW A, DIVU DIVU A, DIVUW DIVUW A, DIV DIV A, DIVW DIVW A, A, R2 @RW2+d8 A, RW2 @RW2+d8 A, R2 @RW2+d8 A, RW2 @RW2+d8 A, R2 @RW2+d8 A, RW2 @RW2+d8 A, R2 @RW2+d8 A, RW2 @RW2+d8 50 +2 40 MULU MULU A, MULUW MULUW A, MUL MUL A, MULW MULW A, DIVU DIVU A, DIVUW DIVUW A, DIV DIV A, DIVW DIVW A, A, R1 @RW1+d8 A, RW1 @RW1+d8 A, R1 @RW1+d8 A, RW1 @RW1+d8 A, R1 @RW1+d8 A, RW1 @RW1+d8 A, R1 @RW1+d8 A, RW1 @RW1+d8 30 +1 20 MULU MULU A, MULUW MULUW A, MUL MUL A, MULW MULW A, DIVU DIVU A, DIVUW DIVUW A, DIV DIV A, DIVW DIVW A, A, R0 @RW0+d8 A, RW0 @RW0+d8 A, R0 @RW0+d8 A, RW0 @RW0+d8 A, R0 @RW0+d8 A, RW0 @RW0+d8 A, R0 @RW0+d8 A, RW0 @RW0+d8 10 +0 00 APPENDIX B Instructions Table B.9-14 ea Instruction 9 (First Byte = 78H) 533 534 MOVEA MOVEA RW1 RW1,RW4 ,@RW4+d8 MOVEA MOVEA RW1 RW1,RW5 ,@RW5+d8 MOVEA MOVEA RW1 RW1,RW6 ,@RW6+d8 MOVEA MOVEA RW1 RW1,RW7 ,@RW7+d8 MOVEA MOVEA RW1 RW1,@RW0 ,@RW0+d16 MOVEA MOVEA RW1 RW1,@RW1 ,@RW1+d16 MOVEA MOVEA RW1 RW1,@RW2 ,@RW2+d16 MOVEA MOVEA RW1 RW1,@RW3 ,@RW3+d16 MOVEA MOVEA RW0 RW0,RW4 ,@RW4+d8 MOVEA MOVEA RW0 RW0,RW5 ,@RW5+d8 MOVEA MOVEA RW0 RW0,RW6 ,@RW6+d8 MOVEA MOVEA RW0 RW0,RW7 ,@RW7+d8 MOVEA RW0 MOVEA RW0 MOVEA RW0 MOVEA RW0 MOVEA RW0 MOVEA RW0 MOVEA MOVEA MOVEA MOVEA MOVEA MOVEA +4 +5 +6 +7 50 70 90 B0 C0 D0 F0 MOVEA MOVEA RW3 RW3,@RW2+ ,@PC+d16 MOVEA MOVEA RW4 RW4,@RW2+ ,@PC+d16 MOVEA MOVEA RW7 RW7,@RW2+ ,@PC+d16 MOVEA MOVEA MOVEA MOVEA RW6,@RW3+ RW6, addr16 RW7@RW3+ RW7, addr16 MOVEA MOVEA RW5 MOVEA MOVEA RW6 RW5,@RW2+ ,@PC+d16 RW6,@RW2+ ,@PC+d16 MOVEA MOVEA MOVEA MOVEA MOVEA MOVEA MOVEA MOVEA MOVEA MOVEA MOVEA MOVEA RW0,@RW3+ RW0, addr16 RW1,@RW3+ RW1, addr16 RW2,@RW3+ RW2, addr16 RW3,@RW3+ RW3, addr16 RW4,@RW3+ RW4, addr16 RW5,@RW3+ RW5, addr16 MOVEA MOVEA RW2 RW2,@RW2+ ,@PC+d16 +F MOVEA MOVEA RW1 RW1,@RW2+ ,@PC+d16 MOVEA MOVEA RW0 RW0,@RW2+ ,@PC+d16 MOVEA RW1 +E MOVEA MOVEA MOVEA RW5 MOVEA MOVEA RW6 MOVEA MOVEA RW7 RW5,@RW1+ ,@RW1+RW7 RW6,@RW1+ ,@RW1+RW7 RW7,@RW1+ ,@RW1+RW7 MOVEA MOVEA RW7 RW7,@RW3 ,@RW3+d16 MOVEA MOVEA RW7 RW7,@RW2 ,@RW2+d16 MOVEA MOVEA RW7 RW7,@RW1 ,@RW1+d16 MOVEA MOVEA RW7 RW7,@RW0 ,@RW0+d16 MOVEA MOVEA RW7 RW7,RW7 ,@RW7+d8 MOVEA MOVEA RW7 RW7,RW6 ,@RW6+d8 MOVEA MOVEA RW7 RW7,RW5 ,@RW5+d8 MOVEA MOVEA RW7 RW7,RW4 ,@RW4+d8 MOVEA MOVEA RW7 RW7,RW3 ,@RW3+d8 MOVEA MOVEA RW7 RW7,RW2 ,@RW2+d8 MOVEA MOVEA RW7 RW7,RW1 ,@RW1+d8 MOVEA MOVEA RW7 RW7,RW0 ,@RW0+d8 E0 MOVEA MOVEA RW2 MOVEA MOVEA RW3 MOVEA MOVEA RW4 RW2,@RW1+ ,@RW1+RW7 RW3,@RW1+ ,@RW1+RW7 RW4,@RW1+ ,@RW1+RW7 MOVEA MOVEA RW5 MOVEA MOVEA RW6 RW5,@RW3 ,@RW3+d16 RW6,@RW3 ,@RW3+d16 MOVEA MOVEA RW5 MOVEA MOVEA RW6 RW5,@RW2 ,@RW2+d16 RW6,@RW2 ,@RW2+d16 MOVEA MOVEA RW5 MOVEA MOVEA RW6 RW5,@RW1 ,@RW1+d16 RW6,@RW1 ,@RW1+d16 MOVEA MOVEA RW5 MOVEA MOVEA RW6 RW5,@RW0 ,@RW0+d16 RW6,@RW0 ,@RW0+d16 MOVEA MOVEA RW5 MOVEA MOVEA RW6 RW5,RW7 ,@RW7+d8 RW6,RW7 ,@RW7+d8 MOVEA MOVEA RW5 MOVEA MOVEA RW6 RW5,RW6 ,@RW6+d8 RW6,RW6 ,@RW6+d8 MOVEA MOVEA RW5 MOVEA MOVEA RW6 RW5,RW5 ,@RW5+d8 RW6,RW5 ,@RW5+d8 MOVEA MOVEA RW5 MOVEA MOVEA RW6 RW5,RW4 ,@RW4+d8 RW6,RW4 ,@RW4+d8 MOVEA MOVEA RW5 MOVEA MOVEA RW6 RW5,RW3 ,@RW3+d8 RW6,RW3 ,@RW3+d8 MOVEA MOVEA RW5 MOVEA MOVEA RW6 RW5,RW2 ,@RW2+d8 RW6,RW2 ,@RW2+d8 MOVEA MOVEA RW5 MOVEA MOVEA RW6 RW5,RW1 ,@RW1+d8 RW6,RW1 ,@RW1+d8 MOVEA MOVEA RW5 MOVEA MOVEA RW6 RW5,RW0 ,@RW0+d8 RW6,RW0 ,@RW0+d8 A0 +D RW0,@RW1+ ,@RW1+RW7 RW1,@RW1+ ,@RW1+RW7 MOVEA MOVEA RW4 RW4,@RW3 ,@RW3+d16 MOVEA MOVEA RW4 RW4,@RW2 ,@RW2+d16 MOVEA MOVEA RW4 RW4,@RW1 ,@RW1+d16 MOVEA MOVEA RW4 RW4,@RW0 ,@RW0+d16 MOVEA MOVEA RW4 RW4,RW7 ,@RW7+d8 MOVEA MOVEA RW4 RW4,RW6 ,@RW6+d8 MOVEA MOVEA RW4 RW4,RW5 ,@RW5+d8 MOVEA MOVEA RW4 RW4,RW4 ,@RW4+d8 MOVEA MOVEA RW4 RW4,RW3 ,@RW3+d8 MOVEA MOVEA RW4 RW4,RW2 ,@RW2+d8 MOVEA MOVEA RW4 RW4,RW1 ,@RW1+d8 MOVEA MOVEA RW4 RW4,RW0 ,@RW0+d8 80 MOVEA MOVEA RW5 MOVEA MOVEA RW6 MOVEA MOVEA RW7 RW5,@RW0+ ,@RW0+RW7 RW6,@RW0+ ,@RW0+RW7 RW7,@RW0+ ,@RW0+RW7 MOVEA MOVEA RW3 RW3,@RW3 ,@RW3+d16 MOVEA MOVEA RW3 RW3,@RW2 ,@RW2+d16 MOVEA MOVEA RW3 RW3,@RW1 ,@RW1+d16 MOVEA MOVEA RW3 RW3,@RW0 ,@RW0+d16 MOVEA MOVEA RW3 RW3,RW7 ,@RW7+d8 MOVEA MOVEA RW3 RW3,RW6 ,@RW6+d8 MOVEA MOVEA RW3 RW3,RW5 ,@RW5+d8 MOVEA MOVEA RW3 RW3,RW4 ,@RW4+d8 MOVEA MOVEA RW3 RW3,RW3 ,@RW3+d8 MOVEA MOVEA RW3 RW3,RW2 ,@RW2+d8 MOVEA MOVEA RW3 RW3,RW1 ,@RW1+d8 MOVEA MOVEA RW3 RW3,RW0 ,@RW0+d8 60 MOVEA MOVEA RW2 MOVEA MOVEA RW3 MOVEA MOVEA RW4 RW2,@RW0+ ,@RW0+RW7 RW3,@RW0+ ,@RW0+RW7 RW4,@RW0+ ,@RW0+RW7 MOVEA MOVEA RW2 RW2,@RW3 ,@RW3+d16 MOVEA MOVEA RW2 RW2,@RW2 ,@RW2+d16 MOVEA MOVEA RW2 RW2,@RW1 ,@RW1+d16 MOVEA MOVEA RW2 RW2,@RW0 ,@RW0+d16 MOVEA MOVEA RW2 RW2,RW7 ,@RW7+d8 MOVEA MOVEA RW2 RW2,RW6 ,@RW6+d8 MOVEA MOVEA RW2 RW2,RW5 ,@RW5+d8 MOVEA MOVEA RW2 RW2,RW4 ,@RW4+d8 MOVEA MOVEA RW2 RW2,RW3 ,@RW3+d8 MOVEA MOVEA RW2 RW2,RW2 ,@RW2+d8 MOVEA MOVEA RW2 RW2,RW1 ,@RW1+d8 MOVEA MOVEA RW2 RW2,RW0 ,@RW0+d8 40 +C RW0,@RW0+ ,@RW0+RW7 RW1,@RW0+ ,@RW0+RW7 +B RW0,@RW3 ,@RW3+d16 +A RW0,@RW2 ,@RW2+d16 +9 RW0,@RW1 ,@RW1+d16 MOVEA RW1 MOVEA MOVEA RW1 RW1,RW3 ,@RW3+d8 MOVEA MOVEA RW0 RW0,RW3 ,@RW3+d8 +3 MOVEA MOVEA MOVEA RW1 RW1,RW2 ,@RW2+d8 MOVEA MOVEA RW0 RW0,RW2 ,@RW2+d8 +2 +8 RW0,@RW0 ,@RW0+d16 MOVEA MOVEA RW1 RW1,RW1 ,@RW1+d8 MOVEA MOVEA RW0 RW0,RW1 ,@RW1+d8 +1 30 MOVEA MOVEA RW1 RW1,RW0 ,@RW0+d8 20 MOVEA MOVEA RW0 RW0,RW0 ,@RW0+d8 10 +0 00 APPENDIX B Instructions Table B.9-15 MOVEA RWi, ea Instruction (First Byte = 79H) MOV MOV R0, MOV MOV R1, MOV MOV R2, MOV MOV R3, MOV MOV R4, MOV MOV R5, MOV MOV R6, MOV MOV R7, R0, R7 @RW7+d8 R1, R7 @RW7+d8 R2, R7 @RW7+d8 R3, R7 @RW7+d8 R4, R7 @RW7+d8 R5, R7 @RW7+d8 R6, R7 @RW7+d8 R7, R7 @RW7+d8 MOV MOV R0, MOV MOV R1, MOV MOV R2, MOV MOV R3, MOV MOV R4, MOV MOV R5, MOV MOV R6, MOV MOV R7, R0,@RW0 @RW0+d16 R1,@RW0 @RW0+d16 R2,@RW0 @RW0+d16 R3,@RW0 @RW0+d16 R4,@RW0 @RW0+d16 R5,@RW0 @RW0+d16 R6,@RW0 @RW0+d16 R7,@RW0 @RW0+d16 MOV MOV R0, MOV MOV R1, MOV MOV R2, MOV MOV R3, MOV MOV R4, MOV MOV R5, MOV MOV R6, MOV MOV R7, R0,@RW1 @RW1+d16 R1,@RW1 @RW1+d16 R2,@RW1 @RW1+d16 R3,@RW1 @RW1+d16 R4,@RW1 @RW1+d16 R5,@RW1 @RW1+d16 R6,@RW1 @RW1+d16 R7,@RW1 @RW1+d16 MOV MOV R0, MOV MOV R1, MOV MOV R2, MOV MOV R3, MOV MOV R4, MOV MOV R5, MOV MOV R6, MOV MOV R7, R0,@RW2 @RW2+d16 R1,@RW2 @RW2+d16 R2,@RW2 @RW2+d16 R3,@RW2 @RW2+d16 R4,@RW2 @RW2+d16 R5,@RW2 @RW2+d16 R6,@RW2 @RW2+d16 R7,@RW2 @RW2+d16 MOV MOV R0, MOV MOV R1, MOV MOV R2, MOV MOV R3, MOV MOV R4, MOV MOV R5, MOV MOV R6, MOV MOV R7, R0,@RW3 @RW3+d16 R1,@RW3 @RW3+d16 R2,@RW3 @RW3+d16 R3,@RW3 @RW3+d16 R4,@RW3 @RW3+d16 R5,@RW3 @RW3+d16 R6,@RW3 @RW3+d16 R7,@RW3 @RW3+d16 MOV R0, MOV R0, MOV R1, MOV R1, MOV R2, MOV R2, MOV R3, MOV R3, MOV R4, MOV R4, MOV R5, MOV R5, MOV R6, MOV R6, MOV R7, MOV R7, @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 MOV R0, MOV R0, MOV R1, MOV R1, MOV R2, MOV R2, MOV R3, MOV R3, MOV R4, MOV R4, MOV R5, MOV R5, MOV R6, MOV R6, MOV R7, MOV R7, @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 MOV R0, MOV R0, MOV R1, MOV R1, MOV R2, MOV R2, MOV R3, MOV R3, MOV R4, MOV R4, MOV R5, MOV R5, MOV R6, MOV R6, MOV R7, MOV R7, @RW2+ @PC+d16 @RW2+ @PC+d16 @RW2+ @PC+d16 @RW2+ @PC+d16 @RW2+ @PC+d16 @RW2+ @PC+d16 @RW2+ @PC+d16 @RW2+ @PC+d16 MOV R0, MOV R0, MOV R1, MOV R1, MOV R2, MOV R2, MOV R3, MOV R3, MOV R4, MOV R4, MOV R5, MOV R5, MOV R6, MOV R6, MOV R7, MOV R7, @RW3+ addr16 @RW3+ addr16 @RW3+ addr16 @RW3+ addr16 @RW3+ addr16 @RW3+ addr16 @RW3+ addr16 @RW3+ addr16 +8 +9 +A +B +C +D +E +F F0 +7 E0 MOV MOV R0, MOV MOV R1, MOV MOV R2, MOV MOV R3, MOV MOV R4, MOV MOV R5, MOV MOV R6, MOV MOV R7, R0, R6 @RW6+d8 R1, R6 @RW6+d8 R2, R6 @RW6+d8 R3, R6 @RW6+d8 R4, R6 @RW6+d8 R5, R6 @RW6+d8 R6, R6 @RW6+d8 R7, R6 @RW6+d8 D0 +6 C0 MOV MOV R0, MOV MOV R1, MOV MOV R2, MOV MOV R3, MOV MOV R4, MOV MOV R5, MOV MOV R6, MOV MOV R7, R0, R5 @RW5+d8 R1, R5 @RW5+d8 R2, R5 @RW5+d8 R3, R5 @RW5+d8 R4, R5 @RW5+d8 R5, R5 @RW5+d8 R6, R5 @RW5+d8 R7, R5 @RW5+d8 B0 +5 A0 MOV MOV R0, MOV MOV R1, MOV MOV R2, MOV MOV R3, MOV MOV R4, MOV MOV R5, MOV MOV R6, MOV MOV R7, R0, R4 @RW4+d8 R1, R4 @RW4+d8 R2, R4 @RW4+d8 R3, R4 @RW4+d8 R4, R4 @RW4+d8 R5, R4 @RW4+d8 R6, R4 @RW4+d8 R7, R4 @RW4+d8 90 +4 80 MOV MOV R0, MOV MOV R1, MOV MOV R2, MOV MOV R3, MOV MOV R4, MOV MOV R5, MOV MOV R6, MOV MOV R7, R0, R3 @RW3+d8 R1, R3 @RW3+d8 R2, R3 @RW3+d8 R3, R3 @RW3+d8 R4, R3 @RW3+d8 R5, R3 @RW3+d8 R6, R3 @RW3+d8 R7, R3 @RW3+d8 70 +3 60 MOV MOV R0, MOV MOV R1, MOV MOV R2, MOV MOV R3, MOV MOV R4, MOV MOV R5, MOV MOV R6, MOV MOV R7, R0, R2 @RW2+d8 R1, R2 @RW2+d8 R2, R2 @RW2+d8 R3, R2 @RW2+d8 R4, R2 @RW2+d8 R5, R2 @RW2+d8 R6, R2 @RW2+d8 R7, R2 @RW2+d8 50 +2 40 MOV MOV R0, MOV MOV R1, MOV MOV R2, MOV MOV R3, MOV MOV R4, MOV MOV R5, MOV MOV R6, MOV MOV R7, R0, R1 @RW1+d8 R1, R1 @RW1+d8 R2, R1 @RW1+d8 R3, R1 @RW1+d8 R4, R1 @RW1+d8 R5, R1 @RW1+d8 R6, R1 @RW1+d8 R7, R1 @RW1+d8 30 +1 20 MOV MOV R0, MOV MOV R1, MOV MOV R2, MOV MOV R3, MOV MOV R4, MOV MOV R5, MOV MOV R6, MOV MOV R7, R0, R0 @RW0+d8 R1, R0 @RW0+d8 R2, R0 @RW0+d8 R3, R0 @RW0+d8 R4, R0 @RW0+d8 R5, R0 @RW0+d8 R6, R0 @RW0+d8 R7, R0 @RW0+d8 10 +0 00 APPENDIX B Instructions Table B.9-16 MOV Ri, ea Instruction (First Byte = 7AH) 535 536 MOVW MOVW RW5, RW5,@RW3 @RW3+d16 MOVW MOVW MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, RW0,@RW1 @RW1+d16 RW1,@RW1 @RW1+d16 RW2,@RW1 @RW1+d16 RW3,@RW1 @RW1+d16 RW4,@RW1 @RW1+d16 MOVW MOVW MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, RW0,@RW2 @RW2+d16 RW1,@RW2 @RW2+d16 RW2,@RW2 @RW2+d16 RW3,@RW2 @RW2+d16 RW4,@RW2 @RW2+d16 MOVW MOVW MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, RW0,@RW3 @RW3+d16 RW1,@RW3 @RW3+d16 RW2,@RW3 @RW3+d16 RW3,@RW3 @RW3+d16 RW4,@RW3 @RW3+d16 MOVW MOVW MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, MOVW MOVW RW5, MOVW MOVW RW6, MOVW MOVW RW7, RW0,@RW0+ @RW0+RW7 RW1,@RW0+ @RW0+RW7 RW2,@RW0+ @RW0+RW7 RW3,@RW0+ @RW0+RW7 RW4,@RW0+ @RW0+RW7 RW5,@RW0+ @RW0+RW7 RW6,@RW0+ @RW0+RW7 RW7,@RW0+ @RW0+RW7 MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, RW1, @RW2+ @PC+d16 RW2, @RW2+ @PC+d16 RW3, @RW2+ @PC+d16 RW4, @RW2+ @PC+d16 MOVW MOVW RW1, @RW3+ RW1, addr16 MOVW RW0, @RW1+ MOVW MOVW RW0, @RW2+ @PC+d16 MOVW MOVW RW0, @RW3+ RW0, addr16 +9 +A +B +C +D +E +F MOVW MOVW RW2, @RW3+ RW2, addr16 MOVW MOVW RW3, @RW3+ RW3, addr16 MOVW MOVW RW5, @RW3+ RW5, addr16 MOVW MOVW RW5, @RW2+ @PC+d16 MOVW MOVW RW6, @RW3+ RW6, addr16 MOVW MOVW RW6, RW6, @RW2+ @PC+d16 MOVW MOVW RW7, @RW3+ RW7, addr16 MOVW MOVW RW7, RW7, @RW2+ @PC+d16 MOVW RW7, @RW1+RW7 MOVW MOVW RW7, RW7,@RW3 @RW3+d16 MOVW MOVW RW7, RW7,@RW2 @RW2+d16 MOVW MOVW RW7, RW7,@RW1 @RW1+d16 MOVW MOVW RW7, RW7,@RW0 @RW0+d16 MOVW MOVW RW7, RW7, RW7 @RW7+d8 MOVW MOVW RW7, RW7, RW6 @RW6+d8 MOVW MOVW RW7, RW7, RW5 @RW5+d8 MOVW MOVW RW7, RW7, RW4 @RW4+d8 MOVW RW6, MOVW @RW1+RW7 RW7, @RW1+ MOVW MOVW RW6, RW6,@RW3 @RW3+d16 MOVW MOVW RW6, RW6,@RW2 @RW2+d16 MOVW MOVW RW6, RW6,@RW1 @RW1+d16 MOVW MOVW RW6, RW6,@RW0 @RW0+d16 MOVW MOVW RW6, RW6, RW7 @RW7+d8 MOVW MOVW RW6, RW6, RW6 @RW6+d8 MOVW MOVW RW6, RW6, RW5 @RW5+d8 MOVW MOVW RW6, RW6, RW4 @RW4+d8 MOVW MOVW @RW1+RW7 RW6, @RW1+ MOVW MOVW RW5, RW5, RW6 @RW6+d8 MOVW MOVW RW5, RW5, RW5 @RW5+d8 MOVW RW4, MOVW @RW1+RW7 RW5, @RW1+ MOVW MOVW RW4, @RW3+ RW4, addr16 MOVW RW3, MOVW @RW1+RW7 RW4, @RW1+ MOVW MOVW RW5, RW5,@RW2 @RW2+d16 MOVW MOVW MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, RW0,@RW0 @RW0+d16 RW1,@RW0 @RW0+d16 RW2,@RW0 @RW0+d16 RW3,@RW0 @RW0+d16 RW4,@RW0 @RW0+d16 +8 MOVW RW2, MOVW @RW1+RW7 RW3, @RW1+ MOVW MOVW RW5, RW5,@RW1 @RW1+d16 MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, RW1, RW7 @RW7+d8 RW2, RW7 @RW7+d8 RW3, RW7 @RW7+d8 RW4, RW7 @RW7+d8 MOVW MOVW RW0, RW7 @RW7+d8 +7 MOVW RW1, MOVW @RW1+RW7 RW2, @RW1+ MOVW MOVW RW5, RW5,@RW0 @RW0+d16 MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, RW1, RW6 @RW6+d8 RW2, RW6 @RW6+d8 RW3, RW6 @RW6+d8 RW4, RW6 @RW6+d8 MOVW MOVW RW0, RW6 @RW6+d8 +6 MOVW MOVW @RW1+RW7 RW1, @RW1+ MOVW MOVW RW5, RW5, RW7 @RW7+d8 MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, RW1, RW5 @RW5+d8 RW2, RW5 @RW5+d8 RW3, RW5 @RW5+d8 RW4, RW5 @RW5+d8 MOVW MOVW RW0, RW5 @RW5+d8 +5 MOVW MOVW RW5, RW5, RW4 @RW4+d8 MOVW MOVW RW7, RW7, RW3 @RW3+d8 MOVW MOVW RW7, RW7, RW2 @RW2+d8 MOVW MOVW RW7, RW7, RW1 @RW1+d8 MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, RW1, RW4 @RW4+d8 RW2, RW4 @RW4+d8 RW3, RW4 @RW4+d8 RW4, RW4 @RW4+d8 MOVW MOVW RW6, RW6, RW3 @RW3+d8 MOVW MOVW RW6, RW6, RW2 @RW2+d8 MOVW MOVW RW6, RW6, RW1 @RW1+d8 MOVW MOVW RW0, RW4 @RW4+d8 MOVW MOVW RW5, RW5, RW3 @RW3+d8 MOVW MOVW RW5, RW5, RW2 @RW2+d8 MOVW MOVW RW5, RW5, RW1 @RW1+d8 +4 F0 MOVW MOVW RW7, RW7, RW0 @RW0+d8 E0 MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, RW1, RW3 @RW3+d8 RW2, RW3 @RW3+d8 RW3, RW3 @RW3+d8 RW4, RW3 @RW3+d8 D0 MOVW MOVW RW6, RW6, RW0 @RW0+d8 C0 MOVW MOVW RW0, RW3 @RW3+d8 B0 MOVW MOVW RW5, RW5, RW0 @RW0+d8 A0 +3 90 MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, RW1, RW2 @RW2+d8 RW2, RW2 @RW2+d8 RW3, RW2 @RW2+d8 RW4, RW2 @RW2+d8 80 MOVW MOVW RW0, RW2 @RW2+d8 70 +2 60 MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, RW1, RW1 @RW1+d8 RW2, RW1 @RW1+d8 RW3, RW1 @RW1+d8 RW4, RW1 @RW1+d8 50 MOVW MOVW RW0, RW1 @RW1+d8 40 +1 30 MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, RW1, RW0 @RW0+d8 RW2, RW0 @RW0+d8 RW3, RW0 @RW0+d8 RW4, RW0 @RW0+d8 20 MOVW MOVW RW0, RW0 @RW0+d8 10 +0 00 APPENDIX B Instructions Table B.9-17 MOVW RWi, ea Instruction (First Byte = 7BH) +F +E +D +C +B +A +9 +8 MOV MOV MOV MOV MOV MOV MOV MOV MOV @RW3+, R1 addr16, R1 MOV MOV @RW3+, R0 addr16, R0 MOV MOV MOV @RW2+, R1 @PC+d16, R1 @RW2+, R0 @PC+d16, R0 MOV MOV MOV MOV MOV @RW0+, R1 @RW0+RW7, R1 MOV @RW3, R1 @RW3+d16, R1 MOV @RW2, R1 @RW2+d16, R1 MOV @RW1, R1 @RW1+d16, R1 MOV @RW1+, R1 @RW1+RW7, R1 MOV MOV @RW0, R1 @RW0+d16, R1 MOV @RW1+, R0 @RW1+RW7, R0 MOV @RW0+, R0 @RW0+RW7, R0 MOV @RW3, R0 @RW3+d16, R0 MOV @RW2, R0 @RW2+d16, R0 MOV @RW1, R0 @RW1+d16, R0 MOV @RW0, R0 @RW0+d16, R0 MOV MOV MOV MOV MOV MOV MOV MOV MOV @RW3+, R2 addr16, R2 MOV @RW2+, R2 @PC+d16, R2 MOV @RW1+, R2 @RW1+RW7, R2 MOV @RW0+, R2 @RW0+RW7, R2 MOV @RW3, R2 @RW3+d16, R2 MOV @RW2, R2 @RW2+d16, R2 MOV @RW1, R2 @RW1+d16, R2 MOV @RW0, R2 @RW0+d16, R2 MOV MOV MOV MOV MOV MOV MOV MOV MOV @RW3+, R3 addr16, R3 MOV @RW2+, R3 @PC+d16, R3 MOV @RW1+, R3 @RW1+RW7, R3 MOV @RW0+, R3 @RW0+RW7, R3 MOV @RW3, R3 @RW3+d16, R3 MOV @RW2, R3 @RW2+d16, R3 MOV @RW1, R3 @RW1+d16, R3 MOV @RW0, R3 @RW0+d16, R3 MOV MOV MOV MOV MOV MOV MOV MOV MOV @RW3+, R4 addr16, R4 MOV @RW2+, R4 @PC+d16, R4 MOV @RW1+, R4 @RW1+RW7, R4 MOV @RW0+, R4 @RW0+RW7, R4 MOV @RW3, R4 @RW3+d16, R4 MOV @RW2, R4 @RW2+d16, R4 MOV @RW1, R4 @RW1+d16, R4 MOV @RW0, R4 @RW0+d16, R4 MOV MOV MOV MOV MOV MOV MOV MOV MOV @RW3+, R5 addr16, R5 MOV @RW2+, R5 @PC+d16, R5 MOV @RW1+, R5 @RW1+RW7, R5 MOV @RW0+, R5 @RW0+RW7, R5 MOV @RW3, R5 @RW3+d16, R5 MOV @RW2, R5 @RW2+d16, R5 MOV @RW1, R5 @RW1+d16, R5 MOV @RW0, R5 @RW0+d16, R5 MOV MOV MOV MOV MOV MOV MOV MOV MOV @RW3+, R6 addr16, R6 MOV @RW2+, R6 @PC+d16, R6 MOV @RW1+, R6 @RW1+RW7, R6 MOV @RW0+, R6 @RW0+RW7, R6 MOV @RW3, R6 @RW3+d16, R6 MOV @RW2, R6 @RW2+d16, R6 MOV @RW1, R6 @RW1+d16, R6 MOV @RW0, R6 @RW0+d16, R6 MOV MOV MOV MOV MOV MOV MOV MOV MOV @RW3+, R7 addr16, R7 MOV @RW2+, R7 @PC+d16, R7 MOV @RW1+, R7 @RW1+RW7, R7 MOV @RW0+, R7 @RW0+RW7, R7 MOV @RW3, R7 @RW3+d16, R7 MOV @RW2, R7 @RW2+d16, R7 MOV @RW1, R7 @RW1+d16, R7 MOV @RW0, R7 @RW0+d16, R7 MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV R7, R0 @RW7+d8, R0 R7, R1 @RW7+d8, R1 R7, R2 @RW7+d8, R2 R7, R3 @RW7+d8, R3 R7, R4 @RW7+d8, R4 R7, R5 @RW7+d8, R5 R7, R6 @RW7+d8, R6 R7, R7 @RW7+d8, R7 F0 +7 E0 MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV R6, R0 @RW6+d8, R0 R6, R1 @RW6+d8, R1 R6, R2 @RW6+d8, R2 R6, R3 @RW6+d8, R3 R6, R4 @RW6+d8, R4 R6, R5 @RW6+d8, R5 R6, R6 @RW6+d8, R6 R6, R7 @RW6+d8, R7 D0 +6 C0 MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV R5, R0 @RW5+d8, R0 R5, R1 @RW5+d8, R1 R5, R2 @RW5+d8, R2 R5, R3 @RW5+d8, R3 R5, R4 @RW5+d8, R4 R5, R5 @RW5+d8, R5 R5, R6 @RW5+d8, R6 R5, R7 @RW5+d8, R7 B0 +5 A0 MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV R4, R0 @RW4+d8, R0 R4, R1 @RW4+d8, R1 R4, R2 @RW4+d8, R2 R4, R3 @RW4+d8, R3 R4, R4 @RW4+d8, R4 R4, R5 @RW4+d8, R5 R4, R6 @RW4+d8, R6 R4, R7 @RW4+d8, R7 90 +4 80 MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV R3, R0 @RW3+d8, R0 R3, R1 @RW3+d8, R1 R3, R2 @RW3+d8, R2 R3, R3 @RW3+d8, R3 R3, R4 @RW3+d8, R4 R3, R5 @RW3+d8, R5 R3, R6 @RW3+d8, R6 R3, R7 @RW3+d8, R7 70 +3 60 MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV R2, R0 @RW2+d8, R0 R2, R1 @RW2+d8, R1 R2, R2 @RW2+d8, R2 R2, R3 @RW2+d8, R3 R2, R4 @RW2+d8, R4 R2, R5 @RW2+d8, R5 R2, R6 @RW2+d8, R6 R2, R7 @RW2+d8, R7 50 +2 40 MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV R1, R0 @RW1+d8, R0 R1, R1 @RW1+d8, R1 R1, R2 @RW1+d8, R2 R1, R3 @RW1+d8, R3 R1, R4 @RW1+d8, R4 R1, R5 @RW1+d8, R5 R1, R6 @RW1+d8, R6 R1, R7 @RW1+d8, R7 30 +1 20 MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV R0, R0 @RW0+d8, R0 R0, R1 @RW0+d8, R1 R0, R2 @RW0+d8, R2 R0, R3 @RW0+d8, R3 R0, R4 @RW0+d8, R4 R0, R5 @RW0+d8, R5 R0, R6 @RW0+d8, R6 R0, R7 @RW0+d8, R7 10 +0 00 APPENDIX B Instructions Table B.9-18 MOV ea, Ri Instruction (First Byte = 7CH) 537 538 MOVW MOVW@RW2 @RW2, RW1 +d16, RW1 MOVW MOVW@RW3 @RW3, RW1 +d16, RW1 MOVW MOVW@RW0 @RW0+, RW1 +RW7,RW1 MOVW MOVW@RW1 @RW1+,RW1 +RW7,RW1 MOVW MOVW@PC @RW2+,RW1 +d16, RW1 MOVW MOVW @RW3+,RW1 addr16, RW1 MOVW MOVW@RW2 @RW2, RW0 +d16, RW0 MOVW MOVW@RW3 @RW3, RW0 +d16, RW0 MOVW MOVW@RW0 @RW0+,RW0 +RW7,RW0 MOVW MOVW@RW1 @RW1+,RW0 +RW7,RW0 MOVW MOVW@PC @RW2+,RW0 +d16, RW0 MOVW MOVW @RW3+,RW0 addr16, RW0 +B +C +D +E +F MOVW MOVW @RW3+,RW2 addr16, RW2 MOVW MOVW@PC @RW2+,RW2 +d16, RW2 MOVW MOVW@RW1 @RW1+,RW2 +RW7,RW2 MOVW MOVW@RW0 @RW0+,RW2 +RW7,RW2 MOVW MOVW@RW3 @RW3, RW2 +d16, RW2 MOVW MOVW@RW2 @RW2, RW2 +d16, RW2 MOVW MOVW @RW3+,RW3 addr16, RW3 MOVW MOVW@PC @RW2+,RW3 +d16, RW3 MOVW MOVW@RW1 @RW1+,RW3 -+RW7,RW3 MOVW MOVW@RW0 @RW0+,RW3 +RW7,RW3 MOVW MOVW@RW3 @RW3, RW3 +d16, RW3 MOVW MOVW@RW2 @RW2, RW3 +d16, RW3 MOVW MOVW@RW1 @RW1, RW3 +d16, RW3 MOVW MOVW @RW3+,RW4 addr16, RW4 MOVW MOVW@PC @RW2+,RW4 +d16, RW4 MOVW MOVW@RW1 @RW1+,RW4 +RW7,RW4 MOVW MOVW@RW0 @RW0+,RW4 +RW7,RW4 MOVW MOVW@RW3 @RW3, RW4 +d16, RW4 MOVW MOVW@RW2 @RW2, RW4 +d16, RW4 MOVW MOVW@RW1 @RW1, RW4 +d16, RW4 MOVW MOVW @RW3+,RW5 addr16, RW5 MOVW MOVW@PC @RW2+,RW5 +d16, RW5 MOVW MOVW@RW1 @RW1+,RW5 +RW7,RW5 MOVW MOVW@RW0 @RW0+,RW5 +RW7,RW5 MOVW MOVW@RW3 @RW3, RW5 +d16, RW5 MOVW MOVW@RW2 @RW2, RW5 +d16, RW5 MOVW MOVW@RW1 @RW1, RW5 +d16, RW5 MOVW MOVW @RW3+,RW6 addr16, RW6 MOVW MOVW @PC @RW2+,RW6 +d16, RW6 MOVW MOVW@RW1 @RW1+,RW6 +RW7,RW6 MOVW MOVW@RW0 @RW0+,RW6 +RW7,RW6 MOVW MOVW@RW3 @RW3, RW6 +d16, RW6 MOVW MOVW@RW2 @RW2, RW6 +d16, RW6 MOVW MOVW@RW1 @RW1, RW6 +d16, RW6 MOVW MOVW @RW3+,RW7 addr16, RW7 MOVW MOVW@PC @RW2+,RW7 +d16, RW7 MOVW MOVW@RW1 @RW1+,RW7 +RW7,RW7 MOVW MOVW@RW0 @RW0+,RW7 +RW7,RW7 MOVW MOVW@RW3 @RW3, RW7 +d16, RW7 MOVW MOVW@RW2 @RW2, RW7 +d16, RW7 MOVW MOVW@RW1 @RW1, RW7 +d16, RW7 MOVW MOVW@RW0 @RW0, RW7 +d16, RW7 +A MOVW MOVW@RW1 @RW1, RW2 +d16, RW2 MOVW MOVW@RW0 @RW0, RW6 +d16, RW6 MOVW MOVW@RW1 @RW1, RW1 +d16, RW1 MOVW MOVW@RW0 @RW0, RW5 +d16, RW5 MOVW MOVW@RW1 @RW1, RW0 +d16, RW0 MOVW MOVW@RW0 @RW0, RW4 +d16, RW4 +9 MOVW MOVW@RW0 @RW0, RW3 +d16, RW3 MOVW MOVW@RW0 @RW0, RW1 +d16, RW1 MOVW MOVW@RW0 @RW0, RW0 +d16, RW0 +8 MOVW MOVW@RW0 @RW0, RW2 +d16, RW2 MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW RW7, RW0 @RW7+d8, RW0 RW7, RW1 @RW7+d8, RW1 RW7, RW2 @RW7+d8, RW2 RW7, RW3 @RW7+d8, RW3 RW7, RW4 @RW7+d8, RW4 RW7, RW5 @RW7+d8, RW5 RW7, RW6 @RW7+d8, RW6 RW7, RW7 @RW7+d8, RW7 F0 +7 E0 MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW RW6, RW0 @RW6+d8, RW0 RW6, RW1 @RW6+d8, RW1 RW6, RW2 @RW6+d8, RW2 RW6, RW3 @RW6+d8, RW3 RW6, RW4 @RW6+d8, RW4 RW6, RW5 @RW6+d8, RW5 RW6, RW6 @RW6+d8, RW6 RW6, RW7 @RW6+d8, RW7 D0 +6 C0 MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW RW5, RW0 @RW5+d8, RW0 RW5, RW1 @RW5+d8, RW1 RW5, RW2 @RW5+d8, RW2 RW5, RW3 @RW5+d8, RW3 RW5, RW4 @RW5+d8, RW4 RW5, RW5 @RW5+d8, RW5 RW5, RW6 @RW5+d8, RW6 RW5, RW7 @RW5+d8, RW7 B0 +5 A0 MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW RW4, RW0 @RW4+d8, RW0 RW4, RW1 @RW4+d8, RW1 RW4, RW2 @RW4+d8, RW2 RW4, RW3 @RW4+d8, RW3 RW4, RW4 @RW4+d8, RW4 RW4, RW5 @RW4+d8, RW5 RW4, RW6 @RW4+d8, RW6 RW4, RW7 @RW4+d8, RW7 90 +4 80 MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW RW3, RW0 @RW3+d8, RW0 RW3, RW1 @RW3+d8, RW1 RW3, RW2 @RW3+d8, RW2 RW3, RW3 @RW3+d8, RW3 RW3, RW4 @RW3+d8, RW4 RW3, RW5 @RW3+d8, RW5 RW3, RW6 @RW3+d8, RW6 RW3, RW7 @RW3+d8, RW7 70 +3 60 MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW RW2, RW0 @RW2+d8, RW0 RW2, RW1 @RW2+d8, RW1 RW2, RW2 @RW2+d8, RW2 RW2, RW3 @RW2+d8, RW3 RW2, RW4 @RW2+d8, RW4 RW2, RW5 @RW2+d8, RW5 RW2, RW6 @RW2+d8, RW6 RW2, RW7 @RW2+d8, RW7 50 +2 40 MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW RW1, RW0 @RW1+d8, RW0 RW1, RW1 @RW1+d8, RW1 RW1, RW2 @RW1+d8, RW2 RW1, RW3 @RW1+d8, RW3 RW1, RW4 @RW1+d8, RW4 RW1, RW5 @RW1+d8, RW5 RW1, RW6 @RW1+d8, RW6 RW1, RW7 @RW1+d8, RW7 30 +1 20 MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW RW0, RW0 @RW0+d8, RW0 RW0, RW1 @RW0+d8, RW1 RW0, RW2 @RW0+d8, RW2 RW0, RW3 @RW0+d8, RW3 RW0, RW4 @RW0+d8, RW4 RW0, RW5 @RW0+d8, RW5 RW0, RW6 @RW0+d8, RW6 RW0, RW7 @RW0+d8, RW7 10 +0 00 APPENDIX B Instructions Table B.9-19 MOVW ea, Rwi Instruction (First Byte = 7DH) XCH XCH XCH XCH R1, XCH XCH R1, R1,@RW2 W2+d16, A XCH XCH R2, XCH XCH R2, R2,@RW2 W2+d16, A XCH XCH R3, XCH XCH R3, R3,@RW2 W2+d16, A XCH XCH R4, XCH XCH R4, R4,@RW2 W2+d16, A XCH XCH R5, XCH XCH R5, R5,@RW2 W2+d16, A XCH XCH R6, XCH XCH R6, R6,@RW2 W2+d16, A XCH XCH R7, XCH XCH R7, R7,@RW2 W2+d16, A XCH XCH XCH XCH XCH R1, XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, +F R0,@RW3+ R0, addr16 XCH XCH R1,@RW3+ R1, addr16 XCH XCH R2,@RW3+ R2, addr16 XCH XCH R3,@RW3+ R3, addr16 XCH XCH R4,@RW3+ R4, addr16 XCH XCH R5,@RW3+ R5, addr16 XCH XCH R6,@RW3+ R6, addr16 XCH XCH R7,@RW3+ R7, addr16 +E R0,@RW2+ @PC+d16 R1,@RW2+ @PC+d16 R2,@RW2+ @PC+d16 R3,@RW2+ @PC+d16 R4,@RW2+ @PC+d16 R5,@RW2+ @PC+d16 R6,@RW2+ @PC+d16 R7,@RW2+ @PC+d16 R0, XCH XCH R0, XCH XCH R1, XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, @RW1+RW7 R1,@RW1+ @RW1+RW7 R2,@RW1+ @RW1+RW7 R3,@RW1+ @RW1+RW7 R4,@RW1+ @RW1+RW7 R5,@RW1+ @RW1+RW7 R6,@RW1+ @RW1+RW7 R7,@RW1+ @RW1+RW7 +D R0,@RW1+ XCH XCH R0, XCH XCH R1, XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, @RW0+RW7 R1,@RW0+ @RW0+RW7 R2,@RW0+ @RW0+RW7 R3,@RW0+ @RW0+RW7 R4,@RW0+ @RW0+RW7 R5,@RW0+ @RW0+RW7 R6,@RW0+ @RW0+RW7 R7,@RW0+ @RW0+RW7 XCH +C R0,@RW0+ +B R0,@RW3 @RW3+d16 R1,@RW3 @RW3+d16 R2,@RW3 @RW3+d16 R3,@RW3 @RW3+d16 R4,@RW3 @RW3+d16 R5,@RW3 @RW3+d16 R6,@RW3 @RW3+d16 R7,@RW3 @RW3+d16 R0, +A R0,@RW2 W2+d16, A R0, XCH XCH R0, XCH XCH R1, XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R0,@RW1 @RW1+d16 R1,@RW1 @RW1+d16 R2,@RW1 @RW1+d16 R3,@RW1 @RW1+d16 R4,@RW1 @RW1+d16 R5,@RW1 @RW1+d16 R6,@RW1 @RW1+d16 R7,@RW1 @RW1+d16 +9 XCH XCH XCH R0, XCH XCH R1, XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R0,@RW0 @RW0+d16 R1,@RW0 @RW0+d16 R2,@RW0 @RW0+d16 R3,@RW0 @RW0+d16 R4,@RW0 @RW0+d16 R5,@RW0 @RW0+d16 R6,@RW0 @RW0+d16 R7,@RW0 @RW0+d16 +8 XCH XCH XCH R0, XCH XCH R1, XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R0, R7 @RW7+d8 R1, R7 @RW7+d8 R2, R7 @RW7+d8 R3, R7 @RW7+d8 R4, R7 @RW7+d8 R5, R7 @RW7+d8 R6, R7 @RW7+d8 R7, R7 @RW7+d8 F0 +7 E0 XCH XCH R0, XCH XCH R1, XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R0, R6 @RW6+d8 R1, R6 @RW6+d8 R2, R6 @RW6+d8 R3, R6 @RW6+d8 R4, R6 @RW6+d8 R5, R6 @RW6+d8 R6, R6 @RW6+d8 R7, R6 @RW6+d8 D0 +6 C0 XCH XCH R0, XCH XCH R1, XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R0, R5 @RW5+d8 R1, R5 @RW5+d8 R2, R5 @RW5+d8 R3, R5 @RW5+d8 R4, R5 @RW5+d8 R5, R5 @RW5+d8 R6, R5 @RW5+d8 R7, R5 @RW5+d8 B0 +5 A XCH XCH R0, XCH XCH R1, XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R0, R4 @RW4+d8 R1, R4 @RW4+d8 R2, R4 @RW4+d8 R3, R4 @RW4+d8 R4, R4 @RW4+d8 R5, R4 @RW4+d8 R6, R4 @RW4+d8 R7, R4 @RW4+d8 90 +4 80 XCH XCH R0, XCH XCH R1, XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R0, R3 @RW3+d8 R1, R3 @RW3+d8 R2, R3 @RW3+d8 R3, R3 @RW3+d8 R4, R3 @RW3+d8 R5, R3 @RW3+d8 R6, R3 @RW3+d8 R7, R3 @RW3+d8 70 +3 60 XCH XCH R0, XCH XCH R1, XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R0, R2 @RW2+d8 R1, R2 @RW2+d8 R2, R2 @RW2+d8 R3, R2 @RW2+d8 R4, R2 @RW2+d8 R5, R2 @RW2+d8 R6, R2 @RW2+d8 R7, R2 @RW2+d8 50 +2 40 XCH XCH R0, XCH XCH R1, XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R0, R1 @RW1+d8 R1, R1 @RW1+d8 R2, R1 @RW1+d8 R3, R1 @RW1+d8 R4, R1 @RW1+d8 R5, R1 @RW1+d8 R6, R1 @RW1+d8 R7, R1 @RW1+d8 30 +1 20 XCH XCH R0, XCH XCH R1, XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R0, R0 @RW0+d8 R1, R0 @RW0+d8 R2, R0 @RW0+d8 R3, R0 @RW0+d8 R4, R0 @RW0+d8 R5, R0 @RW0+d8 R6, R0 @RW0+d8 R7, R0 @RW0+d8 10 +0 00 APPENDIX B Instructions Table B.9-20 XCH Ri, ea Instruction (First Byte = 7EH) 539 540 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0,@RW2+ @PC+d16 RW1,@RW2+ @PC+d16 RW2,@RW2+ @PC+d16 RW3,@RW2+ @PC+d16 RW4,@RW2+ @PC+d16 RW5,@RW2+ @PC+d16 RW6,@RW2+ @PC+d16 RW7,@RW2+ @PC+d16 XCHW XCHW RW0,@RW3+ RW0, addr16 +E +F XCHW XCHW RW7,@RW3+ RW7, addr16 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0,@RW1+ @RW1+RW7 RW1,@RW1+ @RW1+RW7 RW2,@RW1+ @RW1+RW7 RW3,@RW1+ @RW1+RW7 RW4,@RW1+ @RW1+RW7 RW5,@RW1+ @RW1+RW7 RW6,@RW1+ @RW1+RW7 RW7,@RW1+ @RW1+RW7 +D XCHW XCHW RW6,@RW3+ RW6, addr16 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0,@RW0+ @RW0+RW7 RW1,@RW0+ @RW0+RW7 RW2,@RW0+ @RW0+RW7 RW3,@RW0+ @RW0+RW7 RW4,@RW0+ @RW0+RW7 RW5,@RW0+ @RW0+RW7 RW6,@RW0+ @RW0+RW7 RW7,@RW0+ @RW0+RW7 +C XCHW XCHW RW5,@RW3+ RW5, addr16 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0,@RW3 @RW3+d16 RW1,@RW3 @RW3+d16 RW2,@RW3 @RW3+d16 RW3,@RW3 @RW3+d16 RW4,@RW3 @RW3+d16 RW5,@RW3 @RW3+d16 RW6,@RW3 @RW3+d16 RW7,@RW3 @RW3+d16 +B XCHW XCHW RW4,@RW3+ RW4, addr16 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0,@RW2 @RW2+d16 RW1,@RW2 @RW2+d16 RW2,@RW2 @RW2+d16 RW3,@RW2 @RW2+d16 RW4,@RW2 @RW2+d16 RW5,@RW2 @RW2+d16 RW6,@RW2 @RW2+d16 RW7,@RW2 @RW2+d16 +A XCHW XCHW RW3,@RW3+ RW3, addr16 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0,@RW1 @RW1+d16 RW1,@RW1 @RW1+d16 RW2,@RW1 @RW1+d16 RW3,@RW1 @RW1+d16 RW4,@RW1 @RW1+d16 RW5,@RW1 @RW1+d16 RW6,@RW1 @RW1+d16 RW7,@RW1 @RW1+d16 +9 XCHW XCHW RW2,@RW3+ RW2, addr16 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0,@RW0 @RW0+d16 RW1,@RW0 @RW0+d16 RW2,@RW0 @RW0+d16 RW3,@RW0 @RW0+d16 RW4,@RW0 @RW0+d16 RW5,@RW0 @RW0+d16 RW6,@RW0 @RW0+d16 RW7,@RW0 @RW0+d16 +8 XCHW XCHW RW1,@RW3+ RW1, addr16 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0, RW7 @RW7+d8 RW1, RW7 @RW7+d8 RW2, RW7 @RW7+d8 RW3, RW7 @RW7+d8 RW4, RW7 @RW7+d8 RW5, RW7 @RW7+d8 RW6, RW7 @RW7+d8 RW7, RW7 @RW7+d8 F0 +7 E0 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0, RW6 @RW6+d8 RW1, RW6 @RW6+d8 RW2, RW6 @RW6+d8 RW3, RW6 @RW6+d8 RW4, RW6 @RW6+d8 RW5, RW6 @RW6+d8 RW6, RW6 @RW6+d8 RW7, RW6 @RW6+d8 D0 +6 C0 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0, RW5 @RW5+d8 RW1, RW5 @RW5+d8 RW2, RW5 @RW5+d8 RW3, RW5 @RW5+d8 RW4, RW5 @RW5+d8 RW5, RW5 @RW5+d8 RW6, RW5 @RW5+d8 RW7, RW5 @RW5+d8 B0 +5 A0 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0, RW4 @RW4+d8 RW1, RW4 @RW4+d8 RW2, RW4 @RW4+d8 RW3, RW4 @RW4+d8 RW4, RW4 @RW4+d8 RW5, RW4 @RW4+d8 RW6, RW4 @RW4+d8 RW7, RW4 @RW4+d8 90 +4 80 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0, RW3 @RW3+d8 RW1, RW3 @RW3+d8 RW2, RW3 @RW3+d8 RW3, RW3 @RW3+d8 RW4, RW3 @RW3+d8 RW5, RW3 @RW3+d8 RW6, RW3 @RW3+d8 RW7, RW3 @RW3+d8 70 +3 60 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0, RW2 @RW2+d8 RW1, RW2 @RW2+d8 RW2, RW2 @RW2+d8 RW3, RW2 @RW2+d8 RW4, RW2 @RW2+d8 RW5, RW2 @RW2+d8 RW6, RW2 @RW2+d8 RW7, RW2 @RW2+d8 50 +2 40 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0, RW1 @RW1+d8 RW1, RW1 @RW1+d8 RW2, RW1 @RW1+d8 RW3, RW1 @RW1+d8 RW4, RW1 @RW1+d8 RW5, RW1 @RW1+d8 RW6, RW1 @RW1+d8 RW7, RW1 @RW1+d8 30 +1 20 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0, RW0 @RW0+d8 RW1, RW0 @RW0+d8 RW2, RW0 @RW0+d8 RW3, RW0 @RW0+d8 RW4, RW0 @RW0+d8 RW5, RW0 @RW0+d8 RW6, RW0 @RW0+d8 RW7, RW0 @RW0+d8 10 +0 00 APPENDIX B Instructions Table B.9-21 XCHW RWi, ea Instruction (First Byte = 7FH) INDEX INDEX The index follows on the next page. This is listed in alphabetic order. 541 INDEX Index Numerics 16-bit free-run timer (x 1)...................................... 216 16-bit free-run timer count timing ......................... 232 16-bit free-run timer operations ............................ 231 16-bit I/O timer block diagram .............................. 218 16-bit I/O timer registers....................................... 219 16-bit input capture operations............................. 236 16-bit output compare operations ........................ 233 16-bit output compare timing................................ 234 16-bit reload register (TMRLR)............................. 245 16-bit reload timer (with event count function), block diagram of......................................... 240 16-bit reload timer (with event count function), overview of ................................................ 240 16-bit reload timer (with event count function), register of .................................................. 241 16-bit timer register (TMR) ................................... 245 1M-bit flash memory program, of example........... 451 1M-bit flash memory sector configuration of ........ 427 1M-bit flash memory, feature of............................ 426 8/16-bit PPG interrupt .......................................... 264 8/16-bit PPG operation......................................... 264 8/16-bit PPG operation modes ............................. 266 8/16-bit PPG, block diagram of ............................ 253 8/16-bit PPG, overview of .................................... 252 8/16-bit PPG, register in ....................................... 255 A A/D converter block diagram ................................ 290 A/D converter, caution on using ........................... 289 A/D converter, overview of ................................... 288 A/D converter, registers of ................................... 291 access mode ........................................................ 128 accumulator (A) ...................................................... 35 acknowledgment bit ............................................. 401 ADB, additional bank register................................. 30 ADCR1 and ADCR2 ............................................. 297 ADCS1 and ADCS2 ............................................. 292 additional bank register(ADB) ................................ 30 address match detection function, block diagram of......................................... 414 address match detection function, operation of ................................................................... 417 address match detection function, system configuration example of ........................... 418 542 Addressing ........................................................... 482 ADER ................................................................... 158 arbitration ............................................................. 391 ARSR ................................................................... 136 automatic ready function selection register (ARSR) ................................................................... 136 avoiding being subject to the notes........................ 52 B bank method, addressing by.................................. 29 bank registers ........................................................ 43 bank selection prefixes .......................................... 46 BAP........................................................................ 76 basic configuration of MB90F583C/CA serial programming connection ........................... 458 bit format .............................................................. 407 block diagram for IEBusTM controller................... 347 block diagram for MB90580C series........................ 6 broadcast ............................................................. 392 broadcast bit ........................................................ 394 broadcast control bit read register (DCRR).......... 367 broadcast control bit set register (DCWR) ........... 353 broadcast reception ............................................. 375 broadcast reception (occurrence of reception interrupt) ................................................... 378 buffer address pointer (BAP) ................................. 76 bus control signal selection register (ECSR) ....... 139 bus mode ............................................................. 128 C Calculating the Execution Cycle Count................ 499 calculating pulse width/period .............................. 206 caution on using the A/D converter...................... 289 CCR ....................................................................... 38 CDCR................................................................... 316 characteristic of PWC timer ................................. 180 chip deletion, deleting the data from the flash memory ................................................................... 446 CKSCR .................................................................. 97 clearing the timer ................................................. 201 CLK-bsynchronous mode, values set in registers in ................................................................... 339 clock division control register (CDCR) ................. 316 clock generator, notes as to................................... 84 clock monitor functions, block diagram of ............ 410 INDEX clock output permission register (CLKR) ............. 411 clock selection bits ............................................... 213 clock selection register (CKSCR)........................... 97 CMR....................................................................... 47 CMRH .................................................................. 356 CMRL................................................................... 358 command register (higher 8 bits) (CMRH) ........... 356 command register (lower 8 bits) (CMRL) ............. 358 command sequence table.................................... 430 common register bank prefix (CMR) ...................... 47 communication address ....................................... 392 communication modes ......................................... 391 communication prescaler ..................................... 334 communication prescaler, operation of ................ 318 communication, end of......................................... 339 communication, start of........................................ 339 compare register (OCCP0 and OCCP1).............. 225 condition code register (CCR)................................ 38 continuous measurement mode........................... 205 control field........................................................... 397 control status registers (ADCS1 and ADCS2) ..... 292 control status register (FMCS) ............................. 428 control status registers (ICS23 and ICS01) ......... 229 control status register (OCS0 to OCS1)............... 226 conversion data protection function ..................... 307 count clock and maximum period ........................ 203 count clock selection............................................ 197 count clock, notes on selecting ............................ 269 counter operation statuses................................... 250 CPU operation function, intermittent .................... 107 D D/A control registers (DACR0 and DACR1)......... 313 D/A converter block diagram................................ 311 D/A converter data registers (DAT0 and DAT1) ................................................................... 312 D/A converter registers ........................................ 310 D/A converter, operation of .................................. 314 DACR0 and DACR1............................................. 313 DAT0 and DAT1................................................... 312 data bank register (DTB)........................................ 30 data counter (DCT) ................................................ 74 data field .............................................................. 399 data polling flag (DQ7) ......................................... 434 data registers (ADCR1 and ADCR2) ................... 297 DCRR................................................................... 367 DCT........................................................................ 74 DCWR.................................................................. 353 DDRx ................................................................... 154 dedicated registers .................................................33 delayed interrupt generating module (DIRR), register in....................................................284 delayed interrupt generating module, block diagram of ................................................................284 delayed interrupt generating module, operation of ................................................285 delayed interrupt request latch, note on use of ...................................................................285 deleting data for the flash memory .......................426 DERR ...................................................................368 Description of Instruction Presentation Items and Symbols......................................................502 determining the priority for using the bus (arbitration) ................................................391 DEWR...................................................................355 Direct Addressing .................................................484 direct page register (DPR) ......................................42 DIRR.....................................................................284 DIV A, Ri instruction ...............................................51 division rate control register (DIVR)......................191 DIVR .....................................................................191 DIVW A, RWi instruction.........................................51 DPR ........................................................................42 DQ3 ......................................................................439 DQ5 ......................................................................438 DQ6 ......................................................................436 DQ7 ......................................................................434 DTB, data bank register..........................................30 DTP operation ......................................................278 DTP request .........................................................280 DTP/external interrupt circuit operation procedure ...................................................281 DTP/external interrupt circuit, block diagram of ...................................................................275 DTP/external interrupt circuit, registers in ............274 DTP/external interrupt enable register (ENIR)......276 DTP/external interrupt source register (EIRR)......276 dvision period measurement mode ......................213 E each bus mode, memory space for ......................131 each bus mode, recommended setting sample of memory space for......................................132 ECSR....................................................................139 Effective Address Field.................................483, 501 EI2OS activation in pause mode, example of .......305 EI2OS activation in single mode, example of .......301 EI2OS activation in successive mode, example of..................................................303 543 INDEX EI2OS status register (ISCS).................................. 74 EI2OS, conversion with ........................................ 300 EIRR..................................................................... 276 ENIR..................................................................... 276 entire flash memory, block diagram of ................. 427 error, transmission operation at occurrence of..... 388 example of program patch processing ................. 419 Execution Cycle Count ......................................... 498 expanded intelligent I/O service (EI2OS), configuration of ........................................... 69 expanded intelligent I/O service (EI2OS), execution time of .......................................... 79 expanded intelligent I/O service (EI2OS), operational flow of ........................................ 77 expanded intelligent I/O service (EI2OS), overview of ................................................... 68 expanded intelligent I/O service descriptor (ISD) ..................................................................... 73 extended intelligent I/O service (EI2OS)............... 333 extended intelligent I/O service (EI2OS) function and interrupts ............................................. 247 external address output control register (HACR) ................................................................... 138 external bus pin control circuit, block diagram of external memory access ............................ 134 external bus pin control circuit, registers for external memory access .......................................... 135 external clock ....................................................... 335 external event count ............................................. 246 external interrupt operation .................................. 278 external interrupt request and a DTP request, switching between...................................... 280 external interrupt request level ............................. 282 external memory access (external bus pin control circuit) ................ 134 external memory access (external bus pin control circuit), block diagram of ........................... 134 external memory access (external bus pin control circuit), registers for .................................. 135 external memory access control signal ................ 142 flash memory, writing data in ............................... 444 flash microcomputer programmer (when power is supplied from a programmer), example of minimum connection with ......................... 468 flash microcomputer programmer (when user power supply is used), example of minimum connection with .......................................... 466 flash microcomputer programmer, of system configuration ............................................. 461 flowchart of pulse-width measurement operation ................................................................... 211 flowchart of timer mode operation........................ 204 FMCS................................................................... 428 FPT-100P-M05 package, outside dimensions of ..... 7 FPT-100P-M06 package, outside dimensions of ..... 8 FTP-100P-M05, pin layout of ................................... 9 FTP-100P-M06, pin layout of ................................. 10 G general-purpose registers ...................................... 44 group broadcast ................................................... 392 H HACR................................................................... 138 hardware components, initial value in.................. 265 hardware interrupt request during writing to the internal resource area................................. 60 hardware interrupts, example of procedure for using ....................................................... 65 hardware interrupts, notes on the use of ............... 61 hardware interrupts, operating flow for .................. 64 hardware interrupts, operation of ........................... 62 hardware interrupts, overview of............................ 59 hardware interrupts, structure of ............................ 59 hardware sequence flag....................................... 432 hardware standby mode, releasing...................... 106 hardware standby mode, transition to.................. 106 hold function......................................................... 146 I F F2MC-16LX Instruction List .................................. 505 features of IEBusTM controller.............................. 346 features of MB90580C series................................... 2 five flags (PE, ORE, FRE, RDRF, and TDRE) ..... 340 flag change suppression prefix (NCC) ................... 48 flash memory register........................................... 426 flash memory writing and deletion, detailed explanation of............................................ 442 544 I (interrupt enable flag)........................................... 38 I/O circuit types ...................................................... 19 I/O map ................................................................ 472 I/O port block diagram.......................................... 149 I/O port overview.................................................. 148 I/O port registers .................................................. 151 I/O register address pointer (IOA).......................... 74 ICR......................................................................... 70 ICS23 and ICS01 ................................................. 229 INDEX IEBusTM controller, block diagram for .................. 347 IEBusTM controller, features of ............................ 346 IEBusTM controller, registers of............................ 348 IEBusTM protocol operation, overview of ............. 390 iInput pull-up resistor setting registers (RDR0, RDR1, and RDR6)................................................. 157 ILM ......................................................................... 40 Indirect Addressing .............................................. 490 initialization .......................................................... 216 initialization routine .............................................. 380 initializing the machine clock................................ 110 input capture (x 4) ................................................ 217 input capture data register (IPCP0 to IPCP3) ...... 229 input capture input timing..................................... 237 input pin function (for the internal clock mode) .... 248 Instruction Types.................................................. 481 internal clock operations ...................................... 246 internal timer ........................................................ 334 interrupts, Extended Intelligent I/O Service (EI2OS) function and .............................................. 247 interrupt causes ..................................................... 55 interrupt control register (ICR) ............................... 70 interrupt enable flag (I)........................................... 38 interrupt flag setting timing in operating modes ................................................................... 340 interrupt level mask register (ILM) ......................... 40 interrupt processing routine ................................. 379 interrupt request generation......................... 202, 207 interrupt stop instruction......................................... 60 interrupt suppression instructions .......................... 49 interrupt suppression instruction, restrictions on ..................................................................... 49 interrupt vectors ..................................................... 57 Interrupts, overview of............................................ 54 interval interrupt function.............................. 164, 178 IOA......................................................................... 74 IPCP0 to IPCP3 ................................................... 229 ISCS....................................................................... 74 ISD ......................................................................... 73 L linear addressing methods..................................... 29 local address set registers (MAWH and MAWL) ................................................................... 351 lock address and slave status , transmission of ................................................................... 373 lock address, reading the..................................... 406 lock read registers (LRRH and LRRL) ................. 365 locking and unlocking........................................... 406 low power-consumption mode, status transition in ...................................................................119 low-power consumption control circuit, block diagram of ...........................................94 low-power consumption control circuit, operation of ................................................100 low-power consumption control circuit, overview of .....................................................................92 low-power consumption mode control register (LPMCR) .....................................................95 LPMCR ...................................................................95 LRRH and LRRL...................................................365 M machine clock, initializing .....................................110 main and PLL clocks, switching between .............109 main clock and subclock, switching between .......109 main clock, setting the oscillation stabilization time for .......................................................108 main routine..........................................................379 master address field .............................................395 master address read registers (MARH and MARL) ...................................................................366 master or slave transmission (occurrence of transmission interrupt) ...............................376 master reception...................................................374 master reception (occurrence of reception interrupt) .............376 master reception routine.......................................383 master transmission .............................................371 master transmission routine .................................381 MAWH and MAWL ...............................................351 MB90580C series, block diagram for .......................6 MB90580C series, features of ..................................2 MB90F583C/CA serial programming connection, basic configuration of ................................458 measurement mode and measurement operation ...................................................................208 measurement result data......................................205 measurement termination flag in timer mode .......212 memory access mode overview ...........................128 memory space ........................................................28 memory space for each bus mode, recommended setting sample of .......................................132 memory space, allocating multiple-byte data in......32 minimum input pulse width ...........................206, 213 mode 1), application of UART (during operation in ...................................................................343 mode data.............................................................130 545 INDEX mode is changed, PWCR and timer values when ................................................................... 213 mode pin setting and corresponding modes ........ 129 models available ...................................................... 5 multiple interrupts ................................................... 60 multiple-byte data, access of.................................. 32 N N (negative flag) ..................................................... 38 NCC ....................................................................... 48 negative flag (N) ..................................................... 38 notes on the reception of control bits from master unit ................................................. 372 O OCCP0 and OCCP1 ............................................ 225 OCS0 to OCS1..................................................... 226 ODR4 ................................................................... 156 one-shot operation mode ..................................... 202 operating mode .................................................... 128 operations ............................................................ 178 operation mode selection ..................................... 198 operation of communication prescaler ................. 318 operation of D/A converter ................................... 314 oscillation clock frequency ................................... 460 output compare (x 2) ............................................ 216 output pin function ................................................ 249 outside dimensions of FPT-100P-M05 package ...... 7 outside dimensions of FPT-100P-M06 package ...... 8 overflow flag (V) ..................................................... 39 overview of IEBusTM protocol operation............... 390 P PACSR ................................................................. 415 PADR0 and PADR1 ............................................. 415 parity bit................................................................ 400 pause mode ......................................................... 300 pause mode, example of EI2OS activation in....... 305 PC .......................................................................... 41 PCB, program bank register................................... 30 PDRx .................................................................... 153 peripheral devices connected externally when DTP is used, Conditions of................................. 281 pin functions ........................................................... 11 pin layout of FTP-100P-M05 .................................... 9 pin layout of FTP-100P-M06 .................................. 10 port 4 output pin register (ODR4) ......................... 156 port data direction register (DDRx)....................... 154 port data register (PDRx) ..................................... 153 546 ports 5 analog input enable register (ADER) ....... 158 PPG output operation .......................................... 267 PPG0 operation mode control register (PPGC0) ................................................................... 256 PPG0/1 output pin control register (PPGOE)....... 261 PPG1 operation mode control register (PPGC1) ................................................................... 258 PPGOE ................................................................ 261 precautions on the handling of the device ............. 22 prefix codes, in the case of consecutive ................ 50 prefix instructions, restrictions on........................... 49 PRLL/PRLH ......................................................... 263 processor status (PS) ............................................ 38 program address detection control status register (PACSR) ................................................... 415 program address detection registers (PADR0 and PADR1) ................................ 415 program bank register, PCB .................................. 30 program counter (PC) ............................................ 41 program patch processing, example of................ 419 PS .......................................................................... 38 pseudo watch mode, releasing ............................ 103 pseudo watch mode, transition to ........................ 103 pulse output on pins, controlling .......................... 270 pulse width, relationship between the reloaded value and .................................................. 268 pulse width/period measurement range............... 207 pulse-width measurement and starting and stopping timer ............................................ 200 pulse-width measurement function ...................... 195 pulse-width measurement mode using continuous measurement mode.................................. 214 pulse-width measurement operation, flowchart of ................................................ 211 PWC control status register (PWCSR) ................ 184 PWC data buffer register (PWCR) ....................... 190 PWC noise filter register (RNCR) ........................ 192 PWC timer block diagram .................................... 181 PWC timer operation............................................ 180 PWC timer registers............................................. 182 PWC timer, characteristics of............................... 180 PWCR .................................................................. 190 PWCR and timer values when the mode is changed ................................................. 213 PWCSR................................................................ 184 PWCSR, STRT and STOP bits of........................ 212 R RDB ..................................................................... 369 RDR0, RDR1 and RDR6...................................... 157 INDEX read data buffer (RDB)......................................... 369 read, flash memory .............................................. 443 reading slave status (SSR) .................................. 404 reading the lock address...................................... 406 ready function ...................................................... 144 receiver operation ................................................ 336 reception of control bits from master unit, notes on ................................................................... 372 register banks ........................................................ 45 register bank pointer (RP)...................................... 39 register of IEBusTM controller .............................. 348 register value change........................................... 212 releasing the pseudo watch mode ....................... 103 reload operation mode ......................................... 202 reload registers (PRLL/PRLH) ............................. 263 reload registers, write timing for........................... 271 reloaded value and pulse width, relationship between.................................. 268 request level setting register (ELVR) ................... 277 reset causes........................................................... 85 reset input, registers not initialized by.................... 88 reset is released, operation after ........................... 87 reset status, flash memory................................... 443 restart during operation........................................ 213 RNCR................................................................... 192 ROM mirror function selection module, block diagram of ........................................ 422 ROM mirror function selection register (ROMM) ................................................................... 423 RP .......................................................................... 39 S S............................................................................. 38 saving a register to the stack ................................. 61 SAWH and SAWL ................................................ 352 SCR0 to 4 ............................................................ 326 sector configuration of the 1M-bit flash memory ................................................................... 427 sector deletion from the flash memory, temporarily stopping .................................. 449 sector deletion timer flag (DQ3) ........................... 439 Sector Deletion, flash memory from which any data item is deleted............................................ 447 sector deletion, restarting the flash memory ........ 450 sector from the flash memory, procedure for deleting ................................................................... 447 serial clock input frequency.................................. 460 serial control register (SCR0 to 4)........................ 326 serial input data register (SIDR0 to 4), configuration of...........................................329 serial mode register (SMR0 to 4)..........................323 serial output data register (SODR0 to 4) ..............329 serial programming connection (when power is supplied from a programmer), example of ...................................................................464 serial programming connection (when user power supply is used), example of.......................462 serial status register (SSR0 to 4)..........................330 setting the oscillation stabilization time for the main clock ..........................................................108 SIDR0 to 4 ............................................................329 single measurement mode ...................................205 single measurement mode and continuous measurement mode ..................................205 single mode ..........................................................299 single mode, example of EI2OS activation in .......301 slave address field................................................396 slave address set registers (SAWH and SAWL) ...................................................................352 slave data transmission routine ............................382 slave reception .....................................................374 slave reception (occurrence of reception interrupt) .............377 slave status and lock Address, transmission of ...................................................................373 slave transmission ................................................372 sleep mode, releasing ..........................................102 sleep mode, transition to ......................................102 SMR0 to 4.............................................................323 SODR0 to 4 ..........................................................329 software interrupts, notes on ..................................67 software interrupts, operation of .............................66 software interrupt, overview of................................66 software interrupt, structure of................................66 SSB, system stack bank register ............................30 SSP ........................................................................37 SSR ......................................................................404 SSR0 to 4 .............................................................330 stack flag (S)...........................................................38 standby state, return from.....................................281 start bit..................................................................394 starting and stopping timer and pulse-width measurement ............................................200 status register (higher 8 bits) (STRH) ...................361 status register (lower 8 bits) (STRL) .....................363 status transition ....................................................113 status transition in the low-power consumption mode (one clock system) ....................................124 547 INDEX status transition in the low power-consumption mode (two clocks system).................................... 119 sticky bit flag (T) ..................................................... 38 stop mode, releasing ............................................ 105 stop mode, transition to ........................................ 105 STRH ................................................................... 361 STRL .................................................................... 363 STRT and STOP bits of PWCSR ......................... 212 Structure of Instruction Map ................................. 519 successive mode.................................................. 299 successive mode, example of EI2OS activation in ............................................... 303 switching between the main and PLL clocks........ 109 switching between the main clock and subclock ................................................................... 109 system stack bank register (SSB) .......................... 30 system stack pointer (SSP) .................................... 37 T T ............................................................................. 38 TBTC .................................................................... 162 TCDTH and TCDTL.............................................. 221 text length bit set register (DEWR)....................... 355 text length bit read register (lower 8 bit) (DERR) ................................................................... 368 text length field ..................................................... 398 the device, precaution on the handling of .............. 22 time-based timer block diagram ........................... 161 time-based timer control register (TBTC) ............. 162 time-based timer operations................................. 164 time-based timer register...................................... 160 timer clear ............................................................ 213 timer control status register (TCCS)..................... 222 timer control status register (TMCSR).................. 242 timer data register (TCDTH and TCDTL) ............. 221 timer function........................................................ 194 timer mode operation, flowchart of ....................... 204 timer mode, measurement termination flag in ...... 212 timer period .......................................................... 203 timer value and reload value ................................ 202 timing limit excess flag (DQ5)............................... 438 TMCSR ................................................................ 242 TMR, 16-bit timer register..................................... 245 TMRLR, 16-bit reload register .............................. 245 toggle bit 2 flag (DQ2) .......................................... 440 toggle bit flag (DQ6) ............................................. 436 transfer data format ...................................... 336, 338 transferring data or commands ............................ 405 transition to the pseudo watch mode ................... 103 548 transmission data................................................. 403 transmission of slave status and lock Address .... 373 transmission operation at occurrence of error ..... 388 transmission operation over multiple frames ....... 386 transmission protocol ........................................... 393 transmitter operation ............................................ 337 two interrupt sources............................................ 340 U UART (during operation in mode 1), application of ................................................................... 343 UART block diagram............................................ 321 UART operations ................................................. 333 UART register ...................................................... 322 UART,feature of ................................................... 320 undefined instruction, occurrence of exceptions because of executing.................................. 81 underflow operation ............................................. 247 USB, user stack bank register ............................... 30 user power supply is used, example of minimum connection with flash microcomputer programmer .............................................. 466 user power supply is used, example of serial programming connection .......................... 462 user stack bank register, USB ............................... 30 user stack pointer (USP)........................................ 37 USP........................................................................ 37 V V............................................................................. 39 values set in register in the CLK-synchronous mode ................................................................... 339 W watch mode, releasing ......................................... 104 watch mode, transition to ..................................... 104 watch timer block diagram ................................... 175 watch timer control register.................................. 174 watch timer control register (WTC) ...................... 176 watchdog timer block diagram ............................. 167 watchdog timer control register (WDTC).............. 168 watchdog timer register........................................ 166 watchdog timer reset, preventing......................... 171 watchdog timer, activating ................................... 171 watchdog timer, clearing ...................................... 171 watchdog, stopping .............................................. 171 WDB..................................................................... 370 WDTC .................................................................. 168 write data buffer (WDB) ....................................... 370 INDEX writing data for flash memory............................... 426 writing data in flash memory, procedure for......... 444 WTC..................................................................... 176 Z Z .............................................................................39 zero flag (Z) ............................................................39 549 INDEX 550 CM44-10111-3E FUJITSU MICROELECTRONICS • CONTROLLER MANUAL F2MCTM-16LX 16-BIT MICROCONTROLLER MB90580C Series HARDWARE MANUAL July 2008 the 3rd edition Published FUJITSU MICROELECTRONICS LIMITED Edited Business & Media Promotion Dept.