FUJITSU SEMICONDUCTOR CM44-10136-1E CONTROLLER MANUAL 2 TM F MC -16LX 16-BIT MICROCONTROLLER MB90360 Series HARDWARE MANUAL F2MCTM-16LX 16-BIT MICROCONTROLLER MB90360 Series HARDWARE MANUAL FUJITSU LIMITED PREFACE ■ Objectives and intended reader Thank you very much for your continued patronage of Fujitsu semiconductor products. The MB90360 series has been developed as a general-purpose version of the F2MC-16LX family, which is an original 16-bit single-chip microcontroller compatible with the Application Specific IC (ASIC). This manual explains the functions and operation of the MB90360 series for engineers who actually use the MB90360 series to design products. Please read this manual first. ■ Trademark F2MC, an abbreviation of FUJITSU Flexible Microcontroller, is a registered trademark of FUJITSU Ltd. Embedded Algorithm is a registered trademark of Advanced Micro Devices Inc. ■ Structure of this preliminary manual This manual contains the following 26 chapters and appendix. CHAPTER 1 OVERVIEW The MB90360 Series is a family member of the F2MC-16LX micro controllers. CHAPTER 2 CPU This chapter explains the CPU. CHAPTER 3 INTERRUPTS This chapter explains the interrupts and function and operation of the extended intelligent I/O service in the MB90360 series. CHAPTER 4 DELAYED INTERRUPT GENERATION MODULE This chapter explains the functions and operations of the delayed interrupt generation module. CHAPTER 5 CLOCKS This chapter explains the clocks used by MB90360 series microcontrollers. CHAPTER 6 CLOCK SUPERVISOR This chapter explains the function and the operation of the clock supervisor. Only the product with built-in clock supervisor of the MB90360 series is valid to this function. CHAPTER 7 RESETS This chapter describes resets for the MB90360-series microcontrollers. CHAPTER 8 LOW-POWER CONSUMPTION MODE This chapter explains the low-power consumption mode of MB90360 series microcontrollers. CHAPTER 9 MEMORY ACCESS MODES This chapter explains the functions and operations of the memory access modes. i CHAPTER 10 I/O PORTS This chapter explains the functions and operations of the I/O ports. CHAPTER 11 TIMEBASE TIMER This chapter explains the functions and operations of the timebase timer. CHAPTER 12 WATCHDOG TIMER This chapter describes the function and operation of the watchdog timer. CHAPTER 13 16-Bit I/O TIMER This chapter explains the function and operation of the 16- bit I/O timer. CHAPTER 14 16-BIT RELOAD TIMER This chapter describes the functions and operation of the 16-bit reload timer. CHAPTER 15 WATCH TIMER This chapter describes the functions and operations of the watch timer. CHAPTER 16 8-/16-BIT PPG TIMER This chapter describes the functions and operations of the 8-/16-bit PPG timer. CHAPTER 17 DTP/EXTERNAL INTERRUPTS This chapter explains the functions and operations of DTP/external interrupt. CHAPTER 18 8-/10-BIT A/D CONVERTER This chapter explains the functions and operation of 8-/10-bit A/D converter. CHAPTER 19 LOW VOLTAGE DETECTION/CPU OPERATING DETECTION RESET This chapter explains the function and operating the low voltage detection/CPU operating detection reset. This function can use only the product with "T" suffix of MB90360 series. CHAPTER 20 LIN-UART This chapter explains the functions and operation of LIN-UART. CHAPTER 21 CAN CONTROLLER This chapter explains the functions and operations of the CAN controller. CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION This chapter explains the address match detection function and its operation. CHAPTER 23 ROM MIRRORING MODULE This chapter describes the functions and operations of the ROM mirroring function select module. CHAPTER 24 512K-BIT FLASH MEMORY This chapter explains the functions and operation of the 512K-bit flash memory. The following three methods are available for writing data to and erasing data from the flash memory: • Parallel programmer • Serial programmer • Executing programs to write/erase data This chapter explains “Executing programs to write/erase data”. ii CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION This chapter shows an example of a serial programming connection using the AF220/AF210/ AF120/AF110 Flash Micro-computer Programmer by Yokogawa Digital Computer Corporation when the AF220/AF210/AF120/AF110 flash serial microcontroller programer from Yokogawa Digital Computer Corporation is used. CHAPTER 26 ROM SECURITY FUNCTION This chapter explains the ROM security function. APPENDIX The appendixes provide I/O maps, instructions, and other information. iii • • • • • • The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party' s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. ©2005 FUJITSU LIMITED Printed in Japan iv CONTENTS CHAPTER 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 CHAPTER 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.7.1 2.7.2 2.7.3 2.7.4 2.8 2.9 2.10 2.11 CPU ............................................................................................................ 27 Outline of the CPU ............................................................................................................................ Memory Space .................................................................................................................................. Memory Map ..................................................................................................................................... Linear Addressing ............................................................................................................................. Bank Addressing Types .................................................................................................................... Multi-byte Data in Memory Space ..................................................................................................... Registers ........................................................................................................................................... Accumulator (A) ........................................................................................................................... User Stack Pointer (USP) and System Stack Pointer (SSP) ....................................................... Processor Status (PS) ................................................................................................................. Program Counter (PC) ................................................................................................................. Register Bank ................................................................................................................................... Prefix Codes ..................................................................................................................................... Interrupt Disable Instructions ............................................................................................................ Precautions for Use of "DIV A, Ri" and "DIVW A, RWi" Instructions ................................................ CHAPTER 3 3.1 3.2 3.3 3.4 3.5 3.5.1 3.5.2 3.5.3 3.6 3.7 3.7.1 3.7.2 3.8 3.9 OVERVIEW ................................................................................................... 1 Overview of MB90360 ........................................................................................................................ 2 Block Diagram of MB90360 series ..................................................................................................... 9 Package Dimensions ........................................................................................................................ 12 Pin Assignment ................................................................................................................................. 13 Pin Functions .................................................................................................................................... 14 Input-Output Circuits ......................................................................................................................... 17 Handling Device ................................................................................................................................ 21 28 29 32 33 34 36 37 40 41 42 45 46 48 51 52 INTERRUPTS ............................................................................................. 55 Outline of Interrupts .......................................................................................................................... Interrupt Vector ................................................................................................................................. Interrupt Control Registers (ICR) ...................................................................................................... Interrupt Flow .................................................................................................................................... Hardware Interrupts .......................................................................................................................... Hardware Interrupt Operation ...................................................................................................... Occurrence and Release of Hardware Interrupt .......................................................................... Multiple interrupts ........................................................................................................................ Software Interrupts ........................................................................................................................... Extended Intelligent I/O Service (EI2OS) .......................................................................................... Extended Intelligent I/O Service Descriptor (ISD) ....................................................................... EI2OS Status Register (ISCS) ..................................................................................................... Operation Flow of and Procedure for Using the Extended Intelligent I/O Service (EI2OS) .............. Exceptions ........................................................................................................................................ v 56 59 61 65 67 68 69 71 72 74 76 78 79 82 CHAPTER 4 4.1 4.2 4.3 4.3.1 4.4 4.5 4.6 Overview of Delayed Interrupt Generation Module ........................................................................... Block Diagram of Delayed Interrupt Generation Module .................................................................. Configuration of Delayed Interrupt Generation Module .................................................................... Delayed interrupt request generate/cancel register (DIRR) ........................................................ Explanation of Operation of Delayed Interrupt Generation Module .................................................. Precautions when Using Delayed Interrupt Generation Module ....................................................... Program Example of Delayed Interrupt Generation Module ............................................................. CHAPTER 5 5.1 5.2 5.2.1 5.3 5.4 5.5 5.6 5.7 CLOCK SUPERVISOR ............................................................................. 109 110 111 113 115 RESETS .................................................................................................... 119 Resets ............................................................................................................................................. Reset Cause and Oscillation Stabilization Wait Times ................................................................... External Reset Pin .......................................................................................................................... Reset Operation .............................................................................................................................. Reset Cause Bits ............................................................................................................................ Status of Pins in a Reset ................................................................................................................ CHAPTER 8 8.1 8.2 8.3 8.4 8.5 8.5.1 8.5.2 8.5.3 8.5.4 8.6 8.7 8.8 CLOCKS ..................................................................................................... 91 Overview of Clock Supervisor ......................................................................................................... Block Diagram of Clock Supervisor ................................................................................................ Clock Supervisor Control Register (CSVCR) .................................................................................. Operating Mode of Clock Supervisor .............................................................................................. CHAPTER 7 7.1 7.2 7.3 7.4 7.5 7.6 84 85 86 87 88 89 90 Clocks ............................................................................................................................................... 92 Block Diagram of the Clock Generation Block .................................................................................. 95 Register of Clock Generation Block ............................................................................................. 97 Clock Selection Register (CKSCR) ................................................................................................... 98 PLL/Subclock Control Register (PSCCR) ....................................................................................... 101 Clock Mode ..................................................................................................................................... 103 Oscillation Stabilization Wait Interval .............................................................................................. 107 Connection of an Oscillator or an External Clock to the Microcontroller ......................................... 108 CHAPTER 6 6.1 6.2 6.3 6.4 DELAYED INTERRUPT GENERATION MODULE .................................... 83 120 123 125 126 128 132 LOW-POWER CONSUMPTION MODE ................................................... 133 Overview of Low-Power Consumption Mode .................................................................................. Block Diagram of the Low-Power Consumption Control Circuit ..................................................... Low-Power Consumption Mode Control Register (LPMCR) ........................................................... CPU Intermittent Operation Mode .................................................................................................. Standby Mode ................................................................................................................................. Sleep Mode ............................................................................................................................... Watch Mode .............................................................................................................................. Timebase Timer Mode ............................................................................................................... Stop Mode ................................................................................................................................. Status Change Diagram ................................................................................................................. Status of Pins in Standby Mode and during Hold and Reset .......................................................... Usage Notes on Low-Power Consumption Mode ........................................................................... vi 134 137 139 142 143 145 148 150 152 155 156 157 CHAPTER 9 MEMORY ACCESS MODES .................................................................... 161 9.1 Outline of Memory Access Modes .................................................................................................. 9.1.1 Mode Pins .................................................................................................................................. 9.1.2 Mode Data ................................................................................................................................. 9.1.3 Memory Space in Each Bus Mode ............................................................................................ 162 163 164 165 CHAPTER 10 I/O PORTS ................................................................................................ 167 10.1 I/O Ports .......................................................................................................................................... 10.2 I/O Port Registers ........................................................................................................................... 10.2.1 Port Data Register (PDR) .......................................................................................................... 10.2.2 Port Direction Register (DDR) ................................................................................................... 10.2.3 Pull-up Control Register (PUCR) ............................................................................................... 10.2.4 Analog Input Enable Register (ADER) ...................................................................................... 10.2.5 Input Level Select Register ........................................................................................................ 168 169 170 172 174 175 176 CHAPTER 11 TIMEBASE TIMER ................................................................................... 179 11.1 Overview of Timebase Timer .......................................................................................................... 11.2 Block Diagram of Timebase Timer ................................................................................................. 11.3 Configuration of Timebase Timer ................................................................................................... 11.3.1 Timebase timer control register (TBTC) .................................................................................... 11.4 Interrupt of Timebase Timer ........................................................................................................... 11.5 Explanation of Operations of Timebase Timer Functions ............................................................... 11.6 Precautions when Using Timebase Timer ...................................................................................... 11.7 Program Example of Timebase Timer ............................................................................................ 180 182 184 185 187 188 192 193 CHAPTER 12 WATCHDOG TIMER ................................................................................ 195 12.1 Overview of Watchdog Timer ......................................................................................................... 12.2 Configuration of Watchdog Timer ................................................................................................... 12.3 Watchdog Timer Registers ............................................................................................................. 12.3.1 Watchdog timer control register (WDTC) .................................................................................. 12.4 Explanation of Operations of Watchdog Timer Functions .............................................................. 12.5 Precautions when Using Watchdog Timer ...................................................................................... 12.6 Program Examples of Watchdog Timer .......................................................................................... 196 199 201 202 204 207 208 CHAPTER 13 16-Bit I/O TIMER ...................................................................................... 209 13.1 Overview of 16-bit I/O Timer ........................................................................................................... 13.2 Block Diagram of 16-bit I/O Timer .................................................................................................. 13.2.1 Block Diagram of 16-bit Free-run Timer .................................................................................... 13.2.2 Block Diagram of Input Capture ................................................................................................ 13.3 Configuration of 16-bit I/O Timer .................................................................................................... 13.3.1 Timer Control Status Register (Upper) (TCCSH) ...................................................................... 13.3.2 Timer Control Status Register (Lower) (TCCSL) ....................................................................... 13.3.3 Timer Data Register (TCDT) ..................................................................................................... 13.3.4 Input Capture Control Status Registers (ICS) ........................................................................... 13.3.5 Input Capture Register (IPCP) ................................................................................................... 13.3.6 Input Capture Edge Register (ICE) ............................................................................................ 13.4 Interrupts of 16-bit I/O Timer ........................................................................................................... vii 210 211 213 214 216 217 218 220 221 223 224 227 13.5 13.6 13.7 13.8 Explanation of Operation of 16-bit Free-run Timer ......................................................................... Explanation of Operation of Input Capture ..................................................................................... Precautions when Using 16-bit I/O Timer ....................................................................................... Program Example of 16-bit I/O Timer ............................................................................................. 229 231 233 234 CHAPTER 14 16-BIT RELOAD TIMER ........................................................................... 237 14.1 Overview of the 16-bit Reload Timer .............................................................................................. 14.2 Block Diagram of 16-bit Reload Timer ............................................................................................ 14.3 Configuration of 16-bit Reload Timer .............................................................................................. 14.3.1 Timer Control Status Registers (High) (TMCSR:H) ................................................................... 14.3.2 Timer Control Status Registers (Low) (TMCSR: L) ................................................................... 14.3.3 16-bit Timer Registers (TMR) .................................................................................................... 14.3.4 16-bit Reload Registers (TMRLR) ............................................................................................. 14.4 Interrupts of 16-bit Reload Timer .................................................................................................... 14.5 Explanation of Operation of 16-bit Reload Timer ............................................................................ 14.5.1 Operation in Internal Clock Mode .............................................................................................. 14.5.2 Operation in Event Count Mode ................................................................................................ 14.6 Precautions when Using 16-bit Reload Timer ................................................................................ 14.7 Sample Program of 16-bit Reload Timer ........................................................................................ 238 240 242 245 247 249 250 251 252 254 259 262 263 CHAPTER 15 WATCH TIMER ........................................................................................ 267 15.1 Overview of Watch Timer ............................................................................................................... 15.2 Block Diagram of Watch Timer ....................................................................................................... 15.3 Configuration of Watch Timer ......................................................................................................... 15.3.1 Watch Timer Control Register (WTC) ........................................................................................ 15.4 Watch Timer Interrupt ..................................................................................................................... 15.5 Explanation of Operation of Watch Timer ....................................................................................... 15.6 Program Example of Watch Timer .................................................................................................. 268 270 272 273 275 276 278 CHAPTER 16 8-/16-BIT PPG TIMER .............................................................................. 281 16.1 Overview of 8-/16-bit PPG Timer .................................................................................................... 16.2 Block Diagram of 8-/16-bit PPG Timer ........................................................................................... 16.2.1 Block Diagram for 8-/16-bit PPG Timer C ................................................................................. 16.2.2 Block Diagram of 8-/16-bit PPG Timer D ................................................................................... 16.3 Configuration of 8-/16-bit PPG Timer ............................................................................................. 16.3.1 PPGC Operation Mode Control Register (PPGCC) .................................................................. 16.3.2 PPGD Operation Mode Control Register (PPGCD) .................................................................. 16.3.3 PPGC/D Count Clock Select Register (PPGCD) ....................................................................... 16.3.4 PPG Reload Registers (PRLLC/PRLHC, PRLLD/PRLHD) ........................................................ 16.4 Interrupts of 8-/16-bit PPG Timer .................................................................................................... 16.5 Explanation of Operation of 8-/16-bit PPG Timer ........................................................................... 16.5.1 8-bit PPG Output 2-channel Independent Operation Mode ....................................................... 16.5.2 16-bit PPG Output Operation Mode .......................................................................................... 16.5.3 8+8-bit PPG Output Operation Mode ........................................................................................ 16.6 Precautions when Using 8-/16-bit PPG Timer ................................................................................ viii 282 285 286 288 290 292 294 296 298 299 300 301 304 307 310 CHAPTER 17 DTP/EXTERNAL INTERRUPTS .............................................................. 313 17.1 Overview of DTP/External Interrupt ................................................................................................ 17.2 Block Diagram of DTP/External Interrupt ........................................................................................ 17.3 Configuration of DTP/External Interrupt .......................................................................................... 17.3.1 DTP/External Interrupt Factor Register (EIRR1) ....................................................................... 17.3.2 DTP/External Interrupt Enable Register (ENIR1) ...................................................................... 17.3.3 Detection Level Setting Register (ELVR1) ................................................................................ 17.3.4 External Interrupt Factor Select Register (EISSR) .................................................................... 17.4 Explanation of Operation of DTP/External Interrupt ....................................................................... 17.4.1 External Interrupt Function ........................................................................................................ 17.4.2 DTP Function ............................................................................................................................. 17.5 Precautions when Using DTP/External Interrupt ............................................................................ 17.6 Program Example of DTP/External Interrupt Function ................................................................... 314 315 317 319 321 323 325 327 331 332 333 335 CHAPTER 18 8-/10-BIT A/D CONVERTER .................................................................... 339 18.1 Overview of 8-/10-bit A/D Converter ............................................................................................... 18.2 Block Diagram of 8-/10-bit A/D Converter ...................................................................................... 18.3 Configuration of 8-/10-bit A/D Converter ........................................................................................ 18.3.1 A/D Control Status Register (High) (ADCS1) ............................................................................ 18.3.2 A/D Control Status Register (Low) (ADCS0) ............................................................................. 18.3.3 A/D Data Register (ADCR0/ADCR1) ......................................................................................... 18.3.4 A/D Setting Register (ADSR0/ADSR1) ...................................................................................... 18.3.5 Analog Input Enable Register (ADER5, ADER6) ...................................................................... 18.4 Interrupt of 8-/10-bit A/D Converter ................................................................................................ 18.5 Explanation of Operation of 8-/10-bit A/D Converter ...................................................................... 18.5.1 Single-shot Conversion Mode ................................................................................................... 18.5.2 Continuous Conversion Mode ................................................................................................... 18.5.3 Pause-conversion Mode ............................................................................................................ 18.5.4 Conversion Using EI2OS Function ............................................................................................ 18.5.5 A/D-converted Data Protection Function ................................................................................... 18.6 Precautions when Using 8-/10-bit A/D Converter ........................................................................... 340 341 344 346 349 351 352 356 358 359 360 362 364 366 367 369 CHAPTER 19 LOW VOLTAGE DETECTION/CPU OPERATING DETECTION RESET 371 19.1 19.2 19.3 19.4 19.5 19.6 Overview of Low Voltage/CPU Operating Detection Reset Circuit ................................................. Configuration of Low Voltage/CPU Operating Detection Reset Circuit .......................................... Low Voltage/CPU Operating Detection Reset Circuit Register ...................................................... Operating of Low Voltage/CPU Operating Detection Reset Circuit ................................................ Notes on Using Low Voltage/CPU Operating Detection Reset Circuit ........................................... Sample Program for Low Voltage/CPU Operating Detection Reset Circuit .................................... 372 374 376 378 379 380 CHAPTER 20 LIN-UART ................................................................................................. 381 20.1 Overview of LIN-UART ................................................................................................................... 20.2 Configuration of LIN-UART ............................................................................................................. 20.3 LIN-UART Pins ............................................................................................................................... 20.4 LIN-UART Registers ....................................................................................................................... 20.4.1 Serial Control Register (SCR) ................................................................................................... ix 382 386 391 392 393 20.4.2 LIN-UART Serial Mode Register (SMR) .................................................................................... 20.4.3 Serial Status Register (SSR) ..................................................................................................... 20.4.4 Reception and Transmission Data Register (RDR/TDR) ........................................................... 20.4.5 Extended Status/Control Register (ESCR) ................................................................................ 20.4.6 Extended Communication Control Register (ECCR) ................................................................. 20.4.7 Baud Rate Generator Register 0 and 1 (BGR0/1) ..................................................................... 20.5 LIN-UART Interrupts ....................................................................................................................... 20.5.1 Reception Interrupt Generation and Flag Set Timing ................................................................ 20.5.2 Transmission Interrupt Generation and Flag Set Timing ........................................................... 20.6 LIN-UART Baud Rates ................................................................................................................... 20.6.1 Setting the Baud Rate ............................................................................................................... 20.6.2 Restarting the Reload Counter .................................................................................................. 20.7 Operation of LIN-UART .................................................................................................................. 20.7.1 Operation in Asynchronous Mode (Op. Modes 0 and 1) ........................................................... 20.7.2 Operation in Synchronous Mode (Operation Mode 2) ............................................................... 20.7.3 Operation with LIN Function (Operation Mode 3) ...................................................................... 20.7.4 Direct Access to Serial Pins ...................................................................................................... 20.7.5 Bidirectional Communication Function (Normal Mode) ............................................................. 20.7.6 Master-Slave Communication Function (Multiprocessor Mode) ................................................ 20.7.7 LIN Communication Function .................................................................................................... 20.7.8 Sample Flowcharts for LIN-UART in LIN communication (Operation Mode 3) .......................... 20.8 Notes on Using LIN-UART .............................................................................................................. 395 397 399 401 403 405 406 409 411 413 415 418 420 422 426 429 432 433 435 438 439 441 CHAPTER 21 CAN CONTROLLER ................................................................................ 443 21.1 Features of CAN Controller ............................................................................................................ 21.2 Block Diagram of CAN Controller ................................................................................................... 21.3 List of Overall Control Registers ..................................................................................................... 21.4 Classifying CAN Controller Registers ............................................................................................. 21.4.1 Configuration of Control Status Register (CSR) ........................................................................ 21.4.2 Function of Control Status Register (CSR) ................................................................................ 21.4.3 Correspondence between Node Status Bit and Node Status .................................................... 21.4.4 Notes on Using Bus Operation Stop Bit (HALT = 1) .................................................................. 21.4.5 Last Event Indicator Register (LEIR) ......................................................................................... 21.4.6 Receive and Transmit Error Counters (RTEC) .......................................................................... 21.4.7 Bit Timing Register (BTR) .......................................................................................................... 21.4.8 Prescaler Setting by Bit Timing Register (BTR) ........................................................................ 21.4.9 Message Buffer Valid Register (BVALR) ................................................................................... 21.4.10 IDE Register (IDER) .................................................................................................................. 21.4.11 Transmission Request Register (TREQR) ................................................................................ 21.4.12 Transmission RTR Register (TRTRR) ....................................................................................... 21.4.13 Remote Frame Receiving Wait Register (RFWTR) ................................................................... 21.4.14 Transmission Cancel Register (TCANR) ................................................................................... 21.4.15 Transmission Complete Register (TCR) .................................................................................... 21.4.16 Transmission Interrupt Enable Register (TIER) ......................................................................... 21.4.17 Reception Complete Register (RCR) ........................................................................................ 21.4.18 Remote Request Receiving Register (RRTRR) ........................................................................ 21.4.19 Receive Overrun Register (ROVRR) ......................................................................................... x 444 445 446 452 453 454 456 457 458 461 462 463 465 466 467 468 469 470 471 472 473 474 475 21.4.20 Reception Interrupt Enable Register (RIER) ............................................................................. 21.4.21 Acceptance Mask Select Register (AMSR) ............................................................................... 21.4.22 Acceptance Mask Registers 0 and 1 (AMR0 and AMR1) .......................................................... 21.4.23 Message Buffers ........................................................................................................................ 21.4.24 ID Register x (x = 0 to 15) (IDRx) .............................................................................................. 21.4.25 DLC Register x (x = 0 to 15) (DLCRx) ....................................................................................... 21.4.26 Data Register x (x = 0 to 15) (DTRx) ......................................................................................... 21.5 Transmission of CAN Controller ..................................................................................................... 21.6 Reception of CAN Controller .......................................................................................................... 21.7 Reception Flowchart of CAN Controller .......................................................................................... 21.8 How to Use CAN Controller ............................................................................................................ 21.9 Procedure for Transmission by Message Buffer (x) ....................................................................... 21.10 Procedure for Reception by Message Buffer (x) ............................................................................. 21.11 Setting Configuration of Multi-level Message Buffer ....................................................................... 21.12 Setting the CAN Direct Mode Register ........................................................................................... 21.13 Precautions when Using CAN Controller ........................................................................................ 476 477 479 481 483 485 486 488 490 493 494 496 498 500 502 503 CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION ......................................... 505 22.1 Overview of Address Match Detection Function ............................................................................. 22.2 Block Diagram of Address Match Detection Function .................................................................... 22.3 Configuration of Address Match Detection Function ...................................................................... 22.3.1 Address Detection Control Register (PACSR0/PACSR1) ......................................................... 22.3.2 Detect Address Setting Registers (PADR0 to PADR5) ............................................................. 22.4 Explanation of Operation of Address Match Detection Function .................................................... 22.4.1 Example of using Address Match Detection Function ............................................................... 22.5 Program Example of Address Match Detection Function ............................................................... 506 507 508 509 513 516 517 522 CHAPTER 23 ROM MIRRORING MODULE ................................................................... 525 23.1 23.2 Overview of ROM Mirroring Function Select Module ...................................................................... 526 ROM Mirroring Function Select Register (ROMM) ......................................................................... 528 CHAPTER 24 512K-BIT FLASH MEMORY .................................................................... 529 24.1 Overview of 512K-bit Flash Memory ............................................................................................... 24.2 Block Diagram of the Entire Flash Memory and Sector Configuration of the Flash Memory .......... 24.3 Write/Erase Modes ......................................................................................................................... 24.4 Flash Memory Control Status Register (FMCS) ............................................................................. 24.5 Starting the Flash Memory Automatic Algorithm ............................................................................ 24.6 Confirming the Automatic Algorithm Execution State ..................................................................... 24.6.1 Data Polling Flag (DQ7) ............................................................................................................ 24.6.2 Toggle Bit Flag (DQ6) ................................................................................................................ 24.6.3 Timing Limit Exceeded Flag (DQ5) ........................................................................................... 24.7 Detailed Explanation of Writing to and Erasing Flash Memory ....................................................... 24.7.1 Setting The Read/Reset State ................................................................................................... 24.7.2 Writing Data ............................................................................................................................... 24.7.3 Erasing All Data (Erasing Chips) ............................................................................................... 24.8 Notes on Using 512K-bit Flash Memory ......................................................................................... 24.9 Flash Security Feature .................................................................................................................... xi 530 531 533 535 538 539 541 542 543 544 545 546 548 550 551 CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S)SERIAL PROGRAMMING CONNECTION .......................................................................................... 553 25.1 25.2 25.3 25.4 25.5 Basic Configuration of Serial Programming Connection with MB90F362/T(S), MB90F367/T(S) ... Example of Serial Programming Connection (User Power Supply Used) ...................................... Example of Serial Programming Connection (Power Supplied from Programmer) ........................ Example of Minimum Connection to Flash Microcontroller Programmer (User Power Supply Used) ............................................................................................................. Example of Minimum Connection to Flash Microcontroller Programmer (Power Supplied from Programmer) ............................................................................................... 554 557 559 561 563 CHAPTER 26 ROM SECURITY FUNCTION ................................................................... 565 26.1 Overview of ROM Security Function ............................................................................................... 566 APPENDIX ......................................................................................................................... 567 APPENDIX A I/O Maps .............................................................................................................................. APPENDIX B Instructions ........................................................................................................................... B.1 Instruction Types ............................................................................................................................ B.2 Addressing ..................................................................................................................................... B.3 Direct Addressing ........................................................................................................................... B.4 Indirect Addressing ........................................................................................................................ B.5 Execution Cycle Count ................................................................................................................... B.6 Effective address field .................................................................................................................... B.7 How to Read the Instruction List .................................................................................................... B.8 F2MC-16LX Instruction List ............................................................................................................ B.9 Instruction Map ............................................................................................................................... APPENDIX C Timing Diagrams in Flash Memory Mode ............................................................................ APPENDIX D List of Interrupt Vectors ........................................................................................................ xii 568 576 577 578 580 586 593 596 597 600 614 636 644 CHAPTER 1 OVERVIEW The MB90360 Series is a family member of the F2MC16LX micro controllers. 1.1 Overview of MB90360 1.2 Block Diagram of MB90360 series 1.3 Package Dimensions 1.4 Pin Assignment 1.5 Pin Functions 1.6 Input-Output Circuits 1.7 Handling Device 1 CHAPTER 1 OVERVIEW 1.1 Overview of MB90360 The MB90360 Series is a 16-bit microcontroller designed for automotive applications and contains CAN function, capture, compare timer, A/D converter, and so on. ■ Features of MB90360 Series MB90360 series has the following features: ● Clock • Built-in PLL clock multiplying circuit • Machine clock (PLL clock) selectable from 1/2 frequency of oscillation clock or 1 to 6-multiplied oscillation clock (4 MHz to 24 MHz when oscillation clock is 4 MHz) • Subclock operation (8.192 kHz) • Minimum instruction execution time: 42 ns (4-MHz oscillation clock and 6-multiplied PLL clock) • Clock supervisor: monitors main clock or subclock independently • Subclock mode: Clock source selectable from external oscillator or internal CR oscillator ● 16-MB CPU memory space • Internal 24-bit addressing ● Instruction system optimized for controllers • Various data types (bit, byte, word, long word) • 23 types of addressing modes • Enhanced signed instructions of multiplication/division and RETI • High-accuracy operations enhanced by 32-bit accumulator ● Instruction system for high-level language (C language)/multi-task • System stack pointer • Enhanced pointer indirect instructions • Barrel shift instructions ● Higher execution speed 4 bytes instruction queue ● Powerful interrupt function • Powerful interrupt function with 8 levels and 34 factors • Corresponds to 8-channel external interrupts 2 CHAPTER 1 OVERVIEW ● CPU-independent automatic data transfer function Extended intelligent I/O service (EI2OS): Maximum 16 channels ● Lower-power consumption (standby) modes • Sleep mode (stops CPU clock) • Timebase timer mode (operates only oscillation clock and subclock, timebase timer and watch timer) • Watch mode (product without S-suffix operates only subclock and watch timer) • Stop mode (stops oscillation clock and subclock) • CPU intermittent operation mode ● Process CMOS Technology ● I/O ports • General-purpose I/O ports (CMOS output) - 34 ports (product without S-suffix) - 36 ports (product with S-suffix) ● Subclock pin (X0A, X1A) • Yes (external oscillator used) ... products without S-suffix • No (subclock mode is used with internal CR oscillation) ... product with S-suffix ● Timers • Timebase timer, watch timer (product without S-suffix), watchdog timer: 1 channel • 8-/16-bit PPG timer: 8 bits × 4 channels or 16 bits × 2 channels • 16-bit reload timer: 2 channels • 16-bit I/O timer - 16-bit free-run timer: 1 channel (FRT0: ICU0/1/2/3) - 16-bit input capture (ICU): 4 channels ● Full-CAN* CAN Controller: 1 channel • Conforms to CAN Specification Ver. 2.0A and Ver. 2.0B. • Built-in 16 message buffers • CAN wake up ● UART (LIN/SCI): Maximum 2 channels • Full-duplex double buffer • Clock asynchronous or clock synchronous serial transfer ● DTP/external interrupt: 8 channels, CAN wake up: 1 channel External input to start EI2OS and generate external interrupt 3 CHAPTER 1 OVERVIEW ● Delayed interrupt generation module Generates interrupt request for task switching ● 8-/10-bit A/D converter: 16 channels • 8-bit and 10-bit resolutions • Start by external trigger input • Conversion time: 3 µs (including sampling time at 24-MHz machine clock frequency) ● Program patch function Detects address match for six address pointers ● Low voltage/CPU operation detection reset function (product with T-suffix) • Detects low voltage (4.0 V ± 0.3 V) and reset automatically • Automatic reset when program runs away and counter is not cleared within internal time (approx. 262 ms @ 4 MHz external) ● Clock supervisor (MB90x367x only) ● Changeable port input voltage level Automotive input level/CMOS Schmitt input level (initial value in single-chip mode is Automotive level) ● ROM security function Capable of protecting the content of ROM (MASK ROM product only) *: Controller Area Network (CAN) - License of Robert Bosch GmbH 4 CHAPTER 1 OVERVIEW ■ Product overview Table 1.1-1 Product Overview (1/2) Features MB90362 MB90362T MB90362S CPU MB90362TS MB90V340 A-101 MB90V340 A-102 F2MC-16LX CPU System clock pin PLL clock multiplier (✕1, ✕2, ✕3, ✕4, ✕6, 1/2 when PLL stops) Minimum instruction execution time: 42 ns (4 MHz osc. PLL ✕6) Sub clock pin (X0A, X1A) Yes No No Clock supervisor Yes No ROM MASK ROM, 64K bytes External RAM capacitance 3K bytes 30K bytes CAN interface 1 channel 3 channels Low voltage/CPU operation detection reset No Yes Package No No LQFP-48 PGA-299 - Yes Power supply for emulator* Corresponding EVA product name Yes MB90V340A-102 MB90V340A-101 *: It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used. Please refer to Emulator hardware manual. Features MB90F362 MB90F362T CPU System clock pin MB90F362S F2MC-16LX CPU PLL clock multiplier (✕1, ✕2, ✕3, ✕4, ✕6, 1/2 when PLL stops) Minimum instruction execution time: 42 ns (4 MHz osc. PLL ✕6) Sub clock pin (X0A, X1A) Yes No Clock supervisor No ROM Flash memory, 64K bytes RAM capacitance 3K bytes CAN interface 1 channel Low voltage/CPU operation detection reset No Yes Package Corresponding EVA product name MB90F362TS No Yes LQFP-48 MB90V340A-102 MB90V340A-101 5 CHAPTER 1 OVERVIEW Table 1.1-2 Product Overview (2/2) Features MB90367 MB90367T MB90367S CPU MB90367TS MB90V340 A-103 MB90V340 A-104 F2MC-16LX CPU System clock pin PLL clock multiplier (✕1, ✕2, ✕3, ✕4, ✕6, 1/2 when PLL stops) Minimum instruction execution time: 42 ns (4 MHz osc. PLL ✕6) Sub clock pin (X0A, X1A) Yes No (Internal CR oscillation can be used as subclock) Clock supervisor Yes Yes ROM MASK ROM, 64K bytes External RAM capacitance 3K bytes 30K bytes CAN interface 1 channel 3 channels No Low voltage/CPU operation detection reset Yes Package No No LQFP-48 PGA-299 - Yes Power supply for emulator* Corresponding EVA product name Yes MB90V340A-104 MB90V340A-103 *: It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used. Please refer to Emulator hardware manual. Features MB90F367 MB90F367T CPU System clock pin PLL clock multiplier (✕1, ✕2, ✕3, ✕4, ✕6, 1/2 when PLL stops) Minimum instruction execution time: 42 ns (4 MHz osc. PLL ✕6) Yes No (Internal CR oscillation can be used as subclock) Yes ROM Flash memory, 64K bytes RAM capacitance 3K bytes CAN interface 1 channel Low voltage/CPU operation detection reset No Yes Package Corresponding EVA product name 6 MB90F367TS F2MC-16LX CPU Sub clock pin (X0A, X1A) Clock supervisor MB90F367S No Yes LQFP-48 MB90V340A-104 MB90V340A-103 CHAPTER 1 OVERVIEW ■ Features Table 1.1-3 MB90360 Features (1/2) Features UART MB90F362/T(S), MB90362/T(S) MB90F367/T(S), MB90367/T(S) MB90V340A-101, MB90V340A-102 MB90V340A-103, MB90V340A-104 2 channels 5 channels Wide range of baud rate settings using a dedicated reload timer LIN functionality working either as LIN master or LIN slave device A/D converter 16 channels 24 channels 10-bit or 8-bit resolution Conversion time: Minimum 3 µs include sample time (per one channel) 2 channels 16-bit reload timer Operation clock frequency: fsys/21, fsys/23, fsys/25(fsys=System clock freq.) Support External Event Count function 1 channel 16-bit I/O timer 4 channels I/O timer 0 (clock input FRCK0) corresponding ICU 0/1/2/3. 4 channels I/O timer 0 (clock input FRCK0) corresponds to ICU 0/1/2/3, OCU 0/1/2/3 I/O timer 1 (clock input FRCK1) corresponds to ICU 4/5/6/7, OCU 4/5/6/7 Signal an interrupt when overflowing Supports Timer Clear when a match with Output Compare (Channel 0, 4) Operation clock freq.: fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27 (fsys=System clock freq.) 4 channels 16-bit input capture Maintains I/O timer value by pin input (rising edge, falling edge, or both edges) and generates interrupt. 2 channels 8-/16-bit PPG 8 channels Supports 8-bit and 16-bit operation modes Four 8-bit reload counter Four 8-bit reload registers for L pulse width Four 8-bit reload registers for H pulse width 8 channels Supports 8-bit and 16-bit operation modes Sixteen 8-bit reload counter Sixteen 8-bit reload registers for L pulse width Sixteen 8-bit reload registers for H pulse width A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as 8-bit prescaler plus 8-bit reload counter Operation clock freq.: fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 102.4 µs fosc=@5MHz (fsys=system clock frequency, fosc=oscillation clock frequency) 7 CHAPTER 1 OVERVIEW Table 1.1-3 MB90360 Features (2/2) Features CAN interface MB90F362/T(S), MB90362/T(S) MB90F367/T(S), MB90367/T(S) MB90V340A-101, MB90V340A-102 MB90V340A-103, MB90V340A-104 3 channels 1 channel Conforms to CAN Specification Version 2.0 Part A and B Automatic re-transmission in case of error Automatic transmission responding to Remote Frame 16 message buffers for transmission/reception Supports multiple messages Flexible configuration of acceptance filtering: • Full bit compare/Full bit mask/2 partial bit masks • Supports up to 1 Mbps communication External interrupt (8 channels) Can be programmed edge sensitive or level sensitive D/A converter - 2 channels Corresponds to product with T-suffix only - MB90F367/T(S), MB90367/T(S) only - Low voltage/CPU operation detection reset Clock supervisor Subclock (Maximum 100 kHz) Corresponds to product without T-suffix only Corresponds to MB90V340A-102/MB90V340A-104 only I/O port Supports general-purpose I/O (CMOS output): - 34 ports (product without S-suffix) - 36 ports (product with S-suffix) Input level setting: - Port2, Port4, Port6, Port8: selectable from CMOS/Automotive level Flash memory Supports automatic programming, Embedded AlgorithmTM*, Write/Erase/Erase-Suspend/Resume commands A flag indicating completion of the algorithm Number of erase cycles: 10,000 times Data retention time: 20 years Flash Security Feature for protecting the content of the Flash ROM security Protects the content of ROM (MASK ROM product only) Supports general-purpose I/O (CMOS output): - 80 ports (product without S-suffix) - 82 ports (product with S-suffix) Input level setting - Port 0 to Port 3: selectable from CMOS/ Automotive/TTL level - Port 4 to Port A: selectable from CMOS/ Automotive level *:Embedded Algorithm is a registered trademark of Advanced Micro Device Inc. 8 - CHAPTER 1 OVERVIEW 1.2 Block Diagram of MB90360 series Figure 1.2-3 shows a block diagram of the MB90360. ■ Block Diagram of Evaluation Chip Figure 1.2-1 Block Diagram of Evaluation Chip (MB90V340A-101/102) X0, X1 X0A, X1A * Clock control RST F2MC-16LX core 16-bit I/O timer 0 RAM 30KB AVCC AVSS AN23 to AN0 AVRH AVRL ADTG DA01, DA00 PPGF to PPG0 SDA1, SDA0 SCL1, SCL0 Input capture 8 channels IN7 to IN0 Output compare 8 channels OUT7 to OUT0 Prescaler (5 channels) 16-bit I/O timer 1 UART (5 channels) CAN controller 3 channels RX2 to RX0 TX2 to TX0 16-bit reload timer 4 channels TIN3 to TIN0 TOT3 to TOT0 8-/10-bit A/D converter 24 channels 10-bit D/A converter 2 channels Internal data bus SOT4 to SOT0 SCK4 to SCK0 SIN4 to SIN0 FRCK0 AD15 to AD00 A23 to A16 ALE External bus DMA RD WRL WRH HRQ HAK RDY CLK 8-/16-bit PPG 16 channels I2C interface 2channels FRCK1 DTP/ external interrupt Clock monitor INT15 to INT8 (INT15R to INT8R) INT7 to INT0 CKOT *: Support MB90V340A-102 only 9 CHAPTER 1 OVERVIEW Figure 1.2-2 Block Diagram of Evaluation Chip (MB90V340A-103/104) X0,X1 X0A,X1A* Clock control RST F2MC-16LX core CR oscillation circuit RAM 30KB AVcc AVss AN23 to AN0 AVRH AVRL ADTG Output compare 8 channels OUT7 to OUT0 UART 5 channels CAN controller 3 channels RX2 to RX0 TX2 to TX0 16-bit reload timer 4 channels TIN3 to TIN0 TOT3 to TOT0 8-/10-bit A/D converter 24 channels PPGF to PPG0 8-/16-bit PPG 16 channels I2C Interface 2 channels DMA *: Support MB90V340A-104 only 10 IN7 to IN0 FRCK1 10-bit D/A converter 2 channels SCL1 , SCL0 Input capture 8 channels 16-bit I/O timer 1 DA01 , DA00 SDA1 , SDA0 FRCK0 Prescaler (5 channels) Internal data bus SOT4 to SOT0 SCK4 to SCK0 SIN4 to SIN0 16-bit I/O timer 0 External bus AD15 to AD00 A23 to A16 ALE RD WRL WRH HRQ HAK RDY CLK DTP/ external interrupt INT15 to INT8 (INT15R to INT8R) INT7 to INT0 Clock monitor CKOT CHAPTER 1 OVERVIEW ■ Block Diagram of Flash/Mask ROM Version Figure 1.2-3 Block Diagram of Flash/Mask ROM Version X0,X1 X0A,X1A *1 RST Clock control/ monitor *3 F2MC-16LX core CR oscillation circuit RAM 3KB ROM 64KB Prescaler (2 channels) SOT0,SOT1 SCK0,SCK1 SIN0,SIN1 AVCC AVSS AN15 to AN0 AVR Internal data bus Low voltage detection*2 CPU operation detection*2 Input capture 4 channels IN0 to IN3 16-bit I/O timer 0 FRCK0 CAN controller 1 chnnal RX1 TX1 16-bit reload timer 2 channels TIN2,TIN3 TOT2,TOT3 DTP/ external interrupt INT8,INT9R INT10,INT11 INT12R,INT13 INT14R,INT15R UART 2 channels 8/10-bit A/D converter 16 channels ADTG PPGF(E),PPGD(C), PPGC(D),PPGE(F) 8/16bit PPG 2 channels *1: Product without S-suffix *2: Product with T-suffix *3: CR oscillation circuit/clock supervisor supports MB90367/T(S), MB90F367/T(S) only 11 CHAPTER 1 OVERVIEW 1.3 Package Dimensions MB90360 series has a package. Note that the dimensions show below are reference dimensions. For formal dimensions of each package, contact us. ■ Package Dimensions Figure 1.3-1 shows the package dimensions of LQFP-48 type. Figure 1.3-1 Package Dimensions of LQFP-48 Type 48-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 7 × 7 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.17 g Code (Reference) P-LFQFP48-7×7-0.50 (FPT-48P-M26) 48-pin plastic LQFP (FPT-48P-M26) Note 1) * : These dimensions include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 9.00±0.20(.354±.008)SQ +0.40 +.016 * 7.00 –0.10 .276 –.004 SQ 36 0.145±0.055 (.006±.002) 25 37 24 0.08(.003) Details of "A" part +0.20 1.50 –0.10 +.008 48 13 "A" 0˚~8˚ LEAD No. 1 0.50(.020) (Mounting height) .059 –.004 INDEX 0.10±0.10 (.004±.004) (Stand off) 12 0.20±0.05 (.008±.002) 0.08(.003) 0.25(.010) M 0.60±0.15 (.024±.006) C 12 2003 FUJITSU LIMITED F48040S-c-2-2 Dimensions in mm (inches). Note: The values in parentheses are reference values. CHAPTER 1 OVERVIEW 1.4 Pin Assignment This section shows the pin assignments for the MB90360 series. ■ Pin assignment (LQFP-48) Figure 1.4-1 shows the pin assignments of LQFP-48 type. Figure 1.4-1 Pin Assignment (LQFP-48) P43/TX1 P86/SOT1 P87/SCK1 P85/SIN1 48 47 46 45 44 43 42 41 40 39 38 37 AVss X1A/P41 *1 X0A/P40 * 1 P44/FRCK0 P82/SIN0/INT14R/TIN2 P84/SCK0/INT15R P83/SOT0/TOT2 P42/RX1/INT9R (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 TOP VIEW P20 *2 *2 P22/PPGD(C) *2 P23/PPGF(E) *2 P21 P24/IN0 P25/IN1 P26/IN2 P27/IN3 X1 X0 C V ss RST Vcc P54/AN12/TOT3/INT8 P55/AN13/INT10 P56/AN14/INT11 P57/AN15/INT13 MD2 MD1 MD0 P51/AN9 P52/AN10 P53/AN11/TIN3 13 14 15 16 17 18 19 20 21 22 23 24 AVcc AVR P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6/PPGC(D) P67/AN7/PPGE(F) P80/ADTG/INT12R P50/AN8 (FPT-48P-M26) *1: MB90F362/T, MB90362/T, MB90F367/T, MB90367/T : X0A, X1A MB90F362S/TS, MB90362S/TS, MB90F367S/TS, MB90367S/TS : P40, P41 *2: High current port 13 CHAPTER 1 OVERVIEW 1.5 Pin Functions Table 1.5-1 describes the pin functions of the MB90360 series. ■ Pin Functions Table 1.5-1 Pin Description (1/3) Pin number Pin name Circuit type Functional description 1 AVCC I VCC power input pin for analog circuit 2 AVR - Power (Vref+) input pin for A/D converter. The power supply should not be input VCC exceeding. 3 to 8 P60 to P65 H General-purpose I/O port AN0 to AN5 9 to 10 11 12 to 14 P66, P67 Analog input pin for A/D converter. H AN6, AN7 Analog input pin for A/D converter PPGC(D), PPGE(F) Output pin for PPG P80 F 16 17 to 19 General-purpose I/O port ADTG Trigger input pin for A/D converter INT12R External interrupt request input pin for INT12R. P50 to P52 H AN8 to AN10 15 General-purpose I/O port P53 General-purpose I/O port (I/O circuit type of P50 is different from that of MB90V340A) Analog input pin for A/D converter H General-purpose I/O port AN11 Analog input pin for A/D converter TIN3 Event input pin for reload timer 3 P54 H General-purpose I/O port AN12 Analog input pin for A/D converter TOT3 Output pin for reload timer 3 INT8 External interrupt request input pin for INT8 P55 to P57 H General-purpose I/O port AN13 to AN15 Analog input pin for A/D converter INT10, INT11, INT13 External interrupt request input pin for INT10, INT11 and INT13 20 MD2 D Input pin for selecting operation mode 21, 22 MD1,MD0 C Input pin for selecting operation mode 23 RST E Reset input 24 VCC - Power input pin (3.5 V to 5.5 V) 25 VSS - Power input pin (0 V) 14 CHAPTER 1 OVERVIEW Table 1.5-1 Pin Description (2/3) Pin number Pin name Circuit type Functional description 26 C I Capacity pin for stabilizing power supply. It should be connected to higher than or equal to 0.1 µF ceramic capacitor. 27 X0 A Oscillation input pin 28 X1 A Oscillation output pin 29 to 32 P24 to P27 G General-purpose I/O port The register can be set to select whether to use pull-up register. This function is enabled in single-chip mode. IN0 to IN3 33, 34 P22 to P23 Event input pin for input capture 0 to 3. J PPGF(E), PPGD(C) General-purpose I/O port The pull-up resistor ON/OFF can be set by setting the register. This function becomes valid at shingle-chip mode. High current output port Output pin for PPG 35, 36 P20, P21 J General-purpose I/O port The pull-up resistor ON/OFF can be set by setting the register. This function becomes valid at shingle-chip mode. High current output port 37 P85 K General-purpose I/O port SIN1 38 P87 Serial data input pin for UART1 F SCK1 39 P86 Clock I/O pin for UART1 F SOT1 40 P43 42 43 44 P42 General-purpose I/O port Serial data output pin for UART1 F TX1 41 General-purpose I/O port General-purpose I/O port TX output pin for CAN1 interface F General-purpose I/O port RX1 RX input pin for CAN1 interface INT9R External interrupt request input pin for INT9R (sub) P83 F General-purpose I/O port SOT0 Serial data output pin for UART0 TOT2 Output pin for reload timer 2 P84 F General-purpose I/O port SCK0 Clock I/O pin for UART0 INT15R External interrupt request input pin for INT15R P82 K General-purpose I/O port SIN0 Serial data input pin for UART0 INT14R External interrupt request input pin for INT14R TIN2 Event input pin for reload timer 2 15 CHAPTER 1 OVERVIEW Table 1.5-1 Pin Description (3/3) Pin number 45 Pin name P44 Circuit type F FRCK0 46, 47 48 16 Functional description General-purpose I/O port (I/O circuit type of P44 is different from that of MB90V340A.) Free-run timer 0 clock pin P40, P41 F General-purpose I/O port (product with S-suffix and MB90V340A-101/103 only) X1A, X0A B Oscillation input pin for subclock (product without S-suffix and MB90V340A-102/104 only) AVSS I VSS power input pin for analog circuit CHAPTER 1 OVERVIEW 1.6 Input-Output Circuits Table 1.6-1 lists the input-output circuits. ■ Input-output Circuits Table 1.6-1 I/O Circuit Types (1/4) Type A Circuit X1 Remarks Xout Oscillation circuit High-speed oscillation feedback resistor = approx. 1 MΩ X0 Standby control signal B X1A Xout Oscillation circuit Low-speed oscillation feedback resistor = approx. 10 MΩ X0A Standby control signal C Hysteresis input Mask ROM device : CMOS hysteresis input pin Flash device: CMOS input Hysteresis input Mask ROM device : CMOS hysteresis input pin Pull-down resistor value: approx. 50 kΩ R D R Pull-down resistor Flash device: CMOS input pin No Pull-down 17 CHAPTER 1 OVERVIEW Table 1.6-1 I/O Circuit Types (2/4) Type Circuit Remarks E CMOS hysteresis input pin Pull-up resister value: approx. 50 kΩ Pull-up resistor R Hysteresis input F Pout Nout R Hysteresis input CMOS level output (IOL = 4 mA, IOH =-4 mA) CMOS hysteresis inputs (with the standby-time input shutdown function) Automotive input (with the standby-time input shutdown function) Automotive input Standby control for input shutdown G Pull-up control Pout Nout R Hysteresis input Automotive input Standby control for input shutdown 18 CMOS level output (IOL = 4 mA, IOH =-4 mA) CMOS hysteresis inputs (with the standby-time input shutdown function) Automotive input (with the standby-time input shutdown function) Programmable pull-up resistor: approx. 50 kΩ CHAPTER 1 OVERVIEW Table 1.6-1 I/O Circuit Types (3/4) Type Circuit Remarks H Pout Nout R Hysteresis input CMOS level output (IOL = 4 mA, IOH =-4 mA) CMOS hysteresis inputs (with the standby-time input shutdown function) Automotive input (with the standby-time input shutdown function) A/D analog input Automotive input Standby control for input shutdown Analog input I Power supply input protection circuit J Pull-up control Pout High current output Nout High current output R CMOS level output (IOL = 20 mA, IOH =-14 mA) CMOS hysteresis inputs (with the standby-time input shutdown function) Automotive inputs (with the standby-time input shutdown function) Programmable pull-up resistor: approx. 50 kΩ Hysteresis input Automotive input Standby control for input shutdown 19 CHAPTER 1 OVERVIEW Table 1.6-1 I/O Circuit Types (4/4) Type Circuit Remarks K CMOS level output (IOL = 4 mA, IOH = -4 mA) CMOS hysteresis inputs (with the standby-time input shutdown function) Automotive hysteresis inputs (with the standby-time input shutdown function) Pout Nout R CMOS input Automotive input Standby control for input shutdown 20 CHAPTER 1 OVERVIEW 1.7 Handling Device This section explains notes on handling the MB90360 series. ■ Handling the Device ● Preventing latch-up CMOS IC chips may suffer latch-up under the following conditions: • A voltage higher than VCC or lower than VSS is applied to an input or output pin. • A voltage higher than the rated voltage is applied between VCC and VSS. • The AVCC power supply is applied before the VCC voltage. Latch-up may increase the power supply current drastically, causing thermal damage to the device. When used, note that maximum rated voltage is not exceeded. For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVR) exceed the digital power-supply voltage. ● Treatment of unused pins Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the device. Therefore, they must be pulled up or pulled down through resistors. In this case those resistors should be more than 2 kΩ. Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above described connection. 21 CHAPTER 1 OVERVIEW ● Using external clock To use external clock, drive the X0 (X0A) pin and leave X1 (X1A) pin open. Figure 1.7-1 Using External Clock MB90360 series X0 (X0A) Open X1 (X1A) ● Precautions for when not using a sub clock signal If you do not connect pins X0A and X1A to an oscillator, use pull-down handling on the X0A pin, and leave the X1A pin open. ● Notes on during operation of PLL clock mode If the PLL clock mode is selected, the microcontroller attempts to be working with the free-running frequency of self-oscillating circuit in the PLL even when there is no external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed. ● Power supply pins (VCC/VSS) • If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential are connected the inside of the device to prevent such malfunctioning as latch up. To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level, and to keep the recommended DC characteristics specified as the total output current, be sure to connect the VCC and VSS pins to the power supply and ground externally (see Figure 1.7-2 ). • Connect VCC and VSS to the device from the power supply source with lowest possible impedance. • It is recommended to connect a capacitor of about 0.1 µF as a bypass capacitor between VCC and VSS in the vicinity of VCC and VSS pins of the device 22 CHAPTER 1 OVERVIEW Figure 1.7-2 Power Supply Pins (VCC/VSS) Vcc Vss Vcc Vss Vss Vcc MB90360 series Vcc Vss Vss Vcc ● Pull-up/down resistors The MB90360 Series does not support internal pull-up/down resistors (except Port2: programmable pull-up resistors). Use pull-up/down handling where needed. ● Crystal Oscillator Circuit Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits. It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with a ground area for stabilizing the operation. ● Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs Make sure to turn on the A/D converter power supply (AVCC, AVR) and analog inputs (AN0 to AN15) after turning-on the digital power supply (VCC). Turn-off the digital power supply after turning off the A/D converter power supply and analog inputs. In this case, make sure that the voltage not exceed AVR or AVCC. ● Connection of Unused Pins of A/D Converter Connect unused pins of A/D converter as AVCC = VCC, AVSS = AVR = VSS. 23 CHAPTER 1 OVERVIEW ● Notes on Energization To prevent malfunction of the internal voltage regulator, supply voltage profile while turning on the power supply should be slower than 50 µs from 0.2 V to 2.7 V. ● Stabilization of power supply voltage If the power supply voltage varies acutely even within the operation assurance range of the VCC power supply voltage, a malfunction may occur. The VCC power supply voltage must therefore be stabilized. As stabilization guidelines, stabilize the power supply voltage so that VCC ripple fluctuations (peak to peak value) in the commercial frequencies (50 to 60 Hz) fall within 10% of the standard VCC power supply voltage and the transient fluctuation rate becomes 0.1 V/ms or less in instantaneous fluctuation for power supply switching. ● Note on using CAN Function The MB90360 series does not contain the clock modulation function. So, at using CAN, the DIRECT bit of the CAN direct mode register (CDMR) must be set "1". (See Table 1.7-1 ). If the DIRECT bit is not set correctly, the device does not operate normally. Table 1.7-1 Setting of Clock Modulation and CAN Direct Mode Clock modulation setting (CMCR:PMOD bit) CAN direct mode setting (setting of CDMR:DIRECT bit) Required setting 0: Disable clock modulation (initial value) 1: Enable CAN direct mode Setting disabled 1: Enable clock modulation 0: Disable CAN direct mode (initial value) Note: For details on the clock modulation, see "CHAPTER 6 CLOCK SUPERVISOR". For details on the CAN direct mode, see "21.11 Setting Configuration of Multi-level Message Buffer". 24 CHAPTER 1 OVERVIEW ● Flash security Function The security bit is located in the area of the flash memory. If protection code 01H is written in the security bit, the flash memory is in the protected state by security. Therefore please do not write 01H in this address if you do not use the security function. Please refer to following table for the address of the security bit. MB90F362/T(S), MB90F367/T(S) Flash memory size Address of security bit Embedded 512Kbit flash memory FF0001H ● For the diversion of MB90340-series software assets In programming of the MB90360 series, keep the following points in mind for the diversion of MB90340-series software assets in particular. • Access to the registers which do not exist in the MB90360 series. As for the registers and bits which exist in MB90340 series but not in the MB90360 series, do not access them or ensure that the initial value is set. Setting any other value than the initial value may cause an abnormal operation in emulation using MB90V340. • Setting of the external interrupt factor select register (EISSR). The MB90360 series is not equipped with the external interrupt request input, INT8R, INT9, INT10, INT11, INT12, INT13, INT14 and INT15. Enabling unequipped terminals causes a false operation. First set the EISSR and then set each of the registers when DTP/external interrupt is used. 25 CHAPTER 1 OVERVIEW 26 CHAPTER 2 CPU This chapter explains the CPU. 2.1 Outline of the CPU 2.2 Memory Space 2.3 Memory Map 2.4 Linear Addressing 2.5 Bank Addressing Types 2.6 Multi-byte Data in Memory Space 2.7 Registers 2.8 Register Bank 2.9 Prefix Codes 2.10 Interrupt Disable Instructions 2.11 Precautions for Use of "DIV A, Ri" and "DIVW A, RWi" Instructions 27 CHAPTER 2 CPU 2.1 Outline of the CPU The F2MC-16LX CPU core is a 16-bit CPU designed for applications that require highspeed real-time processing, such as home-use or vehicle-mounted electronic appliances. The F2MC-16LX instruction set is designed for controller applications, and is capable of high-speed, highly efficient control processing. ■ Outline of the CPU In addition to 16-bit data, the F2MC-16LX CPU core can process 32-bit data by using an internal 32-bit accumulator. (32-bit data can be processed with some instructions.) Up to 16M bytes of memory space (expandable) can be used, which can be accessed by either the linear pointer or bank method. The instruction system, based on the F2MC-8 A-T architecture, has been reinforced by adding instructions compatible with high-level languages, expanding addressing modes, reinforcing multiplication and division instructions, and enhancing bit processing. The features of the F2MC-16LX CPU are explained below. ● Minimum instruction execution time: 42 ns (at 4-MHz oscillation, 6 times clock multiplication) ● Maximum memory space: 16M bytes, accessed in linear or bank mode ● Instruction set optimized for controller applications • Rich data types: Bit, byte, word, long word • Extended addressing modes: 23 types • High-precision operation (32-bit length) based on 32-bit accumulator ● Powerful interrupt functions Eight priority levels (programmable) ● CPU-independent automatic transfer Up to 16 channels of the extended intelligent I/O service ● Instruction set compatible with high-level language (C)/multitasking System stack pointer/instruction set symmetry/barrel-shift instructions ● Improved execution speed: 4 bytes queue 28 CHAPTER 2 CPU 2.2 Memory Space An F2MC-16LX CPU has a 16M bytes memory space. All data program input and output managed by the F2MC-16LX CPU are located in this 16M bytes memory space. The CPU accesses the resources by indicating their addresses using a 24-bit address bus. ■ Outline of CPU Memory Space Figure 2.2-1 shows a sample relationship between the F2MC-16LX system and memory map. Figure 2.2-1 Sample Relationship between F2MC-16LX System and Memory Map F2MC-16LX device FFFFFFH FFFC00H Programs FF0000H*1 Vector table area ROM area Program area 100000H External area*3 010000H 008000H F2MC-16LX CPU Internal data bus Peripheral circuit 007900H 001900H*2 Data EI2OS 000380H 000180H 000100H ROM area (FF bank image) Peripheral function control register area Data area General-purpose register 2 EI OS descriptor area I/O area RAM area External area*3 Peripheral circuit Interrupt 0000F0H 0000C0H 0000B0H Peripheral circuit General-purpose ports 000020H 000000H Peripheral function control register area Interrupt control register area Peripheral function control register area I/O port control register area I/O area *1: The size of the internal ROM differs for each model. *2: The size of the internal RAM differs for each model. *3: Access is not possible in single-chip mode. 29 CHAPTER 2 CPU ■ ROM area ● Vector table area (address: FFFC00H to FFFFFFH) This area is used as a vector table for reset/interrupt and CALLV vector. This area is allocated at the highest addresses of the ROM area. The start address of the corresponding processing routine is set as data in each vector table address. ● Program area (address: FF0000H to FFFBFFH) ROM is built in as an internal program area. The size of internal ROM differs for each model. ■ RAM Area ● Data area (address: From 000100H to 000CFFH (for 3K bytes)) The static RAM is built in as an internal data area. The size of internal RAM differs for each model. ● General-purpose register area (address: 000180H to 00037FH) Auxiliary registers used for 8-bit, 16-bit, and 32-bit arithmetic operations and transfer are allocated in this area. Since this area is allocated to a part of the RAM area, it can be used as ordinary RAM. When this area is used as a general-purpose register, general-purpose register addressing enables highspeed access with short instructions. ● Extended intelligent I/O service (EI2OS) descriptor area (address: 000100H to 00017FH) This area retains the transfer modes, I/O addresses, transfer count, and buffer addresses. Since this area is allocated to a part of the RAM area, it can be used as ordinary RAM. ■ I/O Area ● Interrupt control register area (address: 0000B0H to 0000BFH) The interrupt control registers (ICR00 to ICR15) correspond to all peripheral functions that have an interrupt function. These registers set interrupt levels and control the extended intelligent I/O service (EI2OS). ● Peripheral function control register area (address: 000020H to 0000AFH , 0000C0H to 0000EFH , 007900H to 007FFFH) This register controls the built-in peripheral functions and inputs and outputs data. ● I/O port control register area (address: 000000H to 00001FH) This register controls I/O ports, and inputs and outputs data. 30 CHAPTER 2 CPU ■ Address generation types The F2MC-16LX has the following 2 addressing modes: ● Linear addressing An entire 24-bit address is specified by an instruction. ● Bank addressing. The eight high-order bits of an address are specified by an appropriate bank register, and the remaining 16 low-order bits are specified by an instruction. 31 CHAPTER 2 CPU 2.3 Memory Map The memory map of the MB90360 Series is shown in Figure 2.3-1 . ■ Memory Map The ROM data in the high-order portion of FF-bank can be seen as an image in the higher 00-bank in order to support the small model C compiler. Since the low-order 16 bits are identical, this part of the ROM data can be referred without using the far specification in the pointer declaration. For example, when 00C000H is accessed, the contents of ROM at FFC000H are read. However, since the ROM area in the FF bank exceeds 32K bytes, its entire image cannot be mirrored in the 00 bank. The image between FF8000H and FFFFFFH is visible in bank 00, whereas the data between FF0000H and FF7FFFH is only visible in bank FF. Figure 2.3-1 Memory Map MB90F362/T(S) MB90362/T(S) MB90F367/T(S) MB90367/T(S) MB90V340A-101/102/103/104 FFFFFFH FFFFFFH ROM (FF bank) FF0000H FEFFFFH FF0000H FEFFFFH ROM (FF bank) ROM (FE bank) FE0000H FDFFFFH ROM (FD bank) FD0000H FCFFFFH ROM (FC bank) FC0000H FBFFFFH ROM (FB bank) FB0000H FAFFFFH FA0000H F9FFFFH F90000H F8FFFFH ROM (FA bank) ROM (F9 bank) ROM (F8 bank) F80000H 00FFFFH 008000H 007FFFH 007900H 0078FFH ROM (image of FF bank) Peripheral 010000H 00FFFFH 008000H 007FFFH 007900H ROM (image of FF bank) Peripheral RAM 30KB 000100H 0000EFH 000000H Peripheral Access prohibited 32 000CFFH 000100H 0000FFH 0000F0H 0000EFH 000000H RAM 3KB Peripheral CHAPTER 2 CPU 2.4 Linear Addressing There are 2 types of linear addressing: • 24-bit operand specification: Directly specifies a 24-bit address using operands. • 32-bit register indirect specification: Indirectly specifies the 24 low-order bits of a 32bit general-purpose register value as the address. ■ 24-bit Operand Specification Figure 2.4-1 shows an example of 24-bit operand specification. Figure 2.4-2 shows an example of 32-bit register indirect specification. Figure 2.4-1 Example of Linear Method (24-bit operand specification) JMPP 123456H 17452DH Old program counter 17 + Program bank 452D JMPP 123456H 123456H Next instruction New program counter 12 + Program bank 3456 Figure 2.4-2 Example of Linear Method (32-bit register indirect specification) MOV A, @RL1+7 Old AL 090700H XXXX 3A 7 RL1 240906F9 (The high-order 8 bits are ignored.) New AL 003A 33 CHAPTER 2 CPU 2.5 Bank Addressing Types In the bank method, the 16M bytes space is divided into 256 for 64K bytes banks. The following 5 bank registers are used to specify the banks corresponding to each space: • Program bank register (PCB) • Data bank register (DTB) • User stack bank register (USB) • System stack bank register (SSB) • Additional bank register (ADB) ■ Bank Addressing Types ● Program bank register (PCB) The 64K bytes bank specified by the PCB is called a program (PC) space. The PC space contains instruction codes, vector tables, and immediate value data, for example. ● Data bank register (DTB) The 64K bytes bank specified by the DTB is called a data (DT) space. The DT space contains readable/ writable data, and control/data registers for internal and external resources. ● User stack bank register (USB)/system stack bank register (SSB) The 64K bytes bank specified by the USB or SSB is called a stack (SP) space. The SP space is accessed when a stack access occurs during a push/pop instruction or interrupt register saving. The S flag in the condition code register determines the stack space to be accessed. ● Additional bank register (ADB) The 64K bytes bank specified by the ADB is called an additional (AD) space. The AD space, for example, contains data that cannot fit into the DT space. Table 2.5-1 lists the default spaces used in each addressing mode, which are pre-determined to improve instruction coding efficiency. To use a non-default space for an addressing mode, specify a prefix code corresponding to a bank before the instruction. This enables access to the bank space corresponding to the specified prefix code. After reset, the DTB, USB, SSB, and ADB are initialized to 00H. The PCB is initialized to a value specified by the reset vector. After reset, the DT, SP, and AD spaces are allocated in bank 00H (000000H to 00FFFFH), and the PC space is allocated in the bank specified by the reset vector. 34 CHAPTER 2 CPU Table 2.5-1 Default Space Default space Program space Addressing mode PC indirect, program access, branch Data space Addressing mode using @RW0, @RW1, @RW4, or @RW5, @A, addr16, and dir Stack space Addressing mode using PUSHW, POPW, @RW3, or @RW7 Additional space Addressing mode using @RW2 or @RW6 Figure 2.5-1 is an example of a memory space divided into register banks. Figure 2.5-1 Physical Addresses of Each Space FFFFFFH Program space FF0000H FFH : PCB (Program bank register) B3H : ADB (Additional bank register) 92H : USB (User stack bank register) B3FFFFH Additional space Physical address B30000H 92FFFFH User stack space 920000H 68FFFFH Data space 680000H 68H : DTB (Data bank register) 4BFFFFH System stack space 4B0000H 4BH : SSB (System stack bank register) 000000H 35 CHAPTER 2 CPU 2.6 Multi-byte Data in Memory Space Data is written to memory from the low-order addresses. Therefore, for a 32-bit data item, the low-order 16 bits are transferred before the high-order 16 bits. If a reset signal is inputted immediately after the low-order bits are written, the highorder bits might not be written. ■ Multi-byte Data Allocation in Memory Space Figure 2.6-1 is a diagram of multi-byte data configuration in memory. The low-order eight bits of a data item are stored at address n, then address n+1, address n+2, address n+3, etc. Figure 2.6-1 Sample Allocation of Multi-byte Data in Memory MSB Address n H LSB 01010101 11001100 11111111 00010100 01010101 11001100 11111111 00010100 L ■ Accessing Multi-byte Data Fundamentally, accesses are made within a bank. For an instruction accessing a multi-byte data item, address FFFFH is followed by address 0000H of the same bank. Figure 2.6-2 is an example of an instruction accessing multi-byte data. Figure 2.6-2 Execution of MOVW A, 080FFFFH H AL before execution 80FFFFH ?? ?? 01H · · · 800000H 23H L 36 AL after execution 23H 01H CHAPTER 2 CPU 2.7 Registers The F2MC-16LX registers are largely classified into two types: special registers in the CPU and general-purpose registers in memory. The special registers are dedicated internal hardware of the CPU, and they have specific use defined by the CPU architecture. The general-purpose registers share the CPU address space with RAM. The general-purpose registers are the same as the special registers in that they can be accessed without using an address. The applications of the general-purpose registers can be specified by the user however, as is ordinary memory space. ■ Special Registers The F2MC-16LX CPU core has the following special registers: • Accumulator (A=AH:AL) : Two 16-bit accumulators (Can be used as a single 32-bit accumulator.) • User stack pointer (USP) : 16-bit pointer indicating the user stack area • System stack pointer (SSP) : 16-bit pointer indicating the system stack area • Processor status (PS) : 16-bit register indicating the system status • Program counter (PC) : 16-bit register holding the address of the program • Program bank register (PCB) : 8-bit register indicating the PC space • Data bank register (DTB) : 8-bit register indicating the DT space • User stack bank register (USB) : 8-bit register indicating the user stack space • System stack bank register (SSB): 8-bit register indicating the system stack space • Additional bank register (ADB) : 8-bit register indicating the AD space • Direct page register (DPR) : 8-bit register indicating a direct page Figure 2.7-1 is a diagram of the special registers. 37 CHAPTER 2 CPU Figure 2.7-1 Special Registers AH AL Accumulator USP User stack pointer SSP System stack pointer PS Processor status PC Program counter DPR Direct page register PCB Program bank register DTB Data bank register USB User bank register SSB System stack bank register ADB Additional data bank register 8 bits 16 bits 32 bits 38 CHAPTER 2 CPU ■ General-purpose registers The F2MC-16LX general-purpose registers are located from addresses 000180H to 00037FH (maximum configuration) of main storage. The register bank pointer (RP) indicates which of the above addresses are currently being used as a register bank. Each bank has the following three types of registers. These registers are mutually dependent as described in Figure 2.7-2 . • R0 to R7: 8-bit general-purpose register • RW0 to RW7: 16-bit general-purpose register • RL0 to RL3: 32-bit general-purpose register Figure 2.7-2 General-purpose Registers MSB LSB 16 bits 000180H RP x 10H Start address of general-purpose register RW0 Low-order RL0 RW1 RW2 RL1 RW3 R1 R0 RW4 R3 R2 RW5 R5 R4 RW6 R7 R6 RW7 RL2 RL3 High-order The relationship between the high-order and low-order bytes of a byte or word register is expressed as follows: RW (i+4) = R (i × 2+1) × 256+R (i × 2) [i=0 to 3] The relationship between the high-order and low-order bytes of RLi and RW can be expressed as follows: RL (i) = RW (i × 2+1) × 65536+RW (i × 2) [i=0 to 3] 39 CHAPTER 2 CPU 2.7.1 Accumulator (A) The accumulator (A) register consists of 2 16-bit arithmetic operation registers (AH and AL), and is used as a temporary storage for operation results and transfer data. ■ Accumulator (A) During 32-bit data processing, AH and AL are used together. Only AL is used for word processing in 16bit data processing mode or for byte processing in 8-bit data processing mode (see Figure 2.7-3 and Figure 2.7-4 ). The data stored in the A register can be operated upon with the data in memory or registers (Ri, Rwi, or RLi). In the same manner as with the F2MC-8L, when a word or shorter data item is transferred to AL, the previous data item in AL is automatically sent to AH (data preservation function). The data preservation function and operation between AL and AH help improve processing efficiency. When a byte or shorter data item is transferred to AL, the data is sign-extended or zero-extended and stored as a 16-bit data item in AL. The data in AL can be handled either as word or byte long. When a byte-processing arithmetic operation instruction is executed on AL, the high-order eight bits of AL before operation are ignored. The high-order eight bits of the operation result all become zeroes. The A register is not initialized by a reset. The A register holds an undefined value immediately after a reset. Figure 2.7-3 32-bit Data Transfer MOVL A,@RW1+6 A before execution MSB XXXXH XXXXH 8F74H 8FH 74H A6153EH 2BH 52H RW1 15H 38H +6 2B52H AH A61540H A6H DTB A after execution LSB AL Figure 2.7-4 AL-AH Transfer MSB MOVW A,@RW1+6 A before execution XXXXH 1234H DTB A6H LSB A61540H 8FH 74H A6153EH 2BH 52H RW1 15H 38H +6 A after execution 40 1234H 1234H CHAPTER 2 CPU 2.7.2 User Stack Pointer (USP) and System Stack Pointer (SSP) USP and SSP are 16-bit registers that indicate the memory addresses for saving and restoring data when a push/pop instruction or subroutine is executed. ■ User Stack Pointer (USP) and System Stack Pointer (SSP) The USP and SSP registers are used by stack instructions. The USP register is enabled when the S flag in the processor status register is “0”, and the SSP register is enabled when the S flag is “1” (see Figure 2.7-5 ). Since the S flag is set when an interrupt is accepted, register values are always saved in the memory area indicated by SSP during interrupt processing. SSP is used for stack processing in an interrupt routine, while USP is used for stack processing outside an interrupt routine. If the stack space is not divided, use only the SSP. During stack processing, the high-order eight bits of an address are indicated by SSB (for SSP) or USB (for USP). USP and SSP are not initialized by a reset. Instead, they hold undefined values. Figure 2.7-5 Stack Manipulation Instruction and Stack Pointer Example of PUSHW A when S flag is "0" Before execution AL S flag After execution AL MSB A624H USB C6H USP F328H 0 SSB 56H SSP 1234H USB C6H USP F326H SSB 56H SSP 1234H C6F326H A6H 24H A624H USB C6H USP F328H 561232H XX XX 1 SSB 56H SSP 1234H A624H USB C6H USP F328H 561232H A6H 24H 1 SSB 56H SSP 1232H A624H 0 C6F326H LSB XX XX System stack is used because S flag is "0". Example of PUSHW A when S flag is "1" AL AL System stack is used because S flag is "1". Note: Specify an even-numbered address in the stack pointer whenever possible. 41 CHAPTER 2 CPU 2.7.3 Processor Status (PS) The PS register consists of the bits controlling the CPU operation and the bits indicating the CPU status. ■ Processor Status (PS) As shown in Figure 2.7-6 , the high-order byte of the PS register consists of a register bank pointer (RP) and an interrupt level mask register (ILM). The ILM indicates the start address of a register bank. The loworder byte of the PS register is a condition code register (CCR), containing the flags to be set or reset depending on the results of instruction execution or interrupt occurrences. Figure 2.7-6 Processor Status (PS) Structure 15 13 PS 12 8 ILM 7 0 RP CCR ■ Condition Code Register (CCR) Figure 2.7-7 is a diagram of condition code register (CCR) configuration. Figure 2.7-7 Condition Code Register (CCR) Configuration Initial value 7 6 5 4 3 2 1 0 - I S T N Z V C - 0 1 * * * * * : CCR * : Undefined ● I: Interrupt enable flag: Interrupt requests other than software interrupts are enabled when the I flag is 1 and are masked when the I flag is 0. The I flag is cleared by a reset. ● S: Stack flag: When the S flag is 0, USP is enabled as the stack manipulation pointer. When the S flag is 1, SSP is enabled as the stack manipulation pointer. The S flag is set by an interrupt reception or a reset. 42 CHAPTER 2 CPU ● T: Sticky bit flag: 1 is set in the T flag when there is at least one "1" in the data shifted out from the carry after execution of a logical right/arithmetic right shift instruction. Otherwise, 0 is set in the T flag. In addition, "0" is set in the T flag when the shift amount is zero. ● N: Negative flag: The N flag is set when the MSB of the operation result is "1", and is otherwise cleared. ● Z: Zero flag: The Z flag is set when the operation result is all zeroes, and is otherwise cleared. ● V: Overflow flag: The V flag is set when an overflow of a signed value occurs as a result of operation execution and is otherwise cleared. ● C: Carry flag: The C flag is set when a carry-up or carry-down from the MSB occurs as a result of operation execution, and is otherwise cleared. ■ Register Bank Pointer (RP) The RP register indicates the relationship between the general-purpose registers of the F2MC-16LX and the internal RAM addresses. Specifically, the RP register indicates the first memory address of the currently used register bank in the following conversion expression: [00180H + (RP)*10H] (see Figure 2.7-8 ). The RP register consists of five bits, and can take a value between 00H and 1FH. Register banks can be allocated at addresses from 000180H to 00037H in memory. Even within that range, however, the register banks cannot be used as general-purpose registers if the banks are not in internal RAM. The RP register is initialized to all zeroes by a reset. An instruction may transfer an eight-bit immediate value to the RP register; however, only the low-order five bits of that data are used. Figure 2.7-8 Register Bank Pointer (RP) Initial value B4 B3 B2 B1 B0 0 0 0 0 0 : RP 43 CHAPTER 2 CPU ■ Interrupt level mask register (ILM) The ILM register consists of three bits, indicating the CPU interrupt masking level. An interrupt request is accepted only when the level of the interrupt is higher than that indicated by these three bits. Level 0 is the highest priority interrupt, and level 7 is the lowest priority interrupt (see Table 2.7-1 ). Therefore, for an interrupt to be accepted, its level value must be smaller than the current ILM value. When an interrupt is accepted, the level value of that interrupt is set in ILM. Thus, an interrupt of the same or lower level cannot be accepted subsequently. ILM is initialized to all zeroes by a reset. An instruction may transfer an eight-bit immediate value to the ILM register, but only the low-order three bits of that data are used. Figure 2.7-9 Interrupt Level Mask Register (ILM) Initial value ILM2 ILM1 ILM0 0 0 0 : ILM Table 2.7-1 Levels Indicated by the Interrupt Level Mask (ILM) Register 44 ILM2 ILM1 ILM0 Level value Acceptable interrupt level 0 0 0 0 Interrupt disabled 0 0 1 1 0 only 0 1 0 2 Level value smaller than 1 0 1 1 3 Level value smaller than 2 1 0 0 4 Level value smaller than 3 1 0 1 5 Level value smaller than 4 1 1 0 6 Level value smaller than 5 1 1 1 7 Level value smaller than 6 CHAPTER 2 CPU 2.7.4 Program Counter (PC) The PC register is a 16-bit counter that indicates the low-order 16 bits of the memory address of an instruction code to be executed by the CPU. The high-order eight bits of the address are indicated by the PCB. The PC register is updated by a conditional branch instruction, subroutine call instruction, interrupt, or reset. The PC register can also be used as a base pointer for operand access. ■ Program Counter (PC) Figure 2.7-10 shows the program counter. Figure 2.7-10 Program Counter PCB FEH PC ABCDH Next instruction to be executed FEABCDH 45 CHAPTER 2 CPU 2.8 Register Bank A register bank consists of eight words. The register bank can be used as the following general-purpose registers for arithmetic operations: byte registers R0 to R7, word registers RW0 to RW7, and long word registers RL0 to RL3. In addition, the register bank can be used as instruction pointers. RL0 to RL3 are used as the linear pointer that directly accesses entire space. ■ Register Bank Table 2.8-1 lists the functions of the registers. Table 2.8-2 indicates the relationship between the registers. In the same manner as for an ordinary RAM area, the register bank values are not initialized by a reset. The status before a reset is maintained. When the power is turned on, however, the register bank will have an undefined value. Table 2.8-1 Register Functions R0 to R7 Used as operands of instructions. Note: R0 is used as a counter for barrel shift and normalization instructions. RW0 to RW7 Used as pointers. Used as operands of instructions. Note: RW0 is used as a counter for string instructions. RL0 to RL3 Used as long pointers. Used as operands of instructions. Table 2.8-2 Relationship between Registers RW0 RL0 RW1 RW2 RL1 RW3 R0 R1 R2 R3 R4 R5 R6 R7 RW4 RL2 RW5 RW6 RL3 RW7 ● Direct page register (DPR) <Initial value: 01H> DPR specifies addr8 to addr15 of the instruction operands in direct addressing mode as shown in Figure 46 CHAPTER 2 CPU 2.8-1 . DPR is eight bits long, and is initialized to 01H by a reset. DPR can be read or written to by an instruction. Figure 2.8-1 Generating a Physical Address in Direct Addressing Mode DTB register αααααααα DPR register Direct address during instruction ββββββββ MSB 24-bit physical address γγγγγγγγ LSB ααααααααββββββββγγγγγγγγ ● Program counter bank register (PCB) <Initial value: Value in reset vector> ● Data bank register (DTB) <Initial value: 00H> ● User stack bank register (USB) <Initial value: 00H> ● System stack bank register (SSB) <Initial value: 00H> ● Additional data bank register (ADB) <Initial value: 00H> Each bank register indicates the memory bank where the PC, DT, SP (user), SP (system), or AD space is allocated. All bank registers are one byte long. PCB is initialized to 00H by a reset. Bank registers other than PCB can be read or written to. PCB can be read but cannot be written to. PCB is updated when the JMPP, CALLP, RETP, RETIQ, or RETF instruction branching to the entire 16M bytes space is executed or when an interrupt occurs. For operation of each register, see "2.2 Memory Space". 47 CHAPTER 2 CPU 2.9 Prefix Codes Placing a prefix code before an instruction partially changes the operation of the instruction. Three types of prefix codes can be used: bank select prefix, common register bank prefix, and flag change disable prefix. ■ Bank Select Prefix The memory space used for accessing data is determined for each addressing mode. When a bank select prefix is placed before an instruction, the memory space used for accessing data by that instruction can be selected regardless of the addressing mode. Table 2.9-1 lists the bank select prefixes and the corresponding memory spaces. Table 2.9-1 Bank Select Prefix Bank select prefix Selected space PCB PC space DTB Data space ADB AD space SPB Either the SSP or USP space is used according to the stack flag value. Use the following instructions with care: ● String instructions (MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW) The bank register specified by an operand is used regardless of the prefix. ● Stack manipulation instructions (PUSHW, POPW) SSB or USB is used according to the S flag regardless of the prefix. ● I/O access instructions MOVA,io/MOVio,A/MOVXA,io/MOVWA,io/MOVWio,A/MOVio,#imm8 MOVWio,#imm16/MOVBA,io:bp/MOVBio:bp,A/SETBio:bp/CLRBio:bp BBCio:bp,rel/BBSio:bp,rel/WBTC,WBTS The IO space of the bank is used regardless of the prefix. ● Flag change instructions (AND CCR,#imm8, OR CCR,#imm8) The instruction is executed normally, but the prefix affects the next instruction. ● POPW PS SSB or USB is used according to the S flag regardless of the prefix. The prefix affects the next instruction. 48 CHAPTER 2 CPU ● MOV ILM,#imm8 The instruction is executed normally, but the prefix affects the next instruction. ● RETI SSB is used regardless of the prefix. ■ Common Register Bank Prefix (CMR) To simplify data exchange between multiple tasks, the same register bank must be accessed relatively easily regardless of the RP value. When CMR is placed before an instruction that accesses a register bank, the register accessed by that instruction can be changed to the common bank (the register bank selected when RP=0) at addresses from 000180H to 00018FH regardless of the current RP value. Use the following instructions with care: ● String instructions (MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW) If an interrupt request occurs during execution of a string instruction with a prefix code, the prefix code becomes invalid when the string instruction is resumed after the interrupt is processed. Thus, the string instruction is executed falsely after the interrupt is processed. Do not prefix any of the above string instructions with CMR. ● Flag change instructions (AND CCR,#imm8, OR CCR,#imm8, POPW PS) The instruction is executed normally, but the prefix affects the next instruction. ● MOV ILM,#imm8 The instruction is executed normally, but the prefix affects the next instruction. ■ Flag Change Disable Prefix (NCC) To disable flag changes, use the flag change disable prefix code (NCC). Placing NCC before an instruction that suppresses unnecessary flag change disables flag changes associated with that instruction. Use the following instructions with care: ● String instructions (MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW) If an interrupt request occurs during execution of a string instruction with a prefix code, the prefix code becomes invalid when the string instruction is resumed after the interrupt is processed. Thus, the string instruction is executed incorrectly after the interrupt is processed. Do not prefix any of the above string instructions with NCC. ● Flag change instructions (AND CCR,#imm8, OR CCR,#imm8, POPW PS) The instruction is executed normally, but the prefix affects the next instruction. ● Interrupt instructions (INT #vct8, INT9, INT addr16, INTP addr24, RETI) CCR changes according to the instruction specifications regardless of the prefix. ● JCTX @A CCR changes according to the instruction specifications regardless of the prefix. 49 CHAPTER 2 CPU ● MOV ILM,#imm8 The instruction is executed normally, but the prefix affects the next instruction. 50 CHAPTER 2 CPU 2.10 Interrupt Disable Instructions Interrupt requests are not sampled for the following ten instructions: - MOV ILM,#imm8 - PCB - SPB - OR CCR,#imm8 - AND CCR,#imm8 - ADB - CMR - POPW PS - NCC - DTB ■ Interrupt Disable Instructions If a valid hardware interrupt request occurs during execution of any of the above instructions, the interrupt can be processed only when an instruction other than the above is executed. For details, see Figure 2.10-1 . Figure 2.10-1 Interrupt Disable Instruction Interrupt disable instruction •••••••• ••• (a) (a) Ordinary instruction Interrupt request Interrupt acceptance ■ Restrictions on Interrupt Disable Instructions and Prefix Instructions When a prefix code is placed before an interrupt disable instruction, the prefix code affects the first instruction after the code other than the interrupt disable instruction. For details, see Figure 2.10-2 . Figure 2.10-2 Interrupt Disable Instructions and Prefix Codes Interrupt disable instruction MOV A, FFH NCC •••• MOV ILM,#imm8 ADD A,01H CCR:XXX10XX CCR:XXX10XX CCR does not change with NCC. ■ Consecutive prefix codes When competitive prefix codes are placed consecutively, the latter becomes valid. In the figure below, competitive prefix codes are PCB, ADB, DTB, and SPB. For details, see Figure 2.10-3 . Figure 2.10-3 Consecutive Prefix Codes Prefix code ••••• ADB DTB PCB ADD A,01H ••••• PCB is valid as the prefix code. 51 CHAPTER 2 CPU 2.11 Precautions for Use of "DIV A, Ri" and "DIVW A, RWi" Instructions Set "00H" in the bank register before using the "DIV A, Ri" and "DIVW A, RWi" instructions. ■ Precautions for Use of "DIV A, Ri" and "DIVW A, RWi" Instructions Table 2.11-1 Precautions for Use of "DIVA,Ri" and "DIVWA,RWi" Instructions (i=0 to 7) Instruction Bank register name affected by the execution of the instructions listed on the left Address that stores the remainder DIVA,R0 (DTB: Upper 8 bits)+(0180H+RP × 10H+8H Lower 16 bits) DIVA,R1 (DTB: Upper 8 bits)+(0180H+RP × 10H+9H Lower 16 bits) DIVA,R4 (DTB: Upper 8 bits)+(0180H+RP × 10H+CH Lower 16 bits) (DTB: Upper 8 bits)+(0180H+RP × 10H+DH Lower 16 bits) DIVA,R5 DTB DIVWA,RW0 (DTB: Upper 8 bits)+(0180H+RP × 10H+0H Lower 16 bits) DIVWA,RW1 (DTB: Upper 8 bits)+(0180H+RP × 10H+2H Lower 16 bits) DIVWA,RW4 (DTB: Upper 8 bits)+(0180H+RP × 10H+8H Lower 16 bits) DIVWA,RW5 (DTB: Upper 8 bits)+(0180H+RP × 10H+AH Lower 16 bits) DIVA,R2 (ADB: Upper 8 bits)+(0180H+RP × 10H+AH Lower 16 bits) (ADB: Upper 8 bits)+(0180H+RP × 10H+EH Lower 16 bits) DIVA,R6 ADB DIVWA,RW2 (ADB: Upper 8 bits)+(0180H+RP × 10H+4H Lower 16 bits) DIVWA,RW6 (ADB: Upper 8 bits)+(0180H+RP × 10H+EH Lower 16 bits) DIVA,R3 (USB*2: Upper 8 bits)+(0180H+RP × 10H+BH Lower 16 bits) DIVA,R7 USB, SSB*1 (USB*2: Upper 8 bits)+(0180H+RP × 10H+FH Lower 16 bits) DIVWA,RW3 (USB*2: Upper 8 bits)+(0180H+RP × 10H+6H Lower 16 bits) DIVWA,RW7 (USB*2: Upper 8 bits)+(0180H+RP × 10H+EH Lower 16 bits) *1: Depends on the S bit of the CCR register *2: In the event that S bit of the CCR register is 0 If the value of the bank registers (DTB, ADB, USB, and SSB) is "00H", the remainder after division is stored in the register of the instruction operands. Otherwise, the upper eight bits is specified by the bank register corresponding to the register of the instruction operand, and the lower 16 bits is the same as the address of the register of the instruction operand. The remainder is stored in the bank register specified by the upper eight bits. 52 CHAPTER 2 CPU Example: If "DIV A,R0" is executed with DTB = "053H" and RP = "03H", the address of R0 is "0180H" + RP ("03H") × "10H" + "08H" (R0 corresponding address) = "0001B8H". Since the data bank register (DTB) is specified by "DIV A,R0" as the bank register, the remainder is stored in address "05301B8H", which was obtained by adding the bank address "053H". Note: For information about the bank register and Ri and RWi registers, see "2.7 Registers". ■ Use of the "DIV A, Ri" and "DIVW A, RWi" Instructions without Precautions To enable users to develop programs without having to take precautions for using the "DIV A,Ri" and "DIVW A,RWi" instructions, special compilers and assemblers are available. The special compiler does not generate the instructions in Table 2.11-1 . The special assemblers have a function that replaces the instructions in Table 2.11-1 with equivalent instruction strings. For the MB90360 series, use the following types of compilers and assemblers: ● Compiler • cc907 V02L06 or later version, or fcc907s V30L02 or later version ● Assembler • asm907a V03L04 or later version, or fasm907s V30L04 (Rev. 300004) or later version 53 CHAPTER 2 CPU 54 CHAPTER 3 INTERRUPTS This chapter explains the interrupts and function and operation of the extended intelligent I/O service in the MB90360 series. 3.1 Outline of Interrupts 3.2 Interrupt Vector 3.3 Interrupt Control Registers (ICR) 3.4 Interrupt Flow 3.5 Hardware Interrupts 3.6 Software Interrupts 3.7 Extended Intelligent I/O Service (EI2OS) 3.8 Operation Flow of and Procedure for Using the Extended Intelligent I/O Service (EI2OS) 3.9 Exceptions 55 CHAPTER 3 INTERRUPTS 3.1 Outline of Interrupts The F2MC-16LX has interrupt functions that terminate the currently executing processing and transfer control to another specified program when a specified event occurs. There are four types of interrupt functions: • Hardware interrupt: Interrupt processing due to an internal resource event • Software interrupt: Interrupt processing due to a software event occurrence instruction • Extended intelligent I/O service (EI2OS): Transfer processing due to an internal resource event • Exception: Termination due to an operation exception ■ Hardware Interrupts A hardware interrupt is activated by an interrupt request from an internal resource. A hardware interrupt request occurs when both the interrupt request flag and the interrupt enable flag in an internal resource are set. Therefore, an internal resource must have an interrupt request flag and interrupt enable flag to issue a hardware interrupt request. ● Specifying an interrupt level An interrupt level can be specified for the hardware interrupt. To specify an interrupt level, use the level setting bits (IL0, IL1, and IL2) of the interrupt controller. ● Masking a hardware interrupt request A hardware interrupt request can be masked by using the I flag of the processor status register (PS) in the CPU and the ILM bits (IL0, IL1, and IL2). When an unmasked interrupt request occurs, the CPU saves 12 bytes of data that consists of registers PS, PC, PCB, DTB, ADB, DPR, and A in the memory area indicated by the SSB and SSP registers. Figure 3.1-1 Overview of Hardware Interrupts PS Micro code IR ILM Check Comparator F2MC-16LX CPU AND Factor FF Interrupt level IL Peripheral Enable FF 56 I Level comparator F2MC-16LX bus Register file Interrupt controller PS I ILM IR : Processor status : Interrupt enable flag : Interrupt level mask register : Instruction register CHAPTER 3 INTERRUPTS ■ Software Interrupts Interrupts requested by executing the INT instruction are software interrupts. An interrupt request by the INT instruction does not have an interrupt request or enable flag. An interrupt request is issued always by executing the INT instruction. No interrupt level is assigned to the INT instruction. Therefore, ILM is not updated when the INT instruction is used. Instead, the I flag is cleared and the continuing interrupt requests are suspended. Figure 3.1-2 Overview of Software Interrupts F2MC-16LX bus Register file PS Micro code F2MC-16LX I S B unit IR Queue PS : Processor status I : Interrupt enable flag ILM : Interrupt level mask register IR : Instruction register B unit : Bus interface unit Fetch CPU Save Instruction bus RAM ■ Extended Intelligent I/O Service (EI2OS) The extended intelligent I/O service automatically transfers data between an internal resource and memory. This processing is traditionally performed by an interrupt processing program, but the EI2OS enables data to be transferred in a manner similar to a DMA (direct memory access) operation. To activate the extended intelligent I/O service function from an internal resource, the interrupt control register (ICR) of the interrupt controller must have an extended intelligent I/O service enable flag (ISE). The extended intelligent I/O service is started when an interrupt request occurs with 1 specified in the ISE flag. To generate a normal interrupt using a hardware interrupt request, set the ISE flag to 0. Figure 3.1-3 Overview of the Extended Intelligent I/O Service (EI2OS) Memory space IOA I/O register I/O register Peripheral Interrupt request CPU (3) ISD (3) (1) ICS (2) Interrupt control register Interrupt controller BAP (4) Buffer DCT (1) I/O requests transfer. (2) Interrupt controller selects descriptor. (3) Transfer source and destination are read from descriptor. (4) Data is transferred between I/O and memory. 57 CHAPTER 3 INTERRUPTS ■ Exceptions Exception processing is basically the same as interrupt processing. When an exception is detected between instructions, ordinary processing is suspended, and exception processing is performed. In general, exception processing occurs as a result of an unexpected operation. Therefore, use exception processing for debugging programs or for activating recovery software in an emergency. 58 CHAPTER 3 INTERRUPTS 3.2 Interrupt Vector An interrupt vector uses the same area for both hardware and software interrupts. For example, interrupt request number INT42 is used for a delayed hardware interrupt and for software interrupt INT #42. Therefore, the delayed interrupt and INT #42 call the same interrupt processing routine. Interrupt vectors are allocated between addresses FFFC00H and FFFFFFH as shown in Table 3.2-1 . ■ Interrupt Vector Table 3.2-1 Interrupt Vector (1/2) Interrupt request Interrupt cause Interrupt control register Number Address Vector address lower Vector address middle Vector address upper Mode register INT 0 * -- -- -- FFFFFCH FFFFFDH FFFFFEH Unused * -- -- -- FFFFF8H FFFFF9H FFFFFAH Unused -- -- -- . . . . . . . . . . . . -- -- -- FFFFE0H FFFFE1H FFFFE2H Unused INT 1 . . . INT 7 * INT 8 Reset -- -- FFFFDCH FFFFDDH FFFFDEH FFFFDFH INT 9 INT9 instruction -- -- FFFFD8H FFFFD9H FFFFDAH Unused INT 10 Exception processing -- -- FFFFD4H FFFFD5H FFFFD6H Unused INT 11 Reserved FFFFD0H FFFFD1H FFFFD2H Unused INT 12 Reserved FFFFCCH FFFFCDH FFFFCEH Unused INT 13 CAN1 reception FFFFC8H FFFFC9H FFFFCAH Unused INT 14 CAN1 transmission/ node status Reserved FFFFC4H FFFFC5H FFFFC6H Unused FFFFC0H FFFFC1H FFFFC2H Unused FFFFBCH FFFFBDH FFFFBEH Unused FFFFB8H FFFFB9H FFFFBAH Unused FFFFB4H FFFFB5H FFFFB6H Unused FFFFB0H FFFFB1H FFFFB2H Unused FFFFACH FFFFADH FFFFAEH Unused FFFFA8H FFFFA9H FFFFAAH Unused FFFFA4H FFFFA5H FFFFA6H Unused FFFFA0H FFFFA1H FFFFA2H Unused FFFF9CH FFFF9DH FFFF9EH Unused INT 15 INT 16 Reserved INT 17 Reserved INT 18 Reserved INT 19 16-bit reload timer 2 16-bit reload timer 3 Reserved INT 20 INT 21 INT 22 Reserved INT 23 PPG C/D INT 24 PPG E/F ICR00 0000B0H ICR01 0000B1H ICR02 0000B2H ICR03 0000B3H ICR04 0000B4H ICR05 0000B5H ICR06 0000B6H 59 CHAPTER 3 INTERRUPTS Table 3.2-1 Interrupt Vector (2/2) Interrupt request Interrupt cause Interrupt control register Number Address INT 25 Timebase timer 3 INT 26 External interrupt 8 to 11 Watch timer ICR07 0000B7H External interrupt 12 to 15 A/D converter ICR08 0000B8H ICR09 0000B9H INT 27 INT 28 INT 29 INT 30 I/O timer 0 INT 31 Reserved FFFF98H FFFF99H FFFF9AH Unused FFFF94H FFFF95H FFFF96H Unused FFFF90H FFFF91H FFFF92H Unused FFFF8CH FFFF8DH FFFF8EH Unused FFFF88H FFFF89H FFFF8AH Unused FFFF84H FFFF85H FFFF86H Unused FFFF80H FFFF81H FFFF82H Unused FFFF7CH FFFF7DH FFFF7EH Unused FFFF78H FFFF79H FFFF7AH Unused FFFF74H FFFF75H FFFF76H Unused FFFF70H FFFF71H FFFF72H Unused FFFF6CH FFFF6DH FFFF6EH Unused FFFF68H FFFF69H FFFF6AH Unused FFFF64H FFFF65H FFFF66H Unused FFFF60H FFFF61H FFFF62H Unused FFFF5CH FFFF5DH FFFF5EH Unused FFFF58H FFFF59H FFFF5AH Unused FFFF54H FFFF55H FFFF56H Unused 0000BBH ICR12 0000BCH ICR13 0000BDH ICR14 0000BEH ICR15 0000BFH -- -- -- FFFF50H FFFF51H FFFF52H Unused -- -- -- . . . . . . . . . . . . -- -- -- FFFC04H FFFC05H FFFC06H Unused -- -- -- FFFC00H FFFC01H FFFC02H Unused Input capture 0 to 3 INT 34 Reserved INT 35 UART 0 reception INT 36 UART 0 transmission INT 37 UART 1 reception INT 38 UART 1 transmission INT 39 Reserved INT 40 Reserved INT 41 Flash memory INT 255 Mode register ICR11 INT 33 . . . INT 254 Vector address upper 0000BAH Reserved INT 43 Vector address middle ICR10 INT 32 INT 42 Vector address lower Delayed interrupt generation module *: When PCB is FFH, the vector area for the CALLV instruction overlaps that for INT #vct8 (#0 to #7). Care must be taken when using the CALLV instruction. 60 CHAPTER 3 INTERRUPTS 3.3 Interrupt Control Registers (ICR) The interrupt control registers are in the interrupt controller. Each interrupt control register has a corresponding I/O that has an interrupt function. The interrupt control registers have the following 3 functions: • Setting an interrupt level for corresponding peripherals • Selecting whether to use an ordinary interrupt or extended intelligent I/O service for the corresponding peripherals • Selecting the extended intelligent I/O service channel Do not access an interrupt control register by using a read-modify-write instruction, as doing so causes a misoperation. ■ Interrupt Control Register (ICR) Figure 3.3-1 is a diagram of the bit configuration of an interrupt control register. Figure 3.3-1 Interrupt Control Register (ICR) 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0 ICS3 ICS2 ICS1 or S1 ICS0 or S0 ISE IL2 IL1 IL0 W W * * R/W R/W R/W R/W Interrupt control register 00000111B when reset *: '1' is read always. ICS1 and ICS0 are valid for write only. S1 and S0 are valid for read only. Note: ICS3 to ICS0 are valid only when EI2OS is activated. Set '1' in ISE to activate EI2OS, and set '0' in ISE not to activate it. When EI2OS is not to be activated, any value can be set in ICS3 to ICS0. [bit 10 to bit 8, bit 2 to bit 0] IL0, IL1, and IL2 (interrupt level setting bits) These bits are readable and writable and specify the interrupt level of the corresponding internal resources. Upon a reset, these bits are initialized to level 7 (no interrupt). Table 3.3-1 describes the relationship between the interrupt level setting bits and interrupt levels. 61 CHAPTER 3 INTERRUPTS Table 3.3-1 Interrupt Level Setting Bits and Interrupt Levels ILM2 ILM1 ILM0 Level 0 0 0 0 (strongest) 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 (weakest) 1 1 1 7 (no interrupt) [bit 11, bit 3] ISE (extended intelligent I/O service enable bits) The ISE bit is readable and writable. In response to an interrupt request, EI2OS is activated when '1' is set in the ISE bit and an interrupt sequence is activated when '0' is set in the ISE bit. Upon completion of EI2OS, the ISE bit is cleared to a zero. If the corresponding peripheral does not have the EI2OS function, the ISE bit must be set to '0' on the software side. Upon a reset, the ISE bit is initialized to '0'. 62 CHAPTER 3 INTERRUPTS [bit 15 to bit 12, bit 7 to bit 4] ICS 3 to ICS 0 (extended intelligent I/O service channel select bits) ICS3 to ICS0 are write-only bits. These bits specify the EI2OS channel. The values set in these bits determined the extended intelligent I/O service descriptor addresses in memory, which is explained later. The ICS bits are initialized to "0000B" by a reset. Table 3.3-2 describes the correspondence between the ICS bits, channel numbers, and descriptor addresses. Table 3.3-2 ICS Bits, Channel Numbers, and Descriptor Address ICS3 ICS2 ICS1 ICS0 Selected channel Descriptor address 0 0 0 0 0 000100H 0 0 0 1 1 000108H 0 0 1 0 2 000110H 0 0 1 1 3 000118H 0 1 0 0 4 000120H 0 1 0 1 5 000128H 0 1 1 0 6 000130H 0 1 1 1 7 000138H 1 0 0 0 8 000140H 1 0 0 1 9 000148H 1 0 1 0 10 000150H 1 0 1 1 11 000158H 1 1 0 0 12 000160H 1 1 0 1 13 000168H 1 1 1 0 14 000170H 1 1 1 1 15 000178H 63 CHAPTER 3 INTERRUPTS [bit 13, bit 12, bits 5, bit 4] S0 and S1 (extended intelligent I/O service status) S0 and S1 are read-only bits. The values set in these bits indicate the end condition of EI2OS. These bits are initialized to '00' upon a reset. Table 3.3-3 shows the relationship between the S bits and the end conditions. Table 3.3-3 S Bits and End Conditions 64 S1 S0 End conditions 0 0 EI2OS running or not activated 0 1 Stop status by count end 1 0 Reserved 1 1 Stop status by request from internal resource CHAPTER 3 INTERRUPTS 3.4 Interrupt Flow Figure 3.4-1 shows the interrupt flow. ■ Interrupt Flow Figure 3.4-1 Interrupt Flow I ILM IF IE ISE IL S START I & IF & IE = 1 AND ILM > IL : Flag in CCR : CPU register level : Internal resource interrupt request : Internal resource interrupt enable flag : EI2OS enable flag : Internal resource interrupt request level : Flag in CCR Yes Yes ISE = 1 No Fetching and decoding the next instruction INT instruction Yes No Saving PS, PC, PCB, DTB, DPR, and A into the stack of SSP, and setting ILM = IL Executing the extended intelligent I/O service No Executing an ordinary instruction No Saving PS, PC, PCB, DTB, ADB, DPR, and A into the stack of SSP, and setting I = O and ILM = IL Completion of string instruction repetition Yes Updating PC S 1 Fetching the interrupt vector 65 CHAPTER 3 INTERRUPTS Figure 3.4-2 Register Saving during Interrupt Processing Word (16 bits) "H" MSB LSB SSP (SSP value before interrupt) AH AL DPR ADB DPB PCB PC PS "L" 66 SSP (SSP value after interrupt) CHAPTER 3 INTERRUPTS 3.5 Hardware Interrupts In response to an interrupt request signal from an internal resource, the CPU pauses current program execution and transfers control to the interrupt processing program defined by the user. This function is called the hardware interrupt function. ■ Hardware Interrupts A hardware interrupt occurs when the relevant conditions are satisfied as a result of two operations: comparison between the interrupt request level and the value in the interrupt level mask register (ILM) of PS in the CPU, and hardware reference to the I flag value of PS. The CPU performs the following processing when a hardware interrupt occurs: • Saves the values in the PC, PS, AH, AL, PCB, DTB, ADB, and DPR registers of the CPU to the system stack. • Sets ILM in the PS register. The currently requested interrupt level is automatically set. • Fetches the corresponding interrupt vector value and branches to the processing indicated by that value. ■ Structure of Hardware Interrupt Hardware interrupts are handled by the following 3 sections: ● Internal resources Interrupt enable and request bits: Used to control interrupt requests from resources. ● Interrupt controller ICR: Assigns interrupt levels and determines the priority levels of simultaneously requested interrupts. ● CPU I and ILM: Used to compare the requested and current interrupt levels and to identify the interrupt enable status. Microcode: Interrupt processing step The status of these sections are indicated by the resource control registers for internal resources, the ICR for the interrupt controller, and the CCR value for the CPU. To use a hardware interrupt, set the three sections beforehand by using software. The interrupt vector table referred during interrupt processing is assigned to addresses FFFC00H to FFFFFFH in memory. These addresses are shared with software interrupts. "Table D-2 Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers" in "APPENDIX D List of Interrupt Vectors" shows the assignment of the MB90360 series. 67 CHAPTER 3 INTERRUPTS 3.5.1 Hardware Interrupt Operation An internal resource that has the hardware interrupt request function has an interrupt request flag and interrupt enable flag. The interrupt request flag indicates whether an interrupt request exists, and the interrupt enable flag indicates whether the relevant internal resource requests an interrupt to the CPU. The interrupt request flag is set when an event that is unique to the internal resource occurs. When the interrupt enable flag indicates "enable", the resource issues an interrupt request to the interrupt controller. ■ Hardware Interrupt Operation When two or more interrupt requests are received at the same time, the interrupt controller compares the interrupt levels (IL) in ICR, selects the request at the highest level (the smallest IL value), then reports that request to the CPU. If multiple requests are at the same level, the interrupt controller selects the request with the lowest interrupt number. The relationship between the interrupt requests and ICRs is determined by the hardware. The CPU compares the received interrupt level (IL) and the ILM in the PS register. If the interrupt level is smaller than the ILM value and the I bit of the PS register is set to '1', the CPU activates the interrupt processing microcode after the currently executing instruction is completed. The CPU refers the ISE bit of the ICR of the interrupt controller at the beginning of the interrupt processing microcode, checks that the ISE bit is 0 (interrupt), and activates the interrupt processing body. The interrupt processing body saves 12 bytes (PS, PC, PCB, DTB, ADB, DPR, and A) to the memory area indicated by SSB and SSP, fetches 3 bytes of interrupt vector, loads them onto PC and PCB, updates the ILM of PS to a level value of the received interrupt request, sets the S flag, then performs branch processing. As a result, the interrupt processing program defined by the user is executed next. 68 CHAPTER 3 INTERRUPTS 3.5.2 Occurrence and Release of Hardware Interrupt Figure 3.5-1 shows the processing flow from occurrence of a hardware interrupt to release of the interrupt request in an interrupt processing program. ■ Occurrence and Release of Hardware Interrupt Figure 3.5-1 Occurrence and Release of Hardware Interrupt PS Micro code IR I ILM Check PS I ILM IR : Processor status : Interrupt enable flag : Interrupt level mask register : Instruction register Comparator Peripheral • • • Enable FF AND Factor FF Interrupt level IL F2MC-16LX CPU Level comparator F2MC-16LX bus Register file Interrupt controller 1. An interrupt cause occurs in a peripheral. 2. The interrupt enable bit in the peripheral is referred. If interrupts are enabled, the peripheral issues an interrupt request to the interrupt controller. 3. Upon reception of the interrupt request, the interrupt controller determines the priority levels of simultaneously requested interrupts. Then, the interrupt controller transfers the interrupt level of the corresponding interrupt to the CPU. 4. The CPU compares the interrupt level requested by the interrupt controller with the ILM bit of the processor status register. 5. If the comparison shows that the requested level is higher than the current interrupt processing level, the I flag value of the same processor status register is checked. 6. If the check in step 5. shows that the I flag indicates interrupt enable status, the requested level is written to the ILM bit. Interrupt processing is performed as soon as the currently executing instruction is completed, then control is transferred to the interrupt processing routine. 7. When the interrupt cause of step 1. is cleared by software in the user interrupt processing routine, the interrupt request is completed. 69 CHAPTER 3 INTERRUPTS The time required for the CPU to execute the interrupt processing in steps 6. and 7. is shown below. See Table 3.5-1 for the cycle count compensation value. Interrupt start: 24 + 6 × (Table 3.3-2 machine cycles) Interrupt return: 15 + 6 × (Table 3.3-2 machine cycles) RETI instruction Table 3.5-1 Compensation Values for Interrupt Processing Cycle Count Address indicated by stack pointer 70 Cycle count compensation value Internal area, even-number address 0 Internal area, add-number address +2 CHAPTER 3 INTERRUPTS 3.5.3 Multiple interrupts As a special case, no hardware interrupt request can be accepted while data is being written to the I/O area. This is intended to prevent the CPU from operating falsely because of an interrupt request issued while an interrupt control register for a resource is being updated. If an interrupt occurs during interrupt processing, a higher-level interrupt is processed first. ■ Multiple Interrupts The F2MC-16LX CPU supports multiple interrupts. If an interrupt of a higher level occurs while another interrupt is being processed, control is transferred to the high-level interrupt after the currently executing instruction is completed. After processing of the high-level interrupt is completed, the original interrupt processing is resumed. An interrupt of the same or lower level may be generated while another interrupt is being processed. If this happens, the new interrupt request is suspended until the current interrupt processing is completed, unless the ILM value or I flag is changed by an instruction. The extended intelligent I/O service cannot be activated from multiple sources; while an extended intelligent I/O service is being processed, all other interrupt requests or extended intelligent I/O service requests are suspended. Figure 3.5-2 shows the order of the registers saved in the stack. Figure 3.5-2 Registers Saved in Stack Word (16 bits) MSB LSB "H" SSP (SSP value before interrupt) AH AL DPR ADB DPB PCB PC PS SSP (SSP value after interrupt) "L" 71 CHAPTER 3 INTERRUPTS 3.6 Software Interrupts In response to execution of a special instruction, control is transferred from the program currently executed by the CPU to the interrupt processing program defined by the user. This is called the software interrupt function. A software interrupt occurs always when the software interrupt instruction is executed. ■ Software Interrupts The CPU performs the following processing when a software interrupt occurs: • Saves the values in the PC, PS, AH, AL, PCB, DTB, ADB, and DPR registers of the CPU to the system stack. • Sets I in the PS register. Interrupts are automatically disabled. • Fetches the corresponding interrupt vector value, then branches to the processing indicated by that value. A software interrupt request issued by the INT instruction has no interrupt request or enable flag. A software interrupt request is always issued by executing the INT instruction. The INT instruction does not have an interrupt level. Therefore, the INT instruction does not update ILM. The INT instruction clears the I flag to suspend subsequent interrupt requests. ■ Structure of Software Interrupts Software interrupts are handled within the CPU: CPU.....Microcode: Interrupt processing step ■ List of Interrupt Vectors "Table D-1 Interrupt Vectors" in APPENDIX D lists the interrupt vectors of the MB90360 series. Software interrupts share the same interrupt vector area with hardware interrupts. For example, interrupt request number INT 12 is used for external interrupt #0 to #7 of a hardware interrupt as well as for INT #12 of a software interrupt. Therefore, external interrupt #0 and INT #12 call the same interrupt processing routine. ■ Software Interrupt Operation When the CPU fetches and executes the software interrupt instruction, the software interrupt processing microcode is activated. The software interrupt processing microcode saves 12 bytes (PS, PC, PCB, DTB, ADB, DPR, and A) to the memory area indicated by SSB and SSP. The microcode then fetches 3 bytes of interrupt vector and loads them onto PC and PCB, resets the I flag, and sets the S flag. Then, the microcode performs branch processing. As a result, the interrupt processing program defined by the user application program is executed next. Figure 3.6-1 illustrates the flow from the occurrence of a software interrupt until there is no interrupt request in the interrupt processing program. 72 CHAPTER 3 INTERRUPTS Figure 3.6-1 Occurrence and Release of Software Interrupt (1) PS F2MC-16LX bus Register file I (2) Micro code F2MC-16LX • CPU S B unit IR Queue Fetch PS I ILM IR : Processor status : Interrupt enable flag : Interrupt level mask register : Instruction register B unit : Bus interface unit Save Instruction bus RAM (1) The software interrupt instruction is executed. (2) Special CPU registers in the register file are saved according to the microcode corresponding to the software interrupt instruction. (3) The interrupt processing is completed with the RETI instruction in the user interrupt processing routine. ■ Others When the program bank register (PCB) is FFH, the CALLV instruction vector area overlaps the table of the INT #vct8 instruction. When designing software, ensure that the CALLV instruction does not use the same address as that of the #vct8 instruction. "Table D-2 Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers" in APPENDIX D shows the relationship of interrupt cause, interrupt vector, and interrupt control register in the MB90360 series. 73 CHAPTER 3 INTERRUPTS 3.7 Extended Intelligent I/O Service (EI2OS) The EI2OS function, a kind of hardware interrupt operation, automatically transfers data between input and output and memory. An interrupt processing program was conventionally used for such processing, but EI2OS enables data transfer to be performed like DMA (direct memory access). ■ Extended Intelligent I/O Service (EI2OS) EI2OS has the following advantages over the conventional method: • The program size can be small because it is not necessary to write a transfer program. • No internal register is used for transfer, eliminating the need for register saving and increasing the transfer speed. • Transfer can be terminated from I/O, preventing unnecessary data from being transferred. • The buffer address may either be incremented or left unupdated. • The I/O register address may either be incremented or left unupdated (buffer address is update). At the end of EI2OS, processing automatically branches to an interrupt processing routine after the end condition is set. Thus, the user can identify the end condition. To implement EI2OS, the hardware is distributed in two blocks. Each block has the following registers and descriptors. • Interrupt control register: Exists in the interrupt controller and indicates the ISD address. • Extended intelligent I/O service descriptor (ISD): Exists in RAM and holds the transfer mode, I/O address, number of transfers, and buffer address. Figure 3.7-1 outlines the extended intelligent I/O service. 74 CHAPTER 3 INTERRUPTS Figure 3.7-1 Outline of Extended Intelligent I/O Service Memory space by IOA I/O register ··· ··· ··· ··· ··· I/O register Peripheral CPU Interrupt request ISD by ICS Interrupt control register Interrupt controller by BAP I/O requests transfer. Interrupt controller selects descriptor. Buffer by DCT Transfer source and destination are read from descriptor. Data is transferred between I/O and memory. Note: • The area that can be specified by IOA is between 000000H and 00FFFFH. • The area that can be specified by BAP is between 000000H and FFFFFFH. • The maximum transfer count that can be specified by DCT is 65,536. ■ Structure EI2OS is handled by the following 4 sections: Internal resources Interrupt enable and request bits: Used to control interrupt requests from resources. Interrupt controller ICR: Assigns interrupt levels, determines the priority levels of simultaneously requested interrupts, and selects the EI2OS operation. CPU I and ILM: Used to compare the requested and current interrupt levels and to identify the interrupt enable status Microcode: EI2OS processing step RAM Descriptor: Describes the EI2OS transfer information. 75 CHAPTER 3 INTERRUPTS 3.7.1 Extended Intelligent I/O Service Descriptor (ISD) The extended intelligent I/O service descriptor exists between 000100H and 00017FH in internal RAM and consists of the following items: • Data transfer control data • Status data • Buffer address pointer ■ Extended Intelligent I/O Service Descriptor (ISD) Figure 3.7-2 shows the configuration of the extended intelligent I/O service descriptor. Figure 3.7-2 Extended Intelligent I/O Service Descriptor Configuration H High-order 8 bits of data counter (DCTH) Low-order 8 bits of data counter (DCTL) High-order 8 bits of I/O address pointer (IOAH) Low-order 8 bits of I/O address pointer (IOAL) EI2OS status (ISCS) High-order 8 bits of buffer address pointer (BAPH) ICS 000100H Midium-order 8 bits of buffer address pointer (BAPM) ISD start address Low-order 8 bits of buffer address pointer(BAPL) L ■ Data Counter (DCT) This is a 16-bit register that works as a counter corresponding to the number of data items transferred. This counter is decremented by one before data transfer. EI2OS is terminated when this counter reaches 0. Figure 3.7-3 is a diagram of the data counter configuration. Figure 3.7-3 Data Counter Configuration 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DCT B15 B14 B13 B12 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00 (Undefined when reset) 76 CHAPTER 3 INTERRUPTS ■ I/O register address pointer (IOA) This is a 16-bit register that indicates the low-order address (A15 to A0) of the buffer and I/O register used for data transfer. The high-order address (A23 to A16) are all zeroes, and any I/O between addresses 000000H and 00FFFFH can be specified. Figure 3.7-4 is a diagram of the IOA configuration. Figure 3.7-4 I/O Register Address Pointer Configuration 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IOA A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00 (Undefined when reset) ■ Buffer Address Pointer (BAP) This 24-bit register holds the address used for the next EI2OS transfer. BAP exists for each EI2OS channel. Therefore, each EI2OS channel can be used for transfer with anywhere in the 16M bytes space. If the BF bit of ISCS is set to '0' (update enabled), only the low-order 16 bits of BAP changes and BAPH does not change. 77 CHAPTER 3 INTERRUPTS 3.7.2 EI2OS Status Register (ISCS) This eight-bit register indicates the update direction (increment/decrement), transfer data format (byte/word), and transfer direction of the buffer address pointer and the I/O register address pointer. This register also indicates whether the buffer address pointer or I/O register address pointer is updated or fixed. ■ EI2OS Status Register (ISCS) Figure 3.7-5 is a diagram of the ISCS configuration. Be sure to write "0" in bit 7 to bit 5 of ISCS. Figure 3.7-5 ISCS Configuration 7 6 5 Reserved Reserved Reserved 4 IF 3 2 BW BF 1 0 DIR SE ISCS (Undefined when reset) Each bit is described below. [bit 4] IF: Specify whether the I/O register address pointer is updated or fixed. 0: The I/O register address pointer is updated after data transfer. 1: The I/O register address pointer is not updated after data transfer. Note: Only increment is allowed. [bit 3] BW: Specify the transfer data length. 0: Byte 1: Word [bit 2] BF: Specify whether the buffer address pointer is updated or fixed. 0: The buffer address pointer is updated after data transfer. 1: The buffer address pointer is not updated after data transfer. Note: Only the low-order 16 bits of the buffer address pointer are updated. Only increment is allowed. [bit 1] DIR: Specify the data transfer direction. 0: I/O --> Buffer 1: Buffer --> I/O [bit 0] SE: Control the termination of the extended intelligent I/O service based on internal resource requests. 0: The extended intelligent I/O service is not terminated by a internal resource request. 1: The extended intelligent I/O service is terminated by a internal resource request. 78 CHAPTER 3 INTERRUPTS 3.8 Operation Flow of and Procedure for Using the Extended Intelligent I/O Service (EI2OS) Figure 3.8-1 is a diagram of the EI2OS operation flow. Figure 3.8-2 is a diagram of the EI2OS use procedure. ■ EI2OS Operation Flow Figure 3.8-1 EI2OS Operation Flow BAP : : : ISCS : DCT : ISE : S1 and S0 : I/OA ISD Interrupt request issued from internal resource ISE = 1 Buffer address pointer I/O address pointer EI2OS descripter EI2OS status Data counter EI2OS enable bit EI2OS end status NO YES Interrupt sequence Reading ISD/ISCS End request from resource YES NO DIR = 1 SE = 1 YES NO Data indicated by IOA ⇓ (Data transfer) Memory indicated by BAP IF = 0 YES NO BF = 0 Data indicated by BAP ⇓ (Data transfer) Memory indicated by IOA Update value depends on BW. Updating IOA Update value depends on BW. Updating BAP YES NO Decrementing DCT DCT = 00 NO Setting S1 and S0 to "00" YES Setting S1 and S0 to "01" Setting S1 and S0 to "11" Clearing resource interrupt request Clearing ISE to "0" CPU operation return Interrupt sequence 79 CHAPTER 3 INTERRUPTS Figure 3.8-2 EI2OS Use Flow Processing by EI2OS Processing by CPU EI2OS initialization (Interrupt request) Normal termination AND (ISE=1) JOB execution Data transfer Count out or interrupt generation by end request from resource Setting of extended intelligent I/O service (Switching channels) Processing data in buffer The extended EI2OS execution time for each flow is described below. ● When data transfer continues (when the stop condition is not satisfied) (Figure 3.8-1 + Table 3.8-2 ) machine cycles ● When a stop request is issued from a resource (36 + 6 × Table 3.5-1 ) machine cycles ● When the counting is completed (Table 3.8-1 + Table 3.8-2 + (21 + 6 × Table 3.5-1 ) machine cycles Table 3.8-1 Execution Time when the EI2OS Continues ISCS SE bit Set to "0" I/O address pointer Set to "1" Fixed Updated Fixed Updated Fixed 32 34 33 35 Updated 34 36 35 37 Buffer address pointer 80 CHAPTER 3 INTERRUPTS Table 3.8-2 Data Transfer Compensation Values for EI2OS Execution Time Internal access I/O address pointer Buffer address pointer Internal access B/E O B/E 0 +2 O +2 +4 B: Byte data transfer E: Even address word transfer O: Odd address word transfer Table 3.8-3 Interrupt Handling Time Address pointed to by the stack pointer Compensation value [cycle] External 8 bits +4 External even-numbered address +1 External odd-numbered address +4 Internal even-numbered address 0 Internal odd-numbered address +2 81 CHAPTER 3 INTERRUPTS 3.9 Exceptions The F2MC-16LX performs exception processing when the following event occurs: ■ Execution of an Undefined Instruction Exception processing is fundamentally the same as interrupt processing. When an exception is detected between instructions, exception processing is performed separately from ordinary processing. In general, exception processing is performed as a result of an unexpected operation. Fujitsu recommends using exception processing for debugging or for activating emergency recovery software. ■ Exception Due to Execution of an Undefined Instruction The F2MC-16LX handles all codes that are not defined in the instruction map as undefined instructions. When an undefined instruction is executed, processing equivalent to the INT 10 software interrupt instruction is performed. Specifically, the AL, AH, DPR, DTB, ADB, PCB, PC, and PS values are saved into the system stack, and processing branches to the routine indicated by the interrupt number 10 vector. In addition, the I flag is cleared and the S flag is set. The PC value saved in the stack is the address at which the undefined instruction is stored. Processing can be restored by the RETI instruction, but is of no use, however, because the same exception occurs again. 82 CHAPTER 4 DELAYED INTERRUPT GENERATION MODULE This chapter explains the functions and operations of the delayed interrupt generation module. 4.1 Overview of Delayed Interrupt Generation Module 4.2 Block Diagram of Delayed Interrupt Generation Module 4.3 Configuration of Delayed Interrupt Generation Module 4.4 Explanation of Operation of Delayed Interrupt Generation Module 4.5 Precautions when Using Delayed Interrupt Generation Module 4.6 Program Example of Delayed Interrupt Generation Module 83 CHAPTER 4 DELAYED INTERRUPT GENERATION MODULE 4.1 Overview of Delayed Interrupt Generation Module The delayed interrupt generation module generates the interrupt for task switching. The hardware interrupt request can be generated/cancelled by software. ■ Overview of Delayed Interrupt Generation Module By using the delayed interrupt generation module, a hardware interrupt request can be generated or cancelled by software. Table 4.1-1 shows the overview of the delayed interrupt generation module. Table 4.1-1 Overview of Delayed Interrupt Generation Module Function and control 84 Interrupt factor An interrupt request is generated by setting the R0 bit in the delayed interrupt request generate/cancel register to 1 (DIRR: R0 = 1). An interrupt request is cancelled by setting the R0 bit in the delayed interrupt request generate/cancel register to 0 (DIRR: R0 = 0). Interrupt number #42 (2AH) Interrupt control An interrupt is not enabled by the DIRR register. Interrupt flag The interrupt flag is held in the R0 bit in the DIRR register. EI2OS The DIRR register does not correspond to the EI2OS. CHAPTER 4 DELAYED INTERRUPT GENERATION MODULE 4.2 Block Diagram of Delayed Interrupt Generation Module The delayed interrupt generation module consists of the following blocks: • Interrupt request latch • Delayed interrupt request generate/cancel register (DIRR) ■ Block Diagram of Delayed Interrupt Generation Module Figure 4.2-1 Block Diagram of Delayed Interrupt Generation Module Internal data bus R0 Delayed interrupt request generate/cancel register (DIRR) S Interrupt request R Latch Interrupt request signal − : Undefined ● Interrupt request latch This latch keeps the settings (delayed interrupt request generation or cancellation) of the delayed interrupt request generate/cancel register (DIRR). ● Delayed interrupt request generate/cancel register (DIRR) This register generates or cancels a delayed interrupt request. ■ Interrupt Number The interrupt number used in the delayed interrupt generation module is as follows: Interrupt number #42(2AH) 85 CHAPTER 4 DELAYED INTERRUPT GENERATION MODULE 4.3 Configuration of Delayed Interrupt Generation Module This section lists registers and reset values in the delayed interrupt generation module. ■ List of Registers and Reset Values Figure 4.3-1 List of Registers and Reset Values in Delayed Interrupt Generation Module Delayed interrupt request generate/cancel register (DIRR) Address: 00009FH × 86 :Undefined bit 15 14 13 12 11 10 × × × × × × 9 8 × 0 CHAPTER 4 DELAYED INTERRUPT GENERATION MODULE 4.3.1 Delayed interrupt request generate/cancel register (DIRR) The delayed interrupt request generate/cancel register (DIRR) generates or cancels a delayed interrupt request. ■ Delayed Interrupt Request Generate/cancel Register (DIRR) Figure 4.3-2 Delayed Interrupt Request Generate/cancel Register (DIRR) Address 15 14 13 12 11 10 9 00009FH − − R/W − − − − − − 8 Reset value R0 XXXXXXX0B R/W : Undefined bit8 : Read/Write R/W R0 : Reset value Delayed interrupt request generate bit 0 Release of delay interrupt request 1 Generation of delay interrupt request Table 4.3-1 Functions of Delayed Interrupt Request Generate/Cancel Register (DIRR) Bit name Function bit8 R0: Delayed interrupt request generate bit This bit generates or cancels a delayed interrupt request. When set to "0": Cancels delayed interrupt request When set to "1": Generates delayed interrupt request bit9 to bit15 Undefined bits Read: The value is undefined. Write: No effect 87 CHAPTER 4 DELAYED INTERRUPT GENERATION MODULE 4.4 Explanation of Operation of Delayed Interrupt Generation Module The delayed interrupt generation module has a function for generating or canceling an interrupt request by software. ■ Explanation of Operation of Delayed Interrupt Generation Module Using the delayed interrupt generation module requires the setting shown in Figure 4.4-1 . Figure 4.4-1 Setting for Delayed Interrupt Generation Module bit15 14 13 12 11 10 9 bit8 − − − − − − − R0 DIRR ❍ − : Undefined bit ❍ : Used bit When the R0 bit in the delayed interrupt request generate/cancel register (DIRR) is set to "1" (DIRR: R0 = 1), an interrupt request is generated. There is no interrupt request enable bit. ● Operation of delayed interrupt generation module • When the R0 bit in the delayed interrupt request generate/cancel register (DIRR) is set to "1", the interrupt request latch is set to "1" and an interrupt request is generated to the interrupt controller. • An interrupt request is generated to the CPU when the interrupt controller prioritizes the interrupt request over other requests. • When the interrupt level mask bit of the condition code register (CCR: ILM) is compared to the interrupt request level (ICR: IL), and the interrupt request level is higher than ILM, CPU executes the delayed interrupt processing after the instruction currently being executed is completed. • At interrupt processing, the user program sets the R0 bit to 0 to cancel the interrupt request and performs task switching. Figure 4.4-2 shows the operation of the delayed interrupt generation module. Figure 4.4-2 Operation of Delayed Interrupt Generation Module Delayed interrupt generation module Other request DIRR Interrupt controller ICR YY CPU IL CMP CMP ICR XX 88 ILM Interrupt processing CHAPTER 4 DELAYED INTERRUPT GENERATION MODULE 4.5 Precautions when Using Delayed Interrupt Generation Module This section explains the precautions when using the delayed interrupt generation module. ■ Precautions when Using Delayed Interrupt Generation Module • The interrupt processing is restarted at return from interrupt processing without setting the R0 bit in the delayed interrupt request generate/cancel register (DIRR) to "0" within the interrupt processing routine. • Unlike software interrupts, interrupts in the delayed interrupt generation module are delayed. 89 CHAPTER 4 DELAYED INTERRUPT GENERATION MODULE 4.6 Program Example of Delayed Interrupt Generation Module This section gives a program example of the delayed interrupt generation module. ■ Program Example of Delayed Interrupt Generation Module ● Processing specification The main program writes "1" to the R0 bit in the delayed interrupt request generate/cancel register (DIRR) to generate a delayed interrupt request and performs task switching. ● Coding example ICR15 DIRR ;Interrupt control register ;Delayed interrupt factor generate/ cancel register DIRR_R0 EQU DIRR:0 ;Delay interrupt request generating bit ;---------Main program-----------------------------------CODE CSEG START: ;Stack pointer (SP),already initialized AND CCR,#0BFH ;Interrupt disabled MOV I:ICR15,#00H ;Interrupt level 0 (strong) MOV ILM,#07H ;Setting ILM in PS to level 7 OR CCR,#40H ;Interrupt enabled SETB I:DIRR_R0 ;Delay interrupt request generating LOOP MOV A,#00H ;No limit loop MOV A,#01H BRA LOOP ;---------Interrupt program-------------------------------------WARI: CLRB I:DIRR_R0 ;Clear interrupt request flag : ; User processing ; : RETI ;Recovery from interrput CODE ENDS ;---------Vector setting----------------------------------------VECT CSEG ABS=0FFH ORG 0FF54H ;Setting vector to interrupt #42 (2AH) DSL WARI ORG 0FFDCH ;Reset vector setting DSL START DB 00H ;Setting to single-chip mode VECT ENDS END START 90 EQU EQU 0000BFH 00009FH CHAPTER 5 CLOCKS This chapter explains the clocks used by MB90360 series microcontrollers. 5.1 Clocks 5.2 Block Diagram of the Clock Generation Block 5.3 Clock Selection Register (CKSCR) 5.4 PLL/Subclock Control Register (PSCCR) 5.5 Clock Mode 5.6 Oscillation Stabilization Wait Interval 5.7 Connection of an Oscillator or an External Clock to the Microcontroller 91 CHAPTER 5 CLOCKS 5.1 Clocks The clock generation block controls the operation of the internal clock that controls operation of the CPU and peripheral functions. The clock generated by the clock generation block is called the machine clock. One cycle of machine clock is called one machine cycle. The clock to be supplied from a high-speed oscillator is called an oscillation clock, and the 2-frequency division of the oscillation clock is called a main clock. The 4- or 2-frequency division of the clock supplied from a low-speed oscillator or internal CR oscillation clock is called a sub-clock, and the clock by the PLL oscillation is called PLL clock. ■ Clocks The clock generation block contains the oscillation circuit that generates the oscillation clock by connecting oscillator to oscillation pin. External clock inputted to the oscillation pins can be used as oscillation clock. The clock generation block also contains the PLL clock multiplier circuit, which generates five clocks whose frequencies are multiplication of the oscillation clock frequency. The clock generation block controls the oscillation stabilization wait interval and PLL clock multiplication as well as internal clock operation by changing the clock with a clock selector. ● Oscillation clock (HCLK) The oscillation clock is generated either by connecting the oscillator to high-speed oscillator pins (X0,X1) or by the input of an external clock. ● Main clock (MCLK) The main clock, whose frequency is the oscillation clock frequency divided by 2, supplies the clock input to the timebase timer and the clock selector. ● Sub-clock (SCLK) The sub-clock is a clock by connecting the oscillator to the low-speed oscillation pins (X0A, X1A) or by inputting the external clock or the internal CR oscillation clock divided by 4 or 2. The division ratio of subclock is determined by SCDS bit of PLL/Subclock Control Register (PSCCR). The sub-clock can be used as operation clock of the watch timer or the low-speed machine clock. ● PLL clock (PCLK) The PLL clock is obtained by multiplying the oscillation clock frequency with the PLL clock multiplier circuit (PLL oscillation circuit). One of five types of clocks can be selected by setting the multiplication ratio selection bits (CKSCR: CS1, CS0, PSCCR: CS2) 92 CHAPTER 5 CLOCKS ● Machine clock The machine clock controls the operation of the CPU and peripheral functions. One cycle of machine clock is regarded as one machine cycle (1/φ). An operating machine clock can be selected from among the main clock, sub-clock, and five types of PLL clock. Note: When the operating voltage is 5 V, the oscillation clock can be between 3 MHz and 16 MHz. When an external clock source is used, its frequency can be between 3 MHz and 24 MHz. The highest operating frequency for the CPU and peripheral resource is 24 MHz. However, normal operation is not guaranteed if a multiplication ratio resulting in a higher frequency than 24 MHz is specified. Therefore, when 24 MHz external clock is inputted, 1 can be specified for the PLL clock multiplication ratio. The PLL oscillation operates at the range of 4 MHz to 24 MHz, but the PLL oscillation range differs by operation voltage and multiplication ratio. See the data sheet for the details. 93 CHAPTER 5 CLOCKS ■ Clock Supply Map Since the machine clock generated in the clock generation block is supplied as the clock that controls the operation of the CPU and peripheral functions, the operation of the CPU and the peripheral functions is affected by switching between the main clock, the PLL clock and the subclock (clock mode) and by a change in the PLL clock multiplication ratio. Since some peripheral functions receive frequency-divided output from the timebase timer, a peripheral unit can select the clock best suited for this operation. Figure 5.1-1 shows the clock supply map. Figure 5.1-1 Clock Supply Map Peripheral function 4 Watch timer 4 Watchdog timer Timebase timer 8/16-bit PPG timer C to F Clock control block 1 2 3 4 6 16-bit reload timer 2, 3 PLL multiplication circuit X0A Pin X1A Pin X0 Pin X1 Pin PCLK(PLL clock) Clock generator Clock selector Clock selector 4/2-divided CAN1 fc A/D converter (16ch) SCLK (sub clock) Clock selector Clock generator Internal CR oscillation clock 2-divided HCLK (oscillation clock) Pin PPGC to F Clock selector UART0 to 1+ serial I/O f (machine clock) Pin TIN2, TIN3 Pin TOT0 to 3 Pin RX1 Pin TX1 Pin AN0 to AN15 Pin SCK0, SCK1 Pin SIN0, SIN1 Pin SOT0, SOT1 I/O timer Free-run timer 0,1 Clock supervisor function CPU Input capture 0 to 3 HCLK : Oscillation clock MCLK : Main clock PCLK : PLL clock SCLK : Sub clock f : Machine clock fc : CAN0 to CAN2 clock 94 4 Oscillation stabilization wait control Pin IN0 to IN3 CHAPTER 5 CLOCKS 5.2 Block Diagram of the Clock Generation Block The clock generation block consists of five blocks: • System clock generation circuit/sub-clock generation circuit • PLL multiplier circuit • Clock selector • Clock selection register (CKSCR) • PLL/sub-clock control register (PSCCR) • Oscillation stabilization wait interval selector ■ Block Diagram of the Clock Generation Block Figure 5.2-1 shows a block diagram of the clock generation block. The figure also includes the standby control circuit and timebase timer circuit. Figure 5.2-1 Block Diagram of the Clock Generation Block Low-Power consumption Mode Control Register(LPMCR) STP SLP SPL RST TMD CG1 CG0 Reserved Terminal high impedance Control circuit RST Internal reset generator Pin CPU intermittent operation cycle selector CPU operating clock Time, sleep, stop sign Standby Control circuit 2 Internal reset Select the intermitted cycle CPU clock Control circuit Reset (Clear) Pin High-z control Time, stop sign Interrupt (Clear) Peripheral Clock Control circuit Clock generator Peripheral function operating clock Subclock oscillation stabilization wait clear Main clock oscillation stabilization wait clear Operation clock selector Machine Clock 2 CS2 PLL/Subclock Control register (PSCCR):bit8 Oscillation stabilization wait time selector 2 PLL multiplier circuit SCM MCM WS1 WS0 SCS MCS CS1 CS0 Clock selection register (CKSCR) Clock selector X0 Pin X1 Pin oscillation clock oscillation circuit X0A Pin 2divided oscillation clock (HCLK) 512- 4- divided Main divided clock Timebase timer 2divided 2divided 4-divided/ 2-divided 1024 -divided 2divided 2divided 4divided To watchdog timer Subclock (SCLK) Clock selector 2divided 8divided 2divided 2divided Clock timer X1A Pin SCDS Internal CR oscillation clock Subclock oscillation circuit Clock supervisor function PLL/Subclock control register (PSCCR):bit10 95 CHAPTER 5 CLOCKS ● Oscillation clock generation circuit This circuit generates an oscillation clock (HCLK) by connecting an oscillator or inputting an external clock to the high-speed oscillation pins. ● Sub-clock generation circuit This circuit generates a sub clock (SCLK) by connecting an oscillator or inputting an external clock to the low-speed oscillation pins (X0A, X1A). ● PLL multiplier circuit This circuit multiplies the oscillation clock and supplies it as a PLL clock (PCLK) to the clock selector. ● Clock selector From among the main clock, five different PLL clocks and subclock, the clock selector selects the clock that is supplied to the CPU and peripheral function. ● Clock selection register (CKSCR) The clock selection register is used to switch between the oscillation clock and PLL clock and between the main clock and sub-clock, also used to select an oscillation stabilization wait interval and a PLL clock multiplier. ● PLL/Subclock Control Register (PSCCR) The PLL/subclock control register is used to select multiplication ratio of the PLL (CS2 bit in this register in addition to CS1 and CS0 bits in the CKSCR register) and to specify division ratio (1/4 or 1/2) of the subclock. ● Oscillation stabilization wait interval selector This oscillation stabilization wait interval selector selects an oscillation stabilization wait interval for the oscillation clock. Selection is made from among four different timebase timer outputs. 96 CHAPTER 5 CLOCKS 5.2.1 Register of Clock Generation Block This section explains the register of the clock generation block. ■ Clock Selection Register and List of Reset Value Figure 5.2-2 Clock Selection Register and List of Reset Value 15 14 13 12 11 10 9 8 Clock selection register (CKSCR) 1 1 1 1 1 1 0 0 PLL/subclock control register (PSCCR) - - - - 0 0 0 0 97 CHAPTER 5 CLOCKS 5.3 Clock Selection Register (CKSCR) The clock selection register (CKSCR) is used to switch among the main clock, PLL clocks and subclock, also used to select an oscillation stabilization wait interval and a PLL clock multiplier. ■ Configuration of the Clock Selection Register (CKSCR) Figure 5.3-1 Configuration of the Clock Selection Register (CKSCR) Address 15 14 13 0000A1H SCM MCM WS1 R R 12 11 10 9 8 Reset value WS0 SCS MCS CS1 CS0 11111100B R/W R/W R/W R/W R/W R/W CS2 CS2(PSCCR register: bit8) bit9 bit8 CS1 CS0 Multiplication rate select bit Parenthesized values are examples calculated at an oscillation clock (HCLK) frequency of 4 MHz. 0 0 0 1 × HCLK (4 MHz) 0 0 1 2 × HCLK (8 MHz) 0 1 0 3 × HCLK (12 MHz) 0 1 1 4 × HCLK (16 MHz) 1 1 0 6 × HCLK (24 MHz) 1 1 1 Setting disabled bit10 MCS PLL clock select bit 0 Select PLL clock 1 Select main clock bit11 SCS Sub clock select bit 0 Select sub clock 1 Select main clock bit13 bit12 WS1 WS0 Oscillation stabilization wait time select bit Parenthesized values are examples calculated at an oscillation clock (HCLK) frequency of 4 MHz. 0 0 210/HCLK (approx. 256 µs) 0 1 213/HCLK (approx. 2.05 ms) 1 0 217/HCLK (approx. 32.77 ms) 1 1 215/HCLK (approx. 8.19 ms, other than power-on reset) 216/HCLK (approx. 16.38 ms, power-on reset only) bit14 MCM PLL clock operation bit 0 Operating in PLL clock 1 Operating in main clock or sub clock bit15 SCM HCLK 0 Operating in sub clock R/W : Read/Write 1 Operating in main clock or PLL clock R : Read only : Reset value 98 Sub clock operation bit : Oscillation clock CHAPTER 5 CLOCKS Table 5.3-1 Functions of Clock Selection Register (CKSCR) (1/2) Bit name Function bit15 SCM: The bit indicates the main clock or subclock currently selected as the machine clock. Sub clock operation When the sub clock operation flag bit (CKSCR: SCM) is "0" and the sub clock select bit flag bit (CKSCR: SCS) is "1", it indicates that the machine clock is currently switching from subclock to main clock. When the sub clock operation flag bit (CKSCR: SCM) is "1" and the sub clock select bit (CKSCR: SCS) is "0", it indicates that the machine clock is currently switching from main clock to subclock. (The writing operation will not be affected.) bit14 MCM: The bit indicates the main clock or PLL clock currently selected as the machine clock. PLL clock operation When the PLL clock operation flag bit (CKSCR: MCM) is "1" and the PLL clock select bit flag bit (CKSCR: MCS) is "0", it indicates that the oscillation stabilization wait time of the PLL clock is currently being taken. (The writing operation will not be affected.) bit13 bit12 WS1, WS0: Oscillation stabilization wait time select bits These bits are used to select an oscillation stabilization wait time required for the oscillation clock when the stop mode is canceled, when transition occurs from subclock mode to main clock mode, or when transition occurs from subclock mode to PLL clock mode. These bits are used to select one from four timebase timer outputs. Any reset causes the bit to return to the reset value. Note: Set the oscillation stabilization wait time to an appropriate value depending on the oscillator used. See 7.2.1 Reset Factors and Oscillation Stabilization Wait Times. The oscillation stabilization wait time taken when the clock mode is switched from main clock to PLL clock is fixed at 214/HCLK (about 4.1 ms during operation at an oscillation clock frequency of 4 MHz).When the CPU switches from subclock mode to PLL clock mode or when it returns from PLL stop mode to PLL clock mode, the oscillation stabilization wait time follows the values specified in these bits. The PLL clock requires an oscillation stabilization wait time of at least 214/HCLK. For switching from subclock mode to PLL clock mode and transiting to the PLL stop mode, therefore, set these bits to "10B" or "11B". bit11 SCS: Sub clock select bit This bit indicates the main clock or sub clock to be selected as the machine clock. When the machine clock is switched from the main clock to the subclock (CKSCR: SCS = 1 → 0), the main clock mode changes to the subclock mode of 1/SCLK (32.768 kHz oscillation clock frequency, operating at 4 division: approx. 130 µs) in synchronization with the subclock. When the machine clock is switched from the subclock to the main clock (CKSCR: SCS = 0 → 1), the clock mode changes from subclock mode to main clock mode after the main clock oscillation stabilization wait time is generated.Timebase timer is cleared automatically. Any reset causes the bit to return to the reset value. Notes: 1) When both of the MCS and SCS bits contain 0, the SCS bit supersedes the MCS bit, thereby setting the subclock mode. 2) If both the subclock select bit (CKSCR: SCS) and PLL clock select bit (CKSCR: MCS) contain 0, the sub clock is preferred. 3) When switching from the main clock to subclock (CKSCR: SCS = 1 → 0), use the timebase timer interrupt enable bit (TBTC: TBIE) or interrupt level mask register (ILM: ILM2 to 0) to disable timebase timer interrupts before writing 0 to the subclock select bit. 4) The 214/SCLK sub clock oscillation stabilization wait time (32.768 kHz oscillation clock frequency, operating at 4 division: approx. 2 s) is generated at power on or at cancellation of the stop mode.If the clock mode is switched from main clock mode to subclock mode, therefore, the oscillation stabilization wait time is generated. 99 CHAPTER 5 CLOCKS Table 5.3-1 Functions of Clock Selection Register (CKSCR) (2/2) Bit name Function bit10 MCS: This bit indicates the main clock or PLL clock to be selected as the machine clock. PLL clock select bit When the machine clock is switched from the main clock to the PLL clock (CKSCR: MCS = 1 → 0), the clock mode changes from main clock mode to PLL clock mode after the PLL clock oscillation stabilization wait time is generated.The timebase timer is cleared automatically.The oscillation stabilization wait time taken when the clock mode is switched from main clock to PLL clock is fixed at 214/HCLK (about 4.1 ms during operation at an oscillation clock frequency of 4 MHz).The oscillation stabilization wait time taken when the machine clock is switched from subclock mode to PLL clock mode follows the values specified in the oscillation stabilization wait time select bits (CKSCR: WS1, WS0). Any reset causes the bit to return to the reset value. Notes: 1) When both of the MCS and SCS bits contain 0, the SCS bit supersedes the MCS bit, thereby setting the subclock mode. 2) When switching from the main clock to PLL clock (CKSCR: MCS = 1 → 0), use the timebase timer interrupt enable bit (TBTC: TBIE) or interrupt level mask register (ILM: ILM2 to 0) to disable timebase timer interrupts before writing 0 to the PLL clock select bit. bit9 bit8 CS1, CS0: Multiplication rate select bits These bits select the PLL clock multiplication rate with the CS2 bit in the PLL/subclock control register (PSCCR). One of five types of PLL clock multiplication rate can be selected. Any reset causes the bit to return to the reset value. Setting of CS0, CS1, and CS2 CS2 CS1 CS0 PLL clock multiplication rate 0 0 0 ×1 0 0 1 ×2 0 1 0 ×3 0 1 1 ×4 1 1 0 ×6 1 1 1 Setting disabled Note: Setting CS2 to CS0 bits to "111B" is prohibited. When PSCCR: CS2 is set to "1", do not set CKSCR: CS1 and CS0 to "11B". When the PLL clock is selected (CKSCR: MCS = 0), writing is inhibited. To change the multiplier, write 1 to the PLL clock select bit (CKSCR: MCS), update the multiplication rate select bits (CKSCR: CS1, CS0), then set the PLL clock select bit (CKSCR: MCS) back to 0. 100 CHAPTER 5 CLOCKS 5.4 PLL/Subclock Control Register (PSCCR) PLL/Subclock control register selects the PLL multiplication rate and subclock division rate. This register is write only. Read value of all bits is set to "1". ■ Configuration of the PLL/Subclock Control Register (PSCCR) Figure 5.4-1 shows the configuration of the PLL/Subclock control register (PSCCR). Table 5.4-1 shows the function of each bit in the PLL/subclock control register (PSCCR). Figure 5.4-1 Configuration of the PLL/Subclock Control Register (PSCCR) Address 0000CFH 15 11 10 9 − 14 − 13 − 12 − Reserved SCDS Reserved 8 CS2 Reset value − − − − W W W W XXXX0000B bit8 CS2 0 1 Multiplication rate selection bit See the clock selection register (CKSCR). bit9 Reserved bit Reserved 0 Always write "0" to this bit. Read value is always "1". bit10 : Write only SCDS X : Undefined 0 4 division − : Unused 1 2 division W : Initial value Subclock division selection bit bit11 Reserved 0 Reserved bit Always write "0" to this bit. Read value is always "1". 101 CHAPTER 5 CLOCKS Table 5.4-1 Functional Description of Each Bit in the PLL/subclock Control Register (PSCCR) Bit name Function bit15 to bit12 Unused These bits are not used. Writing to these bits has no effect to operation. Read value is always "1". bit11 Reserved bit Always write "0" to this bit. Read value is always "1". bit10 SCDS: Subclock division selection bit The division ratio of the subclock is selected. When "0" is written to this bit, 4 division is selected. When "1" is written to this bit, 2 division is selected. Read value is always "1". This bit is initialized to "0" by all reset causes. bit9 Reserved bit Always write "0" to this bit. Read value is always "1". bit8 CS2: Multiplication rate selection bit This bit and CS1 and CS0 bits of the clock selection register (CKSCR) determine the PLL multiplication rate. CS2 CS1 CS0 PLL clock multiplication rate 0 0 0 ×1 0 0 1 ×2 0 1 0 ×3 0 1 1 ×4 1 1 0 ×6 1 1 1 Setting disabled Read value is always "1". This bit is initialized to "0" by all reset causes. Note: When MCS or MCM bit is "0", setting CS2 to CS0 to "111B" is prohibited. When CKSCR: CS1 and CS0 is set to "11B", do not set "1" to this bit. Note: PSCCR register is write-only register. Read value is different from writing value. Do not use the RMW instruction (SETB/CLRB instruction). 102 CHAPTER 5 CLOCKS 5.5 Clock Mode Three clock modes are provided: main clock mode, PLL clock mode and sub-clock mode. ■ Clock Mode ● Main clock mode In main clock mode, a clock with 2-frequency division of the clock generated by connecting on oscillator or by inputting from external to the high-speed oscillation pins (X0, X1) is used. ● Sub-clock mode In sub-clock mode, a clock with 4/2-frequency division of the clock generated by connecting an oscillator or inputting from external, or the internal CR oscillation clock to the low-speed oscillation pins (X0A, X1A) is used. The subclock division ratio is determined by SCDS bit of PLL/subclock control register (PSCCR). ● PLL clock mode In PLL clock mode, a PLL clock is used as the operating clock for the CPU and peripheral resources. A PLL clock multiplier is selected with the clock selection register (CKSCR: CS1 and CS0) and PLL/ subclock control register (PSCCR: CS2). ■ Clock Mode Transition Transition among main clock mode, PLL clock mode, and sub-clock mode is performed by writing to the MCS and SCS bits of the clock selection register (CKSCR). ● Transition from main clock mode to PLL clock mode When the MCS bit of the clock selection register (CKSCR) is rewritten from “1” to “0” in main clock mode, switching from the main clock to a PLL clock occurs after the PLL clock oscillation stabilization wait interval (214/HCLK). ● Transition from PLL clock mode to main clock mode When the MCS bit of the clock selection register (CKSCR) is rewritten from “0” to “1” in PLL clock mode, switching from the PLL clock to the main clock occurs when the edges of the PLL clock and the main clock coincide (after 1 to 12 PLL clocks). ● Transition from main clock mode to sub-clock mode When the SCS bit of the clock selection register (CKSCR) is rewritten from “1” to “0” in main clock mode, switching from the main clock to a sub-clock occurs by synchronizing with the subclock. 103 CHAPTER 5 CLOCKS ● Transition from sub-clock mode to main clock mode When the SCS bit of the clock selection register (CKSCR) is rewritten from “0” to “1” in sub-clock mode, switching from the sub-clock to the main clock occurs after the main clock oscillation stabilization wait interval. ● Transition from PLL clock mode to sub-clock mode When the SCS bit of the clock selection register (CKSCR) is rewritten from “1” to “0” in PLL clock mode, switching from the PLL clock to the sub-clock occurs. ● Transition from sub-clock mode to PLL clock mode When the SCS bit of the clock selection register (CKSCR) is rewritten from “0” to “1” in sub-clock mode, switching from the sub-clock to a PLL clock occurs after the main clock oscillation stabilization wait interval. ■ Selection of a PLL Clock Multiplier Writing the value from “000B” to “011B” and “110B” to the CS1 and CS0 bits of the clock selection register (CKSCR) and CS2 bit of the PLL/subclock control register (PSCCR) can select five types (1 to 4 multiplication and 6 multiplication) of PLL clock multiplier. ■ Machine Clock PLL clock, main clock, and sub-clock outputted from the PLL multiplier circuit are used as machine clock. This machine clock is supplied to the CPU and peripheral functions. The main clock, PLL clock, or subclock can be selected by writing to the MCS or SCS bit of the clock selection register (CKSCR). Notes: Even though the MCS and SCS bits of the clock selection register (CKSCR) are rewritten, machine clock switching does not occur immediately. When operating a resource that depends on the machine clock, confirm that machine clock switching has been performed by referring to the MCM and SCM bits of the clock selection register (CKSCR) before operating the resource. When the MCS bit of the clock selection register (CKSCR) is "0" (PLL clock mode) and when the SCS bit of the clock selection register (CKSCR) is "0" (sub-clock mode), the SCS bit is prioritized, and a transition to the sub-clock mode is occurred. When the clock mode is switched, do not switch to other clock mode and low-power consumption mode before this switching is completed. Confirm the completion of clock mode switching by referring to the MCM and SCM bits of the clock selection register (CKSCR). If switching to other clock mode and low-power consumption mode is performed before a transition is completed, the mode may not be switched. 104 CHAPTER 5 CLOCKS Figure 5.5-1 shows the status change caused by machine clock switching. Figure 5.5-1 Status Change Diagram for Machine Clock Selection Main MCS = 1 MCM = 1 SCS = 1 SCM = 1 CS1, CS0 = xxB CS2=x (10) (12) (20) (13) (8) (9) (9) (9) (9) (11) (1) Main --> PLLx MCS = 0 MCM = 1 SCS = 1 SCM = 1 CS1, CS0 = xxB CS2=x (9) Main --> Sub MCS = 1 MCM = 1 SCS = 0 SCM = 1 CS1, CS0 = xxB CS2=x (2) (3) (4) (5) (6) Sub --> Main MCS = 1 MCM = 1 SCS = 1 SCM = 0 CS1, CS0 = xxB CS2=x (12) Sub MCS = X MCM = 1 SCS = 0 SCM = 0 CS1, CS0 = xxB CS2=x (11) (10) (14) (15) (16) (17) (18) Sub --> PLL MCS = 0 MCM = 1 SCS = 1 SCM = 0 CS1, CS0 = xxB CS2=0 PLL1 --> Main MCS = 1 MCM = 0 SCS = 1 SCM = 1 CS1, CS0 = 00B CS2=0 PLL1: Multiplied MCS = 0 MCM = 0 SCS = 1 SCM = 1 (8) CS1, CS0 = 00B (10) CS2=0 PLL1 --> Sub MCS = 1 MCM = 0 SCS = 0 SCM = 1 CS1, CS = 00B CS2=0 PLL2 --> Main MCS = 1 MCM = 0 SCS = 1 SCM = 1 CS1, CS0 = 01B CS2=0 PLL2: Multiplied MCS = 0 MCM = 0 SCS = 1 (10) (8) SCM = 1 CS1, CS0 = 01B CS2=0 PLL2 --> Sub (21) MCS = 1 MCM = 0 SCS = 0 SCM = 1 CS1, CS0 = 01B CS2=0 PLL3 --> Main MCS = 1 MCM = 0 SCS = 1 SCM = 1 CS1, CS0 = 10B CS2=0 PLL3: Multiplied MCS = 0 MCM = 0 SCS = 1 (10) (8) SCM = 1 CS1, CS0 = 10B CS2=0 PLL4 --> Main MCS = 1 MCM = 0 SCS = 1 SCM= 1 CS1, CS0 = 11B CS2=0 PLL4: Multiplied MCS = 0 MCM = 0 SCS = 1 (10) (8) SCM = 1 CS1, CS0 = 11B CS2=0 PLL6 --> Main MCS = 1 MCM = 0 SCS = 1 SCM = 1 CS1, CS0 = 10B CS2=1 PLL6: Multiplied MCS = 0 MCM = 0 SCS = 1 (10) (8) SCM = 1 CS1, CS0 = 10B CS2=1 (21) PLL3 --> Sub (21) MCS = 1 MCM = 0 SCS = 0 SCM = 1 CS1, CS0 =10B CS2=0 PLL4 --> Sub (21) MCS = 1 MCM = 0 SCS = 0 SCM = 1 CS1, CS0 = 11B CS2=0 PLL6 --> Sub (21) MCS = 1 MCM = 0 SCS = 0 SCM = 1 CS1, CS0 =10B CS2=1 105 CHAPTER 5 CLOCKS (1) (2) Write "0" to MCS bit Termination of PLL clock oscillation stabilization wait time & CS1, CS0= 00B& CS2= 0 (3) Termination of PLL clock oscillation stabilization wait time & CS1, CS0= 01B& CS2= 0 (4) Termination of PLL clock oscillation stabilization wait time & CS1, CS0= 10B& CS2= 0 (5) Termination of PLL clock oscillation stabilization wait time & CS1, CS0= 11B& CS2= 0 (6) Termination of PLL clock oscillation stabilization wait time & CS1, CS0= 10B& CS2= 1 (7) (8) (9) (10) (11) (12) (13) Write "1" to MCS bit (include reset) Synchronous timing of PLL clock and main clock Write "0" to SCS bit Synchronous timing of main clock and sub-clock Write "1" to SCS bit (MCS1) Termination of main clock oscillation stabilization wait time Termination of main clock oscillation stabilization wait time & CS1, CS0= 00B& CS2= 0 (14) Termination of main clock oscillation stabilization wait time & CS1, CS0= 01B& CS2= 0 (15) Termination of main clock oscillation stabilization wait time & CS1, CS0= 10B& CS2= 0 (16) Termination of main clock oscillation stabilization wait time & CS1, CS0= 11B& CS2= 0 (17) Termination of main clock oscillation stabilization wait time & CS1, CS0= 10B& CS2= 1 (18) (19) Write "1" to SCS bit (MCS0) Synchronous timing of PLL clock and sub-clock MCS MCM SCS SCM CS1, CS0 CS2 : : : : : : Machine clock select bit of clock selection register (CKSCR) Machine clock display bit of clock selection register (CKSCR) Machine clock display bit (sub) of clock selection register (CKSCR) Machine clock select bit (sub) of clock selection register (CKSCR) Machine clock of clock selection register (CKSCR) Multiplication rate selection bit of PLL/ subclock control register (PSCCR) Notes: • The initial value for the machine clock setting is main clock (CKSCR: MCS = 1, SCS = 1). • If both the SCS and MCS bits are “0”, the SCS bit takes precedence, that is, the sub-clock is selected. • When sub-clock mode is switched to PLL clock mode, set the WS1 and WS0 bits of CKSCR to “10B” or “11B.” 106 CHAPTER 5 CLOCKS 5.6 Oscillation Stabilization Wait Interval When the power is turned on during the oscillation clock is stopped or when stop mode is released, a time until the oscillation clock stabilizes (oscillation stabilization wait time is required immediately after oscillation starts. Also, the oscillation stabilization wait time is required when the clock mode is switched from main clock to PLL clock, main clock to sub-clock, sub-clock to main clock, and sub-clock to PLL clock. ■ Oscillation Stabilization Wait Interval Ceramic and crystal oscillators generally require several to dozens of ms to stabilize at their natural frequency (oscillation frequency) when oscillation starts. For this reason, CPU operation is not allowed immediately after oscillation starts but is allowed only after full oscillation stabilization. After the oscillation stabilization wait interval has elapsed, the machine clock is supplied to the CPU. Because the oscillation stabilization wait time depends on the type of oscillator (crystal, ceramic, etc.), the proper oscillation stabilization wait interval for the oscillator used must be selected. An oscillation stabilization wait interval is selected by setting the clock selection register (CKSCR). When clock mode is switched from main clock to PLL clock, main clock to subclock, subclock to main clock, or subclock to PLL clock, the CPU runs in the clock mode set before switching for the oscillation stabilization wait time. After the oscillation stabilization wait time has elapsed, the CPU changes to the specified clock mode. Figure 5.6-1 shows the operation immediately after oscillation starts. Figure 5.6-1 Operation Immediately after Oscillation Stabilization Wait Time Oscillation time of oscillator Oscillation stabilization wait time (Start normal operation or switch to PLL clock/subclock X1 Oscillation start Oscillation stabilization 107 CHAPTER 5 CLOCKS 5.7 Connection of an Oscillator or an External Clock to the Microcontroller The MB90360 series microcontroller contains a system clock generation circuit. Connecting an external oscillator to this circuit generates the system clock. Alternatively, an externally generated clock can be input to the microcontroller. ■ Connection of an Oscillator or an External Clock to the Microcontroller ● Example of connecting a crystal or ceramic oscillator to the microcontroller Figure 5.7-1 Example of Connecting a Crystal or Ceramic Oscillator to the Microcontroller X0 X1 C1 MB90360 series C2 X0A X1A C3 C4 ● Example of connecting an external clock to the microcontroller Figure 5.7-2 Example of Connecting an External Clock to the Microcontroller X0 Open X1 MB90360 series X0A Open 108 X1A CHAPTER 6 CLOCK SUPERVISOR This chapter explains the function and the operation of the clock supervisor. Only the product with built-in clock supervisor of the MB90360 series is valid to this function. 6.1 Overview of Clock Supervisor 6.2 Block Diagram of Clock Supervisor 6.3 Clock Supervisor Control Register (CSVCR) 6.4 Operating Mode of Clock Supervisor 109 CHAPTER 6 CLOCK SUPERVISOR 6.1 Overview of Clock Supervisor The clock supervisor checks the oscillation of the main clock or a sub-clock (without "S" suffix product). When the main clock or a sub-clock stops due to some breakdowns, the control circuit of the clock supervisor switches the clock source to built-in CR oscillation clock, sets the detection flag, and generates reset. ■ Overview of Clock Supervisor The clock supervisor checks the oscillation of the main clock or the sub-clock. If the using (main or sub) clock stops during the fixed time (20 µs to 80 µs: When the main clock is used, 160 µs to 640 µs: When the sub clock is used), the corresponding clock stop detection flag is set and reset is generated after switching the stopped clock to the CR oscillation clock. The reset factor can be checked by the reset factor bit of watchdog timer control register (WDTC). Supervising a main and a sub-clock can be set to the disable (watching prohibition) respectively independently. When a sub-clock stops while the device is operating in the main clock mode, internal reset is not generated at once. When changing to the sub-clock mode, internal reset is generated. It is also possible to control the internal reset generation by the setting in this case. When the device changes to the stop mode, the main-/sub-clock supervisor is automatically disabled (watching prohibition). Either of main or sub clock supervisor that is the condition that was enable before the stop mode changed automatically returns from disabled to enabled when returning from the stop mode. Built-in CR oscillation clock can be used as a sub-clock of the device if the product is the external singleclock product (with "S" suffix product). Note: At power-on, the clock supervisor starts monitoring immediately after a lapse of the oscillation stability waiting time for the main clock. 110 CHAPTER 6 CLOCK SUPERVISOR 6.2 Block Diagram of Clock Supervisor The clock Supervisor is composed of the following block: • Main clock supervisor • Sub clock supervisor • Control circuit • Clock supervisor control register (CSVCR) • Main clock selector • Sub clock selector • CR oscillation circuit ■ Block Diagram of Clock Supervisor Figure 6.2-1 shows the block diagram of clock supervisor. Figure 6.2-1 Block Diagram of Clock Supervisor Internal bus Clock Supervisor control register (CSVCR) Internal reset Control circuit Enable CR oscillation circuit Enable Enable Detection Main clock supervisor Detection Sub selection Main selection Sub clock supervisor CR oscillation clock Main clock Main clock selector Internal main clock Sub clock selector Internal sub clock 1/2 Sub clock 111 CHAPTER 6 CLOCK SUPERVISOR ● Main clock supervisor The oscillation of the main oscillation clock (HCLK) is supervised by using the clock from the CR oscillation circuit as a clock source. ● Sub clock supervisor The oscillation of the sub oscillation clock (SCLK) is supervised by using the clock from the CR oscillation circuit as a clock source. ● Control circuit Disable or enable for main/sub clock supervisor, existence of internal reset generation when clock halt condition is detected, and switching to CR oscillation clock of clock to be monitored are controlled by setting of clock supervisor control register (CKSCR). ● Clock supervisor control register (CKSCR) Disable or enable for main/sub clock supervisor, existence of internal reset generation when clock halt condition is detected, or switching to CR oscillation clock of clock to be monitored are selected. ● Main clock selector CR oscillation clock is outputted as main clock when the main oscillation clock is missing. ● Sub clock selector The divided clock of CR oscillation clock is outputted as sub clock when the sub oscillation clock is missing. ● CR oscillation circuit Internal CR oscillation clock circuit. Disable/enable the CR oscillation can be selected by the control circuit. 112 CHAPTER 6 CLOCK SUPERVISOR 6.3 Clock Supervisor Control Register (CSVCR) This register switches main clock/sub clock/PLL clock, and selects the oscillation stabilization wait time and PLL clock multiplication rate. ■ Clock Supervisor Control Register (CSVCR) Figure 6.3-1 Clock Supervisor Control Register (CSVCR) Address 007960H 7 6 SCKS MM R/W R 5 4 3 2 1 0 ReseSM RCE MSVE SSVE SRST rved R R/W R/W R/W R/W R/W Initial value 00011100 bit0 Reserved 0 R/W : R : Read only : Reset value Read/Write B Reserved bit Be sure to write "0" to this bit. Read value is always "0". bit1 SRST 0 1 Sub-clock mode reset No generating reset on subclock mode transition Generating reset on subclock mode transition bit2 SSVE 0 1 Sub clock supervisor enable Sub clock supervisor is disabled. Sub clock supervisor is enabled. bit3 MSVE 0 1 Main clock supervisor enable Main clock supervisor is disabled. Main clock supervisor is enabled. bit4 RCE 0 1 CR oscillation clock enable CR oscillation clock is stopped. CR oscillation clock is enabled. bit5 SM 0 1 Sub clock missing Missing sub-clock has not been detected. Missing sub-clock has been detected. bit6 MM 0 1 Main clock missing Missing main clock has not been detected. Missing main clock has been detected. bit7 SCKS 0 1 Sub clock select (for "S" suffix product) Not use the CR oscillation clock as sub clock Use the CR oscillation clock as sub clock 113 CHAPTER 6 CLOCK SUPERVISOR Bit name Function bit7 SCKS Sub clock select This bit permits built-in CR oscillation clock to be used as a sub-clock. Only "S" suffix product is valid to this function. "1": It is possible to change to the sub clock mode with built-in CR oscillation clock. "0": It is not possible to change to the sub clock mode. This bit is initialized to "0" by power-on reset, external reset, or low voltage detection reset in "T" suffix product. It is initialized to "0" by power-on reset or external reset without "T" suffix product. It is necessary to set this bit to "1" in the main clock mode before the sub-clock supervisor after the above-mentioned is initialized operates automatically. Moreover, after setting to "1", this bit cannot be reset to "0" by software. bit6 MM Main clock missing This bit indicates the oscillation missing of main clock terminal X0 and X1 was detected. "1": Missing main clock has been detected. "0": Missing main clock has not been detected. This bit is initialized to "0" by power-on reset, external reset, or low voltage detection reset with "T" suffix product. It is initialized to "0" by power-on reset or external reset without "T" suffix product. bit5 SM Sub clock missing This bit indicates the oscillation missing of sub clock terminal X0A and X1A was detected. No "S" suffix product is valid to this function. "1": Missing sub-clock has been detected. "0": Missing sub-clock has not been detected. This bit is initialized to "0" by power-on reset, external reset, or low voltage detection reset with "T" suffix product. It is initialized to "0" by power-on reset or external reset without "T" suffix product. bit4 RCE CR oscillation clock enable This bit permits built-in CR oscillation. "1": Built-in CR oscillation is enabled. "0": Built-in CR oscillation is disabled. This bit is initialized to "1" by power-on reset, external reset, or low voltage detection reset with "T" suffix product. It is initialized to "1" by power-on reset or external reset without "T" suffix product. Please set this bit in "1" after confirming both the following: - The supervisor of main and sub-clock is disabled. - MM and SM bits are "0". bit3 MSVE Main clock supervisor enable This bit permits monitoring for main clock oscillation. "1": Main clock supervisor is enabled. "0": Main clock supervisor is disabled. This bit is initialized to "1" by power-on reset or low voltage detection reset with "T" suffix product. It is initialized to "1" by power-on reset or external reset without "T" suffix product. bit2 SSVE Sub clock supervisor enable This bit permits monitoring for sub clock oscillation. "1": Sub clock supervisor is enabled. "0": Sub clock supervisor is disabled. This bit is initialized to "1" by power-on reset or low voltage detection reset with "T" suffix product. It is initialized to "1" by power-on reset or external reset without "T" suffix product. bit1 SRST Sub-clock mode reset This bit permits the reset output when transmitting from main clock/PLL clock mode to the sub-mode with sub-clock breakdown. "1": Output reset. "0": Not output reset This bit is initialized to "0" by power-on reset, external reset, or low voltage detection reset with "T" suffix product. It is initialized to "0" by power-on reset or external reset without "T" suffix product. bit0 Reserved bit This bit is reserved. Be sure to write "0" to this bit. Read value is always "0". 114 CHAPTER 6 CLOCK SUPERVISOR 6.4 Operating Mode of Clock Supervisor This section explains all the operating modes of the Clock Supervisor. ■ Operating Mode in Initialized State The CR oscillation circuit, the main clock supervisor and the sub-clock supervisor are enabled before the clock supervisor control register (CSVCR) is set by the user program. • After power-on reset or reset of the low voltage detection, the CR oscillation circuit is enabled with "T" suffix product. After power-on reset or external reset, the CR oscillation circuit is enabled without "T" suffix product. • If the main clock goes off after a lapse of the oscillation stability waiting time (211/HCLK), the main clock monitor function will be immediately enabled to cause reset to occur. • If the main clock goes off before a lapse of the oscillation stability waiting time after power-on reset, the main clock monitor function will cause reset after a lapse of the 212 cycle of CR oscillation clock (approximately 41 ms for the CR oscillation of 100 kHz). • If the main clock goes off during the period of power-on reset, the device will retain the reset state. • After it passes of 218 cycles of the CR oscillation clock (For about 2.6 s:CR oscillation 100 kHz), the sub-clock supervisor is valid. • When the main clock is stopped on the main clock supervisor enable state, the main clock is replaced with the CR oscillation clock, MM bit is set to one, and the reset is generated. • When the sub clock is stopped on the sub clock mode, the sub clock is replaced with the CR oscillation two dividing frequency clock, SM bit is set to one, and the reset is generated. When the sub clock is stopped on the main clock mode, the sub clock is replaced with the CR oscillation two dividing frequency clock, SM bit is set to one. However, the reset is not generated at the sub-clock mode transition because the initial value of SRST bit is "0". ■ Prohibition Setting of CR Oscillation Circuit and Clock Supervisor In the following settings, it is assumptions that the CR oscillation circuit, the main clock supervisor, and the sub-clock supervisor are operating. • MSVE(CSVCR:bit3) is set to 0 and the main clock supervisor is set disable. • SSVE(CSVCR:bit2) is set to 0 and the sub clock supervisor is set disable. • The RCE bit (bit4 of CSVCR) is set to 0 and the CR oscillation circuit is set disable. Please set it after checking that the main clock and the sub-clock supervisor are disabled, and both SM and MM (bit4 of CSVCR) are 0. Do not set RCE to 0 when either SM or MM is one. ■ Reoperating Setting of CR Oscillation Circuit and Clock Supervisor In the following settings, it is assumptions that the CR oscillation circuit, the main clock supervisor, and the sub-clock supervisor are stopped. • RCE(CSVCR:bit4) is set to 1 and the CR oscillation circuit is set enable. • MSVE(CSVCR:bit3) is set to 1 and the main clock supervisor is set enable. Please note the programming of software to do after 10 µs or more has passed since the CR oscillation circuit was set enable. 115 CHAPTER 6 CLOCK SUPERVISOR • The sub-clock supervisor is operated by setting SSVE(CSVCR:bit2) to 1. Please note the programming of software to do after 10 µs or more has passed since the CR oscillation circuit was set enable. ■ Sub-clock Mode The main clock supervisor automatically becomes disable at the sub-clock mode. The content of enable bit MSVE never changes. If the main clock was lost after oscillation stability waiting time of 211/HCLK (about 0.51 ms: at external 4 MHz) or before the oscillation stability waiting time ends, the main clock supervisor is valid after it passes of 212 cycles of the CR oscillation clock (about 41 ms: at CR oscillation 100 kHz) at transition from main clock mode to sub clock mode. ■ Sub-clock Mode Transition Operating When Sub-clock Has Already Stopped The behavior that shifts to the sub-clock mode depends on the state of the SRST bit when the stop of the sub-clock is detected by the sub-clock supervisor while the device is operating in the main clock mode. • When SRST is set to 0 (initial state), the reset is not generated at transition to the sub-clock mode. In this case, the CR oscillation clock is used as a sub-clock at transition to the sub-clock mode. • When SRST is set to 1, the reset is generated at transition to the sub-clock mode. ■ Stop Mode CR oscillation circuit, the main clock, and the sub-clock supervisor automatically become disable at transition to the stop mode, when all of these functions are enable. Each enable bit of the clock supervisor control register is not changed. Therefore, after it is released from the stop mode, each enable/disable state of CR oscillation circuit and clock supervisor keep the state before they changes to the stop mode. • The CR oscillation circuit immediately becomes enable after released from the stop mode. • If the main clock was lost after oscillation stability waiting time of 211/HCLK (about 0.51 ms: at external 4 MHz) or before the oscillation stability waiting time ends, the main clock supervisor is enabled after it passes of 212 cycles of the CR oscillation clock (about 41 ms: at CR oscillation 100 kHz). • After it passes of 218 cycles of the CR oscillation clock (For about 2.6 s:CR oscillation 100 kHz), the sub-clock supervisor is valid. ■ Sub-clock Mode with External Single Clock Product In the sub-clock mode with external single clock product ("S" suffix product), the CR oscillation clock can be used as a sub-clock. To use this function, SCKS (bit7 of CSVCR) is set to 1 and SRST is set to 0 (initial value). This function can not be used with the external dual clock products (no "S" suffix product). 116 CHAPTER 6 CLOCK SUPERVISOR ■ Reset Check By Clock Supervisor To check whether reset was executed by the clock supervisor, the WDTC register is read with software and the reset factor is checked. When ERSR (bit4 of WDTC) is set, the factor is a reset from an external terminal or a reset by the clock supervisor (include low voltage detection/CPU operating detection reset in "T" suffix products). If both SM and MM bits (bit5 and bit6 of CSVCR) are 0, the reset factor is an external reset (include low voltage detection/CPU operating detection reset in "T" suffix products). If SM is 1, the reset factor is a sub-clock lost. If MM is 1, the reset factor is a main-clock lost. 117 CHAPTER 6 CLOCK SUPERVISOR 118 CHAPTER 7 RESETS This chapter describes resets for the MB90360-series microcontrollers. 7.1 Resets 7.2 Reset Cause and Oscillation Stabilization Wait Times 7.3 External Reset Pin 7.4 Reset Operation 7.5 Reset Cause Bits 7.6 Status of Pins in a Reset 119 CHAPTER 7 RESETS 7.1 Resets If a reset is generated, the CPU immediately stops the current execution process and waits for the reset to be cleared. The CPU then begins processing at the address indicated by the reset vector. The four causes of a reset are as follows • Power-on reset • External reset request via the RST pin • Software reset request • Watchdog timer overflow • Low voltage detection reset request (product with "T"-suffix) • CPU operation detection reset request (product with "T"-suffix) • Clock supervisor reset request (MB90367/T(S)) ■ Causes of a Reset Table 7.1-1 lists the causes of a reset. Table 7.1-1 Cause of a Reset Reset Cause Machine clock Watchdog timer Oscillation stabilization wait Power-on At power on Main clock (MCLK) Stop Yes External pin L level input to RST pin Main clock (MCLK) Stop None Software Write "0" to internal reset signal generation bit (RST) of low-power consumption mode control register (LPMCR) Main clock (MCLK) Stop None Watchdog timer Watchdog timer overflow Main clock (MCLK) Stop None Low voltage detection reset (with "T"-suffix) When low voltage (4.0 V ± 0.3 V) is detected Main clock (MCLK) Stop None CPU operation detection reset (with "T"-suffix) When CPU operation detection counter overflows Main clock (MCLK) Stop None Clock supervisor reset When failure of main clock/subclock is detected Internal CR oscillation clock Stop None MCLK: Main clock (oscillation clock frequency divided by 2) ● Power-on reset A power-on reset is generated when the power is turned on. The oscillation stabilization wait times is fixed to 216 oscillation clock cycles (216/HCLK) (approx. 16.38 ms, oscillating at 4 MHz). When the oscillation 120 CHAPTER 7 RESETS stabilization wait time has elapsed, the reset is executed. ● External reset An external reset is generated by the L level input to an external reset pin (RST pin). The minimum required period of the L level is at least 500 ns. Reset operation is performed after oscillation stabilization wait time elapses. Note: If the reset cause is generated during a write operation, the CPU waits for the reset to be cleared after completion of the instruction only for reset requests via the RST pin. Therefore, the normal write operation is completed even though a reset is inputted concurrently. However, note that the following two points. Note that a reset may prevent the data transfer requested by a string-processing instruction from being completed because the reset is accepted before a specified number of counters are transferred. At external bus access, if the cycle is exceeded a certain period by RDY input, the reset is accepted forcibly without waiting the completion of instruction. Forcible reset is accepted within 16 machine cycles. When returning to the main clock mode by the external reset pin (RST pin) from the stop mode, subclock mode, sub-sleep mode, and watch mode, input L level for at least oscillation time of oscillator* + 100 µs. *: Oscillation time of oscillator is the time that amplitude reaches 90%. It takes several to dozens of ms for crystal oscillators, hundreds of µs to several ms for FAR/ceramic oscillators, and 0 ms for external clocks. When returning to the main clock mode by the external reset pin (RST pin) from the timebase timer mode, input L level for at least 100 µs. ● Software reset A software reset is generated an internal reset by writing "0" to the RST bit of the low-power consumption mode control register (LPMCR). The oscillation stabilization wait time is not required for a software reset. ● Watchdog reset A watchdog reset is generated by a watchdog timer overflow that occurs when "0" is not written to the WTE bit of the watchdog timer control register (WDTC) within a given time after the watchdog timer is activated. The oscillation stabilization wait time is not required for watchdog reset. ● Low voltage detection reset The low voltage detection reset is generated when the low voltage (4.0 V ± 0.3 V) is detected. The oscillation stabilization wait time is not required for the low voltage detection reset. 121 CHAPTER 7 RESETS ● CPU operation detection reset The CPU operation detection reset is 20-bit counter that the source oscillation is count-locked. If the CL bit of the low voltage/CPU operation detection reset is not cleared within a specified time after activation, the reset is generated. The oscillation stabilization wait time is not required for the CPU operation detection reset. ● Clock supervisor reset When the failure of the main clock/subclock is detected, the clock supervisor reset is generated. The oscillation stabilization wait time is not required for the clock supervisor reset. Definition of clocks HCLK: Oscillation clock frequency MCLK: Main clock frequency φ: Machine clock (CPU operating clock) frequency 1/φ: Machine cycle (CPU operating clock period) See "5.1 Clocks", for details. Note: When the reset is occurred in the stop mode or sub-clock mode, the oscillation stabilization wait time of 215/HCLK (approx. 8.19 ms, using at HCLK = 4 MHz oscillation) is required. See "5.6 Oscillation Stabilization Wait Interval" for details. 122 CHAPTER 7 RESETS 7.2 Reset Cause and Oscillation Stabilization Wait Times The MB90360 series has seven reset causes. The oscillation stabilization wait time for a reset depends on the reset cause. ■ Reset Causes and oscillation Stabilization Wait Times Table 7.2-1 summarizes reset causes and oscillation stabilization wait times. Table 7.2-1 Reset Causes and oscillation Stabilization Wait Times Reset Reset cause Oscillation stabilization wait time The parenthesized values are provided when oscillation clock frequency operates at 4 MHz Power-on Power-on 216/HCLK (approx. 16.38 ms) Watchdog Watchdog timer overflow None Note: However, the WS1 and WS0 bits are initialized to "11". External L input from RST pin None Note: However, the WS1 and WS0 bits are initialized to "11". Software Write "0" to RST bit of low-power consumption mode control register (LPMCR) None Note: However, the WS1 and WS0 bits are initialized to "11". Low voltage detection *1 When low voltage is detected None Note: However, the WS1 and WS0 bits are initialized to "11". CPU operation detection *1 When CPU operation detection counter overflows None Note: However, the WS1 and WS0 bits are initialized to "11". Clock supervisor *2 When failure of main clock/subclock is detected None Note: However, the WS1 and WS0 bits are initialized to "11". HCLK: Oscillation clock frequency WS1, WS0: Oscillation stabilization wait time select bit of clock selection register (CKSCR) *1: Product with T-suffix *2: For MB90F367/T(S), MB90367/T(S) Figure 7.2-1 shows the oscillation stabilization wait times at a power-on reset. 123 CHAPTER 7 RESETS Figure 7.2-1 Oscillation Stabilization Wait Times at a Power-on Reset Vcc 215/HCLK 215/HCLK CLK CPU operation Stabilization wait time of voltage step-down circuit Oscillation stabilization wait time Note: Ceramic and crystal oscillators generally require an oscillation stabilization wait time of several milliseconds to some tens of milliseconds, until stabilization at a natural frequency is attained after starts oscillation. A proper oscillation stabilization wait time must be set for the particular oscillator used. See "5.6 Oscillation Stabilization Wait Interval", for details about oscillation stabilization wait times. ■ Oscillation Stabilization Wait and Reset State A reset operation in response to a power-on reset and other resets during stop mode or sub-clock mode is performed after the oscillation stabilization wait time has elapsed. This time interval is generated by the timebase timer. If the external reset has not been cleared after the interval, the reset operation is performed after the external reset is cleared. 124 CHAPTER 7 RESETS 7.3 External Reset Pin The external reset pin (RST pin) is an input pin used exclusively for a reset. Inputting an L level signal generates an internal reset. For the MB90360-series, resets are generated in synchronization with the CPU operating clock. However, initialization of external pin is asynchronous with the CPU operating clock. ■ Block Diagrams of the External Reset Pin ● Block diagram of the external reset pin Figure 7.3-1 Block Diagram of the External Reset Pin CPU operating clock (PLL multiplication circuit, 2-frequency division of HCLK) RST Pch Synchronization circuit Pin Nch CPU peripheral function Input buffer External pin HCLK: Oscillation clock Note: Inputs to the RST pin are accepted during cycles in which memory is not affected to prevent memory from being destroyed by a reset during a write operation. A clock is required to initialize the internal circuit. In particular, an operation with an external clock requires clock input together with reset input. 125 CHAPTER 7 RESETS 7.4 Reset Operation When the reset signal is inactivated, the reset vector and mode data is fetched from the predetermined locations depending on the setting of the mode pins. This operation, the mode fetch, then defines the operation mode of the CPU and the start address of the first instruction. For the power on reset, reset from the stop mode or sub-clock mode, the mode fetch is performed after the oscillation stabilization wait time is elapsed. ■ Overview of Reset Operation Figure 7.4-1 shows the reset operation flow. Figure 7.4-1 Reset Operation Flow Power-on reset Stop mode Sub-clock mode During reset Oscillation stabilization wait reset status External reset Software reset Watchdog timer reset Low voltage detection reset*1 CPU operation detection reset*1 Clock supervisor reset*2 Fetch reset vector Mode fetch (reset operation) Normal operation (RUN status) Fetch mode data Fetch the instruction code from the address indicated by the reset vector and execute instruction *1: Product with T-suffix *2: For MB90F367/T(S), MB90367/T(S) ■ Mode Pins Setting the mode pins (MD0 to MD2) specifies how to fetch the reset vector and the mode data. Fetching the reset vector and the mode data is performed in the reset sequence. See "9.1.1 Mode Pins", for details on mode pins. 126 CHAPTER 7 RESETS ■ Mode Fetch When the reset is cleared, the CPU transfers the reset vector and the mode data to the appropriate registers in the CPU core by hardware. The reset vector and mode data are allocated to the four bytes from "FFFFDCH" to "FFFFDFH". The CPU outputs these addresses to the bus immediately after the reset is cleared and then fetches the reset vector and mode data. Using mode fetching, the CPU can begin processing at the address indicated by the reset vector. Figure 7.4-2 shows the transfer of the reset vector and mode data. Figure 7.4-2 Transfer of Reset Vector and Mode Data F2MC-16LX CPU core Memory space FFFFDFH Mode data FFFFDEH Reset vector bits (23 to 16) FFFFDDH Reset vector bits (15 to 8) FFFFDCH Reset vector bits (7 to 0) Mode register Micro ROM Reset sequence PCB PC ● Mode data (address: FFFFDFH) Only a reset operation changes the contents of the mode register. The mode register setting is valid after a reset operation. See "9.1.2 Mode Data", for details on mode data. ● Reset vector (address: FFFFDCH to FFFFDEH) The reset vector points to the start address after the reset operation. The CPU starts to execute the first instruction stored in the start address. 127 CHAPTER 7 RESETS 7.5 Reset Cause Bits A reset cause can be identified by reading the watchdog timer control register (WDTC). ■ Reset Cause Bits As shown in Figure 7.5-1 , a flip-flop is associated with each reset cause. The contents of the flip-flops are obtained by reading the watchdog timer control register (WDTC). If the cause of a reset must be identified after the reset has been cleared, the value read from the WDTC should be processed by the software and a branch made to the appropriate program. Figure 7.5-1 Block Diagram of Reset Cause Bits For MB90F367/T(S) MB90367/T(S) RST pin No periodic clear CPU operation detection reset request detetion circuit Drop power supply voltage Failure of main/ sub clock Low voltage detection circuit Clock supervisor RST=L External reset request detection circuit Power-on No periodic clear RST bit set Power-on generation detection circuit Watchdog timer reset generation detection circuit Write detection circuit of LPMCR, RST bits Clear Watchdog timer control register (WDTC) S F/F Q R S R F/F Q S F/F Q R S F/F Q R Delay circuit Read watchdog timer control register (WDTC) Internal data bus T-suffix only S R Q F/F 128 : Set : Reset : Output : Flip Flop CHAPTER 7 RESETS ■ Correspondence between reset cause bits and reset causes Figure 7.5-2 shows the configuration of the reset cause bits of the watchdog timer control register (WDTC). Table 7.5-1 maps the correspondence between the reset cause bits and reset causes. See “Watchdog timer control register (WDTC)” in "12.1 Overview of Watchdog Timer", for details. Figure 7.5-2 Configuration of Reset Cause Bits (watchdog timer control register) Watchdog timer control register (WDTC) Address bit15 0000A8H R : Read only W : Write only X : Undefined ........ bit8 (TBTC) bit7 bit6 PONR − R − bit5 bit4 bit3 WRST ERST SRST R R R bit2 bit1 bit0 WTE WT1 WT0 W W W Initial value XXXXX111B Table 7.5-1 Correspondence between Reset Cause Bits and Reset Causes Reset cause PONR WRST ERST SRST Generation of power-on reset request 1 X X X Generation of reset request due to watchdog timer overflow ∆ 1 ∆ ∆ External reset request from RST pin, Low voltage detection reset (product with T-suffix)*1 CPU operation detection reset (product with T-suffix)*2 Clock supervisor reset (MB90F367/T(S), MB90367/T(S)) ∆ ∆ 1 ∆ Generation of software reset request ∆ ∆ ∆ 1 ∆: Previous state retained X: Undefined *1: When the low voltage detection reset request is used, the CPUF bit of the low voltage/CPU operation detection reset control register (LVRC) is also set to "1". *2: When the CPU operation detection reset request is used, the CPUF bit of the low voltage/CPU operation detection reset control register (LVRC) is also set to "1". 129 CHAPTER 7 RESETS ■ Status of Reset Cause Bit and Low Voltage Detection Bit Figure 7.5-3 Status of Reset Cause Bit and Low Voltage Detection Bit Flag status at power-on Bit clear Flag status at low voltage Bit detection (4V) clear Vcc=4V Vcc PONR bit (power-on) (1) 1 → (2) 0 → (3) 0 → (4) 0 ERST bit (external reset input, CPU operation detection, or LVRF = 1) 1 or 0 → 0 → 1 → 0 LVRF bit* (low voltage detection 4V ± 0.3V) 1 or 0 → 0 → 1 → 0 *: The LVRF bit exist in the low voltage/CPU operation detection reset control register (LVRC). (1) At power-on Power-on reset bit (PONR) , ERST, and LVRF are set to "1" at power on. (2) Bit clear Bit is cleared by reading the WDTC register and by writing "0" to LVRF. (3) At low voltage detection (4.0 V ± 0.3 V) The LVRF and ERST bits are set to "1" at low voltage detection of VCC = 4.0 V ± 0.3 V. (4) Bit clear Bit is cleared by reading the WDTC register and by writing "0" to LVRF. 130 CHAPTER 7 RESETS ■ Notes about Reset Cause Bits ● Multiple reset causes generated at the same time When multiple reset causes are generated at the same time, the corresponding reset cause bits of the watchdog timer control register (WDTC) are also set to "1". If, for example, an external reset request via the RST pin and the watchdog timer overflow occur at the same time, the ERST and the WRST bits are both set to "1". ● Power-on reset For a power-on reset, because the PONR bit is set to "1" but all other reset cause bits are undefined, the software should be programmed so that it will ignore all reset cause bits except the PONR bit if it is "1". ● Clearing the reset cause bits The reset cause bits are cleared only when the watchdog timer control register (WDTC) is read. Any bit corresponding to a reset cause that has already been generated is not cleared even though another reset is generated (a setting of "1" is retained). Note: If the power is turned on under conditions where no power-on reset occurs, the value in WDTC register may not be guaranteed. 131 CHAPTER 7 RESETS 7.6 Status of Pins in a Reset This section describes the status of pins when a reset occurs. ■ Status of Pins during a Reset The status of pins during a reset depends on the settings of mode pins (MD2 to MD0). About status of each pins during reset, please see "8.7 Status of Pins in Standby Mode and during Hold and Reset". ● When internal vector mode has been set: (MD2 to MD0 = "011B") All I/O pins (resource pins) are high impedance, and mode data is read from the internal ROM. ■ Status of Pins after Mode Data is Read The status of pins after mode data has been read depends on the mode data (M1 and M0). ● When single-chip mode has been selected (M1, and M0 = "00B") All I/O pins (resource pins) are high impedance, and mode data is read from the internal ROM. Note: For those pins that change to high impedance when a reset cause is generated, confirm that devices connected to the pins do not malfunction. 132 CHAPTER 8 LOW-POWER CONSUMPTION MODE This chapter explains the low-power consumption mode of MB90360 series microcontrollers. 8.1 Overview of Low-Power Consumption Mode 8.2 Block Diagram of the Low-Power Consumption Control Circuit 8.3 Low-Power Consumption Mode Control Register (LPMCR) 8.4 CPU Intermittent Operation Mode 8.5 Standby Mode 8.6 Status Change Diagram 8.7 Status of Pins in Standby Mode and during Hold and Reset 8.8 Usage Notes on Low-Power Consumption Mode 133 CHAPTER 8 LOW-POWER CONSUMPTION MODE 8.1 Overview of Low-Power Consumption Mode The MB90360 series has the following CPU operating modes, any of which can be used depending on operating clock selection and clock oscillation control: • Clock mode : main clock mode, PLL clock mode, or sub-clock mode • CPU intermittent operating mode : main clock intermittent operating mode, PLL clock intermittent operating mode, or sub-clock intermittent operating mode • Standby mode : sleep mode, stop mode, watch mode, or timebase timer mode ■ CPU Operating Modes and Current Consumption Figure 8.1-1 shows the relationship between the CPU operating modes and current consumption. Figure 8.1-1 CPU Operating Mode and Current Consumption Current consumption Several tens of 10mA CPU operation mode PLL clock mode 6 multiplier clock 4 multiplier clock 3 multiplier clock 2 multiplier clock 1 multiplier clock PLL clock intermittent opreting mode 6 multiplier clock 4 multiplier clock 3 multiplier clock 2 multiplier clock 1 multiplier clock Main clock mode (1/2HCLK) Main clock intermittent operating mode Subclock mode (1/4 or 1/2 of oscillation frequency) Subclock intermittent operating mode Several mA Standby mode Sleep mode Timebase timer mode Watch mode Several µA Stop mode Low-power consumption mode This figure shows the imageof operating mode and has some difference from actual current consumpation. 134 CHAPTER 8 LOW-POWER CONSUMPTION MODE ■ Clock Mode ● PLL clock mode In this mode, a PLL clock that is a multiple of the oscillation clock (HCLK) is used to operate the CPU and peripheral functions. ● Main clock mode In this mode, the main clock, with the oscillation clock (HCLK) frequency divided by 2 is used to operate the CPU and peripheral functions. In the main clock mode, the PLL multiplier circuit is inactive. ● Sub-clock mode In this mode, the sub-clock (SCLK) is used to operate the CPU and peripheral functions. The sub-clock can select a clock frequency divided by 2 or 4 of clock from external sub-clock pin or internal CR oscillation clock. In the sub-clock mode, the main clock and PLL multiplier circuit are inactive. The subclock oscillation stabilization wait time of 214/SCLK (Approx. 2 s @32.768 kHz oscillation clock frequency, 1/4 division) takes place when power-on and reactivation from stop mode. If a transition from main clock mode to subclock mode is performed during this oscillation stabilization wait time, actual transition may be delayed. Reference: For the clock mode, see "5.5 Clock Mode". ■ CPU Intermittent Operating Mode In this mode, the CPU is operated intermittently while high-speed clock pluses are supplied to peripheral functions, thereby reducing power consumption. In this mode, intermittent clock pulses are supplied only to the CPU while it is accessing a register, internal memory, peripheral function, or external unit. ■ Standby Mode In this mode, the standby control circuit stops supplying the clock to the CPU or peripheral functions or stops the oscillation clock itself (HCLK), thereby reducing power consumption. ● Sleep mode The sleep mode stops the operation clock to the CPU during operation in each clock mode. The CPU stops, and the peripheral function operates the clock before the transition to the sleep mode. The sleep mode is divided into the main sleep mode, PLL sleep mode before the transition to sleep mode. ● Watch mode The watch mode operates the sub-clock (SCLK), watch timer, and low voltage detection circuit only. The main clock and PLL clock stop. All peripheral functions other than the watch timer and low voltage detection circuit stop. 135 CHAPTER 8 LOW-POWER CONSUMPTION MODE ● Timebase timer mode The timebase timer mode operates the oscillation clock (HCLK), sub-clock (SCLK), timebase timer, watch timer, and low voltage detection circuit only. All peripheral functions other than the timebase timer, watch timer, and low voltage detection circuit stop. ● Stop mode The stop mode stops the oscillation clock (HCLK) and sub-clock (SCLK) during operation in each clock mode, and all functions other than low voltage detection circuit stop. Data can be retained at the lowest power consumption. Note: When the clock mode is switched, do not switch to other clock mode and low-power consumption mode before this switching is completed. Confirm the completion of clock mode switching by referring to the MCM and SCM bits of the clock selection register (CKSCR). If the mode is switched to other clock mode and low-power consumption mode before completion of switching, the mode may not be switched. 136 CHAPTER 8 LOW-POWER CONSUMPTION MODE 8.2 Block Diagram of the Low-Power Consumption Control Circuit This section shows the block diagram of the low-power consumption control circuit. ■ Block Diagram of the Low-Power Consumption Control Circuit Figure 8.2-1 Block Diagram of the Low-Power Consumption Control Circuit Low-power consumption mode control register (LPMCR) STP SLP SPL RST TMD CG1 CG0 RST Reserved Pin Pin High-Z control circuit Pin Hi-Z control Internal reset generator Internal reset CPU intermittent operation cycle selector Select the intermitted cycle CPU clock control circuit Reset (cancellation) Watch, sleep and stop signal Standby control circuit 2 Interrupt (cancellation) CPU operating clock Watch and stop signal Resources operating clock Peripheral clock control circuit Cancellation of subclock oscillation stabilization wait Clock generator Cancellation of main clock oscillation stabilization wait Operation clock selector Machine clock Oscillation stabilization selector 2 CS2 PLL/subclock control register (PSCCR): bit8 2 PLL multiplier circuit SCM MCM WS1 WS0 SCS MCS CS1 CS0 Clock select register (CKSCR) Clock selector X0 Pin 2 -divided Oscillation clock (HCLK) X1 Pin Oscillation clock generator 4-divided/ 2-divided 2divided 2ivided Timebase timer 1024 -divided 2divided 2divided 2divided 4divided To watchdog timer 8-divided 2-divided 2-divided Watch timer X1A Pin Internal CR * oscillation clock 4divided Sub-clock (HCLK) Clock selector X0A Pin 512-divided Main clock Subclock oscillation circuit Clock supervisor SCDS * PLL/subclock control register (PSCCR):bit10 * : MB90367/T(S) ● CPU intermittent operation selector This selector selects the halt cycle count of the CPU clock during the CPU intermittent operation mode. ● Standby control circuit CPU clock control and peripheral clock control circuits switch the CPU operation clock and peripheral function operation clock to transit to and cancel the standby mode. 137 CHAPTER 8 LOW-POWER CONSUMPTION MODE ● CPU clock control circuit This circuit controls clocks supplied to the CPU. ● Pin high-impedance control circuit This circuit makes I/O pins high-impedance in the watch mode, timebase timer mode and stop mode. ● Internal reset generation circuit This circuit generates an internal reset signal. ● Low-power consumption mode control register (LPMCR) This register is used to switch to and release the standby mode and to set the CPU intermittent operation mode. 138 CHAPTER 8 LOW-POWER CONSUMPTION MODE 8.3 Low-Power Consumption Mode Control Register (LPMCR) This register switches to or releases the low-power consumption mode. This register also generates the internal reset signal and sets the halt cycle count during the CPU intermittent operation mode. ■ Low-Power Consumption Mode Control Register (LPMCR) Figure 8.3-1 Configuration of the Low-power Consumption Mode Control Register (LPMCR) 5 4 3 2 1 0 6 7 Address Re0000A0H STP SLP SPL RST TMD CG1 CG0 served W W R/W W W R/W R/W R/W Reset value 00011000 B bit0 Reserved Reserved bit Be sure to set this bit to 0. 0 bit2 bit1 CG1 CG0 CPU suspended cycle number select bit 0 0 0 cycle (CPU clock = peripheral clock) 0 1 8 cycle (CPU clock: peripheral clock = 1: approx. 3 to 4) 1 0 16 cycle (CPU clock: peripheral clock = 1: approx. 5 to 6) 1 1 32 cycle (CPU clock: peripheral clock = 1: approx. 9 to 10) bit3 TMD Watch mode bit 0 Transfer to watch mode or timebase timer 1 No effect bit4 RST 0 1 Generate the internal reset signal of 3-machine cycle No effect bit5 SPL 0 1 Hold I/O pin state High-Z Internal reset signal generation bit Pin state specification bit Valid only in timebase timer, watch and stop mode bit6 Sleep mode bit SLP 0 No effect Change to sleep mode 1 bit7 STP R/W W : Read/Write : Write only : Reset value 0 1 Stop mode No effect Change to stop mode 139 CHAPTER 8 LOW-POWER CONSUMPTION MODE Table 8.3-1 Functions of Low-power Consumption Mode Control Register (LPMCR) Bit name 140 Function bit7 STP: Stop mode bit This bit transits to the stop mode. When the bit is set to "0": No effect. When the bit is set to "1": The CPU enters the stop mode. Read: "0" is always read. • The bit is initialized to "0" when a reset or external interrupt occurs. bit6 SLP: Sleep mode bit This bit shift to sleep mode When the bit is set to "0": No effect. When the bit is set to "1": The CPU enters the sleep mode. Read: "0" is always read. • The bit is initialized to "0" when a reset or external interrupt occurs. • When the STP and SLP bits are set to "1" at the same time, the STP bit supersedes the SLP bit, causing a transition to stop mode. bit5 SPL: Pin state specification bit The bit is used to set the state of input/output pins after transition to the stop mode, watch mode, or timebase timer mode. When the bit is set to "0": The current level of input/output pins is held. When the bit is set to "1": The I/O pins enter a high impedance state. • The bit is initialized to "0" at a reset. bit4 RST: Internal reset signal generation bit This bit generates software reset. When the bit is set to "0": An internal reset signal for three machine cycles is generated. When the bit is set to "1": No effect Read: "1" is always read. bit3 TMD: Watch mode bit This bit shift to watch mode or timebase timer mode When the bit is set to "0": If the main clock mode or PLL clock mode is used, the bit transits to the timebase timer mode. If the sub-clock mode is used, the bit transits to the watch mode. When the bit is set to "1": No effect • The bit is set to "1" when a reset or interrupt occurs. Read: "1" is always read. bit1 bit2 CG1, CG0: CPU suspended cycle number select bits These bits are used to set the halt cycle count of the CPU clock in the CPU intermittent operation mode. • Any reset causes the bit to return to the reset value. bit0 Reserved: reserved bit Always set this bit to "0". CHAPTER 8 LOW-POWER CONSUMPTION MODE Notes: • Switching to a low-power consumption mode is performed by writing the low-power consumption mode control register (LPMCR). Only the instructions listed in Table 8.3-2 should be used for this purpose. If other instructions are used for switching to a low-power consumption mode, operation cannot be assured. • The standby mode transition instruction in Table 8.3-2 must always be followed by an array of instructions highlighted by a line below. MOV LPMCR, #H’ xx ; The low-power consumption mode transition instruction in Table 8.3-2 NOP NOP JMP $+3 ; jump to next instruction MOV A, #H’ 10 ; any instruction The devices does not guarantee its operation after returning from the standby mode if you place an array of instructions other than the one enclosed in the dotted line. • To access the low-power consumption mode control register (LPMCR) with C language, refer to "■ Notes on Accessing the Low-Power Consumption Mode Control Register (LPMCR) to Enter the Standby Mode" in "8.8 Usage Notes on Low-Power Consumption Mode". • When word-length is used for writing the low-power consumption mode control register (LPMCR), even addresses must be used. Using odd addresses to switch to a low-power consumption mode may result in a malfunction. • To set a pin to high impedance when the pin is shared by a peripheral function and a port in stop mode, watch mode or timebase timer mode, disable the output of peripheral functions, and set the STP bit of the LPMCR register to 1 or set the TMD bit of the LPMCR register to 0. Table 8.3-2 Instructions to be Used for Switching to a Low-power Consumption Mode MOV io,#imm8 MOV dir,#imm8 MOV eam,#imm8 MOV eam,Ri MOV io,A MOV dir,A MOV addr16,A MOV eam,A MOV @Rli+disp8,A MOVW io,#imm16 MOVW dir,#imm16 MOVW eam,#imm16 MOVW eam,RWi MOVW io,A MOVW dir,A MOVW addr16,A MOVW eam,A MOVW @Rli+disp8,A SETB io:bp SETB dir:bp SETB addr16:bp CLRB io:bp CLRB dir:bp CLRB addr16:bp 141 CHAPTER 8 LOW-POWER CONSUMPTION MODE 8.4 CPU Intermittent Operation Mode This mode is used for intermittent operation of the CPU while operation clock is supplied to the CPU and peripheral functions. The purpose of this mode is to reduce power consumption. ■ CPU Intermittent Operation Mode This mode halts the supply of the clock pulse to the CPU for a certain period. The halt occurs after the execution of every instruction that accesses a register, internal memory, I/O, peripheral functions, or the external bus. Internal bus cycle activation is therefore delayed. While high-speed peripheral clock pulses are supplied to peripheral functions, the execution speed of the CPU is reduced, thereby enabling lowpower consumption processing. • The low-power consumption mode control register (LPMCR: CG1 and CG0) is used to select the number of machine cycles that halts the clock supplied to the CPU. • Instruction execution time in the CPU intermittent operation mode can be calculated. A correction value should be obtained by multiplying the execution count of instructions that access a register, internal memory, internal peripheral functions, or the external bus by the number of clock pulses per halt cycle. Add this corrective value to the normal execution time. Figure 8.4-1 shows the operating clock pulses during the CPU intermittent operation mode. Figure 8.4-1 Clock Pulses during the CPU Intermittent Operation Mode Peripheral clock CPU clock Halt cycle 1-instruction execution cycle Internal bus starts 142 CHAPTER 8 LOW-POWER CONSUMPTION MODE 8.5 Standby Mode The standby mode causes the standby control circuit to either stop supplying an operation clock to the CPU or peripheral functions or to stop the oscillation clock reducing power consumption. ■ Operation Status during Standby Mode Table 8.5-1 shows operation status during standby mode. Table 8.5-1 Operation Status during Standby Mode Mode name Sleep mode Transition Oscillation Sub-clock Machine conditions clock (SCLK) clock (HCLK) CPU Peripheral function Pin Release method Main sleep MCS=1 mode SCS=1 SLP=1 ❍ ❍ ❍ ✕ ❍ ❍ External reset or interrupt Sub-sleep mode MCS=X SCS=0 SLP=1 ✕ ❍ ❍ ✕ ❍ ❍ External reset or interrupt PLL sleep mode MCS=0 SCS=1 SLP=1 ❍ ❍ ❍ ✕ ❍ ❍ External reset or interrupt Timebase SPL=0 timer mode MCS=X SCS=1 TMD=0 ❍ ❍ ✕ ✕ ✕*1 ◆ External reset or interrupt*4 SPL=1 MCS=X SCS=1 TMD=0 ❍ ❍ ✕ ✕ ✕*1 Hi-Z *3 External reset or interrupt*4 MCS=X SCS=0 TMD=0 ✕ ❍ ✕ ✕ ✕*2 ◆ External reset or interrupt*5 MCS=X SCS=0 TMD=0 ✕ ❍ ✕ ✕ ✕*2 Hi-Z External reset or interrupt*5 ✕ ✕ ✕ ✕ ✕ ◆ ✕ ✕ ✕ ✕ ✕ Hi-Z Watch mode SPL=0 SPL=1 Stop mode SPL=0 STP=1 SPL=1 STP=1 *3 *3 External reset or interrupt*6 External reset or interrupt*6 143 CHAPTER 8 LOW-POWER CONSUMPTION MODE ❍: operation, ✕: stop, ◆: held in the state before transiting, Hi-Z: High impedance *1 : The timebase timer, watch timer, and low voltage detection function operate. *2 : The watch timer operates. *3 : The DTP/external interrupt input pin operates. *4 : Watch timer, timebase timer, and external interrupts *5 : Watch timer and external interrupts *6 : External interrupt MCS: PLL clock select bit in clock selection register (CKSCR) SCS : Subclock select bit in the clock selection register (CKSCR) SPL : Pin state specification bit of low-power consumption mode control register (LPMCR) SLP : Sleep mode bit of low-power consumption mode control register (LPMCR) STP : Stop mode bit of low-power consumption mode control register (LPMCR) TMD: Watch mode bit of low-power consumption mode control register (LPMCR) Note: For those external pins shared between port functions and peripheral functions in the stop mode, watch mode, or timebase timer mode, disable output for the peripheral functions then set the STP bit to "1" or reset the TMD bit to "0" to set these pins in high impedance state. 144 CHAPTER 8 LOW-POWER CONSUMPTION MODE 8.5.1 Sleep Mode This mode causes the CPU operating clock to stop during operation in each clock mode. The CPU stops, and peripheral function operates. ■ Switching to Sleep Mode Writing 1 in the SLP bit and 0 in the STP bit of the low-power consumption mode control register (LPMCR) triggers a switch to a sleep mode according to setting of the MCS and SCS bits in the clock selection register (CKSCR). Table 8.5-2 shows the correspondence between MCS and SCS bits in the clock selection register (CKSCR) and sleep mode. Table 8.5-2 Setting of Clock Selection Register (CKSCR) and Sleep Mode Clock selection register (CKSCR) Sleep mode to be switched MCS SCS 1 1 Main sleep mode 0 1 PLL sleep mode 1 0 0 0 Sub-sleep mode Note: When 1 is written to the SLP and STP bits of the low-power consumption mode control register (LPMCR) at the same time, the STP bit setting overrides the SLP bit setting and the mode switches to the stop mode. When 1 is written to the SLP bit and 0 is written to the TMD bit at the same time, the TMD bit setting overrides the SLP bit setting and the mode switches to the timebase timer mode or watch mode. ● Data retention function In a sleep mode, the contents of dedicated registers, such as accumulators, and the internal RAM are retained. 145 CHAPTER 8 LOW-POWER CONSUMPTION MODE ● Operation during an interrupt request Writing 1 in the SLP bit of the low-power consumption mode control register (LPMCR) during an interrupt request does not trigger a switch to a sleep mode. If the CPU does not accept the interrupt request, the CPU executes the next to currently executing instruction. If the CPU accepts the interrupt request, CPU operation immediately branches to the interrupt processing routine. ● Status of pins During a sleep mode, all pins retain their previous status. ■ Return from Sleep Mode The sleep mode is cancelled by a reset factor or when an interrupt is generated. ● Return by reset factor When the sleep mode is cancelled by a reset factor, the mode transits to the main clock mode after the sleep mode is cancelled, transiting to the reset sequence. Note: • For returning from subsleep mode to main clock mode using the external reset pin (RST pin), input the Low level for at least oscillator’s oscillation time* + 100 µs + 16 machine cycles (main clock). *: The oscillation time for the oscillator is the period of time taken until its amplitude reaches 90%. It takes several to dozens of ms for crystal oscillators, hundreds of µs to several ms for FAR/ ceramic oscillators, and 0 ms for external clocks. ● Return by interrupt When a higher interrupt request than the interrupt level (IL) of 7 is generated from the resources in the sleep mode, the sleep mode is cancelled. After the sleep mode is cancelled, as with normal interrupt processing, the generated interrupt request is identified according to the settings of the I flag in the condition code register (CCR), the interrupt level mask register (ILM), and the interrupt control register (ICR). • When the CPU is not ready to accept any interrupt request, the next instruction to the currently executing instruction is executed. • When the CPU is ready to accept any interrupt request, it immediately branches to the interrupt processing routine. Figure 8.5-1 shows the release of a sleep mode when an interrupt occurs. 146 CHAPTER 8 LOW-POWER CONSUMPTION MODE Figure 8.5-1 Release of Sleep Mode by Interrupt Occurrence Set to interupt flag of resources INT generate (IL<7) YES NO No cancellation of sleep No cancellation of sleep Cancellation of sleep I=0 YES Execute the next instruction NO ILM<IL YES NO Execution of interrupt process Note: When interrupt processing is executed, the CPU normally executes the instruction that follows the instruction in which a sleep mode has been specified. The CPU then proceeds to interrupt processing. 147 CHAPTER 8 LOW-POWER CONSUMPTION MODE 8.5.2 Watch Mode This mode causes all functions, excluding the subclock (SCLK), watch timer, and low voltage detection circuit, to stop. Main clock and PLL clock stop. ■ Switching to the Watch Mode When 0 is written to the TMD bit of the low-power consumption mode control register (LPMCR) in the subclock run mode, switching to the watch mode occurs. ● Data retention function In the watch mode, the contents of the dedicated registers, such as accumulators, and the internal RAM are retained. ● Operation during an interrupt request Writing 1 in the TMD bit of the low-power consumption mode control register (LPMCR) during an interrupt request does not trigger a switch to the watch mode. If the CPU is not ready to accept any interrupt request, the instruction next to currently executing instruction is executed. If the CPU is ready to accept any interrupt request, an interrupt operation immediately branches to the interrupt processing routine. ● Status of pins Whether the I/O pins in the watch mode retain the state they had immediately before switching to the watch mode or go to the high-impedance state can be controlled by the SPL bit of the low-power consumption mode control register (LPMCR). Note: To set the pin that is shared the peripheral function and port to the high impedance in the watch mode, disable the output of peripheral function, then set the TMD bit of the low-power consumption mode control register (LPMCR) to "0". ■ Return from Watch Mode The watch mode is cancelled by a reset factor or when an interrupt is generated. ● Return by reset factor When the watch mode is cancelled by a reset factor, the mode transits to the main clock mode after the watch mode is cancelled, transiting to the reset sequence. ● Return by interrupt When an interrupt request higher than the interrupt level (IL) of 7 is generated from the watch timer and external interrupt in the watch mode, the watch mode is cancelled. After the watch mode is cancelled, as with normal interrupt processing, the generated interrupt request is 148 CHAPTER 8 LOW-POWER CONSUMPTION MODE identified according to the settings of the I flag in the condition code register (CCR), the interrupt level mask register (ILM), and the interrupt control register (ICR). In the sub-watch mode, no oscillation stabilization wait time is generated and the interrupt request is identified immediately after return from the watch mode. • When the CPU is not ready to accept any interrupt request, the next instruction to the currently executing instruction is executed. • When the CPU is ready to accept any interrupt request, it immediately branches to the interrupt processing routine. Note: When interrupt processing is executed, the CPU normally executes the instruction following the instruction in which the watch mode has been specified. The CPU then proceeds to interrupt processing. 149 CHAPTER 8 LOW-POWER CONSUMPTION MODE 8.5.3 Timebase Timer Mode This mode causes all functions, excluding oscillation clock (HCLK), subclock (SCLK), the timebase timer, the watch timer, and low voltage detection circuit, to stop. In this mode, only the timebase timer, watch timer, and low voltage detection circuit, operate. ■ Switching to the Timebase Timer Mode When 0 is written to the TMD bit of the low-power consumption mode control register (LPMCR) in the PLL clock mode or main clock mode (CKSCR: SCM = 1), switching to the timebase timer mode occurs. ● Data retention function In the timebase timer mode, the contents of dedicated registers, such as accumulators, and the internal RAM are retained. ● Operation during an interrupt request Writing 0 in the TMD bit of the low-power consumption mode control register (LPMCR) during an interrupt request does not trigger a switch to the timebase timer mode. If the CPU is not ready to accept any interrupt request, the instruction next to currently executing instruction is executed. If the CPU is ready to accept any interrupt request, an interrupt operation immediately branches to the interrupt processing routine. ● Status of pins Whether the I/O pins in the timebase timer mode retain the state they had immediately before switching to the timebase timer mode or go to the high-impedance state can be controlled by the low-power consumption mode control register (LPMCR: SPL). Note: To set the pin that is shared the peripheral function and port to the high impedance in the timebase timer mode, disable the output of the peripheral function, then set the TMD bit of the low-power consumption mode control register (LPMCR) to "0". ■ Return from Timebase Timer Mode The timebase timer mode is cancelled by a reset factor or when an interrupt is generated. ● Return by reset factor When the timebase timer mode is cancelled by a reset factor, the mode transits to the main clock mode after the timebase timer mode is cancelled, transiting to the reset sequence. 150 CHAPTER 8 LOW-POWER CONSUMPTION MODE ● Return by interrupt When an interrupt request higher than interrupt level (IL) of 7 is generated from the watch timer, timebase timer, and external interrupt in the timebase timer mode, the timebase timer mode is cancelled. After the timebase timer mode is cancelled, as with normal interrupt processing, the generated interrupt request is identified according to the settings of the I flag in the condition code register (CCR), the interrupt level mask register (ILM), and the interrupt control register (ICR). • When the CPU is not ready to accept any interrupt request, the next instruction to the currently executing instruction is executed. • When the CPU is ready to accept any interrupt request, it immediately branches to the interrupt processing routine. • The following two timebase timer modes are available: - Main clock ←→ timebase timer mode - PLL clock ←→ timebase timer mode Note: When interrupt processing is executed, the CPU normally executes the instruction following the instruction in which switching to the timebase timer mode has been specified. The CPU then proceeds to interrupt processing. 151 CHAPTER 8 LOW-POWER CONSUMPTION MODE 8.5.4 Stop Mode Because this mode causes oscillation clock (HCLK) and subclock (SCLK) to stop during operation in each clock mode, data can be retained by the lowest power consumption. ■ Stop Mode When 1 is written to the STP bit of the low-power consumption mode control register (LPMCR) during operation in the PLL clock mode (CKSCR: MCS=1, SCS=0), the mode transits to the stop mode according to the settings of the MCS bit and SCS bit in the clock selection register (CKSCR). Table 8.5-3 shows the settings of the MCS and SCS bits in the clock selection register (CKSCR) and the stop modes. Table 8.5-3 Clock Selection Register (CKSCR) Settings and Stop Modes Clock selection register (CKSCR) Stop Mode to be Transited MCS SCS 1 1 Main stop mode 0 1 PLL stop mode 1 0 0 0 Sub-stop mode Note: If both the STP and SLP bits in the low-power consumption mode control register (LPMCR) are set to "1" simultaneously, the STP bit is preferred and the mode transits to the stop mode. ● Data retention function In the stop mode, the contents of the dedicated registers, such as accumulators, and the internal RAM are retained. ● Operation during an interrupt request Writing 1 in the STP bit of the low-power consumption mode control register (LPMCR) during an interrupt request does not trigger a switch to the stop mode. If the CPU is not ready to accept any interrupt request, the instruction next to currently executing instruction is executed. If the CPU is ready to accept any interrupt request, an interrupt operation immediately branches to the interrupt processing routine. 152 CHAPTER 8 LOW-POWER CONSUMPTION MODE ● Status of pins Whether the I/O pins in the stop mode retain the state they had immediately before switching to the stop mode or go to the high-impedance state can be controlled by the SPL bit of the low-power consumption mode control register (LPMCR). Note: For those external pins shared between port functions and peripheral functions, disable output for the peripheral functions then set the STP bit to "1" to set these pins in high impedance state. ■ Return from Stop Mode The stop mode is cancelled by a reset factor or when an interrupt is generated. At return from the stop mode, the oscillation clock (HCLK) and the sub clock (SCLK) stop, so the stop mode is cancelled after the elapse of the main clock oscillation stabilization wait time or the sub clock oscillation stabilization wait time. ● Return by reset factor When the stop mode is cancelled by a reset factor, the main clock oscillation stabilization wait time is generated. After the termination of the main clock oscillation stabilization wait time, the stop mode is cancelled, transiting to the reset sequence. Figure 8.5-2 shows the return from the sub-stop mode by an external reset. Figure 8.5-2 Return from the Sub-stop Mode by an External Reset RST pin Stop mode Main clock Oscillation stabilization wait During oscillation Subclock Oscillation stabilization wait During oscillation Oscillation stabilization wait During oscillation PLL clock CPU operation clock CPU operation PLL clock Main clock During stop Reset sequence Normal process Cancellation of stop mode Cancellation of reset 153 CHAPTER 8 LOW-POWER CONSUMPTION MODE ● Return by interrupt When an interrupt request higher than the interrupt level (IL) of 7 is generated from external interrupt in the stop mode, the stop mode is cancelled. In the stop mode, the main clock oscillation stabilization wait time or the sub clock oscillation stabilization wait time is generated after the stop mode is cancelled. After the termination of the main clock oscillation stabilization wait time or subclock oscillation stabilization wait time, as with normal interrupt processing, the generated interrupt request is identified according to the settings of the I flag in the condition code register (CCR), the interrupt level mask register (ILM), and the interrupt control register (ICR). • When the CPU is not ready to accept any interrupt request, the instruction next to the currently executing instruction is executed. • When the CPU is ready to accept any interrupt request, it immediately branches to the interrupt processing routine. Notes: • When interrupt processing is executed, the CPU normally executes the instruction following the instruction in which the stop mode has been specified. The CPU then proceeds to interrupt processing. When transiting to the PLL stop mode, set the oscillation stabilization wait time selection bits in the clock selection register (CKSCR: WS1, WS0) to "10B" or "11B". • In PLL stop mode, the main clock and PLL multiplication circuit stop. During recovery from PLL stop mode, it is necessary to allot the main clock oscillation stabilization wait time and PLL clock oscillation stabilization wait time. The oscillation stabilization wait times for the main clock and PLL clock are counted simultaneously according to the value specified in the oscillation stabilization wait time selection bits in the clock selection register (CKSCR: WS1, WS0). The oscillation stabilization wait time selection bits in the clock selection register (CKSCR: WS1, WS0) must be selected accordingly to account for the longer of main clock and PLL clock oscillation stabilization wait time. The PLL clock oscillation stabilization wait time, however, requires 214/HCLK or more. Set the oscillation stabilization wait time selection bits in the clock selection register (CKSCR: WS1, WS0) to "10B" or "11B". 154 CHAPTER 8 LOW-POWER CONSUMPTION MODE 8.6 Status Change Diagram Figure 8.6-1 shows the operation status and status transition in the clock mode and standby mode of the MB90360 series. ■ Status Change Diagram Figure 8.6-1 Status Change Diagram Drop power supply voltage (4.0 V) External reset, Watchdog timer reset, Software reset, Clock supervisor reset, CPU operation detection reset Power-on Low voltage detection reset Reset Power-on reset SCS=0 SCS=1 Terminate of oscillation stabilization wait Main clock mode MCS=0 PLL clock mode MCS=1 SLP=1 Interrupt Main sleep mode TMD=0 Interrupt Interrupt PLL sleep mode TMD=0 Interrupt PLL timebase timer mode STP=1 STP=1 Interrupt Terminate of oscillation stabilization wait Main clock oscillation stabilization wait Subclock mode SCS=1 SLP=1 Main timebase timer mode Main stop mode SCS=0 Interrupt Subsleep mode TMD=0 Interrupt Watch mode STP =1 PLL stop mode Interrupt SLP=1 Terminate of oscillation stabilization wait Main clock oscillation stabilization wait Substop mode Interrupt Terminate of oscillation stabilization wait Subclock oscillation stabilization wait 155 CHAPTER 8 LOW-POWER CONSUMPTION MODE 8.7 Status of Pins in Standby Mode and during Hold and Reset The status of I/O pins in the standby mode and during hold and reset are described for each memory access mode. ■ Status of I/O Pins (Single-chip Mode) Table 8.7-1 Status of I/O Pins (Single-chip Mode) At stop/watch/timebase timer Pin Name At sleep At a reset SPL=0 P27 to P20 P44, P43, P41, P40 P53 to P50 P67 to P60 P87 to P85, P83 Input cut off*4/ immediately preceding Immediately preceding state held*2 P42*7 P54 to P57 P80, P82, P84*7 *1: *2: *3: *4: *5: *6: *7: state held*2 SPL=1 Input cut off*4/ output Hi-Z*5 Input disabled*3/ output Hi-Z*5 Input enabled*1 Input enabled means that input function can be used. When the pin is set as input port, handle the pull-up/pull-down or input the external signal. When the pin is set as output port, the pin is set to the same state as other pins. Indicates that either the output pins output their state as it is immediately before entering each standby mode or the input pins are input-disabled. Output of the output state as it is means that when the resource with an output is in operation, the state of pins is output according to the state of the resource and, when the state of output pins is output, it is held. Input disabled means that no pin value can be accepted internally because the internal circuit is off while the operation of the input gates of pins is enabled. Input cut off means that the operation of the input gates of pins is disabled. Output Hi-Z means that the driving of pin driving transistors is disabled to place the pins in a high impedance state. In these modes, the pull-up function of the port 2 is invalid. When the INTxR bit of the external interrupt cause selection register (EISSR) is set to "1", these pins become "input enabled" in stop mode. When the bit is set to "0", they become the same state as other pins. Note: To set that pin to high impedance which serves either for a peripheral resource or as a port in stop mode, watch mode, or timebase timer mode, disable the output of the peripheral resource, then set the STP bit to "1" or set the TMD bit to "0" in the low-power consumption mode control register (LPMCR). 156 CHAPTER 8 LOW-POWER CONSUMPTION MODE 8.8 Usage Notes on Low-Power Consumption Mode This section explains the notes when using the low-power consumption modes. ■ Transition to Standby Mode When an interrupt request is generated from the resource to the CPU, the mode does not transit to each standby mode even after setting the STP and SLP bits to 1 and the TMD bit to 0 in the low-power consumption mode control register (LPMCR) (and also even after interrupt processing). If the CPU is servicing an interrupt, the interrupt-service-time interrupt request flag is cleared and the CPU can enter the standby mode unless any other interrupt request has been generated. ■ Notes on the Transition to Standby Mode To set a pin to high impedance when the pin is shared by a peripheral function and a port in stop mode, watch mode, or timebase timer mode, use the following procedure: 1. Disable the output of peripheral functions. 2. Set the SPL bit to "1", STP bit to "1", or TMD bit to "0" in the low-power consumption mode control register (LPMCR). ■ Cancellation of Standby Mode by Interrupt When an interrupt request higher than the interrupt level (IL) of 7 is generated from the resource and external interrupt during operation in the sleep mode, watch mode, timebase timer mode, or stop mode, the standby mode is cancelled. The standby mode is cancelled by an interrupt regardless of whether the CPU accepts interrupts or not. Note: To prevent the CPU from causing a branch to interrupt servicing immediately after returning from standby mode, take measures, such as disabling interrupts before setting the standby mode. ■ Note on Canceling Standby Mode The standby mode can be cancelled by an input according to the settings of an input factor of an external interrupt. The input factor can be selected from High level, Low level, rising edge, and falling edge. ■ Oscillation Stabilization Wait Time ● Oscillation stabilization wait time of main clock In the sub clock mode, watch mode, or stop mode, the oscillation of the main clock stops and the oscillation stabilization wait time of the main clock is required. The oscillation stabilization wait time of the main clock is set by the WS1 and WS0 bits in the clock selection register (CKSCR). ● Oscillation stabilization wait time of sub clock In the sub-stop mode, the oscillation of the sub clock (SCLK) stops and the oscillation stabilization wait time of the sub clock is required. The oscillation stabilization wait time of the sub clock is fixed at 214/ SCLK (SCLK: sub clock). 157 CHAPTER 8 LOW-POWER CONSUMPTION MODE ● PLL clock oscillation stabilization wait time In main clock mode, the PLL multiplication circuit stops. When changing to PLL clock mode, it is necessary to reserve the PLL clock oscillation stabilization wait time. The CPU runs in main clock mode till the PLL clock oscillation stabilization wait time has elapsed. When the main clock mode is switched to PLL clock mode, the PLL clock oscillation stabilization wait time is fixed at 214/HCLK (HCLK: oscillation clock). In sub-clock mode, the main clock and PLL multiplication circuit stop. When changing to PLL clock mode, it is necessary to reserve the main clock oscillation stabilization wait time and PLL clock oscillation stabilization wait time. The oscillation stabilization wait time for main clock and PLL clock are counted simultaneously according to the value specified in the oscillation stabilization wait time selection bits in the clock selection register (CKSCR: WS1, WS0). The oscillation stabilization wait time selection bits in the clock selection register (CKSCR: WS1, WS0) must be selected accordingly to account for the longer of the main clock and PLL clock oscillation stabilization wait time. The PLL clock oscillation stabilization wait time, however, requires 214/HCLK or more. Set the oscillation stabilization wait time selection bits in the clock selection register (CKSCR: WS1, WS0) to "10B" or "11B". In PLL stop mode, the main clock and PLL multiplication circuit stop. During recovery from PLL stop mode, it is necessary to allot the main clock oscillation stabilization wait time and PLL clock oscillation stabilization wait time. The oscillation stabilization wait time for the main clock and PLL clock are counted simultaneously according to the value specified in the oscillation stabilization wait time selection bits in the clock selection register (CKSCR: WS1, WS0). The oscillation stabilization wait time selection bits in the clock selection register (CKSCR: WS1, WS0) must be selected accordingly to account for the longer of main clock and PLL clock oscillation stabilization wait time. The PLL clock oscillation stabilization wait time, however, requires 214/HCLK or more. Set the oscillation stabilization wait time selection bits in the clock selection register (CKSCR: WS1, WS0) to "10B" or "11B". ■ Clock Mode Switching When the clock mode is switched, do not switch to other clock mode and low-power consumption mode before this switching is completed. Confirm the completion of clock mode switching by referring to the MCM and SCM bits of the clock selection register (CKSCR). If the mode is switched to other clock mode or low-power consumption mode before completion of switching, the mode may not be switched. ■ Notes on Accessing the Low-Power Consumption Mode Control Register (LPMCR) to Enter the Standby Mode ● To access the low-power consumption mode control register (LPMCR) with assembler language To set the low-power consumption mode control register (LPMCR) to enter the standby mode, use the instruction listed in Table 8.3-2 . The standby mode transition instruction in Table 8.3-2 must always be followed by an array of instructions highlighted by a line below. MOV LPMCR, #H’ xx; The low-power consumption mode transition instruction in Table 8.3-2 NOP NOP JMP $+3 MOV A, #H’ 10 158 ; Jump to the next instruction ; Arbitrary instruction CHAPTER 8 LOW-POWER CONSUMPTION MODE The devices does not guarantee its operation after returning from the standby mode if you place an array of instructions other than the one enclosed in the line. ● To access the low-power consumption mode control register (LPMCR) with C language To enter the standby mode using the low-power consumption mode control register (LPMCR), use one of the following methods 1. to 3. to access the register: 1. Specify the standby mode transition instruction as a function and insert two __wait_nop() built-in functions after that instruction. If any interrupt other than the interrupt to return from the standby mode can occur within the function, optimize the function during compilation to suppress the LINK and UNLINK instructions from occurring. Example: Watch mode or timebase timer mode transition function void enter_watch(){ IO_LPMCR.byte = 0x10; /* Set LPMCR TMD bit to 0 */ __wait_nop(); __wait_nop(); } 2. Define the standby mode transition instruction using __asm statements and insert two NOP and JMP instructions after that instruction. Example: Transition to sleep mode __asm("MOV I:_IO_LPMCR, #H’ 58); __asm("NOP"); __asm("OP"); __asm("JMP $+3"); /* Set LPMCR SLP bit to 1 */ /* Jump to the next instruction*/ 3. Define the standby mode transition instruction between #pragma asm and #pragma endasm and insert two NOP and JMP instructions after that instruction. Example: Transition to stop mode #pragma asm MOV I:_IO_LPMCR, #H’ 98 NOP NOP JMP $+3 #pragma endasm /* Set LPMCR STP bit to 1 */ /* Jump to the next instruction */ 159 CHAPTER 8 LOW-POWER CONSUMPTION MODE 160 CHAPTER 9 MEMORY ACCESS MODES This chapter explains the functions and operations of the memory access modes. 9.1 Outline of Memory Access Modes 161 CHAPTER 9 MEMORY ACCESS MODES 9.1 Outline of Memory Access Modes In the F2MC-16LX, various modes are provided for access methods and access areas. ■ Outline of Memory Access Modes Table 9.1-1 Mode Pin and Mode Operation mode RUN mode Flash programming Bus mode Single-chip − ● Operation mode Operation mode means the mode for controlling the device operation status. The operation mode is specified by the MDx mode setting pin and the Mx bit in mode data. By selecting an operation mode, normal operation activation or flash memory programming can be performed. ● Bus mode Bus mode means the mode for controlling the internal ROM operation and external access function. The bus mode is specified by the MDx mode setting pin and the Mx bit in mode data. The MDx mode setting pin specifies the bus mode for reading the reset vector and mode data, and the Mx bit in mode data specifies the bus mode for normal operation. ● Run mode Run mode means the CPU operation mode. The run mode has the main clock mode, PLL clock mode, and various low-power consumption mode. See CHAPTER 8 "LOW-POWER CONSUMPTION MODE" for details. 162 CHAPTER 9 MEMORY ACCESS MODES 9.1.1 Mode Pins Table 9.1-2 lists the operations that can be specified by combining the three external pins MD2 to MD0. ■ Mode Pins Table 9.1-2 Mode Pin and Mode Mode pin setting MD2 MD1 MD0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Mode name Reset vector access area External data bus width Remarks Setting disabled Internal vector mode Internal (Mode data) Reset sequence and subsequent sequences are controlled by mode data. Setting disabled Flash serial programming* − − Flash memory − − − Mode when parallel writer is used *: The serial programming of the flash memory cannot be written only by setting the mode pin. Other pin also need to be set. See "CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION" for details. 163 CHAPTER 9 MEMORY ACCESS MODES 9.1.2 Mode Data Mode data is stored at FFFFDFH of main memory and used for controlling the CPU operation. This data is fetched during a reset sequence and stored in the mode register inside the device. The mode register value can be changed only by a reset sequence. The setting of this register is valid after the reset sequence. Always set the reserved bits to "0". ■ Mode Data Figure 9.1-1 Mode Data Configuration Address: FFFFDFH 7 6 M1 M0 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved [bit7 and bit6] M1, M0 (bus mode setting bits) The M1 and M0 bits are used to specify the operation mode after the reset sequence is completed. Table 9.1-3 shows the relationship between the M1 and M0 bits and the functions. Table 9.1-3 Function of M1, M0 (bus mode setting bit) 164 M1 M0 Function 0 0 Single-chip mode 0 1 Setting disabled 1 0 1 1 Remarks CHAPTER 9 MEMORY ACCESS MODES 9.1.3 Memory Space in Each Bus Mode Figure 9.1-2 shows the correspondence between the access areas and physical addresses for each bus mode. ■ Memory Space in Each Bus Mode Figure 9.1-2 Relationship between Access Areas and Physical Addresses for Each Bus Mode FFFFFFH ROM area Address #1 010000H ROM area Image of FF Bank 008000H 007900H Extended I/O area Address #2 RAM 000100H 0000F0H Generalpurpose register I/O 000000H : Internal : Access disabled Single-chip Product type Address #1 Address #2 MB90F362/T(S), MB90362/T(S) MB90F367/T(S), MB90367/T(S) FF0000H 000D00H MB90V340A-101/102 F80000H 007900H 165 CHAPTER 9 MEMORY ACCESS MODES ■ Recommended Setting Table 9.1-4 lists an example of recommended settings for mode pins and mode data. Table 9.1-4 Recommended Setting Example of Mode Pin and Mode Data Setting example Single-chip MD2 MD1 MD0 0 1 1 External pins have signal functions that depend on each mode. 166 M1 0 M0 0 CHAPTER 10 I/O PORTS This chapter explains the functions and operations of the I/O ports. 10.1 I/O Ports 10.2 I/O Port Registers 167 CHAPTER 10 I/O PORTS 10.1 I/O Ports Each pin of the ports can be specified as input or output using the port direction register (DDR) if the corresponding peripheral does not use the pin. When a pin is specified as input, the logic level at the pin is read. When a pin is specified as output, the port data register value is read. The above also applies to a read operation for the read-modify-write instructions. ■ I/O Ports When a pin is used as an output of other peripheral function, the logic level at the pin is read regardless of the port data register value. It is generally recommended that the read-modify-write instructions should not be used for setting the port data register prior to setting the port as an output. This is because the read-modify-write instruction in this case results reading the logic level at the port rather than the register value. Figure 10.1-1 is a block diagram of the I/O ports. Figure 10.1-1 I/O Port Block Diagram Internal data bus Port data register read Port data register Port data register write Port direction register Port direction register write Port direction register read 168 Pin CHAPTER 10 I/O PORTS 10.2 I/O Port Registers There are five types of I/O port registers: • Port data register (PDR2, PDR4 to PDR6, PDR8) • Port direction register (DDR2, DDR4 to DDR6, DDR8, DDRA) • Pull-up control register (PUCR2) • Analog input enable register (ADER5, ADER6) • Input level select register (ILSR0, ILSR1) ■ I/O Port Registers Figure 10.2-1 shows the I/O port registers. Figure 10.2-1 I/O Port Registers Bit No. Address: 000002H Address: 000004H Address: 000005H Address: 000006H Address: 000008H Bit No. Address: 000012H Address: 000014H Address: 000015H Address: 000016H Address: 000018H Address: 00001AH Bit No. Address: 00001EH Bit No. Address: 00000BH Address: 00000CH Bit No. Address: 00000EH Address: 00000FH 7 6 5 4 3 2 1 0 P27 P26 P25 P24 P23 P22 P21 P20 − − P44 P43 P42 P41 P40 P57 P56 P55 P54 P53 P52 P51 P50 P67 P66 P65 P64 P63 P62 P61 P60 P87 P86 P85 P84 P83 P82 − P80 7 6 5 4 3 2 1 0 D27 D26 D25 D24 D23 D22 D21 D20 − D44 D43 D42 D41 D40 − − − D57 D56 D55 D54 D53 D52 D51 D50 D67 D66 D65 D64 D63 D62 D61 D60 D87 D86 D85 D84 D83 D82 − − − SIL1 SIL0 − 7 6 4 3 2 5 − − 1 D80 − 14/6 13/5 12/4 11/3 10/2 9/1 Port 2 direction register (DDR2) Port 4 direction register (DDR4) Port 5 direction register (DDR5) Port 6 direction register (DDR6) Port 8 direction register (DDR8) Port A direction register (DDRA) 0 PU27 PU26 PU25 PU24 PU23 PU22 PU21 PU20 15/7 Port 2 data register (PDR2) Port 4 data register (PDR4) Port 5 data register (PDR5) Port 6 data register (PDR6) Port 8 data register (PDR8) Port 2 pull-up control register (PUCR2) 8/0 ADE15 ADE14 ADE13 ADE12 ADE11 ADE10 ADE9 ADE8 ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 15/7 14/6 13/5 12/4 11/3 10/2 9/1 − IL6 IL5 IL4 − IL2 − − − − − − − − − IL8 Port 5 analog input enable register (ADER5) Port 6 analog input enable register (ADER6) 8/0 Input level select register (ILSR0) Input level select register (ILSR1) 169 CHAPTER 10 I/O PORTS 10.2.1 Port Data Register (PDR) Note that R/W for I/O ports differ from R/W for memory in the following points: • Input mode Read: The level at the corresponding pin is read. Write: Data is written to an output latch. • Output mode Read: The port data register latch value is read. Write: Data is written to an output latch and outputted to the corresponding pin. Figure 10.2-2 shows the port data registers (PDR). ■ Port Data Register (PDR) Figure 10.2-2 Port Data Registers (PDR) Reset value Bit No. PDR2 Address: 000002H Bit No. PDR4 Address: 000004H Bit No. PDR5 Address: 000005H 170 7 6 5 4 3 2 1 0 P27 P26 P25 P24 P23 P22 P21 P20 7 6 5 4 3 2 1 0 P44 P43 P42 P41 P40 7 6 5 4 3 2 1 0 P57 P56 P55 P54 P53 P52 P51 P50 Bit No. PDR6 Address: 000006H 7 6 5 4 3 2 1 0 P67 P66 P65 P64 P63 P62 P61 P60 Bit No. PDR8 Address: 000008H 7 6 5 4 3 2 1 P87 P86 P85 P84 P83 P82 Access Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W 0 P80 CHAPTER 10 I/O PORTS ● Reading the port data register The value obtained when reading the port data register (PDR) depends on the status of the port direction register (DDR) and status of the peripheral function connected to the pin. The following shows the value obtained by each combination. Value of DDR Output state of peripheral function Reading value 0 (input) Enabled Output value from peripheral function 1 (output) Enabled Output value from peripheral function 0 (input) Disabled Pin state 1 (output) Disabled Value of output latch Further, when using as input by peripheral function, set the DDR of the connected pin to "0" (input). 171 CHAPTER 10 I/O PORTS 10.2.2 Port Direction Register (DDR) This register has following functions: • Setting the data direction of each pin that is used as a port. • Setting the input level of SIN -- Serial data input pin for LIN-UART. ■ Port Direction Register (DDR) Figure 10.2-3 shows the Port Direction Registers (DDR). Figure 10.2-3 Port Direction Registers (DDR) Bit No. DDR2 Address: 000012H Bit No. DDR4 Address: 000014H Bit No. DDR5 Address: 000015H Bit No. DDR6 Address: 000016H Bit No. DDR8 Address: 000018H Bit No. DDRA Address: 00001AH Reset value 7 6 5 4 3 2 1 0 D27 D26 D25 D24 D23 D22 D21 D20 7 6 5 4 3 2 1 0 D44 D43 D42 D41 D40 7 6 5 4 3 2 1 0 D57 D56 D55 D54 D53 D52 D51 D50 7 6 5 4 3 2 1 0 D67 D66 D65 D64 D63 D62 D61 D60 1 7 6 5 4 3 2 D87 D86 D85 D84 D83 D82 7 6 5 4 3 2 00000000B R/W XXX00000B R/W 00000000B R/W 00000000B R/W 000000X0B R/W 0 D80 1 0 SIL1 SIL0 W Access Access XXX00XXXB W Bits Dxx (DDR2, DDR4 to DDR6, DDR8) These bits set to the I/O direction of the port. When each pin is used as port, the corresponding pin is controlled below. When set to "0": The corresponding pin is set to input mode. When set to "1": The corresponding pin is set to output mode. Bits SIL0, SIL1 (DDRA bit3, bit4) These bits set the input level of the corresponding SIN (Serial Data Input for LIN-UART) pin forcibly. SIL0 to SIL1 correspond to SIN0 (LIN-UART0) to SIN1(LIN-UART1), respectively. When setting to “0”: CMOS or Automotive is selected for the input level depending on the setting of the corresponding ILx bit and ILTx bit in the ILSR. (See "10.2.5 Input Level Select Register" for ILSR.) When set to “1”: CMOS is selected for the input level regardless of the setting of the corresponding ILx bit and ILTx bit in ILSR. The initial value of these bits is “0”. 172 CHAPTER 10 I/O PORTS Table 10.2-1 SIN0/SIN1 Input Level Setting DDRA ILSR SIL0/SIL1 bit IL8 bit 0 0 Automotive level 0 1 CMOS level 1 x CMOS level SIN0(P82) / SIN1(P85) input level Note: SIL0, SIL1 are write-only, and “1” is always read from these bits. Therefore, instructions that perform a read-modify-write (RMW) operation such as the INC/DEC instruction, cannot be used at DDRA. ● DDRA: Bits 0 to 2, Bits 5 to 7 (unused bits) "1" is always read from these bits. Writing to these bits is no effect. 173 CHAPTER 10 I/O PORTS 10.2.3 Pull-up Control Register (PUCR) Each pin of port2 has programmable pull-up resistor. Each bit of this register controls corresponding pull-up resistor whether to be used or not. Figure 10.2-4 shows the pull-up control register (PUCR), and Figure 10.2-5 is the block diagram. ■ Pull-up Control Register (PUCR) Figure 10.2-4 Pull-up Control Register (PUCR) 7 Address: 00001EH 6 5 4 3 2 1 0 PU27 PU26 PU25 PU24 PU23 PU22 PU21 PU20 Read/Write Initial value Bit No. PUCR2 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) R/W: Read/Write ■ Block Diagram of Pull-up Control Register (PUCR) Figure 10.2-5 Block Diagram of Pull-up Control Register (PUCR) Pull-up resistor (approx. 50 kΩ) Port data register Port I/O Port direction register Pull-up control register Internal data bus In input mode, the pull-up resistor is controlled. 0: No pull-up resistor in input mode 1: Pull-up resistor in input mode Note: In output mode, this register has no meaning (no pull-up resistor). The port direction register (DDR) determines the input-output mode. In stop mode (SPL=1), the state with no pull-up resistor is entered (high impedance). 174 CHAPTER 10 I/O PORTS 10.2.4 Analog Input Enable Register (ADER) Figure 10.2-6 shows the analog input enable register. ■ Analog Input Enable Registers (ADER) Figure 10.2-6 Analog Input Enable Registers (ADER6, ADER5) ADER6 Address: 00000CH ADER5 Address: 00000BH 7 6 5 4 3 2 1 0 ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 15 14 13 12 11 10 9 8 ADE15 ADE14 ADE13 ADE12 ADE11 ADE10 ADE9 ADE8 Initial value Access 11111111B R/W 11111111B R/W R/W: Read/Write Each bit of ADER6/ADER5 sets to enable/disable the analog input of each pin in the port 6 and port 5. ADER6 and ADER5 correspond to the port 6 and port 5, respectively. When set to "0": The corresponding pin is set to disable the analog input. A pin set to disable the analog input can be used as I/O pin for peripheral function other than I/O port and A/D converter. When set to "1": The corresponding pin is set to the analog input mode. A pin set to the analog input mode is the dedicated analog input pin for the A/D converter. The pin cannot be used as I/O pin of I/O port and other peripheral function. Note: When the analog input enable bit (ADEx) is set to "1", each pin of the port 6 and port 5 is the analog input pin for the A/D converter. Initial value of the ADEx bit is "1". Therefore, the corresponding pins cannot be used as I/O pin of peripheral function other than I/O port and A/D converter at the initial setting. When the pin is used as I/O pin of other peripheral function and I/O port, the ADEx bit is set to "0". 175 CHAPTER 10 I/O PORTS 10.2.5 Input Level Select Register The input level select register allows to switch from Automotive Hysteresis input levels to CMOS Hysteresis input levels. ■ Input Level Select Register (ILSR) The input level select register ILSR is located on addresses 0EH and 0FH. Figure 10.2-7 Input Level Select Register (ILSR) Address ILSR1 : 00000FH ILSR0 : 00000EH Initial value: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 − − − − − − − IL8 − IL6 IL5 IL4 − IL2 − − − − − − − − − R/W − R/W R/W R/W − R/W − − X X X X X X X 0/1 X 0/1 X 0/1 X X 0/1 0/1 R/W : Read/Write − : Unused X : Undefined bit 2, bit 4 to bit6 and bit8:IL2, IL4 to IL6, IL8 These bits set the input level of the corresponding port. IL2, IL4 to IL6, IL8 correspond to the port 2, port 4 to port 6, port 8, respectively. Setting these bits to “0” selects the Automotive input level. Setting these bits to “1” selects the CMOS hysteresis input level. The initial value of these bits depends on the mode pin setting: • For the flash memory mode, the initial value is “1” (TTL). • For all other modes, the initial value is "0" (Automotive). bit 0, bit 1, bit 3, bit 7 and bit 9 to bit 15: undefined Reading from these bits is undefined. Writing to these bits is no effect. Note: The threshold of the corresponding input pin varies immediately after the setting of the input level select register is changed. Therefore, do not use the read value from the pin until 2 machine cycles are elapsed after the setting is changed. When the setting is changed, be sure to disable the corresponding resource. 176 CHAPTER 10 I/O PORTS ■ Initial value of ILSR Initial value of each bit of ILSR is determined when external reset signal is released depending on the value of MD2, MD1, MD0 pin input, as shown in following table. About detail of each mode, please see "CHAPTER 9 MEMORY ACCESS MODES". Table 10.2-2 Relationship between Mode Pin and Initial Value of Input Level Select Register (ILSR) MD2 MD1 MD0 Operation mode Initial value Port input level ILx Port 2, 4 to 6, 8 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 Flash serial write 0 Automotive 1 1 1 Flash memory 1 TTL Reserved Internal vector mode 0 Automotive Reserved 177 CHAPTER 10 I/O PORTS 178 CHAPTER 11 TIMEBASE TIMER This chapter explains the functions and operations of the timebase timer. 11.1 Overview of Timebase Timer 11.2 Block Diagram of Timebase Timer 11.3 Configuration of Timebase Timer 11.4 Interrupt of Timebase Timer 11.5 Explanation of Operations of Timebase Timer Functions 11.6 Precautions when Using Timebase Timer 11.7 Program Example of Timebase Timer 179 CHAPTER 11 TIMEBASE TIMER 11.1 Overview of Timebase Timer The timebase timer is an 18-bit free-run counter (timebase timer counter) that increments in synchronization with the main clock (half frequency of main oscillation clock). • Four interval times can be selected and an interrupt request can be generated for each interval time. • An operation clock is supplied to the oscillation stabilization wait time timer and other peripherals. ■ Interval Timer Function • When the timebase timer counter reaches the interval time set by the interval time select bits (TBTC: TBC1, TBC0), an overflow (carrying) occurs (TBTC: TBOF = 1) and an interrupt request is generated. • When an interrupt is enabled when an overflow occurs (TBTC: TBIE = 1), an overflow occurs (TBTC: TBOF = 1) and an interrupt is generated. • The timebase timer has four interval times that can be selected. Table 11.1-1 shows the interval times of the timebase timer. Table 11.1-1 Interval Times of Timebase Timer Count clock 2/HCLK(0.5 µs) Interval time 212/HCLK (approx. 1.0 ms) 214/HCLK (approx. 4.1 ms) 216/HCLK (approx. 16.4 ms) 219/HCLK (approx. 131.1 ms) HCLK: Oscillation clock The parenthesized values are provided at 4-MHz oscillation clock. 180 CHAPTER 11 TIMEBASE TIMER ■ Clock Supply The timebase timer supplies an operation clock to the resources such as an oscillation stabilization wait time timer, PPG timer, and watchdog timer. Table 11.1-2 shows the clock cycles supplied from the timebase timer to each resource. Table 11.1-2 Clock Cycles Supplied from Timebase Timer Where to supply clock Clock cycle Oscillation stabilization wait time* 210/HCLK (approx. 256 µs) 213/HCLK (approx. 2.0 ms) 215/HCLK (approx. 8.2 ms) 217/HCLK (approx. 32.8 ms) Watchdog timer 212/HCLK (approx. 1.0 ms) 214/HCLK (approx. 4.1 ms) 216/HCLK (approx. 16.4 ms) 219/HCLK (approx. 131.1 ms) PPG timer 29/HCLK (approx. 128 µs) HCLK: Oscillation clock The parenthesized values are provided at 4-MHz oscillation clock. *:As the oscillation cycle is unstable immediately after oscillation starts, standard oscillation stabilization wait time values are given as a guide. 181 CHAPTER 11 TIMEBASE TIMER 11.2 Block Diagram of Timebase Timer The timebase timer consists of the following blocks: • Timebase timer counter • Counter clear circuit • Interval timer selector • Timebase timer control register (TBTC) ■ Block Diagram of Timebase Timer Figure 11.2-1 Block Diagram of Timebase Timer To watchdog timer To PPG timer Timebase timer counter 21/HCLK 21 22 28 23 29 210 211 OF 212 OF 213 214 215 216 217 218 OF OF To clock control part oscillation stabilization waiting time selector Power-on reset Stop mode CKSCR : MCS=1 0*1 CKSCR : SCS=0 1*2 Counter clear circuit TBOF clear Timebase timer control register (TBTC) Reserved Interval timer selector TBOF set TBIE TBOF TBR TBC1 TBC0 Timebase timer interrupt signal OF HCLK *1 *2 : Overflow : Oscillation clock : For switching machine clock from main clock to PLL clock : For switching machine clock from sub clock to main clock The actual interrupt request number of the timebase timer is as follows: Interrupt request number: #25 (19H) 182 CHAPTER 11 TIMEBASE TIMER ● Timebase timer counter The timebase timer counter is an 18-bit up counter that uses a clock with a half frequency of the oscillation clock (HCLK) as a count clock. ● Counter clear circuit The counter clear circuit clears the value of the timebase timer counter by the following factors: • Timebase timer counter clear bit in the timebase timer control register (TBTC: TBR=0) • Power-on reset • Transition to main stop mode or PLL stop mode (CKSCR:SCS=1, LPMCR: STP=1) • Switching the clock mode (from main clock mode to PLL clock mode, from subclock mode to PLL clock mode, or from subclock mode to main clock mode) ● Interval timer selector The interval timer selector selects the output of the timebase timer counter from four types. When incrementing causes the selected interval time bit to overflow (carrying), an interrupt request is generated. ● Timebase timer control register (TBTC) The timebase timer control register (TBTC) selects the interval time, clears the timebase timer counter, enables or disables interrupts, and checks and clears the state of an interrupt request. 183 CHAPTER 11 TIMEBASE TIMER 11.3 Configuration of Timebase Timer This section explains the registers and interrupt factors of the timebase timer. ■ List of Registers and Reset Values of Timebase Timer Figure 11.3-1 List of Registers and Reset Values of Timebase Timer bit Timebase timer control register (TBTC) 15 14 13 1 12 11 10 9 8 0 0 1 0 0 : Undefined ■ Generation of Interrupt Request from Timebase Timer When the selected interval timer counter bit reaches the interval time, the overflow interrupt request flag bit in the timebase timer control register (TBTC: TBOF) is set to "1". If the overflow interrupt request flag bit is set (TBTC: TBOF = 1) when the interrupt is enabled (TBTC: TBIE = 1), the timebase timer generates an interrupt request. 184 CHAPTER 11 TIMEBASE TIMER 11.3.1 Timebase timer control register (TBTC) The timebase timer control register (TBTC) provides the following settings: • Selecting the interval time of the timebase timer • Clearing the counter value of the timebase timer • Enabling or disabling the interrupt request when an overflow occurs • Checking and clearing the state of the interrupt request flag when an overflow occurs ■ Timebase Timer Control Register (TBTC) Figure 11.3-2 Timebase Timer Control Register (TBTC) Address 15 0000A9H Reserved TBIE TBOF TBR TBC1 TBC0 R/W R/W R/W W R/W R/W 14 13 12 11 10 9 8 Reset value 1XX00100B bit9 bit8 TBC1 TBC0 Interval time select bit 0 0 212/HCLK (approx. 1.0 ms) 0 1 214/HCLK (approx. 4.1 ms) 1 0 216/HCLK (approx. 16.4 ms) 1 1 219/HCLK (approx. 131.1 ms) HCLK: Oscillation clock The parenthesized values are provided when the oscillation clock operates at 4 MHz. bit10 TBR Timebase timer counter clear bit Read Write 0 Clear timebase timer counter. Clear TBOF bit. "1" is always read. 1 No effect bit11 TBOF Overflow interrupt request flag bit Read Write 0 Without overflow of selected Being clear. count bit 1 With overflow of selected count bit No effect bit12 TBIE Overflow interrupt enable bit 0 Disabling of overflow interrupt request 1 Enabling of overflow interrupt request bit15 R/W : Read/write : Write only W : Indeterminate X : Reset value : Undefined Reserved bit Reserved 1 "1" is always set. 185 CHAPTER 11 TIMEBASE TIMER Table 11.3-1 Functions of Timebase Timer Control Register (TBTC) Bit name Function bit15 Reserved: reserved bit Always set this bit to "1". bit14 bit13 Undefined bits Read: The value is undefined. Write: No effect bit12 TBIE: Overflow interrupt enable bit This bit enables or disables an interrupt when the interval timer bit in the timebase timer counter overflows. When set to "0": No interrupt request is generated at an overflow (TBOF = 1). When set to "1": An interrupt request is generated at an overflow (TBOF = 1). bit11 TBOF: Overflow interrupt request flag bit This bit indicates an overflow (carrying) in the interval timer bit in the timebase timer counter. When an overflow (carrying) occurs (TBOF = 1) with interrupts enabled (TBIE = 1), an interrupt request is generated. When set to "0": The bit is cleared. When set to "1": Disabled. The state remains unchanged. Read by read modify write instructions: "1" is read. Note: 1) To clear the TBOF bit, disable interrupts (TBIE = 0) or mask interrupts using the interrupt mask register (ILM) in the processor status. 2) The TBOF bit is cleared at a write of "0", transition to main stop mode or to PLL stop mode, transition from subclock mode to main clock mode or to PLL clock mode, transition from main clock mode to PLL clock mode, at a write of "0" to the timebase timer counter clear bit (TBR), or at a reset. bit10 TBR: Timebase timer counter clear bit This bit clears all the bits in the timebase timer counter. When set to "0" : All the bits in the timebase timer counter are cleared to "0". The TBOF bit is also cleared. When set to "1" : Disabled. The state remains unchanged. Read : "1" is always read. bit9 bit8 TBC1, TBC0: Interval time select bits These bits set the cycle of the interval timer in the timebase timer counter. • The interval time of the timebase timer is set according to the setting of the TBC1 and TBC0 bits. • One of four time intervals can be selected. 186 CHAPTER 11 TIMEBASE TIMER 11.4 Interrupt of Timebase Timer The timebase timer generates an interrupt request (interval timer function) when the interval time bit in the timebase timer counter corresponding to the interval time set by the timebase timer control register carries (overflows). ■ Interrupt of Timebase Timer • The timebase timer continues incrementing for as long as the main clock (with a half frequency of the oscillation clock) is inputted. • When the interval time set by the interval time select bits in the timebase timer control register (TBTC: TBC1, TBC0) is reached, the interval time select bit corresponding to the interval time selected in the timebase timer counter carries and an overflow generates. • When the interval time select bit overflows, the overflow interrupt request flag bit in the timebase timer control register (TBTC: TBOF) is set to "1". • When the overflow interrupt request flag bit in the timebase timer control register is set (TBTC: TBOF = 1) with an interrupt enabled (TBTC: TBIE = 1), an interrupt request is generated. • When the selected interval time is reached, the overflow interrupt request flag bit in the timebase timer control register (TBTC: TBOF) is set regardless of whether an interrupt is enabled or disabled (TBTC: TBIE) • To clear the overflow interrupt request flag bit (TBTC: TBOF), disable a timebase timer interrupt at interrupt processing (TBTC: TBIE = 0) or mask a timebase timer interrupt by using the ILM bit in the processor status (PS) to write "0" to the TBOF bit. Note: An interrupt request is issued immediately if you enable interrupts (TBTC: TBIE = 1) with the overflow interrupt request flag bit in the timebase timer control register set (TBTC: TBOF = 1). ■ Correspondence between Timebase Timer Interrupt and EI2OS • The timebase timer does not correspond to EI2OS. • For details of the interrupt number, interrupt control register, and interrupt vector address, see "3.2 Interrupt Vector". 187 CHAPTER 11 TIMEBASE TIMER 11.5 Explanation of Operations of Timebase Timer Functions The timebase timer operates as an interval timer or an oscillation stabilization wait time timer. It also supplies a clock to peripherals. ■ Interval Timer Function Interrupt generation at every interval time enables the timebase timer to be used as an interval timer. Operating the timebase timer as an interval timer requires the settings shown in Figure 11.5-1 . ● Setting of timebase timer Figure 11.5-1 Setting of Timebase Timer bit15 14 Timebase timer control register (TBTC) Reserved 1 13 12 11 10 9 bit8 TBIE TBOF TBR TBC1TBC0 0 0 : Undefined bit : Used bit 0 : Set to "0". 1 : Set to "1". ● Operations of the Interval Timer Functions The timebase timer can be used as an interval timer by generating an interrupt at every set interval time. • The timebase timer continues incrementing in synchronization with the main clock (a half frequency of the oscillation clock) while the oscillation clock is active. • When the timebase timer counter reaches the interval time set by the interval time select bits in the timebase timer control register (TBTC: TBC1, TBC0), it causes an overflow (carrying) and the overflow interrupt request flag bit (TBTC: TBOF) is set to "1". • When the overflow interrupt request flag bit is set (TBTC: TBOF = 1) with interrupts enabled (TBTC: TBIE = 1), an interrupt request is generated. Note: The interval time may be longer than the one set by clearing the timebase timer counter. ● Example of operation for timebase timer Figure 11.5-2 gives an example of the operation that the timebase timer performs under the following conditions: • A power-on reset occurs. • The mode transits to the sleep mode during the operation of the interval timer. • The mode transits to the stop mode during the operation of the interval timer. • A request to clear the timebase timer counter is issued. 188 CHAPTER 11 TIMEBASE TIMER At transition to the stop mode, the timebase timer counter is cleared to stop counting up. At return from the stop mode, the timebase timer counts the oscillation stabilization wait time of the main clock. Figure 11.5-2 Example of Operation for Timebase Timer Counter value Clear by transferring to stop mode 3FFFFH Oscillation stabilization waiting overflow 00000H Start CPU operation Power-on reset Interval cycle (TBTC: TBC1: TBC0 = 11B) Counter clear (TBTC: TBR = 0) Clear by interrupt process TBOF bit TBIE bit Sleep SLP bit (LPMCR register) Cancellation of sleep at interval interrupt of timebase timer Stop STP bit (LPMCR register) When set the interval time select bit (TBTC:TBC1, TBC0) to "11B"(219/HCLK) : Oscillation stabilization waiting time HCLK : Oscillation clock 189 CHAPTER 11 TIMEBASE TIMER ■ Operation as Oscillation Stabilization Wait Time Timer The timebase timer can be used as the oscillation stabilization wait time timer for the main clock and PLL clock. The oscillation stabilization wait time is the time elapsed from when the timebase timer counter increments from "0" until the set oscillation stabilization wait time select bit overflows (carrying). Table 11.5-1 shows clearing conditions and oscillation stabilization wait time of timebase timer. Table 11.5-1 Clearing Conditions and Oscillation Stabilization Wait Time of Timebase Timer (1/2) Operation Counter clear TBOF clear ❍ ❍ Power-on reset ❍ ❍ Transition to main clock mode after oscillation stabilization wait time of main clock completed Watchdog reset ✕ ❍ None External reset Low voltage detection reset CPU operation detection reset Clock supervisor reset ✕ ❍ None Software reset ✕ ❍ None Main clock → PLL clock (CKSCR: MCS=1 → 0) ❍ ❍ Transition to PLL clock mode after oscillation stabilization wait time of PLL clock completed Main clock → sub clock (CKSCR: SCS=1 → 0) ✕ ✕ Transition to sub clock mode after oscillation stabilization wait time of sub clock completed Sub clock → main clock (CKSCR: SCS=0 → 1) ❍ ❍ Transition to main clock mode after oscillation stabilization wait time of main clock completed Sub clock → PLL clock (CKSCR: MCS=0, SCS=0 → 1) ❍ ❍ Transition to PLL clock mode after oscillation stabilization wait time of main clock completed PLL clock → main clock (CKSCR: MCS=0 → 1) ✕ ✕ None PLL clock → sub clock (CKSCR: MCS=0, SCS=1 → 0) ✕ ✕ None Writing "0" to timebase timer counter clear bit (TBTC: TBR) Oscillation stabilization wait time Reset Switching clock mode 190 CHAPTER 11 TIMEBASE TIMER Table 11.5-1 Clearing Conditions and Oscillation Stabilization Wait Time of Timebase Timer (2/2) Operation Counter clear TBOF clear Oscillation stabilization wait time Cancellation of stop modes Cancellation of main stop mode ❍ ❍ Transition to main clock mode after oscillation stabilization wait time of main clock completed Cancellation of PLL stop mode ❍ ❍ Transition to PLL clock mode after oscillation stabilization wait time of main clock completed Cancellation of sub-stop mode ✕ ✕ Transition to sub clock mode after oscillation stabilization wait time of sub clock completed ✕ ✕ None Return to main clock mode ✕ ✕ None Return to sub clock mode ✕ ✕ None Return to PLL clock mode ✕ ✕ None Cancellation of main sleep mode ✕ ✕ None Cancellation of sub-sleep mode ✕ ✕ None Cancellation of PLL sleep mode ✕ ✕ None Cancellation of watch mode Cancellation of sub-watch mode Cancellation of timebase timer modes Cancellation of sleep modes ■ Supply of Operation Clock The timebase timer supplies an operation clock to the PPG timers and the watchdog timer. Note: Clearing the timebase timer counter may affect the operation of the resources such as the watchdog timer and PPG timers using the output of the timebase timer. References: • For details on the PPG timer, see "CHAPTER 16 8-/16-BIT PPG TIMER". • For details on the watchdog timer, see "CHAPTER 12 WATCHDOG TIMER". 191 CHAPTER 11 TIMEBASE TIMER 11.6 Precautions when Using Timebase Timer Precautions when using the timebase timer are shown below. ■ Precautions when Using Timebase Timer ● Clearing interrupt request To clear the overflow interrupt request flag bit in the timebase timer control register (TBTC: TBOF = 0), disable interrupts (TBTC: TBIE = 0) or mask the timebase timer interrupt by using the interrupt level mask register in the processor status. ● Clearing timebase timer counter Clearing the timebase timer counter affects the following operations: • When the timebase timer is used as the interval timer (interval interrupt). • When the watchdog timer is used. • When the clock supplied from the timebase timer is used as the operation clock of the PPG timer. ● Using timebase timer as oscillation stabilization wait time timer After power on or in the main stop mode, PLL stop mode, and sub clock mode, the oscillation clock stops. Therefore, when oscillation starts, the timebase timer requires the oscillation stabilization wait time of the main clock. An appropriate oscillation stabilization wait time must be selected according to the types of oscillators connected to high-speed oscillation input pins. Reference: For details on the oscillation stabilization wait time, see "5.6 Oscillation Stabilization Wait Interval". ● Resources to which timebase timer supplies clock • At transition to operation modes (PLL stop mode, sub clock mode, and main stop mode) in which the oscillation clock stops, the timebase timer counter is cleared and the timebase timer stops. • When the timebase timer counter is cleared, an after-clearing interval time is needed. It may cause the clock supplied from the timebase timer to have a short High level or a 1/2 cycle longer Low level. • The watchdog timer performs normal counting because the watchdog timer counter and timebase timer counter are cleared simultaneously. 192 CHAPTER 11 TIMEBASE TIMER 11.7 Program Example of Timebase Timer Programming examples for the timebase timer are shown below. ■ Program Example of Timebase Timer ● Processing specification The 212/HCLK (HCLK: oscillation clock) interval interrupt is generated repeatedly. In this case, the interval time is approximately 1.0 ms (at 4-MHz operation). ● Coding example ICR07 EQU 0000B7H ;Timebase timer interrupt control register TBTC EQU 0000A9H ;Timebase timer control register TBOF EQU TBTC:3 ;Interrupt request flag bit TBIE EQU TBTC:2 ;Interrupt enable bit ;-------Main program--------------------------------------CODE CSEG START: ;Stack pointer(SP), already initialized AND CCR,#0BFH ;Interrupt disable MOV I:ICR07 #00H ;Interrupt level 0(highest) MOV I:TBTC,#10000000B ;Upper 3 bis are fixed ;TBOF clear, ;Counter clear interval time ;212/HCLK selection ;Interrupt enable ;Setting ILM in PS to level 7 ;Interrupt enable ;No limit loop SETB I:TBIE MOV ILM,#07H OR CCR,#40H LOOP: MOV A,#00H MOV A,#01H BRA LOOP ;-------Interrupt program-----------------------------------WARI: CLRB I:TBIE ;Clear interrupt enable bit CLRB I:TBOF ;Clear interrupt request flag : User processing : SETB I:TBIE ;Interrupt enable RETI ;Recovery from interrupt processing CODE ENDS ;-------Vector setting---------------------------------------VECT CSEG ABS=0FFH ORG 0FF98H ;Vector setting to interrupt number #25(19H) 193 CHAPTER 11 TIMEBASE TIMER VECT 194 DSL ORG DSL DB ENDS END WARI 0FFDCH START 00H START ;Reset vector setting ;Setting to single-chip mode CHAPTER 12 WATCHDOG TIMER This chapter describes the function and operation of the watchdog timer. 12.1 Overview of Watchdog Timer 12.2 Configuration of Watchdog Timer 12.3 Watchdog Timer Registers 12.4 Explanation of Operations of Watchdog Timer Functions 12.5 Precautions when Using Watchdog Timer 12.6 Program Examples of Watchdog Timer 195 CHAPTER 12 WATCHDOG TIMER 12.1 Overview of Watchdog Timer The watchdog timer is a 2-bit counter that uses the timebase timer or watch timer as a count clock. If the counter is not cleared within a set interval time, the CPU is reset. ■ Functions of Watchdog Timer • The watchdog timer is a timer counter that is used to prevent program malfunction. When the watchdog timer is started, the watchdog timer counter must continue to be cleared within a set interval time. If the set interval time is reached without clearing the watchdog timer counter, the CPU is reset. This is called watchdog timer. • The interval time of the watchdog timer depends on the clock cycle input as a count clock and a watchdog reset occurs between the minimum and maximum times. • The clock source output destination is set by the watchdog clock select bit in the watch timer control register (WTC: WDCS). • The interval time of the watchdog timer is set by the timebase timer output select bit/watch timer output select bit in the watchdog timer control register (WDTC: WT1, WT0). Table 12.1-1 lists the interval times of the watchdog timer. 196 CHAPTER 12 WATCHDOG TIMER Table 12.1-1 Interval Time of Watchdog Timer Main Examples calculated Clock cycle External clock(@4MHz) CR oscillation Min. Max. Min. (@200kHz) (@50kHz) Max. 214 ± 211 /HCLK Approx. 3.58 ms Approx. 4.61 ms Approx. 0.072 s Approx. 0.369 s 216 ± 213 /HCLK Approx. 14.33 ms Approx. 18.4 ms Approx. 0.287 s Approx. 1.475 s 218 ± 215 /HCLK Approx. 57.34 ms Approx. 73.73 ms Approx. 1.147 s Approx. 5.898 s 221 ± 218 /HCLK Approx. 458.75 ms Approx. 589.82 ms Approx. 9.175 s Approx. 47.186 s Sub Examples calculated Clock cycle External clock (@32kHz, 4-frequency division) CR oscillation Min. Max. Min. (@200kHz) (@50kHz) Max. 212 ± 29 /SCLK Approx. 0.437 s Approx. 0.563 s Approx. 0.018 s Approx. 0.092 s 215 ± 212 /SCLK Approx. 3.500 s Approx. 4.500 s Approx. 0.143 s Approx. 0.737 s 216 ± 213 /SCLK Approx. 7.000 s Approx. 9.000 s Approx. 0.287 s Approx. 1.475 s 217 ± 214 /SCLK Approx. 14.000 s Approx. 18.000 s Approx. 0.573 s Approx. 2.949 s Note: See "CHAPTER 6 CLOCK SUPERVISOR" for the CR oscillation. 197 CHAPTER 12 WATCHDOG TIMER Notes: • When the timebase timer output (carry signal) is used as a count clock to the watchdog timer, clearing the timebase timer may extend the time for a watchdog reset to occur. • When the subclock is used as the machine cock, be sure to set the watchdog timer clock source select bit (WDCS) in the watch timer control register (WTC) to "0" to select the watch timer output. 198 CHAPTER 12 WATCHDOG TIMER 12.2 Configuration of Watchdog Timer The watchdog timer consists of the following blocks: • Count clock selector • Watchdog timer counter (2-bit counter) • Watchdog reset generator • Counter clear control circuit • Watchdog timer control register (WDTC) ■ Block Diagram of Watchdog Timer Figure 12.2-1 Block Diagram of Watchdog Timer Watch timer control register (WTC) Watchdog timer control register (WDTC) PONR WRST ERST SRST WTE WT1 WT0 Watchdog timer WDCS 2 Start up Generation of reset Shift to sleep mode Shift to timebase timer mode Count clock selector Counter clear control circuit Shift to watch mode Shift to stop mode 2-bit counter Clear Watchdog reset generation circuit To internal reset generation circuit 4 4 (Timebase timer counter) Main clock (2 division of HCLK) × 21 × 22 ⋅⋅⋅ × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218 (Watch counter) Sub clock SCLK* × 21 × 22 ⋅⋅⋅ × 25 × 26 × 27 × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 HCLK : Oscillation clock SCLK : Sub clock * : SCLK is 2 division or 4 division of the clock inputted to the low-speed oscillation pin (X0A and X1A) or internal CR oscillation clock. The division ratio is set by the SCDS bit of the PLL/subclock control register (PSCCR). (See "CHAPTER 5 CLOCKS".) 199 CHAPTER 12 WATCHDOG TIMER ● Count clock selector The count clock selector selects a count clock input to the watchdog timer from the timebase timer or watch timer. Each timer output has four time intervals that can be set. ● Watchdog timer counter (2-bit counter) The watchdog timer counter is a 2-bit counter that uses the timebase timer output or watch timer output as a count clock. The clock source output destination is set by the watchdog clock select bit in the watch timer control register (WTC: WDCS). ● Watchdog reset generator The watchdog reset generation circuit generates a reset signal when the watchdog timer overflows (carrying). ● Counter clear circuit The counter clear circuit clears the watchdog timer counter. ● Watchdog timer control register (WDTC) The watchdog timer control register starts and clears the watchdog timer, sets the interval time, and holds reset factors. 200 CHAPTER 12 WATCHDOG TIMER 12.3 Watchdog Timer Registers This section explains the registers used for setting the watchdog timer. ■ List of Registers and Reset Values of Watchdog Timer Figure 12.3-1 List of Registers and Reset Values of Watchdog Timer bit Watchdog timer control register (WDTC) Address 0000A8H 7 6 5 4 3 2 1 0 1 1 1 : Undefined 201 CHAPTER 12 WATCHDOG TIMER 12.3.1 Watchdog timer control register (WDTC) The watchdog timer control register starts and clears the watchdog timer, sets the interval time, and holds reset factors. ■ Watchdog Timer Control Register (WDTC) Figure 12.3-2 Watchdog Timer Control Register (WDTC) 7 Address PONR 0000A8H R 6 5 4 3 2 1 0 Reset value WRST ERST SRST WTE WT1 R R R W W WT0 XXXXX111B W bit1 bit0 WT1 WT0 Interval time select bit (timebase timer output select) Interval time Clock cycle Min Max approx. 4.61 ms 214 ± 211/HCLK 216 ± 213/HCLK 0 0 approx. 3.58 ms 0 1 approx. 14.33 ms approx. 18.3 ms 1 0 approx. 57.23 ms approx. 73.73 ms 218 ± 215/HCLK 1 1 approx. 458.75 ms approx. 589.82 ms 221 ± 218/HCLK HCLK: Oscillation clock The parenthesized values are interval time when the oscillation clock operates at HCLK 4 MHz. bit1 bit0 WT1 WT0 Interval time select bit (watch timer output select) Interval time Min Clock cycle Max 0 0 approx. 0.457 s approx. 0.576 s 212 ± 29/SCLK 0 1 approx. 3.584 s approx. 4.608 s 215 ± 212/SCLK 1 0 approx. 7.168 s approx. 9.216 s 216 ± 213/SCLK 1 1 approx. 14.336 s approx. 18.432 s 217 ± 214/SCLK SCLK: Sub clock*2 The parenthesized values are interval time when the oscillation clock bit2 WTE 0 Watchdog timer control bit First programming after reset: Twice or more programming after reset : Start up the watchdog timer Clear the watchdog timer 1 No effect bit7 bit5 bit4 bit3 Reset factor bit Reset factor PONR WRST ERST SRST R : Read only W : Write only X : Undefined 1 X X X Power-on reset *1 1 *1 *1 Watchdog reset *1 *1 1 *1 External reset (Low level input to RST pin) 1 1 1 1 Software reset (write "1" to RST bit) * * * *1 : The previous state is held. *2 : However, SCLK is 2 division or 4 division of the clock inputted to the low-speed oscillation pin (X0A and X1A) or internal CR oscillation clock. The division ratio is set by the SCDS bit of the PLL/subclock control register (PSCCR). (See "CHAPTER 5 CLOCKS".) See Table 12.1-1 for the interval time. 202 CHAPTER 12 WATCHDOG TIMER Table 12.3-1 Functions of the Watching Timer Control Register (WDTC) Bit name Function bit0 bit1 WT1, WT0: Interval time select bits These bits set the interval time of the watchdog timer. The time interval when the watch timer is used as the clock source to the watchdog timer (watchdog clock select bit WDCS= 0) is different from when the main clock mode or the PLL clock mode is selected as the clock mode and the WDCS bit in the watch timer control register (WTC) is set to "1" as shown in Figure 12.3-2 according to the settings of the WTC register. In the subclock mode, be sure to set the watchdog clock select bit (WDCS) in the watch timer control register (WTC) to "0" and select the output of the watch timer. • Data after the watchdog timer is started is valid only. • Write data after the watchdog timer is started is ignored. • These are write-only bits. bit2 WTE: Watchdog timer control bit This bit starts or clears the watchdog timer. When set to "0" (first time after reset): The watchdog timer is started. When set to "0" (second or subsequent): The watchdog timer is cleared. bit6 Undefined bit Read: The value is undefined. Write: No effect bit3 to bit5, bit7 PONR, WRST, ERST, SRST: Reset factor bits These bits indicate reset factors. • When a reset occurs, the bit corresponding to the reset factor is set to "1". After a reset, the reset factor can be checked by reading the watchdog timer control register (WDTC). • These bits are cleared after the watchdog timer control register (WDTC) is read. Note: No bit value other than the PONR bit after poweron reset is assured. If the PONR bit is set at read, other bit values should be ignored. 203 CHAPTER 12 WATCHDOG TIMER 12.4 Explanation of Operations of Watchdog Timer Functions After starting, when the watchdog timer reaches the set interval time without the counter being cleared, a watchdog reset occurs. ■ Operations of Watchdog Timer The operation of the watchdog timer requires the settings shown in Figure 12.4-1 . Figure 12.4-1 Setting of Watchdog Timer bit7 Watchdog timer control register (WDTC) ❍ : Used bit 5 4 3 2 1 bit0 WRST ERST SRST WTE WT1 WT0 PONR bit7 Watch timer control register (WTC) 6 6 5 4 3 0 ❍ ❍ 2 1 bit0 WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0 ❍ 0 : Set to "0". ● Selecting clock input source • The timebase timer or watch timer can be selected as the clock input source of the count clock to the watchdog timer. When the watchdog clock select bit (WTC: WDCS) is set to "1", the timebase timer is selected. When the bit is set to 0, the watch timer is selected. After a reset, the bit returns to "1". • During operation in the sub clock mode, set the WDCS bit to 0 to select the watch timer. ● Setting interval time • Set the interval time select bits (WDTS: WT1, WT0) to select the interval time for the watchdog timer. • Set the interval time concurrently when starting the watchdog timer. Writing to the bit is ignored after the watchdog timer is started. ● Activating watchdog timer When "0" is written to the watchdog timer control bit (WDTC: WTE) after a reset, the watchdog timer is started and starts incrementing. 204 CHAPTER 12 WATCHDOG TIMER ● Clearing watchdog timer • When "0" is written once again to the watchdog timer control bit (WDTC: WTE) within the interval time after starting the watchdog timer, the watchdog timer is cleared. If the watchdog timer is not cleared within the interval time, it overflows and the CPU is reset. • A reset, or transitions to the standby modes (sleep mode, stop mode, watch mode, timebase timer mode) clear the watchdog timer. • During operation in the timebase timer mode or watch mode, the watchdog timer counter is cleared. However, the watchdog timer remains in the activation state. • Figure 12.4-2 shows relationship between clear timing and interval time of watchdog timer. The interval time varies with the timing of clearing the watchdog timer. 205 CHAPTER 12 WATCHDOG TIMER ● Checking reset factors The reset factor bits in the watchdog timer control register (WDTC: PONR, WRST, ERST, SRST) can be read after a reset to check the reset factors. Reference: For details on the reset factor bit, see "CHAPTER 7 RESETS". Figure 12.4-2 Relationship between Clear Timing and Interval Time of Watchdog Timer [Watchdog timer block diagram] 2-bit counter Clock selector 2-division circuit a b 2-division circuit c Reset circuit d Reset signal Count enable and clear WTE bit Count enable output circuit [Minimum interval time] When clear WTE bit immediately before rising of count clock. Count start Counter clear Count clock a 2-division’s value b 2-division’s value c Count enable Reset signal d WTE bit clear 7 × (Count clock cycle/2) Watchdog reset generation [Maximum interval time] When clear WTE bit immediately after rising of count clock. Count start Counter clear Count clock a 2-division’s value b 2-division’s value c Count enable Reset signal WTE bit clear 206 9 × (Count clock cycle/2) Watchdog reset generation CHAPTER 12 WATCHDOG TIMER 12.5 Precautions when Using Watchdog Timer Take the following precautions when using the watchdog timer. ■ Precautions when Using Watchdog Timer ● Stopping watchdog timer The watchdog timer is stopped by all the reset sources. ● Interval time • The interval time uses the carry signal of the timebase timer or watch timer as a count clock. If the timebase timer or watch timer is cleared, the interval time of the watchdog timer may become long. Note that the timebase timer is cleared when "0" is written to the timebase timer counter clear bit (TBR) in the timebase timer control register (TBTC) and when the clock mode changes from the main clock to PLL clock, from the subclock to main clock, or from the subclock to PLL clock. • Set the interval time concurrently when starting the watchdog timer. Setting the time interval except starting the watchdog timer is ignored. ● Precautions when creating program When clearing the watchdog timer repeatedly in the main loop, set a shorter processing time for the main loop, including interrupt processing, than the interval time of watchdog timer. ● Precautions in subclock mode In the subclock mode, be sure to set the watchdog clock select bit (WDCS) in the watch timer control register (WTC) to "0" and select the output of the watch timer. 207 CHAPTER 12 WATCHDOG TIMER 12.6 Program Examples of Watchdog Timer Program example of watchdog timer is given below: ■ Program Examples of Watchdog Timer ● Processing specification • The watchdog timer is cleared each time in the loop of the main program. • The main program must be executed once within the minimum interval time of the watchdog timer. ● Coding example WDTC EQU 0000A8H ;Watchdog timer control register WTE EQU WDTC:2 ;Watchdog control bit ; ;---------Main program------------------------------------CODE CSEG START: ;Stack pointer (SP), already ;initialized MOV I:WDTC,#00000011B ;Start up of watchdog timer ;Select interval time 221+218 ;cycle LOOP: CLRB I:WTE ;Clear watchdog timer ÅE User processing ÅE BRA LOOP ;---------Vector setting-----------------------------------------VECT VECT CSEG ABS=0FFH ORG 00FFDCH DSL START DB 00H ENDS END 208 START ;Reset vector setting ;Setting to single chip mode CHAPTER 13 16-Bit I/O TIMER This chapter explains the function and operation of the 16- bit I/O timer. 13.1 Overview of 16-bit I/O Timer 13.2 Block Diagram of 16-bit I/O Timer 13.3 Configuration of 16-bit I/O Timer 13.4 Interrupts of 16-bit I/O Timer 13.5 Explanation of Operation of 16-bit Free-run Timer 13.6 Explanation of Operation of Input Capture 13.7 Precautions when Using 16-bit I/O Timer 13.8 Program Example of 16-bit I/O Timer 209 CHAPTER 13 16-Bit I/O TIMER 13.1 Overview of 16-bit I/O Timer The 16-bit I/O timer consists of one 16-bit free-run timer and 4 input capture. The timer can be performed the measurement of input pulse and external clock cycle based on the 16-bit free-run timer. ■ Module Configuration of 16-bit I/O Timer The 16-bit I/O timer consists of the following modules: • 16-bit free-run timer × 1 unit 16-bit free-run timer 0 (channel 0) • Input capture × 4 units Input capture unit 0: capture 16-bit free-run timer 0 - Input capture 0 (channel 0) - Input capture 1 (channel 1) - Input capture 2 (channel 2) - Input capture 3 (channel 3) ■ Functions of 16-bit I/O Timer ● Functions of 16-bit free-run timer The 16-bit free-run timer consists of a 16-bit up counter, a prescaler, and a control register. The count value of the 16-bit free-run timer can be use as the base time for the input capture. • One of eight types of the count clock cycle can be set. • An overflow in the counter generates an interrupt request. • The counter of the 16-bit free-run timer is cleared to "0000H" by reset or timer clear (TCCSL:CLR=1). ● Functions of input capture The input capture consists of four 16-bit capture registers and control registers corresponding to the external input pin, and the edge detection circuit. When the trigger edge is inputted to the external input pin, the counter value of the 16-bit free-run timer is retained and the interrupt request is generated at the same time. • The capture interrupt can be generated independently by each channel. • The EI2OS can be started. • Trigger edge can be selected from rising edge, falling edge, or both edges. • Because each channel operates independently, up to 4 input measurement is performed. • When the input signal is set to the LIN-UART, the baud rate measurement at LIN slave operation is executed. 210 CHAPTER 13 16-Bit I/O TIMER 13.2 Block Diagram of 16-bit I/O Timer The 16-bit I/O timer consists of the following modules: • 16-bit free-run timer • Input capture ■ Block Diagram of 16-bit I/O Timer Figure 13.2-1 Block Diagram of 16-bit I/O Timer Internal data bus Input capture Dedicated bus 16-bit free-run timer ● 16-bit free-run timer The count value of the 16-bit free-run timer can be used as the base time for the input capture. ● Input capture When the trigger edge is inputted to the external input pin, or when the trigger edge for the LIN slave baud rate measurement from the LIN-UART is inputted, the counter value of the 16-bit free-run timer is retained and the interrupt request is generated at the same time. 211 CHAPTER 13 16-Bit I/O TIMER ■ Details of Pins and Interrupt Number Table 13.2-1 shows the pins used by the 16-bit details of interrupt. Table 13.2-1 Details of Pins and Interrupt Number Channel Special terminal Pin name Input capture ch0 (using 16-bit free-run timer ch0) IN0 P24/IN0 Input capture ch1 (using 16-bit free-run timer ch0) IN1 P25/IN1 Input capture ch2 (using 16-bit free-run timer ch0) IN2 P26/IN2 Input capture ch3 (using 16-bit free-run timer ch0) IN3 P27/IN3 16-bit free-run timer ch0 (overflow interrupt) FRCK0 P44/FRCK0 Interrupt No. For I2OS #33 (21H) ❍ 212 #30 (1EH) ✕ CHAPTER 13 16-Bit I/O TIMER 13.2.1 Block Diagram of 16-bit Free-run Timer The MB90360 series contains 1 channel of the 16-bit free-run timer, and it consists of the following block. ■ Block Diagram of 16-bit Free-run Timer Figure 13.2-2 Block Diagram of 16-bit Free-run Timer Timer data register (TCDT0) OF Output count value to input capture 16-bit counter CLK STOP CLR External clock (FRCK0) Prescaler 3 Timer control status register (Lower) (TCCSL0) IVF IVFE STOP Reserved CLR CLK2 CLK1 CLK0 Internal data bus φ Free-run timer overflow interrupt request Timer control status register (Upper) (TCCSH0) ECKE φ : Machine clock OF : Overflow ● Prescaler The prescaler divides the frequency of the machine clock to supply a count clock to the 16-bit counter. Any of eight count clock cycles can be selected by setting the timer control status register (TCCSL: CLK2 to CLK0). ● Timer data register (TCDT) The timer data register can read the counter value of the 16-bit free-run timer. During stopping of the 16-bit free-run timer, the counter value can be set by writing the counter value to the TCDT. ● Timer control status register (TCCSH, TCCSL) The timer control status register (upper and lower) selects the count clock and the condition for clearing the counter, clears the counter, enables the count operation and interrupt request, checks the overflow generation flag. 213 CHAPTER 13 16-Bit I/O TIMER 13.2.2 Block Diagram of Input Capture The input capture consist of the following blocks: ■ Block Diagram of Input Capture Figure 13.2-3 Block Diagram of Input Capture Unit 0 16-bit free-run timer Edge detection circuit IN3 Pin Input capture data register 3 (IPCP3) IN2 Pin Input capture data register 2 (IPCP2) Input capture edge register (ICE23) IEI3 IEI2 2 2 ICP3 ICP2 ICE3 ICE2 EG31 EG30 EG21 EG20 Input capture interrupt request Input capture control status register (ICS01) ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00 2 2 Input capture edge register (ICE01) ICUS1 ICUS0 IEI1 IEI0 IN1 Pin Input capture data register 1 (IPCP1) LIN-UART1 IN0 Pin Input capture data register 0 (IPCP0) LIN-UART0 Edge detection circuit 214 Internal data bus Input capture control status register (ICS23) CHAPTER 13 16-Bit I/O TIMER ● Input capture data registers 0 to 3 (IPCP0 to IPCP3) • Input capture data register retains the counter value of the 16-bit free-run timer fetched by the capture operation. • Input capture data register 0 to 3 keep the counter value of the 16-bit free-run timer 0 ● Input capture control status registers 01 to 23 (ICS01 to ICS23) • Input capture control status register selects the trigger edge, enables the capture operation and capture interrupt request, and checks the valid edge detection flag for each input capture. • Input capture control status register has 2 registers, and the input capture operation of the corresponding channel is controlled as shown in Table 13.2-2 . ● Input capture edge registers 01 to 23 (ICS01 to ICS23) • Input capture control status register indicated the edge polarity detected by each input capture. Also, it selects the input signal (external pin INx/LIN-UART). When input is set to the LIN-UART, the baud rate measurement at the LIN slave operation can be performed (See "20.7.3 Operation with LIN Function (Operation Mode 3)"). • Input capture edge register has 2 registers, and the input capture operation of the corresponding channel is controlled as shown in Table 13.2-2 . Table 13.2-2 Relationship between the Register and Pin of Input Capture Input capture unit 0 Input capture control status register Input capture edge register Input capture data register Input pin Input form LIN-UART ICS01 ICE01 IPCP0 IN0 UART0 IPCP1 IN1 UART1 IPCP2 IN2 - IPCP3 IN3 - ICS23 ICE23 ● Edge detection circuit The edge detection circuit detects the edge of the signal input to the external input pin. The detected edge can be selected from among the rising edge, falling edge, both edges, and no detection (capture stop). 215 CHAPTER 13 16-Bit I/O TIMER 13.3 Configuration of 16-bit I/O Timer This section explains the pins, registers, and interrupt factors of the 16-bit I/O timer. ■ Pins of 16-bit I/O Timer The pins of the 16-bit I/O timer serve as general-purpose I/O ports. Table 13.3-1 shows the pin functions and the pin settings required to use the 16-bit I/O timer. Table 13.3-1 Pins of 16-bit I/O Timer Channel Pin Name Pin Function Setting to use the pin P44/ FRCK0 General-purpose I/O port, Set as input port in port direction register (DDR). Input capture 0 P24/IN0 Input capture 1 P25/IN1 General-purpose I/O port, capture input Input capture 2 P26/IN2 Set as input port in port direction register (DDR). Input capture 3 P27/IN3 Set as input port in port direction register (DDR). 16-bit free-run timer 0 external clock input Set as input port in port direction register (DDR). Set as input port in port direction register (DDR). ■ Generation of Interrupt Request from 16-bit I/O Timer The 16-bit I/O timer can generate an interrupt request as a result of the following factors: ● Timer counter overflow interrupt If the overflow interrupt request is set to enable (TCCSL: IVFE=1), the interrupt is occurred by the following factor: • 16-bit free-run timer overflow ● Input capture interrupt If the input capture interrupt request is set to enable (ICS: ICE=1), if the trigger edge is detected by the input capture pin, or if the trigger edge for the LIN slave baud rate measurement from the LIN-UART is inputted, the interrupt request is generated. 216 CHAPTER 13 16-Bit I/O TIMER 13.3.1 Timer Control Status Register (Upper) (TCCSH) Timer control status register (upper) selects the count clock and the conditions for clearing the counter, enables the count operation and interrupt, and checks the interrupt request flag. ■ Timer Control Status Register (Upper) (TCCSH) Figure 13.3-1 Timer Control Status Register (Upper) (TCCSH) 15 Address 14 13 TCCSH0 : 007943H ECKE 12 11 10 9 8 Reset value 0XXXXXXXB R/W bit15 ECKE External clock input enable bit 0 Use the internal clock (prescaler output). 1 Use the external clock (FRCK0 pin input). R/W : Read/Write : Undefined X : Indetermination : Reset value Table 13.3-2 Function of Timer Control Status Register (Upper) (TCCSH) Bit name Function bit15 ECKE : External clock input enable bit This bit selects the count clock of the 16-bit free-run timer. When set to "1": Use the clock inputted from the external pin FRCK0. When set to "0": Use the internal clock (clock outputted from the prescaler). Note: Set the ECKE bit during stopping of the free-run timer (TCCSL:STOP=1). bit14 Undefined bits Read: The value is undefined Write: No effect to bit8 217 CHAPTER 13 16-Bit I/O TIMER 13.3.2 Timer Control Status Register (Lower) (TCCSL) The timer control status register (Lower) selects the count clock and conditions for clearing the counter, clears the counter, enables the count operation or interrupt, and checks the interrupt request flag. ■ Timer Control Status Register (Lower) (TCCSL) Figure 13.3-2 Timer Control Status Register (Lower) (TCCSL) 6 7 5 Address TCCSL0:007942H IVF IVFE STOP 4 3 2 1 0 Reset value Reserved CLR CLK2 CLK1 CLK0 00000000 B R/W R/W R/W R/W R/W R/W R/W R/W bit2 bit1 bit0 CLK2 CLK1 CLK0 Count clock cycle selection bits 0 0 0 1/φ 0 0 1 2/φ 0 1 0 4/φ 0 1 1 8/φ 1 0 0 16/φ 1 0 1 32/φ 1 1 0 64/φ 1 1 1 128/φ φ: Machine clock frequency bit3 CLR Timer clear bit 0 No effect 1 Clear counter (TCDT = "0000H") bit4 Reserved bit Reserved 0 Be sure to set to "0". bit5 STOP Timer operation stop bit 0 Timer operating enabled 1 Timer operating disabled (stop) bit6 IVFE Timer overflow interrupt enable bit 0 Timer overflow interrupt disabled 1 Timer overflow interrupt enabled bit7 IVF R/W 218 Timer overflow generating flag bit Read Write : Read/Write 0 Without timer overflow Clear this bit : Reset value 1 With timer overflow No effect CHAPTER 13 16-Bit I/O TIMER Table 13.3-3 Functions of Timer Control Status Register (Lower) (TCCSL) Bit name Function bit7 IVF: Timer overflow generation flag bit This bit indicates the timer overflow. [Condition set to "1"] Condition is set when the following is used. • When 16-bit free-run timer overflows [When set to "1"] When the timer overflow interrupt request is set to enable (TCCSL:IVFE=1) if the IVF bit is set to "1", the interrupt request is generated. When set to "0": The bit is cleared. When set to "1": No effect. Read by read modify write instructions: "1" is always read. bit6 IVFE: Timer overflow interrupt enable bit This bit enables or disables the interrupt request when the IVF bit is set to "1". When set to "1": When the IVF bit is set to "1", the interrupt request is generated. When set to "0": The generation of the interrupt request is disabled. bit5 STOP: Timer operation stop bit This bit enables or disables (stops) the operation of the 16-bit free-run timer. When set to "0": Enable the timer operation and count up with count clock set by the CLK2 to CLK0. When set to "1":Stops count operation bit4 Reserved bit Always set this bit to "0". bit3 CLR: Timer clear bit This bit clears the counter (TCDT) of the 16-bit free-run timer. When set to "1": Clears timer data register (TCDT) to "0000H" When set to "0": No effect. Read: "0" is always read. Note: When clearing during stopping of the 16-bit free-run timer (TCCSL:STOP=1), write "0000H" to the TCDT directly. bit2 bit1 bit0 CLK2, CLK1, CLK0: Count clock cycle selection bits These bits set the count clock to cycle of the 16-bit free-run timer. Note: Set the count clock cycle during stopping of the input capture operation (ICSnm: EGn1, EGn0="00B" or ICSnm:EGm1, EGm0="00B"). n=0, 2 m=n+1 219 CHAPTER 13 16-Bit I/O TIMER 13.3.3 Timer Data Register (TCDT) The timer data register is a 16-bit up counter. • The counter value of the 16-bit free-run timer is read. • The counter value can be set during stopping of the 16-bit free-run timer. ■ Timer Data Register (TCDT) Figure 13.3-3 Timer Data Register (TCDT) Address TCDT0 upper: 007941H bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 Tn15 Tn14 Tn13 Tn12 Tn11 Tn10 Tn9 Tn8 Reset value 00000000B R/W R/W R/W R/W R/W R/W R/W R/W TCDT0 lower: 007940H bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Tn7 Tn6 Tn5 Tn4 Tn3 Tn2 Tn1 Tn0 Reset value 00000000B R/W R/W R/W R/W R/W R/W R/W R/W R/W: Read/Write n=0 The TCDT register can read the counter value of the 16-bit free-run timer. [Condition for clear the counter value] The counter value is cleared to "0000H" by the following conditions. • Overflow • Setting of "1" to the timer clear bit of the timer control status register (TCCSL:CLR=1) • Setting of "0000H" to the timer data register during stopping of 16-bit free-run timer • Reset [Setting of counter value] Write the counter value to the timer data register (TCDT) and set the timer during stopping the timer operation (TCCSL:STOP=1). Note: Always use a word instruction (MOVW) to read/write the timer data register. 220 CHAPTER 13 16-Bit I/O TIMER 13.3.4 Input Capture Control Status Registers (ICS) The function of the input capture control status register is shown below. The correspondence between ICS01 to ICS23 and input pin is as follows. • ICS01: IN0, IN1 input capture ch0, ch1 • ICS23: IN2, IN3 input capture ch2, ch3 ■ Input Capture Control Status Registers (ICS01, ICS23) Figure 13.3-4 Input Capture Control Status Registers (ICS) Address ICS01 : 000050H ICS23 : 000052H 7 6 5 4 3 2 1 0 Reset value ICPm ICPn ICEm ICEn EGm1 EGm0 EGn1 EGn0 R/W R/W R/W R/W R/W R/W R/W R/W 00000000 bit1 EGn1 0 0 1 1 bit0 EGn0 0 1 0 1 B Edge select bit n Without edge detection (operation stop state) Detect rising edge Detect falling edge Detect both edges bit3 bit2 EGm1 EGm0 Edge select bit m 0 0 Without edge detection(operation stop state) 0 1 Detect rising edge 1 0 Detect falling edge 1 1 Detect both edges bit4 ICEn 0 1 Capture interrupt enable bit n Input capture 0 interrupt disable Input capture 0 interrupt enable bit5 ICEm Capture interrupt enable bit m 0 Input capture 1 interrupt disable 1 Input capture 1 interrupt enable bit6 ICPn 0 1 Valid edge detection flag bit n Read Write Input capture 0 without Clear of ICP0 bit valid edge detection Input capture 0 with valid No effect edge detection bit7 ICPm 0 R/W : Read/Write 1 Valid edge detection flag bit m Read Write Input capture 1 without Clear of ICP1 bit valid edge detection Input capture 1 with valid No effect edge detection : Reset value n = 0, 2 m=n+1 221 CHAPTER 13 16-Bit I/O TIMER Table 13.3-4 Functions of Input Capture Control Status Register (ICS) Bit name Function bit7 ICPm: Valid edge detection flag bit m This bit is set to "1" when the valid edge is detected by the INm pin. When the interrupt request of the input capture m is set to enable (ICSnm:ICEm=1), if the ICPm bit is set, the interrupt request is generated. When set to "0": The bit is cleared. When set to "1": No effect. bit6 ICPn: Valid edge detection flag bit n This bit is set to "1" when the valid edge is detected by the INn pin. When the interrupt request of the input capture m is set to enable (ICSnm:ICEn=1), if the ICPn bit is set, the interrupt request is generated. When set to "0": The bit is cleared. When set to "1": No effect. bit5 ICEm: Capture interrupt enable bit m This bit enables or disables the interrupt request of the input capture m. When set to "1": When the valid edge detection flag bit m is set to "1" (ICSnm: ICPm=1), the interrupt request is generated. bit4 ICEn: Capture interrupt enable bit n This bit enables or disables the interrupt request of the input capture n. When set to "1": When the valid edge detection flag bit n is set to "1" (ICSnm: ICPn=1), the interrupt request is generated. bit3 bit2 EGm1, EGm0: Edge select bits m For the input capture register m, the trigger edge of the capture operation is set. • Setting of the trigger edge is used to specify enable and stop of the operation. When set to "00B": The operation of input capture is disabled and no edge is detected. bit1 bit0 EGn1, EGn0: Edge select bits n For the input capture register n, the trigger edge of the capture operation is set. • Setting of the trigger edge is used to specify enable and stop of the operation. When set to "00B": The operation of input capture is disabled and no edge is detected. n = 0, 2 m = n + 1 222 CHAPTER 13 16-Bit I/O TIMER 13.3.5 Input Capture Register (IPCP) Input capture register stores the counter value fetched from 16-bit free-run timer by the capture operation. The IPCP register is the 16-bit read-only register and has the input capture registers 0 to 3 (IPCP0 to IPCP3). ■ Input Capture Register (IPCP) Figure 13.3-5 Input Capture Register (IPCP) Address IPCP0 (upper): 007921H bit15 bit14 bit13 bit12 bit11 bit10 bit9 CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08 R R bit7 R bit6 R bit5 R bit4 R bit3 R bit2 XXXXXXXX B R bit1 bit0 IPCP0 (lower): 007920H CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00 XXXXXXXX B R R R R R R R R bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 IPCP1 (upper): 007923H CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08 R R bit7 R bit6 R bit5 R bit4 R bit3 R bit2 XXXXXXXX B R bit1 bit0 IPCP1 (lower): 007922H CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00 XXXXXXXX B R R R R R R R R bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 IPCP2 (upper): 007925H CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08 R R bit7 R bit6 R bit5 R bit4 R bit3 R bit2 XXXXXXXX B R bit1 bit0 IPCP2 (lower): 007924H CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00 XXXXXXXX B R R R R R R R R bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 IPCP3 (upper): 007927H CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08 R R bit7 IPCP3 (lower): 007926H R X Reset value bit8 : Read only : Undefined R bit6 R bit5 R bit4 R bit3 R bit2 XXXXXXXX B R bit1 bit0 CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00 XXXXXXXX B R R R R R R R R When the trigger edge of the capture operation (ICSnm: set by EGn1, EGn0 or EGm1, EGm0) is detected by the IN0 to IN3 pins, the counter value of the 16-bit free-run timer is stored in the input capture registers 0 to 3 corresponding to each pin. However, the input capture registers 0 and 1 can be selected a signal from the LIN-UART as the input signal (ICE: selected by IEI bit). See "13.3.6 Input Capture Edge Register (ICE)" for details. The input capture register can be read, but can not be written. n =0,2 m = n+1 Note: Always use a word instruction (MOVW) to read the input capture register. 223 CHAPTER 13 16-Bit I/O TIMER 13.3.6 Input Capture Edge Register (ICE) The input capture edge register has a function to indicate the selected edge direction and to select whether the input signal is inputted from either external pin or LIN-UART. By cooperating with the LIN-UART, the baud rate measurement at the LIN slave operation can be performed. The correspondence between ICE01 to ICE23 / channel name and input pin (UART) name is shown as follows. ICE01: input capture ch0, ch1 IN0(/UART0) IN1(/UART1) ICE23: input capture ch2, ch3 IN2 IN3 ■ Input Capture Edge Register (ICE) Figure 13.3-6 Input Capture Edge Register (ICE) bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 Reset value ICUS1 ICUS0 IEI1 IEI0 R/W R/W XXX0X0XXB bit10 ICUS0 Input signal selection bit 0 0 Input signal of external pin IN0 1 Signal from UART0 ICE01 : 000051H R R bit12 ICUS1 Input signal selection bit 1 0 Input signal of external pin IN1 1 Signal from UART1 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 IEI3 IEI2 R R ICE23 : 000053H Reset value XXXXXXXXB bit8 IEIn 0 1 R/W : Read/Write : Read only R : Indeterminate : Undefined X : Reset value n = 0, 2 m = n+1 224 Detection edge indication bit n Detect falling edge Detect rising edge bit9 IEIm 0 1 Detection edge indication bit m Detect falling edge Detect rising edge CHAPTER 13 16-Bit I/O TIMER Table 13.3-5 Functions of Input Capture Edge Register 01 (ICE01) Bit name bit15 Function Undefined bits Read : The value is undefined. Write: No effect. bit12 ICUS1: Input signal selection bit 1 This bit selects the input signal used as the trigger of the input capture 1. When set to "0": Select the external pin IN1. When set to "1": Select the IN-UART1. bit11 Undefined bit Read : The value is undefined. Write: No effect. bit10 ICUS0: Input signal selection bit 0 This bit selects the input signal used as the trigger of the input capture 0. When set to "0": Select the external pin IN0. When set to "1": Select the IN-UART0. bit9 IEI1: Detection edge indication bit 1 This bit indicated the edge detected by the input capture 1 (rising/falling). This bit is read only. "0": Indicate that falling edge is detected. "1": Indicate that rising edge is detected. Note: This bit value is disabled when the capture operation is stopped (ICS01 : EG11, EG10="00"). bit8 IEI0: Detection edge indication bit 0 This bit indicated the edge detected by the input capture 0 (rising/falling). This bit is read only. "0": Indicate that falling edge is detected. "1": Indicate that rising edge is detected. Note: This bit value is disabled when the capture operation is stopped (ICS01 : EG01, EG00="00"). to bit13 225 CHAPTER 13 16-Bit I/O TIMER Table 13.3-6 Functions of Input Capture Edge Register 23 (ICE23) Bit name bit15 Function Undefined bits Read : The value is undefined. Write: No effect. bit9 IEI3: Detection edge indication bit 3 This bit indicates the edges detected by the input capture 3 (rising/falling). This bit is read only. "0": Indicate that falling edge is detected. "1": Indicate that rising edge is detected. Note: This bit value is disabled when the capture operation is stopped (ICSnm : EGm1, EGm0="00"). (n=2, m=n+1) bit8 IEI2 : Detection edge indication bit 2 This bit indicates the edges detected by the input capture 2 (rising/falling). This bit is read only. "0": Indicate that falling edge is detected. "1": Indicate that rising edge is detected. Note: This bit value is disabled when the capture operation is stopped (ICS23 : EG21, EG20="00"). to bit10 Note: In the input capture 0 and 1, if the input signal is selected to the LIN-UART (ICE01:ICUS), the input capture is used to calculate the baud rate when the LIN-UART operates the LIN slave. In this case, it must be set to the input capture interrupt enable (ICS01:ICE0=1 or ICE1=1) and to the detection of both edges (ICS01:EG01, EG00=11B or EG11, EG10=11B). See "20.7.3 Operation with LIN Function (Operation Mode 3)" for details of the baud rate calculation. 226 CHAPTER 13 16-Bit I/O TIMER 13.4 Interrupts of 16-bit I/O Timer The interrupt factors of the 16-bit I/O timer has overflow of the counter value in the 16bit free-run timer, trigger edge input to the input capture input pin, and trigger edge input for the LIN slave baud rate measurement from the LIN-UART. The EI2OS can be started by the interrupt of the input capture. ■ Interrupts of 16-bit I/O Timer Table 13.4-1 shows interrupt control bits and interrupt factors of 16-bit I/O timer. Table 13.4-1 Interrupts of 16-bit I/O Timer Timer counter overflow interrupt Input capture interrupt Interrupt request flag TCCSL: IVF ICSnm: ICPn, ICPm Interrupt request output enable bit TCCSL: IVFE ICSnm: ICEn, ICEm Counter overflow of 16-bit free-run timer Valid edge input to the input capture input pin and trigger edge input for the LIN slave baud rate measurement from the LIN-UART Interrupt factor n = 0, 2 m = n+1 ● Timer counter overflow interrupt When the timer overflow interrupt request is set: The timer overflow generation flag of the timer control status register is set in the following cases (TCCSL:IVF=1). • When overflow ("FFFFH" → "0000H") occurs at counting up of the 16-bit free-run timer. When the timer overflow interrupt request occurs: When the timer overflow interrupt request is set to enable (TCCSL:IVFE=1) if the timer overflow generation flag is set to "1" (TCCSL:IVF=1), the interrupt request is generated. ● Input capture Interrupt When the valid edge set by the input capture pin (ICS:EG) is detected, or when the trigger edge for the LIN slave baud rate measurement from the LIN-UART is inputted (valid edge must be set to both edges), the interrupt is shown below. • The counter value of the detected 16-bit free-run timer is stored to the input capture register. • The valid edge detection flag of the input capture control status register is set to "1". (ICS: ICP=1) • When the output of the input capture interrupt request is set to enable (ICS: ICE=1), the interrupt request is generated. 227 CHAPTER 13 16-Bit I/O TIMER ■ 16-bit I/O Timer Interrupt and EI2OS Reference: ■ For details of the interrupt number, interrupt control register, and interrupt vector address, see "CHAPTER 3 INTERRUPTS". Correspondence to EI2OS Function The input capture corresponds to the EI2OS function. However, to use the EI2OS function, it is necessary to disable other interrupt that shares the interrupt control register (ICR). 228 CHAPTER 13 16-Bit I/O TIMER 13.5 Explanation of Operation of 16-bit Free-run Timer After a reset, the 16-bit free-run timer starts incrementing from "0000H". The counter value of the 16-bit free-run timer is the base time of the input capture. ■ Explanation of Operation of 16-bit Free-run Timer Operation of the 16-bit free-run timer requires the setting shown in Figure 13.5-1 . Figure 13.5-1 Setting of 16-bit Free-run Timer bit15 14 TCCSH/TCCSL ECKE ❍ 13 12 11 10 9 bit8 bit7 − − − − − − − ✕ ✕ ✕ ✕ ✕ ✕ ✕ TCDT 6 5 4 IVF IVFE STOP − ❍ 0 0 0 3 2 1 bit0 CLR CLK2 CLK1 CLK0 ❍ ❍ ❍ ❍ Counter value of 16-bit free-run timer ❍ : Used bit ✕ : Undefined bit 0 : Setting to "0" [Setting of counter value in 16-bit free-run timer] • Because the timer operation is enabled (TCCSL:STOP=0) after a reset, the 16-bit free-run timer starts incrementing from the counter value "0000H". • When setting the counter value of the 16-bit free-run timer, disable the operation of the 16-bit free-run timer (TCCSL:STOP=1), set the value that starts counting to the timer data register, enable the timer operation (TCCSL:STOP=0). [Generation of overflow and interrupt request] • When overflow ("FFFFH" → "0000H") occurs in the 16-bit free-run timer, the timer overflow generation flag is set to "1" (TCCSL:IVF) and starts incrementing from "0000H". • When the timer overflow interrupt request is enabled (TCCSL:IVFE=1), the interrupt request is occurred. [Clear factor of counter value and clear timing] Table 13.5-1 shows the clear factor and clear timing of the 16-bit free-run timer. Table 13.5-1 Clear Factor of Counter Value and Clear Timing Clear factor Clear timing When "1" to timer clear bit of timer control status register (TCCSL: CLR) Synchronize with generation of factor Write "0000H" to timer data register during stopping Synchronize with generation of factor Reset Synchronize with generation of factor Timer overflow Synchronize with count timing 229 CHAPTER 13 16-Bit I/O TIMER Figure 13.5-2 shows counter clearing at an overflow. Figure 13.5-2 Counter Clearing at an Overflow Counter value Overflow FFFFH BFFF H 7FFFH 3FFFH 0000H Reset 230 Time CHAPTER 13 16-Bit I/O TIMER 13.6 Explanation of Operation of Input Capture The input capture stores the counter value of the 16-bit free-run timer to the input capture register at the timing that is detected the input signal of the valid edge from the external input pin or that the trigger edge for the LIN slave baud rate measurement is inputted, the interrupt request is generated. ■ Setting of Input Capture Operation of the input capture requires the setting shown in Figure 13.6-1 Figure 13.6-1 Setting of Input Capture bit15 14 13 12 11 10 9 bit8 bit7 6 5 4 3 2 1 bit0 IEIm IEIn ICPm ICPn ICEm ICEn EGm1 EGm0 EGn1 EGn0 ICE/ICS ✕ ✕ ✕ ▲ ▲ ▲ ❍ ❍ ❍ ❍ ❍ ❍ ❍ ❍ ❍ ❍ Hold counter value of input capture IPCP DDR port direction register Setting the corresponding bit using pin as capture input pin to "0". ❍: Using bit (Set the bit corresponding to used channel) ▲: Using bit (Exist only ICE01’s bit, Set the bit at measurement LIN slave baud rate n = 0, 2 m = n + 1 [Input capture operation] The following operation is executed when the set valid edge (ICS:EG) is detected in the input capture pin, or when the trigger edge for the LIN slave baud rate measurement from the LIN-UART is inputted. • The counter value of the 16-bit free-run timer to time detected is stored in the input capture register. • The detected edge direction is stored to the detection edge indication bit. (rising:IEI=1, falling:IEI=0) • The valid edge detection flag of the input capture control status register is set to "1". (ICS:ICP=1) • When the input capture interrupt request is enabled (ICS:ICE=1), the interrupt request is generated. • To measure the baud rate at the LIN slave operation, it is necessary to set the input signal to the LINUART (ICE:ICUS), enable the input capture interrupt request (ICS:ICE=1), and set the valid edge to both edges (ICE:EG1, EG0=11B). See "20.7.3 Operation with LIN Function (Operation Mode 3)" for the calculation of the baud rate. Figure 13.6-2 shows the timing of fetching a data for the input capture. Figure 13.6-3 shows the operation when valid edge is set to the rising edge/falling edge. Figure 13.6-4 shows the operation when valid edge is set to both edges. 231 CHAPTER 13 16-Bit I/O TIMER Figure 13.6-2 Timing of Fetching Data for Input Capture φ Counter value N N+1 Input capture input Valid edge Capture signal Capture register N+1 Data fetch φ: Machine clock Figure 13.6-3 Operation of Input Capture (Rising edge/falling edge) Counter value FFFFH BFFFH 7FFFH 3FFFH Time 0000H Reset INn (rising edge) INm (falling edge) Capture n Undefined Capture m Undefined 3FFFH 7FFFH n = 0, 2 m = n+1 Figure 13.6-4 Operation of Input Capture (both edges) Counter value FFFFH BFFFH Time 7FFFH 3FFFH 0000H Reset INn (both edge) Capture example Undefined BFFFH 3FFFH n = 0 to 3 232 CHAPTER 13 16-Bit I/O TIMER 13.7 Precautions when Using 16-bit I/O Timer This section explains the precautions when using the 16-bit I/O timer. ■ Precautions when Using 16-bit I/O Timer ● Precautions when setting 16-bit free-run timer • Do not change the count clock select bits (TCCSL: CLK2, CLK1, CLK0) during the operation in the 16bit free-run timer (TCCSL: STOP = 0). • The counter value of the 16-bit free-run timer is cleared to "0000H" by reset. • Stop the 16-bit free-run timer (TCCSL:STOP=1), then write the counter value to the timer data register (TCDT) directly. • Always use a word instruction to write the timer data register (TCDT). ● Operation delay by synchronization operation The input capture generates delay of operation time because it synchronizes with the operation clock. After the input capture detects the trigger signal from the pin, it synchronizes with the machine clock and performs the capture operation. 233 CHAPTER 13 16-Bit I/O TIMER 13.8 Program Example of 16-bit I/O Timer This section gives a program example of the 16-bit I/O timer. ■ Program Example of 16-bit I/O Timer ● Processing specification • The cycle of a signal input to the IN0 pin is measured. • The 16-bit free-run timer 0 and input capture 0 are used. • The rising edge is selected as the trigger to be detected. • The machine clock (φ) is 24 MHz and the count clock of the free-run timer is 4/φ (0.17 µs). • The timer overflow interrupt and input capture interrupt of input capture 0 are used. • The overflow interrupt of the 16-bit free-run timer is counted beforehand and used for the cycle calculation. • The cycle can be determined from the following equation: Cycle = (overflow count × "10000H" + nth IPCP0 value - (n-1)th IPCP0 value) × count clock cycle = (overflow count × 10000H + nth IPCP0 value - (n-1)th IPCP0 value) × 0.17 µs ● Coding example ICR09 ICR11 DDR2 TCCSL TCDT ICS01 IPCP0 IVF0 ICP0 DATA EQU 0000B9H ;Interrupt control register EQU 0000BBH ;Interrupt control register EQU 000012H ;Port 2 direction register EQU 007942H ;Timer control status register EQU 007940H ;Timer data register EQU 000050H ;Input capture control status register EQU 007920H ;Input capture register 0 EQU TCCSL:7 ;Timer overflow generation flag bit EQU ICS01:6 ;Valid edge detection flag bit DSEG ABS=00H ORG 0100H OV_CNT RW 1H DATA ENDS ;Overflow count counter ; ;---------Main program------------------------------------------CODE CSEG START: ; ;Stack pointer (SP), ;already initialized AND CCR,#0BFH ;Interrupt disable MOV I:ICR09,#00H ;Interrupt level 0(strongest) MOV I:ICR11,#00H ;Interrupt level 0(strongest) MOV I:DDR2,#00000000B ;Port 2 direction setting MOV I:TCCSL,#01001010B ;Count enable, Counter clear, ;Overflow, Interrupt enable, ;Count clock selection, Counter clear 234 CHAPTER 13 16-Bit I/O TIMER MOV MOV OR I:ICS01,#00010001B ;IN0 pin selection, External trigger, ;IPCP0 rising edge ;Without IPCP1 edge detection ;Clear each valid edge detection flag ;Input capture interrupt request enable ILM,#07H ;Set ILM in PS to level 7 CCR,#40H ;Interrupt enable LOOP: : User processing : BRA LOOP ;---------Interrupt program--------------------------------------------WARI0: CLRB I:ICP0 ;Clear valid edge detection flag : ;Save OV-CNT and input capture value User processing : MOV A,0 ;Clear overflow count counter MOV OV_CNT,A ;for next cycle measurement RETI ;Recover from interrupt WARI1: CLRB I:IVF0 ;Clear timer overflow generation flag INC OV_CNT ;Increment overflow counter : User processing : RETI ;Recover from interrupt CODE ENDS ;---------Vector setting-----------------------------------------------VECT CSEG ABS=0FFH ORG 00FF78H ;Setting vector to interrupt number #33(21H) ;(Input capture) VECT DSL ORG WARI0 00FF84H DSL ORG DSL DB ENDS END WARI1 00FFDCH START 00H ;Setting vector to interrupt number #30(1EH) ;(Overflow) ;Reset vector setting ;Setting to single-chip mode START 235 CHAPTER 13 16-Bit I/O TIMER 236 CHAPTER 14 16-BIT RELOAD TIMER This chapter describes the functions and operation of the 16-bit reload timer. 14.1 Overview of the 16-bit Reload Timer 14.2 Block Diagram of 16-bit Reload Timer 14.3 Configuration of 16-bit Reload Timer 14.4 Interrupts of 16-bit Reload Timer 14.5 Explanation of Operation of 16-bit Reload Timer 14.6 Precautions when Using 16-bit Reload Timer 14.7 Sample Program of 16-bit Reload Timer 237 CHAPTER 14 16-BIT RELOAD TIMER 14.1 Overview of the 16-bit Reload Timer The 16-bit reload timer has the following functions: • The count clock can be selected from three internal clocks and external event clocks. • A software trigger or external trigger can be selected as the start trigger. • If the 16-bit timer register (TMR) underflows, an interrupt can be generated to the CPU. The 16-bit reload timer can be used as an interval timer by using an interrupt. • If the TMR underflows, either the one-shot mode for stopping the TMR count operation, or the reload mode for reloading the value of the 16-bit reload register (TMRLR) to the TMR to continue the TMR count operation can be selected. • The 16-bit reload timer corresponds to the EI2OS (correspond to 2 channels). • The MB90360 series has two channels of 16-bit reload timers. ■ Operation Modes of 16-bit Reload Timer Table 14.1-1 indicates the operation modes of the 16-bit reload timer. Table 14.1-1 Operation Modes of 16-bit Reload Timer Count clock Start trigger Operation performed upon underflow Internal clock mode Software trigger External trigger One-shot mode Reload mode Event count mode Software trigger One-shot mode Reload mode ■ Internal Clock Mode • When the count clock select bits in the timer control status register (TMCSR:CSL1, CSL0) are set to "00B", "01B" or "10B", the 16-bit reload timer is set in the internal clock mode. • In the internal clock mode, the 16-bit reload timer decrements in synchronization with the internal clock. • The count clock select bits in the timer control status register (TMCSR:CSL1, CSL0) can be used to select three count clock cycles. • The start trigger sets the edge detection for a software trigger or an external trigger. ■ Event Count Mode • When the count clock select bits in the timer control status register (TMCSR:CSL1, CSL0) are set to "11B", the 16-bit reload timer is set to the event count mode. • In the event count mode, the 16-bit reload timer decrements in synchronization with the edge detection of the external event clock input to the TIN pin. • A software trigger is selected as the start trigger. • The 16-bit reload timer can be used as an interval timer by using a fixed cycle of the external clock. 238 CHAPTER 14 16-BIT RELOAD TIMER ■ Operation at Underflow When the start trigger is inputted, the value set in the 16-bit reload register (TMRLR) is reloaded to the 16bit timer register, starting decrementing in synchronization with the count clock. When the 16-bit timer register (TMR) is decremented from "0000H" to "FFFFH", an underflow occurs. • When an underflow occurs with an underflow interrupt enabled (TMCSR:INTE = 1), an underflow interrupt is generated. • The 16-bit reload timer operation when an underflow occurs is set by the reload select bit in the timer control status register (TMCSR:RELD). [One-shot mode (TMCSR: RELD=0)] When an underflow occurs, the TMR count operation is stopped. When the next start trigger is inputted, the value set in the TMRLR is reloaded in the TMR, starting the TMR count operation. • In the one-shot mode, during the TMR count operation, a High-level or Low-level rectangular wave is outputted from the TOT pin. • The pin output level select bit in the timer control status register (TMCSR:OUTL) can be set to select the level (High or Low) of the rectangular wave. [Reload mode (TMCSR: RELD=1)] When an underflow occurs, the value set in the TMRLR is reloaded to the TMR, continuing the TMR count operation. • In the reload mode, a toggle wave inverting the output level of the TOT pin is outputted each time an underflow occurs during the TMR count operation. • The pin output level select bit in the timer control status register (TMCSR:OUTL) can be set to select the level (High or Low) of a toggle wave at starting the reload timer. • The 16-bit reload timer can be used as an interval timer by using an underflow interrupt. Table 14.1-2 Interval Time for the 16-bit Reload Timer Count clock Internal clock mode Event count mode Count clock period Interval time 21T(0.083 µs) 0.083 µs to 5.46 ms 23T(0.33 µs) 0.33 µs to 21.8 ms 25T(1.3 µs) 1.3 µs to 87.4 ms 23T or more 0.33 µs or more T: Machine cycle The values in interval time and the parenthesized values are provided when the machine clock operates at 24 MHz. 239 CHAPTER 14 16-BIT RELOAD TIMER 14.2 Block Diagram of 16-bit Reload Timer The 16-bit reload timers 2 and 3 composed of the following seven blocks: • Count clock generator • Reload controller • Output controller • Operation controller • 16-bit timer register (TMR) • 16-bit reload register (TMRLR) • Timer control status register (TMCSR) ■ Block Diagram of 16-bit Reload Timer Figure 14.2-1 Block Diagram of 16-bit Reload Timer Internal data bus TMRLR 16-bit reload register Reload signal TMR 16-bit timer register Counter clock generating circuit Machine clock Prescaler 3 Reload control circuit UF CLK Gate input Valid clock judgement circuit φ Wait signal Clear Internal clock Input control circuit Pin TIN Output control circuit CLK Clock selector Output signal generating circuit Pin TOT EN External clock 3 2 Select signal Operating control circuit Function selection − − − − CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE UF CNTE TRG Timer control status register (TMCSR) 240 Interrupt request output CHAPTER 14 16-BIT RELOAD TIMER ● Details of pins in block diagram There are two channels for 16-bit reload timer. The actual pin names, outputs to resources, and interrupt request numbers for each channel are as follows: Table 14.2-1 Pin Names, Outputs to Resources, and Interrupt Request Numbers of 16-bit Reload Timer Reload timer 2 Reload timer 3 TIN pin P82 P53 TOT pin P83 P54 - - #19(13H) #20(14H) Output to resources Interrupt request number ● Count clock generator The count clock generator generates a count clock supplied to the 16-bit timer register (TMR) on the basis of the machine clock or external event clock. ● Reload controller When the 16-bit reload timer starts operation or the TMR underflows, the reload controller reloads the value set in the 16-bit reload register (TMRLR) to the TMR. ● Output controller The output controller inverts and enables or disables the output of the TOT pin at underflow. ● Operation controller The operation controller starts or stops the 16-bit reload timer. ● 16-bit timer register (TMR) The 16-bit timer register (TMR) is a 16-bit down counter. At read, the value being counted is read. ● 16-bit reload register (TMRLR) The 16-bit reload register (TMRLR) sets the interval time of the 16-bit reload timer. When the 16-bit reload timer starts operation or the 16-bit timer register (TMR) underflows, the value set in the TMRLR is reloaded to the TMR. ● Timer control status register (TMCSR) The timer control status register (TMCSR) selects the operation mode, sets the operation conditions, selects the start trigger, performs a start using the software trigger, selects the reload operation mode, enables or disables an interrupt request, sets the output level of the TOT pin, and sets the TOT output pin of the 16-bit reload timer. 241 CHAPTER 14 16-BIT RELOAD TIMER 14.3 Configuration of 16-bit Reload Timer This section explains the pins, registers, and interrupt factors of the 16-bit reload timer. ■ Pins of 16-bit Reload Timer The pins of the 16-bit reload timer serve as general-purpose I/O ports. Table 14.3-1 shows the pin functions and the pin settings required to use the 16-bit reload timer. Table 14.3-1 Pins of 16-bit Reload Timer Pin name Pin function Pin Setting Required for Use in 16-bit Reload Timer P82 / SIN0 / INT14R / TIN2 General-purpose I/O port/ UART input 0/ External interrupt 14/ 16-bit reload timer input 2 • Port direction register: Setting for the input port (DDR8:D82=0) • Serial control register: Setting for the reception disable (SCR0:RXE=0) • Disable the external interrupt (external interrupt enable register ENIR1: EN14 = 0) P83 / SOT0 / TOT2 General-purpose I/O port/ UART output 0/ 16-bit reload timer output 2 • Serial control register P53 / AN11 / TIN3 General-purpose I/O port/ A/D converter analog input 11/ 16-bit reload timer input 3 • Port direction register P54 / AN12 / TOT3 General-purpose I/O port/ A/D converter analog input 12/ 16-bit reload timer output 3 • Analog input enable register: Setting for the prohibition (ADER5:ADE12=0) • Timer control status register: Enable the timer output (TMCSR3: OUTE=1) 242 : Setting for the transmission disable (SCR0:TXE=0) • Timer control status register: Enable the timer output (TMCSR2: OUTE=1) : Setting for the input port (DDR5:D53=0) • Analog input enable register: Setting for the prohibition (ADER5:ADE11=0) CHAPTER 14 16-BIT RELOAD TIMER ■ 16-bit Reload Timer Registers and Reset Value ● 16-bit reload timer 2 register Figure 14.3-1 List of 16-bit Reload Timer 2 Register and Reset Value bit Timer Control Status Register Upper (TMCSR2) bit Timer Control Status Register Lower (TMCSR2) bit 16-bit Timer Register Upper (TMR2) bit 16-bit Timer Register Lower (TMR2) bit 16-bit Reload Register Upper (TMRLR2) bit 16-bit Reload Register Lower (TMRLR2) 15 14 13 12 11 10 9 8 X X X X 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 X X X X X X X X 7 6 5 4 3 2 1 0 X X X X X X X X 15 14 13 12 11 10 9 8 X X X X X X X X 7 6 5 4 3 2 1 0 X X X X X X X X X : Undefined ● 16-bit reload timer 3 register Figure 14.3-2 List of 16-bit Reload Timer 3 Register and Reset Value bit Timer Control Status Register Upper (TMCSR3) bit Timer Control Status Register Lower (TMCSR3) bit 16-bit Timer Register Upper (TMR3) bit 16-bit Timer Register Lower (TMR3) bit 16-bit Reload Register Upper (TMRLR3) bit 16-bit Reload Register Lower (TMRLR3) 15 14 13 12 11 10 9 8 X X X X 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 X X X X X X X X 7 6 5 4 3 2 1 0 X X X X X X X X 15 14 13 12 11 10 9 8 X X X X X X X X 7 6 5 4 3 2 1 0 X X X X X X X X X : Undefined 243 CHAPTER 14 16-BIT RELOAD TIMER ■ Generation of Interrupt Request from 16-bit Reload Timer When the 16-bit reload timer is started and the count value of the 16-bit timer register is decremented from "0000H" to "FFFFH", an underflow occurs. When an underflow occurs, the UF bit in the timer control status register is set to 1 (TMCSR:UF). If an underflow interrupt is enabled (TMCSR:INTE = 1), an interrupt request is generated. 244 CHAPTER 14 16-BIT RELOAD TIMER 14.3.1 Timer Control Status Registers (High) (TMCSR:H) The timer control status registers (High) (TMCSR:H) set the operation mode and count clock. This section also explains the bit 7 in the timer control status registers (Low) (TMCSR:L). ■ Timer Control Status Registers (High) (TMCSR:H) Figure 14.3-3 Timer Control Status Registers (High) (TMCSR:H) Address: 15 14 13 12 TMCSR2 : 000065H TMCSR3 : 000067H 11 10 9 8 7 CSL1 CSL0 MOD2MOD1MOD0 − − − − Reset value XXXX0000 B R/W R/W R/W R/W R/W bit9 bit8 bit7 MOD2 MOD1 MOD0 0 0 0 0 0 1 0 1 0 0 1 1 1 X 0 1 X 1 bit9 bit8 bit7 MOD2 MOD1 MOD0 X 0 0 X 0 1 X 1 0 X 1 1 bit11 bit10 CSL1 CSL0 0 0 0 1 1 0 1 1 Operating mode select bit (internal clock mode) (CSL1, 0="00B", "01B", "10B") Input pin function Valid edge, level − Trigger disable Rising edge Trigger input Falling edge Both edges "L" level Gate input "H" level Operating mode select bit (event count mode) (CSL1, 0="11B") Input pin function R/W : Read/Write X ; Indeterminate − : Undefined Valid edge − − Rising edge Trigger input Falling edge Both edges Count clock select bit Count clock Count clock cycle 21T Internal clock mode 23T 25T Event count mode External event clock T: Machine cycle : Reset value 245 CHAPTER 14 16-BIT RELOAD TIMER Table 14.3-2 Functions of Timer Control Status Registers (High) (TMCSR: H) Bit name 246 Function bit15 to bit12 Undefined bits Read: The value is undefined. Write: No effect bit11 bit10 CSL1, CSL0: Count clock select bits These bits select the count clock of the 16-bit reload timer. When set to anything other than "11B": These bit is counted by internal clock (internal clock mode). When set to "11B": The edge of the external event clock is counted (event count mode). bit9 to bit7 MOD2, MOD1, MOD0: Operating mode select bits These bits set the operation conditions of the 16-bit reload timer. [Internal clock mode] The MOD2 bit is used to select the function of the input pin. When MOD2 bit set to 0: The input pin functions as a trigger input. The MOD1 and MOD0 bits are used to select the edge to be detected. When the edge is detected, the value set in the 16-bit reload register (TMRLR) is reloaded in the 16-bit timer register (TMR), starting the count operation of the TMR. When MOD2 set to 1: The input pin functions as a gate input. The MOD1 bit is not used. The MOD0 bit is used to select the signal level (High or Low) to be detected. The count operation of the 16-bit timer register (TMR) is performed only when the signal level is inputted. [Event count mode] The MOD2 bit is not used. An external event clock is inputted from the input pin. The MOD1 and MOD0 bits are used to select the edge to be detected. CHAPTER 14 16-BIT RELOAD TIMER 14.3.2 Timer Control Status Registers (Low) (TMCSR: L) The timer control status registers (Low) (TMCSR:L) enables or disable the timer operation, check the generation of a software trigger or an underflow, enables or disable an underflow interrupt, select the reload mode, and set the output of the TOT pin. ■ Timer Control Status Registers (Low) (TMCSR: L) Figure 14.3-4 Timer Control Status Registers (Low) (TMCSR: L) Address: 7 TMCSR2 : 000064H TMCSR3 : 000066H ∗ 6 5 4 3 2 1 0 OUTE OUTL RELD INTE UF CNTE TRG Reset value 00000000B R/W R/W R/W R/W R/W R/W R/W bit0 TRG Software trigger bit 0 No effect 1 After reloading, starts counting bit1 CNTE Timer operation enable bit 0 Timer operation disabled 1 Timer operation enabled (wait start trigger) bit2 UF Underflow generating flag bit Read Write 0 No underflow Clear UF bit 1 Underflow No effect bit3 INTE Underflow interrupt enable bit 0 Underflow interrupt disable 1 Underflow interrupt enable bit4 RELD Reload select bit 0 One-shot mode 1 Reload mode bit5 OUTL TOT pin output level select bit One-shot mode (RELD=0) Reload mode (RELD=1) 0 High rectangular wave output during counting Low toggle output at starting reload timer 1 Low rectangular wave output during counting High toggle output at starting reload timer bit6 OUTE R/W : Read/Write TOT pin output enable bit Pin function 0 General-purpose I/O port 1 TOT output : Reset value ∗ : For MOD0 (bit 7), see "14.3.1 Timer Control Status Registers (High) (TMCSR:H)". 247 CHAPTER 14 16-BIT RELOAD TIMER Table 14.3-3 Timer Control Status Registers (Low) (TMCSR: L) Bit Name 248 Function bit6 OUTE: TOT pin Output enable bit This bit sets the function of the TOT pin of the 16-bit reload timer. When set to 0: Functions as general-purpose I/O port When set to 1: Functions as TOT pin of 16-bit reload timer bit5 OUTL: TOT Pin output level select bit This bit sets the output level of the output pin of the 16-bit reload timer. <One-shot mode (RELD = 0)> When set to 0: Outputs High-level rectangular wave during TMR count operation When set to 1: Outputs Low-level rectangular wave during TMR count operation <Reload mode (RELD = 1)> When set to 0: Outputs Low-level toggle wave when 16-bit reload timer started When set to 1: Outputs High-level toggle wave when 16-bit reload timer started bit4 RELD: Reload select bit This bit sets the reload operation at underflow. When set to 1: At underflow, reloads value set in TMRLR to TMR, continuing count operation (reload mode) When set to 0: At underflow, stops count operation (one-shot mode) bit3 INTE: Underflow interrupt enable bit This bit enables or disables an underflow interrupt. When an underflow occurs (TMCSR:UF = 1) with an underflow interrupt enabled (TMCSR:INTE = 1), an interrupt request is generated. bit2 UF: Underflow generating flag bit This bit indicates that the TMR underflows. When set to 0: Clears this bit When set to 1: No effect Read by read modify write instructions: 1 is always read. bit1 CNTE: Timer operation enable bit This bit enables or disables the operation of the 16-bit reload timer. When set to 1: 16-bit reload timer enters start trigger wait state. When the start trigger is inputted, the count operation of the TMR is restarted. When set to 0: Stops count operation bit0 TRG: Software trigger bit This bit starts the 16-bit reload timer by software. The software trigger function works only when the timer operation is enabled (CNTE = 1). When set to 0: Disabled. The state remains unchanged. When set to 1: Reloads value set in 16-bit reload register (TMRLR) to 16-bit timer register (TMR), starting TMR count operation Read: 0 is always read. CHAPTER 14 16-BIT RELOAD TIMER 14.3.3 16-bit Timer Registers (TMR) The 16-bit timer registers are 16-bit down counters. At read, the value being counted is read. ■ 16-bit Timer Registers (TMR) Figure 14.3-5 16-bit Timer Registers (TMR) Address: TMR2 : 00794DH TMR3 : 00794FH 15 14 D15 D14 R Address: TMR2 : 00794CH TMR3 : 00794EH R : Read only X : Undefined 13 12 D13 D12 D11 D10 R R 11 R 10 R 9 8 D9 D8 R R R Reset value XXXXXXXX B 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 R R R R R R R R Reset value XXXXXXXX B When the timer operation is enabled (TMCSR:CNTE = 1) and the start trigger is inputted, the value set in the 16-bit reload register (TMRLR) is reloaded to the 16-bit timer register (TMR), starting the TMR count operation. When the timer operation is disabled (TMCSR:CNTE = 0), the TMR value is retained. When the TMR value is counted down from "0000H" to "FFFFH" during the TMR count operation, an underflow occurs. [Reload mode] When the TMR underflows, the value set in the TMRLR is reloaded to the TMR, restarting the TMR count operation. [One-shot mode] When the TMR underflows, the TMR count operation is stopped, entering the start trigger input wait state. The TMR value is retained to "FFFFH". Notes: • The TMR can be read during the TMR count operation. However, always use the word instruction (MOVW). • The TMR and the TMRLR are assigned to the same address. At write, the set value can be written to the TMRLR without affecting the TMR. At read, the TMR value being counted can be read. 249 CHAPTER 14 16-BIT RELOAD TIMER 14.3.4 16-bit Reload Registers (TMRLR) The 16-bit reload registers set the value to be reloaded to the 16-bit timer register (TMR). When the start trigger is inputted, the value set in the 16-bit reload registers is reloaded to the TMR, starting the TMR count operation. ■ 16-bit Reload Registers (TMRLR) Figure 14.3-6 16-bit Reload Registers (TMRLR) Address: 15 TMRLR2 : 00794DH TMRLR3 : 00794FH D15 D14 14 W Address: TMRLR2 : 00794CH TMRLR3 : 00794EH W : Write only X : Undefined 13 12 D13 D12 D11 D10 W W 11 W 10 W W 9 8 Reset value D9 D8 XXXXXXXX B W W 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 W W W W W W W W Reset value XXXXXXXX B Set the 16-bit reload registers after disabling the timer operation (TMCSR:CNTE = 0). After completing setting of the 16-bit reload registers, enable the timer operation (TMCSR:CNTE = 1). When the start trigger is inputted, the value set in the TMRLR is reloaded to the TMR, starting the TMR count operation. Notes: • Perform a write to the TMRLR after disabling the operation of the 16-bit reload timer (TMCSR:CNTE = 0). Always use the word instruction (MOVW). • The TMRLR and the TMR are assigned to the same address. At write, the set value can be written to the TMRLR without affecting the TMR. At read, the TMR value being counted is read. • Instructions, such as the INC/DEC instruction, which provide the read modify write (RMW) operation cannot be used. 250 CHAPTER 14 16-BIT RELOAD TIMER 14.4 Interrupts of 16-bit Reload Timer The 16-bit reload timer generates an interrupt request when the 16-bit timer register (TMR) underflows. ■ Interrupts of 16-bit Reload Timer When the value of the TMR is decremented from "0000H" to "FFFFH" during the TMR count operation, an underflow occurs. When an underflow occurs, the underflow generating flag bit in the timer control status register (TMCSR:UF) is set to l. When an underflow interrupt is enabled (TMCSR:INTE = 1), an interrupt request is generated. Table 14.4-1 Interrupt Control Bits and Interrupt Factors of 16-bit Reload Timer 16-bit Reload Timer 2 16-bit Reload Timer 3 Interrupt request flag bit TMCSR2: UF TMCSR3: UF Interrupt request enable bit TMCSR2: INTE TMCSR3: INTE Interrupt factor Underflow in TMR2 Underflow in TMR3 ■ Correspondence between 16-bit Reload Timer Interrupt and EI2OS Reference: For details of the interrupt number, interrupt control register, and interrupt vector address, see "CHAPTER 3 INTERRUPTS". ■ EI2OS Function of 16-bit Reload Timer The 16-bit reload timers 2 and 3 correspond to the EI2OS function. An underflow in the TMR starts the EI2OS. However, the EI2OS is available only when other resources sharing the interrupt control register (ICR) do not use interrupts. The 16-bit reload timers 2 and 3 share the ICR04. When using the EI2OS in the 16-bit reload timers 2 and 3, it is necessary to disable the interrupt of the 16-bit reload timer sharing the interrupt control register. 251 CHAPTER 14 16-BIT RELOAD TIMER 14.5 Explanation of Operation of 16-bit Reload Timer This section explains the setting of the 16-bit reload timer and the operation state of the counter. ■ Setting of 16-bit Reload Timer ● Setting of internal clock mode Counting the internal clock requires the setting shown in Figure 14.5-1 . Figure 14.5-1 Setting of Internal Clock Mode bit15 14 TMCSR − − 13 12 − − 11 10 9 8 7 6 5 4 3 2 1 bit0 CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE UF CNTE TRG 1 Other than "11B" Set the reload value to 16-bit timer register TMRLR : Used bit 1 : Set "1". ● Setting of event count mode Inputting an external event to operate the 16-bit reload timer requires the setting shown in Figure 14.5-2 . Figure 14.5-2 Setting of Event Count Mode TMCSR bit15 14 13 12 − − − − 11 9 8 7 6 5 4 3 2 1 bit0 CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE UF CNTE TRG 1 TMRLR 10 1 ❍ ❍ ❍ ❍ ❍ ❍ ❍ ❍ 1 Set the reload value to 16-bit timer register Set the bit of DDR (port direction register) corresponding to the pin to be used as TIN pin to "0". ❍: Used bit 1 : Set "1". 252 ❍ CHAPTER 14 16-BIT RELOAD TIMER ■ Operating State of 16-bit Timer Register The operating state of the 16-bit timer register is determined by the timer operation enable bit in the timer control status register (TMCSR:CNTE) and the WAIT signal. The operating states include the stop state, start trigger input wait state (WAIT state), and RUN state. Figure 14.5-3 shows the state transition diagram for the 16-bit timer registers. Figure 14.5-3 State Transition Diagram STOP state CNTE=0, WAIT=1 TIN pin: Input disable TOUT pin: General-purpose I/O port Reset 16-bit timer register:retain the value at stop the value immediately after resetting is undefined CNTE=0 CNTE=0 CNTE=1 TRG=0 WAIT state CNTE=1, WAIT=1 TIN pin: only trigger input is valid TOUT pin: outputs value of 16-bit reload register CNTE=1 TRG=1 RUN state CNTE=1, WAIT=0 TIN pin:function as input pin of 16-bit reload timer UF=1& RELD=0 16-bit timer register:retains the value at stop (one-shot mode) the value immediately after resetting is undefined UF=1& RELD=1 TOUT pin:function as output pin of 16-bit reload timer 16-bit timer register: operation (reload mode) TRG=1 (software trigger) External trigger from TIN TRG=1 LOAD CNTE=1, WAIT=0 Loads 16-bit reload register value to 16-bit timer register (software trigger) Load ended : State transition by hardware WAIT TRG CNTE UF RELD : State transition by register access : WAIT signal (internal signal) : Software trigger bit (TMCSR) : Timer operation enable bit (TMCSR) : Underflow generating flag bit (TMCSR) : Reload select bit (TMCSR) 253 CHAPTER 14 16-BIT RELOAD TIMER 14.5.1 Operation in Internal Clock Mode In the internal clock mode, three operation modes can be selected by setting the operating mode select bits in the timer control status register (TMCSR:MOD2 to MOD0).When the operation mode and reload mode are set, a rectangular wave or a toggle wave is outputted from the TOT pin. ■ Setting of Internal Clock Mode • By setting the count clock select bits (CSL1, CSL0) in the timer control status register to "00B", "01B" and "10B", the 16-bit reload timer (TMRLR) is set to the internal clock mode. • In the internal clock mode, the 16-bit timer register (TMR) decrements in synchronization with the internal clock. • In the internal clock mode, three count clock cycles can be selected by setting the count clock select bits in the timer control status register (TMCSR:CSL1, CSL0). [Setting a reload value to TMR] After the 16-bit reload timer is started, the value set in the TMRLR is reloaded to the TMR. 1. Disables the timer operation (TMCSR:CNTE = 0). 2. Sets a reload value to the TMR in the TMRLR. 3. Enables the timer operation (TMCSR:CNTE = 1). Note: It takes 1 T (T: machine cycle (time) to load the value set in the TMRLR to the TMR after the start trigger is inputted. 254 CHAPTER 14 16-BIT RELOAD TIMER ■ Operation as 16-bit Timer Register Underflows When the value of the 16-bit timer register (TMR) is decremented from "0000H" to "FFFFH" during the TMR count operation, an underflow occurs. • When an underflow occurs, the underflow generating flag bit in the timer control status register (TMCSR:UF) is set to 1. • When the underflow interrupt enable bit in the timer control status register (TMCSR:INTE) is set to 1, an underflow interrupt is generated. • The reload operation when an underflow occurs is set by the reload select bit in the timer control status register (TMCSR:RELD). [One-shot mode (TMCSR:RELD = 0)] When an underflow occurs, the count operation of the TMR is stopped, entering the start trigger input wait state. When the next start trigger is inputted, the TMR count operation is restarted. In the one-shot mode, a rectangular wave is outputted from the TOT pin during the TMR count operation. The pin output level select bit in the timer control status register (TMCSR:OUTL) can be set to select the level (High or Low) of a rectangular wave. [Reload mode (TMCSR:RELD = 1)] When an underflow occurs, the value set in the 16-bit reload timer register (TMRLR) is reloaded to the TMR, continuing the TMR count operation. In the reload mode, a toggle wave inverting the output level of the TOT pin is outputted each time an underflow occurs during the TMR count operation. The pin output level select bit in the timer control status register (TMCSR:OUTL) can be set to select the level (High or Low) of a toggle wave as the 16-bit reload timer is started. ■ Operation in Internal Clock Mode In the internal clock mode, the operation mode select bits in the timer control status register (TMCSR:MOD2 to MOD0) can be used to select the operation mode. Disable the timer operation by setting the timer operation enable bit in the timer control status register (TMCSR:CNTE to 0). [Software trigger mode (MOD2 to MOD0="000B")] If the software trigger mode is set, start the 16-bit reload timer by setting the software trigger bit in the timer control status register (TMCSR:TRG) to 1. When the 16-bit reload timer is started, the value set in the TMRLR is reloaded to the TMR, starting the TMR count operation. Note: When both the timer operation enable bit in the timer control status register (TMCSR:CNTE) and the software trigger bit in the timer control status register (TMCSR:TRG) are set to 1, the 16-bit reload timer and the count operation of the TMR are started simultaneously. 255 CHAPTER 14 16-BIT RELOAD TIMER Figure 14.5-4 Count Operation in Software Trigger Mode (One-shot Mode) Counter clock Counter Reload data -1 0000H FFFFH Reload data -1 0000H FFFFH Data load signal UF bit CNTE bit TRG bit T* TOT pin Start trigger input wait T: Machine cycle * : It takes 1 machine cycle (time) to load data of reload register from trigger input. Figure 14.5-5 Count Operation in Software Trigger Mode (Reload Mode) Count clock Counter Reload data -1 0000H Reload data -1 0000H Reload data Data load signal UF bit CNTE bit TRG bit TOT pin T* T: Machine cycle * : It takes 1 T time to load data of reload register from trigger input. 256 -1 0000H Reload data -1 CHAPTER 14 16-BIT RELOAD TIMER [External trigger mode (MOD2 to MOD0="001B", "010B", "011B")] When the external trigger mode is set, the 16-bit reload timer is started by inputting the external valid edge to the TIN pin. When the 16-bit reload timer is started, the value set in the 16-bit reload register (TMRLR) is reloaded to the 16-bit timer register (TMR), starting the TMR count operation. By setting the operating mode select bits in the timer control status register (TMCSR:MOD2 to MOD0), the detected edge can be selected from the rising edge, falling edge, and both edges. Note: The trigger pulse width of the edge to be inputted to the TIN pin should be 2 T (T: machine cycles) or more. Figure 14.5-6 Count Operation in External Trigger Mode (One-shot Mode) Counter clock Counter Reload data -1 0000H FFFFH Reload data -1 0000H FFFFH Data load signal UF bit CNTE bit TIN pin 2T to 2.5T* TOT pin Start trigger input wait T: Machine cycle * : It takes 2T to 2.5T time to load data of reload register from external trigger input. Figure 14.5-7 Count Operation in External Trigger Mode (Reload Mode) Counter clock Counter Reload data -1 0000H Reload data -1 0000H Reload data -1 0000H Reload data -1 Data load signal UF bit CNTE bit TIN pin TOT pin 2T to 2.5T* T : Machine cycle * : It takes 2T to 2.5T time to load data of reload register from external trigger input. 257 CHAPTER 14 16-BIT RELOAD TIMER [External gate input mode (MOD2 to MOD0="1x0B", "1x1B")] When the external gate input mode is set, start the 16-bit reload timer by setting the software trigger bit in the timer control status register (TMCSR:TRG) to 1. When the 16-bit reload timer is started, the value set in the 16-bit reload register (TMRLR) is reloaded to the 16-bit timer register (TMR). • After the 16-bit reload timer is started, the count operation of the TMR is performed while the set gate input level is inputted to the TIN pin. • The gate input level (High or Low) can be selected by setting the operating mode select bits in the timer control status register (TMCSR:MOD2 to MOD0). Figure 14.5-8 Count Operation in External Gate Input Mode (One-shot Mode) Counter clock Counter Reload data -1 0000H -1 FFFFH Reload data -1 -1 Data load signal UF bit CNTE bit TRG bit T* TIN pin T* TOT pin Start trigger input wait T : Machine cycle * : It takes 1 T time to load data of reload register from trigger input. Figure 14.5-9 Count Operation in External Gate Input Mode (Reload Mode) Counter clock Counter Reload data -1 -1 -1 0000H Reload data Data load signal UF bit CNTE bit TRG bit TIN pin T* TOT pin T : Machine cycle * : It takes 2T to 2.5T time to load data of reload register from trigger input. 258 -1 -1 CHAPTER 14 16-BIT RELOAD TIMER 14.5.2 Operation in Event Count Mode In the event count mode, after the 16-bit reload timer is started, the edge of the signal input to the TIN pin is detected to perform the count operation of the 16-bit timer register (TMR). When the operation mode and the reload mode are set, a rectangular wave or a toggle wave is outputted from the TOT pin. ■ Setting of Event Count Mode • The 16-bit reload timer is placed in the event count mode by setting the count clock select bits in the timer control status register (TMCSR:CSL1, CSL0) to "11B". • In the event count mode, the TMR decrements in synchronization with the edge detection of the external event clock input to the TIN pin. [Setting initial value of counter] After the 16-bit reload timer is started, the value set in the TMRLR is reloaded to the TMR. 1. Disables the operation of the 16-bit reload timer (TMCSR:CNTE = 0). 2. Sets a reload value to the TMR in the TMRLR. 3. Enables the operation of the 16-bit reload timer (TMCSR:CNTE = 1). Note: It takes 1 T (T: machine cycle) to load the value set in the TMRLR to the TMR after the start trigger is inputted. 259 CHAPTER 14 16-BIT RELOAD TIMER ■ Operation as 16-bit Timer Register Underflows When the value of the 16-bit timer register (TMR) is decremented from "0000H" to "FFFFH" during the TMR count operation, an underflow occurs. • When an underflow occurs, the underflow generating flag bit in the timer control status register (TMCSR:UF) is set to 1. • When the underflow interrupt enable bit in the timer control status register (TMCSR:INTE) is set to 1, an underflow interrupt is generated. • The reload operation when an underflow occurs is set by the reload select bit in the timer control status register (TMCSR:RELD). [One-shot mode (TMCSR: RELD=0)] When an underflow occurs, the TMR count operation is stopped, entering the start trigger input wait state. When the next start trigger is inputted, the TMR count operation is restarted. In the one-shot mode, a rectangular wave is outputted from the TOT pin during the TMR count operation. The pin output level select bit in the timer control status register (TMCSR:OUTL) can be set to select the level (High or Low) of the rectangular wave. [Reload mode (TMCSR: RELD=1)] When an underflow occurs, the value set in the TMRLR is reloaded to the TMR, continuing the TMR count operation. In the reload mode, a toggle wave inverting the output level of the TOT pin is outputted each time an underflow occurs during the TMR count operation. The pin output level select bit in the timer control status register (TMCSR:OUTL) can be set to select the level (High or Low) of the toggle wave when the 16-bit reload timer is started. 260 CHAPTER 14 16-BIT RELOAD TIMER ■ Operation in Event Count Mode The operation of the 16-bit reload timer is enabled by setting the timer operation enable bit in the timer control status register (TMCSR:CNTE) to 1. When the software trigger bit in the timer control status register (TMCSR:TRG) is set to 1, the 16-bit reload timer is started. When the 16-bit reload timer is started, the value set in the 16-bit reload register (TMRLR) is reloaded to the 16-bit timer register (TMR), starting the TMR count operation. After the 16-bit reload timer is started, the edge of the external event clock input to the TIN pin is detected to perform the TMR count operation. • By setting the operating mode select bits in the timer control status register (TMCSR:MOD2 to MOD0), the detected edge can be selected from the rising edge, falling edge, and both edges. Note: The level width of the external event clock to be inputted to the TIN pin should be 4 T (T: machine cycles) or more. Figure 14.5-10 Count Operation in Event Count Mode (One-shot Mode) TIN pin Counter Reload data -1 0000H FFFFH Reload data -1 0000H FFFFH Data load signal UF bit CNTE bit TRG bit T* TOT pin Start trigger input wait T : Machine cycle * : It takes 1 T time to load data of reload register from trigger input. Figure 14.5-11 Count Operation in Event Count Mode (Reload Mode) TIN pin Counter Reload data -1 0000H Reload data -1 0000H Reload data -1 0000H Reload data -1 Data load signal UF bit CNTE bit TRG bit TOT pin T* T : Machine cycle * : It takes 1 T time to load data of reload register from trigger input. 261 CHAPTER 14 16-BIT RELOAD TIMER 14.6 Precautions when Using 16-bit Reload Timer This section explains the precautions when using the 16-bit reload timer. ■ Precautions when Using 16-bit Reload Timer ● Precautions when setting by program • Set the 16-bit reload register (TMRLR) after disabling the timer operation (TMCSR:CNTE = 0) • The 16-bit timer register (TMR) can be read during the TMR count operation. However, always use the word instruction. • Change the CSL1 and CSL0 bits in the TMCSR after disabling the timer operation (TMCSR:CNTE = 0) ● Precautions on interrupt • When the UF bit in the TMCSR is set to 1 and the underflow interrupt output is enabled (TMCSR:INTE = 1), it is impossible to return from interrupt processing. Always clear the UF bit. However, when the EI2OS is used, the UF bit is cleared automatically. • When using the EI2OS in the 16-bit reload timer, it is necessary to disable the interrupt of the 16-bit reload timer that shares the interrupt control register (ICR). 262 CHAPTER 14 16-BIT RELOAD TIMER 14.7 Sample Program of 16-bit Reload Timer This section gives a program example of the 16-bit reload timer operated in the internal clock mode and the event count mode: ■ Program Example in Internal Clock Mode ● Processing specification • The 24 ms interval timer interrupt is generated by the 16-bit reload timer 2. • The repeated interrupts are generated in the reload mode. • The timer is started using the software trigger instead of the external trigger input. • EI2OS is not used. • The machine clock is 24 MHz; the count clock is 1.33 µs. ● Coding example ICR04 EQU 0000B4H ;Interrupt control register for 16-bit ;reload timer TMCSR2 EQU 000064H ;Timer control status register TMR2 EQU 00794CH ;16-bit timer register TMRLR2 EQU 00794CH ;16-bit reload register UF2 EQU TMCSR2:2 ;Interrupt request flag bit CNTE2 EQU TMCSR2:1 ;Counter operation enable bit TRG2 EQU TMCSR2:0 ;Software trigger bit ;--------Main program-----------------------------------CODE CSEG ; : ;Stack pointer (SP), already initialized AND CCR,#0BFH ;Interrupts disabled MOV I:ICR04,#00H ;Interrupt level 0 (highest) CLRB I:CNTE2 ;Counter suspended MOVW I:TMRLR2,#4650H ;Set data for 24 ms timer MOVW I:TMCSR2,#0000100000011011B ;Operation of interval timer, clock = 1.33 µs ;External trigger disabled, external output disabled ;Reload mode selected, interrupt enabled ;Interrupt flag cleared, count started MOV ILM,#07H ;ILM in PS set to level 7 OR CCR,#40H ;Interrupts enabled LOOP: : Processing by user : 263 CHAPTER 14 16-BIT RELOAD TIMER BRA LOOP ; ;---------Interrupt program----------------------------------WARI: CLR I:UF2 ;Interrupt request flag cleared : : Processing by user : : RETI ;Return from interrupt CODE ENDS ;---------Vector setting---------------------------------------VECT CSEG ABS=0FFH ORG 00FFB0H ;Set vector to interrupt #19(13H) VECT DSL ORG DSL DB ENDS END WARI 00FFDCH START 00H ;Reset vector set ;Set to single-chip mode START ■ Program Example in Event Counter Mode ● Processing specification • An interrupt is generated when rising edges of the pulse input to the external event input pin are counted 10000 times by the 16-bit reload timer 2. • Operation is performed in the one-shot mode. • The rising edge is selected for the external trigger input. • EI2OS is not used. ● Coding example ICR04 ;Interrupt control register for 16-bit ;reload timer TMCSR2 EQU 000064H ;Timer control status register TMR2 EQU 00794CH ;16-bit timer register TMRLR2 EQU 00794CH ;16-bit reload register DDR8 EQU 000018H ;Port data register UF2 EQU TMCSR2:2 ;Interrupt request flag bit CNTE2 EQU TMCSR2:1 ;Counter operation enable bit TRG2 EQU TMCSR2:0 ;Software trigger bit ;---------Main program----------------------------------CODE CSEG ; : ;Stack pointer (SP), already initialized ;Used at software starting mode(ACS1 : STS1, 0 = 00B) 264 EQU 0000B4H CHAPTER 14 16-BIT RELOAD TIMER AND MOV MOV CLRB MOVW MOVW MOV OR CCR,#0BFH ;Interrupts disabled I:ICR04,#00H ;Interrupt level 0 (highest) I:DDR8,00H ;Sets P82/TIN2 pin to input I:CNTE0 ;Counter suspended I:TMRLR2,#2710H;Reload value set to 10000 times I:TMCSR2,#0000110001001011B ;Counter operation, rising edge, ;and external output disabled ;One-shot mode selected, interrupt enabled ;Interrupt flag cleared, count started ILM,#07H ;Set ILM in PS to level 7 CCR,#40H ;Interrupts enabled LOOP: : Processing by user : BRA LOOP ; ;---------Interrupt program----------------------------------WARI: CLR I:UF2 ;Interrupt request flag cleared : : Processing by user : : RETI ;Return from interrupt CODE ENDS ;---------Vector setting---------------------------------------VECT CSEG ABS=0FFH ORG 00FFB0H ;Set vector to interrupt #19 (13H) VECT DSL ORG DSL DB ENDS END WARI 00FFDCH START 00H ;Reset vector set ;Set to single-chip mode START 265 CHAPTER 14 16-BIT RELOAD TIMER 266 CHAPTER 15 WATCH TIMER This chapter describes the functions and operations of the watch timer. 15.1 Overview of Watch Timer 15.2 Block Diagram of Watch Timer 15.3 Configuration of Watch Timer 15.4 Watch Timer Interrupt 15.5 Explanation of Operation of Watch Timer 15.6 Program Example of Watch Timer 267 CHAPTER 15 WATCH TIMER 15.1 Overview of Watch Timer The watch timer is a 15-bit free-run counter that increments in synchronization with the subclock. • Eight interval times can be selected and an interrupt request can be generated for each interval time. • An operation clock can be supplied to the oscillation stabilization wait time timer of the subclock and the watchdog timer. • The subclock is always used as a count clock regardless of the settings of the clock select register (CKSCR). ■ Interval Timer Function • When the watch timer reaches the interval time set by the interval time select bits (WTC:WTC2 to WTC0), the bit corresponding to the interval time of the watch timer counter overflows (carries) and the overflow flag bit is set (WTC:WTOF = 1). • When the overflow flag bit is set (WTC:WTOF = 1) with interrupt enabled when an overflow occurs (WTC:WTIE = 1), an interrupt request is generated. • The interval time of the watch timer can be selected from eight types shown in Table 15.1-1 . Table 15.1-1 Interval Times of Watch Timer Subclock Cycle Interval Time 28/SCLK(31.25 ms) 29/SCLK(62.5 ms) 210/SCLK(125 ms) SCLK(122 µs) 211/SCLK(250 ms) 212/SCLK(500 ms) 213/SCLK(1.0 s) 214/SCLK(2.0 s) 215/SCLK(4.0 s) SCLK: Subclock frequency The parenthesized values are provided when the subclock operates at 8.192 kHz. Please consider the frequency difference of built-in CR oscillation when you use built-in CR oscillation clock as a sub-clock. 268 CHAPTER 15 WATCH TIMER ■ Cycle of Clock Supply The watch timer supplies an operation clock to the oscillation stabilization wait time timer of the subclock and the watchdog timer. Table 15.1-2 shows the cycles of clocks supplied from the watch timer. Table 15.1-2 Cycle of Clock Supplied from Watch Timer Where to Supply Clock Timer for oscillation stabilization wait time of subclock Clock Cycle 214/SCLK(4.000 s) 210/SCLK(125 ms) 213/SCLK(1.000 s) Watchdog timer 214/SCLK(2.000 s) 215/SCLK(4.000 s) SCLK: Subclock frequency The parenthesized values are provided when the subclock operates at 8.192 kHz. Note: The frequency of the subclock (SCLK) is a value for 2 division/4 division of the clock inputted to the low-speed oscillation pin (X0A and X1A) or the internal CR oscillation clock. The division ratio is set by the SCDS bit of the PLL/subclock control register (PSCCR). When using the internal CR oscillation clock, see "CHAPTER 6 CLOCK SUPERVISOR". Please consider the frequency difference of built-in CR oscillation when you use built-in CR oscillation clock as a sub-clock. 269 CHAPTER 15 WATCH TIMER 15.2 Block Diagram of Watch Timer The watch timer consists of the following blocks: • Watch timer counter • Counter clear circuit • Interval timer selector • Watch timer control register (WTC) ■ Block Diagram of Watch Timer Figure 15.2-1 Block Diagram of Watch Timer To watchdog timer Watch timer counter SCLK × 21 × 22 × 23 × 24 × 25 × 26 × 27 × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 OF OF OF OF Power-on reset Transits to hardware standby Transits to stop mode Counter clear circuit OF OF OF OF To subclock oscillation stabilization wait time Interval timer selector Watch timer interrupt OF : Overflow SCLK : Subclock WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0 Watch timer control register (WTC) The actual interrupt request number of the watch timer is as follows: Interrupt request number: #27(1BH) ● Watch timer counter The watch timer counter is a 15-bit up counter that uses the subclock (SCLK) as a count clock. ● Counter clear circuit The counter-clear circuit clears the watch timer counter. 270 CHAPTER 15 WATCH TIMER ● Interval timer selector The interval timer selector sets the overflow flag bit when the watch timer counter reaches the interval time set in the watch timer control register (WTC). ● Watch timer control register (WTC) The watch timer control register (WTC) selects the interval time, clears the watch timer counter, enables or disables an interrupt, checks the overflow (carry) state, and clears the overflow flag bit. 271 CHAPTER 15 WATCH TIMER 15.3 Configuration of Watch Timer This section explains the registers and interrupt factors of the watch timer. ■ List of Registers and Reset Values of Watch Timer Figure 15.3-1 List of Registers and Reset Values of Watch Timer Watch timer control register (WTC) bit Address: 0000AAH 7 6 5 4 3 2 1 0 1 × 0 0 1 0 0 0 ✕: Undefined ■ Generation of Interrupt Request from Watch Timer • When the interval time set by the interval time select bits (WTC:WTC2 to WTC0) is reached, the overflow flag bit (WTC:WTOF) is set to "1". • When the overflow flag bit is set (WTC:WTOF = 1) with interrupt enabled when the watch timer counter overflows (carries) (WTC:WTIE = 1), an interrupt request is generated. 272 CHAPTER 15 WATCH TIMER 15.3.1 Watch Timer Control Register (WTC) This section explains the functions of the watch timer control register (WTC). ■ Watch Timer Control Register (WTC) Figure 15.3-2 Watch Timer Control Register (WTC) Address 0000AAH 7 6 5 4 3 2 1 0 Reset value WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0 R/W R 1X001000 B R/W R/W R/W R/W R/W R/W bit2 bit1 bit0 WTC2 WTC1 WTC0 Interval time select bit 0 0 0 28/SCLK(31.25 ms) 0 0 1 29/SCLK(62.5 ms) 0 1 0 210/SCLK(125 ms) 0 1 1 211/SCLK(250 ms) 1 0 0 212/SCLK(500 ms) 1 0 1 213/SCLK(1.0 s) 1 1 0 214/SCLK(2.0 s) 1 1 1 215/SCLK(4.0 s) bit3 WTR 0 1 Watch timer clear bit Read ⎯ "1" is always read. Write Clear watch timer counter No effect bit4 WTOF 0 1 Overflow flag bit Read Write No overflow of the bit Clears WTOF bit corresponding to set interval time Overflow of the bit No effect corresponding to set interval time bit5 WTIE Overflow interrupt enable bit 0 Interrupt request disable 1 Interrupt request enable bit6 SCE Oscillation stabilization wait time end bit 0 Oscillation stabilization wait state 1 Oscillation stabilization wait time end R/W R X SCLK : Read/Write : Read only : Undefined : Subclock : Reset value bit7 WDCS 0 1 Watchdog clock select bit (input clock of watchdog timer) Main or PLL clock mode Subclock mode Watch timer Set "0" Timebase timer The parenthesized values are provided when subclock operates at 8.192 kHz. 273 CHAPTER 15 WATCH TIMER Table 15.3-1 Functions of Watch Timer Control Register (WTC) Bit Name Function bit7 WDCS: Watchdog clock select bit This bit selects the operation clock of the watchdog timer. <Main clock mode or PLL clock mode> When set to "0": Selects output of watch timer as operation clock of watchdog timer. When set to "1": Selects output of timebase timer as operation clock of watchdog timer. <Subclock mode> Always set this bit to 0 to select the output of the watch timer. Note: The watch timer and the timebase timer operate asynchronously. When the WDCS bit is changed from 0 to 1, the watchdog timer may run fast. The watchdog timer must be cleared before and after changing the WDCS bit. bit6 SCE: Oscillation stabilization wait time end bit This bit indicates that the oscillation stabilization wait time of the subclock ends. When cleared to "0": Subclock in oscillation stabilization wait state When set to "1" : Subclock oscillation stabilization wait time ends • The oscillation stabilization wait time of the subclock is fixed at 214 /SCLK (SCLK: subclock frequency). bit5 WTIE: Overflow interrupt enable bit This bit enables or disables generation of an interrupt request when the watch timer counter overflows (carries). When set to "0": Interrupt request not generated even at overflow (WTOF=1) When set to "1": Interrupt request generated at overflow (WTOF = 1) bit4 WTOF: Overflow flag bit This bit is set to "1" when the counter value of the watch timer reaches the value set by the interval time select bit. When an overflow carry occurs (WTOF = 1) with interrupt request enabled (WTIE = 1), an interrupt request is generated. When set to "0": Clears watch timer counter When set to "1": No effect • The overflow flag bit is set to "1" when the bit of the watch timer counter corresponding to the interval time set by the interval time select bits (WTC2 to WTC0) overflows (carries). bit3 WTR: Watch timer clear bit This bit clears the watch timer counter. When set to "0": Clears watch timer counter to "0000H". When set to "1": No effect Read: 1 is always read. bit2 to bit0 WTC2, WTC1, WTC0: Interval time select bits These bits set the interval time of the watch timer. • When the interval time set by the WTC2 to WTC0 bits is reached, the corresponding bit of the watch timer counter overflows (carries) and the overflow flag bit is set (WTC:WTOF = 1). • To set the WTC2 to WTC0 bits, set the WTOF bit to 0. 274 CHAPTER 15 WATCH TIMER 15.4 Watch Timer Interrupt When the interval time is reached with the watch timer interrupt enabled, the overflow flag bit is set to "1" and an interrupt request is generated. ■ Watch Timer Interrupt Table 15.4-1 shows the interrupt control bits and interrupt factors of the watch timer. Table 15.4-1 Interrupt Control Bits of Watch Timer Watch Timer Interrupt factor Interval time of watch timer counter Interrupt request flag bit WTC: WTOF(overflow flag bit) Interrupt factor enable bit WTC: WTIE • When the value set by the interval time select bits (WTC2 to WTC0) in the watch timer control register (WTC) is reached, the overflow flag bit in the WTC register is set to "1" (WTC:WTOF = 1). • When the overflow flag bit is set (WTC:WTOF = 1) with the watch timer interrupt enabled (WTC:WTIE = 1), an interrupt request is generated. • At interrupt processing, set the WTOF bit to 0 and cancel the interrupt request. ■ Watch Timer Interrupt and EI2OS Transfer Function • The watch timer does not correspond to the EI2OS function. • For details of the interrupt number, interrupt control register, and interrupt vector address, see "CHAPTER 3 INTERRUPTS". 275 CHAPTER 15 WATCH TIMER 15.5 Explanation of Operation of Watch Timer The watch timer operates as an interval timer or an oscillation stabilization wait time timer of subclock. It also supplies an operation clock to the watchdog timer. ■ Watch Timer Counter The watch timer counter continues incrementing in synchronization with the subclock (SCLK) while the subclock (SCLK) is operating. ● Clearing watch timer counter The watch timer counter is cleared to "0000H" when: • A power-on reset occurs. • The mode transits to the stop mode. • The watch timer clear bit (WTR) in the watch timer control register (WTC) is set to "0". Note: When the watch timer counter is cleared, the interrupts of the watchdog timer and interval timer that use the output of the watch timer counter are affected. To clear the watch timer by writing zero to the watch timer clear bit (WTR) in the watch timer control register (WTC), set the overflow interrupt enable bit (WTIE) in the WTC register to "0" and set the watch timer to interrupt inhibited state. Before permitting an interrupt, clear the interrupt request issued by writing zero to the overflow flag bit (WTOF) in the WTC register. ■ Interval Timer Function The watch timer can be used as an interval timer by generating an interrupt at each interval time. ● Settings when using watch timer as interval timer Operating the watch timer as an interval timer requires the settings shown in Figure 15.5-1 . Figure 15.5-1 Setting of Watch Timer bit7 WTC 6 5 4 3 2 1 bit0 WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0 : Used bit : Unused bit • When the value set by the interval time select bits (WTC1, WTC0) in the watch timer control register (WTC) is reached, the overflow flag bit in the WTC register is set to "1" (WTC:WTOF = 1). • When the overflow flag bit is set (WTC:WTOF = 1) with the overflow interrupt of the watch timer counter enabled (WTC:WTIE = 1), an interrupt request is generated. • The overflow flag bit (WTC:WTOF) is set when the interval time is reached at the starting point of the timing at which the watch timer is finally cleared. 276 CHAPTER 15 WATCH TIMER ● Clearing overflow flag bit (WTC:WTOF) When the mode is switched to the stop mode, the watch timer is used as an oscillation stabilization wait time timer of subclock. The WTOF bit is cleared concurrently with mode switching. ■ Setting Operation Clock of Watchdog Timer The watchdog clock select bit (WDCS) in the watch timer control register (WTC) can be used to set the clock input source of the watchdog timer. When using the subclock as the machine clock, always set the WDCS bit to 0 and select the output of the watch timer. ■ Oscillation Stabilization Wait Time Timer of Subclock When the watch timer returns from the power-on reset and the stop mode, it functions as an oscillation stabilization wait time timer of subclock. The subclock oscillation stabilization wait time is fixed at 214 /SCLK (SCLK: subclock frequency). Note: Please consider the frequency difference of built-in CR oscillation when you use built-in CR oscillation clock as a sub-clock. 277 CHAPTER 15 WATCH TIMER 15.6 Program Example of Watch Timer This section gives a program example of the watch timer. ■ Program Example of Watch Timer ● Processing specifications An interval interrupt at 213/SCLK (SCLK: subclock) is generated repeatedly. The internal time is approximately 1.0 s (when subclock operates at 8.192 kHz). ● Coding example ICR08 EQU 0000B8H ;Interrupt control register WTC EQU 0000AAH ;Watch timer control register WTOF EQU WTC:4 ;Overflow flag bit ; ;---------Main program------------------------------------CODE CSEG START: ; ;Stack pointer (SP) already ;initialized AND CCR,#0BFH ;Interrupt disabled MOV I:ICR07,#00H ;Interrupt level 0 (highest) MOV I:WTC,#10100101B ;Interrupt enabled ;Overflow flag cleared ;Watch timer counter cleared, MOV OR ILM,#07H CCR,#40H ;213/SCLK(approx. 1.0 s) ;Set ILM in PS to level 7 ;Interrupt enabled LOOP: • Processing by user • BRA LOOP ;---------Interrupt program-------------------------------------WARI: CLRB I:WTOF ;Overflow flag cleared • Processing by user • RETI ;Return from interrupt processing CODE ENDS ;---------Vector setting-----------------------------------------VECT CSEG ABS=0FFH ORG 00FF90H ;Reset vector set #27 (1BH) DSL 278 WARI CHAPTER 15 WATCH TIMER VECT ORG DSL DB ENDS END 00FFDCH START 00H ;Reset vector set ;Set to single-chip mode START 279 CHAPTER 15 WATCH TIMER 280 CHAPTER 16 8-/16-BIT PPG TIMER This chapter describes the functions and operations of the 8-/16-bit PPG timer. 16.1 Overview of 8-/16-bit PPG Timer 16.2 Block Diagram of 8-/16-bit PPG Timer 16.3 Configuration of 8-/16-bit PPG Timer 16.4 Interrupts of 8-/16-bit PPG Timer 16.5 Explanation of Operation of 8-/16-bit PPG Timer 16.6 Precautions when Using 8-/16-bit PPG Timer 281 CHAPTER 16 8-/16-BIT PPG TIMER 16.1 Overview of 8-/16-bit PPG Timer The 8-/16-bit PPG timer is a reload timer module with two channels (PPGC and PPGD) that outputs a pulse in any cycle and at any duty ratio. A combination of two channels provides: • 8-bit PPG output 2-channel independent operation mode • 16-bit PPG output operation mode • 8+8-bit PPG output operation mode The MB90360 series has two 8-/16-bit PPG timers. This section explains the functions of PPGC/D. PPGE/F has the same functions as PPGC/D. ■ Functions of 8-/16-bit PPG Timer The 8-/16-bit PPG timer consists of four 8-bit reload registers (PRLHC, PRLLC, PRLHD, and PRLLD) and two PPG down counters (PCNTC and PCNTD). • Individual setting of High and Low widths in output pulse enables an output pulse of any cycle and duty ratio. • The count clock can be selected from six internal clocks. • The 8-/16-bit PPG timer can be used as an interval timer by generating an interrupt request at each interval time. • An external circuit enables the 8-/16-bit PPG timer to be used as a D/A converter. 282 CHAPTER 16 8-/16-BIT PPG TIMER ■ Operation Modes of 8-/16-bit PPG Timer ● 8-bit PPG output 2-channel independent operation mode The 8-bit PPG output 2-channel independent operation mode causes the 2-channel modules (PPGC and PPGD) to operate as each independent 8-bit PPG timer. Table 16.1-1 shows the interval times in the 8-bit PPG output 2-channel independent operation mode. Table 16.1-1 Interval Times in 8-bit PPG Output 2-channel Independent Operation Mode PPGC, PPGD Count Clock Cycle Interval Time Output Pulse Time 1/φ(41.7 ns) 1/φ to 28/φ 2/φ to 29/φ 2/φ(83.3 ns) 2/φ to 29/φ 22/φ to 210/φ 22/φ(167 ns) 22/φ to 210/φ 23/φ to 211/φ 23/φ(333 ns) 23/φ to 211/φ 24/φ to 212/φ 24/φ(667 ns) 24/φ to 212/φ 25/φ to 213/φ 29/HCLK(128 µs) 29/HCLK to 217/HCLK 210/HCLK to 218/HCLK HCLK: Oscillation clock φ : Machine clock The parenthesized values are provided when the oscillation clock operates at 4 MHz and the machine clock operates at 24 MHz. ● 16-bit PPG output operation mode The 16-bit PPG output operation mode concatenates the 2-channel modules (PPGC and PPGD) to operate as a 16-bit 1-channel PPG timer. Table 16.1-2 shows the interval times in this mode. Table 16.1-2 Interval Times in 16-bit PPG Output Operation Mode Count clock cycle Interval time Output pulse time 1/φ(41.7 ns) 1/φ to 216/φ 2/φ to 217/φ 2/φ(83.3 ns) 2/φ to 217/φ 22/φ to 218/φ 22/φ(167 ns) 22/φ to 218/φ 23/φ to 219/φ 23/φ(333 ns) 23/φ to 219/φ 24/φ to 220/φ 24/φ(667 ns) 24/φ to 220/φ 25/φ to 221/φ 29/HCLK(128 µs) 29/HCLK to 225/HCLK 210/HCLK to 226/HCLK HCLK: Oscillation clock φ : Machine clock The parenthesized values are provided when the oscillation clock operates at 4 MHz and the machine clock operates at 24 MHz. 283 CHAPTER 16 8-/16-BIT PPG TIMER ● 8+8-bit PPG output operation mode The 8 + 8-bit PPG output operation mode causes the PPGC of the 2-channel modules to operate as an 8-bit prescaler and the underflow output of the PPGC to operate as the count clock of the PPGD. Table 16.1-3 shows the interval times in this mode. Table 16.1-3 Interval Times in 8+8-bit PPG Output Operation Mode PPGC PPGD Count Clock Cycle Interval Time Output Pulse Time Interval Time Output Pulse Time 1/φ(41.7 ns) 1/φ to 28/φ 2/φ to 29/φ 1/φ to 216/φ 2/φ to 217/φ 2/φ(83.3 ns) 2/φ to 29/φ 22/φ to 210/φ 2/φ to 217/φ 22/φ to 218/φ 22/φ(167 ns) 22/φ to 210/φ 23/φ to 211/φ 22/φ to 218/φ 23/φ to 219/φ 23/φ(333 ns) 23/φ to 211/φ 24/φ to 212/φ 23/φ to 219/φ 24/φ to 220/φ 24/φ(667 ns) 24/φ to 212/φ 25/φ to 213/φ 24/φ to 220/φ 25/φ to 221/φ 29/HCLK(128µs) 29/HCLK to 217/HCLK 210/HCLK to 218/ HCLK 29/HCLK to 225/HCLK 210/HCLK to 226/ HCLK HCLK: Oscillation clock φ : Machine clock The parenthesized values are provided when the oscillation clock operates at 4 MHz and the machine clock operates at 24 MHz. 284 CHAPTER 16 8-/16-BIT PPG TIMER 16.2 Block Diagram of 8-/16-bit PPG Timer The MB90360 series contains two 8-/16-bit PPG timers (each with 2 channels). One 8-/16-bit PPG timer consists of 8-bit PPG timers with two channels. This section shows the block diagrams for the 8-/16-bit PPG timer C and 8-/16-bit PPG timer D. The PPGE has the same function as the PPGC, and PPGF has the same function as PPGD. ■ Channels and PPG Pins of PPG Timers Figure 16.2-1 shows the relationship between the channels and the PPG pins of the 8-/16-bit PPG timers in the MB90360 series. Figure 16.2-1 Channels and PPG Pins of PPG Timers PPGC/D Pin PPGCD: REV PPGC output pin Pin PPGD output pin PPGE/F Pin PPGEF: REV PPGE output pin Pin PPGF output pin 285 CHAPTER 16 8-/16-BIT PPG TIMER 16.2.1 Block Diagram for 8-/16-bit PPG Timer C The 8-/16-bit PPG timer C consists of the following blocks. ■ Block Diagram of 8-/16-bit PPG Timer C Figure 16.2-2 Block Diagram of 8-/16-bit PPG Timer C High level side data bus Low level side data bus PPGC reload register PPGC operation mode control register (PPGCC) PRLLC (Low level PRLHC (High level side) PEN0 - PE0 PIE0 PUF0 - PPGC temporary buffer C (PRLBHC) - R S Reload register L/H selector Select signal Reload Interrupt request output* Q 2 Count start value Reserved Operation mode control signal PPGD underflow PPGC underflow (to PPGD) Clear Pulse selector PPGC down counter (PCNTC) Underflow CLK Invert PPGC output latch Pin PPG output control circuit PPGC PPGD output Timebase timer output(512/HCLK) Resource clock (1/φ) Resource clock (2/φ) Resource clock (4/φ) Resource clock (8/φ) Resource clock (16/φ) Count clock selector 3 Select signal PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 - REV PPGC/D count clock select register (PPGCD) : Undefined Reserved : Reserved bit HCLK : Oscillation clock frequency : Machine clock frequency φ * : The interrupt output of 8-/16- bit PPG timer C is combined to one interrupt by OR circuit with the interrupt request output of PPG timer D. 286 CHAPTER 16 8-/16-BIT PPG TIMER ● Details of pins in block diagram Table 16.2-1 lists the actual pin names and interrupt request numbers of the 8-/16-bit PPG timer. Table 16.2-1 Pins and Interrupt Request Numbers in Block Diagram Channel Output Pin Interrupt Request Number PPG:REV=0 PPG:REV=1 PPGC P66 / PPGC P22 / PPGD PPGD P22 / PPGD P66 / PPGC PPGE P67/ PPGE P23 / PPGF PPGF P23/ PPGF P67 / PPGE #23 (17H) #24 (18H) ● PPG operation mode control register C (PPGCC) This register enables or disables operation of the 8-/16-bit PPG timer, pin output and an underflow interrupt. It also indicates the occurrence of an underflow. ● PPGC/D count clock select register (PPGCD) This register sets the count clock of the 8-/16-bit PPG timer and switching the output pin between PPGC and PPGD. ● PPGC reload registers (PRLHC, PRLLC) These registers set the High width or Low width of the output pulse. The values set in these registers are reloaded to the PPGC down counter (PCNTC) when the 8-/16-bit PPG timer is started. ● PPGC down counter (PCNTC) This counter is an 8-bit down counter that alternately reloads the values set in the PPGC reload registers (PRLHC and PRLLC) to decrement. When an underflow occurs, the pin output is inverted. The 2-channel PPG down counters (PPGC and PPGD) can also be concatenated for use as a single-channel 16-bit PPG down counter. ● PPGC temporary buffer (PRLBHC) This buffer prevents deviation of the output pulse width caused at writing to the PPG reload registers (PRLHC and PRLLC). This buffer stores the PRLHC value temporarily and enables it in synchronization with the timing of writing to the PRLLC. ● Reload register L/H selector This selector detects the current pin output level to select which register value, Low reload register (PRLLC) or High reload register (PRLHC), should be reloaded to the PPGC down counter. ● Count clock selector This selector selects the count clock to be inputted to the PPGC down counter from five frequency-divided clocks of the machine clock or the frequency-divided clocks of the timebase timer. ● PPG output control circuit This circuit inverts the pin output level and the output when an underflow occurs. 287 CHAPTER 16 8-/16-BIT PPG TIMER 16.2.2 Block Diagram of 8-/16-bit PPG Timer D The 8-/16-bit PPG timer D consists of the following blocks. ■ Block Diagram of 8-/16-bit PPG Timer D Figure 16.2-3 Block Diagram of 8-/16-bit PPG Timer D High level side data bus Low level side data bus PPGD operation mode control register (PPGCD) PPGD reload register PRLHD PRLLD (High level side) (Low level side) PEN1 Re- - Operation mode control signal PE1 PIE1 PUF1 MD1 MD0 served 2 R PPGD temporary buffer (PRLBHD) S Reload register L/H selector Count start value PPGC underflow (from PPGC) Q Select signal Reload Clear UnderPPGD down counter flow (PCNTD) PPGD underflow (to PPGC) Interrupt request output* CLK Invert PPGD output latch Pin PPGD PPG output control circuit MD0 PPGC output Timebase timer output (512/HCLK) Resource clock (1/φ) Resource clock (2/φ) Resource clock (4/φ) Resource clock (8/φ) Resource clock (16/φ) Count clock selector 3 Select signal PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 - REV : Undefined (from PPG0) PPGC/D count clock select register (PPGCD) Reservation: Reserved bit HCLK : Oscillation clock frequency : Machine clock frequency φ * : The interrupt output of 8-/16- bit PPG timer D is combined to one interrupt by OR circuit with the interrupt request output of PPG timer C. 288 CHAPTER 16 8-/16-BIT PPG TIMER ● Details of pins in block diagram Table 16.2-2 lists the actual pin names and interrupt request numbers of the 8-/16-bit PPG timer. Table 16.2-2 Pins and Interrupt Request Numbers in Block Diagram Channel Output Pin Interrupt Request Number PPG:REV=0 PPG:REV=1 PPGC P66 / PPGC P22 / PPGD PPGD P22 / PPGD P66 / PPGC PPGE P67/ PPGE P23 / PPGF PPGF P23/ PPGF P67 / PPGE #23 (17H) #24 (18H) ● PPG operation mode control register D (PPGCD) This register sets the operation mode of the 8-/16-bit PPG timer, enables or disables the operation of the 8-/ 16-bit PPG timer D, the pin output and an underflow interrupt, and also indicates the generation of an underflow. ● PPGC/D count clock select register (PPGCD) This register sets the count clock of the 8-/16-bit PPG timer. ● PPGD reload registers (PRLHD, PRLLD) These registers set the High width or Low width of the output pulse. The values set in these registers are reloaded to the PPGD down counter (PCNTD) when the 8-/16-bit PPG timer D is started. ● PPGD down counter (PCNTD) This counter is an 8-bit down counter that alternately reloads the values set in the PPGD reload registers (PRLHD and PRLLD) to decrement. When an underflow occurs, the pin output is inverted. The 2-channel PPG down counters (PPGC and PPGD) can also be connected for use as a single-channel 16-bit PPG down counter. ● PPGD temporary buffer (PRLBHD) This buffer prevents deviation of the output pulse width caused at writing to the PPG reload registers (PRLHD and PRLLD). It stores the PRLHD value temporarily and enables it in synchronization with the timing of writing to the PRLLD. ● Reload register L/H selector This selector detects the current pin output level to select which register value, Low reload register (PRLLD) or High reload register (PRLHD), should be reloaded to the PPGD down counter. ● Count clock selector This selector selects the count clock to be inputted to the PPGD down counter from five frequency-divided clocks of the machine clock or the frequency-divided clocks of the timebase timer. ● PPG output control circuit This circuit inverts the pin output level and the output when an underflow occurs. 289 CHAPTER 16 8-/16-BIT PPG TIMER 16.3 Configuration of 8-/16-bit PPG Timer This section explains the pins, registers and interrupt factors of the 8-/16-bit PPG timer. ■ Pins of 8-/16-bit PPG Timer The pins of the 8-/16-bit PPG timer serve as general-purpose I/O ports. Table 16.3-1 indicates the pin functions and pin settings required to use the 8-/16-bit PPG timer. Table 16.3-1 Pins of 8-/16-bit PPG Timer Channel 290 Pin Name Pin Function Pin Setting Required for Use of 8-/16-bit PPG Timer PPGC P66 / AN6 / PPGC General-purpose I/O port, A/D converter analog input 6/ PPG output C • Analog input enable register : setting to disable(ADER6:ADE6=0) • PPG operating mode control register : pin output enable (PPGCC:PE0=1) PPGD P22 / PPGD General-purpose I/O port, PPG output D • PPG operating mode control register : pin output enable (PPGCD:PE1=1) PPGE P67 / AN7 / PPGE General-purpose I/O port, A/D converter analog input 7/ PPG output E • Analog input enable register : setting to disable (ADER6:ADE7=0) • PPG operating mode control register : pin output enable (PPGCE:PE0=1) PPGF P23 / PPGF General-purpose I/O port, PPG output F • PPG operating mode control register : pin output enable (PPGCF:PE1=1) CHAPTER 16 8-/16-BIT PPG TIMER ■ List of Registers and Reset Values of 8-/16-bit PPG Timer Figure 16.3-1 List of Registers and Reset Values of 8-/16-bit PPG Timer PPGm operation mode control register: H (PPGCm) bit 14 0 bit PPGn operation mode control register: L (PPGCn) PPGn/m count clock select register (PPGnm) 15 7 6 0 13 12 11 10 9 8 0 0 0 0 0 1 5 4 3 2 1 0 0 0 0 1 7 6 5 4 3 2 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 bit 7 6 5 4 3 2 1 0 bit 15 14 13 12 11 10 9 8 bit 7 6 5 4 3 2 1 0 bit 1 0 0 PPGn reload register: H(PRLHn) PPGn reload register: L(PRLLn) PPGm reload register: H(PRLHm) PPGm reload register: L(PRLLm) ✕: Undefined n = C, E m = D, F ■ Generation of Interrupt Request from 8-/16-bit PPG Timer In the 8-/16-bit PPG timer, the underflow generation flag bits in the PPG operation mode control registers (PPGCn:PUFn, PPGCm:PUFm) are set to "1" when an underflow occurs. If the underflow interrupts of channels causing an underflow are enabled (PPGCn: PIE0=1, PPGCm: PIE1=1), an underflow interrupt request is generated to the interrupt controller. 291 CHAPTER 16 8-/16-BIT PPG TIMER 16.3.1 PPGC Operation Mode Control Register (PPGCC) The PPGC operation mode control register (PPGC0) provides the following settings for the operation of 8-/16-bit PPG timer C: • Enabling or disabling operation of 8-/16-bit PPG timer C • Switching between pin functions (enabling or disabling pulse output) • Enabling or disabling underflow interrupt • Setting underflow interrupt request flag This section explains the PPGCC function only. The PPGCE has the same function as the PPGCC, and the 8-/16-bit PPPG timer C and E is set. ■ PPGC Operation Mode Control Register (PPGCC) Figure 16.3-2 PPGC Operation Mode Control Register (PPGCC) PPGCC Address: 000048H Other channel: chE PPGCE 00004CH chC 7 6 PEN0 R/W 5 4 3 2 1 PE0 PIE0 PUF0 − R/W R/W R/W 0 Reserved − − R/W Reset value 0 X 0 0 0 X X 1B bit 0 Reserved 1 Reserved bit Always set to "1" bit 3 PUF0 0 1 Underflow generation flag bit Read Write No underflow Clears PUF0 bit Underflow No effect bit 4 PIE0 0 1 Underflow interrupt enable bit Interrupt request disable Interrupt request enable bit 5 PE0 0 1 PPG0 pin output enable bit General-purpose I/O port (pulse output disable) PPGC output (pulse output enable) bit 7 PEN0 R/W : Read/Write W : Write only X : Indeterminate − : Undefined : Reset value 292 PPG0 operation enable bit 0 Couting disable (holds "L" level output) 1 Counting enable CHAPTER 16 8-/16-BIT PPG TIMER Table 16.3-2 Functions of PPGC Operation Mode Control Register (PPGCC) Bit Name Function bit7 PEN0: PPG0 operation enable bit This bit enables or disables the count operation of the 8-/16-bit PPG timer C. When set to "0": Count operation disabled When set to "1": Count operation enabled • When the count operation is disabled (PEN0=0), and the pulse output is enabled (PE0=1), the output is held at a Low level. bit6 Undefined bit Read: The value is undefined. Write: No effect bit5 PE0: PPG0 pin output enable bit This bit switches between PPGC pin functions and enables or disables the pulse output. When set to "0": PPGC pin functions as general-purpose I/O port. The pulse output is disabled. When set to "1": PPGC pin functions as PPGC output pin. The pulse output is enabled. bit4 PIE0: Underflow interrupt enable bit This bit enables or disables an interrupt. When set to "0": No interrupt request generated even at underflow (PUF0 = 1). When set to "1": Interrupt request generated at underflow (PUF0 = 1) bit3 PUF0: Underflow generation flag bit 8-bit PPG output 2-channel independent operation mode, 8+8-bit PPG output operation mode: When the value of the PPGC down counter is decremented from "00H" to"FFH", an underflow occurs (PUF0 = 1). 16-bit PPG output operation mode: When the values of the PPGC and PPGD down counters are decremented from "0000H" to "FFFFH", an underflow occurs (PUF0 = 1). • When an underflow occurs (PUF0 = 1) with an underflow interrupt enabled (PIE0 = 1), an interrupt request is generated. When set to "0": Clears counter When set to "1": No effect Read by read modify write instructions: 1 is read. bit2 bit1 Undefined bits Write: No effect Read: The value is undefined. bit0 Reserved: Reserved bit Always set this bit to 1. 293 CHAPTER 16 8-/16-BIT PPG TIMER 16.3.2 PPGD Operation Mode Control Register (PPGCD) The PPGD operation mode control register provides the following settings about operation of 8-/16-bit PPG timer D: • Enabling or disabling operation of 8-/16-bit PPG timer D • Switching between pin functions (enabling or disabling pulse output) • Enabling or disabling underflow interrupt • Setting underflow interrupt request flag • Setting the operation mode of the 8-/16-bit PPG timer D and C This section explains the PPGCD function only. The PPGCF has the same function as the PPGCD, and the 8-/16-bit PPG timer F is set. ■ PPGD Operation Mode Control Register (PPGCD) Figure 16.3-3 PPGD Operation Mode Control Register (PPGCD) chD PPGCD Other channel: chF PPGCF Address: 000049H 00004DH 15 14 12 11 10 9 8 PE1 PIE1 PUF1 MD1 MD0 Reserved PEN1 R/W 13 − R/W R/W R/W R/W R/W W Reset value 0 X 0 0 0 0 0 1B bit 8 Reserved 1 Reserved bit Always set to "1". bit 10 MD1 bit 9 MD0 0 0 0 1 1 1 0 1 Operation mode select bits 8-bit PPG output 2 channels independent operation mode 8+8-bit PPG output operation mode Setting disable 16-bit PPG output operation mode bit 11 PUF1 0 1 bit 12 PIE1 0 1 bit 13 PE1 0 1 R/W : Read/Write W : Write only X : Indeterminate − : Undefined : Reset value 294 bit 15 PEN1 0 1 Underflow generation flag bit Read Write No underflow Clears PUF1 bit Underflow No effect Underflow interrupt enable bit Underflow interrupt request disable Underflow interrupt request enable PPG1 pin output enable bit General-purpose I/O port (pulse output disable) PPG1 output (pulse output enable) PPG1 operation enable bit Counting disable (holds "L" level output) Counting enable CHAPTER 16 8-/16-BIT PPG TIMER Table 16.3-3 Functions of PPGD Operation Mode Control Register (PPGCD) Bit name Function bit15 PEN1: PPG1 operation enable bit This bit enables or disables the count operation of the 8-/16-bit PPG timer D. When set to "0": Count operation disabled When set to "1": Count operation enabled • When the count operation is disabled (PEN1 = 0), and the pulse output is enabled (PE1=1), the output is held at a Low level. bit14 Undefined bit Read: The value is undefined. Write: No effect bit13 PE1: PPG1 Pin output enable bit This bit switches between PPGD pin functions and enables or disables the pulse output. When set to "0": PPGD pin functions as general-purpose I/O port. The pulse output is disabled. When set to "1": PPGD pin functions as PPGD output pin. The pulse output is enabled. bit12 PIE1: Underflow interrupt enable bit This bit enables or disables an interrupt. When set to "0": No interrupt request is generated even at underflow (PUF1 = 1) When set to "1": Interrupt request is generated at underflow (PUF1 = 1) bit11 PUF1: Underflow generation flag bit 8-bit PPG output 2-channel independent operation mode, 8+8-bit PPG output operation mode: When the value of the PPGD down counter is decremented from "00H" to "FFH", an underflow occurs (PUF1 = 1). 16-bit PPG output operation mode:When the values of the PPGC and PPGD down counters are decremented from "0000H" to "FFFFH", an underflow occurs (PUF1 = 1). • When an underflow occurs (PUF1 = 1) with an underflow interrupt request enabled (PIE1 = 1), an interrupt request is generated. When set to "0": Clears counter When set to "1": No effect Read by read modify write instructions: 1 is read. bit10 bit9 MD1, MD0: Operation mode select bits These bits set the operation mode of the 8-/16-bit PPG timer. [Any mode other than 8-bit PPG output 2-channel independent operation mode] • Use a word instruction to set the PPG operation enable bits (PEN0 and PEN1) at one time. • Do not set operation of only one of the two channels (PEN1 = 0/PEN0 = 1 or PEN1 = 1/ PEN0 = 0). Note: Do not set the MD1 and MD0 bits to "10B". bit8 Reserved: Reserved bit Always set this bit to 1. 295 CHAPTER 16 8-/16-BIT PPG TIMER 16.3.3 PPGC/D Count Clock Select Register (PPGCD) The PPGC/D count clock select register selects the count clock of the 8-/16-bit PPG timers C and D and the output pin. This section explains the PPGCD function only. The PPGEF has the same function as the PPGCD, and the 8-/16-bit PPG timers E and F are set. ■ PPGC/D Count Clock Select Register (PPGCD) Figure 16.3-4 PPGC/D Count Clock Select Register (PPGCD) chD PPGCD Address: 00004AH 7 6 5 4 3 2 1 PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 Other channel: chF PPGEF 00004EH R/W R/W R/W R/W R/W R/W 0 REV − R/W Reset value 0 0 0 0 0 0 X 0B bit 0 REV 0 1 PPG output pin select bit Output pulse from standard output pin Switch output pin between PPGn and PPGm bit 4 bit 3 bit 2 PCM2 PCM1 PCM0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 PPGC count clock select bits 1/φ(41.7 ns) 2/φ(83.3 ns) 22/φ(167 ns) 23/φ(333 ns) 24/φ(667 ns) Setting disable Setting disable 29/HCLK(128 µs) bit 7 bit 6 bit 5 PCS2 PCS1 PCS0 : Read/Write : Indeterminate − : Undefined : Reset value HCLK : Oscillation clock φ : Machine clock frequency R/W X 0 0 0 0 1 1 1 1 The parenthesized values are provided when the oscillation clock operates at 4 MHz and the machine clock operates at 24 MHz. n = C, E m = n+1 296 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 PPGD count clock select bits 1/φ(41.7 ns) 2/φ(83.3 ns) 22/φ(167 ns) 23/φ(333 ns) 24/φ(667 ns) Setting disable Setting disable 29/HCLK(128 µs) CHAPTER 16 8-/16-BIT PPG TIMER Table 16.3-4 Functions of PPGC/D Count Clock Select Register (PPGCD) Bit Name Function bit7 to bit5 PCS2 to PCS0: PPGD count clock select bits These bits set the count clock of the 8-/16-bit PPG timer D. • The count clock can be selected from five frequency-divided clocks of the machine clock and the frequency-divided clocks of the timebase timer. • The settings of the PPGD count clock select bits (PCS2 to PCS0) are enabled only in the 8-bit PPG output 2-channel independent mode (PPGCD: MD1, MD0="00B"). bit4 to bit2 PCM2 to PCM0: PPGC count clock select bits These bits set the count clock of the 8-/16-bit PPG timer C. • The count clock can be selected from five frequency-divided clocks of the machine clock and the frequency-divided clocks of the timebase timer. bit1 Undefined bit Read: The value is undefined. Write: No effect bit0 REV: PPG output pin select bit This bit switches the output pin in the 8-/16-bit PPG timer C and D. When set to "0": Output from the standard output pin. PPGC → PPGC output pin PPGD → PPGD output pin When set to "1": Switch the output pin. PPGC → PPGD output pin PPGD → PPGC output pin 297 CHAPTER 16 8-/16-BIT PPG TIMER 16.3.4 PPG Reload Registers (PRLLC/PRLHC, PRLLD/PRLHD) The value (reload value) from which the PPG down counter starts counting is set in the PPG reload registers, which are an 8-bit register at Low level and an 8-bit register at High level. This section explains the function of PRLLC/PRLHC and PRLLD/PRLHD only. The PRLLE/PRLHE, PRLLF/PRLHF have the same function as the PRLLC/PRLHC, and the 8-/ 16-bit PPG timers E, F are set. ■ PPG Reload Registers (PRLLC/PRLHC, PRLLD/PRLHD) Figure 16.3-5 PPG Reload Registers (PRLLC/PRLHC, PRLLD/PRLHD) Address: chC PRLHC chD PRLHD 007919H 00791BH Other channel: chE PRLHE chF PRLHF chC PRLLC chD PRLLD 00791DH 00791FH bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 D15 D8 D13 D12 D11 D10 D9 Reset value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W Address: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 007918H 00791AH Reset value D7 D6 D5 D4 D3 D2 D1 D0 XXXXXXXXB Other channel: chE PRLLE chF PRLLF D14 R/W R/W R/W R/W R/W R/W R/W R/W 00791CH 00791EH R/W : Read/Write ✕ : Undefined Table 16.3-5 indicates the functions of the PPG reload registers. Table 16.3-5 Functions of PPG Reload Registers Function 8-/16-bit PPG Timer C 8-/16-bit PPG Timer D Retains reload value on Low-level side PRLLC PRLLD Retains reload value on High-level side PRLHC PRLHD Notes: • In the 16-bit PPG output operation mode (PPGCD: MD1, MD0="11B"), use a long-word instruction to set the PPG reload registers or the word instruction to set the PPGC and PPGD in this order. • In the 8 + 8-bit PPG output operation mode (PPGCD: MD1, MD0="01B"), set the same value in both the Low-level and High-level PPG reload registers (PRLLC/PRLHC) of the 8-/16-bit PPG timer C. Setting a different value in the Low-level and High-level PPG reload registers may cause the 8-/16-bit PPG timer D to have different PPG output waveforms at each clock cycle. 298 CHAPTER 16 8-/16-BIT PPG TIMER 16.4 Interrupts of 8-/16-bit PPG Timer The 8-/16-bit PPG timer can generate an interrupt request when the PPG down counter underflows. It also not corresponds to the EI2OS. ■ Interrupts of 8-/16-bit PPG Timer Table 16.4-1 shows the interrupt control bits and interrupt factor of the 8-/16-bit PPG timer. Table 16.4-1 Interrupt Control Bits of 8-/16-bit PPG Timer PPGn PPGm Interrupt request flag bit PPGCn: PUF0 PPGCm: PUF1 Interrupt request enable bit PPGCn: PIE0 PPGCm: PIE1 Interrupt factor Underflow in PPGn down counter Underflow in PPGm down counter Note: n = C, E m=n+1 [8-bit PPG output 2-channel independent operation mode or 8 + 8-bit PPG output operation mode] • In the 8-bit PPG output 2-channel independent operation mode or the 8 + 8-bit PPG output operation mode, the PPGn and PPGm timers can generate an interrupt independently. • When the value of the PPGn or PPGm down counter is decremented from "00H" to "FFH", an underflow occurs. When an underflow occurs, the underflow generation flag bit in the channel causing an underflow is set (PPGCn: PUF0=1 or PPGCm: PUF1=1). • If an interrupt request from the channel that causes an underflow is enabled (PPGCn: PIE0=1 or PPGCm: PIE1=1), an interrupt request is generated. [16-bit PPG output operation mode] • In the 16-bit PPG output operation mode, when the values of the PPGn and PPGm down counters are decremented from "0000H" to "FFFFH", an underflow occurs. When an underflow occurs, the underflow generation flag bits in the two channels are set at one time (PPGCn: PUF0=1 or PPGCm: PUF1=1). • When an underflow occurs with either of the two channel of the interrupt requests enabled (PPGCn: PIE1=0, PPGCm: PIE1=1 or PPGCn: PIE0=1, PPGCm: PIE0=0), an interrupt request is generated. • To prevent duplication of interrupt requests, disable either of the two channel of the underflow interrupt enable bits in advance (PPGCn: PIE0=0, PPGCm: PIE1=1 or PPGCn: PIE0=1, PPGCm: PIE1=0). • When the two channels of the underflow generation flag bits are set (PPGCn: PUF0=1 and PPGCm: PUF1=1), clear the two channels at the same time. ■ Interrupt of 8-/16-bit PPG Timer For details of the interrupt number, interrupt control register, and interrupt vector address, see "CHAPTER 3 INTERRUPTS". 299 CHAPTER 16 8-/16-BIT PPG TIMER 16.5 Explanation of Operation of 8-/16-bit PPG Timer The 8-/16-bit PPG timer outputs a pulse width at any frequency and at any duty ratio continuously. ■ Operation of 8-/16-bit PPG Timer ● Output operation of 8-/16-bit PPG timer • The 8-/16-bit PPG timer has two (Low-level and High-level) 8-bit reload registers (PRLLn/PRLHn and PRLLm/PRLHm) for per channel. • The values set in the 8-bit reload registers (PRLLn/PRLHn and PRLLm/PRLHm) are reloaded alternately to the PPG down counters (PCNTn and PCNTm). • After reloading the values in the PPG down counters, decrementing is performed in synchronization with the count clocks set by the PPG count clock select bits (PPGnm: PCM2 to PCM0 and PCS2 to PCS0). • If the values set in the reload registers are reloaded to the PPG down counters when an underflow occurs, the pin output is inverted. Figure 16.5-1 shows the output waveform of the 8-/16-bit PPG timer. Figure 16.5-1 Output Waveform of 8-/16-bit PPG Timer Operating start Operating stop PPG operating enable bit (PEN) PPG output pin T × (L + 1) T × (H + 1) L : Value of PPG reload register (PRLL) H : Value of PPG reload register (PRLH) T : Count clock cycle ● Operation modes of 8-/16-bit PPG timer As long as the operation of the 8-/16-bit PPG timer is enabled (PPGCn: PEN0=1, PPGCm: PEN1=1), a pulse waveform is outputted continuously from the PPG output pin. A pulse width of any frequency and duty ratio can be set. The pulse output of the 8-/16-bit PPG timer is not stopped until operation of the 8-/16-bit PPG timer is stopped (PPGCn: PEN0=0, PPGCm: PEN1=0). • 8-bit PPG output 2-channel independent operation mode • 16-bit PPG output operation mode • 8 + 8-bit PPG output operation mode Note: n = C, E m = n+1 300 CHAPTER 16 8-/16-BIT PPG TIMER 16.5.1 8-bit PPG Output 2-channel Independent Operation Mode In the 8-bit PPG output 2-channel independent operation mode, the 8-/16-bit PPG timer is set as an 8-bit PPG timer with two independent channels. PPG output operation and interrupt request generation can be performed independently for each channel. ■ Setting for 8-bit PPG Output 2-channel Independent Operation Mode Operating the 8-/16-bit PPG timer in the 8-bit PPG output 2-channel independent operation mode requires the setting shown in Figure 16.5-2 . Figure 16.5-2 Setting for 8-bit PPG Output 2-channel Independent Operation Mode bit15 14 PPGCm/PPGCn PEN1 1 PPGnm PRLHn/PRLLn − 13 12 11 10 9 PE1 PIE1 PUF1 MD1 MD0 0 bit8 bit7 Reserved PEN0 0 1 (Reserved area) PPGn set High level side reload values. PRLHm/PRLLm PPGm set High level side reload values. 6 − 5 4 3 PE0 PIE0 PUF0 2 − 1 bit0 − Reserved 1 1 PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 − REV PPGn set Low level side reload values. PPGm set Low level side reload values. : Used bit - : Undefined bit 1 : Set 1 0 : Set 0 Note: n = C, E m=n+1 Note: Use the word instruction to set both High-level and Low-level PPG reload registers (PRLLn/PRLHn and PRLLm/PRLHm) at the same time. 301 CHAPTER 16 8-/16-BIT PPG TIMER ● Operation in 8-bit PPG output 2-channel independent operation mode • The 8-bit PPG timer with two channels performs an independent PPG operation. • When the pin output is enabled (PPGCn: PEC=1, PPGCm: PED=1), if the PPG output pin selection is set to standard (PPGnm:REV=0), the PPGn pulse wave is outputted from the PPGn pin and the PPGm pulse wave is outputted from the PPGm pin. When the PPG output pin is switched (PPGnm: REV=1), the PPGm pulse wave is outputted from the PPGn pin and the PPGn pulse wave is outputted from the PPGm pin. • When the reload value is set in the PPG reload registers (PRLLn/PRLHn, PRLLm/PRLHm) to enable the operation of the PPG timer (PPGCn: PENC=1, PPGCm: PEND=1), the PPG down counter of the enabled channel starts counting. • To stop the count operation of the PPG down counter, disable the operation of the PPG timer of the channel to be stopped (PPGCn: PENC=0, PPGCm: PEND=0). The count operation of the PPG down counter is stopped and the output of the PPG output pin is held at a Low level. • When the PPG down counter of each channel underflows, the reload values set in the PPG reload registers (PRLLn/PRLHn, PRLLm/PRLHm) are reloaded to the PPG down counter that underflows. • When an underflow occurs, the underflow generation flag bit in the channel that causes an underflow is set (PPGCn: PUFC=1, PPGCm: PUFD=1). If an interrupt request is enabled at the channel that causes an underflow (PPGCn: PIEC=1, PPGCm: PIED=1), the interrupt request is generated. 302 CHAPTER 16 8-/16-BIT PPG TIMER ● Output waveform in 8-bit PPG output 2-channel independent operation mode The High and Low pulse widths to be outputted are determined by adding 1 to the value in the PPG reload register and multiplying it by the count clock cycle. For example, if the value in the PPG reload register is "00H", the pulse width has one count clock cycle, and if the value is "FFH", the pulse width has 256 count clock cycles. The equations for calculating the pulse width are shown below: PL=T × (L+1) PH=T × (H+1) PL: Low width of output pulse PH: High width of output pulse L: Values of 8 bits in PPG reload register (PRLLn or PRLLm) H: Values of 8 bits in PPG reload register (PRLHn or PRLHm) T: Count clock cycle Figure 16.5-3 shows the output waveform in the 8-bit PPG output 2-channel independent operation mode. Figure 16.5-3 Output Waveform in 8-bit PPG Output 2-channel Independent Operation Mode Operating start Operating stop PPG operating enable bit (PEN) PPG output pin T × (L + 1) T × (H + 1) L : Value of PPG reload register (PRLL) H : Value of PPG reload register (PRLH) T : Count clock cycle Note: n = C, E m=n+1 303 CHAPTER 16 8-/16-BIT PPG TIMER 16.5.2 16-bit PPG Output Operation Mode In the 16-bit PPG output operation mode, the 8-/16-bit PPG timer is set as a 16-bit PPG timer with one channel. ■ Setting for 16-bit PPG Output Operation Mode Operating the 8-/16-bit PPG timer in the 16-bit PPG output operation mode requires the setting shown in Figure 16.5-4 . Figure 16.5-4 Setting for 16-bit PPG Output Operation Mode bit15 14 PPGCm/PPGCn PEN1 1 − 13 12 11 10 9 PE1 PIE1 PUF1 MD1 MD0 1 bit8 bit7 Reserved PEN0 1 1 6 − 5 4 3 PE0 PIE0 PUF0 2 − 1 bit0 − Reserved 1 1 PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 − REV PPGnm (Reserved area) PRLHn/PRLLn PPGn set high level side reload values of lower 8 bits. PPGn set low level side reload values of lower 8 bits. PRLHm/PRLLm PPGm set high level side reload values of upper 8 bits. PPGm set low level side reload values of upper 8 bits. : Used bit ✕ : Unused bit - : Undefined bit 1 : Set 1 0 : Set 0 Note: n = C, E m=n+1 Note: Use a long-word instruction to set the values in the PPG reload registers or a word instruction to set the PPGn and PPGm (PRLLn --> PRLLm or PRLHn --> PRLHm) in this order. 304 CHAPTER 16 8-/16-BIT PPG TIMER ● Operation in 16-bit PPG output operation mode • When either PPGn pin output or PPGm pin output is enabled (PPGCn:PEC=1, PPGCm: PED=1), the same pulse wave is outputted from both the PPGn and PPGm pins. • When the reload value is set in the PPG reload registers (PRLLn/PRLHn, PRLLm/PRLHm) to enable operation of the PPG timer (PPGCn:PENC=1 and PPGCm: PEND=1), the PPG down counters start counting as 16-bit down counters (PCNTn + PCNTm). • To stop the count operation of the PPG down counters, disable the operation of the PPG timers of both channels (PPGCn: PENC=0 and PPGCm: PEND=0). The count operation of the PPG down counters is stopped and the output of the PPG output pin is held at a Low level. • If the PPGm down counter underflows, the reload values set in the PPGn and PPGm reload registers (PRLLn/PRLHn, PRLLm/PRLHm) are reloaded simultaneously to the PPG down counters (PCNTn + PCNTm). • When an underflow occurs, the underflow generation flag bits in both channels are set simultaneously (PPGCn:PUFC=1, PPGCm:PUFD=1). If an interrupt request is enabled at either channel (PPGCn: PIEC=1, PPGCm: PIED=1), an interrupt request is generated. Notes: • In the 16-bit PPG output operation mode, the underflow generation flag bits in the two channels are set simultaneously when an underflow occurs (PPGCn: PUFC=1 and PPGCm: PUFD=1). To prevent duplication of interrupt requests, disable either of the underflow interrupt enable bits in the two channels (PPGCn:PIEC=0, PPGCm:PIED=1 or PPGCn:PIEC=1, PPGCm:PIED=0). • If the underflow generation flag bits in the two channels are set (PPGCn: PUFC=0 and PPGCm: PUFD=0), clear the two channels at the same time. Note: n = C, E m = n+1 305 CHAPTER 16 8-/16-BIT PPG TIMER ● Output waveform in 16-bit PPG output operation mode The High and Low pulse widths to be outputted are determined by adding 1 to the value in the PPG reload register and multiplying it by the count clock cycle. For example, if the value in the PPG reload register is "0000H", the pulse width has one count clock cycle, and if the value is "FFFFH", the pulse width has 65,536 count clock cycles. The equations for calculating the pulse width are shown below: PL=T × (L+1) PH=T × (H+1) PL: Low width of output pulse PH: High width of output pulse L: Values of 16 bits in PPG reload register (PRLLn+PRLLm) H: Values of 16 bits in PPG reload register (PRLHn+PRLHm) T: Count clock cycle Figure 16.5-5 shows the output waveform in the 16-bit PPG output operation mode. Figure 16.5-5 Output Waveform in 16-bit PPG Output Operation Mode Operation start Operation stop PPG operation enable bit (PEN) PPG output pin T × (L + 1) T × (H + 1) L : Values of 16 bits in PPG reload register (PRLLm + PRLLn) H : Values of 16 bits in PPG reload register (PRLHm + PRLHn) T : Count clock cycle Note: n = C, E m=n+1 306 CHAPTER 16 8-/16-BIT PPG TIMER 16.5.3 8+8-bit PPG Output Operation Mode In the 8 + 8-bit PPG output operation mode, the 8-/16-bit PPG timer is set as an 8-bit PPG timer. The PPGC operates as an 8-bit prescaler and the PPG operates using the PPG output of the PPGC as a clock source. ■ Setting for 8+8-bit PPG Output Operation Mode Operating the 8-/16-bit PPG timer in the 8+8-bit PPG output operation mode requires the setting shown in Figure 16.5-6 . Figure 16.5-6 Setting for 8+8-bit PPG Output Operation Mode bit15 14 PPGCm/PPGCn PEN1 1 − 13 12 11 10 9 PE1 PIE1 PUF1 MD1 MD0 0 1 bit8 bit7 Reserved PEN0 1 1 6 − 5 4 3 PE0 PIE0 PUF0 2 − 1 bit0 − Reserved 1 PPGnm (Reserved area) PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 − REV PRLHn/PRLLn PPGn set High level side reload values. PPGn set Low level side reload values. PRLHm/PRLLm PPGm set High level side reload values. PPGm set Low level side reload values. : Used bit ✕ : Unused bit - : Undefined bit 1 : Set 1 0 : Set 0 Note: n = C, E m=n+1 Note: Use the word instruction to set both High-level and Low-level PPG reload registers (PRLLn/PRLHn, PRLLm/PRLHm) at the same time. 307 CHAPTER 16 8-/16-BIT PPG TIMER ● Operation in 8+8-bit PPG output operation mode • The PPGn operates as the prescaler of the PPGm timer and the PPGm operates using the PPGn output as a clock source. • When the pin output is enabled (PPGCn: PE0=1, PPGCm: PE1=1) if PPG output pin selection is set to standard (PPGnm:REV=0), PPGn pulse wave is outputted from the PPGn pin and the PPGm pulse wave is outputted from the PPGm pin. When the PPG output pin is switched (PPGnm:REV=1), the output pins PPGn and PPGm are switched. • When the reload value is set in the PPG reload registers (PRLLn/PRLHn, PRLLm/PRLHm) to enable operation of the PPG timer (PPGCn:PEN0=1 and PPGCm: PEN1=1), the PPG down counter starts counting. • To stop the count operation of the PPG down counters, disable the operation of the PPG timers of both channels (PPGCn: PEN0=0 and PPGCm: PEN1=0). The count operation of the PPG down counters is stopped and the output of the PPG output pin is held at a Low level. • If the PPG down counter of each channel underflows, the reload values set in the PPG reload registers (PRLLn/PRLHn, PRLLm/PRLHm) are reloaded to the PPG down counter that underflows. • When an underflow occurs, the underflow generation flag bit in the channel that causes an underflow (PPGCn:PUF0=1, PPGCm:PUF1=1) is set. If an interrupt request is enabled at the channel that causes an underflow (PPGCn: PIE0=1, PPGCm: PIE1=1), an interrupt request is generated. Notes: • Do not operate PPGm (PPGCm:PEN1 = 1) when PPGn is stopped (PPGCn:PEN0 = 0). • It is recommended to set the same value in both Low-level and High-level PPG reload registers (PRLLn/ PRLHn, PRLLm/PRLHm). Note: n = C, E m = n+1 308 CHAPTER 16 8-/16-BIT PPG TIMER ● Output waveform in 8+8-bit PPG output operation mode The High and Low pulse widths to be outputted are determined by adding 1 to the value in the PPG reload register and multiplying it by the count clock cycle. The equations for calculating the pulse width are shown below: PL=T × (Ln+1) × (Lm+1) PH=T × (Hn+1) × (Hm+1) PL: Low width of output pulse of PPGm pin PH: High width of output pulse of PPGm pin Ln: Values of 8 bits in PPG reload register (PRLLn) Hn: Values of 8 bits in PPG reload register (PRLHn) Lm: Values of 8 bits in PPG reload register (PRLLm) Hm: Values of 8 bits in PPG reload register (PRLHm) T: Count clock cycle Figure 16.5-7 shows the output waveform in the 8+8-bit PPG output operation mode. Figure 16.5-7 Output Waveform in 8+8-bit PPG Output Operation Mode Operation start Operation stop PPG operation enable bit (PENn, PENm) T × (L0 + 1) T × (H0 + 1) PPGn output pin PPGm output pin T × (L0 + 1) × (L1+ 1) Ln Hn Hm Lm T T × (H0 + 1) × (H1 + 1) : Values of 8 bits in PPG reload register (PRLLn) : Values of 8 bits in PPG reload register (PRLHn) : Values of 8 bits in PPG reload register (PRLLm) : Values of 8 bits in PPG reload register (PRLHm) : Count clock cycle Note: n = C, E m=n+1 309 CHAPTER 16 8-/16-BIT PPG TIMER 16.6 Precautions when Using 8-/16-bit PPG Timer This section explains the precautions when using the 8-/16-bit PPG timer. ■ Precautions when Using 8-/16-bit PPG Timer ● Effect on 8-/16-bit PPG timer when using timebase timer output • If the output signal of the timebase timer is used as the input signal for the count clock of the 8-/16-bit PPG timer (PPGnm: PCM2 to PCM0="111B", PCS2 to PCS0="111B"), deviation may occur in the first count cycle in which the PPG timer is started by trigger input or in the count cycle immediately after the PPG timer is stopped. • When the timebase timer counter is cleared (TBTC: TBR=0) during the count operation of the PPG down counter, deviation may occur in the count cycle. ● Setting of PPG reload registers when using 8-bit PPG timer • The Low-level and High-level pulse widths are determined at the timing of reloading the values in the Low-level PPG reload registers (PRLLn, PRLLm) to the PPG down counter. • If the 8-bit PPG timer is used in the 8-bit PPG output 2-channel independent operation mode or the 8 + 8-bit PPG output operation mode, use a word instruction to set both High-level and Low-level PPG reload registers (PRLLn/PRLHn, PRLLm/PRLHm) at the same time. Using a byte instruction may cause an unexpected pulse to be generated. [Example of rewriting PPG reload registers using byte instruction] Immediately before the signal level of the PPG pin switches from High to Low, if the value in the Highlevel PPG reload register (PRLH) is rewritten after the value in the Low-level PPG reload register (PRLL) is rewritten using the byte instruction, a Low-level pulse width is generated after rewriting and a High-level pulse width is generated before rewriting. Figure 16.6-1 shows the waveform as the values in the PPG reload registers are rewritten using the byte instruction. Note: n = C, E m = n+1 310 CHAPTER 16 8-/16-BIT PPG TIMER Figure 16.6-1 Waveform when Values in PPG Reload Registers Rewritten Using Byte Instruction PRLL A PRLH B C D A+B A+B B+C C+D B B C+D C+D D D Timing of updating reload value PPG pin A B A C C C <1> <2> <1>: Change the value (A → C) of PPG reload register (PRLL) <2>: Change the value (B → D) of PPG reload register (PRLH) ● Setting of PPG reload registers when using 16-bit PPG timer Use a long-word instruction to set the PPG reload registers (PRLLn/PRLHn, PRLLm/PRLHm) or a word instruction to set the word instruction to set the PPGn and PPGm (PRLLn --> PRLLn or PRLHm --> PRLHm) in this order. [Reload timing in 16-bit PPG output operation mode] In the 16-bit PPG output operation mode, the reload values written to the PPGn reload registers (PRLLn, PRLHn) are written temporarily to the temporary latch, written to the PPGm reload registers (PRLLm/ PRLHm), and then transferred to the PPGn reload registers (PRLLn/PRLHn). Therefore, when setting the reload value in the PPGm reload registers (PRLLm/PRLHm), it is necessary to set the reload value in the PPGn reload registers (PRLLn/PRLHn) simultaneously or set the reload value in the PPGn reload registers (PRLLn/PRLHn) before setting it in the PPGm reload registers (PRLLm/PRLHm). Figure 16.6-2 shows the reload timing in the 16-bit PPG output operation mode. 311 CHAPTER 16 8-/16-BIT PPG TIMER Figure 16.6-2 Reload Timing in 16-bit PPG Output Operation Mode Reload value of PPGn Write to PPGn except 16-bit PPG output operation mode Only 16-bit PPG output operation mode Temporary latch Reload value of PPGm Write to PPGm Transfers synchronously with writing to PPGm PPG reload register (PRLLn, PRLHn) Note: n = C, E m = n+1 312 PPG reload register (PRLLm, PRLHm) CHAPTER 17 DTP/EXTERNAL INTERRUPTS This chapter explains the functions and operations of DTP/external interrupt. 17.1 Overview of DTP/External Interrupt 17.2 Block Diagram of DTP/External Interrupt 17.3 Configuration of DTP/External Interrupt 17.4 Explanation of Operation of DTP/External Interrupt 17.5 Precautions when Using DTP/External Interrupt 17.6 Program Example of DTP/External Interrupt Function 313 CHAPTER 17 DTP/EXTERNAL INTERRUPTS 17.1 Overview of DTP/External Interrupt The DTP/external interrupt sends interrupt requests from external peripheral devices or data transfer requests to the CPU to generate an external interrupt request, or starts the EI2OS. ■ DTP/External Interrupt Function The DTP/external interrupt follows the same procedure as resource interrupts to send interrupt requests from external peripheral devices to the CPU to generate an external interrupt request, or starts the EI2OS. If the EI2OS is disabled in the interrupt control register (ICR: ISE=0), the external interrupt function is enabled, branching to interrupt processing. If the EI2OS is enabled, the DTP function is enabled and automatic data transfer is performed, branching to interrupt processing after the completion of data transfer for the specified number of times. Table 17.1-1 shows an overview of the DTP/external interrupt. Table 17.1-1 Overview of DTP/External Interrupt External Interrupt Input pin DTP Function 8 pins : INT8, INT9R, INT10, INT11, INT12R, INT13, INT14R, INT15R The interrupt factor is set in unit of pins using the detection level setting registers (ELVR1). Interrupt factor Input of High level, Low level, rising edge, or falling edge 314 Input of High level or Low level Interrupt number #26(1AH), #28(1CH) Interrupt control The interrupt request output is enabled/disabled using the DTP/external interrupt enable register (ENIR1). Interrupt flag The interrupt factor is held using the DTP/external interrupt factor register (EIRR1). Processing selection The EI2OS is disabled. (ICR: ISE=0) The EI2OS is enabled. (ICR: ISE=1) Processing contents A branch is caused to the external interrupt processing routine. EI2OS performs automatic data transfer and completes the specified number of time for data transfers, causing a branch to the interrupt processing. CHAPTER 17 DTP/EXTERNAL INTERRUPTS 17.2 Block Diagram of DTP/External Interrupt The block diagram of the DTP/external interrupt is shown below. ■ Block Diagram of DTP/External Interrupt Figure 17.2-1 Block Diagram of DTP/External Interrupt Detection level setting register (ELVR1) LB15 LA15 LB14 LA14 LB13 LA13 LB12 LA12 Pin Level edge selector INT15R Internal data bus Pin Level edge selector Level edge selector Pin Level edge selector INT10 Level edge selector INT13 Pin Pin INT11 INT14R Pin LB11 LA11 LB10 LA10 LB9 LA9 LB8 LA8 Pin Level edge selector INT9R Level edge selector INT12R Pin Level edge selector INT8 DTP/external interrupt input detection circuit ER15 ER14 ER13 ER12 ER11 ER10 ER9 ER8 DTP/external interrupt factor register (EIRR1) Interrupt request signal Interrupt request signal EN15 EN14 EN13 EN12 EN11 EN10 EN9 EN8 DTP/external interrupt enable register (ENIR1) 315 CHAPTER 17 DTP/EXTERNAL INTERRUPTS ● DTP/external interrupt input detection circuit This circuit detects interrupt requests or data transfer requests generated from external peripheral devices. The interrupt request flag bit corresponding to the pin whose level or edge set by the detection level setting register (ELVR) is detected is set to "1" (EIRR1:ER). ● Detection level setting register (ELVR1) This register sets the level or edge of input signals from external peripheral devices that cause DTP/external interrupt factors. ● DTP/external interrupt factor register (EIRR1) This register holds DTP/external interrupt factors. If an enable signal is inputted to the DTP/external interrupt pin, the corresponding DTP/external interrupt request flag bit is set to "1". ● DTP/external interrupt enable register (ENIR1) This register enables or disables DTP/external interrupt requests from external peripheral devices. ■ Details of Pins and Interrupt Numbers Table 17.2-1 shows the pins and interrupt numbers used in the DTP/external interrupt. Table 17.2-1 Pins and Interrupt Numbers Used by DTP/External Interrupt Pin Channel P54 INT8 P42 INT9R P55 INT10 P56 INT11 P80 INT12R P57 INT13 P82 INT14R P84 INT15R Interrupt number #26(1AH) #28(1CH) INT9R, INT12R, INT14R, and INT15R are enabled by setting the corresponding bit of the external interrupt factor select register (EISSR) to "1". 316 CHAPTER 17 DTP/EXTERNAL INTERRUPTS 17.3 Configuration of DTP/External Interrupt This section lists and details the pins, interrupt factors, and registers in the DTP/ external interrupt. ■ Pins of DTP/External Interrupt The pins used by the DTP/external interrupt serve as general-purpose I/O ports. Table 17.3-1 lists the pin functions and the pin setting required for use in the DTP/external interrupt. Table 17.3-1 Pins of DTP/External Interrupt Pin Name P54/AN12/TOT3 /INT8 Pin Function General-purpose I/O ports, analog input, event pin for reload timer, DTP external interrupt inputs P55/AN13/INT10 P56/AN14/INT11 General-purpose I/O ports, analog input, DTP external interrupt inputs Pin Settings Required for Use in DTP/ External Interrupt • Set external interrupt factor select register (EISSR) to 0. • Set as input ports in port direction register (DDR5). P57/AN15/INT13 P42/ INT9R/ RX1/ General-purpose I/O ports, DTP external interrupt inputs, CAN1 input Rx1 P80/ INT12R/ ADTG General-purpose I/O ports, DTP external interrupt inputs, A/D converter trigger input ADTG P82/ INT14R/ SIN0/ TIN2 General-purpose I/O ports, DTP external interrupt inputs, UART0 input SIN0, reload timer 2 trigger input TIN2 P84/ INT15R/ SCK0 General-purpose I/O ports, DTP external interrupt inputs, UART0 clock I/O SCK0 • Set external interrupt factor select register (EISSR) to 1. • Set as input ports in port direction register (DDR4). • Set external interrupt factor select register (EISSR) to 1. • Set as input ports in port direction register (DDR8). 317 CHAPTER 17 DTP/EXTERNAL INTERRUPTS ■ List of Registers and Reset Values in DTP/External Interrupt Figure 17.3-1 List of Registers and Reset Values in DTP/External Interrupt Reset value ENIR1 bit Address: 0000CA H bit EIRR1 Address: 0000CB H ELVR1 bit Address: 0000CC H ELVR1 bit Address: 0000CD H EISSR bit 7 6 5 4 3 EN15 EN14 EN13 EN12 EN11 15 14 13 ER15 ER14 ER13 12 11 ER12 ER11 2 1 0 EN10 EN9 EN8 9 8 ER9 ER8 10 ER10 7 6 5 4 3 2 1 LB11 LA11 LB10 LA10 LB9 LA9 LB8 LA8 15 14 13 12 11 10 9 8 LB14 LA14 LB13 LA13 LB15 LA15 7 6 5 4 3 2 Address: 0000CE H INT15R INT14R INT13R INT12R INT11R INT10R 318 XXXXXXXX B 0 LB12 LA12 1 00000000 B 00000000 B 00000000 B 0 INT9R INT8R 00000000 B CHAPTER 17 DTP/EXTERNAL INTERRUPTS 17.3.1 DTP/External Interrupt Factor Register (EIRR1) The DTP/external interrupt factor register holds DTP/external interrupt factors. When a valid signal is inputted to the DTP/external interrupt pin, the corresponding DTP/external interrupt request flag bit is set to "1". The EIRR1 register is corresponding to INT8, INT9R, INT10, INT11, INT12R, INT13, INT14R, and INT15R. ■ DTP/External Interrupt Factor Register (EIRR1) Figure 17.3-2 DTP/External Interrupt Factor Register (EIRR1) EIRR1 15 14 13 12 11 10 9 8 Address 0000CBH ER15 ER14 ER13 ER12 ER11 ER10 ER9 ER8 R/W R/W R/W R/W R/W R/W R/W R/W Reset value XXXXXXXX B bit15 to bit8 ER15 to ER8 R/W : Read/Write : Undefined X 0 1 DTP/external interrupt request flag bit Read Write No DTP/external interrupt input Clear of ER bit No effect DTP/external interrupt input 319 CHAPTER 17 DTP/EXTERNAL INTERRUPTS Table 17.3-2 Function of DTP/External Interrupt Factor Register (EIRR1) Bit Name bit8 to bit15 320 ER15 to ER8(EIRR1), DTP/External interrupt request flag bits Function These bits are set to "1" when the edges or level signals set by the detection condition select bits in the detection level setting register (ELVR1:LB, LA) are inputted to the DTP/external interrupt pins. When set to "1": When the DTP/external interrupt request enable bit (ENIR1:EN) is set to "1", an interrupt request is generated to the corresponding DTP/external interrupt channel. When set to "0": Cleared When set to "1": No effect Note: Reading by read-modify-write type instructions always returns "1". If more than one DTP/external interrupt request is enabled (ENIR1:EN = 1), clear only the bit in the channel that accepts an interrupt (EIRR1:ER = 0). No other bits must be cleared unconditionally. Reference: When the EI2OS is started, the interrupt request flag bit is automatically cleared after the completion of data transfer (EIRR1:ER = 0). CHAPTER 17 DTP/EXTERNAL INTERRUPTS 17.3.2 DTP/External Interrupt Enable Register (ENIR1) The DTP/external interrupt enable register (ENIR1) enables/disables the DTP/external interrupt request in the external peripheral devices. ENIR1 is corresponding to INT8, INT9R, INT10, INT11, INT12R, INT13, INT14R and INT15R. ■ DTP/External Interrupt Enable Register (ENIR1) Figure 17.3-3 DTP/External Interrupt Enable Register (ENIR1) 7 6 5 4 3 2 1 0 Address ENIR1: 0000CAH EN15 EN14 EN13 EN12 EN11 EN10 EN9 EN8 R/W R/W R/W R/W R/W R/W R/W R/W Reset value: 00000000B bit7 to bit0 EN15 to EN8 DTP/external interrupt request enable bit 0 1 R/W : Read/Write : Reset value DTP/external interrupt disable DTP/external interrupt enable Table 17.3-3 Functions of DTP/External Interrupt Enable Register (ENIR1) Bit Name bit0 to bit7 EN15 to EN8(ENIR1), DTP/external interrupt request enable bits Function These bits enable or disable the DTP/external interrupt request to the DTP/external interrupt channel. If the DTP/external interrupt request enable bit (ENIR1:EN) and the DTP/external interrupt request flag bit (EIRR1:ER) are set to "1", the interrupt request is generated to the corresponding DTP/ external interrupt pin. Reference: The state of the DTP/external interrupt pin can be read directly using the port data register irrespective of the setting of the DTP/external interrupt request enable bit. 321 CHAPTER 17 DTP/EXTERNAL INTERRUPTS Table 17.3-4 Correspondence between DTP/External Interrupt Pins, DTP/External Interrupt Request Flag Bits, and DTP/External Interrupt Request Enable Bits 322 DTP/external interrupt pin DTP/external interrupt request flag bit DTP/external interrupt request enable bit INT8 ER8 EN8 INT9R ER9 EN9 INT10 ER10 EN10 INT11 ER11 EN11 INT12R ER12 EN12 INT13 ER13 EN13 INT14R ER14 EN14 INT15R ER15 EN15 CHAPTER 17 DTP/EXTERNAL INTERRUPTS 17.3.3 Detection Level Setting Register (ELVR1) The detection level setting register sets the level or edge of input signals that cause the interrupt factors of the DTP/external interrupt pin. ELVR1 is corresponding to INT8, INT9R, INT10, INT11, INT12R, INT13, INT14R and INT15R. ■ Detection Level Setting Register (ELVR1) Figure 17.3-4 Detection Level Setting Register (ELVR1) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset value Address ELVR1:0000CC B LB15 LA15 LB14 LA14 LB13 LA13 LB12 LA12 LB11 LA11 LB10 LA10 LB9 LA9 LB8 LA8 0000000000000000B R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W bit15 to bit0 LB15,LA15,LB14,LA14, LB13,LA13,LB12,LA12, LB11,LA11,LB10,LA10, LB9 ,LA9 ,LB8 ,LA8 0 0 0 1 1 0 1 1 R/W : Read/Write : Reset value Detection condition select bit Low level detection High level detection Rising edge detection Falling edge detection Table 17.3-5 Functions of Detection Level Setting Register (ELVR1) Bit Name bit15 to bit0 ELVR1 ... LB15, LA15 to LB8, LA8 Detection condition select bits Function These bits set the levels or edges of input signals from external peripheral devices that cause interrupt factors in the DTP/external interrupt pins. • Two levels or two edges are selectable for external interrupts, and two levels are selectable for the EI2OS. Reference: When the set detection signal is input to the DTP/external interrupt pins, the DTP/external interrupt request flag bits are set to "1" even if DTP/external interrupt requests are disabled (ENIR1:EN = 0). 323 CHAPTER 17 DTP/EXTERNAL INTERRUPTS Table 17.3-6 Correspondence between Detection Level Setting Register and Channels DTP/External Interrupt Pin Register Name Bit Name INT8 LB8, LA8 INT9R LB9, LA9 INT10 LB10, LA10 INT11 LB11, LA11 ELVR1 324 INT12R LB12, LA12 INT13 LB13, LA13 INT14R LB14, LA14 INT15R LB15, LA15 CHAPTER 17 DTP/EXTERNAL INTERRUPTS 17.3.4 External Interrupt Factor Select Register (EISSR) The external interrupt factor select register (EISSR) can change the assignment of the external interrupt pin. This allows the external interrupt. Also, the function such as CAN wakeup is implemented. ■ Selection of External Interrupt Factor The external interrupt pin of the upper 8-bit is assigned to INT13, INT11, INT10, and INT8 normally and shares the port 5 and pin. In the external bus mode, the port 0 cannot be used as the external interrupt pin. The pin is switched by the external interrupt factor select register (EISSR). In addition, because INT15R, INT14R, INT12R, and INT9R share the function such as CAN input pin, the function such as CAN wakeup can be implemented. See Table 17.3-8 for the pin function of INT15R, INT14R, INT12R, and INT9R. Figure 17.3-5 DTP/external Interrupt Factor Select Register (EISSR) Address EISSR: 0000CEH 7 6 5 4 3 2 1 0 INT15R INT14RINT13R INT12R INT11RINT10R INT9R INT8R Reset value 00000000B R/W R/W R/W R/W R/W R/W R/W R/W R/W : Read/Write : Undefined X : Reset value bit7 to bit0 INT15R to INT8R 0 1 External interrupt factor select bit Set pins INT15 to INT8 as external interrupt factor Set pins INT15R to INT8R as external interrupt factor * See Table 17.3-8 "External interrupt factor select (upper 8-bit)" for the pin assignment of INT15R to INT8R. Table 17.3-7 Function of DTP/external Interrupt Factor Select Register (EISSR) Bit Name bit7 to bit0 INT15R to INT8R: External interrupt factor select bits Function When these bits are set to "1", the input pin of the corresponding external interrupt factor (upper 8-bit) is assigned to the INT15R to INT8R. When set to "0" : The external interrupt factor of the upper 8-bit is assigned to INT15 to INT8 pins. When set to "1": The external interrupt factor of the upper 8-bit is assigned to the INT15R to INT8R pins. 325 CHAPTER 17 DTP/EXTERNAL INTERRUPTS Table 17.3-8 External Interrupt Factor Select (Upper 8-bit) EISSR Bit INT8R INT9R 326 "0" (Initial Value) "1" INT8: P54 (AN12/TOT3) - INT9R: P42 (RX1) INT10R INT10: P55 (AN13) - INT11R INT11: P56 (AN14) - INT12R - INT13R INT13: P57 (AN15) INT14R - INT14R: P82 (SIN0/TIN2) INT15R - INT15R: P84 (SCK0) INT12R: P80 (ADTG) - CHAPTER 17 DTP/EXTERNAL INTERRUPTS 17.4 Explanation of Operation of DTP/External Interrupt The DTP/external interrupt has an external interrupt function and a DTP function. The setting and operation of each function are explained. ■ Setting of DTP/External Interrupt Using the DTP/external interrupt requires, the setting shown in Figure 17.4-1 . Figure 17.4-1 Setting of DTP/External Interrupt bit15 14 ICR interrupt control register At DTP 13 12 11 10 9 bit8 bit7 6 5 4 3 2 1 bit0 ICS3 ICS2 ICS1 ICS0 ISE IL2 IL1 IL0 ICS3 ICS2 ICS1 ICS0 ISE IL2 IL1 IL0 1 (EI2OS) 1 ENIR1 EN15 EN14 EN13 EN12 EN11 EN10 EN9 EN8 EIRR1 ER15 ER14 ER13 ER12 ER11 ER10 ER9 ER8 ELVR1 LB15 LA15 LB14 LA14 LB13 LA13 LB12 LA12 LB11 LA11 LB10 LA10 LB9 LA9 LB8 LA8 DDR port direction register Set the bit corresponding to pin used for DTP/external interrupt input to 0. ADER5 (Analog input enable) only using INT8,10,11,13E TMCSR3 (timer control) ADE15 ADE14 ADE13 ADE12 ADE11 ADE10 ADE9 ADE8 − − − − At using INT8R CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE UF CNTE TRG 0 − : Unused bit : Used bit : Set the bit corresponding to used pin to 1 : Set the bit corresponding to used pin to 0 0 : Set 0 1 : Set 1 327 CHAPTER 17 DTP/EXTERNAL INTERRUPTS ● Setting procedure To use the DTP/external interrupt, set each register by using the following procedure: 1. Set the input port to the general-purpose I/O port, which is shared with the terminal to be used as external interrupt input. 2. Set the external interrupt factor select register (EISSR) corresponding to the DTP/external interrupt channel to be used. 3. Set the interrupt request enable bit corresponding to the DTP/external interrupt channel to be used to 0 (ENIR1:EN). 4. Use the detection condition select bit corresponding to the DTP/external interrupt pin to be used to set the edge or level to be detected (ELVR1: LA, LB). 5. Set the interrupt request flag bit corresponding to the DTP/external interrupt channel to be used to 0 (EIRR1: ER). 6. Set the interrupt request enable bit corresponding to the DTP/external interrupt channel to be used to 1 (ENIR1: EN). Note that concurrent writing with 16-bit data is available in 5 and 6. • When setting the registers for the DTP/external interrupt, the external interrupt request must be disabled in advance (ENIR1: EN = 0). • When enabling the DTP/external interrupt request (ENIR1:EN = 1), the corresponding DTP/external interrupt request flag bit must be cleared in advance (EIRR1:ER = 0). These actions prevent the mistaken interrupt request from occurring when setting the register. ● Selecting of DTP or external interrupt function Whether the DTP function or the external interrupt function is executed depends on the setting of the EI2OS enable bit in the corresponding interrupt control register (ICR:ISE). If the ISE bit is set to "1", the EI2OS is enabled. If the ISE bit is set to "0", the EI2OS is disabled and the external interrupt function is executed. Notes: • All interrupt requests assigned to one interrupt control register have the same interrupt levels (IL2 to IL0). • If two or more interrupt requests are assigned to one interrupt control register and the EI2OS is used in one of them, other interrupt requests cannot be used. • Enabling unequipped terminals causes a false operation. First set the EISSR and then set each of the registers when DTP/external interrupt is used. 328 CHAPTER 17 DTP/EXTERNAL INTERRUPTS ■ DTP/External Interrupt Operation The control bits and the interrupt factors for the DTP/external interrupt are shown in Table 17.4-1 . Table 17.4-1 Control Bits and Interrupt Factors for DTP/External Interrupt DTP/External interrupt Interrupt request flag bit EIRR1: ER15 to ER8 Interrupt request enable bit ENIR1: EN15 to EN8 Interrupt factor Input of valid edge or level to INT13, INT11, INT10, INT8 , INT9R, INT12R, INT14R, INT15R pins If the interrupt request signal from the DTP/external interrupt is output to the interrupt controller and the EI2OS enable bit in the interrupt control register (ICR:ISE) is set to "0", the interrupt processing is executed. This bit is set to "1", the EI2OS is executed. Figure 17.4-2 shows the operation of the DTP/external interrupt. 329 CHAPTER 17 DTP/EXTERNAL INTERRUPTS Figure 17.4-2 Operation of DTP/External Interrupt DTP/external interrupt circuit Other request ELVR1 CPU Interrupt controller ICR YY EIRR1 IL CMP CMP ICR XX ENIR1 ILM Interrupt processing Factor DTP/external interrupt request generating Interrupt controller reception judge CPU interrupt reception judge Interrupt processing microprogram starting EI2OS starting Memory Peripheral data transfer 1 ICR:ISE 0 Renewal of descriptor External interrupt starting Descriptor data counter Processing and interrupt flag clear Recovery from external interrupt 330 =0 Interrupt processing 0 Reset or stop Recovery from DTP processing Recovery from EI2OS processing (DTP processing) CHAPTER 17 DTP/EXTERNAL INTERRUPTS 17.4.1 External Interrupt Function The DTP/external interrupt has an external interrupt function for generating an interrupt request by detecting the signal (edge or level) in the DTP/external interrupt pin. ■ External Interrupt Function • When the signal (edge or level) set in the detection level setting register is detected in the DTP/external interrupt pin, the interrupt request flag bit in the DTP/external interrupt factor register (EIRR1:ER) is set to "1". • If the interrupt request enable bit in the DTP/external interrupt enable register is enabled (ENIR1:EN = 1) with the interrupt request flag bit set to "1", the interrupt request generation is posted to the interrupt controller. • If an interrupt request is preferred to other interrupt request by the interrupt controller, the interrupt request is generated. • If the level of an interrupt request (ICR:IL) is higher than that of the interrupt level mask bit in the condition code register (CCR:ILM) and the interrupt enable bit is enabled (PS:CCR:I = 1), the CPU performs interrupt processing after completion of the current instruction execution and branches to interrupt processing. • At interrupt processing, set the corresponding DTP/external interrupt request flag bit to 0 and clear the DTP/external interrupt request. Notes: • When the DTP/external interrupt start factor is generated, the DTP/external interrupt request flag bit (EIRR1:ER) is set to "1", regardless of the setting of the DTP/external interrupt request enable bit (ENIR1:EN). • When the interrupt processing is started, clear the DTP/external interrupt request flag bit that caused the start factor. Control cannot be returned from the interrupt while the DTP/external interrupt request flag bit is set to "1". When clearing, do not clear any flag bit other than the accepted DTP/external interrupt factor. 331 CHAPTER 17 DTP/EXTERNAL INTERRUPTS 17.4.2 DTP Function The DTP/external interrupt has the DTP function that detects the signal of the external peripheral device from the DTP/external interrupt pin to start the EI2OS. ■ DTP Function The DTP function detects the signal level set by the detection level setting register of the DTP/external interrupt function to start the EI2OS. • When the EI2OS operation is already enabled (ICR:ISE = 1) at the point when the interrupt request is accepted by the CPU, the DTP function starts the EI2OS and starts data transfer. • When transfer of one data item is completed, the descriptor is updated and the DTP/external interrupt request flag bit is cleared to prepare for the next request from the DTP/external interrupt pin. • When the EI2OS completes transfer of all the data, control branches to the interrupt processing. Figure 17.4-3 Example of Interface with External Peripheral Device (when using EI2OS in Single-chip mode) High level request (ELVR1: LB8, LA8=01B) Input to INT8 pin (DTP factor) CPU internal operation Descriptor select and read Peripheral device of external connection Data transfer request Descriptor renewal Internal data bus Read and write operation*2 DTP factor *1 Interrupt INT DTP/external request interrupt circuit CPU (EI2OS) *1: This must be cancelled within three machine clocks after the start of data transfer. *2: When EI2OS is "peripheral function" "internal memory transfer". 332 Internal memory CHAPTER 17 DTP/EXTERNAL INTERRUPTS 17.5 Precautions when Using DTP/External Interrupt This section explains the precautions when using the DTP/external interrupt. ■ Precautions when Using DTP/External Interrupt ● Condition of external-connected peripheral device when DTP function is used • When using the DTP function, the peripheral device must automatically clear a data transfer request when data transfer is performed. • Inactivate the transfer request signal within three machine clocks after starting data transfer. If the transfer request signal remains active, the DTP/external interrupt regards the transfer request signal as a generation of next transfer request. ● External interrupt input polarity • When the edge detection is set in the detection level setting register, the pulse width for edge detection must be at least three machine clocks. • When a level causing an interrupt factor is inputted with level detection set in the detection level setting register, factor F/F in the DTP/external interrupt factor register is set to "1" and the factor is held as shown in Figure 17.5-1 . With the factor held in factor F/F, the request to the interrupt controller remains active if the interrupt request is enabled (ENIR1: EN = 1) even after the DTP/external interrupt factor is cancelled. To cancel the request to the interrupt controller, clear the external interrupt request flag bit (EIRR1: ER) and clear the factor F/F as shown in Figure 17.5-2 . Figure 17.5-1 Clearing Factor Hold Circuit when Level Set DTP/external interrupt factor DTP/ interrupt input detection circuit Factor F/F (EIRR1 register) Enable gate To interrupt controller (interrupt request) The factor remains held unless cleared. Figure 17.5-2 DTP/External Interrupt Factor and Interrupt Request Generated when Interrupt Request Enabled DTP/external interrupt factor (when High level detected) Interrupt factor cancelled Interrupt request issued to interrupt controller The interrupt request is inactived by clearing the factor F/F. 333 CHAPTER 17 DTP/EXTERNAL INTERRUPTS ● Precautions on interrupts • When the DTP/external interrupt is used as the external interrupt function, no return from interrupt processing can be made with the DTP/external interrupt request flag bit set to "1" (EIRR1:ER) and the DTP/external interrupt request set to "enabled" (ENIR1:EN = 1). Always set the DTP/external interrupt request flag bit to 0 (EIRR1:ER) at interrupt processing. • When the level detection is set in the detection level setting register and the level that becomes the interrupt factor remains input, the DTP/external interrupt request flag bit is reset immediately even when cleared (EIRR1:ER = 0). Disable the DTP/external interrupt request output as needed (ENIR1:EN = 0), or cancel the interrupt factor itself. 334 CHAPTER 17 DTP/EXTERNAL INTERRUPTS 17.6 Program Example of DTP/External Interrupt Function This section gives a program example of the DTP/external interrupt function. ■ Program Example of DTP/External Interrupt Function ● Processing specifications An external interrupt is generated by detecting the rising edge of the pulse input to the INT8 pin. ● Coding example ICR07 DDR5 ENIR1 EQU EQU EQU 0000B7H 000015H 0000CAH ;Interrupt control register ICR7 ;Port 5 direction register ;DTP/external interrupt enable register 1 EIRR1 EQU 0000CBH ;DTP/external interrupt factor register 1 ELVR1L EQU 0000CCH ;Detection level setting register 1:"L" ELVR1H EQU 0000CDH ;Detection level setting register 1:"H" ADER5 EQU 00000BH ;Port5 analog input enable register ER8 EQU EIRR1:0 ;INT8 Interrupt request flag bit EN8 EQU ENIR1:0 ;INT8 Interrupt request enable bit ;---------Main program------------------------------------CODE CSEG START: ;Stack pointer (SP) already initialized MOV I:ADER5,#00000000B ;Set analog input of Port5 to disable MOV I:DDR5,#00000000B ;Set DDR5 to input port AND CCR,#0BFH ;Interrupts disabled MOV I:ICR07,#00H ;Interrupt level 0 (highest) CLRB I:EN8 ;INT8 disabled using ENIR1 MOV I:ELVR0L,#00000010B;Rising edge selected for INT8 CLRB I:ER0 ;INT8 interrupt flag cleared using ;EIRR1 SETB I:EN8 ;INT8 interrupt request enabled using ENIR1 MOV ILM,#07H ;Set ILM in PS to level 7 OR CCR,#40H ;Interrupts enabled LOOP: ÅE Processing by user ÅE BRA LOOP ;---------Interrupt program------------------------------------WARI: CLRB I:ER8 ;Interrupt request flag cleared 335 CHAPTER 17 DTP/EXTERNAL INTERRUPTS ÅE Processing by user ÅE RETI ;Return from interrupt processing CODE ENDS ;---------Vector setting-----------------------------------------VECT CSEG ABS=0FFH ORG 00FF94H ;Set vector to interrupt number #26(1AH) VECT DSL ORG DSL DB ENDS END WARI 00FFDCH START 00H ;Reset vector set ;Set to single-chip mode START ■ Program Example of DTP Function ● Processing specification • Channel 0 of the EI2OS is started by detecting the High level of the signal input to the INT8 pin. • RAM data is outputted to port 5 by performing DTP processing (EI2OS). ● Coding example 336 ICR07 EQU 0000B7H DDR6 DDR5 ENIR1 EQU EQU EQU 000016H 000015H 0000CAH EIRR1 EQU 0000CBH ELVR1L ELVR1H ADER5 ADER6 ER1 EN1 ; BAPL BAPM BAPH EQU EQU EQU EQU EQU EQU 0000CCH 0000CDH 00000BH 00000CH EIRR:0 ENIR:0 ;DTP/external interrupt control register ;Port 6 direction register ;Port 5 direction register ;DTP/external interrupt enable register 1 ;DTP/external interrupt factor register 1 ;Detection level setting register 1:"L" ;Detection level setting register 1:"H" ;Port5 analog input enable register ;Port6 analog input enable register ;INT8 interrupt request flag bit ;INT8 interrupt request enable bit EQU EQU EQU 000100H 000101H 000102H ;Buffer address pointer lower ;Buffer address pointer middle ;Buffer address pointer higher ISCS IOAL IOAH DCTL DCTH EQU EQU EQU EQU EQU 000103H 000104H 000105H 000106H 000107H ;EI2OS status register ;I/O address register lower ;I/O address register higher ;Data counter lower ;Data counter higher CHAPTER 17 DTP/EXTERNAL INTERRUPTS ; ;---------Main program------------------------------------CODE CSEG START: ;Stack pointer (SP) already initialized MOV I:ADER5,#00000000B ;Set analog input of port5 to disable MOV I:ADER6,#00000000B ;Set analog input of port6 to disable MOV I:DDR6,#11111111B ;Set DDR6 to output port MOV I:DDR5,#00000000B ;Set DDR5 to input port AND CCR,#0BFH ;Interrupts disabled MOV I:ICR07,#08H ;Interrupt level 0 (highest) EI2OS ;Channel 0 ;Data bank register (DTB) = 00H MOV BAPL,#00H ;Address for storing output data set MOV BAPM,#06H ;(600H to 60AH used) MOV MOV BAPH,#00H ISCS,#12H MOV MOV MOV MOV IOAL,#00H IOAH,#00H DCTL,#0AH DCTH,#00H CLRB MOV CLRB I:EN8 ;INT8 disabled using ENIR1 I:ELVR1L,#00000001B;H level detection set for INT8 I:ER8 ;INT8 interrupt request flag cleared ;using EIRR1 I:EN8 ;INT8 interrupt request enabled using ENIR1 ILM,#07H ;Set ILM in PS to level 7 CCR,#40H ;Interrupts enabled ;Byte transfer, buffer address +1, ;I/O address fixed, ;transfer from memory to I/O ;Set port 0 as transfer destination ;address pointer ;Set transfer count to 10 ; SETB MOV OR LOOP: ÅE Processing by user ÅE BRA LOOP ;---------Interrupt program------------------------------------WARI: CLRB I:ER8 ;INT8 interrupt request flag cleared ÅE Processing by user ÅE RETI ;Return from interrupt processing CODE ENDS ;---------Vector setting-----------------------------------------VECT CSEG ABS=0FFH ORG 00FF94H ;Set vector to interrupt number 337 CHAPTER 17 DTP/EXTERNAL INTERRUPTS #26(1AH) VECT 338 DSL ORG DSL DB ENDS END WARI 00FFDCH START 00H START ;Reset vector set ;Set to single-chip mode CHAPTER 18 8-/10-BIT A/D CONVERTER This chapter explains the functions and operation of 8-/ 10-bit A/D converter. 18.1 Overview of 8-/10-bit A/D Converter 18.2 Block Diagram of 8-/10-bit A/D Converter 18.3 Configuration of 8-/10-bit A/D Converter 18.4 Interrupt of 8-/10-bit A/D Converter 18.5 Explanation of Operation of 8-/10-bit A/D Converter 18.6 Precautions when Using 8-/10-bit A/D Converter 339 CHAPTER 18 8-/10-BIT A/D CONVERTER 18.1 Overview of 8-/10-bit A/D Converter The 8-/10-bit A/D converter converts the analog input voltage to a 8- or 10-bit digital value by using the RC sequential-comparison converter system. • An input signal can be selected from the input signals of the analog input pins for 16 channels. • The start trigger can be selected from a software trigger and an external trigger. ■ Function of 8-/10-bit A/D Converter The 8-/10-bit A/D converter converts the analog voltage (input voltage) input to the analog input pin into an 8- or 10-bit digital value (A/D conversion). The 8-/10-bit A/D converter has the following functions: • A/D conversion time is a minimum of 1.9 µs* per channel including sampling time. • Sampling time is a minimum of 0.5 µs* per channel. • RC sequential-comparison converter system with sample & hold circuit • Setting of 8-bit or 10-bit resolution enabled • Analog input pin can be used up to 16 channels. • Generates interrupt request by storing A/D conversion results in A/D data register • Starts EI2OS if interrupt request generated. Use of the EI2OS prevents data loss even at continuous A/D conversion. • Selects start trigger from software trigger and external trigger (falling edge) *: When the machine clock frequency operates at 24 MHz and AVCC ≥ 4.5 V. ■ Conversion Modes of 8-/10-bit A/D Converter There are 3 conversion modes of 8-/10-bit A/D converter as shown below: Table 18.1-1 Conversion Modes of 8-/10-bit A/D Converter Conversion Mode 340 Description Single-shot conversion mode A/D conversion is performed sequentially from the start channel to the end channel. When A/D conversion for the end channel is terminated, it stops. Continuous conversion mode A/D conversion is performed sequentially from the start channel to the end channel. When A/D conversion for the end channel is terminated, it is continued after returning to the start channel. Pause-conversion mode A/D conversion is performed pausing per channel. When A/D conversion for the end channel is terminated, A/D conversion and pause are repeated after returning to the start channel. CHAPTER 18 8-/10-BIT A/D CONVERTER 18.2 Block Diagram of 8-/10-bit A/D Converter The 8-/10-bit A/D converter consists of following blocks. ■ Block Diagram of 8-/10-bit A/D Converter Figure 18.2-1 Block Diagram of 8-/10-bit A/D Converter Interrupt request output ADTG Pin Starting selector MD1 MD0 S10 Software starting Sample & hold circuit AN0 to AN7 AN15 to AN8 Reserved 2 Comparator Control circuit Analog channel selector AVR AVcc AVss D/A converter Internal data bus A/D control status BUSY INT INTE PAUS STS1 STS0 STRT register (ADCS0/ 2 ADCS1) 3 3 A/D data register (ADCR0/ ADCR1) D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Decoder 8 A/D setting register ReReANS3 ANS2 ANS1 ANS0 served ANE3 ANE2 ANE1 ANE0 ST2 ST1 ST0 CT2 CT1 CT0 served (ADSR0/ ADSR1) : Undefined Reserved : Always set to 0. : Machine clock 341 CHAPTER 18 8-/10-BIT A/D CONVERTER ● Details of pins in block diagram Table 18.2-1 shows the actual pin names and interrupt request numbers of the 8-/10-bit A/D converter. Table 18.2-1 Pins and Interrupt Request Numbers in Block Diagram Pin Name/Interrupt Request Number in Block Diagram Actual Pin Name/Interrupt Request Number ADTG Trigger input pin P80/ADTG/INT12R AN0 to AN7 Analog input pin ch0 to ch7 P60/AN0 to P65/AN5 P66/AN6/PPGC(D) P67/AN7/PPGE(F) AN8 to AN15 Analog input pin ch8 to ch15 P50/AN8 to P52/AN10 P53/AN11/TIN3 P54/AN12/TOT3/INT8 P55/AN13/INT10 P56/AN14/INT11 P57/AN15/INT13 AVR Vref+ input pin AVR AVCC VCC input pin AVCC AVSS VSS input pin AVSS Interrupt request output Interrupt request output #29(1DH) ● A/D control status registers (ADCS) This register starts the A/D conversion function by software, selects the start trigger for the A/D conversion function, selects the conversion mode, enables or disables an interrupt request, checks and clears the interrupt request flag, temporarily stops A/D conversion and checks the state during conversion, and sets the resolution. ● A/D data registers (ADCR) This register stores the A/D conversion results. ● A/D setting register (ADSR) Starting channel and end channel of A/D conversion, compare time of A/D conversion and sampling time are set. ● Start selector This selector selects the trigger to start A/D conversion. An external pin input can be set as the start trigger. ● Decoder This decoder sets the A/D conversion start channel select bits and the A/D conversion end channel select bits in the A/D control status register (ADSR0:ANS3 to ANS0 and ANE3 to ANE0) to select the analog input pin to be used for A/D conversion. 342 CHAPTER 18 8-/10-BIT A/D CONVERTER ● Analog channel selector This selector selects the pin to be used for A/D conversion from the 16-channel analog input pins by receiving a signal from the decoder. ● Sample & hold circuit This circuit holds the input voltage selected by the analog channel selector. By holding the input voltage immediately after A/D conversion is started, A/D conversion is performed without being affected by the fluctuation of the input voltage during A/D conversion. ● D/A converter This converter generates the reference voltage which is compared with the input voltage held in the sample & hold circuit. ● Comparator This comparator compares the D/A converter output voltage with input voltage held in the sample & hold circuit to determine the amount of voltage. ● Controller This circuit determines the A/D conversion value by receiving the signal indicating the amount of voltage determined by the comparator. When the A/D conversion results are determined, the result data is stored in the A/D data register. If an interrupt request is enabled, an interrupt is generated. 343 CHAPTER 18 8-/10-BIT A/D CONVERTER 18.3 Configuration of 8-/10-bit A/D Converter This section explains the pins, registers, and interrupt factors of the A/D converter. ■ Pins of 8-/10-bit A/D Converter The pins of the 8-/10-bit A/D converter serve as general-purpose I/O ports. Table 18.3-1 shows the pin functions and the setting required for use of the 8-/10-bit A/D converter. Table 18.3-1 Pins of 8-/10-bit A/D Converter Function Name Pin Name Trigger input P80 / ADTG/INT12R Channel 0 P60 / AN0 Channel 1 P61 / AN1 Channel 2 P62 / AN2 Channel 3 P63 / AN3 Channel 4 P64 / AN4 Channel 5 P65 / AN5 Channel 6 P66 / AN6/PPGC(D) General-purpose I/O ports, analog inputs, PPG output Channel 7 P67 / AN7/PPGE(F) General-purpose I/O ports, analog inputs, PPG output Channel 8 P50 / AN8 Channel 9 P51 / AN9 Channel 10 P52 / AN10 Channel 11 P53 / AN11/TIN3 Channel 12 P54 / AN12/TOT3/ INT8 Channel 13 P55 / AN13/INT10 Channel 14 P56 / AN14/INT11 Channel 15 P57 / AN15/INT13 344 Pin Function General-purpose I/O port, external trigger input, external interrupt Setting Required for Use of 8-/10-bit A/D Converter Set as input port in port direction register (DDR8). General-purpose I/O ports, analog inputs Enable input of analog signal (ADER6: set the corresponding bit of ADE7 to ADE0 to "1") General-purpose I/O ports, analog inputs General-purpose I/O ports, analog inputs, event input pin for reload timer General-purpose I/O ports, analog inputs, external interrupt input, output pin for reload timer General-purpose I/O ports, analog inputs, external interrupt input Enable input of analog signal (ADER5: set the corresponding bit of ADE15 to ADE8 to "1") CHAPTER 18 8-/10-BIT A/D CONVERTER ■ List of Registers and Reset Values of 8-/10-bit A/D Converter Figure 18.3-1 List of Register and Reset Value of 8-/10-bit A/D Converter A/D control status register (High) 15 14 ADCS1 Address:000069H 8 Reset value INTE PAUS STS1 STS0 STRT − 0000000XB R/W R/W R/W R/W R/W − 6 5 4 3 2 1 0 MD1 MD0 S10 − − − − Reserved R/W R/W − − − − R/W BUSY INT R/W A/D control status register (Low) ADCS0 7 Address:000068H Data register (High) ADCR1 Address:00006BH Address:00006CH 10 9 W 13 12 11 10 9 8 − − − − − − − − − − − D9 R D8 R Reset value 000XXXX0B Reset value XXXXXX00B 7 6 5 4 3 2 1 0 Reset value D7 D6 D5 D4 D3 D2 D1 D0 00000000B R R R R R R R R A/D setting register (High) ADSR1 15 ST2 R/W A/D setting register (Low) ADSR0 11 14 Data register (Low) ADCR0 Address:00006AH R/W 12 15 − Address:00006DH 13 7 14 13 12 ST1 R/W ST0 R/W 6 5 R/W R/W 10 CT2 CT1 R/W R/W ANS2 ANS1 ANS0 R/W 11 4 Reserved R/W 9 8 CT0 R/W Reserved 2 1 3 Reset value ANS3 R/W R/W 0 ANE3 ANE2 ANE1 ANE0 R/W R/W R/W 00000000B Reset value 00000000B R/W R/W : Read/Write : Read only R : Write only W : Undefined bit X : Indeterminate ■ Generation of Interrupt from 8-/10-bit A/D Converter In the 8-/10-bit A/D converter, when the A/D conversion results are stored in the A/D data register (ADCR0, 1), the interrupt request flag bit in the A/D control status register (ADCS1:INT) is set to "1". When an interrupt request is enabled (ADCS1:INTE = 1), an interrupt is generated. 345 CHAPTER 18 8-/10-BIT A/D CONVERTER 18.3.1 A/D Control Status Register (High) (ADCS1) The A/D control status register (High) (ADCS1) provides the following settings: • Starting A/D conversion function by software • Selecting start trigger for A/D conversion • Storing A/D conversion results in A/D data register to enable or disable interrupt request • Storing A/D conversion results in A/D data register to check and clear interrupt request flag • Pausing A/D conversion and checking state during conversion ■ A/D Control Status Register (High) (ADCS1) Figure 18.3-2 A/D Control Status Register (High) (ADCS1) 15 Address 14 13 12 11 10 9 000069H BUSY INT INTE PAUS STS1 STS0 STRT R/W R/W R/W R/W R/W R/W W 8 Reset value − 0000000X B − bit8 - Undefined bit Read value is always 1. bit9 STRT A/D conversion software starting bit Not starting A/D conversion function 0 1 Starting A/D conversion function bit11 bit10 STS1 STS0 0 0 0 1 1 0 1 1 A/D conversion starting trigger select bit Starting software Starting software or external trigger Starting software Starting software or external trigger bit12 Suspended flag bit PAUS (This bit is enabled only when EI2OS is used.) Read 0 1 bit13 INTE 0 1 Write Conversion is not suspended. Clear to "0". Conversion is suspended. No effect. Interrupt request enable bit Interrupt request disable Interrupt request enable bit14 INT 0 1 Interrupt request flag bit Read A/D conversion not terminated Write Clear to "0" A/D conversion terminated No effect bit15 BUSY R/W : Read/Write : Write only W : Undefined bit − X : Indeterminate : Reset value 346 0 1 A/D conversion-on flag bit Read A/D conversion terminated (inactive state) A/D conversion in operation Write Terminates A/D conversion forcibly No effect CHAPTER 18 8-/10-BIT A/D CONVERTER Table 18.3-2 Function of Each Bit of A/D Control Status Register (High) (ADCS1) (1/2) Bit name Function bit15 BUSY: A/D conversion-on flag bit This bit forcibly terminates the 8-/10-bit A/D converter. When read, this bit indicates whether the 8-/10-bit A/D converter is operating or stopped. When set to "0": Forcibly terminates 8-/10-bit A/D converter When set to "1": No effect Read: 1 is read when the 8-/10-bit A/D converter is operating and 0 is read when the converter is stopped. Note: • "1" is read from this bit when an read-modify-write instruction is used. • In the single-shot mode, this bit is cleared when A/D conversion ends. • In the continuous or pause mode, the A/D conversion does not stop until writing "0" to this bit. • Do not perform the forced stop (BUSY=0) and the activation of the A/D converter concurrently (using software (STRT=1), external trigger, or timer). bit14 INT: Interrupt request flag bit This bit indicates that an interrupt request is generated. • When A/D conversion is terminated and its results are stored in the A/D data register (ADCR0, 1), the INT bit is set to "1". • When the interrupt request flag bit is set (INT = 1) with an interrupt request enabled (INTE = 1), an interrupt request is generated. When set to "0": Cleared When set to "1": No effect When EI2OS function started: Cleared Note: • "1" is read from this bit when an read-modify-write instruction is used. • To clear the INT bit, write 0 when the 8-/10-bit A/D converter is stopped. bit13 INTE: Interrupt request enable bit This bit enables or disables output of an interrupt request. • When the interrupt request flag bit is set (INT =1) with an interrupt request enabled (INTE = 1), an interrupt request is generated. Note: Always set this bit to 1 when the EI2OS function is used. 347 CHAPTER 18 8-/10-BIT A/D CONVERTER Table 18.3-2 Function of Each Bit of A/D Control Status Register (High) (ADCS1) (2/2) Bit name 348 Function bit12 PAUS: Pause flag bit This bit indicates the A/D conversion operating state when the EI2OS function is used. • The PAUS bit is enabled only when the EI2OS function is used. • When next A/D conversion terminates before the A/D conversion result completes the transfer from the A/D data register (ADCR0, 1) to memory, the A/D conversion pauses in order to prevent previous data from being overwritten. When the A/D conversion pauses, the PAUS bit is set to "1". • After transfer of the A/D conversion results to memory, the 8-/10-bit A/D converter automatically resumes A/D conversion. Note: • See "18.5.5 A/D-converted Data Protection Function" for the conversion data protection function. • This bit is not cleared even if the pause state is cancelled. To clear this bit, write "0" to it. bit11, bit10 STS1, STS0: A/D conversion start trigger select bits These bits select the trigger to start the 8-/10-bit A/D converter. • 00B: Software start • 01B: External pin trigger or software start • 10B: Software start • 11B: External pin trigger or software start Note: • When the falling edge is detected in the ADTG pin at selected external terminal trigger (01B, 11B), the A/D conversion is begun. • If two or more start triggers are set (other than STS1, STS0="00B", "10B"), the 8-/10-bit A/D converter is started by the first-generated start trigger. • Start trigger setting should be changed when the operation of resource generating a start trigger is stopped (trigger is inactive). bit9 STRT: A/D conversion software start bit This bits starts the 8-/10-bit A/D converter by software. When set to "1": Starts 8-/10-bit A/D converter • If A/D conversion pauses in the pause-conversion mode, it is resumed by writing 1 to the STRT bit. When set to "0": Invalid. The state remains unchanged. Note: • The read-modify-write instructions read "0". • The byte/word command reads "1". • Do not perform forcible termination (BUSY = 0) and software start (STRT = 1) of the 8-/10-bit A/D converter simultaneously. bit8 Undefined bit • Read: "1" is always read. • Write: No effect CHAPTER 18 8-/10-BIT A/D CONVERTER 18.3.2 A/D Control Status Register (Low) (ADCS0) The A/D control status register (Low) (ADCS0) provides the following settings: • Selecting A/D conversion mode • Selecting start channel and end channel of A/D conversion ■ A/D Control Status Register (Low) (ADCS0) Figure 18.3-3 A/D Control Status Register (Low) (ADCS0) Address 7 6 5 4 3 2 1 0 000068H MD1 MD0 S10 - - - - Reserved R/W R/W R/W - - - - R/W Reset value 000XXXX0 B bit0 Reserved bit Reserved 0 Always write 0. bit5 S10 0 Resolution select bit Resolution of A/D conversion is set to 10-bit. Resolution of A/D conversion is set to 8-bit. bit7 bit6 MD1 MD0 R/W : Read/Write : Undefined bit X : Indeterminate : Reset value 0 0 0 1 1 0 1 1 A/D conversion mode select bit Single-shot conversion mode 1 (restartable during conversion) Single-shot conversion mode 2 (not-restartable during conversion) Continuous conversion mode (not-restartable during conversion) Pause-conversion mode (not-restartable during conversion) 349 CHAPTER 18 8-/10-BIT A/D CONVERTER Table 18.3-3 Function of Each Bit of A/D Control Status Register (Low) (ADCS0) Bit Name Function bit7 bit6 MD1, MD0: A/D conversion mode select bits These bits set the A/D conversion mode. Single-shot conversion mode 1: • The analog inputs from the start channel (ADSR0 : ANS3 to ANS0) to the end channel (ADSR0 : ANE3 to ANE0) are A/D-converted continuously. • The A/D conversion pauses after A/D conversion for the end channel. • This mode can be restarted during A/D conversion. Single-shot conversion mode 2: • The analog inputs from the start channel (ADSR0 : ANS3 to ANS0) to the end channel (ADSR0 : ANE3 to ANE0) are A/D-converted continuously. • The A/D conversion pauses after A/D conversion for the end channel. • This mode cannot be restarted during A/D conversion. Continuous conversion mode: • The analog inputs from the start channel (ADSR0 : ANS3 to ANS0) to the end channel (ADSR0 : ANE3 to ANE0) are A/D-converted continuously. • When A/D conversion for the end channel is terminated, it is continued after returning to the analog input for the start channel. • To terminate A/D conversion forcibly, write 0 to the A/D conversion-on flag bit in the A/D control status register (ADCS1:BUSY). • This mode cannot be restarted during A/D conversion. Pause conversion mode: • A/D conversion for the start channel (ADSR0 : ANS3 to ANS0) starts. The A/D conversion pauses at termination of A/D conversion for a channel. When the start trigger is inputted while A/D conversion pauses, A/D conversion for the next channel is started. • The A/D conversion pauses at the termination of A/D conversion for the end channel. When the start trigger is inputted while A/D conversion pauses, A/D conversion is continued after returning to the analog input for the start channel. • To terminate A/D conversion forcibly, write 0 to the A/D conversion-on flag bit in the A/D control status register (ADCS1:BUSY). • This mode cannot be restarted during A/D conversion. Note: • To change the conversion mode, perform at the stop state before starting the A/D conversion. • When the conversion mode is set to "not restartable" (other than MD1, MD0 ="00B"), it cannot be restarted with any start triggers (software trigger and external trigger) during A/D conversion. bit5 S10: Resolution select bit This bit sets the resolution of the A/D conversion. When set to "0": Set the resolution of the A/D conversion to 10-bit of A/D conversion data bits D9 to D0. When set to "1": Set the resolution of the A/D conversion to 8-bit of A/D conversion data bits D7 to D0. Note: To change the S10 bit, perform at the stop state before starting the A/D conversion. When the S10 bit is changed after starting A/D conversion, the converted result stored in the A/D conversion data bit (D9 to D0) is invalid. 350 CHAPTER 18 8-/10-BIT A/D CONVERTER 18.3.3 A/D Data Register (ADCR0/ADCR1) The A/D data register (ADCR0/ADCR1) stores the digital value generated as the conversion result. The ADCR0 stores the lower 8-bit, and ADCR1 stores the most significant 2-bit of the conversion result. This register is rewritten each time the conversion complete and stores last conversion value normally. ■ A/D Data Register (ADCR0/ADCR1) Figure 18.3-4 A/D Data Register (ADCR0/ADCR1) Data register (High) Address ADCR1 00006BH 15 14 13 12 11 10 9 8 - - - - - - D9 D8 R R Data register (Low) Address ADCR0 00006AH 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 R R R R R R R R Reset value XXXXXX00 B Reset value 00000000B R : Read only X : Indeterminate - : Undefined bit Table 18.3-4 Functions of A/D Data Register (ADCR0/ADCR1) Bit Name Function bit15 to bit10 Undefined bits 1 is always read at reading. bit9 to bit0 D9 to D0: A/D conversion data bits These bits store the A/D conversion results. When resolution set in 10 bits (S10=0): Conversion data is stored in the 10 bits from D9 to D0. When resolution set in 8 bits (S10=1): Conversion data is stored in the 8 bits from D7 to D0. In this case, the read values of D9 and D8 are 1. Note: • Writing to this register is disabled. • Use a word instruction (MOVW) to read the A/D conversion results stored in the A/D conversion data bits (D9 to D0). 351 CHAPTER 18 8-/10-BIT A/D CONVERTER 18.3.4 A/D Setting Register (ADSR0/ADSR1) A/D setting register (ADSR0/ADSR1) can set as following. • Setting of A/D conversion time (sampling time and comparing time) • Setting of sampling channel (starting channel and end channel) • Displaying the present sampling channels ■ A/D Setting Register (ADSR0/ADSR1) Figure 18.3-5 A/D Setting Register (ADSR0/ADSR1) 15 14 13 12 11 10 Address 00006CH ST2 ST1 ST0 CT2 CT1 CT0 9 8 7 6 5 4 3 2 1 0 Reset value Re- ANS3ANS2 ANS1 ANS0 Re- ANE3ANE2 ANE1 ANE0 served served 0000000000000000B R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W bit3 to bit0 ANE3 to ANE0 A/D conversion end channel select bit 1111B to 0000B (reset value:0000B) AN15 pin to AN0 pin bit8 to bit5 A/D conversion start channel select bit ANS3 to ANS0 1111B to 0000B (reset value:0000B) bit12 bit11 bit10 CT2 CT1 CT0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 1 bit9,bit4 Reserved bit15 bit14 bit13 ST2 ST1 ST0 φ 352 : Read/Write : Machine clock : Reset value AN15 pin to AN0 pin Read at pausing in pauseconversion mode Converted channel Channel number immediately number before in converting Comparing time select bit 22/φ (φ=20 MHz: 1.1 µs) 33/φ (φ=24 MHz: 1.4 µs) 44/φ (φ=24 MHz: 1.8 µs) 66/φ (φ=24 MHz: 2.75 µs) 88/φ (φ= 8 MHz:11.0 µs) 132/φ (φ=16 MHz: 8.25 µs) 176/φ (φ=20 MHz: 8.8 µs) 264/φ (φ=24 MHz:11.0 µs) Reserved bit Always write 0 to this bit. Reading value is always 0. 0 R/W Write Read (state in not in converting starting) 0 0 0 0 0 0 1 1 0 1 0 1 1 1 1 1 0 0 1 1 0 1 0 1 Sampling time select bit 4/φ (φ= 8 MHz:0.5 µs) 6/φ (φ= 8 MHz:0.75 µs) 8/φ (φ=16 MHz:0.5 µs) 12/φ (φ=24 MHz:0.5 µs) 24/φ (φ= 8 MHz:3.0 µs) 36/φ (φ=16 MHz:2.25 µs) 48/φ (φ=16 MHz:3.0 µs) 128/φ (φ=24 MHz:5.3 µs) CHAPTER 18 8-/10-BIT A/D CONVERTER Table 18.3-5 Function of A/D Setting Register (ADSR0/ADSR1) (1/2) Bit Name Function bit15 to bit13 ST2, ST1, ST0: Sampling time select bits These bits set the sampling time of A/D conversion. • These bits set the time when the A/D conversion is started and inputted analog voltage is sampled by the sample & hold circuit until it is retained. • See Table 18.3-6 for the setting of these bits. bit12 to bit10 CT2, CT1, CT0: Comparing time select bits Comparing time of A/D conversion (comparing time) is set. • These bits set the time when the analog input is A/D converted until it stores to the data bits (D9 to D0). • See Table 18.3-7 for the setting of these bits. bit9, bit4 Reserved bits Always write 0 to these bits. Reading value is always 0. bit8 to bit5 ANS3 to ANS0: A/D conversion start channel select bits These bits set the channel at which A/D conversion start.At read, the channel number under conversion can be checked if the A/D conversion is in progress and last A/D converted channel number can be checked if the A/D conversion is completed or is stopping. And before A/D conversion starts, the previous conversion channel will be read even if these bits have already been set to the new value. These bits are initialized to "0000B" at reset. Start channel < end channel: A/D conversion starts at channel set by A/D conversion start channel select bits (ANS3 to ANS0) and terminates channel set by A/D conversion end channel select bits (ANE3 to ANE0) Start channel = end channel: A/D conversion is performed only for one channel set by A/D conversion start (= end) channel select bits (ANS3 to ANS0 = ANE3 to ANE0) Start channel > end channel: Do not set Continuous conversion mode and pause-conversion mode: When A/D conversion terminated at the channel set by the A/D conversion end channel select bits (ANE3 to ANE0), it returns to the channel set by the A/D conversion start channel select bits (ANS3 to ANS0). Read (Other than pause-conversion mode) : The channel numbers (15 to 0) under A/D conversion are read. Read (Pause-conversion mode) : At read during a pause, the channel number A/D-converted immediately before a pause is read. Notes: • Do not set the A/D conversion start channel bits (ANS3 to ANS0) during A/D conversion. • Access in units of word when writing to these bits. If the byte write or bit operation is performed, the A/D conversion may be started from unexpected channel. 353 CHAPTER 18 8-/10-BIT A/D CONVERTER Table 18.3-5 Function of A/D Setting Register (ADSR0/ADSR1) (2/2) Bit Name bit3 to bit0 Function ANE3 to ANE0: A/D conversion end channel select bits These bits set the channel at which A/D conversion terminated. Start channel < end channel: A/D conversion starts at channel set by A/D conversion start channel select bits (ANS3 to ANS0) and terminates channel set by A/D conversion end channel select bits (ANE3 to ANE0) Start channel = end channel: A/D conversion is performed only for one channel set by A/D converter start (= end) channel select bits (ANE3 to ANE0 = ANS3 to ANS0). Start channel > end channel: Do not set. Continuous conversion mode and pause-conversion mode: When A/D conversion terminated at the channel set by the A/D conversion end channel select bits (ANE3 to ANE0), it returns to the channel set by the A/D conversion start channel select bits (ANS3 to ANS0). Note: Do not set the A/D conversion end channel select bits (ANE3 to ANE0) during A/D conversion. Note: Do not set the A/D conversion mode set bits (MD1 and MD0) and A/D conversion end channel select bits (ANE3, ANE2, ANE1 and ANE0) through read-modify-write commands after the start channel is set in the A/D conversion start channel select bits (ANS3, ANS2, ANS1 and ANS0). The ANS3, ANS2, ANS1 and ANS0 bits will read the last conversion channel until the A/D conversion operation starts. Accordingly when the MD1 and MD0 bits and the ANE3, ANE2, ANE1 and ANE0 bits are set through read-modify-write commands after the start channel is set in the ANS3, ANS2, ANS1 and ANS0 bits, the values of the ANE3, ANE2, ANE1 and ANE0 bits may be rewritten. ■ Setting of Sampling Time (ST2 to ST0 bits) Table 18.3-6 Relation between ST2 to ST0 Bits and Sampling Time 354 ST2 ST1 ST0 Setting of Sampling Time Setting example (φ: Internal operating frequency) 0 0 0 4 machine cycles φ= 8 MHz: 0.5 µs 0 0 1 6 machine cycles φ= 8 MHz: 0.75 µs 0 1 0 8 machine cycles φ= 16 MHz: 0.5 µs 0 1 1 12 machine cycles φ= 24 MHz: 0.5 µs 1 0 0 24 machine cycles φ= 8 MHz: 3 µs 1 0 1 36 machine cycles φ= 16 MHz: 2.25 µs 1 1 0 48 machine cycles φ= 16 MHz: 3.0 µs 1 1 1 128 machine cycles φ= 24 MHz: 5.3 µs CHAPTER 18 8-/10-BIT A/D CONVERTER The sampling time must be set according to drive impedance Rext connected to analog input. If the following condition is not met, the conversion accuracy will not be guaranteed. • Rext ≤ 1.5kΩ : •- 4.5 V ≤ AVCC < 5.5 V: The sampling time must be set greater than 0.5 µs. • 4.0 V ≤ AVCC < 4.5 V: The sampling time must be set greater than 1.2 µs. • Rext > 1.5kΩ : The sampling time must be set greater than Tsamp given by the following formula. • 4.5 V ≤ AVCC < 5.5 V: Tsamp = (2.52 kΩ+Rext) × 10.7 pF × 7 • 4.0 V ≤ AVCC < 4.5 V: Tsamp = (13.6 kΩ+Rext) × 10.7 pF × 7 ■ Setting of Comparing Time (CT2 to CT0 bits) Table 18.3-7 Relation between CT2 to CT0 Bits and Comparing Time CT2 Setting of comparing time Setting example (φ: Internal operating frequency) CT1 CT0 0 0 0 22 machine cycles φ= 20 MHz: 1.1 µs 0 0 1 33 machine cycles φ= 24 MHz: 1.4 µs 0 1 0 44 machine cycles φ= 24 MHz: 1.8 µs 0 1 1 66 machine cycles φ= 24 MHz: 2.75 µs 1 0 0 88 machine cycles φ= 8 MHz: 11.0 µs 1 0 1 132 machine cycles φ= 16 MHz: 8.25 µs 1 1 0 176 machine cycles φ= 20 MHz: 8.8 µs 1 1 1 264 machine cycles φ= 24 MHz: 11.0 µs The comparing time must be set according to the analog power supply voltage AVCC. If the following condition is not met, the conversion accuracy will not be guaranteed. • 4.5 V ≤ AVCC < 5.5 V: The comparing time must be set greater than 1.00 µs. • 4.0 V ≤ AVCC < 4.5 V: The comparing time must be set greater than 2.00 µs. 355 CHAPTER 18 8-/10-BIT A/D CONVERTER 18.3.5 Analog Input Enable Register (ADER5, ADER6) The analog input enable register enables or disables the analog input pins to be used in the 8-/10-bit A/D converter. ■ Analog Input Enable Register (ADER5, ADER 6) Figure 18.3-6 Analog Input Enable Register (ADER5 to 6) 15 Address ADER5 14 13 12 11 10 9 8 Reset value 00000BH ADE15 ADE14 ADE13 ADE12 ADE11 ADE10 ADE9 ADE8 11111111 B R/W R/W R/W R/W R/W R/W R/W R/W bit15 to bit8 ADE15 to ADE8 Analog input enable bit 15 to 8 (AN15 to AN8) Analog input disable 0 Analog input enable 1 Address ADER6 7 6 5 4 3 2 1 0 Reset value 00000CH ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 11111111 B R/W R/W R/W R/W R/W R/W R/W R/W R/W : Read/Write : Reset value bit7 to bit0 ADE7 to ADE0 0 1 Analog input enable bit 7 to 0 (AN7 to AN0) Analog input disable Analog input enable Table 18.3-8 Functions of Port 5 Analog Input Enable Register (ADER5) Bit Name bit15 to bit8 ADE15 to ADE8: Analog input enable bits 15 to 8 Function These bits enable or disable the analog input pin (AN15 to AN8) of A/D conversion arranged on port 5. When set to "0": Disables analog input When set to "1": Enables analog input Table 18.3-9 Functions of Port 6 Analog Input Enable Register (ADER6) Bit Name bit0 to bit7 356 ADE7 to ADE0: Analog input enable bits 7 to 0 Function These bits enable or disable the analog input pin (AN7 to AN0) of A/ D conversion arranged on port 6. When set to "0": Disables analog input When set to "1": Enables analog input CHAPTER 18 8-/10-BIT A/D CONVERTER Notes: • When using as the analog input pin, write "1" to the bit of the analog input enable register (ADER5, ADER6) corresponding to the pin to be used and set to the analog input. • Setting the analog input pin to ADERx = "0" is disabled. Always set it to ADERx = "1". • Each analog input pin serves as the general-purpose I/O port and I/O of peripheral function. The pin set to ADERx = "1" is forcibly set to the analog input pin regardless of the port direction register (DDR5, DDR6) and the I/O setting of each peripheral function. 357 CHAPTER 18 8-/10-BIT A/D CONVERTER 18.4 Interrupt of 8-/10-bit A/D Converter When A/D conversion is terminated and its results are stored in the A/D data register (ADCR), the 8-/10-bit A/D converter generates an interrupt request. The EI2OS function can be used. ■ Interrupt of A/D Converter When A/D conversion of the analog input voltage is terminated and its results are stored in the A/D data register (ADCR), the interrupt request flag bit in the A/D control status register (ADCS:INT) is set to "1". When the interrupt request flag bit is set (ADCS:INT = 1) with an interrupt request output enabled (ADCS:INTE = 1), an interrupt request is generated. ■ 8-/10-bit A/D Converter Interrupt and EI2OS Reference: See "CHAPTER 3 INTERRUPTS" for details of the interrupt number, interrupt control register, and interrupt vector address. ■ EI2OS Function of 8-/10-bit A/D Converter In the 8-/10-bit A/D converter, the EI2OS function can be used to transfer the A/D conversion results from the A/D data register (ADCR) to memory. If the EI2OS function is used, the A/D-converted data protection function is activated to cause A/D conversion to pause during memory transfer and prevent data loss as A/ D conversion is performed continuously. 358 CHAPTER 18 8-/10-BIT A/D CONVERTER 18.5 Explanation of Operation of 8-/10-bit A/D Converter The 8-/10-bit A/D converter has the following A/D conversion modes. Set each mode according to the setting of the A/D conversion mode select bits in the A/D control status register (ADCS:MD1, MD0). • Single-shot conversion mode (restartable/not-restartable during A/D conversion) • Continuous conversion mode (not-restartable during A/D conversion) • Pause--conversion mode (not-restartable during A/D conversion) ■ Single-shot Conversion Mode (ADCS: MD1, MD0="00B" or "01B") • When the start trigger is inputted, the analog inputs from the start channel (ADCS:ANS3 to ANS0) to the end channel (ADCS:ANE3 to ANE0) are A/D-converted continuously. • The A/D conversion stops at the termination of the A/D conversion for the end channel. • To terminate A/D conversion forcibly, write 0 to the A/D conversion-on flag bit in the A/D control status register (ADCS:BUSY). • When the A/D conversion mode select bits (MD1, MD0) are set to "00B", this mode can be restarted during A/D conversion. If the bits are set to "01B", this mode cannot be restarted during A/D conversion. ■ Continuous Conversion Mode (ADCS: MD1, MD0="10B") • When the start trigger is inputted, the analog inputs from the start channel (ADCS:ANS3 to ANS0) to the end channel (ADCS:ANE3 to ANE0) are A/D-converted continuously. • When A/D conversion for the end channel is terminated, it is continued after returning to the analog input for the start channel. • To terminate A/D conversion forcibly, write 0 to the A/D conversion-on flag bit in the A/D control status register (ADCS:BUSY). • This mode cannot be restarted during A/D conversion. ■ Pause-conversion Mode (ADCS: MD1, MD0="11B") • When the start trigger is inputted, A/D conversion starts for the start channel (ADCS:ANS3 to ANS0). The A/D conversion pauses at the termination of A/D conversion for one channel. When the start trigger is inputted while A/D conversion pauses, A/D conversion is performed for the next channel. • The A/D conversion pauses at termination of A/D conversion for the end channel. When the start trigger is inputted while A/D conversion pauses, A/D conversion is continued after returning to the analog input for the start channel. • To terminate A/D conversion forcibly, write 0 to the A/D conversion-on flag bit in the A/D control status register (ADCS:BUSY). • This mode cannot be restarted during A/D conversion. 359 CHAPTER 18 8-/10-BIT A/D CONVERTER 18.5.1 Single-shot Conversion Mode In the single-shot conversion mode, A/D conversion is performed sequentially from the start channel to the end channel. The A/D conversion stops at the termination of A/D conversion for the end channel. ■ Setting of Single-shot Conversion Mode Operating the 8-/10-bit A/D converter in the single-shot conversion mode requires the setting shown in Figure 18.5-1 . Figure 18.5-1 Setting of Single-shot Conversion Mode bit15 14 13 12 11 10 ADCS 9 bit8 bit7 6 5 4 3 2 1 bit0 BUSY INT INTE PAUS STS1 STS0 STRT − MD1 MD0 S10 − − − − Reserved 0 ADCR ADSR − − − − − − D9 to D0 (Converted data stored) ReReST2 ST1 ST0 CT2 CT1 CT0 served ANS3 ANS2 ANS1 ANS0 served ANE3 ANE2 ANE1 ANE0 0 ADER5 ADER6 0 0 ADE15ADE14ADE13ADE12ADE11ADE10 ADE9 ADE8 ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 − : Undefined : Used bit : Set the bit corresponding to pin to be used as analog input pin to 1. 0 : Setting 0 360 CHAPTER 18 8-/10-BIT A/D CONVERTER ■ Operation of Single-shot Conversion Mode • When the start trigger is inputted, A/D conversion starts from the channel set by the A/D conversion start channel select bits (ANS3 to ANS0) and is performed continuously up to the channel set by the A/ D conversion end channel select bits (ANE3 to ANE0). • The A/D conversion stops at the termination of the A/D conversion for the channel set by the A/D conversion end channel select bits (ANE3 to ANE0). • To terminate A/D conversion forcibly, write 0 to the A/D conversion-on flag bit in the A/D control status register (ADCS:BUSY). • When the A/D conversion mode select bits (MD1, MD0) are set to "00B", this mode can be restarted during A/D conversion. If the bits are set to "01B", this mode cannot be restarted during A/D conversion. [When start and end channels are the same] If the start and end channels have the same channel number (ADCS: ANS3 to ANS0=ADCS: ANE3 to ANE0), only one A/D conversion for one channel set as the start channel (= end channel) is performed and terminated. [Conversion order in single-shot conversion mode] Table 18.5-1 gives an example of the conversion order in the single-shot conversion mode. Table 18.5-1 Conversion Order in Single-shot Conversion Mode Start Channel End Channel Conversion Order AN0 pin (ADCS: ANS="0000B") AN3 pin (ADCS: ANE="0011B") AN0 → AN1 → AN2 → AN3 → end AN3 pin (ADCS: ANS="0011B") AN3 pin (ADCS: ANE="0011B") AN3 → end 361 CHAPTER 18 8-/10-BIT A/D CONVERTER 18.5.2 Continuous Conversion Mode In the continuous conversion mode, A/D conversion is performed sequentially from the start channel to the end channel. When A/D conversion for the end channel is terminated, it is continued after returning to the start channel. ■ Setting of Continuous Conversion Mode Operating the 8-/10-bit A/D converter in the continuous conversion mode requires the setting shown in Figure 18.5-2 . Figure 18.5-2 Setting of Continuous Conversion Mode bit15 14 13 12 11 10 ADCS 9 bit8 bit7 6 4 3 2 1 bit0 BUSY INT INTE PAUS STS1 STS0 STRT − MD1 MD0 S10 − − − − 1 ADCR ADSR − − − − − − ADER6 − 1 0 362 Reserved 0 0 D9 to D0 (Converted data stored) ReReST2 ST1 ST0 CT2 CT1 CT0 served ANS3 ANS2 ANS1 ANS0 served ANE3 ANE2 ANE1 ANE0 0 ADER5 5 0 ADE15ADE14ADE13ADE12ADE11ADE10 ADE9 ADE8 ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 : Undefined : Used bit : Set the bit corresponding to pin to be used as analog input pin to 1. : Setting 1 : Setting 0 CHAPTER 18 8-/10-BIT A/D CONVERTER ■ Operation of Continuous Conversion Mode • When the start trigger is inputted, A/D conversion starts from the channel set by the A/D conversion start channel select bits (ANS3 to ANS0) and is performed continuously up to the channel set by the A/ D conversion end channel select bits (ANE3 to ANE0). • When A/D conversion for the channel set by the A/D conversion end channel select bits (ANE3 to ANE0) is terminated, it is continued after returning to the channel set by the A/D conversion start channel select bits (ANS3 to ANS0). • To terminate A/D conversion forcibly, write 0 to the A/D conversion-on flag bit in the A/D control status register (ADCS:BUSY). • This mode cannot be restarted during A/D conversion. [When start and end channels are the same] If the start and end channels have the same channel number (ADCS:ANS3 to ANS0 = ADCS:ANE3 to ANE0), A/D conversion for one channel set as the start channel (= end channel) is repeated. [Conversion order in continuous conversion mode] Table 18.5-2 gives an example of the conversion order in the continuous conversion mode. Table 18.5-2 Conversion Order in Continuous Conversion Mode Start Channel End Channel Conversion Order AN0 pin (ADCS: ANS="0000B") AN3 pin (ADCS: ANE="0011B") AN0 → AN1 → AN2 → AN3 → AN0 → repeat AN3 pin (ADCS: ANS="0011B") AN3 pin (ADCS: ANE="0011B") AN3 → AN3 → repeat 363 CHAPTER 18 8-/10-BIT A/D CONVERTER 18.5.3 Pause-conversion Mode In the pause-conversion mode, A/D conversion starts and pauses repeatedly for each channel. When the start trigger is inputted after the A/D conversion pauses at the termination of the A/D conversion for the end channel, A/D conversion is continued after returning to the start channel. ■ Setting of Pause-conversion Mode Operating the 8-/10-bit A/D converter in the pause-conversion mode requires the setting shown in Figure 18.5-3 . Figure 18.5-3 Setting of Pause-conversion Mode bit15 14 13 12 11 10 ADCS 9 bit8 bit7 6 4 3 2 1 bit0 BUSY INT INTE PAUS STS1 STS0 STRT − MD1 MD0 S10 − − − − 1 ADCR ADSR − − − − − − ADER6 0 1 ReReST2 ST1 ST0 CT2 CT1 CT0 served ANS3 ANS2 ANS1 ANS0 served ANE3 ANE2 ANE1 ANE0 0 ADE15ADE14ADE13ADE12ADE11ADE10 ADE9 ADE8 ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 − : Undefined : Used bit : Set the bit corresponding to pin to be used as analog input pin to 1. 1 : Setting 1 0 : Setting 0 364 Reserved D9 to D0 (Converted data stored) 0 ADER5 5 CHAPTER 18 8-/10-BIT A/D CONVERTER ■ Operation of Pause-conversion Mode • When the start trigger is inputted, A/D conversion starts at the channel set by the A/D conversion start channel select bits (ANS3 to ANS0). The A/D conversion pauses at the termination of the A/D conversion for one channel. When the start trigger is inputted while A/D conversion pauses, A/D conversion for the next channel is performed. • The A/D conversion pauses at the termination of the A/D conversion for the channel set by the A/D conversion end channel select bits (ANE3 to ANE0). When the start trigger is inputted while A/D conversion pauses, A/D conversion is continued after returning to the channel set by the A/D conversion start channel select bits (ANS3 to ANS0). • To restart this mode while A/D conversion pauses, input the start trigger set by the A/D start trigger select bits in the A/D control status register (ADCS:STS1, STS0). • To terminate A/D conversion forcibly, write 0 to the A/D conversion-on flag bit in the A/D control status register (ADCS:BUSY). • This mode cannot be restarted during A/D conversion. [When start and end channels are the same] If the start and end channels have the same channel number (ADCS:ANS3 to ANS0 = ADCS:ANE3 to ANE0), A/D conversion for one channel set as the start channel (= end channel) and pause are repeated. [Conversion order in pause-conversion mode] Table 18.5-3 gives an example of the conversion order in the pause-conversion mode. Table 18.5-3 Conversion Order in Pause-conversion Mode Start Channel End Channel Conversion Order AN0 pin (ADCS: ANS="0000B") AN3 pin (ADCS: ANE="0011B") AN0 → Stop, Start → AN1 → Stop, Start → AN2 → Stop, Start → AN3 → Stop, Start → AN0 → Repeat AN3 pin (ADCS: ANS="0011B") AN3 pin (ADCS: ANE="0011B") AN3 → Stop, Start → AN3 → Stop, Start → Repeat 365 CHAPTER 18 8-/10-BIT A/D CONVERTER 18.5.4 Conversion Using EI2OS Function The 8-/10-bit A/D converter can transfer the A/D conversion result to memory by using the EI2OS function. ■ Conversion Using EI2OS The use of the EI2OS enables the A/D-converted data protection function to transfer multiple data to memory without the loss of converted data even if A/D conversion is performed continuously. The conversion flow when the EI2OS is used is shown in Figure 18.5-4 . Figure 18.5-4 Flow of Conversion when Using EI2OS A/D converter starts Sample & hold A/D conversion starts A/D conversion terminates Interrupt generated EI2OS starts Converted data transferred Specified count completed?* NO Interrupt cleared YES Interrupt processing *: The specified count depends on the setting of the EI2OS. 366 CHAPTER 18 8-/10-BIT A/D CONVERTER 18.5.5 A/D-converted Data Protection Function A/D conversion with the output of an interrupt request enabled activates the A/D conversion data protection function. ■ A/D-converted Data Protection Function in 8-/10-bit A/D Converter The 8-/10-bit A/D converter has only one A/D data register (ADCR) where A/D-converted data is stored. When the A/D conversion results are determined after the termination of A/D conversion, data in the A/D data register is rewritten. Therefore, the A/D conversion results may be lost if the A/D conversion results already stored are not read before data in the A/D data register is rewritten. The A/D-converted data protection function in the 8-/10-bit A/D converter is activated to prevent data loss. This function automatically causes A/D conversion to pause when an interrupt request is generated (ADCS:INT = 1) with an interrupt request enabled (ADCS:INTE = 1). ● A/D-converted data protection function when EI2OS not used • When the A/D conversion results are stored in the A/D data register (ADCR) after the analog input is A/D-converted, the interrupt request flag bit in the A/D control status register (ADCS: INT) is set to "1". • The A/D conversion stops for data protection immediately before new data is overwritten to the A/D data register if the interrupt request is enabled (ADCS: INTE = 1) while the interrupt request flag bit set at termination of previous A/D conversion is set at the point that next A/D conversion is terminated. • When the INT bit is set with an interrupt request from the A/D control status register enabled (ADCS: INTE = 1), an interrupt request is generated. When the INT bit is cleared by the generated interrupt processing, the pause of A/D conversion is cancelled. ● A/D-converted data protection function when EI2OS used • The A/D conversion stops for data protection immediately before new data is overwritten to the A/D data register while the EI2OS function is used to transfer the A/D conversion results from the A/D data register to memory when next A/D conversion is terminated. When A/D conversion pauses, the pause flag bit in the A/D control status register (ADCS: PAUS) is set to "1". • When the transfer of the A/D conversion results to memory by the EI2OS function is terminated, the pause of A/D conversion is cancelled. If the A/D conversion is performed continuously, it is restarted. In this case, the pause flag bit (ADCS:PAUS) is not cleared to "0" automatically. Clearing this bit writes 0 to it. ● Processing flow of A/D conversion data protection function when EI2OS used Figure 18.5-5 shows the processing flow of the A/D conversion data protection function when the EI2OS is used. 367 CHAPTER 18 8-/10-BIT A/D CONVERTER Figure 18.5-5 Processing Flow of A/D Conversion Data Protection Function when Using EI2OS EI2OS set A/D continuous conversion starts First conversion terminates Data in A/D data register stored EI2OS starts Second conversion terminates EI2OS end NO A/D pauses YES Data in A/D data register stored Third conversion EI2OS starts Continued Entire conversion terminates EI2OS terminates NO A/D pauses YES EI2OS starts Interrupt processing A/D conversion pauses Note: The operation flow of when the A/D converter is stopped is omitted. End Notes: • The A/D conversion data protection function is activated only when an interrupt request is enabled. Set the interrupt request enable bit in the A/D control status register (ADCS:INTE) to 1. • The EI2OS function is used to transfer the A/D conversion results to memory, do not disable output of an interrupt request. If output of an interrupt request is disabled during a pause of A/D conversion (ADCS:INTE = 0), A/D conversion may be restarted to rewrite data being transferred. • The EI2OS function is used to transfer the A/D conversion results to memory, do not restart. Restarting during a pause of A/D conversion may cause loss of the A/D conversion results. 368 CHAPTER 18 8-/10-BIT A/D CONVERTER 18.6 Precautions when Using 8-/10-bit A/D Converter Precautions when using the 8-/10-bit A/D converter are given below: ■ Precautions when Using 8-/10-bit A/D Converter ● Analog input pin • The analog input pins serve as general-purpose I/O ports of port 5 and port 6. When using the pin as an analog input pin, switch the pin to "analog input pin" according to the setting of the analog input enable register (ADER5 , ADER6). • When using the pin as an analog input pin, write 1 to the bit in the analog input enable register (ADER5, ADER6) corresponding to the pin to be used and set the pin to "analog input enable". • When an intermediate-level signal is inputted with the pin set as a general-purpose I/O port, the input leakage current flows in the gate. When using the pin as an analog input pin, always set the pin to "analog input enable". ● Precaution when starting by external trigger • Set the level of the external trigger to inactive ("H" for external trigger) when the A/D start trigger select bits in the A/D control status register (ADCS: STS1 and STS0) is set the same way as starting the 8-/10bit A/D converter by the external trigger. Holding the input value for the start trigger active may cause the 8-/10-bit A/D converter to start the A/D start trigger select bits in the A/D control status register (ADCS: STS1 and STS0). ● Procedure of 8-/10-bit A/D converter and analog input power-on • Always apply a power to the 8-/10-bit A/D converter power (AV CC , AVR) and the analog input (AN0 to AN15 pins) after or concurrently with the digital power (VCC)-on. • Always turn off the 8-/10-bit A/D converter power and the analog input before or concurrently with the digital power (VCC)-down. • Note that AVR should not exceed AVCC at power on or power down. (Turning on and off the analog power and digital power simultaneously is enabled.) ● Power supply voltage of 8-/10-bit A/D converter • To prevent latch up, note that the 8-/10-bit A/D converter power (AVCC) should not exceed the digital power (VCC) voltage. 369 CHAPTER 18 8-/10-BIT A/D CONVERTER 370 CHAPTER 19 LOW VOLTAGE DETECTION/ CPU OPERATING DETECTION RESET This chapter explains the function and operating the low voltage detection/CPU operating detection reset. This function can use only the product with "T" suffix of MB90360 series. 19.1 Overview of Low Voltage/CPU Operating Detection Reset Circuit 19.2 Configuration of Low Voltage/CPU Operating Detection Reset Circuit 19.3 Low Voltage/CPU Operating Detection Reset Circuit Register 19.4 Operating of Low Voltage/CPU Operating Detection Reset Circuit 19.5 Notes on Using Low Voltage/CPU Operating Detection Reset Circuit 19.6 Sample Program for Low Voltage/CPU Operating Detection Reset Circuit 371 CHAPTER 19 LOW VOLTAGE DETECTION/CPU OPERATING DETECTION RESET 19.1 Overview of Low Voltage/CPU Operating Detection Reset Circuit The low voltage detection reset circuit watches the power-supply voltage and has the function to detect the power-supply voltages falling lower than the detection voltage values. When the low voltage is detected, internal reset is generated. When the counter is not cleared within the fixed time after 20-bit counter start that makes the oscillation clock a count clock, CPU operating detection reset circuit generates internal reset. ■ Low Voltage Detection Reset Circuit Figure 19.1-1 Detection Voltage of Low Voltage/CPU operating Detection Reset Circuit Detection voltage 4.0V ± 0.3V After detecting the low voltage, low voltage detection flag (LVRC:LVRF) is set to "1", and internal reset is outputted. After the low voltage is detected, internal reset is generated and the STOP mode is canceled, because of that keep operating at the STOP mode. After writing ends, low voltage reset is generated for internal RAM writing period. 372 CHAPTER 19 LOW VOLTAGE DETECTION/CPU OPERATING DETECTION RESET ■ CPU Operating Detection Reset Circuit CPU operating detection reset circuit is a counter for preventing the program out of control. After power-on reset, it starts automatically. After it starts, it is necessary to keep clearing regularly within the fixed time. Internal reset is generated when not cleared during the fixed time by an program infinite loop, etc. The width of internal reset generated by CPU operating detection circuit is five machine cycles. Figure 19.1-2 Interval Time of CPU operating Detection Reset Circuit Interval time 220/FC (approx.262ms)* *: It is the interval time at oscillation clock 4 MHz. In the mode that CPU stops operating, the circuit stops. The counter condition of CPU operating detection reset circuit is indicated as follows. 1) Writing "0" to CL bit of LVRC register 2) Internal reset 3) Oscillation clock stop 4) Transition to sleep mode 5) Transition to timebase timer mode 373 CHAPTER 19 LOW VOLTAGE DETECTION/CPU OPERATING DETECTION RESET 19.2 Configuration of Low Voltage/CPU Operating Detection Reset Circuit Low voltage/CPU operating detection reset circuit has following three blocks. • CPU operating detection circuit • Voltage comparison circuit • Low voltage/CPU operating detection reset control register (LVRC) ■ Block Diagram of Low Voltage/CPU Operating Detection Reset Circuit Figure 19.2-1 Block Diagram of Low Voltage/CPU operating Detection Reset Circuit VCC Voltage comparison circuit + VSS Fixed voltage supply CPU operating detection circuit Oscillation clock Counter Clear OF F/ F Internal reset Noise canceler Reserved Reserved Reserved Reserved CL LVRF Reserved CPUF Low voltage/CPU operating detection reset control register (LVRC) Internal data bus 374 CHAPTER 19 LOW VOLTAGE DETECTION/CPU OPERATING DETECTION RESET ● CPU operating detection circuit It is a counter for preventing the program out of control. After it starts, it is necessary to keep clearing regularly within the fixed time. ● Voltage comparison circuit When the detection voltage is compared with the power-supply voltage, the output is set to "H" after the low voltage detection. After the power supply is turned on, it always operates. ● Low voltage/CPU operating detection reset control register (LVRC) This register clears the low voltage/CPU operating detection reset flag and the counter of CPU operating detection function. ● Reset factor of low voltage/CPU operating detection reset circuit After power-supply voltages is fallen more than the detection voltages, internal reset is generated. When the counter of CPU operating detection circuit is not cleared during the fixed time, internal reset is generated. 375 CHAPTER 19 LOW VOLTAGE DETECTION/CPU OPERATING DETECTION RESET 19.3 Low Voltage/CPU Operating Detection Reset Circuit Register This register clears the low voltage/CPU operating detection reset flag and the counter of CPU operating detection circuit. ■ Low Voltage/CPU Operating Detection Reset Control Register (LVRC) Figure 19.3-1 Low Voltage/CPU operating Detection Reset Control Register (LVRC) Address 006EH bit7 bit6 bi t5 bit4 Reserved Reserved Reserved Reserved R/W R/W R/W R/W bit3 W R/W LVRF 0 1 CL 0 1 376 bit0 LVRF Reserved CPUF 0 1 :Initial value bit1 CL CPUF R/W:Read Write bit2 Initial value 00111000 b R/W CPU operatign detection flag bit Read Write No overflow Clear CPUF bit Overflow No change, No other effect Low voltage detection flag bit Read Write No detect voltage falling Clear LVRF bit Detect voltage falling No change, No other effect CPU operating detection circuit clear bit Counter clear No change, No other effect Reserved Reserved bit This bit should write "1". Reserved Reserved bit This bit should write "0". CHAPTER 19 LOW VOLTAGE DETECTION/CPU OPERATING DETECTION RESET Table 19.3-1 Functional Description of Low Voltage/CPU operating Detection Reset Control Register Bit name Function bit7/ bit6 Reserved: Reserved bits Note: These bits should write "0". bit5/ bit4 Reserved: Reserved bits Note: These bits should write "1". bit3 CL: CPU operating detection clear bit This bit is a bit that clears the counter of CPU operating detection circuit. When "0" is written in the CL bit, the counter of CPU operating detection circuit is cleared. bit2 LVRF: Low voltage detection flag bit When falling of the power-supply voltage is detected, the LVRF bit is set to "1". This bit is cleared by "0" at write. And even if "1" is written in this bit, the LVRF bit is no effect. This bit is not initialized in internal reset, and it is initialized only by the external reset input. bit1 Reserved: Reserved bit Note: This bit should write "0". bit0 CPUF: CPU When the counter of CPU operating detecting function overflows, the CPUF bit is set to "1". This bit is cleared by "0" at write. And even if "1" is written in this bit, the CPUF bit is no effect. This bit is not initialized in internal reset, and it is initialized only by the external reset input. 377 CHAPTER 19 LOW VOLTAGE DETECTION/CPU OPERATING DETECTION RESET 19.4 Operating of Low Voltage/CPU Operating Detection Reset Circuit The circuit watches the power-supply voltage. When the power supply voltage is lower than the set value, internal reset is generated. In CPU operating detecting function, internal reset is generated without the counter clear at constant intervals. When internal reset is generated by the detection of the low voltage or the out of CPU control, the content of the register is not guaranteed. The program restarts from the address specified by the reset vector after the reset sequence is executed when the low voltage reset is canceled. ■ Operating of Low Voltage/CPU Operating Detection Reset Circuit The low voltage detection reset circuit starts the detection of the low voltage without taking the operating stability wait time after reset is canceled. ■ Operating of CPU Operating Detection Reset Circuit The CPU operating detection reset circuit starts the detection of the CPU operation without taking the operating stability wait time after reset is canceled. Note: The current is consumed during the sleep or stop mode because the low voltage reset circuit always operates. 378 CHAPTER 19 LOW VOLTAGE DETECTION/CPU OPERATING DETECTION RESET 19.5 Notes on Using Low Voltage/CPU Operating Detection Reset Circuit This section explains the note on using the low voltage/CPU operating detection reset circuit. ■ Notes on Using Low Voltage Detection Reset Circuit ● Disabled operating stop from program The low voltage detection reset circuit operates continuously after the power supply is turned on and the operating stabilization wait time passes. Operating can not be stopped with software. ● Operating at STOP mode Low voltage detection reset keeps operating at the STOP mode. Therefore, if a low voltage is detected in the STOP mode, reset is generated and the STOP mode is canceled. ■ Notes on Using CPU Operating Detection Reset Circuit ● Disabled operating stop from program CPU operating detection reset circuit operates continuously after turning on the power supply. Operating cannot be stopped with software. ● Reset generation control of CPU operating detecting function CPU operating detecting function should clear the counter at regular intervals. The counter is cleared by writing "0" to the CL bit of the LVRC register, and the reset generation can be controlled. ● Stop and clear of counter In the mode CPU stops operating, CPU operating detecting function clears the counter and stops operating. ● Operation in sub-oscillation mode The CPU operation detection function will stop operation in sub-oscillation mode. For this reason, also use the watchdog reset function. 379 CHAPTER 19 LOW VOLTAGE DETECTION/CPU OPERATING DETECTION RESET 19.6 Sample Program for Low Voltage/CPU Operating Detection Reset Circuit This section shows the sample program for low voltage/CPU operating detection reset circuit. ■ Sample Program for Low Voltage/CPU Operating Detection Reset Circuit ● Processing specification The counter of CPU operating detecting function is cleared. ● Coding example LVRC EQU 006EH ; Address of low voltage/CPU operating detection reset control register -------------------------------------Main program------------------------------------CSEG ; [CODE SEGMENT] : MOV LVRC,#00110101B : END 380 CHAPTER 20 LIN-UART This chapter explains the functions and operation of LIN-UART. 20.1 Overview of LIN-UART 20.2 Configuration of LIN-UART 20.3 LIN-UART Pins 20.4 LIN-UART Registers 20.5 LIN-UART Interrupts 20.6 LIN-UART Baud Rates 20.7 Operation of LIN-UART 20.8 Notes on Using LIN-UART 381 CHAPTER 20 LIN-UART 20.1 Overview of LIN-UART The LIN-UART with LIN (Local Interconnect Network) - Function is a general-purpose serial data communication interface for performing synchronous or asynchronous communication (start-stop synchronization) with external devices. LIN-UART provides bidirectional communication function (normal mode), master-slave communication function (multiprocessor mode in master/slave systems), and special features for LINbus systems. ■ LIN-UART Functions ● LIN-UART functions LIN-UART is a general-purpose serial data communication interface for transmitting serial data to and receiving data from another CPU and peripheral devices. It has the functions listed in Table 20.1-1 . Table 20.1-1 LIN-UART Functions (1/2) Function Data buffer Full-duplicate double-buffer Serial input Perform oversampling 5 times and determine the received value by majority decision of sampling time (asynchronous mode only) Transfer mode • • Baud rate • Data length • Synchronous to clock (selecting start/stop synchronous or start/stop bit) Asynchronous (start/stop bits can be used.) Dedicated baud-rate generator (The baud rate is consisted of 15-bit reload counter.) • An external clock can be inputted and also be adjusted by reload counter. • 7 bits (other than synchronous or LIN mode) 8 bits Signal type NRZ (Non Return to Zero) Start bit timing Synchronization to the falling edge of the start bit in the asynchronous mode Detection of receive error • Framing error Overrun error • Parity error (not supported for operation mode 1) • Interrupt request • Receive interrupt (receive termination, detection of receive error, LIN Synch break detection) Transmit interrupt (transmit data empty) • Interrupt request to ICU (LIN Synch field detection: LSYN) 2 • Both the transmission and reception support EI OS • Master/slave type communication function (multiprocessor mode) This function enables communication between 1 (only use master) and n (slave) (This function supports for the both of master and slave system.) Synchronous mode Master of slave function Pin access Capable of reading the state of serial I/O pin directly 382 CHAPTER 20 LIN-UART Table 20.1-1 LIN-UART Functions (2/2) Function LIN bus option • Master device operation Slave device operation • LIN Synch break detection • LIN Synch break generation • Detection of start/stop edges in LIN Synch field connected to input capture 0 and 1 • Synchronous serial clock Synchronous serial clock can be continuously outputted to SCK pin for synchronous communication with start/stop bits. Clock delay option Special synchronous clock mode for delaying clock (useful to SPI) 383 CHAPTER 20 LIN-UART ■ LIN-UART operation modes The LIN-UART operates in four different modes, which are determined by the MD0- and the MD1-bit of the serial mode register (SMR). Mode 0 and 2 are used for bidirectional serial communication, mode 1 for master/slave communication and mode 3 for LIN master/slave communication. Table 20.1-2 Operation Mode of LIN-UART Operation Mode Data Length No Parity 0 Normal mode 7 or 8 bits 1 Multiprocessor mode 7 or 8 bits-+1 * 2 Normal mode 8 3 LIN mode 8 Synchronous/ Asynchronous Length of Stop Bit Data Bit Format With Parity Asynchronous - 1 bit or 2 bits Asynchronous - Synchronous None, 1 bit, 2 bits Asynchronous 1 bit LSB first MSB first LSB first - : Setting disabled *: +1 is the address/data select bit (A/D) used for controlling communication in multiprocessor mode. The MD1 and MD0 bits of the serial mode register (SMR) determine the operation mode of LIN-UART as shown in the following table: Table 20.1-3 Operation Mode of LIN-UART MD1 0 0 1 1 MD0 0 1 0 1 Mode 0 1 2 3 Type Asynchronous (normal mode) Asynchronous (multiprocessor mode) Synchronous (normal mode) Asynchronous (LIN mode) Note: Mode 1 operation is supported both for master or slave operation of LIN-UART in a master-slave connection system. In Mode 3 the LIN-UART function is locked to 8N1-Format, LSB first. If the mode is changed, LIN-UART cuts off all possible transmission or reception and awaits then new action. 384 CHAPTER 20 LIN-UART ■ LIN-UART interrupt and EI2OS Table 20.1-4 LIN-UART Interrupt and EI2OS Channel Interrupt number Interrupt control register Register name Address Vector table address EI2OS Lower Upper Bank LIN-UART0 reception #35(23H) ICR12 0000BCH FFFF70H FFFF71H FFFF72H *1 LIN-UART0 transmission #36(24H) ICR12 0000BCH FFFF6CH FFFF6DH FFFF6EH *2 LIN-UART1 reception #37(25H) ICR13 0000BDH FFFF68H FFFF69H FFFF6AH *1 LIN-UART1 transmission #38(26H) ICR13 0000BDH FFFF64H FFFF65H FFFF66H *2 *1: EI2OS service is usable if the other interrupt (s) which shares the ICR12 to ICRB and same interrupt vector is (are) not enabled. Detection of receive errors is possible and stop function for EI2OS service is supported. *2: EI2OS service is usable if the other interrupt (s) which shares the ICR12 to ICRB and same interrupt vector is (are) not enabled. 385 CHAPTER 20 LIN-UART 20.2 Configuration of LIN-UART This section provides a short overview on the building blocks of LIN-UART. LIN-UART consists of the following blocks: • Reload Counter • Reception Control Circuit • Reception Shift Register • Reception Data Register (RDR) • Transmission Control Circuit • Transmission Shift Register • Transmission Data Register (TDR) • Error Detection Circuit • Oversampling circuit • Interrupt Generation Circuit • LIN Synch Break/Synch Field Detection Circuit • LIN Synch Break Generation Circuit • Bus Idle Detection Circuit • LIN-UART Serial Mode Register (SMR) • Serial Control Register (SCR) • Serial Status Register (SSR) • Extended Com. Contr. Reg. (ECCR) • Extended Status/Contr. Reg. (ESCR) 386 CHAPTER 20 LIN-UART ■ Block Diagram of LIN-UART Figure 20.2-1 Block Diagram of LIN-UART OTO, EXT, REST CLK PE ORE FRE Transmission clock Reload counter Interrupt generation circuit Reception clock Transmission control circuit Reception control circuit SCKn Pin Start bit detection circuit Transmission start circuit Restart reception reload counter Received bit counter Transmission bit counter Received parity counter Transmission parity counter RBI TBI Reception IRQ SINn Pin TIE RIE LBIE LBD Transmission IRQ TDRE SOTn Oversampling unit Pin RDRF SOTn SINn Internal signal to capture LIN break/ SynchField detection circuit To EI2OS SINn Reception shift register Transmission shift register Transmission start Bus idle detection circuit Error detection PE ORE FRE LIN break generation circuit RDRn LBR LBL1 LBL0 TDRn RBI LBD TBI Internal data bus PE ORE FRE RDRF TDRE BDS RIE TIE SSRn register MD1 MD0 OTO EXT REST UPCL USCKE USOE SMRn register PEN P SBL CL A/D CRE RXE TXE SCRn register LBIE LBD LBL1 LBL0 SOPE SIOP CCO SCES LBR ESCRn register MS SCDE SSM ECCRn RBI TBI n = 0, 1 387 CHAPTER 20 LIN-UART ■ Explanation of the different blocks ● Reload Counter The reload counter is a 15-bit reload counter that functions as the dedicated baud rate generator. It can select external clock or internal clock for the transmitting and receiving clocks. The reload counter has a 15-bit register for the reload value. The actual count of the transmission reload counter can be read via the BGRn0/n1. ● Reception Control Circuit The reception control circuit consists of a received bit counter, start bit detection circuit, and received parity counter. The received bit counter counts reception data bits. When reception of one data item for the specified data length is completed, the received bit counter sets the reception data register full flag. In this case, if the reception interrupt is enabled, the reception interrupt request is generated. The start bit detection circuit detects start bits from the serial input signal and sends a signal to the reload counter to synchronize it to the falling edge of these start bits. The received parity counter calculates the parity of the reception data. ● Reception Shift Register The reception shift register fetches reception data input from the SINn pin, shifting the data bit by bit. When reception is completed, the reception shift register transfers receive data to the RDR register. ● Reception Data Register (RDR) This register retains reception data. Serial input data is converted and stored in this register. ● Transmission Control Circuit The transmission control circuit consists of a transmission bit counter, transmission start circuit, and transmission parity counter. The transmission bit counter counts transmission data bits. When the transmission of one data item of the specified data length is completed, the transmission bit counter sets the transmission data register full flag. In this case, if the transmission interrupt is enabled, the transmission interrupt request is generated. The transmission start circuit starts transmission when data is written to TDR register. The transmission parity counter generates a parity bit for data to be transmitted if parity is enabled. ● Transmission Shift Register The transmission shift register transfers data written to the TDR register to itself and outputs the data to the SOTn pin, shifting the data bit by bit. ● Transmission Data Register (TDR) This register sets transmission data. Data written to this register is converted to serial data and outputted. ● Error Detection Circuit The error detection circuit checks if there was any error during the last reception. If an error has occurred it sets the corresponding error flags. 388 CHAPTER 20 LIN-UART ● Oversampling Circuit The oversampling circuit oversamples the incoming data at the SINn pin for five times in the asynchronous mode. The received value is determined by majority decision of sampling time. It is switched off in synchronous operation mode. ● Interrupt Generation Circuit The interrupt generation circuit administers all cases of generating a reception or transmission interrupt. If a corresponding interrupt enable bit is set, the interrupt will be generated immediately. ● LIN synch Break and Synchronization Field Detection Circuit The LIN break and LIN synchronization field detection circuit detects a LIN synch break if a LIN master node is sending a message header. If a LIN synch break is detected LBD flag bit is generated. The first and the fifth falling edge of the LIN synchronization field is recognized by this circuit by generating an internal signal for the Input Capture Unit to measure the actual serial clock synchronization of the transmitting master node. ● LIN Synch Break Generation Circuit The LIN break generation circuit generates a LIN synch break of a determined length. ● Bus Idle Detection circuit The bus idle detection circuit recognizes if neither reception nor transmission is going on. In this case, the circuit generates the special flag bits TBI and RBI. ● LIN-UART Serial Mode Register (SMR) This register performs the following operations: • Selecting the LIN-UART operation mode • Selecting a clock input source • Selecting if an external clock is connected "one-to-one" or connected to the reload counter • Resetting dedicated reload timer • Resetting the LIN-UART software (preserving the settings of the registers) • Specifying whether to enable serial data output to the corresponding pin • Specifying whether to enable clock output to the corresponding pin 389 CHAPTER 20 LIN-UART ● Serial Control Register (SCR) This register performs the following operations: • Specifying whether to provide parity bits • Selecting parity bits • Specifying a stop bit length • Specifying a data length • Selecting a frame data format in mode 1 • Clearing the error flags • Specifying whether to enable transmission • Specifying whether to enable reception ● Serial Status Register (SSR) This register performs the following functions; • Indicating status of receive/transmit operations and errors • Specifying LSB first or MSB first • Receive interrupt enable/disable • Transmit interrupt enable/disable ● Extended Communication Control Register (ECCR) This register performs the following functions; • Indicating bus idle detection • Specifying synchronous clock • Specifying LIN synch break generation ● Extended Status/Control Register (ESCR) This register performs the following functions; • LIN synch break interrupt enable/disable • Indicating LIN synch break detection • Specifying LIN synch break length • Directly accessing SINn and SOTn pins • Specifying continuous clock output operation in LIN-UART synchronous clock mode • Specifying sampling clock edge 390 CHAPTER 20 LIN-UART 20.3 LIN-UART Pins This section describes the LIN-UART pins and provides a pin block diagram. ■ LIN-UART Pins The LIN-UART pins also serve as general ports. Table 20.3-1 lists the pin functions, I/O formats, and settings required to use LIN-UART. Table 20.3-1 LIN-UART Pin Pin Name P82/SIN0 P85/SIN1 Pin Function I/O Format Port I/O or serial data input Standby Control CMOS output/CMOS, Provided Automotive input Setting Required to Use Pin Set as input port (DDR: corresponding bit = 0) P83/SOT0 Port I/O or serial P86/SOT1 data output Set to output enable mode (SMRn: SOE = 1) P84/SCK0 Port I/O or serial P87/SCK1 clock input/output Set as an input port when a clock is inputted (DDR: corresponding bit = 0) Set to output enable mode when a clock is outputted (SMRn: SCKE = 1) See "3. DC Characteristics in ELECTRICAL CHARACTERISTICS" in the data sheet for the standard value. ■ Block Diagram of LIN-UART Pins Figure 20.3-1 Block Diagram of LIN-UART Pins Resource input* Port data register (PDR) Resource output* Resource output enable Internal data bus PDR read Output write Pch PDR read Pin Port direction register (DDR) Nch Direction latch General-purpose I/O pin/SIN General-purpose I/O pin/SCK General-purpose I/O pin/SOT DDR write Standby control (SPL = 1) DDR read Standby control: Stop mode (SPL=1), watch mode (SPL=1), timebase timer mode (SPL=1) *: Resource I/O signals are inputted or outputted from pins having peripheral functions. 391 CHAPTER 20 LIN-UART 20.4 LIN-UART Registers The following figure shows the LIN-UART registers. ■ LIN-UART Registers Figure 20.4-1 LIN-UART Registers • LIN-UART0 Address: bit 15 bit 8 bit 7 bit 0 000021H 000020H SCR0 (serial control register) SMR0 (serial mode register) 000023H 000022H SSR0 (serial status register) RDR0/TDR0 (reception data register/transmission data register) 000025H 000024H ESCR0 (Extended status control register) ECCR0 (Extended communication control register) 000027H 000026H BGR01 (Baud rate generator register) BGR00 (Baud rate generator register) • LIN-UART1 Address: 000029H bit 15 000028H bit 8 bit 7 SCR1 (serial control register) bit 0 SMR1 (serial mode register) 00002BH 00002AH SSR1 (serial status register) RDR1/TDR1 (reception data register/transmission data register) 00002DH 00002CH ESCR1 (Extended status control register) ECCR1 (Extended communication control register) 00002FH BGR10(Baud rate generator register) 392 00002EH BGR11(Baud rate generator register) CHAPTER 20 LIN-UART 20.4.1 Serial Control Register (SCR) This register specifies parity bits, selects the stop bit and data lengths, selects a frame data format in mode 1, clears the reception error flag, and specifies whether to enable transmission and reception. ■ Serial Control Register (SCR) Figure 20.4-2 Configuration of the Serial Control Register (SCR) Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 SCR0 : 000021H PEN P SBL CL AD CRE RXE TXE SCR1 : 000029H R/W R/W R/W R/W R/W W R/W R/W Initial value bit0 00000000B bit8 TXE Transmission operation enable bit 0 Disable transmission 1 Enable transmission bit9 RXE Reception operation enable bit 0 Disable reception 1 Enable reception bit10 Clear reception error flag bit CRE Write 0 No effect 1 Clear all reception error flags (PE, FRE, ORE) Read Read always returns 0 bit11 AD Address/data format select bit 0 Data frame 1 Address frame bit12 CL Data length select bit 0 7 bits 1 8 bits bit13 SBL Stop bit length select bit 0 1 bit 1 2 bits bit14 P Even parity enabled 1 Odd parity enabled R/W : Read/Write bit15 W : Write only PEN : Initial value Parity select bit 0 Parity enabled bit 0 Parity disabled 1 Parity enabled 393 CHAPTER 20 LIN-UART Table 20.4-1 Function of Each Bit in Serial Control Register (SCR) No. Bit Name Function bit15 PEN: Parity enable bit This bit selects whether to add a parity bit during transmission or detect it during reception. Note: Parity bit is only provided in mode 0 and in mode 2 if SSM of the ECCR is selected to 1. This bit is fixed to 0 (no parity) in mode 3 (LIN). bit14 P: Parity selection bit When parity is provided, this bit selects even (0) or odd (1) parity bit13 SBL: Stop bit length selection bit This bit selects the length of the stop bit of an asynchronous data frame or a synchronous frame if SSM of the ECCR is selected 1. This bit is fixed to 0 (1 stop bit) in mode 3 (LIN). Note: At reception, first stop bit is always detected. bit12 CL: Data length selection bit This bit specifies the length of transmission or reception data. This bit is fixed to 1 (8 bits) in mode 2 and 3. bit11 AD: Address/Data format selection bit This bit specifies the frame data format to be transmitted and received in multiprocessor mode 1. Writing to this bit is provided for a master CPU, reading from it for slave CPU. A 1 indicates an address data frame, a 0 indicates a usual data frame. The reading value is a value of last received data format. Note: Please read the hints about using this bit in "20.8 Notes on Using LIN-UART". bit10 CRE: Clear reception error flag bit This bit clears the FRE, ORE, and PE flags of the Serial Status Register (SSR). Writing a 1 to it clears the error flag. Writing a 0 has no effect. Reading from it always returns 0. Note; Clear reception error flags after the receive operation. bit9 RXE: Reception operation enable bit This bit enables/disables LIN-UART reception. If this bit is set to 0, LIN-UART disables the reception of data frames. If this bit is set to 1, LIN-UART enables the reception of data frames. The LIN synch break detection in mode 3 remains unaffected. Note: If reception is disabled (RXE=0) during receiving, it is stopped immediately. In this case, data is not guaranteed. bit8 TXE: Transmission operation enable bit This bit enables/disables LIN-UART transmission. If the bit is set to 0, LIN-UART disables the transmission of data frames. If the bit is set to 1, LIN-UART enables the transmission of data frames. Note: If transmission is disabled (TXE=0) during transmitting, it is stopped immediately. In this case, data is not guaranteed. 394 CHAPTER 20 LIN-UART 20.4.2 LIN-UART Serial Mode Register (SMR) This register selects an operation mode and baud rate clock and specifies whether to enable output of serial data and clocks to the corresponding pin. ■ LIN-UART Serial Mode Register (SMR) Figure 20.4-3 Configuration of the Serial Mode Register (SMR) Address SMR0:000020H SMR1:000028H bit15 bit8 bit7 bit6 bit5 bit4 bit2 bit3 bit1 bit0 Initial value MD1 MD0 OTO EXT REST UPCL SCKE SOE 00000000B R/W R/W R/W R/W W W R/W R/W bit0 SOE Serial data output enable bit of LIN-UART 0 General-purpose I/O port 1 Serial data output enable pin of LIN-UART bit1 SCKE LIN-UART serial clock output enable bit 0 General-purpose I/O port or LIN-UART clock input pin 1 Serial clock output pin of LIN-UART bit2 LIN-UART programmable clear bit UPCL write 0 Ignored 1 Reset LIN-UART read always read 0 bit3 Restart dedicated Reload Counter bit REST write 0 Ignored 1 Restart Counter read always read 0 bit4 EXT External Serial Clock Source select bit 0 Use internal Baud Rate Generator (Reload Counter) 1 Use external Serial Clock Source bit5 R/W W OTO One-to-one external clock Input enable bit 0 Use external Clock with Baud Rate Generator (Reload Counter) 1 Use external Clock as it is bit7 bit6 MD1 MD0 0 0 Mode 0: Asynchronous normal : Read/Write 0 1 Mode 1: Asynchronous Multiprocessor : Write only 1 0 Mode 2: Synchronous 1 1 Mode 3: Asynchronous LIN Operation Mode Setting bit : Initial value 395 CHAPTER 20 LIN-UART Table 20.4-2 Function of Each Bit in Serial Mode Register (SMR) No. Bit name Function bit7, bit6 MD1, MD0: Operation mode setting bits These two bits set the LIN-UART operation mode. bit5 OTO: One-to-one external clock input enable bit This bit sets an external clock directly to the LIN-UART serial clock by writing "1". This function is used for operating mode 2 (synchronous) slave mode operation (ECCR:MS=1). When EXT=0, this bit is fixed to "0". bit4 EXT: External serial clock source selection bit This bit selects the clock input. When "0" is set to this bit, it selects the clock of internal baud rate generator (reload counter). When "1" is set to it, it selects the external serial clock source. bit3 REST: Restart of dedicated reload counter bit If a 1 is written to this bit, the reload counter is restarted. Writing 0 to it has no effect. Reading from this bit always returns 0. bit2 UPCL : LIN-UART programmable clear bit (LIN-UART software reset) Writing a 1 to this bit resets LIN-UART immediately (LIN-UART software reset). The register settings are preserved. Possible reception or transmission will cut off. All flags (TDRE, RDRF, LBD, PE, ORE, FRE) are cleared. Reset the LINUART after disabling the interrupt and transmission. Also, when the reception data register is cleared (RDR = 00H), the reload counter restarts. Writing 0 to this bit has no effect. Reading from it always returns 0. bit1 SCKE: LIN-UART serial clock output enable bit This bit controls the serial clock I/O ports. When this bit is 0, SCKn pin operates as general-purpose I/O port or serial clock input pin. When this bit is 1, the pin operates as serial clock output pin and outputs clock in operating mode 2 (synchronous). Note: When using SCKn pin as serial clock input (SCKE=0) pin, set the corresponding DDR bit of general-purpose port as input port. Also, select external clock (EXT = 1) using the external clock selection bit. Reference: When the SCKn pin is assigned to serial clock output (SCKE=1), it functions as the serial clock output pin regardless of the status of the general-purpose I/ O ports. bit0 SOE: LIN-UART serial data output enable bit This bit enables or disables the output of serial data. When this bit is 0, SOTn pin operates as general-purpose I/O port. When this bit is 1, SOTn pin operates as serial data output pins (SOTn). Reference: When the output of serial data is enabled (SOE=1), SOTn pin functions as serial data output pin (SOTn) regardless of the status of general-purpose I/O ports. 396 CHAPTER 20 LIN-UART 20.4.3 Serial Status Register (SSR) This register checks the transmission and reception status and error status, and enables and disables the transmission and reception interrupts. ■ Serial Status Register (SSR) Figure 20.4-4 Configuration of the Serial Status Register (SSR) Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 SSR0:000023H SSR1:00002BH PE ORE FRE RDRF TDRE BDS RIE TIE R R R R R bit0 Initial value 00001000B R/W R/W R/W bit8 TIE Transmission interrupt request enable bit 0 Disables transmission interrupt 1 Enables transmission interrupt bit9 RIE Reception interrupt request enable bit 0 Disables reception interrupt 1 Enables reception interrupt bit10 BDS Transfer direction selection bit 0 LSB first (transfer from lowest bit) 1 MSB first (transfer from highest bit) bit11 TDRE Transmission data empty flag bit 0 Transmission data register is full. 1 Transmission data register is empty. bit12 RDRF Reception data full flag bit 0 Reception data register is empty 1 Reception data register is full bit13 FRE Framing error flag bit 0 No framing error occurred 1 A framing error occurred bit14 ORE Overrun error flag bit 0 No overrun error occurred 1 An overrun error occurred bit15 PE R/W : Read/Write R : Read only Parity error flag bit 0 No parity error occurred 1 A parity error occurred : Initial value 397 CHAPTER 20 LIN-UART Table 20.4-3 Function of Each Bit in Serial Status Register (SSR) No. Bit name Function bit15 PE: Parity error flag bit • bit14 ORE: Overrun error flag bit • This bit bit13 FRE: Framing error flag bit • bit12 RDRF: Receive data full flag bit • TDRE: Transmission data empty flag bit • bit10 BDS: Transfer direction selection bit • This bit selects whether to transfer serial data from the least significant bit (LSB first, BDS=0) or the most significant bit (MSB first, BDS=1). Note: The high-order and low-order sides of serial data are interchanged with each other during reading from or writing to the serial data register. If this bit is set to another value after the data is written to the RDR register, the data becomes invalid. This bit is fixed to "0" in mode 3 (LIN). bit9 RIE: Reception interrupt request enable bit • TIE: Transmission request interrupt enable bit • bit11 bit8 398 This bit is set to 1 when a parity error occurs during reception at PE=1 and is cleared when 1 is written to the CRE bit of the LIN-UART serial control register (SCR). • A reception interrupt request is outputted when this bit and the RIE bit are 1. • Data in the reception data register (RDR) is invalid when this flag is set. is set to 1 when an overrun error occurs during reception and is cleared when 1 is written to the CRE bit of the LIN-UART serial control register (SCR). • A reception interrupt request is outputted when this bit and the RIE bit are 1. • Data in the reception data register (RDR) is invalid when this flag is set. This bit is set to 1 when a framing error occurs during reception and is cleared when 1 is written to the CRE bit of the LIN-UART serial control register (SCR). • A reception interrupt request is outputted when this bit and the RIE bit are 1. • Data in the reception data register (RDR) is invalid when this flag is set. This flag indicates the status of the reception data register (RDR). This bit is set to 1 when reception data is loaded into RDR and can only be cleared to 0 when the reception data register (RDR) is read. • A reception interrupt request is outputted when this bit and the RIE bit are 1. • This flag indicates the status of the transmission data register (TDR). This bit is cleared to 0 when transmission data is written to TDR and indicates that valid data exists in TDR. This bit is set to 1 when data is loaded into the transmission shift register and transmission start and indicates that no valid data exists in TDR. • A transmission interrupt request is generated if both this bit and the TIE bit are 1. • If the LBR bit in the ECCR register is set to "1" while the TDRE bit is "1", then this bit once changes to "0". After the completion of LIN synch break generator, the TDRE bit changes back to "1". Note: This bit is set to 1 (TDR empty) as its initial value. • • • This bit enables or disables the reception interrupt request output to the CPU. If any of the RDRF, PE, ORE and FRE bits is set to "1" and this bit is "1", then a reception interrupt request is outputted. This bit enables or disables the transmission interrupt request output to the CPU. A transmission interrupt request is outputted when this bit and the TDRE bit are 1. CHAPTER 20 LIN-UART 20.4.4 Reception and Transmission Data Register (RDR/TDR) Both RDR and TDR registers are located at the same address. At reading, it functions as the reception data register. At writing, it functions as the transmission data register. ■ Reception Data Register (RDR) Figure 20.4-5 Transmission and Reception Data Registers (RDR/TDR) Address RDR0/TDR0: 000022H RDR1/TDR1: 00002AH bit 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Initial value 00000000B R/W R/W R/W R/W R/W R/W R/W R/W bit7 to bit0 R/W R/W: Read/Write Data register Read Read from reception data register Write Write to transmission data register RDR is the data buffer register for serial data reception. The serial data signal transmitted to the SINn pin is converted in the shift register and stored in RDR register. When the data length is 7 bits, the uppermost bit (RDR: D7) contains 0. When the data is stored in this register and the reception data full flag bit (SSR: RDRF) is set to 1. If a reception interrupt request is enabled (SSR: RIE=1) at this point, a reception interrupt occurs. Read RDR when the RDRF bit of the serial status register (SSR) is 1. The RDRF bit is cleared automatically to 0 when RDR is read. Also the reception interrupt is cleared if it is enabled and no error has occurred. Data in RDR is invalid when a reception error occurs (SSR: PE, ORE, or FRE = 1). 399 CHAPTER 20 LIN-UART ■ Transmission Data Register (TDR) TDR is the data buffer register for serial data transmission. When data to be transmitted is written to the transmission data register (TDR) in transmission enable state (SCR: TXE=1), it is transferred to the transmission shift register, then converted to serial data, and transmitted from the serial data output pin (SOTn pin). If the data length is 7 bits, the uppermost bit (TDR: D7) is invalid data. When transmission data is written to this register, the transmission data empty flag bit (SSR: TDRE) is cleared to 0. When transfer to the transmission shift register is completed and transmission starts, the bit is set to 1. When the TDRE bit is 1, the next part of transmission data can be written. If transmission interrupt requests have been enabled, a transmission interrupt is generated. Write the next part of transmission data when a transmission interrupt is generated or the TDRE bit is 1. Note: TDR is a write-only register and RDR is a read-only register. These registers are located in the same address, so the read value is different from the write value. Therefore, instructions that perform a readmodify-write (RMW) operation, such as the INC/DEC instruction, cannot be used. 400 CHAPTER 20 LIN-UART 20.4.5 Extended Status/Control Register (ESCR) This register provides several LIN functions, direct access to the SINn and SOTn pins and setting of continuous clock output and sampling clock edge in LIN-UART synchronous clock mode. ■ Extended Status/control Register (ESCR) Figure 20.4-6 shows the Configuration of the extended status/control register (ESCR), and Table 20.4-4 shows the function of each bit. Figure 20.4-6 Configuration of the Extended Status/control Register (ESCR) Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 ESCR0 : 000025H LBIE LBD LBL1 LBL0 SOPE SIOP CCO SCES ESCR1 : 00002DH R/W R/W R/W R/W R/W R/W R/W R/W bit 0 Initial value 00000100B bit 8 SCES 0 1 Sampling Clock Edge Selection Bit (Mode 2) Sampling on rising clock edge (normal) Sampling on falling clock edge (inverted clock) bit 9 CCO 0 1 Continuous Clock Output Enable Bit (Mode 2) Continuous Clock Output disabled Continuous Clock Output enabled bit 10 SIOP 0 1 Serial Input/Output Pin Access write (SOPE = "1") read SOTn pin is forced to "0" Reading the actual value of SINn pin SOTn pin is forced to "1" bit 11 SOPE 0 1 Serial Output pin direct Access Enable Bit Serial Output pin direct access disable Serial Output pin direct access enable bit 12 LBL0 0 1 0 1 bit 13 LBL1 0 0 1 1 LIN Synch break length select bit LIN break length 13-bit times LIN break length 14-bit times LIN break length 15-bit times LIN break length 16-bit times bit 14 LBD 0 1 R/W × : Read/Write : Undefined bit 15 LBIE 0 1 LIN Synch break detected flag bit write read Clear LIN synch break detected No LIN synch break flag detected Ignored LIN synch break detected LIN Synch break detection Interrupt enable bit LIN Synch break detection interrupt disable LIN Synch break detection interrupt enable : Initial value 401 CHAPTER 20 LIN-UART Table 20.4-4 Function in Each Bit of the Extended Status/control Register (ESCR) NO. Bit name Function bit15 LBIE: LIN synch break detection interrupt enable bit This bit enables/disables LIN synch break detection interrupt. When the LBD bit is set to 1 and this bit is "1", a interrupt is generated. This bit is fixed to "0" in operation mode 1 and 2. bit14 LBD: LIN synch break detected flag bit This bit goes 1 if a LIN synch break was detected in operating mode 3. Writing a 0 to it clears this bit and the corresponding interrupt, if it is enabled. Read-modify-write instructions always return 1. Note that this dose not indicate a LIN synch break detection. Note: When LIN synch break detection is performed, disable reception (SCR: RXE=0) after enable LIN synch break detection interrupt (LBIE=1). bit13, bit12 LBL1/0: LIN synch break length selection bits These two bits determine how many serial bit times the LIN synch break is generated by LIN-UART. Receiving a LIN synch break is always fixed to 11 bit times. bit11 SOPE: Serial Output pin direct access enable bit * Setting this bit to 1 enables the direct write to the SOTn pin, if SOE = 1 (SMR). * bit10 SIOP: Serial Input/Output Pin direct access bit * Normal read instructions always return the actual value of the SINn pin. Writing to it sets the bit value to the SOTn pin, if SOPE = 1. During a ReadModify-Write instruction the bit returns the SOTn value in the read cycle. * bit9 CCO: Continuous Clock Output enable bit This bit enables a continuous serial clock output at the SCKn pin if LINUART operates in master operation mode 2 (synchronous) and the SCKn pin is configured as a clock output. <Note> When CCO bit is "1", use SSM bit of ECCR as setting to "1". bit8 SCES: Sampling clock edge selection bit This bit inverts the serial clock signal in operation mode 2 (synchronous communication). Receiving data is sampled at the falling edge of the internal clock. If the MS bit of the ECCR register is "0" (master mode) and the SCKE bit of the SMR register is "1" (clock output enabled), the output clock signal is also inverted. During operation mode 0,1,3, please set this bit to 0. *: Refer to the following table. Table 20.4-5 Description of the Interaction of SOPE and SIOP SOPE SIOP Writing to SIOP Reading from SIOP 0 R/W Has no effect on SOTn, but holds the written value Returns current value of SINn 1 R/W Write "0" or "1" to SOTn Returns current value of SINn 1 RMW Reads current value of SOTn and write it back 402 CHAPTER 20 LIN-UART 20.4.6 Extended Communication Control Register (ECCR) The extended communication control register (ECCR) provides bus idle detection, synchronous clock settings, and the LIN synch break generation. ■ Extended Communication Control Register (ECCR) Figure 20.4-7 shows the configuration of the extended communication control register (ECCR), and Table 20.4-6 shows the function of each bit. Figure 20.4-7 Configuration of the Extended Communication Control Register (ECCR) Address bit 15 ECCR0:000024H ECCR1:00002CH bit 8 bit 7 − bit 6 bit 5 LBR MS W R/W bit 4 bit 3 bit 2 SCDE SSM R/W R/W − bit 1 bit 0 RBI TBI R R Initial value 000000XXB bit 0 TBI* 0 1 Transmission bus idle detection flag bit Transmission is ongoing No transmission activity bit1 RBI* 0 1 Reception bus idle detection flag bit Reception is ongoing No reception activity bit 2 Unused bit Reading value is undefined. Always write "0". bit 3 SSM 0 1 bit 4 SCDE 0 1 bit 5 MS 0 1 Start/stop bit mode enable bit in mode 2 No start/stop bit Enable start/stop bit Serial Clock Delay enable bit in mode 2 Disable clock delay Enable clock delay Master/Slave mode selection bit in mode 2 Master mode (generating serial clock) Slave mode (receiving external serial clock) bit 6 LBR 0 1 R/W R W X : Read/Write : Read only : Write only : Undefined Generating LIN synch break bit write read Ignored Generate LIN Synch break Always read 0 bit 7 Unused bit Read value is undefined. Always write 0 : Initial value *: Not used in operation mode 2 when SSM = 0 403 CHAPTER 20 LIN-UART Table 20.4-6 Function of Each Bit in the Extended Communication Control Register (ECCR) NO. Bit name Function bit7 Unused bit This bit is unused bit. Reading bit is undefined. Always write "0". bit6 LBR: Lin Synch break Generating bit Writing a 1 to this bit generates a LIN synch break of the length selected by the LBL0/LBL1 bits of the ESCR, if operation mode 3 is selected. Setting to "0" in operation mode 0. bit5 MS: Master/Slave mode selection bit in mode 2 This bit selects master or slave mode of LIN-UART in synchronous mode 2. If master is selected LIN-UART generates the synchronous clock by itself. If slave mode is selected, LINUART receives external serial clock. This bit is fixed to "0" in operation mode 0, 1 and 3. Change this bit, when the SCR: TXE bit is "0". Note: If slave mode is selected, the clock source must be external and enabled the external clock input (SMR: SCKE = 0, EXT = 1, OTO = 1). bit4 SCDE: Serial clock delay enable bit in mode 2 If this bit is set to 1 the serial output clock is delayed as shown in Figure 20.7-5 if LIN-UART operates in master mode 2. This bit is enabled to SPI. This bit is fixed to "0" in operation mode 0, 1, and 3. bit3 SSM: Start/Stop bit mode enable bit in mode 2 This bit adds start and stop bits to the synchronous data format in operation mode 2. It is ignored in mode 0, 1, and 3. This bit is fixed to "0" in operation mode 0, 1, and 3. bit2 Unused bit Unused bit. Reading value is undefined. Always write to "0". bit1 RBI: Reception bus idle detection flag bit This bit is "1" if there is no reception activity on the SINn pin and it is kept at "H". Do not use this bit in mode 2 when SSM=0. bit0 TBI: Transmission bus idle detection flag bit This bit is "1" if there is no transmission activity on the SOTn pin. Do not use this bit in mode 2 when SSM=0. 404 CHAPTER 20 LIN-UART 20.4.7 Baud Rate Generator Register 0 and 1 (BGR0/1) The baud rate generator registers set the division ratio for the serial clock. Also, the actual count of the transmission reload counter can be read. ■ Baud Rate Generator Register (BGRn0/n1) Figure 20.4-8 shows the configuration of the baud rate generator register (BGRn0/n1). Figure 20.4-8 Configuration of Baud Rate Generator Register (BGRn0/n1) Address BGR00: 000026H BGR01: 000027H BGR10: 00002EH BGR11: 00002FH Initial value bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 D14 D13D12 D11D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 00000000B 00000000B R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W bit 7 to 0 BGRn0 write read Baud rate Generator Register n0 Write bit 7 to 0 of reload value to counter Read bit 7 to 0 of transmission reload counter bit 14 to 8 BGRn1 write read Baud rate Generator Register n1 Write bit 14 to 8 of reload value to counter Read bit 14 to 8 of transmission reload counter bit 15 Unused bit read Returns "0" R/W : Read/Write R : Read only n = 0, 1 The baud rate generator registers determine the division ratio for the serial clock. The BGRn1 corresponds to the upper bit and BGRn0 to lower bit, writing of the reload value to counter and reading of the transmission reload counter value are allowed. Also, byte and word access are enabled. When writing the reload value to the baud rate generator register, the reload counter starts counting. 405 CHAPTER 20 LIN-UART 20.5 LIN-UART Interrupts LIN-UART uses both reception and transmission interrupts. An interrupt request can be generated for either of the following causes: • Receive data is set in the reception data register (RDR), or a reception error occurs. • Transmission data is transferred from the transmission data register (TDR) to the transmission shift register and transmission is started. • A LIN break is detected. The extended intelligent I/O service (EI2OS) is available for these interrupts. ■ LIN-UART Interrupts Table 20.5-1 shows the interrupt control bits and interrupt cause of the LIN-UART. Table 20.5-1 Interrupt Control Bits and Interrupt Cause of LIN-UART Reception/ transmission /ICU Reception Interrupt request flag bit Flag register Operation mode 0 1 2 Interrupt cause 3 RDRF SSR ❍ ❍ ❍ ❍ Receive data is written to RDR. ORE SSR ❍ ❍ ❍ ❍ Overrun error Interrupt How to clear the cause enable interrupt request bit SSR:RIE Receive data is read. "1" is written to clear reception error flag bit (SCR: CRE). FRE SSR ❍ ❍ ∆ ❍ Framing error PE SSR ❍ × ∆ × Parity error LBD ESCR × × × ❍ LIN Synch break detected ESCR:LBIE "0" is written to ESCR: LBD. Transmission TDRE SSR ❍ ❍ ❍ ❍ TDR empty SSR:TIE Write data to TDR Input Capture ICP0/ICP1 ICS01 × × × ❍ 1st falling edge of ICS01: LIN synch field ICE0/ICE1 ICP0/ICP1 ICS01 × × × ❍ 5th falling edge of LIN synch field ❍: Used bit ×: Unused bit ∆: Only available if ECCR/SSM = 1 406 Disable ICP0/ ICP1 temporary CHAPTER 20 LIN-UART ● Reception Interrupt If one of the following events occurs in reception mode, the corresponding flag bit of the serial status register (SSR) is set to "1": • Data reception is completed, i. e. the received data was transferred from the serial input shift register to the reception data register (RDR) and data can be read: RDRF • Overrun error, i. e. RDRF = 1 and RDR was not read by the CPU and next serial data is received: ORE • Framing error, i. e. a stop bit was expected, but a "0"-bit was received: FRE • Parity error, i. e. a wrong parity bit was detected: PE If at least one of these flag bits above go "1" and the reception interrupt is enabled (SSR: RIE = 1), a reception interrupt request is generated. If the reception data register (RDR) is read, the RDRF flag is automatically cleared to "0". The error flags are cleared to "0", if a "1" is written to the clear reception error (CRE) flag bit of the serial control register (SCR). Note: The CRE flag is "write only" and by writing a "1" to it, it is internally held to "1" for one clock cycle. ● Transmission Interrupt If transmission data is transferred from the transmission data register (TDR) to the transfer shift register and transfer is started, the transmission data empty flag bit (TDRE) of the serial status register (SSR) is set to "1". In this case an interrupt request is generated, if the transmission interrupt enable (TIE) bit of the SSR was set to "1" before. Note: The initial value of TDRE (after hardware or software reset) is "1". So an interrupt is generated immediately then, if the TIE flag is set to "1". Also note, that the only way to reset the TDRE flag is writing data to the transmission data register (TDR). ● LIN Synchronization Break Interrupt This paragraph is only relevant, if LIN-UART operates in mode 3 as a LIN slave. If the bus (serial input) goes "0" (dominant) for more than 11 bit times, the LIN synch break detected (LBD) flag bit of the extended status/control register (ESCR) is set to "1". Note, that in this case after 9 bit times the reception error flags are set to "1", therefore the RXE flag has to set to "0", if only a LIN synch break detect is desired. The LIN synch break interrupt and the LBD flag are cleared after writing a "0" to the LBD flag. The LBD flag has to be performed before input capture interrupt for LIN synch field. When LIN synch break detection is performed, it is necessary to disable the reception (SCR: RXE=0). 407 CHAPTER 20 LIN-UART ● LIN Synchronization Field Edge Detection Interrupts This paragraph is only relevant, if LIN-UART operates in mode 3 as a LIN slave. After LIN synch break detection, the internal signal is set to "1" at first falling edge of the LIN synch field and to "0" after fifth falling edge. When the internal signal is set in the capture side to be inputted to capture (ICV0/1) and to be detected both edges, the interrupt occurs if the capture interrupt is enabled. The difference of the count values detected in the capture is serial clock 8 bits for master, and new baud rate can be calculated. When the falling edge of the start bit is detected, the reload counter restarts automatically. ■ LIN-UART Interrupts and EI2OS Table 20.5-2 LIN-UART Interrupts and EI2OS Channel Interrupt number Interrupt control register Register name Address Vector table address EI2OS Lower Upper Bank LIN-UART0 reception #35(23H) ICR12 0000BCH FFFF70H FFFF71H FFFF72H *1 LIN-UART0 transmission #36(24H) ICR12 0000BCH FFFF6CH FFFF6DH FFFF6EH *2 LIN-UART1 reception #37(25H) ICR13 0000BDH FFFF68H FFFF69H FFFF6AH *1 LIN-UART1 transmission #38(26H) ICR13 0000BDH FFFF64H FFFF65H FFFF66H *2 *1: Usable when ICR12 and ICR13 or interrupt causes that share an interrupt vector are not used. Provided with a function that detects a LIN-UART reception error and stops EI2OS. *2: Usable when ICR12 and ICR13 or interrupt causes that share an interrupt vector are not used. ■ LIN-UART EI2OS functions LIN-UART has a circuit for operating EI2OS, which can be started up for either reception or transmission interrupts. ● For Reception EI2OS can be used if other interrupt is not enabled because the UART shares the interrupt control registers with transmission interrupt and other UART. ● For Transmission LIN-UART shares the interrupt control registers with the LIN-UART reception interrupts and other UART. Therefore, EI2OS can be started up only when no LIN-UART reception interrupts are used. 408 CHAPTER 20 LIN-UART 20.5.1 Reception Interrupt Generation and Flag Set Timing The following are the reception interrupt causes: completion of reception (SSR: RDRF) and occurrence of a reception error (SSR: PE, ORE, or FRE). ■ Reception Interrupt Generation and Flag Set Timing The received data is stored in the RDR register if the first stop bit is detected in mode 0, 1, 2 (if SSM = 1), 3, or the last data bit was read in mode 2 (if SSM = 0). Each flag is set if the received data is completed (RDRF = 1) and the reception error (PE, ORE, FRE) of the Serial Status Register (SSR) was set to "1". In this case, if the reception interrupt is enabled (SSR: RIE=1), reception interrupt occurs. Note: If a reception error has occurred, the Reception Data Register (RDR) contains invalid data in each mode. Figure 20.5-1 shows the reception operation and flag set timing. Figure 20.5-1 Reception Operation and Flag Set Timing Receive data (mode 0/3) ST D0 D1 D2 ... D5 D6 D7/P SP ST Receive data (mode 1) ST D0 D1 D2 ... D6 D7 A/D SP ST D0 D1 D2 ... D4 D5 D6 D7 D0 Receive data (mode 2) PE*1, FRE RDRF ORE*2 (RDRF = "1") Reception interrupt occurs *1: The PE flag will always remain "0" in mode 1 or 3. *2: ORE only occurs, if next data is transferred before the reception data is read (RDRF=1). ST: Start Bit SP: Stop Bit A/D: Mode 1 (multiprocessor) address/data selection bit Note: The example in Figure 20.5-1 does not show all possible reception options for mode 0. Here it is: "7p1" and "8N1" (p = "E" [even] or "O" [odd]). 409 CHAPTER 20 LIN-UART Figure 20.5-2 ORE Flag Set Timing: Reception data RDRF ORE 410 CHAPTER 20 LIN-UART 20.5.2 Transmission Interrupt Generation and Flag Set Timing A transmission interrupt is generated when the transmission data is transferred from transmission data register (TDR) to transmission shift register and transmission is started. ■ Transmission Interrupt Generation and Flag Set Timing When the data written to the TDR register is transferred to the transmission shift register and the transmission is started, next data to be written is enabled (SSR: TDRE=1). Then, if transmission interrupt is enabled (SSR: TIE=1), the transmission interrupt occurs. Because the TDRE bit is "read only", it only can be cleared to "0" by writing data into TDR. The following figure demonstrates the transmission operation and flag set timing for the four modes of LIN-UART. Figure 20.5-3 Transmission Operation and Flag Set Timing Transmission interrupt occurs Transmission interrupt occurs Mode 0, 1 or 3: write to TDR TDRE Serial output ST D0 D1 D2 D3 D4 D5 D6 D7 Transmission interrupt occurs P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP AD AD Transmission interrupt occurs Mode 2 (SSM = 0): write to TDR TDRE Serial output D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 ST: Start bit D0 ... D7: data bits P: Parity SP: Stop bit AD: Address/data selection bit (mode1) Note: The example in Figure 20.5-3 does not show all possible transmission options for mode 0. Here it is: "8p1" (p = "E" [even] or "O" [odd]). Parity is not provided in mode 3 or 2, if SSM = 0. 411 CHAPTER 20 LIN-UART ■ Transmission interrupt request generation timing If the TDRE flag is set to "1" when a transmission interrupt is enabled (SSR: TIE=1), transmission interrupt is generated. Note: A transmission interrupt is generated immediately after the transmission interrupt is enabled (SSR: TIE=1) because the TDRE bit is set to 1 as its initial value. TDRE is a read-only bit that can be cleared only by writing new data to the transmission data register (TDR). Carefully specify the transmission interrupt enable timing. 412 CHAPTER 20 LIN-UART 20.6 LIN-UART Baud Rates One of the following can be selected for the LIN-UART transmission/reception clock source: • Dedicated baud rate generator (Reload Counter) • Input external clock to baud rate generator (Reload Counter) • External clock (directly use SCKn pin input clock) ■ LIN-UART Baud Rate Selection The baud rate selection circuit is designed as shown below. One of the following three types of baud rates can be selected: ● Baud rates determined using the dedicated baud rate generator (reload counter) with internal clock LIN-UART has two independent internal reload counters for transmission and reception serial clock. The baud rate can be selected via the 15-bit reload value determined by the Baud Rate Generator Register 0 and 1 (BGR0/1). The reload counter divides the internal clock by set value. It is used in asynchronous or synchronous (master) mode. Internal clock and baud rate generator clock is selected for the setting of clock source (SMR: EXT=0, OTO=0). ● Baud rates determined using the dedicated baud rate generator (reload counter) with external clock An external clock source can also be connected internally to the reload counter. The baud rate can be selected via the 15-bit reload value determined by the baud rate generator register 0 and 1 (BGR 0/1). The reload counter divides the external clock by set value. It is used in asynchronous mode. External clock and baud rate generator clock is selected for the setting of the clock source (SMR: EXT=1, OTO=0). This was designed to use quartz oscillators with special frequencies and having the possibility to divide them. ● Baud rates determined using external clock (one-to-one mode) The clock input from LIN-UART clock pulse input pins (SCKn) is used as it is (synchronous mode 2 slave operation (ECCR: MS=1)). It is used in synchronous mode (slave). External clock and direct use of external clock is selected for the setting of clock source (SMR: EXT=1, OTO=1). 413 CHAPTER 20 LIN-UART Figure 20.6-1 Baud Rate Selection Circuit of LIN-UART Reset Start bit falling edge detection Reload Value: v Reception 15-bit Reload Counter Rxc = 0? Set Reload FF 0 Reception clock Reset Rxc = v/2? 1 Reload Value: v CLK 0 SCKn (external clock input) Transmission 15-bit Reload Counter EXT OTO FF Reload 1 Count Value: TXC Set Txc = 0? 0 Reset Txc = v/2? 1 Transmission clock Internal data bus EXT REST OTO n=0,1 414 SMRn register D14 D13 D12 D11 D10 D9 D8 BGRn1 register D7 D6 D5 D4 D3 D2 D1 D0 BGRn0 register CHAPTER 20 LIN-UART 20.6.1 Setting the Baud Rate This section describes how the baud rates are set and the resulting serial clock frequency is calculated. ■ Calculating the Baud Rate The both 15-bit reload counters are programmed by the baud rate generator registers 1, 0 (BGR1/BGR0). The following calculation formula should be used to set the desired baud rate: Reload Value: v = [Φ / b] - 1, where Φ is the machine clock, b the baud rate and [] gaussian brackets (mathematical rounding function). ● Example of calculation If the machine clock is 16 MHz and the desired baud rate is 19200 bps baud then the reload value v is: v = [16*106 / 19200] - 1 = 832 The exact baud rate can then be recalculated: bexact = Φ / (v + 1), here it is: 16*106 / 833 = 19207.6831 Note: Setting the reload value to 0 stops the reload counter. For this reason the minimum division ratio is 2. For asynchronous communication, the reload value must be greater than equal to 4 because 5 times over-sampling is performed to determine the reception value internally. 415 CHAPTER 20 LIN-UART ■ Suggested division ratios for different machine speeds and baud rates The following settings are suggested for different MCU clock speeds and baud rates: Table 20.6-1 Suggested Baud Rates and Reload Values at Different Machine Speeds. 8 MHz Baud rate value 10 MHz dev. value 16 MHz dev. value 20 MHz dev. value 24 MHz dev. value dev. 4M - - - - - - 4 0 5 0 2M - - 4 0 7 0 9 0 11 0 1M 7 0 9 0 15 0 19 0 23 0 500000 15 0 19 0 31 0 39 0 47 0 460800 - - - - - - - - 51 -0.16 250000 31 0 39 0 63 0 79 0 95 0 230400 - - - - - - - - 103 -0.16 153600 51 -0.16 64 -0.16 103 -0.16 129 -0.16 155 -0.16 125000 63 0 79 0 127 0 159 0 191 0 115200 68 -0.64 86 0.22 138 0.08 173 0.22 207 -0.16 76800 103 -0.16 129 -0.16 207 -0.16 259 -0.16 311 -0.16 57600 138 0.08 173 0.22 277 0.08 346 -0.06 416 0.08 38400 207 -0.16 259 -0.16 416 0.08 520 0.03 624 0 28800 277 0.08 346 <0.01 554 -0.01 693 -0.06 832 -0.03 19200 416 0.08 520 0.03 832 -0.03 1041 0.03 1249 0 10417 767 <0.01 959 <0.01 1535 <0.01 1919 <0.01 2303 <0.01 9600 832 0.04 1041 0.03 1666 0.02 2083 0.03 2499 0 7200 1110 <0.01 1388 <0.01 2221 <0.01 2777 <0.01 3332 <0.01 4800 1666 0.02 2082 -0.02 3332 <0.01 4166 <0.01 4999 0 2400 3332 <0.01 4166 <0.01 6666 <0.01 8332 <0.01 9999 0 1200 6666 <0.01 8334 0.02 13332 <0.01 16666 <0.01 19999 0 600 13332 <0.01 16666 <0.01 26666 <0.01 - - - - 300 26666 <0.01 - - - - - - - - Note: Deviations are given in%. Maximum Synchronous Baud Rate: MCU-Clock div. by 5. 416 CHAPTER 20 LIN-UART ■ Using external clock If the EXT bit of the SMR is set to 1, an external clock is selected, which has to be connected to the SCKn pin. The external clock is used in the same way as the internal clock to the baud rate generator. If One-to-one External Clock Input Mode (SMR: OTO=1) is selected the SCKn signal is directly connected to the LIN-UART serial clock inputs. This is needed for the LIN-UART synchronous mode 2 operating as slave device. Note: In any case the resulting clock signal is synchronized to the internal clock in the LIN-UART module. This means that indivisible clock rates will result in phase unstable signals. ■ Counting Example Assume the reload value is 832. Figure 20.6-2 demonstrates the behavior of both Reload Counters: Figure 20.6-2 Counting Example of the Reload Counters Transmission/Reception Clock Reload Counter 001 000 832 831 830 829 828 827 413 412 411 410 Reload counter value Transmission/Reception Clock Reload Counter 417 416 415 414 Note: The falling edge of the Serial Clock Signal always occurs after | (v + 1) / 2 |. 417 CHAPTER 20 LIN-UART 20.6.2 Restarting the Reload Counter The reload counter is a 15-bit reload counter that functions as dedicated baud rate generator. The transmission/reception clock is generated by the external or internal clock. Also, the count value of the transmission reload counter can be read by the baud rate generator register (BGR1, BGR0). ■ Function of Reload Counter The reload counter has the transmission and reception reload counters and functions as dedicated baud rate generator. It consists of a 15-bit register for the reload value and generates the transmission/reception clocks by the external or internal clock. Also, the count value of the transmission reload counter can be read by the baud rate generator register (BGR1, BGR0) ● Count start When the reload value is written to the baud rate generator register (BGR1, BGR0), the reload counter starts counting. ● Restart If the REST bit of the Serial Mode Register (SMR) is set to "1", both Reload Counters are restarted at the next clock cycle. This feature is intended to use the Transmission Reload Counter as a simple timer. The following figure illustrates a possible usage of this feature (assume that the reload value is 100.) Figure 20.6-3 Reload Counter Restart Example MCU Clock Reload Counter Clock Outputs REST Reload Value 37 36 35 100 99 98 97 96 95 94 93 92 91 90 89 88 87 Read BGR0/1 Data Bus 90 : don’t care In this example the number of MCU clock cycles (cyc) after REST is then: cyc = v - c + 1 = 100 - 90 + 1 = 11, where v is the reload value and c is the read counter value. 418 CHAPTER 20 LIN-UART Note: If LIN-UART is reset by setting SMR:UPCL to "1", the Reload Counters will restart too. • Automatic restart (reception reload counter only) In asynchronous LIN-UART mode, if a falling edge of a start bit is detected, the Reception Reload Counter is restarted. This is intended to synchronize the serial shift register to the incoming serial data stream. ● Clearing reload counters The reload value of the baud rate generator register (BGR1, BGR0) and the reload counters are cleared to "00" by the MCU global reset and the counters stops. The reload counters are cleared to "00H" by writing "1" to the UPCL bit in the SMR register. However, the value stored in the reload register is kept unchanged and the counters restart from reload value immediately. Writing "1" to the REST bit does not clear the counters and they restart from reload value immediately. 419 CHAPTER 20 LIN-UART 20.7 Operation of LIN-UART LIN-UART operates in operation mode 0 for normal bidirectional serial communication, in mode 2 and 3 in bidirectional communication as master or slave, and in mode 1 as master or slave in multiprocessor communication. ■ Operation of LIN-UART ● Operation modes There are four LIN-UART operation modes: modes 0 to 3. As listed in Table 20.7-1 , an operation mode can be selected according to the communication method. Table 20.7-1 Operation Mode of LIN-UART Operation mode Data length Parity disabled 0 Normal mode 7 or 8 bits 1 Multiprocessor mode 7 or 8 bits + 1* 2 Normal mode 8 3 LIN mode 8 Synchronization of mode Length of stop bit Data bit format Parity enabled Asynchronous - - 1 or 2 bits Asynchronous Synchronous None, 1 or 2 bits Asynchronous 1 bit LSB first MSB first LSB first -: Setting disabled *: "+1" means the indicator bit of the address/data selection used for controlling communication in the multiprocessor mode. Note: Mode 1 operation is supported both for master or slave operation of LIN-UART in a master-slave connection system. In Mode 3, the LIN-UART function is locked to 8N1-Format, LSB first. If the mode is changed, LIN-UART cuts off all possible transmission or reception and awaits then new action. 420 CHAPTER 20 LIN-UART ■ Inter-CPU Connection Method External Clock One-to-one connection (normal mode) and master-slave connection (multiprocessor mode) can be selected. For either connection method, the data length, whether to enable parity, and the synchronization method must be common to all CPUs. Select an operation mode as follows: • In the one-to-one connection method, operation mode 0 or 2 must be used in the two CPUs. Select operation mode 0 for asynchronous transfer mode and operation mode 2 for synchronous transfer mode. Note, that one CPU has to set to the master and the other to the slave in synchronous mode 2. • Select operation mode 1 for the master-slave connection method and use it either for the master or slave system. ■ Synchronization Methods In asynchronous operation, LIN-UART reception clock is automatically synchronized to the falling edge of a received start bit. In synchronous mode, the synchronization is performed either by the clock signal of the master device or by LIN-UART itself if operating as master. ■ Signal Mode LIN-UART can treat data only in non-return to zero (NRZ) format. ■ Operation Enable Bit LIN-UART controls both transmission and reception using the operation enable bit for transmission (SCR: TXE) and reception (SCR: RXE). • If reception operation is disabled during reception (data is input to the reception shift register), finish frame reception and read the received data of the reception data register (RDR). Then stop the reception operation. • If the transmission operation is disabled during transmission (data is output from the transmission shift register), wait until there is no data in the transmission data register (TDR) before stopping the transmission operation. 421 CHAPTER 20 LIN-UART 20.7.1 Operation in Asynchronous Mode (Op. Modes 0 and 1) When LIN-UART is used in operation mode 0 (normal mode) or operation mode 1 (multiprocessor mode), the asynchronous transfer mode is selected. ■ Operation in Asynchronous Mode ● Transfer data format Generally each data transfer in the asynchronous mode operation begins with the start bit (low-level) and ends with at least one stop bit (high-level). The direction of the bit stream (LSB first or MSB first) is determined by the BDS bit of the Serial Status Register (SSR). The parity bit (if enabled) is always placed between the last data bit and the (first) stop bit. In operation mode 0 the length of the data frame can be 7 or 8 bits, with or without parity, and 1 or 2 stop bits. In operation mode 1 the length of the data frame can be 7 or 8 bits with a following address-/data-selection bit instead of a parity bit. 1 or 2 stop bits can be selected. The calculation formula for the bit length of a transfer frame is: Length = 1 + d + p + s (d = number of data bits [7 or 8], p = parity [0 or 1], s = number of stop bits [1 or 2] Figure 20.7-1 shows the data format in the asynchronous mode. 422 CHAPTER 20 LIN-UART Figure 20.7-1 Transfer Data Format (operation Modes 0 and 1) [Operation mode 0] ST D0 D1 D2 D3 D4 D5 D6 D7 SP SP ST D0 D1 D2 D3 D4 D5 D6 D7 SP Without parity 8-bit data ST D0 D1 D2 D3 D4 D5 D6 D7 P SP SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 SP SP ST D0 D1 D2 D3 D4 D5 D6 SP With parity Without parity 7-bit data ST D0 D1 D2 D3 D4 D5 D6 P SP SP ST D0 D1 D2 D3 D4 D5 D6 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 AD SP SP With parity [Operation mode 1] 8-bit data ST D0 D1 D2 D3 D4 D5 D6 D7 AD SP ST D0 D1 D2 D3 D4 D5 D6 AD SP SP 7-bit data ST D0 ST SP P AD D1 D2 D3 D4 D5 D6 AD SP : Start bit : Stop mode : Parity bit : Address/data bit Note: If BDS bit of the Serial Status Register (SSR) is set to "1" (MSB first), the bit stream processes as: D7, D6, ..., D1, D0, (P). 423 CHAPTER 20 LIN-UART ● Transmission operation If the Transmission Data Register Empty (TDRE) flag bit of the Serial Status Register (SSR) is "1", transmission data is allowed to be written to the Transmission Data Register (TDR). When data is written, the TDRE flag goes "0". If the transmission operation is enabled by the TXE-Bit ("1") of the Serial Control Register (SCR), the data is written next to the transmission shift register and the transmission starts at the next clock cycle of the serial clock, beginning with the start bit. If transmission interrupt is enabled (TIE = 1), the interrupt is generated by the TDRE flag. Note, that the initial value of the TDRE flag is "1", so that in this case if TIE is set to "1" an interrupt will occur immediately. When the data length is set to 7 bits (CL=0), the unused bit of the TDR is always the MSB, independently from the transfer direction selection in the BDS bit (LSB first or MSB first). Note: As the initial value of transmission data empty flag bit (SSR: TDRE) is "1" if the transmission interrupt is enabled (SSR: TIE=1), the interrupt occurs immediately. ● Reception operation Reception operation is performed when it is enabled by the Reception Enable (RXE) flag bit of the SCR. If a start bit is detected, a data frame is received according to the data format specified by the SCR. In case of errors, the corresponding error flags are set (SSR: PE, ORE, FRE). After the reception of the data frame, the data is transferred from the reception shift register to the Reception Data Register (RDR) and the Receive Data Register Full (RDRF) flag bit of the SSR is set to "1". In this case, if the reception interrupt request is enabled (SSR: RIE=1), the reception interrupt request is occurred. When reading data after reception of one frame data, check the error flag state and read reception data from the RDR register if the reception is performed normally. If the reception error occurs, perform error processing. The data then has to be read by the CPU. By doing so, the RDRF flag of SSR is cleared to "0". When the data length is set to 7 bits (CL=0), the unused bit of the TDR is always the MSB, independently from the bit transfer direction selection in the BDS bit (LSB first or MSB first). Note: Only when the RDRF flag bit of SSR is set to "1" and no errors have occurred (SSR: PE, ORE, FRE=0) the Reception Data Register (RDR) contains valid data. ● Used clock Use the internal clock or external clock. Select the baud rate generator (SMR: EXT = 0 or 1, OTO = 0) for desired baud rate. 424 CHAPTER 20 LIN-UART ● Stop bit 1- or 2-stop bit can be selected at the transmission. When 2-stop bit is selected, both stop bits is detected at the reception. When first stop bit is detected, the RDRF bit of SSR is "1". Then, when the start bit is not detected, the RBI bit of ECCR is set to "1", indicating no reception operation. ● Error detection In mode 0, the parity, overrun, and framing errors can be detected. In mode 1, the overrun and framing errors can be detected, and the parity error cannot be detected. ● Parity Parity can set to add (transmission) or detect (reception) the parity bit. The parity enable bit (SCR: PEN) is used to specify whether there is parity or not, and parity selection bit (SCR: P) is selected the even/odd parity. In operation mode 1, the parity cannot be used. Figure 20.7-2 Transmission Data when Parity Enabled SIN ST SP 1 0 1 1 0 0 0 0 0 SOT ST Parity error generating at received even parity error (SCR:P=0) SP Even parity transmitting (SCR:P=0) SP Odd parity transmitting (SCR:P=1) 1 0 1 1 0 0 0 0 1 SOT ST 1 0 1 1 0 0 0 0 0 ST: Start bit, SP: Stop bit at parity ON (PEN=1) Note: Parity can not be used at operation mode 1. ● Data signal type The data signal type is NRZ data format. ● Data transition method The data bit transfer method can be selected by LSB or MSB first. 425 CHAPTER 20 LIN-UART 20.7.2 Operation in Synchronous Mode (Operation Mode 2) The clock synchronous transfer method is used for LIN-UART operation mode 2 (normal mode). ■ Operation in Synchronous Mode (Operation mode 2) ● Transfer data format In the synchronous mode, 8-bit data is transferred without start or stop bits if the SSM bit of the Extended Communication Control Register (ECCR) is 0. Also, when the start/stop bit is provided (ECCR: SSM = 1), presence or absence of the parity bit can be selected (SCR: PEN). The figure below illustrates the data format during a transmission in the synchronous operation mode. Figure 20.7-3 Transfer Data Format (operation mode 2) Reception or transfer data (ECCR:SSM=0,SCR:PEN=0) D0 D1 D2 D3 D4 D5 D6 D7 Reception or transfer data (ECCR:SSM=1,SCR:PEN=0) ST D0 D1 D2 D3 D4 D5 D6 D7 Reception or transfer data (ECCR:SSM=1,SCR:PEN=1) * SP SP * ST D0 D1 D2 D3 D4 D5 D6 D7 P SP SP *: Set to 2-stop bits (SCR: SBL = 1) ST: Start bit SP: Stop bit P: Parity bit LSB first ● Clock inversion function If the SCES bit of the Extended Status/Control Register (ESCR) is set to "1", the serial clock is inverted. Therefore, in slave mode LIN-UART samples the data bits at the falling edge of the received serial clock. Note, that in master mode if SCES is set to "1", the clock signal’s mark level is "0". Figure 20.7-4 Transfer Data Format with Clock Inversion mark level Reception or transmission clock (SCES = 0, CCO = 0): Reception or transmission clock (SCES = 1, CCO = 0): Data stream (SSM = 1) (here: no parity, 1 stop bit) mark level ST SP data frame ● Start/stop bits If the SSM bit of the Extended Communication Control Register (ECCR) is set to "1", the data format gets additional start and stop bits like in asynchronous mode. 426 CHAPTER 20 LIN-UART ● Clock supply: In operation mode 2, the number of clock cycles for the clock signal must be the same as the number of bits for the transmission and reception. If the start/stop bits are enabled, it must be matched the additional start/ stop bits. If the MS bit of the ECCR register is "0" (master mode) and the SCKE bit of the SMR register is "1" (serial clock output enabled), the consistent clock cycles are generated automatically. If the MS bit of the ECCR register is "1" (slave mode), or if the SCKE bit of SMR is 0 (serial clock output disabled), the clock for each bit of transfer data must be supplied from outside. While there is no communication, the clock signal must be kept at "H" as the mark level If the SCDE bit of the ECCR register is "1", the clock output signal is delayed by the half of the serial clock cycle as shown in Figure 20.7-5 . The operation is prepared for communication devices which use the rising or falling edge of the serial clock signal for the data sampling. Figure 20.7-5 Delayed Transmitting Clock Signal(SCDE=1) Transmission data writing Reception data sample edge (SCES = 0) Transmitting or receiving clock (normal) Mark level Mark level Transmitting clock (SCDE = 1) Transmission and reception data Mark level 0 1 1 0 LSB 1 0 Data 0 1 MSB If the SCES bit of the ESCR register is "1", the serial clock signal is inverted. Receiving data is sampled at the falling edge of the serial clock. In this case, the serial data must be valid value at the falling edge of the clock. If the CCO bit of ESCR register is "1" (master mode), the serial clock output of the SCKn pin is supplied continuously. In this mode, be sure to add the start/stop bits (SSM = 1) to identify the start and end of data frame. Figure 20.7-6 shows the operation of this function. Figure 20.7-6 Continuous Clock Supply in Mode 2 Reception or transmission clock (SCES = 0, CCO = 1): Reception or transmission clock (SCES = 1, CCO = 1): Data stream (SSM = 1) (here: no parity, 1 stop bit) ST SP data frame ● Error detection: If no start/stop bits are selected (ECCR: SSM = 0) only overrun errors are detected. 427 CHAPTER 20 LIN-UART ● Communication: For initialization of the synchronous mode, following settings have to be done: Baud rate generator registers (BGR0/BGR1): Set the desired reload value for the dedicated baud rate reload counter. Serial mode register (SMR): MD1, MD0: "10B" (Mode 2) SCKE: "1" for the dedicated baud rate reload counter "0" for external clock input SOE: "1" for transmission and reception "0" for reception only Serial control register (SCR): RXE, TXE: set one or both of these bits to "1" AD: no address/data selection - don’t care CL: automatically fixed to 8-bit data - don’t care CRE: "1" to clear receive error flags. Suspend transmission and reception. -- when SSM=0: PEN, P, SBL: don’t care -- when SSM=1: PEN: "1" if parity bit is added/detected, "0" if not P: "0" for even parity, "1" odd parity SBL: "1" for 2 stop bits, "0" for 1 stop bit. Serial status register (SSR): BDS: "0" for LSB first, "1" for MSB first RIE: "1" if reception interrupts are used; "0" reception interrupts are disabled. TIE: "1" if transmission interrupts are used; "0" transmission interrupts are disabled. Extended communication control register (ECCR): SSM: "0" if no start/stop bits are desired (normal); "1" for adding start/stop bits (exteneded function) MS: "0" for master mode (LIN-UART generates the serial clock); "1" for slave mode (LIN-UART receives serial clock from the master device) Note: To start the communication, write data to TDR register. When receiving the data, disable the serial output (SMR: SOE = "0") and write the dummy data to TDR. By enabling the continuous clock and start/stop bits, in the bi-directional communication the same as the asynchronous mode is allowed. 428 CHAPTER 20 LIN-UART 20.7.3 Operation with LIN Function (Operation Mode 3) LIN-UART can be used either as LIN-Master or LIN-Slave. For this LIN function a special mode is provided. Setting the LIN-UART to mode 3 configures the data format to 8N1LSB-first format. ■ Operation in Asynchronous LIN Mode (Operation mode 3) ● LIN-UART as LIN master In LIN master mode, the master determines the baud rate of the whole bus, therefore slaves devices have to synchronize to the master. Therefore, the desired baud rate remains fixed in master operation after initialization. Writing a "1" into the LBR bit of the Extended Communication Control Register (ECCR) generates a 13 16 bit time low-level on the SOTn pin, which is the LIN synchronization break and the start of a LIN message. Thereby the TDRE flag of the Serial Status Register (SSR) goes "0" and is reset to "1" after the break, and generates a transmission interrupt for the CPU (if TIE of SSR is "1"). The length of the LIN break to be sent can be determined by the LBL1/0 bits of the ESCR as follows: Table 20.7-2 LIN Break Length LBL0 LBL1 Break length 0 0 13 bits 1 0 14 bits 0 1 15 bits 1 1 16 bits The Synch Field is sent as byte data of 0x55 after the LIN break. To prevent a transmission interrupt, the 0x55 can be written to the TDR just after writing the "1" to the LBR bit, although the TDRE flag is "0". ● LIN-UART as LIN slave In LIN slave mode, LIN-UART has to synchronize to the master’s baud rate. If Reception is disabled (RXE = 0) but LIN break interrupt is enabled (LBIE = 1) LIN-UART will generate a reception interrupt, if a synchronization break from the LIN master is detected, and indicates it with the LBD flag of the ESCR to "1". Writing "0" to this bit clears the reception interrupt request. For the calculation of the baud rate, the UART0 operation is explained as an example. When UART0 detects first falling edge of synch field, set the internal signal inputted to the input capture (ICU0) to "H" and start ICU0. This internal signal is set to "L" at fifth falling edge, ICU0 must be set to the LIN mode (ICE01). Also, the ICUO interrupt must be set to enable and to detect both edges (ICS01). The time when the ICU0 input signal is "1" is the value in which eight baud rates are multiplied. Therefore, baud rate setting value is summarized as follows: without free-run timer overflow : BGR value = (b-a)/8 -1 with free-run timer overflow : BGR value = (Max + b-a)/8-1 where Max is the free-run timer maximum value at the overflow occurs. 429 CHAPTER 20 LIN-UART where a is the value of the ICU data register after the first interrupt where b is the value of the ICU data register after the second interrupt Note: As shown in the LIN slave mode, when the BGR value newly calculated by synch field generates ±15% or more baud rate error, do not set the baud rate. For the correspondence between other LIN-UARTs and ICUs, see "13.5 Explanation of Operation of 16bit Free-run Timer" and "13.6 Explanation of Operation of Input Capture". ● LIN Synch Break Detection Interrupt and Flags If a LIN Synch break is detected in the slave mode, the LIN Break Detected (LBD) Flag of the ESCR is set to "1". This causes an interrupt, if the LIN Break Interrupt Enable (LBIE) bit is set to 1. Figure 20.7-7 LIN Synch Break Detection and Flag Set Timing. Serial clock cycle# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Serial clock Serial input (LIN bus) FRE (RXE=1) LBD (RXE=0) Reception interrupt occurs, if RXE=1 Reception interrupt occurs, if RXE=0 The figure above demonstrates the LIN synch break detection and flag set timing. Note, that if reception is enabled (RXE = 1) and reception interrupt is enabled (RIE = 1) the Reception Data Framing Error (FRE) flag bit of the SSR will cause a reception interrupt 2 bit times ("8N1") earlier than the LIN break interrupt, so it is recommended to turn off RXE, if a LIN break is expected. LIN synch break detection is only supported in operation mode 3. Figure 20.7-8 shows a typical start of a LIN message and the behavior of the LIN-UART. 430 CHAPTER 20 LIN-UART Figure 20.7-8 LIN-UART Behavior as Slave in LIN Mode Serial clock Serial input (LIN bus) LBR cleared by CPU LBD ICU input signal (LSYN) Synch break (at 14-bit setting) Synch field ● LIN bus timing Figure 20.7-9 LIN Bus Timing and LIN-UART Signals No clock used (calibration frame) Old serial clock New (calibrated) serial clock ICU count LIN bus (SIN) RXE LBD (IRQ0) LBIE ICU input (LSYN) IRQ(ICU) RDRF (IRQ0) RIE Read RDR by CPU Reception interrupt enable LIN break begins LIN break detected and Interrupt IRQ cleared by CPU (LBD->0) IRQ (ICU) IRQ cleared: Begin of ICU IRQ(ICU) IRQ cleared: Calculate & set new baud rate LBIE disable Reception enable Falling edge of start bit Store one byte of received data to RDR RDR read by CPU 431 CHAPTER 20 LIN-UART 20.7.4 Direct Access to Serial Pins LIN-UART allows the user to directly access to the transmission pin (SOTn) or the reception pin (SINn). ■ LIN-UART Direct Pin Access The LIN-UART provides the ability for the software to access directly to serial input or output pin. The software can always monitor the incoming serial input pin (SINn) by reading the SIOP bit of the ESCR. If direct write to the serial output pin (SOTn) is allowed (ESCR: SOPE = 1) when the serial output is enabled (SMR: SOE = 1) after "0" or "1" is written to the SIOP bit of the ESCR register, the SOTn value can be set arbitrarily. In LIN mode, this function can be used for reading back the own transmission and is used for error handling if something is physically wrong with the single-wire LIN-bus. Notes: • Direct access is enabled only when the transmission is not ongoing (transmission shift register is empty). • Write a value to the SIOP bit of ESCR register before enabling the transmission (SMR: SOE = 1). This prevents the signal of the unexpected level from being outputted because the SIOP bit retains the previous value. • During a Read-Modify-Write instruction the SIOP bit returns the actual value of the SOTn pin in the read cycle instead of the value of SINn during a normal read instruction. 432 CHAPTER 20 LIN-UART 20.7.5 Bidirectional Communication Function (Normal Mode) In operation mode 0 or 2, normal serial bidirectional communication is available. Select operation mode 0 for asynchronous communication and operation mode 2 for synchronous communication. ■ Bidirectional Communication Function The settings shown in Figure 20.7-10 are required to operate LIN-UART in normal mode (operation mode 0 or 2). Figure 20.7-10 Settings for LIN-UART Operation Mode 0 and 2 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SCRn, SMRn PEN P SBL CL AD CRE RXE TXE MD1 MD0 OTO EXT REST UPCLSCKE SOE Mode 0 Mode 2 SSRn, TDRn/RDRn PE ORE FRE RDRF TDRE BDS RIE TIE Set conversion data (during writing) Retain reception data (during reading) Mode 0 Mode 2 ESCRn, ECCRn LBIE LBD LBL1 LBL0 SOPE SIOP CCO SCES LBR MS SCDE SSM Mode 0 Mode 2 : Used bit : Unused bit : Set 1 : Set 0 : Bit used if SSM = 1 (Synchronous start-/stop-bit mode) : Bit automatically set to correct value RBI TBI n = 0, 1 ● Inter-CPU connection As shown in Figure 20.7-11 , interconnect two CPUs in LIN-UART mode 2 Figure 20.7-11 Connection Example of LIN-UART Mode 2 Bidirectional Communication SOT SOT SIN Output SCK CPU-1 (Master) SIN Input SCK CPU-2 (Slave) 433 CHAPTER 20 LIN-UART ● Communication procedure Communication starts at arbitrary timing from the transmission side when the transmission data is provided. When the transmission data is received at the reception side, ANS (per one byte in example) is returned periodically. Figure 20.7-12 shows an example of the bi-directional communication flowchart. Figure 20.7-12 Example of Master-slave Communication Flowchart (Transmission side) (Reception side) Start Start Operating mode setting (either 0 or 2) Operating mode setting (match the transmission side) Set 1 byte data to TDR and communicate Data transmission NO With reception data YES NO With reception data Read reception data and process YES Read reception data and process 434 Data transmission 1byte data transmission (ANS) CHAPTER 20 LIN-UART 20.7.6 Master-Slave Communication Function (Multiprocessor Mode) LIN-UART communication with multiple CPUs connected in master-slave mode is available for both master or slave systems in the operation mode 1. ■ Master-slave Communication Function The settings shown in Figure 20.7-13 are required to operate LIN-UART in multiprocessor mode (operation mode 1). Figure 20.7-13 Settings for LIN-UART Operation Mode 1 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SCRn, SMRn PEN P SBL CL AD CRE RXE TXE MD1 MD0 OTO EXT REST UPCL SCKE SOE Mode 1 SSRn, TDRn/RDRn PE ORE FRE RDRF TDRE BDS RIE TIE Set conversion data (during writing) Retain reception data (during reading) Mode 1 ESCRn, ECCRn LBIE LBD LBL1 LBL0 SOPE SIOP CCO SCES LBR MS SCDE SSM RBI TBI Mode 1 : Used bit : Unused bit : Set 1 : Set 0 : Bit automatically set to correct value n = 0, 1 ● Inter-CPU connection As shown in Figure 20.7-14 , a communication system consists of one master CPU and multiple slave CPUs connected to two communication lines. LIN-UART can be used for the master or slave CPU. Figure 20.7-14 Connection Example of LIN-UART Master-slave Communication SOT SIN Master CPU SOT SIN Slave CPU#0 SOT SIN Slave CPU#1 435 CHAPTER 20 LIN-UART ● Function selection Select the operation mode and data transfer mode for master-slave communication as shown in Table 20.73. Table 20.7-3 Selection of the Master-slave Communication Function Operation mode Master CPU Address transmission and reception Mode 1 (transmit/ receive ADbit) Data Parity Slave CPU Mode 1 (transmit/ receive ADbit) Data transmission and reception AD="1" + 7- or 8-bit address None Synchron ization method Stop bit Asynchro- 1 bit or 2 bits nous Bit direction LSB or MSB first AD="0" + 7- or 8-bit data ● Communication procedure When the master CPU transmits address data, communication starts. The AD bit in the address data is set to 1, and the communication destination slave CPU is selected. Each slave CPU checks the address data using a program. When the address data indicates the address assigned to a slave CPU, the slave CPU communicates with the master CPU. Figure 20.7-15 shows a flowchart of master-slave communication (multiprocessor mode) 436 CHAPTER 20 LIN-UART Figure 20.7-15 Master-slave Communication Flowchart (Master CPU) (Slave CPU) Start Start Set operation mode 1 Set operation mode 1 Set SINn pin as the serial data input pin. Set SOTn pin as the serial data output pin. Set SINn pin as the serial data input pin. Set SOTn pin as the serial data output pin. Set 7 or 8 data bits. Set 1 or 2 stop bits. Set 7 or 8 data bits. Set 1 or 2 stop bits. Set "1" in AD bit. Transfer & reception operation enabled Transfer & reception operation enabled Receive byte Send address to slave. AD bit = 1 NO YES Slave address match? NO Set "0" in AD bit. YES Communicate with master CPU Communicate with slave CPU Is communication complete? Communication complete? NO NO YES YES Communicate with another slave CPU? NO YES Transfer & reception operation disabled End 437 CHAPTER 20 LIN-UART 20.7.7 LIN Communication Function LIN-UART communication with LIN devices is available for both LIN master or LIN slave systems. ■ LIN-master-slave Communication Function The settings shown in the figure below are required to operate LIN-UART in LIN communication mode (operation mode 3). Figure 20.7-16 Settings for LIN-UART in Operation Mode 3 (LIN) SCRn, SMRn PEN P SBL CL AD CRE RXE TXE MD1 MD0 OTO EXT REST UPCL SCKE SOE Mode 3 SSRn, TDRn/RDRn PE ORE FRE RDRF TDRE BDS RIE TIE Set conversion data (during writing) Retain reception data (during reading) Mode 3 ESCRx, ECCRx LBIE LBD LBL1 LBL0 SOPE SIOP CCO SCES LBR MS SCDE SSM RBI TBI Mode 3 : Used bit : Unused bit : Set 1 : Set 0 : Bit automatically set to correct value n = 0, 1 ● LIN device connection As shown in the Figure below, a communication system of one LIN-Master device and a LIN-Slave device. LIN-UART can operate both as LIN-Master or LIN-Slave. Figure 20.7-17 Connection Example of a Small LIN-Bus System SOT SOT LIN bus SIN LIN master 438 SIN Transceiver Transceiver LIN slave CHAPTER 20 LIN-UART 20.7.8 Sample Flowcharts for LIN-UART in LIN communication (Operation Mode 3) This section contains sample flowcharts for LIN-UART in LIN communication. ■ LIN-UART as LIN Master Device Figure 20.7-18 LIN-UART LIN Master Flowchart Start Initial setting : Set operation mode 3 Serial data output enabled, Baud rate setting, Synch break length setting TXE = 1, TIE = 0, RXE = 1, RIE = 1 Send Message?N Y (Reception) Wake up ? (0x80 reception) N Y Y (Transmission) Data Field N reception ? RDRF = 1 Reception interrupt Data 1 reception*1 RXE = 0 Synch break interrupt enabled Sync Break transmission: ECCR: LBR = 1 Synch Field transmission: TDR = 0x55 Transmission data 1 set : TDR = Data 1 Transmission interrupt enabled RDRF = 1 Reception interrupt Data N reception*1 TDRE = 1 Transmission interrupt Transmission data N set: TDR = Data N Transmission interrupt disabled LBD = 1 Synch Break interrupt RDRF = 1 Reception interrupt Reception enabled LBD = 0 Synch break interrupt disabled Data 1 reception*1 Data 1 reading RDRF = 1 Reception interrupt RDRF = 1 Reception interrupt Synch field reception *1 Identify field set : TDR = lD Data N reception*1 Data N reading RDRF = 1 Reception interrupt ID field reception*1 Without error? N Error processing*2 Y *1: If an error occurs, perform the error processing *2: • When fre and ore is "1", write 1 to SCR: CRE bit and clear the error flag. • When ESCR: LBD bit is "1", execute UART reset. Note: The error is detected in each processing and take appropriate measure. 439 CHAPTER 20 LIN-UART ■ LIN-UART as LIN slave device Figure 20.7-19 LIN-UART LIN Slave Flowchart Start Initial setting : Set operation mode 3 Serial data output enabled TXE = 1, TIE = 0, RXE = 0, RIE = 1 Connection with LIN-UART and ICU Reception prohibited ICU interrupt enabled Synch break interrupt enabled LBD = 1 Synch break interrupt Synch Break detection clear ECCR: LBD = 0 Synch break interrupt prohibited ICU interrupt (reception) Y (transmission) Data Field reception ? N RDRF = 1 Reception interrupt Transmission data 1 set TDR = Data 1 Transmission interrupt enabled Data 1 reception*1 RDRF = 1 Reception interrupt TDRE = 1 Transmission interrupt Data N reception*1 ICU data read ICU interrupt flag clear ICU interrupt Transmission data N set TDR = Data N Transmission interrupt prohibited Reception prohibited RDRF = 1 Reception interrupt ICU data read Baud rate regulation Reception enabled ICU interrupt flag clear ICU interrupt prohibited Data 1 reception*1 Data 1 read RDRF = 1 Reception interrupt RDRF = 1 Reception interrupt Data N reception*1 Data N read Reception prohibited Identify field reception*1 Sleep mode? N Y Without error? N Y Wake up reception? N Y Wake up N transmission? Y Wake up code transmission *1: If an error occurs, perform the error processing *2: • When fre and ore is "1", write 1 to SCR: CRE bit and clear the error flag. • When ESCR: LBD bit is "1", execute UART reset. Note: The error is detected in each processing and take appropriate measure. 440 Error processing*2 CHAPTER 20 LIN-UART 20.8 Notes on Using LIN-UART Notes on using LIN-UART are given below. ■ Notes on Using LIN-UART ● Enabling operations In LIN-UART, the serial control register (SCR) has TXE (transmission) and RXE (reception) operation enable bits. Both, transmission and reception operations, must be enabled before the communication starts because they have been disabled as the default value (initial value). The operation can also be canceled by disabling these bits. ● Communication mode setting Set the communication mode while the system is not operating. If the mode is changed during transmission or reception, the transmission or reception is stopped and possible data will be lost. ● Transmission interrupt enabling timing The default (initial value) of the transmission data empty flag bit (SSR: TDRE) is "1" (no transmission data and transmission data write enable state). A transmission interrupt request is generated as soon as the transmission interrupt request is enabled (SSR: TIE=1). Be sure to set the TIE flag to "1" after setting the transmission data to avoid an immediate interrupt. ● Changing operation settings It is strongly recommended to reset LIN-UART after changing operation settings. Particularly if (for example) start-/stop-bits added to or removed from the data format. If settings in the serial mode register (SMR) are desired, it is not useful to set the UPCL bit to 1 at the same time to reset LIN-UART. The correct operation settings are not guaranteed in this case. Thus it is recommended to set the bits of the SMR and then to reset them again plus the UPCL bit. ● Using LIN operation mode 3 The LIN features are available in mode 3 (transmitting, receiving synch break), but using mode 3 sets the UART data format automatically to LIN format (8N1, LSB first). Note that the length of the synch break for transmission is variable but for reception it is fixed 11-bit time. ● LIN slave settings Set the baud rate before receiving the first LIN synch break for the slave operation. This is needed to detect the minimum of 13-bit time of a LIN synch break surely. ● Software compatibility Although this LIN-UART is similar to other LIN-UART in other microcontrollers, it is not software compatible to them. The programming models may be the same, but the structure of the registers differ. Furthermore, the setting of the baud rate is now determined by a reload value instead of selecting a 441 CHAPTER 20 LIN-UART predefined value. ● Bus idle function The bus idle function cannot be used in synchronous mode 2. ● AD bit (serial control register (SCR): address/data type select bit) Special care has to be taken when using the AD bit (Address-Data-Bit for multiprocessor mode 1) of the Serial Control Register. This bit is both a control and a flag bit, because writing to it sets the AD bit for transmission, whereas reading from it returns the last received AD bit. Internally, the received and the transmitted value are stored in different registers, but in Read-Modify-Write instructions, the transmitted value is read. This can lead to a wrong value in the AD bit, when one of the other bits in the same register is accessed by an instruction of this kind. Therefore, this bit should be written by the last register access before transmission. Alternatively, using byte wise access and writing the correct values for all bits at once avoids this problem. ● Software reset of LIN-UART Perform the software reset (SMR: UPCL=1), when the TXE bit of the SCR register is "0". ● LIN Synch detection In mode 3 (LIN operation), the LBD bit in the ESCR register is set to "1" if the input signal is kept at "0" for more than equal to 11-bit time. Then the LIN-UART waits for the following synch field to be received. If the LIN-UART is set into this state for other reasons than the synch break, it recognizes that synch break is inputted (LBD = 1) and waits for synch field. In this case, execute the LIN-UART reset (SMR: UPCL = 1). 442 CHAPTER 21 CAN CONTROLLER This chapter explains the functions and operations of the CAN controller. 21.1 Features of CAN Controller 21.2 Block Diagram of CAN Controller 21.3 List of Overall Control Registers 21.4 Classifying CAN Controller Registers 21.5 Transmission of CAN Controller 21.6 Reception of CAN Controller 21.7 Reception Flowchart of CAN Controller 21.8 How to Use CAN Controller 21.9 Procedure for Transmission by Message Buffer (x) 21.10 Procedure for Reception by Message Buffer (x) 21.11 Setting Configuration of Multi-level Message Buffer 21.12 Setting the CAN Direct Mode Register 21.13 Precautions when Using CAN Controller 443 CHAPTER 21 CAN CONTROLLER 21.1 Features of CAN Controller The CAN (Controller Area Network) is the standard protocol for serial communication between automobile controllers and is widely used in industrial applications. ■ Features of CAN Controller • Conforms to CAN Specification Version 2.0 Part A and B Supports transmission/reception in standard frame and extended frame formats • Supports transmitting of data frames by receiving remote frames • 16 transmitting/receiving message buffers - 29-bit ID and 8 bytes data - Multi-level message buffer configuration • Supports full-bit comparison, full-bit mask and partial bit mask filtering Two acceptance mask registers in either standard frame format or extended frame formats • Bit rate programmable from 10 Kbps to 1 Mbps (Minimum 8 MHz machine clock is required at using 1 Mbps.) 444 21.2 Block Diagram of CAN Controller Figure 21.2-1 shows a block diagram of the CAN controller. ■ Block Diagram of CAN Controller Figure 21.2-1 Block Diagram of CAN Controller F2MC-16LX bus TQ (Operating clock) Prescaler 1 to 64 frequency division Clock Bit timing generation SYNC, TSEG1, TSEG2 PSC TS1 BTR TS2 RSJ TOE TS RS CSR IDLE, SUSPND, transmit, receive, ERR, OVRLD HALT NIE NT Node status change interrupt generation Bus state machine Node status change interrupt NS1, 0 Error control RTEC Transmitting/ receiving sequencer BVALR TREQR TBFx clear Transmitting buffer x decision TBFx Data counter Error frame generation Acceptance filter control Overload frame generation TDLC RDLC IDSEL TBFx BITER, STFER, CRCER, FRMER, ACKER TCANR Output driver ARBLOST TX TRTRR TCR TBFx, set, clear Transmission complete interrupt generation TIER RCR Stuffing Transmission shift register RFWTR Transmission complete interrupt RBFx, set Reception complete interrupt RBFx, TBFx, set, clear CRC generation ACK generation CRCER RDLC Reception complete interrupt generation RIER TDLC CRC generation/error check Receive shift register STFER Destuffing/stuffing error check RRTRR RBFx, set IDSEL ROVRR ARBLOST AMSR AMR0 0 1 BITER Acceptance filter Receiving buffer to decision AMR1 RBFx IDR0 to 15, DLCR0 to 15, DTR0 to 15, RAM RAM address generation Arbitration check Bit error check PH1 ACKER Acknowledgment error check FRMER Form error check Input latch RX RBFx, TBFx, RDLC, TDLC, IDSEL LEIR IDER 445 CHAPTER 21 CAN CONTROLLER 21.3 List of Overall Control Registers Following Table lists the register. ■ List of overall Control Registers Table 21.3-1 List of overall Control Register (1 / 2) Address Register Abbreviation Access Initial Value CAN1 000080H 000081H 000082H 000083H 000084H 000085H 000086H 000087H 000088H 000089H 00008AH 00008BH 00008CH 00008DH 00008EH 00008FH 007D00H 007D01H 007D02H 007D03H 007D04H 007D05H 007D06H 007D07H 007D08H 007D09H 007D0AH 007D0BH 446 Message buffer valid register BVALR R/W 00000000 00000000 Transmit request register TREQR R/W 00000000 00000000 Transmit cancel register TCANR W 00000000 00000000 Transmit complete register TCR R/W 00000000 00000000 Receive complete register RCR R/W 00000000 00000000 Remote request receiving register RRTRR R/W 00000000 00000000 Receive overrun register ROVRR R/W 00000000 00000000 Receive interrupt enable register RIER R/W 00000000 00000000 Control status register CSR R/W, R 0 0 XXX 0 0 0 0 XXXX0 X1 Last event indicator register LEIR R/W XXXXXXXX 0 0 0 X0 0 0 0 Receive/transmit error counter RTEC R 00000000 00000000 Bit timing register BTR R/W X1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 IDE register IDER R/W XXXXXXXX XXXXXXXX Transmit RTR register TRTRR R/W 00000000 00000000 Table 21.3-1 List of overall Control Register (2 / 2) Address Register Abbreviation Access Initial Value CAN1 007D0CH 007D0DH 007D0EH 007D0FH Remote frame receive waiting register RFWTR R/W XXXXXXXX XXXXXXXX Transmit interrupt enable register TIER R/W 00000000 00000000 007D10H 007D11H 007D12H XXXXXXXX XXXXXXXX Acceptance mask select register AMSR R/W XXXXXXXX XXXXXXXX 007D13H 007D14H 007D15H 007D16H XXXXXXXX XXXXXXXX Acceptance mask register 0 AMR0 R/W XXXXXXXX XXXXXXXX 007D17H 007D18H 007D19H 007D1AH 007D1BH XXXXXXXX XXXXXXXX Acceptance mask register 1 AMR1 R/W XXXXXXXX XXXXXXXX 447 CHAPTER 21 CAN CONTROLLER ■ List of Message Buffers (ID registers) Table 21.3-2 List of Message Buffers (ID registers) (1 / 2) Address Register Abbreviation Access Initial Value CAN1 007C00H to 007C1FH − General-purpose RAM R/W 007C20H 007C21H 007C22H XXXXXXXX XXXXXXXX ID register 0 IDR0 R/W XXXXXXXX XXXXXXXX 007C23H 007C24H 007C25H 007C26H XXXXXXXX XXXXXXXX ID register 1 IDR1 R/W XXXXXXXX XXXXXXXX 007C27H 007C28H 007C29H 007C2AH XXXXXXXX XXXXXXXX ID register 2 IDR2 R/W XXXXXXXX XXXXXXXX 007C2BH 007C2CH 007C2DH 007C2EH XXXXXXXX XXXXXXXX ID register 3 IDR3 R/W XXXXXXXX XXXXXXXX 007C2FH 007C30H 007C31H 007C32H XXXXXXXX XXXXXXXX ID register 4 IDR4 R/W XXXXXXXX XXXXXXXX 007C33H 007C34H 007C35H 007C36H XXXXXXXX XXXXXXXX ID register 5 IDR5 R/W XXXXXXXX XXXXXXXX 007C37H 007C38H 007C39H 007C3AH 007C3BH 448 XXXXXXXX to XXXXXXXX XXXXXXXX XXXXXXXX ID register 6 IDR6 R/W XXXXXXXX XXXXXXXX Table 21.3-2 List of Message Buffers (ID registers) (2 / 2) Address Register Abbreviation Access Initial Value CAN1 007C3CH 007C3DH 007C3EH XXXXXXXX XXXXXXXX ID register 7 IDR7 R/W XXXXXXXX XXXXXXXX 007C3FH 007C40H 007C41H 007C42H XXXXXXXX XXXXXXXX ID register 8 IDR8 R/W XXXXXXXX XXXXXXXX 007C43H 007C44H 007C45H 007C46H XXXXXXXX XXXXXXXX ID register 9 IDR9 R/W XXXXXXXX XXXXXXXX 007C47H 007C48H 007C49H 007C4AH XXXXXXXX XXXXXXXX ID register 10 IDR10 R/W XXXXXXXX XXXXXXXX 007C4BH 007C4CH 007C4DH 007C4EH XXXXXXXX XXXXXXXX ID register 11 IDR11 R/W XXXXXXXX XXXXXXXX 007C4FH 007C50H 007C51H 007C52H XXXXXXXX XXXXXXXX ID register 12 IDR12 R/W XXXXXXXX XXXXXXXX 007C53H 007C54H 007C55H 007C56H XXXXXXXX XXXXXXXX ID register 13 IDR13 R/W XXXXXXXX XXXXXXXX 007C57H 007C58H 007C59H 007C5AH XXXXXXXX XXXXXXXX ID register 14 IDR14 R/W XXXXXXXX XXXXXXXX 007C5BH 007C5CH 007C5DH 007C5EH 007C5FH XXXXXXXX XXXXXXXX ID register 15 IDR15 R/W XXXXXXXX XXXXXXXX 449 CHAPTER 21 CAN CONTROLLER ■ List of Message Buffers (DLC registers and data registers) Table 21.3-3 List of Message Buffer (DLC register and data register) Address Register Abbreviation Access Initial Value CAN1 007C60H 007C61H 007C62H 007C63H 007C64H 007C65H 007C66H 007C67H 007C68H 007C69H 007C6AH 007C6BH 007C6CH 007C6DH 007C6EH 007C6FH 007C70H 007C71H 007C72H 007C73H 007C74H 007C75H 007C76H 007C77H 007C78H 007C79H 007C7AH 007C7BH 007C7CH 007C7DH 007C7EH 007C7FH 450 DLC register 0 DLCR0 R/W XXXXXXXX DLC register 1 DLCR1 R/W XXXXXXXX DLC register 2 DLCR2 R/W XXXXXXXX DLC register 3 DLCR3 R/W XXXXXXXX DLC register 4 DLCR4 R/W XXXXXXXX DLC register 5 DLCR5 R/W XXXXXXXX DLC register 6 DLCR6 R/W XXXXXXXX DLC register 7 DLCR7 R/W XXXXXXXX DLC register 8 DLCR8 R/W XXXXXXXX DLC register 9 DLCR9 R/W XXXXXXXX DLC register 10 DLCR10 R/W XXXXXXXX DLC register 11 DLCR11 R/W XXXXXXXX DLC register 12 DLCR12 R/W XXXXXXXX DLC register 13 DLCR13 R/W XXXXXXXX DLC register 14 DLCR14 R/W XXXXXXXX DLC register 15 DLCR15 R/W XXXXXXXX ■ List of Message Buffer (data register) Table 21.3-4 List of Message Buffer (data register) Address Register Abbreviation Access Initial Value CAN1 007C80H to 007C87H Data register 0 (8 bytes) DTR0 R/W XXXXXXXX to XXXXXXXX 007C88H to 007C8FH Data register 1 (8 bytes) DTR1 R/W XXXXXXXX to XXXXXXXX 007C90H to 007C97H Data register 2 (8 bytes) DTR2 R/W XXXXXXXX to XXXXXXXX 007C98H to 007C9FH Data register 3 (8 bytes) DTR3 R/W XXXXXXXX to XXXXXXXX 007CA0H to 007CA7H Data register 4 (8 bytes) DTR4 R/W XXXXXXXX to XXXXXXXX 007CA8H to 007CAFH Data register 5 (8 bytes) DTR5 R/W XXXXXXXX to XXXXXXXX 007CB0H to 007CB7H Data register 6 (8 bytes) DTR6 R/W XXXXXXXX to XXXXXXXX 007CB8H to 007CBFH Data register 7 (8 bytes) DTR7 R/W XXXXXXXX to XXXXXXXX 007CC0H to 007CC7H Data register 8 (8 bytes) DTR8 R/W XXXXXXXX to XXXXXXXX 007CC8H to 007CCFH Data register 9 (8 bytes) DTR9 R/W XXXXXXXX to XXXXXXXX 007CD0H to 007CD7H Data register 10 (8 bytes) DTR10 R/W XXXXXXXX to XXXXXXXX 007CD8H to 007CDFH Data register 11 (8 bytes) DTR11 R/W XXXXXXXX to XXXXXXXX 007CE0H to 007CE7H Data register 12 (8 bytes) DTR12 R/W XXXXXXXX to XXXXXXXX 007CE8H to 007CEFH Data register 13 (8 bytes) DTR13 R/W XXXXXXXX to XXXXXXXX 007CF0H to 007CF7H Data register 14 (8 bytes) DTR14 R/W XXXXXXXX to XXXXXXXX 007CF8H to 007CFFH Data register 15 (8 bytes) DTR15 R/W XXXXXXXX to XXXXXXXX 451 CHAPTER 21 CAN CONTROLLER 21.4 Classifying CAN Controller Registers There are 3 types of CAN controller registers; • Overall control registers • Message buffer control registers • Message buffers ■ Overall Control Registers The overall control registers are the following 4 registers; • Control status register (CSR) • Last event indicator register (LEIR) • Receive and transmit error counter (RTEC) • Bit timing register (BTR) ■ Message Buffer Control Registers The message buffer control registers are the following 14 registers; • Message buffer valid register (BVALR) • IDE register (IDER) • Transmission request register (TREQR) • Transmission RTR register (TRTRR) • Remote frame receiving wait register (RFWTR) • Transmission cancel register (TCANR) • Transmission complete register (TCR) • Transmission interrupt enable register (TIER) • Reception complete register (RCR) • Remote request receiving register (RRTRR) • Receive overrun register (ROVRR) • Reception interrupt enable register (RIER) • Acceptance mask select register (AMSR) • Acceptance mask registers 0 and 1 (AMR0 and AMR1) ■ Message Buffers The message buffers are the following 3 registers; • ID register x (x = 0 to 15) (IDRx) • DLC register x (x = 0 to 15) (DLCRx) • Data register x (x = 0 to 15) (DTRx) 452 21.4.1 Configuration of Control Status Register (CSR) This register indicates bus operation, node status, transmit output enable and transmit/ receive status. The lower 8-bit with the control status register (CSR) is prohibited from executing any bit manipulation instructions (Read-Modify-Write instructions). Only in the case of HALT bits unchanged (initialization of the macro instructions etc.), there is no problem even if any bit manipulation instructions is used. ■ Control Status Register (CSR) (Lower) Figure 21.4-1 Configuration of the Control Status Register (lower byte) Address: 7 6 5 4 3 2 CAN1: 007D00H TOE R/W NIE - - - - CSR1 (Lower) 0 1 Reserved HALT R/W Reset Vaue 0XXXX0X1B W R/W bit0 HALT 0 1 Bus operation styop bit Write: Stop of bus operation is released. Read:The state of bus operation is not stop mode Write: Stops bus operation Read: Bus operation in stop mode bit1 Reserved Reserved bit 0 Always write "0" to this bit. bit2 NIE 0 1 Node status transition interrupt enable Node status transition interrupt enabled Node status transition interrupt disabled bit7 R/W W X - TOE 0 1 : Read/Writ : Write only : Undefined : Unused : Reset value Transmit output enable General-purpose port pin Transmit pin of TX ■ Control Status Register (CSR) (upper) Figure 21.4-2 Configuration of the Control Status Register (upper byte) CSR1 (High) Address: CAN1: 007D01H 15 14 TS RS R R 13 12 11 10 9 8 NT NS1 NS0 - - - R/W R Reset value 00XXX000 B R bit9 NS1 0 0 1 1 bit8 Node status bit NS0 0 Error active 1 Warning (error active) Error passive 0 Bus off 1 bit10 NT Node status transfer flag 0 With node status transfer 1 Without node status reansfer R/W R X - : Read/Write : Read only : Undefined : Unused : Reset value bit14 RS Reception status bit 0 Message is not received. 1 Massage is being received. bit15 TS Transfer status bit 0 Message is not transferred. 1 Message is being transferred. 453 CHAPTER 21 CAN CONTROLLER 21.4.2 Function of Control Status Register (CSR) The operating status of the register’s each bit is confirmed by following; • Setting "0" or "1" • Function control by writing • Read ■ Control Status Register (CSR-lower) Table 21.4-1 Function of Each Bit of the Control Status Register (CSR:L) Bit Name Function bit7 TOE: Transmit output enable bit This bit switches from a general-purpose I/O port to a transmit pin TX. When setting to 0: Functions as general-purpose I/O port. When setting to 1: Functions as transmit pin TX. bit6 to bit3 Undefined bits When reading: Value is undefined. When writing: No effect bit2 NIE: Node status transition interrupt output enable bit This bit controls a node status transition interrupt generation (CSR: NT = 1) when a node status is transferred. When setting to 0: Interrupt generation is disabled. When setting to 1: Interrupt generation is enabled. bit1 Reserved: Reserved bit This bit is always set to 0. When reading: The value is always 0. bit0 HALT: Bus operation halt bit This bit controls the bus halt. The halt state of the bus can be checked by reading this bit. Writing to this bit: 0: Cancels bus halt 1: Halt bus Reading from this bit: 0: Bus operation not in stop state 1: Bus operation in stop state Note: After ensuring that 1 is written to this bit, write 0 to this bit if the node status is Bus Off. Example program: switch ( IO_CANCT1.CSR.bit.NS ) { case 0 : /* error active */ break; case 1 : /* warning */ break; case 2 : /* error passive */ break; default : /* bus off */ for ( i=0; ( i <= 500 ) || ( IO_CANCT1.CSR.bit.HALT == 0); i++); IO_CANCT1.CSR.word = 0x0084; /* HALT = 0 */ break; } *: The variable "i" is used for fail-safe. For detail information, see "21.4.4 Notes on Using Bus Operation Stop Bit (HALT = 1)". 454 ■ Control status register (CSR-upper) Table 21.4-2 Function of Each Bit of the Control Status Register (CSR:H) Bit Name Function bit15 TS: Transmit status bit This bit indicates whether a message is being transmitted. At read: 0: Message not being transmitted 1: Message being transmitted This bit is set 0 even while error and overload frames are transmitted. bit14 RS: Receive status bit This bit indicates whether a message is being received. At read: 0: Message not being received 1: Message being received • While a message is on the bus, this bit becomes 1. Therefore, this bit is also 1 while a message is being transmitted. This bit does not necessarily indicates whether a receiving message passes through the acceptance filter. • As a result, when this bit is 0, it implies that the bus operation is stopped (HALT = 1); the bus is in the intermission/bus idle or a error/overload frame is on the bus. bit13 to bit11 Undefined bits When reading: The value is undefined. When writing: No effect bit10 NT: Node status transition flag When the node status changes from increment transition or off bus into error active, this bit is set to "1". The condition that this bit is set to "1" is as follows. At this time, the interruption is generated for the node status interruption permission bit (NIE) = "1". 1) Error active ("00B") → Warning ("01B") 2) Warning ("01B") → Error passive ("10B") 3) Error passive ("10B") → Bus off ("11B") 4) Bus off ("11B") → Error active ("00B") Note: In parentheses, the value of NS1 and the NS0 bit is indicated. At Write: "0": Cleared "1": Not possible to set (No effect) At read by the instruction of the read-modify-write type: Always read "1". bit9 bit8 NS1, NS0: Node status bits These bits indicate the current node status. For detail information, see "21.4.3 Correspondence between Node Status Bit and Node Status". 455 CHAPTER 21 CAN CONTROLLER 21.4.3 Correspondence between Node Status Bit and Node Status Node status bit shows the node status by two bits (NS1 and NS0). ■ Correspondence between Node Status Bit and Node Status Table 21.4-3 Correspondence between NS1 and NS0 and Node Status NS1 NS0 Node status 0 0 Error active 0 1 Warning (error active) 1 0 Error passive 1 1 Bus off Note: Warning (error active) is included in the error active in CAN Specification 2.0B for the node status, however, indicates that the transmit error counter or receive error counter has exceeded 96. The node status change diagram is shown in Figure 21.4-3 . Figure 21.4-3 Node Status Transition Diagram Hardware reset It is necessary to cancel the bus operation halt for the shift. Error active REC: Receive error counter TEC: Transmit error counter REC ≥ 96 or TEC ≥ 96 REC < 96 and TEC < 96 Warning (Error active) After 0 has been written to the HALT bit of the register (CSR), continuous 11-bit High levels (recessive bits) are input 128 times to the the shift. REC ≥ 128 or TEC ≥ 128 REC < 128 and TEC < 128 Error passive 456 TEC ≥ 256 Bus off (HALT=1) 21.4.4 Notes on Using Bus Operation Stop Bit (HALT = 1) The bus operation stop bit is set by writing to the bit, hardware reset and the node status. The stop operation of the bus operation is different according to the state of the message buffer. ■ Conditions for Setting Bus Operation Stop (HALT=1) There are 3 conditions for setting bus operation stop (HALT = 1): • After hardware reset • When node status changed to bus off • By writing 1 to HALT Notes: • The bus operation should be stopped by writing 1 to HALT before the F2MC-16LX is changed in lowpower consumption mode (stop mode and timebase timer mode). If transmission is in progress when 1 is written to HALT, the bus operation is stopped (HALT = 1) after transmission is terminated. If reception is in progress when 1 is written to HALT, the bus operation is stopped immediately (HALT = 1). If received messages are being stored in the message buffer (x), stop the bus operation (HALT = 1) after storing the messages. • To check whether the bus operation has stopped, always read the HALT bit. ■ Conditions for Canceling Bus Operation Stop (HALT = 0) The condition for canceling the bus operation if halt is writing 0 to HALT. Notes: • Canceling the bus operation stop after hardware reset or by writing 1 to HALT as above conditions is performed after 0 is written to HALT and continuous 11-bit High levels (recessive bits) have been input to the receive input pin (RX) (HALT = 0). • Canceling the bus operation stop when the node status is changed to bus off as above conditions is performed after 0 is written to HALT and continuous 11-bit High levels (recessive bits) have been input 128 times to the receive input pin (RX) (HALT = 0). Then, the values of both transmit and receive error counters reach 0 and the node status is changed to error active. • When write 0 to HALT during the node status is Bus Off, ensure that 1 is written to this bit. ■ State during Bus Operation Stop (HALT = 1) • The bus does not perform any operation, such as transmission and reception. • The transmit output pin (TX) outputs a High level (recessive bit). • The values of other registers and error counters are not changed. Note: The bit timing register (BTR) should be set during bus operation stop (HALT = 1). 457 CHAPTER 21 CAN CONTROLLER 21.4.5 Last Event Indicator Register (LEIR) This register indicates the last event. The NTE, TCE, and RCE bits are exclusive. When the corresponding bit of the last event is set to 1, other bits are set to 0. ■ Last Event Indicator Register (LEIR) Figure 21.4-4 Configuration of the Last Event Indicator Register (LEIR) Address: bit7 6 5 4 CAN1: 007D02H NTE TCE RCE R/W R/W R/W 3 2 1 LEIR1 0 Reset value 000X0000 MBP3 MBP2 MBP1 MBP0 - B R/W R/W R/W R/W bit3 bit2 bit1 bit0 MBP3 MBP2 MBP1 MBP0 0000B to 1111B (reset value: 0000B) Message buffer pointer bits Message buffer 0 to 15 bit5 RCE 0 1 Receive completion event bit Read Write The last event has not received, Bit clear The last event has received. No effect bit6 TCE 0 1 Transmit completion event bit Read Write The last event has not transferred, Bit clear The last event has transferred. No effect bit7 NTE R/W : Read/Write X : Undefined : Unused : Reset value 0 1 458 Node status transition event bit Read Write The last event has not node Bit clear status transferred, The last event has node status transferred, No effect ■ Last Event Indicator Register (LEIR) Table 21.4-4 Function of Each Bit of the Last Event Indicator Register (LEIR) (1 / 2) Bit Name Function bit7 NTE: Node status transition event bit When this bit is 1, node status transition is the last event. This bit is set to 1 after set either of bit of the control status register to "1" (CSR:NTx=1). • This setting is not related to the setting of NIE bit of the control status register (CSR). At Write: "0": Cleared "1": No effect At read by the instruction of the read-modify-write type: Always read "1". bit6 TCE: Transmit completion event bit When this bit is 1, it indicates that transmit completion is the last event. This bit is set to 1 after set either of bit of the transmit completion register to "1" (TCR:TCx=1). • This setting is not related to the setting of the transmit interrupt enable register (TIER). • When this bit is "1", MBP3 to MBP0 bits show the message buffer number (x) to complete the transmission of the message in the last event. At Write: "0": Cleared "1": No effect At read by the instruction of the read-modify-write type: Always read "1". bit5 RCE: Receive completion event bit When this bit is 1, it indicates that receive completion is the last event. This bit is set to 1 after set either of bit of the receive complete register to "1" (RCR:RCx=1). • This setting is not related to the setting of the receive interrupt enable register (RIER). • When this bit is "1", MBP3 to MBP0 bits show the message buffer number (x) to complete the transmission of the message in the last event. At Write: "0": Cleared "1": No effect At read by the instruction of the read-modify-write type: Always read "1". bit4 Undefined bit When reading: The value is undefined. When writing: No effect 459 CHAPTER 21 CAN CONTROLLER Table 21.4-4 Function of Each Bit of the Last Event Indicator Register (LEIR) (2 / 2) Bit Name bit3 to bit0 460 MBP3 to MBP0: Message buffer pointer bits Function When TCE bit or RCE bit is "1", these bits show the message buffer number (x) to generating of corresponding the last event. If the NTE bit is set to 1, these bits have no meaning. At Write: "0": Cleared "1": No effect At read by the instruction of the read-modify-write type: Always read "1". Note: If LEIR is accessed within an CAN interrupt handler, the event causing the interrupt is not necessarily the same as indicated by LEIR. In the time from interrupt request to the LEIR access by the interrupt handler there may occur other CAN events. 21.4.6 Receive and Transmit Error Counters (RTEC) The receive and transmit error counters indicate the counts for transmission errors and reception errors defined in the CAN specifications. These registers can only be read. ■ Register Configuration Figure 21.4-5 Configuration of the Receive and Transmit Error Counters Address CAN1: 007D05H bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 RTEC1(Upper) TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 Reset value 00000000B R R R R R R R R bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 RTEC1(Lower) REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 Reset value 00000000B R R R R R R R R Address CAN1: 007D04H R : Read only ■ Register Function Table 21.4-5 Function of Each Bit of the Receive and Transmit Error Counters (RTEC) Bit Name Function bit15 to bit8 TEC7 to TEC0: Transmit error counter bits These are transmit error counters. TEC7 to TEC0 values indicate 0 to 7 when the counter value is more than 256, and the subsequent increment is not counted for counter value. In this case, Bus Off is indicated for the node status (NS1 and NS0 of control status register CSR = 11). bit7 to bit0 REC7 to REC0: Receive error counter bits These are receive error counters. REC7 to REC0 values indicate 0 to 7 when the counter value is more than 256, and the subsequent increment is not counted for counter value. In this case, Error Passive is indicated for the node status (NS1 and NS0 of control status register CSR = 10). 461 CHAPTER 21 CAN CONTROLLER 21.4.7 Bit Timing Register (BTR) Bit timing register (BTR) sets the prescaler and bit timing setting. ■ Register Configuration Figure 21.4-6 Configuration of the Bit Timing Register (BTR) Address CAN1: 007D07H Address CAN1: R/W : X: −: 007D06H bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 − TS2.2 TS2.1 TS2.0 TS1.3 TS1.2 TS1.1 TS1.0 − R/W R/W R/W R/W R/W R/W R/W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 RSJ1 RSJ0 PSC5 PSC4 PSC3 PSC2 PSC1 PSC0 R/W R/W R/W R/W R/W R/W R/W R/W BTR1(Upper) Reset value X1 1 1 1 1 1 1 B BTR1(Lower) Reset value 11 1 1 1 1 1 1 B Read/Write Undefined Unused ■ Register Function Table 21.4-6 Function of Each Bit of the Bit Timing Register (BTR) Bit Name Function bit14 to bit12 TS2.2 to TS2.0: Time segment 2 setting bits 2 to 0 These bits define the number of the time quanta (TQ’s) for the time segment 2 (TSEG2). The time segment 2 is equal to the phase buffer segment 2 (PHASE_SEG2) in the CAN specification. bit11 to bit8 TS1.3 to TS1.0: Time segment 1 setting bits 3 to 0 These bits define the number of the time quanta (TQ’s) for the time segment 1 (TSEG1). The time segment 1 is equal to the propagation segment (PROP_SEG) + phase buffer segment 1 (PHASE_SEG1) in the CAN specification. bit7 bit6 RSJ1, RSJ0: Resynchronization jump width setting bits 1, 0 These bits define the number of the time quanta (TQ’s) for the resynchronization jump width. bit5 to bit0 PSC5 to PSC0: Prescaler setting bits 5 to 0 These bits define the time quanta (TQ) of the CAN controller. (see below for details.) Note: Please set (CSR: HALT=1) to bit timing register (BTR) after stopping the bus operation. Please release the bus operation stop by writing "0" in the HALT bit of the control status register after the setting of bit timing register (BTR) is ended. 462 21.4.8 Prescaler Setting by Bit Timing Register (BTR) The setting of bit timing register (BTR) corresponds to the bit time of prescaler in the CAN specification and the CAN controller segment. ■ Prescaler Settings The bit time segments defined in the CAN specification, and the CAN controller are shown in Figure 21.4-7 and Figure 21.4-8 respectively. Figure 21.4-7 Bit Time Segment in CAN Specification Nominal bit time SYNC_SEG PROP_SEG PHASE_SEG1 PHASE_SEG2 Sample point Figure 21.4-8 Bit Time Segment in CAN Controller Nominal bit time SYNC_SEG TSEG1 TSEG2 Sample point 463 CHAPTER 21 CAN CONTROLLER The relationship between PSC = PSC5 to PSC0, TSI = TS1.3 to TS1.0, TS2 = TS2.2 to TS2.0, and RSJ = RSJ1, RSJ0 TQ BT = (PSC + 1) x CLK = SYNC_SEG + TSEG1 + TSEG2 = (1 + (TS1 + 1) + (TS2 +1)) x TQ = (3 + TS1 +TS2) x TQ RSJW = (RSJ + 1) x TQ RSJ1 and RSJ0 is shown below. CLK: input clock (CLK) TQ: time quanta BT: bit time SYNC_SEG: synchronous segment TSEG1 and TSEG2: time segment 1 and 2 resynchronization jump width [(RSJ1 and RSJ0) +1] frequency division For correct operation, the following conditions should be met. For 1 PSC TSEG1 TSEG1 TSEG2 TSEG2 For PSC = 0: TSEG1 TSEG2 TSEG2 63: 2TQ RSJW 2TQ RSJW 5TQ 2TQ RSJW In order to meet the bit timing requirements defined in the CAN specification, additions have to be met, e.g. the propagation delay has to be considered. 464 21.4.9 Message Buffer Valid Register (BVALR) Message buffer valid register (BVALR) stores the validity of the message buffers or displays their state. ■ Register Configuration Figure 21.4-9 Configuration of the Message Buffer Valid Register (BVALR) Address CAN1: 000081H Address CAN1: 000080H bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 BVRLR1(Upper) BVAL15 BVAL14 BVAL13 BVAL12 BVAL11 BVAL10 BVAL9 BVAL8 Reset value 00000000B R/W R/W R/W R/W R/W R/W R/W R/W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 BVRLR1(Lower) BVAL7 BVAL6 BVAL5 BVAL4 BVAL3 BVAL2 BVAL1 BVAL0 Reset value 00000000B R/W R/W R/W R/W R/W R/W R/W R/W R/W : Read/Write ■ Register Function 0: Message buffer (x) invalid 1: Message buffer (x) valid If the message buffer (x) is set to invalid, it will not transmit or receive messages. If the buffer is set to invalid during transmission operating, it becomes invalid (BVALx = 0) after the transmission is completed or terminated by an error. If the buffer is set to invalid during reception operating, it immediately becomes invalid (BVALx = 0). If received messages are stored in a message buffer (x), the message buffer (x) is invalid after storing the messages. Notes: • x indicates a message buffer number (x = 0 to 15). • When invaliding a message buffer (x) by writing 0 to a bit (BVALx), execution of a bit manipulation instruction is prohibited until the bit is set to 0. • To invalidate the message buffer (by setting the BVALR: BVAL bit to 0) while the CAN controller is operating for CAN communication (the read value of the CSR: HALT bit is 0 and the CAN controller is operating for CAN bus communication to enable transmission and reception), follow the procedure in "21.13 Precautions when Using CAN Controller". 465 CHAPTER 21 CAN CONTROLLER 21.4.10 IDE Register (IDER) This register stores the frame format used by the message buffers (x) during transmission/reception. ■ Register Configuration Figure 21.4-10 Configuration of the IDE Register (IDER) Address CAN1: 007D09H Address CAN1: 007D08H bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 IDER1(upper) IDE15 IDE14 IDE13 IDE12 IDE11 IDE10 IDE9 IDE8 Reset value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 IDER1(Lower) IDE7 IDE6 IDE5 IDE4 IDE3 IDE2 IDE1 IDE0 Reset value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W R/W : Read/Write X : Undefined ■ Register Function 0: The standard frame format (ID11 bit) is used for the message buffer (x). 1: The extended frame format (ID29 bit) is used for the message buffer (x). Notes: • This register should be set when the message buffer (x) is invalid (BVALx of the message buffer valid register (BVALR) = 0). Setting when the buffer is valid (BVALx = 1) may cause unnecessary received messages to be stored. • To invalidate the message buffer (by setting the BVALR: BVAL bit to 0) while the CAN controller is operating for CAN communication (the read value of the CSR: HALT bit is 0 and the CAN controller is operating for CAN bus communication to enable transmission and reception), follow the procedure in "21.13 Precautions when Using CAN Controller". 466 21.4.11 Transmission Request Register (TREQR) Transmission request register (TREQR) stores transmission requests to the message buffers (x) or displays their state. ■ Register Configuration Figure 21.4-11 Configuration of the Transmission Request Register (TREQR) Address CAN1: 000083H Address CAN1: 000082H bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 TREQR1(Upper) TREQ15 TREQ14 TREQ13 TREQ12 TREQ11 TREQ10 TREQ9 TREQ8 Reset value 00000000B R/W R/W R/W R/W R/W R/W R/W R/W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 TREQR1(Lower) TREQ7 TREQ6 TREQ5 TREQ4 TREQ3 TREQ2 TREQ1 TREQ0 Reset value 00000000B R/W R/W R/W R/W R/W R/W R/W R/W R/W : Read/Write ■ Register Function When 1 is written to TREQx, transmission to the message buffer (x) starts. If RFWTx of the remote frame receiving wait register (RFWTR) *1 is 0, transmission starts immediately. However, if RFWTx = 1, transmission starts after waiting until a remote frame is received (RRTRx of the remote request receiving register (RRTRR)*1 becomes 1). Transmission starts RFWTx = 1, if RRTRx is already 1 when 1 is written to TREQx. *2 immediately even when *1: For RFWTR and TRTRR, see "21.4.12 Transmission RTR Register (TRTRR)" and "21.4.13 Remote Frame Receiving Wait Register (RFWTR)". *2: For cancellation of transmission, see "21.4.14 Transmission Cancel Register (TCANR)" and "21.4.15 Transmission Complete Register (TCR)". Writing 0 to TREQx is ignored. 0 is read when a Read Modify Write instruction is performed. If clearing (to 0) at completion of the transmit operation and setting by writing 1 are concurrent, clearing is preferred. If 1 is written to more than 1 bit, transmission is performed, starting with the lower-numbered message buffer (x). TREQx is 1 while transmission is pending, and becomes 0 when transmission is completed or canceled. 467 CHAPTER 21 CAN CONTROLLER 21.4.12 Transmission RTR Register (TRTRR) This register stores the RTR (Remote Transmission Request) bits for the message buffers (x). ■ Register Configuration Figure 21.4-12 Configuration of the Transmission RTR Register (TRTRR) Address CAN1: 007D0BH Address CAN1: 007D0AH bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 TRTRR1(Upper) TRTR15 TRTR14 TRTR13 TRTR12 TRTR11 TRTR10 TRTR9 TRTR8 Reset value 00000000B R/W R/W R/W R/W R/W R/W R/W R/W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 TRTRR1(Lower) TRTR7 TRTR6 TRTR5 TRTR4 TRTR3 TRTR2 TRTR1 TRTR0 Reset value 00000000B R/W R/W R/W R/W R/W R/W R/W R/W R/W : Read/Write ■ Register Function 0: Transmit data frame. 1: Transmit remote frame. 468 21.4.13 Remote Frame Receiving Wait Register (RFWTR) Remote frame receiving wait register (RFWTR) sets the conditions for starting transmission when a request for data frame transmission is set (TREQx of the transmission request register (TREQR) is 1 and TRTRx of the transmitting RTR register (TRTRR) is 0). ■ Register Configuration Figure 21.4-13 Configuration of the Remote Frame Receiving Wait Register (RFWTR) Address CAN1: 007D0DH Address CAN1: 007D0CH bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 RFWT15 RFWT14 RFWT13 RFWT12 RFWT11 RFWT10 RFWT9 RFWT8 R/W R/W R/W R/W R/W R/W R/W R/W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 RFWT7 RFWT6 RFWT5 RFWT4 RFWT3 RFWT2 RFWT1 RFWT0 R/W R/W R/W R/W R/W R/W R/W R/W RFWTR1(Upper) Reset value XXXXXXXXB RFWTR1(Lower) Reset value XXXXXXXXB R/W : Read/Write X : Undefined ■ Register Function 0: Transmission starts immediately 1: Transmission starts after waiting until remote frame received (RRTRx of remote request receiving register (RRTRR) becomes 1) Notes: • Transmission starts immediately if RRTRx is already 1 when a request for transmission is set. • For remote frame transmission, do not set RFWTx to 1. 469 CHAPTER 21 CAN CONTROLLER 21.4.14 Transmission Cancel Register (TCANR) This register cancels a pending request for transmission to the message buffer (x). ■ Register Configuration Figure 21.4-14 Configuration of the Transmission Cancel Register (TCANR) Address CAN1: 000085H Address CAN1: 000084H bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 TCANR1(Upper) TCAN15 TCAN14 TCAN13 TCAN12 TCAN11 TCAN10 TCAN9 TCAN8 Reset value 00000000B W W W W W W W W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 TCANR1(Lower) TCAN7 TCAN6 TCAN5 TCAN4 TCAN3 TCAN2 TCAN1 TCAN0 Reset value 00000000B W W W W W W W W W : Write only ■ Register Function When 1 is written to TCANx, this register cancels a pending request for transmission to the message buffer (x). At completion of cancellation, TREQx of the transmission request register (TREQR) becomes 0. Writing 0 to TCANx is ignored. This is a write-only register and its read value is always 0. 470 21.4.15 Transmission Complete Register (TCR) At completion of transmission by the message buffer (x), the corresponding TCx becomes 1. If TIEx of the transmission complete interrupt enable register (TIER) is 1, an interrupt occurs. ■ Register Configuration Figure 21.4-15 Configuration of the Transmission Complete Register (TCR) Address CAN1: 000087H Address CAN1: 000086H bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 TCR1(Upper) TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8 Reset value 00000000B R/W R/W R/W R/W R/W R/W R/W R/W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 TCR1(Lower) TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 Reset value 00000000B R/W R/W R/W R/W R/W R/W R/W R/W R/W : Read/Write X : Undefined ■ Register Function ● Conditions for TCx = 0 • Write 0 to TCx. • Write 1 to TREQx of the transmission request register (TREQR). After the completion of transmission, write 0 to TCx to set it to 0. Writing 1 to TCx is ignored. 1 is read when a Read Modify Write instruction is performed. Note: If setting to 1 by completion of the transmit operation and clearing to 0 by writing occur at the same time, the bit is set to 1. 471 CHAPTER 21 CAN CONTROLLER 21.4.16 Transmission Interrupt Enable Register (TIER) This register enables or disables the transmission interrupt by the message buffer (x). The transmission interrupt is generated at transmission completion (when TCx of the transmission complete register (TCR) is 1). ■ Register Configuration Figure 21.4-16 Configuration of the Transmission Interrupt Enable Register (TIER) Address CAN1: 007D0FH Address CAN1: 007D0EH bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 TIER1(Upper) TIE15 TIE14 TIE13 TIE12 TIE11 TIE10 TIE9 TIE8 Reset value 00000000B R/W R/W R/W R/W R/W R/W R/W R/W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 TIER1(Lower) TIE7 TIE6 TIE5 TIE4 TIE3 TIE2 TIE1 TIE0 Reset value 00000000B R/W R/W R/W R/W R/W R/W R/W R/W R/W : Read/Write ■ Register Function 0: Transmission interrupt disabled. 1: Transmission interrupt enabled. 472 21.4.17 Reception Complete Register (RCR) At completion of storing received message in the message buffer (x), RCx becomes 1. If RIEx of the reception complete interrupt enable register (RIER) is 1, an interrupt occurs. ■ Register Configuration Figure 21.4-17 Configuration of the Reception Complete Register (RCR) Address CAN1: 000089H Address CAN1: 000088H bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 RCR1(Upper) RC15 RC14 RC13 RC12 RC11 RC10 RC9 RC8 Reset value 00000000B R/W R/W R/W R/W R/W R/W R/W R/W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 RCR1(Lower) RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 Reset value 00000000B R/W R/W R/W R/W R/W R/W R/W R/W R/W : Read/Write ■ Register Function ● Conditions for RCx = 0 Write 0 to RCx. After completion of handling received message, write 0 to RCx to set it to 0. Writing 1 to RCx is ignored. 1 is read when a Read Modify Write instruction is performed. Note: If setting to 1 by completion of the receive operation and clearing to 0 by writing occur at the same time, the bit is set to 1. 473 CHAPTER 21 CAN CONTROLLER 21.4.18 Remote Request Receiving Register (RRTRR) After a remote frame is stored in the message buffer (x), RRTRx becomes 1 (at the same time as RCx setting to 1). ■ Register Configuration Figure 21.4-18 Configuration of the Remote Request Receiving Register (RRTRR) Address CAN1: 00008BH Address CAN1: 00008AH bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 RRTRR1(Upper) RRTR15 RRTR14 RRTR13 RRTR12 RRTR11 RRTR10 RRTR9 RRTR8 Reset value 00000000B R/W R/W R/W R/W R/W R/W R/W R/W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 RRTRR1(Lower) RRTR7 RRTR6 RRTR5 RRTR4 RRTR3 RRTR2 RRTR1 RRTR0 Reset value 00000000B R/W R/W R/W R/W R/W R/W R/W R/W R/W : Read/Write ■ Register Function ● Conditions for RRTRx = 0 • Write 0 to RRTRx. • After a received data frame is stored in the message buffer (x) (at the same time as RCx setting to 1). • Transmission by the message buffer (x) is completed (TCx of the transmission complete register (TCR) is 1). Writing 1 to RRTRx is ignored. 1 is read when a Read Modify Write instruction is performed. Note: If setting to 1 by completion of the receive operation and clearing to 0 by writing occur at the same time, the bit is set to 1. 474 21.4.19 Receive Overrun Register (ROVRR) If RCx of the reception complete register (RCR) is 1 when completing storing of a received message in the message buffer (x), ROVRx becomes 1, indicating that reception has overrun. ■ Register Configuration Figure 21.4-19 Configuration of the Receive overrun Register (ROVRR) Address CAN1: 00008DH Address CAN1: 00008CH bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 ROVRR1(Upper) RVOR15 RVOR14 RVOR13 RVOR12 RVOR11 RVOR10 RVOR9 RVOR8 Reset value 00000000B R/W R/W R/W R/W R/W R/W R/W R/W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ROVRR1(Lower) RVOR7 RVOR6 RVOR5 RVOR4 RVOR3 RVOR2 RVOR1 RVOR0 Reset value 00000000B R/W R/W R/W R/W R/W R/W R/W R/W R/W : Read/Write ■ Register Function Writing 0 to ROVRx results in ROVRx = 0. Writing 1 to ROVRx is ignored. After checking that reception has overrun, write 0 to ROVRx to set it to 0. 1 is read when a Read-Modify-Write instruction is performed. Note: If setting to 1 by completion of the receive operation and clearing to 0 by writing occur at the same time, the bit is set to 1. 475 CHAPTER 21 CAN CONTROLLER 21.4.20 Reception Interrupt Enable Register (RIER) Reception interrupt enable register (RIER) enables or disables the reception interrupt by the message buffer (x). The reception interrupt is generated at reception completion (when RCx of the reception completion register (RCR) is 1). ■ Register Configuration Figure 21.4-20 Configuration of the Reception Interrupt Enable Register (RIER) Address CAN1: 00008FH Address CAN1: 00008EH bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 RIER1(Upper) RIE15 RIE14 RIE13 RIE12 RIE11 RIE10 RIE9 RIE8 Reset value 00000000B R/W R/W R/W R/W R/W R/W R/W R/W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 RIE7 RIE6 RIE5 RIE4 RIE3 RIE2 RIE1 RIE0 R/W R/W R/W R/W R/W R/W R/W R/W R/W : Read/Write ■ Register Function 0: Reception interrupt disabled. 1: Reception interrupt enabled. 476 RIER1(Lower) Reset value 00000000B 21.4.21 Acceptance Mask Select Register (AMSR) This register selects masks (acceptance mask) for comparison between the received message ID’s and the message buffer ID. ■ Register Configuration Figure 21.4-21 Configuration of the Acceptance Mask Select Register (AMSR) Address CAN1: 007D10H Address CAN1: 007D11H Address CAN1: 007D12H Address CAN1: 007D13H bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 AMS3.1 AMS3.0 AMS2.1 AMS2.0 AMS1.1 AMS1.0 AMS0.1 AMS0.0 R/W R/W R/W R/W R/W R/W R/W R/W bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 AMS7.1 AMS7.0 AMS6.1 AMS6.0 AMS5.1 AMS5.0 AMS4.1 AMS4.0 R/W R/W R/W R/W R/W R/W R/W R/W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 AMS11.1 AMS11.0 AMS10.1 AMS10.0 AMS9.1 AMS9.0 AMS8.1 AMS8.0 R/W R/W R/W R/W R/W R/W R/W R/W bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 AMS15.1 AMS15.0 AMS14.1 AMS14.0 AMS13.1 AMS13.0 AMS12.1 AMS12.0 R/W R/W R/W R/W R/W R/W R/W R/W AMSR1(Byte0) Reset value XXXXXXXXB AMSR1(Byte1) Reset value XXXXXXXXB AMSR1(Byte2) Reset value XXXXXXXXB AMSR1(Byte3) Reset value XXXXXXXXB R/W : Read/Write X : Undefined 477 CHAPTER 21 CAN CONTROLLER ■ Register Function Table 21.4-7 Selection of Acceptance Mask AMSx.1 AMSx.0 Acceptance Mask 0 0 Full-bit comparison 0 1 Full-bit mask 1 0 Acceptance mask register 0 (AMR0) 1 1 Acceptance mask register 1 (AMR1) Notes: • AMSx.1 and AMSx.0 should be set when the message buffer (x) is invalid (BVALx of the message buffer valid register (BVALR) is 0). Setting when the buffer is valid (BVALx = 1) may cause unnecessary received messages to be stored. • To invalidate the message buffer (by setting the BVALR: BVAL bit to 0) while the CAN controller is operating for CAN communication (the read value of the CSR: HALT bit is 0 and the CAN controller is operating for CAN bus communication to enable transmission and reception), follow the procedure in "21.13 Precautions when Using CAN Controller". 478 21.4.22 Acceptance Mask Registers 0 and 1 (AMR0 and AMR1) There are two acceptance mask registers, which are available either in the standard frame format or extended frame format. AM28 to AM18 (11 bits) are used for acceptance masks in the standard frame format and AM28 to AM0 (29 bits) are used for acceptance masks in the extended format. ■ Register Configuration Figure 21.4-22 Configuration of the Acceptance Mask Register 0 (AMR0) Address CAN1: 007D14H Address CAN1: 007D15H Address CAN1: 007D16H Address CAN1: R/W X − 007D17H bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 AMR01(Byte0) AM28 AM27 AM26 AM25 AM24 AM23 AM22 AM21 R/W R/W R/W R/W R/W R/W R/W R/W bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 AM20 AM19 AM18 AM17 AM16 AM15 AM14 AM13 R/W R/W R/W R/W R/W R/W R/W R/W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 AMR01(Byte2) AM12 AM11 AM10 AM9 AM8 AM7 AM6 AM5 Reset value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 AM4 AM3 AM2 AM1 AM0 − − − R/W R/W R/W R/W R/W − − − Reset value XXXXXXXXB AMR01(Byte1) Reset value XXXXXXXXB AMR01(Byte3) Reset value XXXXXXXXB : Read/Write : Undefined : Unused : Used bit in typical frame format 479 CHAPTER 21 CAN CONTROLLER Figure 21.4-23 Configuration of the Acceptance Mask Register 1 (AMR1) Address CAN1: 007D18H Address CAN1: 007D19H Address CAN1: 007D1AH Address CAN1: R/W X − 007D1BH bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 AMR11(Byte0) AM28 AM27 AM26 AM25 AM24 AM23 AM22 AM21 R/W R/W R/W R/W R/W R/W R/W R/W bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 AM20 AM19 AM18 AM17 AM16 AM15 AM14 AM13 R/W R/W R/W R/W R/W R/W R/W R/W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 AMR11(Byte2) AM12 AM11 AM10 AM9 AM8 AM7 AM6 AM5 Reset value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 AM4 AM3 AM2 AM1 AM0 − − − R/W R/W R/W R/W R/W − − − Reset value XXXXXXXXB AMR11(Byte1) Reset value XXXXXXXXB AMR11(Byte3) Reset value XXXXXXXXB : Read/Write : Undefined : Unused : Used bit in typical frame format ■ Register Function ● 0: Compare Compare the bit (be set to "0") of the acceptance code (ID register IDRx for comparing with the received message ID) corresponding to this bit with the bit of the received message ID. If there is no match, no message is received. ● 1: Mask Mask the bit of the acceptance code ID register (IDRx) corresponding to this bit. No comparison is made with the bit of the received message ID. Notes: • AMR0 and AMR1 should be set when all the message buffers (x) selecting AMR0 and AMR1 are invalid (BVALx of the message buffer valid register (BVALR) is 0). Setting when the buffers are valid (BVALx = 1) may cause unnecessary received messages to be stored. • To invalidate the message buffer (by setting the BVALR: BVAL bit to 0) while the CAN controller is operating for CAN communication (the read value of the CSR: HALT bit is 0 and the CAN controller is operating for CAN bus communication to enable transmission and reception), follow the procedure in "21.13 Precautions when Using CAN Controller". 480 21.4.23 Message Buffers There are 16 message buffers. Message buffer x (x = 0 to 15) consists of an ID register (IDRx), DLC register (DLCRx), and data register (DTRx). ■ Message Buffers ● Register Configuration • ID register x (x = 0 to 15) (IDRx) This register is a ID register of the message buffer. This register memorizes receipt code setting, transmission message ID setting, and reception ID. • DLC register x (x = 0 to 15) (DLCRx) This register stores the DLC of the message buffer. This register sets the data length of the message when a data frame and a remote frame are transmitted and the data length of the message when a data frame or a remote frame is received. • Data register x (x = 0 to 15) (DTRx) This register is a data register of the message buffer. This register memorizes the setting or the reception message data of the transmission message data. ● The message buffer (x) is used both for transmission and reception. ● The lower-numbered message buffers are assigned higher priority. • At transmission, when a request for transmission is made to more than 1 message buffer, transmission is performed, starting with the lowest-numbered message buffer (See "21.5 Transmission of CAN Controller"). • At reception, when the received message ID passes through the acceptance filter (mechanism for comparing the acceptance-masked ID of received message and message buffer) of more than 1 message buffer, the received message is stored in the lowest-numbered message buffer (See "21.6 Reception of CAN Controller"). 481 CHAPTER 21 CAN CONTROLLER ● Message buffer that can be used as multi level message buffer When the same receipt filter is set in 1 or more message buffers, the message buffer can be used as a multi level message buffer. As a result, the reserve to the reception time is given. (See "21.10 Procedure for Reception by Message Buffer (x)"). Notes: • A write operation to message buffers and general-purpose RAM areas should be performed in words to even addresses only. A write operation in bytes causes undefined data to be written to the upper byte at writing to the lower byte. Writing to the upper byte is ignored. • When the BVALx bit of the message buffer valid register (BVALR) is 0 (Invalid), the message buffers x (IDRx, DLCRx, and DTRx) can be used as general-purpose RAM. During the receive/transmit operation of the CAN controller, the CAN Controller write/read to/from the message buffers. If the CPU tries to write/read to/from the message buffers in this period, the CPU has to wait a maximum time of 64 machine cycles. This is also true for the general-purpose RAM (Address 007A00H to 007A1FH, 007C00H to 007C1FH, 007E00H to 007E1FH). 482 21.4.24 ID Register x (x = 0 to 15) (IDRx) This register is the ID register for message buffer (x). ■ Register Configuration Figure 21.4-24 Configuration of the ID Registers (IDRx) Address CAN1: 007C20H + 4 × x Address CAN1: 007C21H + 4 × x Address CAN1: 007C22H + 4 × x Address CAN1: 007C23H + 4 × x bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 IDRx1(Byte0) ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 Reset value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 IDRx1(Byte1) ID20 ID19 ID18 ID17 ID16 ID15 ID14 ID13 Reset value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 IDRx1(Byte2) ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5 Reset value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 IDRx1(Byte3) ID4 ID3 ID2 ID1 ID0 − − − R/W R/W R/W R/W R/W − − − Reset value XXXXXXXXB x = 0, ..., 15 R/W X − : Read/Write : Undefined : Unused : Used bit in typical frame format 483 CHAPTER 21 CAN CONTROLLER ■ Register Function When using the message buffer (x) in the standard frame format (IDEx of the IDE register (IDER) = 0), use 11 bits of ID28 to ID18. When using the buffer in the extended frame format (IDEx = 1), use 29 bits of ID28 to ID0. ID28 to ID0 have the following functions; • Set acceptance code (ID for comparing with the received message ID). • Set transmitted message ID. Note: In the standard frame format, setting 1s to all bits of ID28 to ID22 is prohibited). • Store the received message ID. Note: All received message ID bits are stored (even if bits are masked). In the standard frame format, ID17 to ID0 stores image of old message left in the receive shift register. Notes: • A write operation to this register should be performed in words. A write operation in bytes causes undefined data to be written to the upper byte at writing to the lower byte. Writing to the upper byte is ignored. • This register should be set when the message buffer (x) is invalid (BVALx of the message buffer valid register (BVALR) is 0). Setting when the buffer is valid (BVALx = 1) may cause unnecessary received messages to be stored. • To invalidate the message buffer (by setting the BVALR: BVAL bit to 0) while the CAN controller is operating for CAN communication (the read value of the CSR: HALT bit is 0 and the CAN controller is operating for CAN bus communication to enable transmission and reception), follow the procedure in "21.13 Precautions when Using CAN Controller". 484 21.4.25 DLC Register x (x = 0 to 15) (DLCRx) This register is the DLC register for message buffer (x). ■ Register Configuration Figure 21.4-25 Configuration of the DLC Registers (DLCRx) Address CAN1: 007C60H + 2 × x bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 − − − − DLC3 DLC2 DLC1 DLC0 − − − − R/W R/W R/W R/W DLCR1x(Lower) Reset value XXXXXXXXB x = 0, ..., 15 R/W : Read/Write X : Undefined − : Unused ■ Register Function ● Transmission • Set the data length (byte count) of a transmitted message when a data frame is transmitted (TRTRx of the transmitting RTR register (TRTRR) is 0). • Set the data length (byte count) of a requested message when a remote frame is transmitted (TRTRx = 1). Note: Setting other than 0000B to 1000B (0 to 8 bytes) is prohibited. ● Reception • Store the data length (byte count) of a received message when a data frame is received (RRTRx of the remote frame request receiving register (RRTRR) is 0). • Store the data length (byte count) of a requested message when a remote frame is received (RRTRx = 1). Note: A write operation to this register should be performed in words. A write operation in bytes causes undefined data to be written to the upper byte at writing to the lower byte. Writing to the upper byte is ignored. 485 CHAPTER 21 CAN CONTROLLER 21.4.26 Data Register x (x = 0 to 15) (DTRx) This register is the data register for message buffer (x). This register is used only in transmitting and receiving a data frame but not in transmitting and receiving a remote frame. ■ Register Configuration Figure 21.4-26 Configuration of the Data Registers (DTRx) Address CAN1: 007C80H + 8 × x Address CAN1: 007C81H + 8 × x Address CAN1: 007C82H + 8 × x Address CAN1: 007C83H + 8 × x Address CAN1: 007C84H + 8 × x Address CAN1: 007C85H + 8 × x Address CAN1: 007C86H + 8 × x Address CAN1: 007C87H + 8 × x R/W : Read/Write X : Undefined − : Unused 486 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 DTRx1(Byte0) D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W Reset value XXXXXXXXB bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 DTRx1(Byte1) D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W Reset value XXXXXXXXB bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 DTRx1(Byte2) D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W Reset value XXXXXXXXB bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 DTRx1(Byte3) D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W Reset value XXXXXXXXB bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 DTRx1(Byte4) D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W Reset value XXXXXXXXB bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 DTRx1(Byte5) D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W Reset value XXXXXXXXB bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 DTRx1(Byte6) D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W Reset value XXXXXXXXB bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 DTRx1(Byte7) D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W Reset value XXXXXXXXB x = 0, ..., 15 ■ Register Function ● Sets transmitted message data (any of 0 to 8 bytes). Data is transmitted in the order of BYTE0, BYTE1, ..., BYTE7, starting with the MSB. ● Stores received message data. Data is stored in the order of BYTE0, BYTE1, ..., BYTE7, starting with the MSB. Even if the received message data is less than 8 bytes, the remaining bytes of the data register (DTRx), to which data are stored, are undefined. Note: A write operation to this register should be performed in words. A write operation in bytes causes undefined data to be written to the upper byte at writing to the lower byte. Writing to the upper byte is ignored. 487 CHAPTER 21 CAN CONTROLLER 21.5 Transmission of CAN Controller When 1 is written to TREQx of the transmission request register (TREQR), transmission by the message buffer (x) starts. At this time, TREQx becomes 1 and TCx of the transmission complete register (TCR) becomes 0. ■ Starting Transmission of CAN Controller If RFWTx of the remote frame receiving wait register (RFWTR) is 0, transmission starts immediately. If RFWTx is 1, transmission starts after waiting until a remote frame is received (RRTRx of the remote request receiving register (RRTRR) becomes 1). If a request for transmission is made to more than 1 message buffer (more than one TREQx is 1), transmission is performed, starting with the lowest-numbered message buffer. Message transmission to the CAN bus (by the transmit output pin TX) starts when the bus is idle. If TRTRx of the transmission RTR register (TRTRR) is 0, a data frame is transmitted. If TRTRx is 1, a remote frame is transmitted. If the message buffer competes with other CAN controllers on the CAN bus for transmission and arbitration fails, or if an error occurs during transmission, the message buffer waits until the bus is idle and repeats retransmission until it is successful. ■ Canceling Transmission Request from CAN Controller ● Canceling by transmission cancel register (TCANR) A transmission request for message buffer (x) having not executed transmission during transmission pending can be canceled by writing 1 to TCANx of the transmission cancel register (TCANR). At completion of cancellation, TREQx becomes 0. ● Canceling by storing received message The message buffer (x) having not executed transmission despite transmission request also performs reception. If the message buffer (x) has not executed transmission despite a request for transmission of a data frame (TRTRx = 0 or TREQx = 1), the transmission request is canceled after storing received data frames passing through the acceptance filter (TREQx = 0). Note: A transmission request is not canceled by storing remote frames (TREQx = 1 remains unchanged). If the message buffer (x) has not executed transmission despite a request for transmission of a remote frame (TRTRx = 1 or TREQx = 1), the transmission request is canceled after storing received remote frames passing through the acceptance filter (TREQx = 0). Note: The transmission request is canceled by storing either data frames or remote frames. 488 ■ Completing Transmission of CAN Controller When transmission is successful, RRTRx becomes 0, TREQx becomes 0, and TCx of the transmission complete register (TCR) becomes 1. If the transmission complete interrupt is enabled (TIEx of the transmission complete interrupt enable register (TIER) is 1), an interrupt occurs. ■ Transmission Flowchart of CAN Controller Figure 21.5-1 Transmission Flowchart of the CAN Controller Transmission request (TREQx:=1) TCx:=0 0 TREQx? 1 0 RFWTx? 1 0 RRTRx? 1 If there are any other message buffers meeting the above conditions, select the lowest-numbered message buffer. NO Is the bus idle? YES 0 1 TRTRx? A data frame is transmitted. A remote frame is transmitted. NO Is transmission successful? 0 YES TCANx? 1 RRTRx:= 0 TREQx:= 0 TCx := 1 TREQx:=0 1 TIEx? 0 A transmission complete interrupt occurs. End of transmission 489 CHAPTER 21 CAN CONTROLLER 21.6 Reception of CAN Controller Reception starts when the start of data frame or remote frame (SOF) is detected on the CAN bus. ■ Acceptance Filtering The received message in the standard frame format is compared with the message buffer (x) set in the standard frame format (IDEx of the IDE register (IDER) is 0). The received message in the extended frame format is compared with the message buffer (x) set (IDEx is 1) in the extended frame format. If all the bits set to Compare by the acceptance mask agree after comparison between the received message ID and acceptance code (ID register (IDRx) for comparing with the received message ID), the received message passes to the acceptance filter of the message buffer (x). ■ Storing Received Message When the receive operation is successful, received messages are stored in a message buffer x including IDs passed through the acceptance filter. When receiving data frames, received messages are stored in the ID register (IDRx), DLC register (DLCRx), and data register (DTRx). Even if received message data is less than 8 bytes, some data is stored in the remaining bytes of the DTRx and its value is undefined. When receiving remote frames, received messages are stored only in the IDRx and DLCRx, and the DTRx remains unchanged. If there is more than 1 message buffer including IDs passed through the acceptance filter, the message buffer x in which received messages are to be stored is determined according to the following rules. • The order of priority of the message buffer x (x = 0 to 15) rises as its number lower; in other words, message buffer 0 is given the highest and the message buffer 15 is given the lowest priority. • Basically, message buffers with the RCx bit of 0 in the receive completion register (RCR) are preferred in storing received messages. • If the bits of the acceptance mask select register (AMSR) are set to All Bits Compare (for message buffers with the AMSx.1 and AMSx.0 bits set to 00B), received messages are stored irrespective of the value of the RCx bit of the RCR. • If there are message buffers with the RCx bit of the RCR set to 0, or with the bits of the AMSR set to All Bits Compare, received messages are stored in the lowest-number (highest-priority) message buffer x. • If there are no message buffers above-mentioned, received messages are stored in a lower-number message buffer x. • Message buffers should be arranged in ascending numeric order. The lowest message buffers should be with All Bits Compare, then AMR0 or AMR1 masks. And The highest message buffers should be with All Bits Mask. 490 Figure 21.6-1 shows a flowchart for determining the message buffer (x) where received messages are to be stored. It is recommended that message buffers be arranged in the following order: message buffers in which each AMSR bit is set to All Bits Compare, message buffers using AMR0 or AMR1, and message buffers in which each AMSR bit is set to All Bits Mask. Figure 21.6-1 Flowchart Determining Message Buffer (x) where Received Messages Stored Start Are message buffers with RCx set to 0 or with AMSx.1 and AMSx.0 set to 00B found? NO YES Select the lowest-numbered message buffer from above message buffer. Select the lowest-numbered message buffer. End ■ Receive Overrun When a message is stored in the message buffer with the corresponding RCx being already set to 1, it will results in receive overrun. In this case, the corresponding ROVRx bit in the receive overrun register ROVRR is set to 1. ■ Processing for Reception of Data Frame and Remote Frame ● Processing for reception of data frame RRTRx of the remote request receiving register (RRTRR) becomes 0. TREQx of the transmission request register (TREQR) becomes 0 (immediately before storing the received message). A transmission request for message buffer (x) having not executed transmission will be canceled. Note: A request for transmission of either a data frame or remote frame is canceled. ● Processing for reception of remote frame RRTRx becomes 1. If TRTRx of the transmitting RTR register (TRTRR) is 1, TREQx becomes 0. As a result, the request for transmitting remote frame to message buffer having not executed transmission will be canceled. Notes: • A request for data frame transmission is not canceled. • For cancellation of a transmission request, see "21.5 Transmission of CAN Controller". 491 CHAPTER 21 CAN CONTROLLER ■ Completing Reception RCx of the reception complete register (RCR) becomes 1 after storing the received message. If a reception interrupt is enabled (RIEx of the reception interrupt enable register (RIER) is 1), an interrupt occurs. Note: This CAN controller will not receive any messages transmitted by itself. 492 21.7 Reception Flowchart of CAN Controller Figure 21.7-1 shows a reception flowchart of the CAN controller. ■ Reception Flowchart of the CAN Controller Figure 21.7-1 Reception Flowchart of the CAN Controller Detection of start of data frame or remote frame (SOF) NO Is any message buffer (x) passing to the acceptance filter found? YES NO Is reception successful? YES Determine message buffer (x) where received messages to be stored. Store the received message in the message buffer (x). 1 RCx? 0 Data frame ROVRx:=1 Remote frame Received message? RRTRx:=0 RRTRx:=1 1 TRTRx? 0 TREQx:=0 RCx:=1 RIEx? 0 1 A reception interrupt occurs. End of reception 493 CHAPTER 21 CAN CONTROLLER 21.8 How to Use CAN Controller The following settings are required to use the CAN controller; • Bit timing • Frame format • ID • Acceptance filter • Low-power consumption mode ■ Setting Bit Timing The bit timing register (BTR) should be set during bus operation stop (when the bus operation stop bit (HALT) of the control status register (CSR) is 1). After the setting completion, write 0 to HALT to cancel bus operation stop. ■ Setting Frame Format Set the frame format used by the message buffer (x). When using the standard frame format, set IDEx of the IDE register (IDER) to 0. When using the extended frame format, set IDEx to 1. This setting should be made when the message buffer (x) is invalid (BVALx of the message buffer valid register (BVALR) is 0). Setting when the buffer is valid (BVALx = 1) may cause unnecessary received messages to be stored. ■ Setting ID Set the message buffer (x) ID to ID28 to ID0 of ID register (IDRx). The message buffer (x) ID need not be set to ID11 to ID0 in the standard frame format. The message buffer (x) ID is used as a transmission message at transmission and is used as an acceptance code at reception. This setting should be made when the message buffer (x) is invalid (BVALx of the message buffer valid register (BVALR) is 0). Setting when the buffer is valid (BVALx = 1) may cause unnecessary received messages to be stored. ■ Setting Acceptance Filter The acceptance filter of the message buffer (x) is set by an acceptance code and acceptance mask set. It should be set when the acceptance message buffer (x) is invalid (BVALx of the message buffer enable register (BVALR) is 0). Setting when the buffer is valid (BVALx = 1) may cause unnecessary received messages to be stored. Set the acceptance mask used in each message buffer (x) by the acceptance mask select register (AMSR). The acceptance mask registers (AMR0 and AMR1) should also be set if used (For the setting details, see "21.4.21 Acceptance Mask Select Register (AMSR)" and "21.4.22 Acceptance Mask Registers 0 and 1 (AMR0 and AMR1)"). The acceptance mask should be set so that a transmission request may not be canceled when unnecessary received messages are stored. For example, it should be set to a full-bit comparison if only one specific ID is used for the transmission. 494 ■ Setting Low-power Consumption Mode To set the F2MC-16LX in a low-power consumption mode (Stop and Timebase timer), write 1 to the bus operation stop bit (HALT) of the control status register (CSR), and then check that the bus operation has stopped (HALT = 1). 495 CHAPTER 21 CAN CONTROLLER 21.9 Procedure for Transmission by Message Buffer (x) After setting the bit timing, frame format, ID, and acceptance filter, set BVALx to 1 to activate the message buffer (x). ■ Procedure for Transmission by Message Buffer (x) ● Setting transmit data length code Set the transmit data length code (byte count) to DLC3 to DLC0 of the DLC register (DLCRx). For data frame transmission (when TRTRx of the transmission RTR register (TRTRR) is 0), set the data length of the transmitted message. For remote frame transmission (when TRTRx = 1), set the data length (byte count) of the requested message. Note: Setting other than 0000B to 1000B (0 to 8 bytes) is prohibited. ● Setting transmit data (only for transmission of data frame) For data frame transmission (when TRTRx of the transmission register (TRTRR) is 0), set data as the count of byte transmitted in the data register (DTRx). Note: Transmit data should be rewritten while the TREQx bit of the transmission request register (TREQR) set to 0. There is no need for setting the BVALx bit of the message buffer valid register (BVALR) to 0. Setting the BVALx bit to 0 may cause incoming remote frame to be lost. ● Setting transmission RTR register For data frame transmission, set TRTRx of the transmission RTR register (TRTRR) to 0. For remote frame transmission, set TRTRx to 1. 496 ● Setting conditions for starting transmission (only for transmission of data frame) Set RFWTx of the remote frame receiving wait register (RFWTR) to 0 to start transmission immediately after a request for data frame transmission is set (TREQx of the transmission request register (TREQR) is 1 and TRTRx of the transmission RTR register (TRTRR) is 0). Set RFWTx to 1 to start transmission after waiting until a remote frame is received (RRTRx of the remote request receiving register (RRTRR) becomes 1) after a request for data frame transmission is set (TREQx = 1 and TRTRx = 0). Note: Remote frame transmission can not be made, if RFWTx is set to 1. ● Setting transmission complete interrupt When generating a transmission complete interrupt, set TIEx of the transmission complete interrupt enable register (TIER) to 1. When not generating a transmission complete interrupt, set TIEx to 0. ● Setting transmission request For a transmission request, set TREQx of the transmission request register (TREQR) to 1. ● Canceling transmission request When canceling a pending request for transmission to the message buffer (x), write 1 to TCANx of the transmission cancel register (TCANR). Check TREQx. For TREQx = 0, transmission cancellation is terminated or transmission is completed. Check TCx of the transmission complete register (TCR). For TCx = 0, transmission cancellation is terminated. For TCx = 1, transmission is completed. ● Processing for completion of transmission If transmission is successful, TCx of the transmission complete register (TCR) becomes 1. If the transmission complete interrupt is enabled (TIEx of the transmission complete interrupt enable register (TIER) is 1), an interrupt occurs. After checking the transmission completion, write 0 to TCx to set it to 0. This cancels the transmission complete interrupt. In the following cases, the pending transmission request is canceled by receiving and storing a message. • Cancel the request for data frame transmission by reception of data frame • Cancel the request for remote frame transmission by reception of data frame • Cancel the request for remote frame transmission by reception of remote frame Request for data frame transmission is not canceled by receiving and storing a remote frame. ID and DLC, however, are changed by the ID and DLC of the received remote frame. Note that the ID and DLC of data frame to be transmitted become the value of received remote frame. 497 CHAPTER 21 CAN CONTROLLER 21.10 Procedure for Reception by Message Buffer (x) After setting the bit timing, frame format, ID, and acceptance filter, make the settings described below. ■ Procedure for Reception by Message Buffer (x) ● Setting reception interrupt To enable reception interrupt, set RIEx of the reception interrupt enable register (RIER) to 1. To disable reception interrupt, set RIEx to 0. ● Starting reception When starting reception after setting, set BVALx of the message buffer valid register (BVALR) to 1 to make the message buffer (x) valid. ● Processing for reception completion If reception is successful after passing to the acceptance filter, the received message is stored in the message buffer (x) and RCx of the reception complete register (RCR) becomes 1. For data frame reception, RRTRx of the remote request receiving register (RRTRR) becomes 0. For remote frame reception, RRTRx becomes 1. If a reception interrupt is enabled (RIEx of the reception interrupt enable register (RIER) is 1), an interrupt occurs. After checking the reception completion (RCx = 1), process the received message. After completion of processing the received message, check ROVRx of the reception overrun register (ROVRR). If ROVRx = 0, the processed received message is valid. Write 0 to RCRx to set it to 0 (the reception complete interrupt is also canceled) to terminate reception. If ROVRx = 1, a reception overrun occurred and the next message may have overwritten the processed message. In this case, received messages should be processed again after setting the ROVRx bit to 0 by writing 0 to it. Figure 21.10-1 shows an example of receive interrupt handling. 498 Figure 21.10-1 Example of Receive Interrupt Handling Interrupt with RCx = 1 Read received messages. A:=ROVRx ROVRx:=0 A = 0? NO YES RCx:=0 End 499 CHAPTER 21 CAN CONTROLLER 21.11 Setting Configuration of Multi-level Message Buffer If the receptions are performed frequently, or if several different ID’s of messages are received, in other words, if there is insufficient time for handling messages, more than 1 message buffer can be combined into a multi-level message buffer to provide allowance for processing time of the received message by CPU. ■ Setting Configuration of Multi-level Message Buffer To provide a multi-level message buffer, the same acceptance filter must be set in the combined message buffers. If the bits of the acceptance mask select register (AMSR) are set to All Bits Compare ((AMSx.1, AMSx.0) = (0, 0)), multi-level message configuration of message buffers is not allowed. This is because All Bits Compare causes received messages to be stored irrespective of the value of the RCx bit of the receive completion register (RCR), so received messages are always stored in lower-numbered (higher-priority) message buffers even if All Bits Compare and identical acceptance code (ID register (IDRx)) are specified for more than 1 message buffer. Therefore, All Bits Compare and identical acceptance code should not be specified for more than 1 message buffer. Figure 21.11-1 shows operational examples of multi-level message buffers. 500 Figure 21.11-1 Examples of Operation of Multi-level Message Buffer Initialization AMS15, AMS14, AMS13 AMSR 10 10 10 Select AMR0. ... AM28 to AM18 AMS0 ID28 to ID18 0000 1111 111 RC15, RC14, RC13 IDE ... Message buffer 13 0101 0000 000 0 ... RCR 0 0 0 ... Message buffer 14 0101 0000 000 0 ... ROVRR 0 0 0 ... Message buffer 15 0101 0000 000 0 ... ROVR15, ROVR14, ROVR13 Mask Message receiving: The received message is stored in message buffer 13. IDE ID28 to ID18 Message receiving 0101 1111 000 0 ... Message buffer 13 0101 1111 000 0 ... RCR 0 0 1 ... Message buffer 14 0101 0000 000 0 ... ROVRR 0 0 0 ... Message buffer 15 0101 0000 000 0 ... Message receiving: The received message is stored in message buffer 14. Message receiving 0101 1111 001 0 ... Message buffer 13 0101 1111 000 0 ... RCR 0 1 1 ... ROVRR 0 0 0 ... Message buffer 14 0101 1111 001 0 ... Message buffer 15 0101 0000 000 0 ... Message receiving: The received message is stored in message buffer 15. Message receiving 0101 1111 010 0 ... Message buffer 13 0101 1111 000 0 ... RCR 1 1 1 ... Message buffer 14 0101 1111 001 0 ... ROVRR 0 0 0 ... Message buffer 15 0101 1111 010 0 ... Message receiving: The received message is stored in message buffer 13. Message receiving 0101 1111 011 0 ... Message buffer 13 0101 1111 011 0 ... RCR 1 1 1 ... Message buffer 14 0101 1111 001 0 ... ROVRR 0 0 1 ... Message buffer 15 0101 1111 010 0 ... Note: Four messages are received with the same acceptance filter set in message buffers 13, 14 and 15. 501 CHAPTER 21 CAN CONTROLLER 21.12 Setting the CAN Direct Mode Register To operate CAN normally, this register must be set correctly. ■ CAN Direct Mode Register (CDMR) (Only MB90V340) Figure 21.12-1 Configuration of the CAN Direct Mode Register (CDMR) (Only MB90V340) Address: 7 6 5 4 3 2 1 CAN0: 00796EH - - - - - - - - - - - - - - R/W 0 DIRECT CDMR Initial value XXXXXXX0 B R/W : Readable and writable X : Undefined value : Undefined Table 21.12-1 Function of CAN Direct Mode Register (CDMR) Bit Name bit 7 to 1 Undefined bits bit 0 DIRECT Function If the clock modulation is set (initial state), the bit should be set "0". If the clock modulation is not set, the bit should be set "1". Note: MB90360 does not have the clock modulation function. So, at using CAN controller, the DIRECT bit of the register must be set "1". 502 21.13 Precautions when Using CAN Controller Use of the CAN Controller requires the following cautions. ■ Caution for Disabling Message Buffers by BVAL Bits The use of BVAL bits may affect malfunction of CAN Controller when messages buffers are set disabled while CAN Controller is participating in CAN communication. This section shows the work around of this malfunction. ● Condition When following 2 conditions occur at the same time, the CAN Controller will not perform to transmit messages normally. • CAN Controller is participating in the CAN communication. (i.e. The read value of the CSR: HALT bit is 0 and CAN Controller is ready to transmit messages) • Message buffers are read when BVAL bits disable the message buffers. ● Work around Operation for suppressing transmission request Do not use BVAL bit for suppressing transmission request, use TCAN bit instead of it. Operation for composing transmission message For composing a transmission message, it is necessary to disable the message buffer by BVAL bit to change contents of ID and IDE registers. In this case, BVAL bit should reset (BVAL=0) after checking if TREQ bit is 0 or after completion of the previous message transmission (TC=1). In case a buffer needs to be disabled, ensure that no transmission request is pending (if it was requested before). Therefore, do not reset BVALx-Bit before testing, if a transmission is ongoing; a) Cancel the transmission request (TCANx=1;), if necessary b) and wait for the transmission completion (while (TREQx==1);) by polling or interrupt. Only after that the transmission buffer can be disabled (BVALx=0;). Note: For case a), if transmission of that buffer has already started, canceling the request is ignored and disabling the buffer is delayed until the end of the transmission. 503 CHAPTER 21 CAN CONTROLLER ■ Setting of CAN Direct Mode MB90360 does not provide the clock modulation function. For this reason, ensure that the DIRECT bit of the CAN direct mode register (CDMR) is set to 1 when CAN is used. Note that the CAN controller will not normally operate without correct setting of the DIRECT bit. 504 CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION This chapter explains the address match detection function and its operation. 22.1 Overview of Address Match Detection Function 22.2 Block Diagram of Address Match Detection Function 22.3 Configuration of Address Match Detection Function 22.4 Explanation of Operation of Address Match Detection Function 22.5 Program Example of Address Match Detection Function 505 CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION 22.1 Overview of Address Match Detection Function If the address of the instruction to be processed next to the instruction currently processed by the program matches the address set in the detect address setting registers, the address match detection function forcibly replaces the next instruction to be processed by the program with the INT9 instruction to branch to the interrupt processing program. Since the address match detection function can use the INT9 interrupt for instruction processing, the program can be corrected by patch processing. ■ Overview of Address Match Detection Function • The address of the instruction to be processed next to the instruction currently processed by the program is always held in the address latch through the internal data bus. The address match detection function always compares the value of the address held in the address latch with that of the address set in the detect address setting registers. When these compared values match, the next instruction to be processed by the CPU is forcibly replaced by the INT9 instruction, and the interrupt processing program is executed. • There are six detect address setting registers (PADR0 to PADR5), each of which has an interrupt enable bit. The generation of an interrupt due to a match between the address held in the address latch and the address set in the detect address setting registers can be enabled or disabled for each register. 506 CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION 22.2 Block Diagram of Address Match Detection Function The address match detection module consists of the following blocks: • Address latch • Address detection control register (PACSR0/PACSR1) • Detect address setting registers (PADR0 to PADR5) ■ Block Diagram of Address Match Detection Function Figure 22.2-1 shows the block diagram of the address match detection function. Figure 22.2-1 Block Diagram of the Address Match Detection Function Address latch Comparator INT9 instruction (INT9 instruction generation) Detection address setting register 0 PADR0 (24 bits) Detection address setting register 1 Internal data bus PADR1 (24 bits) Detection address setting register 5 PADR5 (24 bits) PACSR0 Reserved Reserved AD2E Reserved AD1E Reserved AD0E Reserved AD3E Reserved Address detection control register 0 (PACSR0) PACSR1 Reserved Reserved AD5E Reserved AD4E Reserved Address detection control register 1 (PACSR1) Reserved: Always setting to 0. ● Address latch The address latch stores the value of the address output to the internal data bus. ● Address detection control register (PACSR0/PACSR1) The address detection control register enables or disables output of an interrupt at an address match. ● Detect address setting registers (PADR0 to PADR5) The detect address setting registers set the address that is compared with the value of the address latch. 507 CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION 22.3 Configuration of Address Match Detection Function This section lists and details the registers used by the address match detection function. ■ List of Registers and Reset Values of Address Match Detection Function Figure 22.3-1 List of Registers and Reset Values of Address Match Detection Function bit 7 0 0 0 0 bit 15 14 13 12 0 0 0 0 bit 7 6 5 bit 15 14 bit 7 bit 2 1 0 0 0 0 0 11 10 9 8 0 0 0 0 4 3 2 1 0 13 12 11 10 9 8 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 bit 7 6 5 4 3 2 1 0 bit 15 14 13 12 11 10 9 8 bit 7 6 5 4 3 2 1 0 bit 15 14 13 12 11 10 9 8 bit 7 6 5 4 3 2 1 0 bit 7 6 5 4 3 2 1 0 bit 15 14 13 12 11 10 9 8 bit 7 6 5 4 3 2 1 0 bit 15 14 13 12 11 10 9 8 bit 7 6 5 4 3 2 1 0 bit 15 14 13 12 11 10 9 8 bit 7 6 5 4 3 2 1 0 bit 15 14 13 12 11 10 9 8 bit 7 6 5 4 3 2 1 0 Address detection control register 0(PACSR0) Address detection control register 1(PACSR1) 6 5 4 3 Detection address setting register 0(PADR0): Low Detection address setting register 0(PADR0): Middle Detection address setting register 0(PADR0): High Detection address setting register 1(PADR1): Low Detection address setting register 1(PADR1): Middle Detection address setting register 1(PADR1): High Detection address setting register 2(PADR2): Low Detection address setting register 2(PADR2): Middle Detection address setting register 2(PADR2): High Detection address setting register 3(PADR3): Low Detection address setting register 3(PADR3): Middle Detection address setting register 3(PADR3): High Detection address setting register 4(PADR4): Low Detection address setting register 4(PADR4): Middle Detection address setting register 4(PADR4): High Detection address setting register 5(PADR5): Low Detection address setting register 5(PADR5): Middle Detection address setting register 5(PADR5): High ×: Undefined 508 CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION 22.3.1 Address Detection Control Register (PACSR0/PACSR1) The address detection control register enables or disables output of an interrupt at an address match. When an address match is detected when output of an interrupt at an address match is enabled, the INT9 interrupt is generated. ■ Address Detection Control Register 0 (PACSR0) Figure 22.3-2 Address Detection Control Register 0 (PACSR0) Address 00009EH 7 6 ReReserved served 5 4 AD2E Reserved 3 AD1E 2 1 0 ReReserved AD0E served R/W R/W R/W R/W R/W R/W R/W R/W Reset value 0 0 0 0 0 0 0 0B bit 0 Reserved bit Reserved 0 Always set to "0" bit 1 AD0E Address match detection enable bit 0 0 Disables address match detection in PADR0 1 Enables address match detection in PADR0 bit 2 Reserved bit Reserved 0 Always set to "0" bit 3 AD1E Address match detection enable bit 1 0 Disables address match detection in PADR1 1 Enables address match detection in PADR1 bit 4 Reserved bit Reserved 0 Always set to "0" bit 5 AD2E Address match detection enable bit 2 0 Disables address match detection in PADR2 1 Enables address match detection in PADR2 bit 6 Reserved bit Reserved 0 Always set to "0" bit 7 Reserved bit Reserved R/W : Read/Write 0 Always set to "0" : Reset value 509 CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION Table 22.3-1 Functions of Address Detection Control Register (PACSR0) Bit Name 510 Function bit7, bit6 Reserved: reserved bits Always set to 0. bit5 AD2E: Address match detection enable bit 2 The address match detection operation with the detect address setting register 2 (PADR2) is enabled or disabled. When set to 0: Disables the address match detection operation. When set to 1: Enables the address match detection operation. • When the value of detect address setting registers 2 (PADR2) matches with the value of address latch at enabling the address match detection operation (AD2E = 1), the INT9 instruction is immediately executed. bit4 Reserved: reserved bit Always set to 0. bit3 AD1E: Address match detection enable bit 1 The address match detection operation with the detect address setting register 1 (PADR1) is enabled or disabled. When set to 0: Disables the address match detection operation. When set to 1: Enables the address match detection operation. • When the value of detect address setting registers 1 (PADR1) matches with the value of address latch at enabling the address match detection operation (AD1E = 1), the INT9 instruction is immediately executed. bit2 Reserved: reserved bit Always set to 0. bit1 AD0E: Address match detection enable bit 0 The address match detection operation with the detect address setting register 0 (PADR0) is enabled or disabled. When set to 0: Disables the address match detection operation. When set to 1: Enables the address match detection operation. • When the value of detect address setting registers 0 (PADR0) matches with the value of address latch at enabling the address match detection operation (AD0E = 1), the INT9 instruction is immediately executed. bit0 Reserved: reserved bit Always set to 0. CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION ■ Address Detection Control Register 1 (PACSR1) Figure 22.3-3 Address Detection Control Register 1 (PACSR1) Address 15 14 Re- Re0 0 0 0 3 B H served served 13 12 11 10 9 8 ReReReAD5E served AD4E served AD3E served R/W R/W R/W R/W R/W R/W R/W R/W Reset value 00000000B bit 8 Reserved bit Reserved 0 Always set to "0". bit 9 AD3E Address match detection enable bit 3 0 Disables address match detection in PADR3. 1 Enables address match detection in PADR3. bit 10 Reserved bit Reserved 0 Always set to "0". bit 11 AD4E Address match detection enable bit 4 0 Disables address match detection in PADR4. 1 Enables address match detection in PADR4. bit 12 Reserved bit Reserved 0 Always set to "0". bit 13 AD5E Address match detection enable bit 5 0 Disables address match detection in PADR5. 1 Enables address match detection in PADR5. bit 14 Reserved bit Reserved 0 Always set to "0". bit 15 Reserved bit Reserved R/W Read/Write 0 Always set to "0". : Reset value 511 CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION Table 22.3-2 Functions of Address Detection Control Register (PACSR1) Bit Name 512 Function bit15, bit14 Reserved: reserved bit Always set to 0. bit13 AD5E: Address match detection enable bit 5 The address match detection operation with the detect address setting register 5 (PADR5) is enabled or disabled. When set to 0: Disables the address match detection operation. When set to 1: Enables the address match detection operation. • When the value of detect address setting registers 5 (PADR5) matches with the value of address latch at enabling the address match detection operation (AD5E = 1), the INT9 instruction is immediately executed. bit12 Reserved: reserved bit Always set to 0. bit11 AD4E: Address match detection enable bit 4 The address match detection operation with the detect address setting register 4 (PADR4) is enabled or disabled. When set to 0: Disables the address match detection operation. When set to 1: Enables the address match detection operation. • When the value of detect address setting registers 4 (PADR4) matches with the value of address latch at enabling the address match detection operation (AD4E = 1), the INT9 instruction is immediately executed. bit10 Reserved: reserved bit Always set to 0. bit9 AD3E: Address match detection enable bit 3 The address match detection operation with the detect address setting register 3 (PADR3) is enabled or disabled. When set to 0: Disables the address match detection operation. When set to 1: Enables the address match detection operation. • When the value of detect address setting registers 3 (PADR3) matches with the value of address latch at enabling the address match detection operation (AD3E = 1), the INT9 instruction is immediately executed. bit8 Reserved: reserved bit Always set to 0. CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION 22.3.2 Detect Address Setting Registers (PADR0 to PADR5) The value of an address to be detected is set in the detect address setting registers. When the address of the instruction processed by the program matches the address set in the detect address setting registers, the next instruction is forcibly replaced by the INT9 instruction, and the interrupt processing program is executed. ■ Detect Address Setting Registers (PADR0 to PADR5) Figure 22.3-4 Detect Address Setting Registers (PADR0 to PADR5) Address XXXXXXXXB PADR5: Middle 0079F7H PADR2: Middle 0079E7H R/W R/W R/W R/W R/W R/W R/W R/W bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 D15 D14 D13 D12 D11 D10 D9 D8 XXXXXXXXB PADR5: Low PADR2: Low R/W R/W R/W R/W R/W R/W R/W R/W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 D7 D6 D5 D4 D3 D2 D1 D0 XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 Reset value D23 D22 XXXXXXXXB PADR4: High PADR1: High 0079F8H 0079E8H 0079F6H 0079E6H 0079F5H 0079E5H PADR4: Middle 0079F4H PADR1: Middle 0079E4H PADR4: Low PADR1: Low PADR3: High PADR0: High 0079F3H 0079E3H 0079F2H 0079E2H PADR3: Middle 0079F1H PADR0: Middle 0079E1H PADR3: Low PADR0: Low 0079F0H 0079E0H bit7 bit6 D23 D22 bit5 D21 D21 bit4 bit3 bit2 D20 D19 D18 D20 D19 D18 bit1 D17 Reset value bit0 D16 PADR5: High PADR2: High D17 D16 R/W R/W R/W R/W R/W R/W R/W R/W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 D15 D14 D13 D12 D11 D10 D9 D8 Reset value Reset value Reset value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 D7 D6 D5 D4 D3 D2 D1 D0 XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reset value D23 D22 D21 D20 D19 D18 D17 Reset value D16 XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 D15 D14 D13 D12 D11 D10 D9 D8 Reset value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 D7 D6 D5 D4 D3 D2 D1 D0 XXXXXXXXB Reset value R/W R/W R/W R/W R/W R/W R/W R/W R/W : Read/Write X : Undefined 513 CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION ■ Functions of Detect Address Setting Registers • There are six detect address setting registers (PADR0 to PADR5) that consist of a high byte (bank), middle byte, and low byte, totaling 24 bits. Table 22.3-3 Address Setting of Detect Address Setting Registers Register Name Detect address setting register 0 (PADR0) Detect address setting register 1 (PADR1) Detect address setting register 2 (PADR2) Detect address setting register 3 (PADR3) Detect address setting register 4 (PADR4) Detect address setting register 5 (PADR5) Address Setting Interrupt Output Enable High PACSR0: AD0E PACSR0: AD1E PACSR0: AD2E PACSR1: AD3E PACSR1: AD4E PACSR1: AD5E Set the upper 8 bits of detect address 0 (bank). Middle Set the middle 8 bits of detect address 0. Low Set the lower 8 bits of detect address 0. High Set the upper 8 bits of detect address 1 (bank). Middle Set the middle 8 bits of detect address 1. Low Set the lower 8 bits of detect address 1. High Set the upper 8 bits of detect address 2 (bank). Middle Set the middle 8 bits of detect address 2. Low Set the lower 8 bits of detect address 2. High Set the upper 8 bits of detect address 3 (bank). Middle Set the middle 8 bits of detect address 3. Low Set the lower 8 bits of detect address 3. High Set the upper 8 bits of detect address 4 (bank). Middle Set the middle 8 bits of detect address 4. Low Set the lower 8 bits of detect address 4. High Set the upper 8 bits of detect address 5 (bank). Middle Set the middle 8 bits of detect address 5. Low Set the lower 8 bits of detect address 5. • In the detect address setting registers (PADR0 to PADR5), starting address (first byte) of instruction to be replaced by INT9 instruction should be set. 514 CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION Figure 22.3-5 Setting of Starting Address of Instruction Code to be Replaced by INT9 Instruction Instruction code Address FF001C : FF001F : FF0022 : A8 00 00 4A 00 00 4A 80 08 Set to detect address (High: FFH, Middle: 00H, Low: 1FH) Mnemonic MOVW MOVW MOVW RW0,#0000 A,#0000 A,#0880 Notes: • When an address of other than the first byte is set to the detect address setting registers (PADR0 to PADR5), the instruction code is not replaced by INT9 instruction and a program of an interrupt processing is not be performed. When the address is set to the second byte or subsequent, the address set by the instruction code is replaced by "01" (INT9 instruction code) and, which may cause malfunction. • The detect address setting registers (PADR0 to PADR5) should be set after disabling the address match detection (PACSR: ADnE=0) of corresponding address match control registers. If the detect address setting registers are changed without disabling the address match detection, the address match detection function will work immediately after an address match occurs during writing address, which may cause malfunction. • The address match detection function can be used only for addresses of the internal ROM area. If addresses of the external memory area are set, the address match detection function will not work and the INT9 instruction will not be executed. 515 CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION 22.4 Explanation of Operation of Address Match Detection Function If the addresses of the instructions executed in the program match those set in the detection address setting registers (PADR0 to PADR5), the address match detection function will replace the first instruction code executed by the CPU with the INT9 instruction (01H) to branch to the interrupt processing program. ■ Operation of Address Match Detection Function Figure 22.4-1 shows the operation of the address match detection function when the detect addresses are set and an address match is detected. Figure 22.4-1 Operation of Address Match Detection Function Program execution Address The instruction address to be executed by program matches detect address setting register 0 FF001C : FF001F : FF0022 : Instruction code Mnemonic A8 00 00 4A 00 00 4A 80 08 MOVW MOVW MOVW RW0,#0000 A,#0000 A,#0880 Replaced by INT9 instruction (01H) ■ Setting Detect Address 1) Disable the detection address setting register 0 (PADR0) where the detect address is set for address match detection (PACSR0: AD0E=0). 2) Set the detect address in the detection address setting register 0 (PADR0). Set "FFH" at the higher bits, "00H" at the middle bits, and "1FH" at the lower bits of the detection address setting register 0 (PADR0). 3) Enable the detect address setting register 0 (PADR0) where the detect address is set for address match detection (PACSR0: AD0E=1). ■ Program Execution 1) If the address of the instruction to be executed in the program matches the set detect address, the first instruction code at the matched address is replaced by the INT9 instruction code ("01H"). 2) INT9 instruction is executed. INT9 interrupt is generated and then interrupt processing program is executed. 516 CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION 22.4.1 Example of using Address Match Detection Function This section gives an example of patch processing for program correction using the address match detection function. ■ System Configuration and E2PROM Memory Map ● System configuration Figure 22.4-2 gives an example of the system configuration using the address match detection function. Figure 22.4-2 Example of System Configuration Using Address Match Detection Function Serial E2PROM interface MCU F2MC16LX E2PROM Storing patch program Pull up resistor SIN Storing patch program from the outside Connector (UART) 517 CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION ■ E2PROM Memory Map Figure 22.4-3 shows the allocation of the patch program and data at storing the patch program in E2PROM. Figure 22.4-3 Allocation of E2PROM Patch Program and Data E2PROM address 0 0 0 0 H Patch program byte count PADR0 0001H Detect address 0 (Low) 0002H Detect address 0 (Middle) 0003H Detect address 0 (High) For patch program 0 0 0 0 4 H Patch program byte count 0005H PADR1 Detect address 1 (Low) For patch program 1 0 0 0 6 H Detect address 1 (Middle) 0 0 0 7 H Detect address 1 (High) . . . . . . 0 0 1 4 H Patch program byte count 0015H PADR5 Detect address 5 (Low) For patch program 5 0 0 1 6 H Detect address 5 (Middle) 0017H Detect address 5 (High) 0020H Patch program 0 (main body) 0030H Patch program 1 (main body) . . . 0070H . . . Patch program 5 (main body) ● Patch program byte count The total byte count of the patch program (main body) is stored. If the byte count is "00H", it indicates that no patch program is provided. ● Detect address (24 bits) The address where the instruction code is replaced by the INT9 instruction code due to program error is stored. This address is set in the detection address setting registers (PADR0 to PADR5). ● Patch program (main body) The program executed by the INT9 interrupt processing when the program address matches the detect address is stored. Patch program 0 is allocated from any predetermined address. Patch program 1 is allocated from the address indicating <starting address of patch program 0 + total byte count of patch program 0>. It is similar for the correction program 2 to 5. 518 CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION ■ Setting and Operating State ● Initialization E2PROM data are all cleared to "00H". ● Occurrence of program error • By using the connector (UART), information about the patch program is transmitted to the MCU (F2MC16LX) from the outside according to the allocation of the E2PROM patch program and data. • The MCU (F2MC16LX) stores the information received from outside in the E2PROM. ● Reset sequence • After reset, the MCU (F2MC16LX) reads the byte count of the E2PROM patch program to check the presence or absence of the correction program. • If the byte count of the patch program is not "00H", the higher, middle and lower bits at detect addresses 0 to 5 are read and set in the detection address setting registers 0 to 5 (PADR0 to PADR5). The patch program (main body) is read according to the byte count of the patch program and written to RAM in the MCU (F2MC16LX). • The patch program (main body) is allocated to the address where the patch program is executed in the INT9 interrupt processing by the address match detection function. • Address match detection is enabled (PACSR: AD0E=1, AD1E=1 ... AD5E=1). ● INT9 Interrupt processing • Interrupt processing is performed by the INT9 instruction. The MB90360 series has no interrupt request flag by address match detection. Therefore, if the stack information in the program counter is discarded, the detect address cannot be checked. When checking the detect address, check the value of program counter stacked in the interrupt processing routine. • The patch program is executed, branching to the normal program. 519 CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION ■ Operation of Address Match Detection Function at Storing Patch Program in E2PROM Figure 22.4-4 shows the operation of the address match detection function at storing the patch program in E2PROM. Figure 22.4-4 Operation of Address Match Detection Function at Storing Patch Program in E2PROM 000000H (3) Patch program RAM Detection address setting register E2PROM (1) Detection address setting (reset sequence) Serial E2PROM interface • Patch program byte count • Address for address detection • Patch program ROM (2) (4) Program error FFFFFFH (1) Execution of detection address setting of reset sequence and normal program (2) Branch to patch program which expanded in RAM with INT9 interrupt processing by address match detection (3) Patch program execution by branching of INT9 processing (4) Execution of normal program which branches from patch program ■ Flow of Patch Processing for Patch Program Figure 22.4-5 shows the flow of patch processing for patch program using the address match detection function. 520 CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION Figure 22.4-5 Flow of Patch Processing for Patch Program 000000H I/O area 0000H E2PROM Patch program byte count : 80H 000100H Register/RAM area 0001H Detect address (Low): 00H 000400H Patch program 0002H Detect address (Middle): 80H 000480H RAM area 0003H Detect address (High): FFH MB90360 RAM Stack area 0010H Patch program 000900H Detection address setting register 0090H FFFFH FF0000H Program error FF8000H ROM FF8050H FFFFFFH Reset INT9 Read the 00H of Branch to patch program JMP 000400H E2PROM YES Execution of patch program 000400H to 000480H E2PROM : 0000H = 0 NO End of patch program JMP FF8050H Read detect address E2PROM: 0001H to 0003H Å´ MCU: Set to PADR0 Read patch program E2PROM: 0010H to 008FH Å´ MCU: 000400H to 000047FH Enable address match detection (PACSR: AD0E = 1) Execution of normal program NO Program address = PADR0 YES INT9 521 CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION 22.5 Program Example of Address Match Detection Function This section gives a program example for the address match detection function. ■ Program Example for Address Match Detection Function ● Processing specifications If the address of the instruction to be executed by the program matches the address set in the detection address setting register (PADR0), the INT9 instruction is executed. ● Coding example PACSR0 EQU PADRL EQU 00009EH 0079E0H PADRM EQU 0079E1H PADRH EQU 0079E2H ;Address detection ;Detection address (Low) ;Detection address (Middle) ;Detection address (High) control register 0 setting register 0 setting register 0 setting register 0 ; ;---------Main program------------------------------------CODE CSEG START: ;Stack pointer (SP), etc., ;already initialized MOV PADRL,#00H ;Set address detection register 0 (Low) MOV PADRM,#00H ;Set address detection register 0 (Middle) MOV PADRH,#00H ;Set address detection register 0 (High) ; MOV I:PACSR0,#00000010B ;Enable address match . processing by user . LOOP: . processing by user . BRA LOOP ;---------Interrupt program------------------------------------WARI: . processing by user 522 CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION . RETI ;Return from interrupt processing CODE ENDS ;---------Vector setting-----------------------------------------VECT CSEG ABS=0FFH ORG 00FFD8H DSL WARI ORG 00FFDCH ;Set reset vector DSL START DB 00H ;Set to single-chip mode VECT ENDS END START 523 CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION 524 CHAPTER 23 ROM MIRRORING MODULE This chapter describes the functions and operations of the ROM mirroring function select module. 23.1 Overview of ROM Mirroring Function Select Module 23.2 ROM Mirroring Function Select Register (ROMM) 525 CHAPTER 23 ROM MIRRORING MODULE 23.1 Overview of ROM Mirroring Function Select Module The ROM mirroring function select module provides a setting so that ROM data in the FF bank can be read by access to the 00 bank. ■ Block Diagram of ROM Mirroring Function Select Module Figure 23.1-1 Block Diagram of ROM Mirroring Function Select Module ROM mirror function select register (ROMM) ReReReReReReReserved served served served served served served MI Internal data bus Address Address area FF bank 00 bank Data ROM ■ Access to FF Bank by ROM Mirroring Function Figure 23.1-2 shows the location in memory when ROM mirroring function allows access to the 00 bank to read ROM data in the FF bank. Figure 23.1-2 Access to FF Bank by ROM Mirroring Function 008000H 00 bank ROM mirror area 00FFFF H FEFFFF H FF0000H F F 8 0 0 0 H FF bank Area for ROM mirror FFFFFF H 526 MB90F362/T(S),MB90362/T(S) MB90F367/T(S),MB90367/T(S) CHAPTER 23 ROM MIRRORING MODULE ■ Memory Space when ROM Mirroring Function Enabled/Disabled Figure 23.1-3 shows the availability of access to memory space when the ROM mirroring function is enabled or disabled. Figure 23.1-3 Memory Space when ROM Mirroring Function Enabled/Disabled FFFFFFH Address #1 010000H 008000H 007900H Single chip ROM area ROM area (image of FF bank) Extended I/O area Address #2 RAM 000100H 0000F0H 000000H Generalpurpose register : Internal : Access disabled I/O Product type MB90F362/T(S), MB90362/T(S), MB90F367/T(S), MB90367/T(S) MB90V340A-101/102/103/104 Address #1 FF0000H Address #2 000D00H F80000H 007900H ■ List of Registers and Reset Values of ROM Mirroring Function Select Module Figure 23.1-4 List of Registers and Reset Values of ROM Mirroring Function Select Module bit ROM mirror function select register (ROMM) 15 14 13 12 11 10 9 8 1 : Undefined 527 CHAPTER 23 ROM MIRRORING MODULE 23.2 ROM Mirroring Function Select Register (ROMM) The ROM mirroring function select register (ROMM) enables or disables the ROM mirroring function. When the ROM mirroring function is enabled, ROM data in the FF bank can be read by access to the 00 bank. ■ ROM Mirroring Function Select Register (ROMM) Figure 23.2-1 ROM Mirroring Function Select Register (ROMM) Address 15 14 13 12 11 10 9 8 Reset value MI 00006FH XXXXXXX1B W bit8 W X : Write only MI : Indeterminate 0 ROM mirroring function disabled : Undefined 1 ROM mirroring function enabled ROM mirroring function select bit : Reset value Table 23.2-1 Functions of ROM Mirroring Function Select Register (ROMM) Bit Name Function bit8 MI: ROM mirroring function select bit This bit enables or disables the ROM mirroring function. When set to 0: Disables ROM mirroring function When set to 1: Enables ROM mirroring function • When the ROM mirroring function is enabled (MI = 1), data at ROM addresses "FF8000H" to "FFFFFFH" can be read by accessing addresses "008000H" to "00FFFFH". bit9 to bit15 Undefined bits Read: Value is undefined. Write: No effect Note: While the ROM area at addresses "008000H" to "00FFFFH" is being used, access to the ROM mirroring function select register (ROMM) is prohibited. 528 CHAPTER 24 512K-BIT FLASH MEMORY This chapter explains the functions and operation of the 512K-bit flash memory. The following three methods are available for writing data to and erasing data from the flash memory: • Parallel programmer • Serial programmer • Executing programs to write/erase data This chapter explains “Executing programs to write/ erase data”. 24.1 Overview of 512K-bit Flash Memory 24.2 Block Diagram of the Entire Flash Memory and Sector Configuration of the Flash Memory 24.3 Write/Erase Modes 24.4 Flash Memory Control Status Register (FMCS) 24.5 Starting the Flash Memory Automatic Algorithm 24.6 Confirming the Automatic Algorithm Execution State 24.7 Detailed Explanation of Writing to and Erasing Flash Memory 24.8 Notes on Using 512K-bit Flash Memory 24.9 Flash Security Feature 529 CHAPTER 24 512K-BIT FLASH MEMORY 24.1 Overview of 512K-bit Flash Memory The 512K-bit flash memory is mapped to the FFH bank in the CPU memory map. The functions of the flash memory interface circuit enable read-access and program-access from the CPU in the same way as mask ROM. Instructions from the CPU can be used via the flash memory interface circuit to write data to and erase data from the flash memory. Internal CPU control therefore enables rewriting of the flash memory while it is mounted. As a result, improvements in programs and data can be performed efficiently. ■ 512K-bit Flash Memory Features • Use of automatic program algorithm (Embedded AlgorithmTM*: Equivalent to MBM29LV200) • Detection of completion of writing/erasing using data polling or toggle bit functions • Detection of completion of writing/erasing using CPU interrupts • Minimum of 10,000 write/erase operations • Flash reading cycle time: Minimum of 2 machine cycles *: Embedded AlgorithmTM is a trademark of Advanced Micro Devices, Inc. Note: The manufacturer code and device code do not have the reading function. These codes cannot be accessed by the command. ■ Writing to/erasing Flash Memory The flash memory cannot be written to and erased at the same time. That is, when data is written to or erased data from the flash memory, the program in the flash memory must first be copied to RAM. The entire process is then executed in RAM so that data is simply written to the flash memory. This eliminates the need for the program to access the flash memory from the flash memory itself. ■ Flash Memory Control Status Register (FMCS) Figure 24.1-1 Flash Memory Control Status Register (FMCS) Flash memory control status register (FMCS) Address: 0000AEH Read/Write Initial value R/W: Read/Write R : Read only 530 7 6 5 4 3 2 1 0 INTE RDYINT WE RDY Reserved (R/W) (R/W) (R/W) (0) (0) (0) (R) (X) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) Reserved Reserved Reserved FMCS CHAPTER 24 512K-BIT FLASH MEMORY 24.2 Block Diagram of the Entire Flash Memory and Sector Configuration of the Flash Memory Figure 24.2-1 shows a block diagram of the entire flash memory with the flash memory interface circuit included. Figure 24.2-2 shows the sector configuration of the flash memory. ■ Block Diagram of the Entire Flash Memory Figure 24.2-1 Block Diagram of the Entire Flash Memory Flash memory interface circuit Port 2 Port 4 Port 5 F2MC-16LX bus 512K bits flash memory BYTE BYTE CE CE OE OE WE WE AQ0 to AQ18 AQ0 to AQ15 AQ-1 DQ0 to DQ15 DQ0 to DQ15 INT RY/BY RY/BY RESET Write enable interrupt signal (to CPU) External reset signal RY/BY Write enable signal ■ Sector Configuration of the 512K-bit Flash Memory Figure 24.2-2 shows the sector configuration of the 512K-bit flash memory. The addresses in the figure indicate the high-order and low-order addresses of each sector. 531 CHAPTER 24 512K-BIT FLASH MEMORY Figure 24.2-2 Sector Configuration of the 512K-bit Flash Memory MB90F362/T(S), MB90F367/T(S) Programmer address* CPU address 7FFFFH FFFFFFH 70000H FF0000H SA0 (64K bytes) *: The programmer address is equivalent to the CPU address when data is written to the flash memory using a parallel programmer. When a general programmer is used for writing/erasing, this address is used for writing/erasing. 532 CHAPTER 24 512K-BIT FLASH MEMORY 24.3 Write/Erase Modes The flash memory can be accessed in 2 different ways: Flash memory mode and alternative mode. Flash memory mode enables data to be directly written to or erased from the external pins. Alternative mode enables data to be written to or erased from the CPU via the internal bus. Use the mode external pins to select the mode. ■ Flash Memory Mode The CPU stops when the mode pins are set to "111B" while the reset signal is asserted. The flash memory interface circuit is connected directly to ports 2, 4 and 5, enabling direct control from the external pins. This mode makes the MCU seem like a standard flash memory to the external pins, and write/erase can be performed using a flash memory programmer. In flash memory mode, all operations supported by the flash memory automatic algorithm can be used. ■ Alternative Mode The flash memory is located in the FF bank in the CPU memory space, and like ordinary mask ROM, can be read-accessed and program-accessed from the CPU via the flash memory interface circuit. Since writing/erasing the flash memory is performed by instructions from the CPU via the flash memory interface circuit, this mode allows rewriting even when the MCU is soldered on the target board. ■ Flash Memory Control Signals Table 24.3-1 lists the flash memory control signals in flash memory mode. The flash memory control signals and the external pin of the MBM29LV200 have one-to-one relationship. In flash memory mode, the external data bus signal width is limited to 8 bits, enabling only 1 byte access. The DQ15 to DQ8 pins are not supported. The BYTE pin should always be set to 0. 533 CHAPTER 24 512K-BIT FLASH MEMORY Table 24.3-1 Flash Memory Control Signals (Developing: it is possible to change) MB90F362/T(S), MB90F367/T(S) Pin number MBM29LV200 Normal function Flash memory mode 42 P83 AQ16 A15 38 P87 CE CE 39 P86 OE OE 40 P43 WE WE 41 (45) P42(P44) AQ17 (AQ18) A16 37 P85 BYTE BYTE 11 P80 RY/BY RY/BY 12 to 19 P50 to P57 AQ8 to AQ15 A7 to A14 21 MD1 MD1 RESET(VID) 20 MD2 MD2 OE(VID) 3 to 10 P60 to P67 DQ0 to DQ7 DQ0 to DQ7 23 RST RESET RESET 29 to 36 P27 to P20 AQ0 to AQ7 A-1, A0 to A6 LQFP 534 CHAPTER 24 512K-BIT FLASH MEMORY 24.4 Flash Memory Control Status Register (FMCS) This section shows the function of the flash memory control status register (FMCS). ■ Flash Memory Control Status Register (FMCS) Figure 24.4-1 Flash Memory Control Status Register (FMCS) Address: 0000AEH 7 6 5 4 3 2 1 0 Reset value Re- Re- Re- ReINTE RDY INT WE RDY served served served served R/W R/W R/W R 000X0000B R/W R/W R/W R/W bit0 Reserved Reserved bit 0 Always set to "0" bit1 Reserved 0 Reserved bit Always set to "0" bit2 Reserved 0 Reserved bit Always set to "0" bit3 Reserved 0 Reserved bit Always set to "0" bit4 RDY Flash memory programming/erasing status bit 0 Programming/erasing (next data programming/erasing disabled) 1 Programming/erasing terminated (next data programming/erasing enabled) bit5 WE Flash memory programming/erasing enable bit 0 Programming/erasing flash memory area disabled 1 Programming/erasing flash memory area enabled bit6 RDYINT Flash memory operation flag bit Read Write 0 Programming/erasing This RDYIN bit cleared 1 Programming/erasing terminated No effect bit7 INTE R/W R W X : Read/Write : Read only : Write only : Undefined : Reset value Flash memory programming/erasing interrupt enable bit 0 Interrupt disabled at end of programming/erasing 1 Interrupt enabled at end of programming/erasing 535 CHAPTER 24 512K-BIT FLASH MEMORY Table 24.4-1 Functions of Control Status Register (FMCS) Bit Name Function bit7 INTE: Flash memory programming/erasing interrupt enable bit This bit enables or disables an interrupt as programming/erasing flash memory is terminated. When set to 1: If the flash memory operation flag bit is set to 1 (FMCS: RDYINT=1), an interrupt is requested. bit6 RDYINT: Flash memory operation flag bit This bit shows the operating state of flash memory. If programming/erasing flash memory is terminated, the RDYINT bit is set to 1 in timing of termination of the flash memory automatic algorithm. • If the RDYINT bit is set to 1 when an interrupt as programming/erasing flash memory is terminated is enabled (FMCS:INTE = 1), an interrupt is requested. • If the RDYINT bit is 0, programming/erasing flash memory is disabled. When set to 0: Cleared. When set to 1: No effect If the read-modify-write (RMW) instructions are used, 1 is always read. bit5 WE: Flash memory programming/erasing enable bit This bit enables or disables the programming/erasing of flash memory. The WE bit should be set before starting the command to program/erase flash memory. When set to 0: No program/erase signal is generated even if the command to program/ erase the FF bank is inputted. When set to 1: Programming/erasing flash memory is enabled after inputting program/ erase command to the FF bank. When not performing programming/erasing, the WE bit should be set to 0 so as not to accidentally program or erase flash memory. bit4 RDY: Flash memory programming/erasing status bit This bit shows the programming/erasing status of flash memory. If the RDY bit is 0, programming/erasing flash memory is disabled. The read/reset command can be accepted even if the RDY bit is 0. The RDY bit is set to 1 when programming/erasing is completed. bit3 to bit0 Reserved: Reserved bits Always set to 0. Note: 536 • The RDYINT and RDY bits cannot be changed at the same time. Create a program so that decisions are made using one or the other of these bits. (See Figure 24.4-2 .) • This register can be accessed only in byte-access mode. CHAPTER 24 512K-BIT FLASH MEMORY Figure 24.4-2 Transitions of the RDYINT and RDY Bits Automatic algorithm end timing RDYINT bit RDY bit 1 Machine cycle 537 CHAPTER 24 512K-BIT FLASH MEMORY 24.5 Starting the Flash Memory Automatic Algorithm Three types of commands are available for starting the flash memory automatic algorithm: Read/Reset, Write, and Chip Erase. ■ Command Sequence Table Table 24.5-1 lists the commands used for flash memory write/erase. All of the data written to the command register is in bytes, but use word access to write. The data of the high-order bytes at this time is ignored. Table 24.5-1 Command Sequence Table Command sequence Bus write access 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle Address Data Address Data Address Data Address Data Address Data Address Data Read/ reset* 1 FFXXXX XXF0 - - Read/ reset* 4 FFAAAA XXAA FF5554 Write program 4 Chip erase 6 - - - - - - - - XX55 FFAAAA XXF0 RA RD - - - - FFAAAA XXAA FF5554 XX55 FFAAAA XXA0 PA (even) PD (word) - - - FFAAAA XXAA FF5554 XX55 FFAAAA XX80 FFAAAA XXAA FF5554 XX55 FFAAAA XX10 Notes:• Addresses in the table are the values in the CPU memory map. All addresses and data are hexadecimal values, where "x" is any value. • RA: Read address • PA: Program address. Only even addresses can be specified. • RD: Read data • PD: Program data. Only word data can be specified. *: Two kinds of read/reset commands can reset flash memory to the read mode. 538 CHAPTER 24 512K-BIT FLASH MEMORY 24.6 Confirming the Automatic Algorithm Execution State Because the write/erase flow of the flash memory is controlled using the automatic algorithm, the flash memory has hardware for posting its internal operating state and completion of operation. This automatic algorithm enables confirmation of the operating state of the built-in flash memory using the following hardware sequences flag. ■ Hardware Sequence Flags The hardware sequence flags are configured from the three-bit output of DQ7, DQ6, and DQ5. The functions of these bits are those of the data polling flag (DQ7), toggle bit flag (DQ6), and timing limit exceeded flag (DQ5). The hardware sequence flags can therefore be used to confirm that writing or chip erase has been completed or that erase code write is valid. The hardware sequence flags can be accessed by read-accessing the addresses of the target sectors in the flash memory after setting of the command sequence (see Table 24.5-1 ). Table 24.6-1 lists the bit assignments of the hardware sequence flags. Table 24.6-1 Bit Assignments of Hardware Sequence Flags Bit No. Hardware sequence flag 7 6 5 4 3 2 1 0 DQ7 DQ6 DQ5 − − − − − 539 CHAPTER 24 512K-BIT FLASH MEMORY To determine whether automatic writing or chip erase is being executed, the hardware sequence flags can be checked or the status can be determined from the RDY bit of the flash memory control status register (FMCS) that indicates whether writing has been completed. After writing/erasing has terminated, the state returns to the read/reset state. When creating a program, use one of the flags to confirm that automatic writing/erasing has terminated. Then, perform the next processing operation, such as data read. The following sections describe each hardware sequence flag separately. Table 24.6-2 lists the functions of the hardware sequence flags. Table 24.6-2 Hardware Sequence Flag Function State State change for normal operation Abnormal operation 540 DQ7 DQ6 DQ5 Write → Write completed (write address specified) DQ7 → DATA:7 Toggle → DATA:6 0→ DATA:5 Chip/selector erase → Erase completed 0→1 Toggle → Stop 0→1 Write DQ7 Toggle 1 Chip erase 0 Toggle 1 CHAPTER 24 512K-BIT FLASH MEMORY 24.6.1 Data Polling Flag (DQ7) The data polling flag (DQ7) uses the data polling function to post that the automatic algorithm is being executed or has terminated ■ Data Polling Flag (DQ7) Table 24.6-3 and Table 24.6-4 list the state transitions of the data polling flag. Table 24.6-3 State Transition of Data Polling Flag (State change at normal operation) Operating State Programming → Completed Chip Erasing → Completed DQ7 DQ7 → DATA:7 0→1 Table 24.6-4 State Transition of Data Polling Flag (State change at abnormal operation) Operating State Programming Chip Erasing DQ7 DQ7 0 ● Write Read-access during execution of the automatic write algorithm causes the flash memory to output the opposite data of bit 7 last written, regardless of the value at the address specified by the address signal. Read-access at the end of the automatic write algorithm causes the flash memory to output bit 7 of the read value of the address specified by the address signal. ● Chip erase Read-access during execution of the chip erase algorithm causes the flash memory to output 0. Read-access at the end of the automatic chip algorithm causes the flash memory to output 1 in the same way. Note: When the automatic algorithm is being started, read-access to the specified address is ignored. Since termination of the data polling flag (DQ7) can be accepted for a data read and other bits output, data read after the automatic algorithm has terminated should be performed after read-access has confirmed that data polling has terminated. 541 CHAPTER 24 512K-BIT FLASH MEMORY 24.6.2 Toggle Bit Flag (DQ6) Like the data polling flag (DQ7), the toggle bit flag (DQ6) uses the toggle bit function to post that the automatic algorithm is being executed or has terminated. ■ Toggle Bit Flag (DQ6) Table 24.6-5 and Table 24.6-6 list the state transitions of the toggle bit flag. Table 24.6-5 State Transition of Toggle Bit Flag (State change at normal operation) Operating State Programming → Completed Chip Erasing → Completed DQ6 Toggle → DATA:6 Toggle → Stop Table 24.6-6 State Transition of Toggle Bit Flag (State change at abnormal operation) Operating State Programming Chip Erasing DQ6 Toggle Toggle ● Write/chip erase Continuous read-access during execution of the automatic write algorithm and chip erase algorithm causes the flash memory to toggle the 1 or 0 state for every read cycle, regardless of the value at the address specified by the address signal. Continuous read-access at the end of the automatic write algorithm and chip erase algorithm causes the flash memory to stop toggling bit 6 and output bit 6 (DATA: 6) of the read value of the address specified by the address signal. 542 CHAPTER 24 512K-BIT FLASH MEMORY 24.6.3 Timing Limit Exceeded Flag (DQ5) The timing limit exceeded flag (DQ5) is used to post that execution of the automatic algorithm has exceeded the time (internal pulse count) prescribed in the flash memory. ■ Timing Limit Exceeded Flag (DQ5) Table 24.6-7 and Table 24.6-8 list the state transitions of the timing limit exceeded flag. Table 24.6-7 State Transition of Timing Limit Exceeded Flag (State change at normal operation) Operating State Programming → Completed Chip Erasing → Completed DQ5 0 → DATA:5 0→1 Table 24.6-8 State Transition of Timing Limit Exceeded Flag (State change at abnormal operation) Operating State Programming Chip Erasing DQ5 1 1 ● Write/chip erase Read-access after write or chip erase automatic algorithm activation causes the flash memory to output 0 if the time is within the prescribed time (time required for write/erase) or to output 1 if the prescribed time has been exceeded. Because this is done regardless of whether the automatic algorithm is being executed or has terminated, it is possible to determine whether write/erase was successful or unsuccessful. That is, when this flag outputs 1, writing can be determined to have been unsuccessful if the automatic algorithm is still being executed by the data polling function or toggle bit function. For example, writing 1 to a flash memory address where 0 has been written will cause the fail state to occur. In this case, the flash memory will lock and execution of the automatic algorithm will not terminate. In rare cases normal termination may be seen as with the case where "1" can be written. As a result, valid data will not be outputted from the data polling flag (DQ7). In addition, the toggle bit flag (DQ6) will exceed the time limit without stopping the toggle operation and the timing limit exceeded flag (DQ5) will output 1. Note that this state indicates that the flash memory is not faulty, but has not been used correctly. When this state occurs, execute the Reset command. 543 CHAPTER 24 512K-BIT FLASH MEMORY 24.7 Detailed Explanation of Writing to and Erasing Flash Memory This section describes each operation procedure of flash memory Read/Reset, Write, Chip Erase when a command that starts the automatic algorithm is issued. ■ Detailed Explanation of Flash Memory Write/erase The flash memory executes the automatic algorithm by issuing a command sequence (see Table 24.5-1 ) for a write cycle to the bus to perform Read/Reset, Write, or Chip Erase operations. Each bus write cycle must be performed continuously. In addition, whether the automatic algorithm has terminated can be determined using the data polling or other function. At normal termination, the flash memory is returned to the read/ reset state. Each operation of the flash memory is described in the following order: 544 • Setting the read/reset state • Writing data • Erasing all data (erasing chips) CHAPTER 24 512K-BIT FLASH MEMORY 24.7.1 Setting The Read/Reset State This section describes the procedure for issuing the Read/Reset command to set the flash memory to the read/reset state. ■ Setting the Flash Memory to the Read/reset State The flash memory can be set to the read/reset state by sending the Read/Reset command in the command sequence table (see Table 24.5-1 ) continuously to the target sector in the flash memory. The Read/Reset command has two types of command sequences that execute the first and third bus operations. However, there are no essential differences between these command sequences. The read/reset state is the initial state of the flash memory. When the power is turned on and when a command terminates normally, the flash memory is set to the read/reset state. In the read/reset state, other commands wait for input. In the read/reset state, data is read by regular read-access. As with the mask ROM, program access from the CPU is enabled. The Read/Reset command is not required to read data by a regular read. The Read/Reset command is mainly used to initialize the automatic algorithm in such cases as when a command does not terminate normally. 545 CHAPTER 24 512K-BIT FLASH MEMORY 24.7.2 Writing Data This section describes the procedure for issuing the Write command to write data to the flash memory. ■ Writing Data to the Flash Memory The data write automatic algorithm of the flash memory can be started by sending the Write command in the command sequence table (see Table 24.5-1 ) continuously to the target sector in the flash memory. When data write to the target address is completed in the fourth cycle, the automatic algorithm and automatic write are started. ● Specifying addresses Only even addresses can be specified as the write addresses specified in a write data cycle. Odd addresses cannot be written correctly. That is, writing to even addresses must be done in units of word data. Writing can be done in any order of addresses. However, the Write command writes only data of one word for each execution. ● Notes on writing data Writing cannot return data 0 to data 1. When data 1 is written to data 0, the data polling algorithm (DQ7) or toggle operation (DQ6) does not terminate and the flash memory elements are determined to be faulty. If the time prescribed for writing is thus exceeded, the timing limit exceeded flag (DQ5) is determined to be an error. Otherwise, the data is viewed as if dummy data 1 had been written. However, when data is read in the read/reset state, the data remains 0. Data 0 can be set to data 1 only by erase operations. All commands are ignored during execution of the automatic write algorithm. If a hardware reset is started during writing, the data of the written addresses will be unpredictable. ■ Writing to the Flash Memory Figure 24.7-1 is an example of the procedure for writing to the flash memory. The hardware sequence flags (see "24.6 Confirming the Automatic Algorithm Execution State") can be used to determine the state of the automatic algorithm in the flash memory. Here, the data polling flag (DQ7) is used to confirm that writing has terminated. The data read to check the flag is read from the address written to last. The data polling flag (DQ7) changes at the same time that the timing limit exceeded flag (DQ5) changes. For example, even if the timing limit exceeded flag (DQ5) is 1, the data polling flag bit (DQ7) must be rechecked. Also for the toggle bit flag (DQ6), the toggle operation stops at the same time that the timing limit exceeded flag bit (DQ5) changes to 1. The toggle bit flag (DQ6) must therefore be rechecked. 546 CHAPTER 24 512K-BIT FLASH MEMORY Figure 24.7-1 Example of the Flash Memory Write Procedure Start writing FMCS: WE (bit 5) Flash programming enabled Program command sequence (1) FxAAAA ← XXAA (2) Fx5554 ← XX55 (3) FxAAAA ← XXA0 (4) Program address ← Program data Next address Internal address read Data polling flag (DQ7) DATA DATA 0 Timing limit (DQ5) 1 Internal address read DATA Data polling flag (DQ7) DATA Programming error Last address NO YES FMCS: WE (bit 5) Flash programming enabled Completed : Check by hardware sequence flag 547 CHAPTER 24 512K-BIT FLASH MEMORY 24.7.3 Erasing All Data (Erasing Chips) This section describes the procedure for issuing the Chip Erase command to erase all data in the flash memory. ■ Erasing all Data in the Flash Memory (Erasing chips) All data can be erased from the flash memory by sending the Chip Erase command in the command sequence table (see Table 24.5-1 ) continuously to the target sector in the flash memory. The Chip Erase command is executed in six bus operations. When writing of the sixth cycle is completed, the chip erase operation is started. For chip erase, the user need not write to the flash memory before erasing. During execution of the automatic erase algorithm, the flash memory writes 0 for verification before all of the cells are erased automatically. ■ Erasing Chip in the Flash Memory The hardware sequence flags (see "24.6 Confirming the Automatic Algorithm Execution State") can be used to determine the state of the automatic algorithm in the flash memory. Figure 24.7-2 is an example of the procedure for erasing chip in the flash memory. Here, the toggle bit flag (DQ6) is used to confirm that erasing has terminated. The data that is read to check the flag is read from the sector to be erased. The toggle bit flag (DQ6) stops the toggle operation at the same time that the timing limit exceeded flag (DQ5) is changed to 1. For example, even if the timing limit exceeded flag (DQ5) is 1, the toggle bit flag (DQ6) must be rechecked. The data polling flag (DQ7) also changes at the same time that the timing limit exceeded flag bit (DQ5) changes. As a result, the data polling flag (DQ7) must be rechecked. 548 CHAPTER 24 512K-BIT FLASH MEMORY Figure 24.7-2 Example of the Flash Memory Chip Procedure Start writing FMCS: WE (bit 5) Flash programming enabled Erase command sequence (1) FFAAAA ← XXAA (2) FF5554 ← XX55 (3) FFAAAA ← XX80 (4) FFAAAA ← XXAA (5) FF5554 ← XX55 (6) FFAAAA ← XX10 Read internal address 1 Read internal address 2 Toggle bit (DQ6) data1(DQ6)=data2(DQ6) YES NO 0 Timing limit (DQ5) 1 Read internal address 1 Read internal address 2 NO Toggle bit (DQ6) data1(DQ6)=data2(DQ6) YES Erase error FMCS: WE (bit 5) Disable flash memory erase Completed : Check by hardware sequence flag 549 CHAPTER 24 512K-BIT FLASH MEMORY 24.8 Notes on Using 512K-bit Flash Memory This section contains notes on using 512K-bit flash memory. ■ Notes on Using Flash Memory ● Input of a hardware reset (RST) To input a hardware reset when the automatic algorithm has not been started and reading is in progress, a minimum "L" level width of 500 ns must be maintained. In this case, a maximum of 500 ns is required until data can be read from the flash memory after a hardware reset has been activated. Similarly, to input a hardware reset when the automatic algorithm has been activated and writing or erasing is in progress, a minimum "L" level width of 500 ns must be maintained. In this case, 20 µs are required until data can be read after the operation for initializing the flash memory has terminated. When a hardware reset is performed during writing, the data being written is undefined. ● Canceling of a software reset and watchdog timer reset When the flash memory is being written to or erased with CPU access and if reset conditions occur while the automatic algorithm is active, the CPU may run out of control. This occurs because these reset conditions cause the automatic algorithm to continue without initializing the flash memory unit, possibly preventing the flash memory unit from entering the read state when the CPU starts the sequence after the reset has been deasserted. These reset conditions must be disabled during writing to or erasing of the flash memory. ● Program access to flash memory When the automatic algorithm is operating, read access to the flash memory is disabled. With the memory access mode of the CPU set to internal ROM mode, writing or erasing must be started after the program area is switched to another area such as RAM. ● Extended intelligent I/O service (EI2OS) Because write and erase interrupts issued to the CPU from the flash memory interface circuit cannot be accepted by the EI2OS, they should not be used. 550 CHAPTER 24 512K-BIT FLASH MEMORY 24.9 Flash Security Feature Flash security feature provides possibilities to protect the content of the flash memory. ■ Abstract By writing the protection code of "01H" to the security bit in the flash memory, access to the flash memory is restricted. Once the flash memory is protected, performing the chip erase operation only can unlock the function. Otherwise, read/write access to the flash memory from the external pins is not possible. This function is suitable for applications requiring security of self-containing and data stored in the flash memory. Address of the security bit depends on the size of built-in flash memory. Table 24.9-1 shows the address of security bit. Table 24.9-1 Address of Flash Security Bit Flash memory size MB90F362/T(S), MB90F367/T(S) Built-in 512K-bit flash memory Address of security bit FF0001H ■ How to Enable the Flash Security Feature After writing the protection code "01H" to the security bit, the following external reset or power-on enables the Flash Security Feature. ■ How to Disable the Flash Security Feature Performing the chip erase operation. ■ Behavior Under the Flash Security Feature Read operation: invalid data read Write operation: ignored ■ Others (1) About configuration of the general-purpose parallel programmer, please follow to the specification of parallel programmer. (2) Writing the protection code at the last of flash memory programming is recommended, in order to prevent the device from enabling the Flash Security Feature accidentally. Notes: • The flash security bit is allocated in the flash memory area. When the protection code "01H" is written to the security bit, it is locked by the security. So, when not using the security function, do not write "01H" to this address. See Table 24.9-1 for the address of the security bit. • By specifying the sector of the flash memory, it cannot be locked the security per sector. It is the security function for all areas in the flash memory. • The FLASH memory trouble in the state to put security cannot be analyzed at all. 551 CHAPTER 24 512K-BIT FLASH MEMORY 552 CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION This chapter shows an example of a serial programming connection using the AF220/AF210/AF120/AF110 Flash Micro-computer Programmer by Yokogawa Digital Computer Corporation when the AF220/AF210/AF120/ AF110 flash serial microcontroller programer from Yokogawa Digital Computer Corporation is used. 25.1 Basic Configuration of Serial Programming Connection with MB90F362/T(S), MB90F367/T(S) 25.2 Example of Serial Programming Connection (User Power Supply Used) 25.3 Example of Serial Programming Connection (Power Supplied from Programmer) 25.4 Example of Minimum Connection to Flash Microcontroller Programmer (User Power Supply Used) 25.5 Example of Minimum Connection to Flash Microcontroller Programmer (Power Supplied from Programmer) 553 CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION 25.1 Basic Configuration of Serial Programming Connection with MB90F362/T(S), MB90F367/T(S) The MB90F362/T(S), MB90F367/T(S) supports on-board writing (Fujitsu standard) of the flash ROM. This section provides the related specifications. ■ Basic Configuration of Serial Programming Connection with MB90F362/T(S), MB90F367/T(S) Fujitsu standard serial on-board writing uses the Yokogawa Digital Computer Corporation AF220/AF210/ AF120/AF110 flash microcontroller programmer. Figure 25.1-1 shows the basic configuration for the example serial programming connection of MB90F362/ T(S), MB90F367/T(S). Figure 25.1-1 Basic Configuration MB90F362/T(S), MB90F367/T(S) Serial Programming Connection General-purpose common cable (AZ210) Host interface cable RS232C AF220/AF210/ AF120/AF110 flash microcontroller programmer + memory card CLK synchronous serial MB90F362/T(S), MB90F367/T(S) User system Stand-alone operation enabled Note: For information on the functions of and operational procedures related to the flash microcontroller programmer (AF220/AF210/AF120/AF110), the general-purpose common cable (AZ210) for connection, and the connector, contact Yokogawa Digital Computer Corporation. 554 CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION Table 25.1-1 Pin Used for Fujitsu Standard Serial on-board Programming Pin Function Additional information MD2, MD1, MD0 Mode pins Controls programming mode from the flash microcontroller programmer. X0, X1 Oscillation pins In programming mode, the CPU internal operation clock signal is one multiple of the PLL clock signal frequency. Therefore, because the oscillation clock frequency becomes the internal operation clock signal, the oscillator used for serial reprogramming is 4 MHz to 16 MHz. P83, P84 Programming activation pins Input "L" level to P83 and "H" level to P84. RST Reset pin SIN1 Serial data input pin SOT1 Serial data output pin SCK1 Serial clock signal input pin C C pin This pin is used to stabilize the power supply. Connect to a external ceramic capacitor of approximately 0.1 µF or more. VCC Power voltage supply pin If the programming voltage (5 V ± 10%) is supplied from the user system, the flash microcontroller programmer need not be connected. Connect so that the power supply of the user side is not short-circuited. VSS GND pin Common to the ground of the flash microcontroller programmer. - Use UART1 as CLK synchronous mode. Even if the P83, P84, SIN1, SOT1, and SCK1 pins are used for the user system, the control circuit shown in Figure 25.1-2 is required. (The /TICS signal of the flash microcontroller programmer can be used to disconnect the user circuit during serial programming.) Figure 25.1-2 Control Circuit AF220/AF210/AF120/AF110 write control pin MB90F362/T(S), MB90F367/T(S) 10kΩ Write control pin AF220/AF210/AF120/AF110 /TICS pin User "25.2 Example of Serial Programming Connection (User Power Supply Used)" to "25.5 Example of Minimum Connection to Flash Microcontroller Programmer (Power Supplied from Programmer)" present examples the following 4 types of serial programming connection. See each Section as required. • Example of serial programming connection (user power supply used) • Example of serial programming connection (power supplied from the programmer) • Example of minimum connection to the flash microcontroller programmer (user power supply used) • Example of minimum connection to the flash microcontroller programmer (power supplied from the 555 CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION programmer) Table 25.1-2 System Configuration of Flash Microcontroller Programmers (Manufactured by Yokogawa Digital Computer Corporation) Model Main unit Function AF220/AC4P Ethernet interface built-in model and 100 V to 220 V AC power adapter AF210/AC4P Standard model and 100 V to 220 V AC power adapter AF120/AC4P Single-key Ethernet interface built-in model and 100 V to 220 V AC power adapter AF110/AC4P Single-key model and 100 V to 220 V AC power adapter AZ221 RS232C cable for programmer PC/AT AZ210 Standard target probe (a) cable length: 1 m FF201 Fujitsu F2MC-16LX flash microcontroller control module AZ290 Remote controller /P2 2MB PC Card (optional) for flash memory sizes up to 128 KB /P4 4MB PC Card (optional) for flash memory sizes up to 512 KB Inquiries: Yokogawa Digital Computer Corporation Telephone number: (81)-42-333-6224 Note: Although the AF200 flash microcontroller programmer is no longer manufactured, the programmer still can be used in combination with the FF201 control module. Examples of serial programming connection can correspond to the connection example as shown in "■Oscillating Clock Frequency and Serial Clock Input Frequency". ■ Oscillating Clock Frequency and Serial Clock Input Frequency The equation listed below can be used to calculate the serial clock frequencies that can be used for the MB90F362/T(S), MB90F367/T(S). Serial clock frequency that can be input = 0.125 * example of oscillation clock frequency Set an appropriate serial clock input frequency in the flash microcontroller programmer according to the oscillating clock frequency in use. Table 25.1-3 Examples of Serial Clock Frequencies that can be Input 556 Oscillating clock frequency Maximum serial clock frequency that can be input for microcontrollers Maximum serial clock frequency that can be used for the AF220, AF210, AF120 and AF110 Maximum serial clock frequency that can be used for the AF200 4 MHz 500 kHz 500 kHz 500 kHz 8 MHz 1 MHz 850 kHz 500 kHz 16 MHz 2 MHz 1.25 MHz 500 kHz CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION 25.2 Example of Serial Programming Connection (User Power Supply Used) Figure 25.2-1 shows an example of a serial programming connection when the user power supply is used. The value 1 and 0 are input to mode pins MD2 and MD0 from TAUX3 and TMODE of the AF220/AF210/AF120/AF110 programmer. Serial reprogramming mode: MD2, MD1, MD0 = 110. ■ Example of Serial Programming Connection (User power supply used) Figure 25.2-1 Example of Serial Programming Connection for MB90F362/T(S), MB90F367/T(S) Single-chip Modes (User power supply Used) AF220/AF210/AF120/AF110 flash microcontroller programmer User system TAUX3 MB90F362 /T(S), MB90F367/T(S) Connector DX10-28S DX20-28S (19) MD2 10kΩ 10kΩ MD1 10kΩ TMODE (12) 4MHz to 16MHz TAUX (23) MD0 X0 X1 P83 10kΩ /TICS (10) User 10kΩ /TRES 10kΩ (5) RST 10kΩ P84 User 0.1µF (13) (27) (6) TTXD TRXD TCK TVcc (2) GND (7,8, 14,15, 21,22, 1,28) C SIN1 SOT1 SCK1 Vcc User power supply Vss - 3,4,9,11,16,17,18,20,24,25 and 26 pins are OPEN. - DX10-28S : Right-angle type - DX20-28S : Straight type 14 pin 1 pin 28 pin 15 pin DX10-28S DX20-28S Connector (Hirose Electronics Ltd.) pin arrangement 557 CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION • Even if the SIN1, SOT1, and SCK1 pins are used for the user system, the control circuit shown in the figure below is required in the same way that it is for P83. (The /TICS signal of the flash microcontroller programmer can be used to disconnect the user circuit during serial programming.) Figure 25.2-2 Control Circuit AF220/AF210/AF120/AF110 write control pin MB90F362/T(S), MB90F367/T(S) 10kΩ write control pin AF220/AF210/AF120/AF110 /TICS pin User • 558 Connect the AF220/AF210/AF120/AF110 while the user power is off. CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION 25.3 Example of Serial Programming Connection (Power Supplied from Programmer) Figure 25.3-1 shows an example of a serial programming connection when power is supplied from the programmer. The value 1 and 0 are input to mode pins MD2 and MD0 from TAUX3 and TMODE of the AF220/AF210/AF120/AF110 programmer. Serial reprogramming mode: MD2, MD1, MD0 = 110. ■ Example of Serial Programming Connection (Power supplied from programmer) Figure 25.3-1 Example of Serial Programming Connection for MB90F362/T(S), MB90F367/T(S) Single-chip Modes (Power supplied from programmer) AF220/AF210/AF120/AF110 flash microcontroller programmer User system TAUX3 MB90F362/T(S), MB90F367/T(S) Connector DX10-28S DX20-28S (19) MD2 10kΩ 10kΩ MD1 10kΩ TMODE (12) 4MHz to 16MHz TAUX (23) MD0 X0 X1 P83 10kΩ /TICS (10) User 10kΩ 10kΩ /TRES (5) RST 10kΩ P84 User 0.1µF TTXD TRXD TCK TVcc Vcc TVPP1 (13) (27) (6) (2) (3) (16) GND (7,8, 14,15, 21,22, 1,28) SIN1 SOT1 SCK1 Vcc Vss - 4,9,11,17,18,20,24,25 and 26 pins are OPEN. - DX10-28S : Right-angle type - DX20-28S : Straight type C 14 pin 1 pin 28 pin 15 pin DX10-28S DX20-28S Connector (Hirose Electronics Ltd.) pin arrangement 559 CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION • Even if the SIN1, SOT1, and SCK1 pins are used for the user system, the control circuit shown in the figure below is required in the same way that it is for P83. (The /TICS signal of the flash microcontroller programmer can be used to disconnect the user circuit during serial programming.) Figure 25.3-2 Control Circuit AF220/AF210/AF120/AF110 write control pin MB90F362/T(S), MB90F367/T(S) 10kΩ AF220/AF210/AF120/AF110 /TICS pin Write control pin User 560 • Connect the AF220/AF210/AF120/AF110 while the user power is off. • When the programming power is supplied from the AF220/AF210/AF120/AF110, be careful not to short-circuit the user power supply. CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION 25.4 Example of Minimum Connection to Flash Microcontroller Programmer (User Power Supply Used) Figure 25.4-1 shows an example of the minimum connection to the flash microcontroller programmer when the user power supply is used. Serial reprogramming mode: MD2, MD1, MD0 = 110. ■ Example of Minimum Connection to Flash Microcontroller Programmer (User power supply used) For a flash memory write, the MD2, MD1, MD0, P83, and P84 pins and flash microcontroller programmer need not be connected if the pins are set as Figure 25.4-1 . Figure 25.4-1 Example of Minimum Connection to MB90F362/T(S), MB90F367/T(S) Flash Microcontroller Programmer (User power supply Used) AF220/AF210/AF120/AF110 flash microcontroller programmer MB90F362/T(S), MB90F367/T(S) User system 1 for serial rewriting 10kΩ MD2 10kΩ 10kΩ 10kΩ 10kΩ 0 for serial rewriting 10kΩ 1 for serial rewriting MD1 MD0 4MHz to 16MHz 10kΩ X0 X1 P83 10kΩ 0 for serial rewriting User circuit P84 1 for serial rewriting User circuit Connector DX10-28S DX20-28S /TRES TTXD TRXD TCK TVcc GND (5) C 0.1µF 10kΩ RST (13) SIN1 SOT1 SCK1 Vcc (27) (6) (2) (7,8, 14,15, 21,22, 1,28) User power supply Vss 14 pin - 3,4,9,10,11,12,16,17,18,19,20, 23,24,25 and 26 pins are OPEN. - DX10-28S : Right-angle type - DX20-28S : Straight type 1 pin DX10-28S DX20-28S 28 pin 15 pin Connector (Hirose Electronics Ltd.) pin arrangement 561 CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION • Even if the SIN1, SOT1, and SCK1 pins are used for the user system, the control circuit shown in the figure below is required. (The /TICS signal of the flash microcontroller programmer can be used to disconnect the user circuit during serial programming.) Figure 25.4-2 Control Circuit AF220/AF210/AF120/AF110 write control pin MB90F362/T(S), MB90F367/T(S) 10kΩ AF220/AF210/AF120/AF110 /TICS pin Write control pin User • 562 Connect the AF220/AF210/AF120/AF110 while the user power is off. CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION 25.5 Example of Minimum Connection to Flash Microcontroller Programmer (Power Supplied from Programmer) Figure 25.5-1 shows an example of the minimum connection to the MB90F362/T(S), MB90F367/T(S) flash microcontroller programmer when power is supplied from the Programmer. Serial reprogramming mode: MD2, MD1, MD0 = 110B. ■ Example of Minimum Connection to Flash Microcomputer Programmer (Power supplied from programmer) For a flash memory write, the MD2, MD1, MD0, P83, and P84 pins and flash microcontroller programmer need not be connected if the pins are set as Figure 25.5-1 . Figure 25.5-1 Example of Minimum Connection to the MB90F362/T(S), MB90F367/T(S) Flash Microcontroller Programmer (power supplied from programmer) AF220/AF210/AF120/AF110 flash microcontroller programmer MB90F362/T(S), MB90F367/T(S) User system 1 for serial rewrite 10kΩ MD2 1 for serial rewrite 10kΩ 10kΩ 10kΩ 10kΩ MD1 MD0 0 for serial rewrite 10kΩ 4MHz to 16MHz X0 X1 P83 10kΩ 10kΩ 0 for serial rewrite User circuit P84 1 for serial rewrite User circuit C Connector DX10-28S DX20-28S /TRES TTXD TRXD TCK TVcc Vcc TVPP1 GND 0.1µF 10kΩ (5) (13) RST SIN1 SOT1 SCK1 (27) (6) (2) (3) (16) Vcc (7,8, 14,15, 21,22, 1,28) Vss - 4,9,10,11,12,17,18,19,20,23,24,25 and 26 pins are open. - DX10-28S : Right-angle type - DX20-28S : Straight type 14 pin 1 pin DX10-28S DX20-28S 28 pin 15 pin Connector (Hirose Electronics Ltd.) pin arrangement 563 CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION • Even if the SIN1, SOT1, and SCK1 pins are used for the user system, the control circuit shown in the figure below is required. (The /TICS signal of the flash microcontroller programmer can be used to disconnect the user circuit during serial programming.) Figure 25.5-2 Control Circuit AF220/AF210/AF120/AF110 write control pin MB90F362/T(S), MB90F367/T(S) 10kΩ Write control pin AF220/AF210/AF120/AF110 /TICS pin User 564 • Connect the AF220/AF210/AF120/AF110 while the user power is off. • When the programming power is supplied from the AF220/AF210/AF120/AF110, be careful not to short-circuit the user power supply. CHAPTER 26 ROM SECURITY FUNCTION This chapter explains the ROM security function. 26.1 Overview of ROM Security Function 565 CHAPTER 26 ROM SECURITY FUNCTION 26.1 Overview of ROM Security Function The ROM security function protects the content of ROM. ■ Overview of ROM Security Function The ROM security function is a function to prevent ROM data being read to the third party by limiting the access to ROM. Please contact to Fujitsu about details of this function. 566 APPENDIX The appendixes provide I/O maps, instructions, and other information. APPENDIX A I/O Maps APPENDIX B Instructions APPENDIX C Timing Diagrams in Flash Memory Mode APPENDIX D List of Interrupt Vectors 567 APPENDIX APPENDIX A I/O Maps Table A-1 lists addresses to be assigned to the registers in the peripheral blocks. ■ I/O Maps (00XX Addresses) Table A-1 I/O Map (1/5) Address Register 000000H to 000001H Reserved 000002H Port 2 data register 000003H Reserved 000004H Abbreviation Access Peripheral Initial value PDR2 R/W Port 2 XXXXXXXXB Port 4 data register PDR4 R/W Port 4 XXXXXXXXB 000005H Port 5 data register PDR5 R/W Port 5 XXXXXXXXB 000006H Port 6 data register PDR6 R/W Port 6 XXXXXXXXB 000007H Reserved 000008H Port 8 data register PDR8 R/W Port 8 XXXXXXXXB 000009H to 00000AH Reserved 00000BH Analog input enable port 5 ADER5 R/W Port 5, A/D 1 1 1 1 1 1 1 1B 00000CH Analog input enable port 6 ADER6 R/W Port 6, A/D 1 1 1 1 1 1 1 1B 00000DH Reserved 00000EH Input level select register0 ILSR0 R/W Ports XXXXXXXXB 00000FH Input level select register1 ILSR1 R/W Ports XXXXXXXXB DDR2 R/W Port 2 0 0 0 0 0 0 0 0B 000010H Reserved 000011H 000012H Port 2 direction register 000013H Reserved 000014H Port 4 direction register DDR4 R/W Port 4 XXX 0 0 0 0 0B 000015H Port 5 direction register DDR5 R/W Port 5 0 0 0 0 0 0 0 0B 000016H Port 6 direction register DDR6 R/W Port 6 0 0 0 0 0 0 0 0B 000017H Reserved 000018H Port 8 direction register DDR8 R/W Port 8 0 0 0 0 0 0 X 0B 568 APPENDIX A I/O Maps Table A-1 I/O Map (2/5) Address Register 000019H Reserved 00001AH Port A direction register 00001BH to 00001DH Reserved 00001EH Port 2 pull-up control register 00001FH Reserved 000020H Abbreviation Access Peripheral Initial value DDRA W Port A XXX0 0XXXB PUCR2 R/W Port 2 0 0 0 0 0 0 0 0B Serial mode register 0 SMR0 W, R/W 0 0 0 0 0 0 0 0B 000021H Serial control register 0 SCR0 W, R/W 0 0 0 0 0 0 0 0B 000022H Reception/transmission data register 0 RDR0/TDR0 R/W 0 0 0 0 0 0 0 0B 000023H Serial status register 0 SSR0 R, R/W 0 0 0 0 1 0 0 0B 000024H Extended communication control register 0 ECCR0 R, W, R/W 0 0 0 0 0 0 XXB 000025H Extended status control register0 ESCR0 R/W 0 0 0 0 0 1 0 0B 000026H Baud rate generator register 00 BGR00 R/W, R 0 0 0 0 0 0 0 0B 000027H Baud rate generator register 01 BGR01 R/W, R 0 0 0 0 0 0 0 0B 000028H Serial mode register 1 SMR1 W, R/W 0 0 0 0 0 0 0 0B 000029H Serial control register 1 SCR1 W, R/W 0 0 0 0 0 0 0 0B 00002AH Reception/transmission data register 1 RDR1/TDR1 R/W 0 0 0 0 0 0 0 0B 00002BH Serial status register 1 SSR1 R, R/W 0 0 0 0 1 0 0 0B 00002CH Extended communication control register1 ECCR1 R, W, R/W 0 0 0 0 0 0 XXB 00002DH Extended status control register 1 ESCR1 R/W 0 0 0 0 0 1 0 0B 00002EH Baud rate generator register 10 BGR10 R/W, R 0 0 0 0 0 0 0 0B 00002FH Baud rate generator register 11 BGR11 R/W, R 0 0 0 0 0 0 0 0B 000030H to 00003AH Reserved 00003BH Address detection control register 1 PACSR1 R/W 00003CH to 000047H Reserved 000048H PPGC operation mode control register PPGCC W, R/W 000049H PPGD operation mode control register PPGCD W, R/W 00004AH PPGC /D count clock selection register PPGCD R/W UART0 UART1 Address Match Detection 1 0 0 0 0 0 0 0 0B 0 X 0 0 0 XX1B 16-bit PPGC/D 0 X 0 0 0 0 0 1B 0 0 0 0 0 0 X 0B 569 APPENDIX Table A-1 I/O Map (3/5) Address Register Abbreviation Access 00004BH Reserved 00004CH PPGE operation mode control register PPGCE W, R/W 00004DH PPGF operation mode control register PPGCF W, R/W 00004EH PPGE/F count clock selection register PPGEF R/W 00004FH Reserved 000050H Input capture control status 0/1 000051H Input capture edge 0/1 ICE01 R/W, R 000052H Input capture control status 2/3 ICS23 R/W 000053H Input capture edge 2/3 000054H to 000063H Reserved 000064H ICS01 Peripheral Initial value 0 X 0 0 0 XX1B 16-bit PPGE/F 0 X 0 0 0 0 0 1B 0 0 0 0 0 0 X 0B R/W Input Capture 0/1 0 0 0 0 0 0 0 0B XXX0X0XXB Input Capture 2/3 0 0 0 0 0 0 0 0B XXXXXXXXB ICE23 R Timer control status 2 TMCSR2 R/W 000065H Timer control status 2 TMCSR2 R/W 000066H Timer control status 3 TMCSR3 R/W 000067H Timer control status 3 TMCSR3 R/W 16-bit Reload Timer 0 0 0 0 0 0 0 0B 3 XXXX 0 0 0 0B 000068H A/D control status 0 ADCS0 R/W 0 0 0 XXXX 0B 000069H A/D control status 1 ADCS1 R/W, W 0 0 0 0 0 0 0 XB 00006AH A/D data 0 ADCR0 R 00006BH A/D data 1 ADCR1 R XXXXXX 0 0B 00006CH ADC setting 0 ADSR0 R/W 0 0 0 0 0 0 0 0B 00006DH ADC setting 1 ADSR1 R/W 0 0 0 0 0 0 0 0B 00006EH Detection reset control register of low-voltage/CPU operation LVRC R/W, W 00006FH ROM mirror function select ROMM W 000070H to 00007FH Reserved 000080H to 00008FH Reserved for CAN interface. (For more information, see Table 21.3-1 .) 000090H to 00009DH Reserved 00009EH Address detection control register0 570 16-bit Reload Timer 0 0 0 0 0 0 0 0B 2 XXXX 0 0 0 0B A/D Converter PACSR0 R/W 0 0 0 0 0 0 0 0B Detection Reset of Low-voltage/CPU 0 0 1 1 1 0 0 0B Operation ROM Mirror XXXXXXX1B Address Match Detection 0 0 0 0 0 0 0 0 0B APPENDIX A I/O Maps Table A-1 I/O Map (4/5) Address Register Abbreviation Access Peripheral Initial value Delayed Interrupt XXXXXXX0B Generation Module 00009FH Delayed interrupt/release register DIRR R/W 0000A0H Low-power mode control register LPMCR W, R/W Low Power Controller 0 0 0 1 1 0 0 0B 0000A1H Clock selection register CKSCR R, R/W Low Power Controller 1 1 1 1 1 1 0 0B 0000A2H to 0000A7H Reserved 0000A8H Watchdog timer control register WDTC R, W Watchdog Timer XXXXX111B 0000A9H Time base timer control register TBTC W, R/W Time Base Timer 1 XX 0 0 1 0 0B 0000AAH Watch timer control register WTC R, R/W Watch Timer 1 X 0 0 1 0 0 0B 0000ABH to 0000ADH Reserved 0000AEH Flash control status (Flash device only.) FMCS R, R/W Flash Memory 0 0 0 X 0 0 0 0B 0000AFH Reserved 0000B0H Interrupt control register 00 ICR00 W, R/W 0 0 0 0 0 1 1 1B 0000B1H Interrupt control register 01 ICR01 W, R/W 0 0 0 0 0 1 1 1B 0000B2H Interrupt control register 02 ICR02 W, R/W 0 0 0 0 0 1 1 1B 0000B3H Interrupt control register 03 ICR03 W, R/W 0 0 0 0 0 1 1 1B 0000B4H Interrupt control register 04 ICR04 W, R/W 0 0 0 0 0 1 1 1B 0000B5H Interrupt control register 05 ICR05 W, R/W 0 0 0 0 0 1 1 1B 0000B6H Interrupt control register 06 ICR06 W, R/W 0 0 0 0 0 1 1 1B 0000B7H Interrupt control register 07 ICR07 W, R/W 0000B8H Interrupt control register 08 ICR08 W, R/W 0 0 0 0 0 1 1 1B 0000B9H Interrupt control register 09 ICR09 W, R/W 0 0 0 0 0 1 1 1B 0000BAH Interrupt control register 10 ICR10 W, R/W 0 0 0 0 0 1 1 1B 0000BBH Interrupt control register 11 ICR11 W, R/W 0 0 0 0 0 1 1 1B 0000BCH Interrupt control register 12 ICR12 W, R/W 0 0 0 0 0 1 1 1B 0000BDH Interrupt control register 13 ICR13 W, R/W 0 0 0 0 0 1 1 1B 0000BEH Interrupt control register 14 ICR14 W, R/W 0 0 0 0 0 1 1 1B 0000BFH Interrupt control register 15 ICR15 W, R/W 0 0 0 0 0 1 1 1B 0000C0H to 0000C9H Reserved Interrupt Controller 0 0 0 0 0 1 1 1B 571 APPENDIX Table A-1 I/O Map (5/5) Address Register Abbreviation Access Peripheral Initial value 0000CAH External interrupt enable 1 ENIR1 R/W 0 0 0 0 0 0 0 0B 0000CBH External interrupt request 1 EIRR1 R/W XXXXXXXXB 0000CCH External interrupt level 1 ELVR1 R/W External Interrupt 1 0 0 0 0 0 0 0 0B 0000CDH External interrupt level 1 ELVR1 R/W 0 0 0 0 0 0 0 0B 0000CEH External interrupt 1 source select EISSR R/W 0 0 0 0 0 0 0 0B 0000CFH PLL/subclock control register PSCCR W 0000D0H to 0000FFH Reserved 572 PLL XXXX 0 0 0 0B APPENDIX A I/O Maps ■ I/O map (79XX - 7FXX addresses) Table A-2 I/O Map (7900H - 7FFFH) (1/3) Address Register Abbreviation Access Peripheral Initial value 7900H to 7917H Reserved 7918H Reload register LC PRLLC R/W 7919H Reload register HC PRLHC R/W 791AH Reload register LD PRLLD R/W 791BH Reload register HD PRLHD R/W XXXXXXXXB 791CH Reload register LE PRLLE R/W XXXXXXXXB 791DH Reload register HE PRLHE R/W 791EH Reload register LF PRLLF R/W 791FH Reload register HF PRLHF R/W XXXXXXXXB 7920H Input capture 0 IPCP0 R XXXXXXXXB 7921H Input capture 0 IPCP0 R 7922H Input capture 1 IPCP1 R XXXXXXXXB 7923H Input capture 1 IPCP1 R XXXXXXXXB 7924H Input capture 2 IPCP2 R XXXXXXXXB 7925H Input capture 2 IPCP2 R 7926H Input capture 3 IPCP3 R XXXXXXXXB 7927H Input capture 3 IPCP3 R XXXXXXXXB 7928H to 793FH Reserved 7940H Timer data 0 TCDT0 R/W 0 0 0 0 0 0 0 0B 7941H Timer data 0 TCDT0 R/W 7942H Timer control 0 TCCSL0 R/W 0 0 0 0 0 0 0 0B 7943H Timer control 0 TCCSH0 R/W 0XXXXXXXB 7944H to 794BH Reserved TMR2/ TMRLR2 R, W TMR3/ TMRLR3 R, W 794CH 794FH 16-bit PPG C/D 16-bit PPG E/F Input Capture 0/1 Input Capture 2/3 I/O Timer 0 Timer 2/reload 2 794DH 794EH XXXXXXXXB Timer 3/reload 3 R, W R, W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 0B 16-bit Reload Timer 2 XXXXXXXXB 16-bit Reload Timer 3 XXXXXXXXB XXXXXXXXB XXXXXXXXB 573 APPENDIX Table A-2 I/O Map (7900H - 7FFFH) (2/3) Address Register 7950H to 795FH Reserved 7960H Clock supervisor control register 7961H to 796DH Reserved 796EH CAN direct mode register (For only MB90V340) 796FH to 79DFH Reserved 79E0H Abbreviation Access Peripheral Initial value CSVCR R, R/W Clock supervisor 0 0 0 1 1 1 0 0B CDMR R/W CAN Clock Sync XXXXXXX0B Detection address setting 0 PADR0 R/W XXXXXXXXB 79E1H Detection address setting 0 PADR0 R/W XXXXXXXXB 79E2H Detection address setting 0 PADR0 R/W XXXXXXXXB 79E3H Detection address setting 1 PADR1 R/W XXXXXXXXB 79E4H Detection address setting 1 PADR1 R/W 79E5H Detection address setting 1 PADR1 R/W XXXXXXXXB 79E6H Detection address setting 2 PADR2 R/W XXXXXXXXB 79E7H Detection address setting 2 PADR2 R/W XXXXXXXXB 79E8H Detection address setting 2 PADR2 R/W XXXXXXXXB 79E9H to 79EFH Reserved 79F0H Detection address setting 3 PADR3 R/W XXXXXXXXB 79F1H Detection address setting 3 PADR3 R/W XXXXXXXXB 79F2H Detection address setting 3 PADR3 R/W XXXXXXXXB 79F3H Detection address setting 4 PADR4 R/W XXXXXXXXB 79F4H Detection address setting 4 PADR4 R/W 79F5H Detection address setting 4 PADR4 R/W XXXXXXXXB 79F6H Detection address setting 5 PADR5 R/W XXXXXXXXB 79F7H Detection address setting 5 PADR5 R/W XXXXXXXXB 79F8H Detection address setting 5 PADR5 R/W XXXXXXXXB 79F9H to 7BFFH Reserved 7C00H to 7CFFH Reserved for CAN interface 1. (For more information, see Table 21.3-1 .) 574 Address Match Detection 0 Address Match Detection 1 XXXXXXXXB XXXXXXXXB APPENDIX A I/O Maps Table A-2 I/O Map (7900H - 7FFFH) (3/3) Address Register Abbreviation Access Peripheral 7D00H to 7DFFH Reserved for CAN interface 1. (For more information, see Table 21.3-2 .) 7E00H to 7FFFH Reserved Initial value Note: Any write access to reserved addresses in I/O map should not be perfoermed. A read access to reserved address results in reading "X". ● Explanation of write and read R/W: Both read and write enabled R: Only read enabled W: Only write enabled ● Explanation of initial values 0: The initial value of this bit is "0". 1: The initial value of this bit is "1". X: The initial value of this bit is undefined. 575 APPENDIX APPENDIX B Instructions Appendix B describes the instructions used by the F2MC-16LX. B.1 Instruction Types B.2 Addressing B.3 Direct Addressing B.4 Indirect Addressing B.5 Execution Cycle Count B.6 Effective address field B.7 How to Read the Instruction List B.8 F2MC-16LX Instruction List B.9 Instruction Map 576 APPENDIX B Instructions B.1 Instruction Types The F2MC-16LX supports 351 types of instructions. Addressing is enabled by using an effective address field of each instruction or using the instruction code itself. ■ Instruction Types The F2MC-16LX supports the following 351 types of instructions: • 41 transfer instructions (byte) • 38 transfer instructions (word or long word) • 42 addition/subtraction instructions (byte, word, or long word) • 12 increment/decrement instructions (byte, word, or long word) • 11 comparison instructions (byte, word, or long word) • 11 unsigned multiplication/division instructions (word or long word) • 11 signed multiplication/division instructions (word or long word) • 39 logic instructions (byte or word) • 6 logic instructions (long word) • 6 sign inversion instructions (byte or word) • 1 normalization instruction (long word) • 18 shift instructions (byte, word, or long word) • 50 branch instructions • 6 accumulator operation instructions (byte or word) • 28 other control instructions (byte, word, or long word) • 21 bit operation instructions • 10 string instructions 577 APPENDIX B.2 Addressing With the F2MC-16LX, the address format is determined by the instruction effective address field or the instruction code itself (implied). When the address format is determined by the instruction code itself, specify an address in accordance with the instruction code used. Some instructions permit the user to select several types of addressing. ■ Addressing The F2MC-16LX supports the following 23 types of addressing: 578 • Immediate (#imm) • Register direct • Direct branch address (addr16) • Physical direct branch address (addr24) • I/O direct (io) • Abbreviated direct address (dir) • Direct address (addr16) • I/O direct bit address (io:bp) • Abbreviated direct bit address (dir:bp) • Direct bit address (addr16:bp) • Vector address (#vct) • Register indirect (@RWj j = 0 to 3) • Register indirect with post increment (@RWj+ j = 0 to 3) • Register indirect with displacement (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3) • Long register indirect with displacement (@RLi + disp8 i = 0 to 3) • Program counter indirect with displacement (@PC + disp16) • Register indirect with base index (@RW0 + RW7, @RW1 + RW7) • Program counter relative branch address (rel) • Register list (rlst) • Accumulator indirect (@A) • Accumulator indirect branch address (@A) • Indirectly-specified branch address (@ear) • Indirectly-specified branch address (@eam) APPENDIX B Instructions ■ Effective Address Field Table B.2-1 lists the address formats specified by the effective address field. Table B.2-1 Effective Address Field Code Representation Address format Default bank 00 R0 RW0 RL0 01 R1 RW1 (RL0) 02 R2 RW2 RL1 03 R3 RW3 (RL1) 04 R4 RW4 RL2 05 R5 RW5 (RL2) 06 R6 RW6 RL3 07 R7 RW7 (RL3) 08 @RW0 09 @RW1 0A @RW2 0B @RW3 SPB 0C @RW0+ DTB 0D @RW1+ 0E @RW2+ 0F @RW3+ SPB 10 @RW0+disp8 DTB 11 @RW1+disp8 12 @RW2+disp8 13 @RW3+disp8 SPB 14 @RW4+disp8 DTB 15 @RW5+disp8 16 @RW6+disp8 17 @RW7+disp8 SPB 18 @RW0+disp16 DTB 19 @RW1+disp16 1A @RW2+disp16 1B @RW3+disp16 1C @RW0+RW7 Register indirect with index DTB 1D @RW1+RW7 Register indirect with index DTB 1E @PC+disp16 PC indirect with 16-bit displacement PCB 1F addr16 Direct address DTB Register direct: Individual parts correspond to the byte, word, and long word types in order from the left. None DTB Register indirect Register indirect with post increment Register indirect with 8-bit displacement Register indirect with 8-bit displacement Register indirect with 16-bit displacement DTB ADB DTB ADB DTB ADB DTB ADB DTB ADB SPB 579 APPENDIX B.3 Direct Addressing An operand value, register, or address is specified explicitly in direct addressing mode. ■ Direct Addressing ● Immediate addressing (#imm) Specify an operand value explicitly (#imm4/ #imm8/ #imm16/ #imm32). Figure B.3-1 Example of Immediate Addressing (#imm) MOVW A, #01212H (This instruction stores the operand value in A.) Before execution A 2233 4455 After execution A 4 4 5 5 1 2 1 2 (Some instructions transfer AL to AH.) ● Register direct addressing Specify a register explicitly as an operand. Table B.3-1 lists the registers that can be specified. Figure B.3-2 shows an example of register direct addressing. Table B.3-1 Direct Addressing Registers General-purpose register Special-purpose register Byte R0, R1, R2, R3, R4, R5, R6, R7 Word RW0, RW1, RW2, RW3, RW4, R5W, RW6, RW7 Long word RL0, RL1, RL2, RL3 Accumulator A, AL Pointer SP * Bank PCB, DTB, USB, SSB, ADB Page DPR Control PS, CCR, RP, ILM *: One of the user stack pointer (USP) and system stack pointer (SSP) is selected and used depending on the value of the S flag bit in the condition code register (CCR). For branch instructions, the program counter (PC) is not specified in an instruction operand but is specified implicitly. 580 APPENDIX B Instructions Figure B.3-2 Example of Register Direct Addressing MOV R0, A (This instruction transfers the eight low-order bits of A to the general-purpose register R0.) Before execution A 0716 2534 After execution A 0716 2564 Memory space R0 ?? Memory space R0 34 ● Direct branch addressing (addr16) Specify an offset explicitly for the branch destination address. The size of the offset is 16 bits, which indicates the branch destination in the logical address space. Direct branch addressing is used for an unconditional branch, subroutine call, or software interrupt instruction. Bits 23 to 16 of the address are specified by the program bank register (PCB). Figure B.3-3 Example of Direct Branch Addressing (addr16) JMP 3B20H (This instruction causes an unconditional branch by direct branch addressing in a bank.) Before execution After execution PC 3 C 2 0 PC 3 B 2 0 PCB 4 F Memory space 4F3C22H 4F3C21H 4F3C20H 3B 20 62 4F3B20H Next instruction JMP 3B20H PCB 4 F 581 APPENDIX ● Physical direct branch addressing (addr24) Specify an offset explicitly for the branch destination address. The size of the offset is 24 bits. Physical direct branch addressing is used for unconditional branch, subroutine call, or software interrupt instruction. Figure B.3-4 Example of Direct Branch Addressing (addr24) JMPP 333B20H (This instruction causes an unconditional branch by direct branch 24-bit addressing.) Before execution PC 3 C 2 0 PC 3 B 2 0 After execution PCB 4 F Memory space 4F3C23H 4F3C22H 4F3C21H 4F3C20H 33 3B 20 63 333B20H Next instruction JMPP 333B20H PCB 3 3 ● I/O direct addressing (io) Specify an 8-bit offset explicitly for the memory address in an operand. The I/O address space in the physical address space from 000000H to 0000FFH is accessed regardless of the data bank register (DTB) and direct page register (DPR). A bank select prefix for bank addressing is invalid if specified before an instruction using I/O direct addressing. Figure B.3-5 Example of I/O Direct Addressing (io) MOVW A, i:0C0H (This instruction reads data by I/O direct addressing and stores it in A.) Before execution A 0716 2534 Memory space 0000C1H 0000C0H After execution 582 A 2534 FFEE FF EE APPENDIX B Instructions ● Abbreviated direct addressing (dir) Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register (DTB). Figure B.3-6 Example of Abbreviated Direct Addressing (dir) MOVW S;20H, A (This instruction writes the contents of the eight low-order bits of A in abbreviated direct addressing mode.) Before execution A 4455 66 After execution A DTB 7 7 4455 66 Memory space 1212 776620H 1212 DTB 7 7 ?? Memory space 776620H 12 ● Direct addressing (addr16) Specify the 16 low-order bits of a memory address explicitly in an operand. Address bits 16 to 23 are specified by the data bank register (DTB). A prefix instruction for access space addressing is invalid for this mode of addressing. Figure B.3-7 Example of Direct Addressing (addr16) MOVW A, 3B20H (This instruction reads data by direct addressing and stores it in A.) Before execution A Memory space 2 0 2 0 A A B B DTB 5 5 After execution A AABB 0123 553B21H 553B20H 01 23 DTB 5 5 583 APPENDIX ● I/O direct bit addressing (io:bp) Specify bits in physical addresses 000000H to 0000FFH explicitly. Bit positions are indicated by ":bp", where the larger number indicates the most significant bit (MSB) and the lower number indicates the least significant bit (LSB). Figure B.3-8 Example of I/O Direct Bit Addressing (io:bp) SETB I:0C1H:0 (This instruction sets bits by I/O direct bit addressing.) Memory space Before execution 0000C1H 00 After execution 0000C1H 01 ● Abbreviated direct bit addressing (dir:bp) Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register (DTB). Bit positions are indicated by ":bp", where the larger number indicates the most significant bit (MSB) and the lower number indicates the least significant bit (LSB). Figure B.3-9 Example of Abbreviated Direct Bit Addressing (dir:bp) SETB S:10H:0 (This instruction sets bits by abbreviated direct bit addressing.) Memory space Before execution DTB 5 5 DPR 6 6 556610H 00 Memory space After execution DTB 5 5 DPR 6 6 556610H 01 ● Direct bit addressing (addr16:bp) Specify arbitrary bits in 64K bytes explicitly. Address bits 16 to 23 are specified by the data bank register (DTB). Bit positions are indicated by ":bp", where the larger number indicates the most significant bit (MSB) and the lower number indicates the least significant bit (LSB). Figure B.3-10 Example of Direct Bit Addressing (addr16:bp) SETB 2222H:0 (This instruction sets bits by direct bit addressing.) Memory space Before execution DTB 5 5 552222H 00 Memory space After execution 584 DTB 5 5 552222H 01 APPENDIX B Instructions ● Vector Addressing (#vct) Specify vector data in an operand to indicate the branch destination address. There are two sizes for vector numbers: 4 bits and 8 bits. Vector addressing is used for a subroutine call or software interrupt instruction. Figure B.3-11 Example of Vector Addressing (#vct) CALLV #15 (This instruction causes a branch to the address indicated by the interrupt vector specified in an operand.) Before execution PC 0000 PCB F F After execution PC Memory space FFFFE1H FFFFE0H D0 00 FFC000H EF D000 PCB F F CALLV #15 Table B.3-2 CALLV Vector List Instruction Vector address L Vector address H CALLV #0 XXFFFEH XXFFFFH CALLV #1 XXFFFCH XXFFFDH CALLV #2 XXFFFAH XXFFFBH CALLV #3 XXFFF8H XXFFF9H CALLV #4 XXFFF6H XXFFF7H CALLV #5 XXFFF4H XXFFF5H CALLV #6 XXFFF2H XXFFF3H CALLV #7 XXFFF0H XXFFF1H CALLV #8 XXFFEEH XXFFEFH CALLV #9 XXFFECH XXFFEDH CALLV #10 XXFFEAH XXFFEBH CALLV #11 XXFFE8H XXFFE9H CALLV #12 XXFFE6H XXFFE7H CALLV #13 XXFFE4H XXFFE5H CALLV #14 XXFFE2H XXFFE3H CALLV #15 XXFFE0H XXFFE1H Note: A PCB register value is set in XX. Note: When the program bank register (PCB) is FFH, the vector area overlaps the vector area of INT #vct8 (#0 to #7). Use vector addressing carefully (see Table B.3-2 ). 585 APPENDIX B.4 Indirect Addressing In indirect addressing mode, an address is specified indirectly by the address data of an operand. ■ Indirect Addressing ● Register indirect addressing (@RWj j = 0 to 3) Memory is accessed using the contents of general-purpose register RWj as an address. Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 is used, or additional data bank register (ADB) when RW2 is used. Figure B.4-1 Example of Register Indirect Addressing (@RWj j = 0 to 3) MOVW A, @RW1 (This instruction reads data by register indirect addressing and stores it in A.) Before execution A 0716 2534 RW1 D 3 0 F DTB 7 8 After execution A Memory space 78D310H 78D30FH FF EE 2534 FFEE RW1 D 3 0 F DTB 7 8 ● Register indirect addressing with post increment (@RWj+ j = 0 to 3) Memory is accessed using the contents of general-purpose register RWj as an address. After operand operation, RWj is incremented by the operand size (1 for a byte, 2 for a word, or 4 for a long word). Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 is used, or additional data bank register (ADB) when RW2 is used. If the post increment results in the address of the register that specifies the increment, the incremented value is referenced after that. In this case, if the next instruction is a write instruction, priority is given to writing by an instruction and, therefore, the register that would be incremented becomes write data. 586 APPENDIX B Instructions Figure B.4-2 Example of Register Indirect Addressing with Post Increment (@RWj+ j = 0 to 3) MOVW A, @RW1+ (This instruction reads data by register indirect addressing with post increment and stores it in A.) Before execution A 0716 2534 Memory space RW1 D 3 0 F DTB 7 8 After execution A 78D310H 78D30FH FF EE 2534 FFEE RW1 D 3 1 1 DTB 7 8 ● Register indirect addressing with offset (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3) Memory is accessed using the address obtained by adding an offset to the contents of general-purpose register RWj. Two types of offset, byte and word offsets, are used. They are added as signed numeric values. Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0, RW1, RW4, or RW5 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 or RW7 is used, or additional data bank register (ADB) when RW2 or RW6 is used. Figure B.4-3 Example of Register Indirect Addressing with Offset (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3) MOVW A, @RW1+10H (This instruction reads data by register indirect addressing with an offset and stores it in A.) Before execution A 0716 2534 Memory space RW1 D 3 0 F DTB 7 8 78D320H 78D31FH FF EE (+10H) After execution A 2534 FFEE RW1 D 3 0 F DTB 7 8 ● Long register indirect addressing with offset (@RLi + disp8 i = 0 to 3) Memory is accessed using the address that is the 24 low-order bits obtained by adding an offset to the contents of general-purpose register RLi. The offset is 8-bits long and is added as a signed numeric value. Figure B.4-4 Example of Long Register Indirect Addressing with Offset (@RLi + disp8 i = 0 to 3) MOVW A, @RL2+25H (This instruction reads data by long register indirect addressing with an offset and stores it in A.) Before execution A RL2 0716 2534 F382 4B02 Memory space 824B28H 824B27H FF EE (+25H) After execution A 2534 FFEE RL2 F382 4B02 587 APPENDIX ● Program counter indirect addressing with offset (@PC + disp16) Memory is accessed using the address indicated by (instruction address + 4 + disp16). The offset is one word long. Address bits 16 to 23 are specified by the program bank register (PCB). Note that the operand address of each of the following instructions is not deemed to be (next instruction address + disp16): • DBNZ eam, rel • DWBNZ eam, rel • CBNE eam, #imm8, rel • CWBNE eam, #imm16, rel • MOV eam, #imm8 • MOVW eam, #imm16 Figure B.4-5 Example of Program Counter Indirect Addressing with Offset (@PC + disp16) MOVW A, @PC+20H (This instruction reads data by program counter indirect addressing with a offset and stores it in A.) Before execution A 0716 2534 PCB C 5 PC 4 5 5 6 After execution A 2534 FFEE PCB C 5 PC 4 5 5 A Memory space C5457BH C5457AH FF EE C5455AH +20H C54559H +4 C54558H C54557H C54556H 00 20 9E 73 MOVW A, @PC+20H ● Register indirect addressing with base index (@RW0 + RW7, @RW1 + RW7) Memory is accessed using the address determined by adding RW0 or RW1 to the contents of generalpurpose register RW7. Address bits 16 to 23 are indicated by the data bank register (DTB). Figure B.4-6 Example of Register Indirect Addressing with Base Index (@RW0 + RW7, @RW1 + RW7) MOVW A, @RW1+RW7 (This instruction reads data by register indirect addressing with a base index and stores it in A.) Before execution A 0716 RW1 D 3 0 F 2534 DTB 7 8 + RW7 0 1 0 1 After execution A 2534 FFEE RW1 D 3 0 F RW7 0 1 0 1 588 DTB 7 8 Memory space 78D411H 78D410H FF EE APPENDIX B Instructions ● Program counter relative branch addressing (rel) The address of the branch destination is a value determined by adding an 8-bit offset to the program counter (PC) value. If the result of addition exceeds 16 bits, bank register incrementing or decrementing is not performed and the excess part is ignored, and therefore the address is contained within a 64-Kbyte bank. This addressing is used for both conditional and unconditional branch instructions. Address bits 16 to 23 are indicated by the program bank register (PCB). Figure B.4-7 Example of Program Counter Relative Branch Addressing (rel) BRA 3B20H (This instruction causes an unconditional relative branch.) Before execution PC After execution PC 3C20 3B20 Memory space PCB 4 F PCB 4 F 4F3B20H Next instruction 4F3C20H 4F3C21H 4F3C22H 60 FE FF BRA 3B20H ● Register list (rlst) Specify a register to be pushed onto or popped from a stack. Figure B.4-8 Configuration of the Register List MSB LSB RW7 RW6 RW5 RW4 RW3 RW2 RW1 RW0 A register is selected when the corresponding bit is 1 and deselected when the bit is 0. MSB : Highest bit LSB : Lowest bit 589 APPENDIX Figure B.4-9 Example of Register List (rlst) POPW RW0, RW4 (This instruction transfers memory data indicated by the SP to multiple word registers indicated by the register list.) SP 34FA SP RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7 RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7 SP 02 01 04 03 Memory space Memory space SP 34FEH 34FDH 34FCH 34FBH 34FAH 04 03 02 01 34FE 04 03 02 01 34FEH 34FDH 34FCH 34FBH 34FAH After execution Before execution ● Accumulator indirect addressing (@A) Memory is accessed using the address indicated by the contents of the low-order bytes (16 bits) of the accumulator (AL). Address bits 16 to 23 are specified by a mnemonic in the data bank register (DTB). Figure B.4-10 Example of Accumulator Indirect Addressing (@A) MOVW A, @A (This instruction reads data by accumulator indirect addressing and stores it in A.) Before execution A 0716 2534 DTB B B After execution A 0716 FFEE DTB B B 590 Memory space BB2535H BB2534H FF EE APPENDIX B Instructions ● Accumulator indirect branch addressing (@A) The address of the branch destination is the content (16 bits) of the low-order bytes (AL) of the accumulator. It indicates the branch destination in the bank address space. Address bits 16 to 23 are specified by the program bank register (PCB). For the Jump Context (JCTX) instruction, however, address bits 16 to 23 are specified by the data bank register (DTB). This addressing is used for unconditional branch instructions. Figure B.4-11 Example of Accumulator Indirect Branch Addressing (@A) JMP @A (This instruction causes an unconditional branch by accumulator indirect branch addressing.) Before execution PC 3C20 PCB 4 F A 6677 3B20 PC 3B20 PCB 4 F Memory space 4F3C20H 4F3B20H After execution A 61 JMP @A Next instruction 6677 3B20 ● Indirect specification branch addressing (@ear) The address of the branch destination is the word data at the address indicated by ear. Figure B.4-12 Example of Indirect Specification Branch Addressing (@ear) JMP @@RW0 (This instruction causes an unconditional branch by register indirect addressing.) Before execution 3C20 PCB 4 F PW0 7 F 4 8 DTB 2 1 PC Memory space 4F3C21H 4F3C20H 4F3B20H After execution 3B20 PCB 4 F PW0 7 F 4 8 DTB 2 1 PC 217F49H 217F48H 08 73 JMP @@RW0 Next instruction 3B 20 591 APPENDIX ● Indirect specification branch addressing (@eam) The address of the branch destination is the word data at the address indicated by eam. Figure B.4-13 Example of Indirect Specification Branch Addressing (@eam) JMP @RW0 (This instruction causes an unconditional branch by register indirect addressing.) Before execution PC 3C20 PCB 4 F 4F3C21H 4F3C20H PW0 3 B 2 0 After execution PC 3B20 PW0 3 B 2 0 592 Memory space PCB 4 F 4F3B20H 00 73 JMP @RW0 Next instruction APPENDIX B Instructions B.5 Execution Cycle Count The number of cycles required for instruction execution (execution cycle count) is obtained by adding the number of cycles required for each instruction, "correction value" determined by the condition, and the number of cycles for instruction fetch. ■ Execution Cycle Count The number of cycles required for instruction execution (execution cycle count) is obtained by adding the number of cycles required for each instruction, "correction value" determined by the condition, and the number of cycles for instruction fetch. In the mode of fetching an instruction from memory such as internal ROM connected to a 16-bit bus, the program fetches the instruction being executed in word increments. Therefore, intervening in data access increases the execution cycle count. Similarly, in the mode of fetching an instruction from memory connected to an 8-bit external bus, the program fetches every byte of an instruction being executed. Therefore, intervening in data access increases the execution cycle count. In CPU intermittent operation mode, access to a general-purpose register, internal ROM, internal RAM, internal I/O, or external data bus causes the clock to the CPU to halt for the cycle count specified by the CG0 and CG1 bits of the low power consumption mode control register. Therefore, for the cycle count required for instruction execution in CPU intermittent operation mode, add the "access count x cycle count for the halt" as a correction value to the normal execution count. 593 APPENDIX ■ Calculating the execution cycle count Table B.5-1 lists execution cycle counts and Table B.5-2 and Table B.5-3 summarize correction value data. Table B.5-1 Execution Cycle Counts in Each Addressing Mode (a) * Code Operand 00 | 07 Ri Rwi RLi 08 | 0B Register access count in each addressing mode See the instruction list. See the instruction list. @RWj 2 1 0C | 0F @RWj+ 4 2 10 | 17 @RWi+disp8 2 1 18 | 1B @RWi+disp16 2 1 1C 1D 1E 1F @RW0+RW7 @RW1+RW7 @PC+disp16 addr16 4 4 2 1 2 2 0 0 *: (a) is used for 594 Execution cycle count in each addressing mode (cycle count) and B (correction value) in "B.8 F2MC-16LX Instruction List". APPENDIX B Instructions Table B.5-2 Cycle Count Correction Values for Counting Execution Cycles (b) byte *1 Operand (c) word *1 (d) long *1 Cycle count Access count Cycle count Access count Cycle count Access count Internal register +0 1 +0 1 +0 2 Internal memory Even address +0 1 +0 1 +0 2 Internal memory Odd address +0 1 +2 2 +4 4 External data bus *2 16-bit even address +1 1 +1 1 +2 2 External data bus *2 16-bit odd address +1 1 +4 2 +8 4 External data bus *2 8-bits +1 1 +4 2 +8 4 *1: (b), (c), and (d) are used for (cycle count) and B (correction value) in "B.8 F2MC-16LX Instruction List". *2: When an external data bus is used, the number of cycles during which an instruction is made to wait by ready - signal input or automatic ready must also be added. Note: When an external data bus is used, the cycle counts during which an instruction is made to wait by ready input or automatic ready must also be added. Table B.5-3 Cycle Count Correction Values for Counting Instruction Fetch Cycles Instruction Byte boundary Word boundary Internal memory - +2 External data bus 16-bits - +3 External data bus 8-bits +3 - Note: • When an external data bus is used, the cycle counts during which an instruction is made to wait by ready input or automatic ready must also be added. • Actually, instruction execution is not delayed by every instruction fetch. Therefore, use the correction values to calculate the worst case. 595 APPENDIX B.6 Effective address field Table B.6-1 shows the effective address field. ■ Effective Address Field Table B.6-1 Effective Address Field Code 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Representation R0 RW0 R1 RW1 R2 RW2 R3 RW3 R4 RW4 R5 RW5 R6 RW6 R7 RW7 @RW0 @RW1 @RW2 @RW3 @RW0+ @RW1+ @RW2+ @RW3+ @RW0+disp8 @RW1+disp8 @RW2+disp8 @RW3+disp8 @RW4+disp8 @RW5+disp8 @RW6+disp8 @RW7+disp8 @RW0+disp16 @RW1+disp16 @RW2+disp16 @RW3+disp16 @RW0+RW7 @RW1+RW7 @PC+disp16 addr16 RL0 (RL0) RL1 (RL1) RL2 (RL2) RL3 (RL3) Address format Byte count of extended address part * Register direct: Individual parts correspond to the byte, word, and long word types in order from the left. - Register indirect 0 Register indirect with post increment 0 Register indirect with 8-bit displacement 1 Register indirect with 16-bit displacement 2 Register indirect with index Register indirect with index PC indirect with 16-bit displacement Direct address 0 0 2 2 *: Each byte count of the extended address part applies to + in the # (byte count) column in "B.8 F2MC16LX Instruction List". For the meaning of "#", see "B.7 How to Read the Instruction List". 596 APPENDIX B Instructions B.7 How to Read the Instruction List Table B.7-1 describes the items used in the F2MC-16LX Instruction List, and Table B.7-2 describes the symbols used in the same list. ■ Description of Instruction Presentation Items and Symbols Table B.7-1 Description of Items in the Instruction List (1/2) Item Description Mnemonic Uppercase, symbol: Represented as is in the assembler. Lowercase: Rewritten in the assembler. Number of following lowercase: Indicates bit length in the instruction. # Indicates the number of bytes. Indicates the number of cycles. RG Indicates the number of times a register access is performed during instruction execution. The number is used to calculate the correction value for CPU intermittent operation. B Indicates the correction value used to calculate the actual number of cycles during instruction execution. The actual number of cycles during instruction execution can be determined by adding the value in the column to this value. Operation Indicates the instruction operation. LH Indicates the special operation for bits 15 to 08 of the accumulator. Z: Transfers 0. X: Transfers after sign extension. -: No transfer AH Indicates the special operation for the 16 high-order bits of the accumulator. *: Transfers from AL to AH. -: No transfer Z: Transfers 00 to AH. X: Transfers 00H or FFH to AH after AL sign extension. I S T N Z V Each indicates the state of each flag: I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero), V (overflow), C (carry). *: Changes upon instruction execution. -: No change Z: Set upon instruction execution. X: Reset upon instruction execution. C 597 APPENDIX Table B.7-1 Description of Items in the Instruction List (2/2) Item RMW Description Indicates whether the instruction is a Read Modify Write instruction (reading data from memory by the I instruction and writing the result to memory). *: Read Modify Write instruction -: Not Read Modify Write instruction Note: Cannot be used for an address that has different meanings between read and write operations. Table B.7-2 Explanation on Symbols in the Instruction List (1/2) Symbol 598 Explanation A The bit length used varies depending on the 32-bit accumulator instruction. Byte: Low-order 8 bits of byte AL Word: 16 bits of word AL Long word: 32 bits of AL and AH AH 16 high-order bits of A AL 16 low-order bits of A SP Stack pointer (USP or SSP) PC Program counter PCB Program bank register DTB Data bank register ADB Additional data bank register SSB System stack bank register USB User stack bank register SPB Current stack bank register (SSB or USB) DPR Direct page register brg1 DTB, ADB, SSB, USB, DPR, PCB, SPB brg2 DTB, ADB, SSB, USB, DPR, SPB Ri R0, R1, R2, R3, R4, R5, R6, R7 RWi RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7 RWj RW0, RW1, RW2, RW3 RLi RL0, RL1, RL2, RL3 dir Abbreviated direct addressing addr16 Direct addressing addr24 Physical direct addressing ad24 0-15 Bits 0 to 15 of addr24 ad24 16-23 Bits 16 to 23 of addr24 io I/O area (000000H to 0000FFH) APPENDIX B Instructions Table B.7-2 Explanation on Symbols in the Instruction List (2/2) Symbol Explanation #imm4 4-bit immediate data #imm8 8-bit immediate data #imm16 16-bit immediate data #imm32 32-bit immediate data ext (imm8) 16-bit data obtained by sign extension of 8-bit immediate data disp8 8-bit displacement disp16 16-bit displacement bp Bit offset vct4 Vector number (0 to 15) vct8 Vector number (0 to 255) ( )b Bit address rel PC relative branch ear Effective addressing (code 00 to 07) eam Effective addressing (code 08 to 1F) rlst Register list 599 APPENDIX B.8 F2MC-16LX Instruction List Table B.8-1 to Table B.8-18 list the instructions used by the F2MC-16LX. ■ F2MC-16LX Instruction List Table B.8-1 41 Transfer Instructions (byte) Mnemonic MOV A,dir MOV A,addr16 MOV A,Ri MOV A,ear MOV A,eam MOV A,io MOV A,#imm8 MOV A,@A MOV A,@RLi+disp8 MOVN A,#imm4 MOVX A,dir MOVX A,addr16 MOVX A,Ri MOVX A,ear MOVX A,eam MOVX A,io MOVX A,#imm8 MOVX A,@A MOVX A,@RWi+disp8 MOVX A,@RLi+disp8 MOV dir,A MOV addr16,A MOV Ri,A MOV ear,A MOV eam,A MOV io,A MOV @RLi+disp8,A MOV Ri,ear MOV Ri,eam MOV ear,Ri MOV eam,Ri MOV Ri,#imm8 MOV io,#imm8 MOV dir,#imm8 MOV ear,#imm8 MOV eam,#imm8 MOV @AL,AH / MOV @A,T XCH A,ear XCH A,eam XCH Ri,ear XCH Ri,eam # 2 3 1 2 2+ 2 2 2 3 1 2 3 2 2 2+ 2 2 2 2 3 2 3 1 2 2+ 2 3 2 2+ 2 2+ 2 3 3 3 3+ 2 2 2+ 2 2+ RG 3 4 2 2 3 + (a) 3 2 3 10 1 3 4 2 2 3 + (a) 3 2 3 5 10 3 4 2 2 3 + (a) 3 10 3 4 + (a) 4 5 + (a) 2 5 5 2 4 + (a) 3 4 5 + (a) 7 9 + (a) 0 0 1 1 0 0 0 0 2 0 0 0 1 1 0 0 0 0 1 2 0 0 1 1 0 0 2 2 1 2 1 1 0 0 1 0 0 2 0 4 2 B (b) (b) 0 0 (b) (b) 0 (b) (b) 0 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) 0 0 (b) (b) (b) 0 (b) 0 (b) 0 (b) (b) 0 (b) (b) 0 2 x (b) 0 2 x (b) Operation byte (A) <-- (dir) byte (A) <-- (addr16) byte (A) <-- (Ri) byte (A) <-- (ear) byte (A) <-- (eam) byte (A) <-- (io) byte (A) <-- imm8 byte (A) <-- ((A)) byte (A) <-- ((RLi)+disp8) byte (A) <-- imm4 byte (A) <-- (dir) byte (A) <-- (addr16) byte (A) <-- (Ri) byte (A) <-- (ear) byte (A) <-- (eam) byte (A) <-- (io) byte (A) <-- imm8 byte (A) <-- ((A)) byte (A) <-- ((RWi)+disp8) byte (A) <-- ((RLi)+disp8 byte (dir) <-- (A) byte (addr16) <-- (A) byte (Ri) <-- (A) byte (ear) <-- (A) byte (eam) <-- (A) byte (io) <-- (A) byte ((RLi)+disp8) <-- (A) byte (Ri) <-- (ear) byte (Ri) <-- (eam) byte (ear) <-- (Ri) byte (eam) <-- (Ri) byte (Ri) <-- imm8 byte (io) <-- imm8 byte (dir) <-- imm8 byte (ear) <-- imm8 byte (eam) <-- imm8 byte ((A)) <-- (AH) byte (A) <--> (ear) byte (A) <--> (eam) byte (Ri) <--> (ear) byte (Ri) <--> (eam) L H A H I S T N Z V C R M W Z Z Z Z Z Z Z Z Z Z X X X X X X X X X X Z Z - * * * * * * * * * * * * * * * * * * - - - * * * * * * * * * R - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - * * * * * * * * * * * * * * * * * * * * * * * * - - - - Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. 600 APPENDIX B Instructions Table B.8-2 38 Transfer Instructions (byte) Mnemonic # MOVW A,dir MOVW A,addr16 MOVW A,SP MOVW A,RWi MOVW A,ear MOVW A,eam MOVW A,io MOVW A,@A MOVW A,#imm16 MOVW A,@RWi+disp8 MOVW A,@RLi+disp8 MOVW dir,A MOVW addr16,A MOVW SP,A MOVW RWi,A MOVW ear,A MOVW eam,A MOVW io,A MOVW @RWi+disp8,A MOVW @RLi+disp8,A MOVW RWi,ear MOVW MOVW ear,Rwi MOVW eam,Rwi MOVW RWi,#imm16 MOVW io,#imm16 MOVW ear,#imm16 MOVW eam,#imm16 MOVW @AL,AH / MOVW @A,T XCHW A,ear XCHW A,eam XCHW RWi, ear XCHW RWi, eam MOVL A,ear MOVL A,eam MOVL A,#imm32 MOVL ear,A MOVL eam,A 2 3 3 1 2 2+ 2 2 3 2 3 2 3 1 1 2 2+ 2 2 3 2 2+ 2 2+ 3 4 4 4+ 2 2 2+ 2 2+ 2 2+ 5 2 2+ RG 3 4 1 2 2 3 + (a) 3 3 2 5 10 3 4 1 2 2 3 + (a) 3 5 10 3 4 + (a) 4 5 + (a) 2 5 2 4 + (a) 3 4 5 + (a) 7 9 + (a) 4 5 + (a) 3 4 5 + (a) 0 0 0 1 1 0 0 0 2 1 2 0 0 0 1 1 0 0 1 2 2 1 2 1 1 0 1 0 0 2 0 4 2 2 0 0 2 0 B (c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) (c) (c) 0 0 0 (c) (c) (c) (c) 0 (c) 0 (c) 0 (c) 0 (c) (c) 0 2 x (c) 0 2 x (c) 0 (d) 0 0 (d) Operation word (A) <-- (dir) word (A) <-- (addr16) word (A) <-- (SP) word (A) <-- (RWi) word (A) <-- (ear) word (A) <-- (eam) word (A) <-- (io) word (A) <-- ((A)) word (A) <-- imm16 word (A) <-- ((RWi)+disp8) word (A) <-- ((RLi)+disp8) word (dir) <-- (A) word (addr16) <-- (A) word (SP) <-- (A) word (RWi) <-- (A) word (ear) <-- (A) word (eam) <-- (A) word (io) <-- (A) word ((RWi)+disp8) <-- (A) word ((RLi)+disp8) <-- (A) word (RWi) <-- (ear) word (RWi) <-- (eam) word (ear) <-- (RWi) word (eam) <-- (RWi) word (RWi) <-- imm16 word (io) <-- imm16 word (ear) <-- imm16 word (eam) <-- imm16 word ((A)) <-- (AH) word (A) <--> (ear) word (A) <-- >(eam) word (RWi) <--> (ear) word (RWi) <--> (eam) long (A) <-- (ear) long (A) <-- (eam) long (A) <-- imm32 long (ear1) <-- (A) long(eam1) <-- (A) L H A H I S T N Z V C R M W - * * * * * * * * * * - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - - Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. 601 APPENDIX Table B.8-3 42 Addition/subtraction Instructions (byte, word, long word) Mnemonic ADD ADD ADD ADD ADD ADD ADDC ADDC ADDC # A,#imm8 A,dir A,ear A,eam ear,A eam,A A A,ear A,eam 2 2 2 2+ 2 2+ 1 2 2+ RG 2 5 3 4 + (a) 3 5 + (a) 2 3 4 + (a) 0 0 1 0 2 0 0 1 0 B 0 (b) 0 (b) 0 2 x (b) 0 0 (b) ADDDC A 1 3 0 0 SUB SUB SUB SUB SUB SUB SUBC SUBC SUBC A,#imm8 A,dir A,ear A,eam ear,A eam,A A A,ear A,eam 2 2 2 2+ 2 2+ 1 2 2+ 2 5 3 4 + (a) 3 5 + (a) 2 3 4 + (a) 0 0 1 0 2 0 0 1 0 0 (b) 0 (b) 0 2 x (b) 0 0 (b) SUBDC A 1 3 0 0 ADDW ADDW ADDW ADDW ADDW ADDW ADDCW ADDCW SUBW SUBW SUBW SUBW SUBW SUBW SUBCW SUBCW ADDL ADDL ADDL SUBL SUBL SUBL A A,ear A,eam A,#imm16 ear,A eam,A A,ear A,eam A A,ear A,eam A,#imm16 ear,A eam,A A,ear A,eam A,ear A,eam A,#imm32 A,ear A,eam A,#imm32 1 2 2+ 3 2 2+ 2 2+ 1 2 2+ 3 2 2+ 2 2+ 2 2+ 5 2 2+ 5 2 3 4+(a) 2 3 5+(a) 3 4+(a) 2 3 4+(a) 2 3 5+(a) 3 4+(a) 6 7+(a) 4 6 7+(a) 4 0 1 0 0 2 0 1 0 0 1 0 0 2 0 1 0 2 0 0 2 0 0 0 0 (c) 0 0 2 x (c) 0 (c) 0 0 (c) 0 0 2 x (c) 0 (c) 0 (d) 0 0 (d) 0 Operation byte (A) <-- (A) + imm8 byte (A) <-- (A) + (dir) byte (A) <-- (A) + (ear) byte (A) <-- (A) + (eam) byte (ear) <-- (ear) + (A) byte (eam) <-- (eam) + (A) byte (A) <-- (AH) + (AL) + (C) byte (A) <-- (A) + (ear)+ (C) byte (A) <-- (A) + (eam)+ (C) byte (A) <-- (AH) + (AL) + (C) (decimal) byte (A) <-- (A) - imm8 byte (A) <-- (A) - (dir) byte (A) <-- (A) - (ear) byte (A) <-- (A) - (eam) byte (ear) <-- (ear) - (A) byte (eam) <-- (eam) - (A) byte (A) <-- (AH) - (AL) - (C) byte (A) <-- (A) - (ear) - (C) byte (A) <-- (A) - (eam) - (C) byte (A) <-- (AH) - (AL) - (C) (decimal) word (A) <-- (AH) + (AL) word (A) <-- (A) + (ear) word (A) <-- (A) + (eam) word (A) <-- (A) + imm16 word (ear) <-- (ear) + (A) word (eam) <-- (eam) + (A) word (A) <-- (A) + (ear) + (C) word (A) <-- (A) + (eam) + (C) word (A) <-- (AH) - (AL) word (A) <-- (A) - (ear) word (A) <-- (A) - (eam) word (A) <-- (A) - imm16 word (ear) <-- (ear) - (A) word (eam) <-- (eam) - (A) word (A) <-- (A) - (ear) - (C) word (A) <-- (A) - (eam) - (C) long (A) <-- (A) + (ear) long (A) <-- (A) + (eam) long (A) <-- (A) + imm32 long (A) <-- (A) - (ear) long (A) <-- (A) - (eam) long (A) <-- (A) - imm32 L H A H I S T N Z V C R M W Z Z Z Z Z Z Z Z - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - Z - - - - * * * * - Z Z Z Z Z Z Z - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - Z - - - - * * * * - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. 602 APPENDIX B Instructions Table B.8-4 12 Increment/decrement Instructions (byte, word, long word) Mnemonic # RG B Operation L H A H I S T N Z V C R M W INC ear 2 3 2 0 byte (ear) <-- (ear) + 1 - - - - - * * * - - INC eam 2+ 5+(a) 0 2 x (b) byte (eam) <-- (eam) + 1 - - - - - * * * - * DEC ear 2 3 2 0 byte (ear) <-- (ear) - 1 - - - - - * * * - - DEC eam 2+ 5+(a) 0 2 x (b) byte (eam) <-- (eam) - 1 - - - - - * * * - * INCW ear 2 3 2 0 word (ear) <-- (ear) + 1 - - - - - * * * - - INCW eam 2+ 5+(a) 0 2 x (c) word (eam) <-- (eam) + 1 - - - - - * * * - * DECW ear 2 3 2 0 word (ear) <-- (ear) - 1 - - - - - * * * - - DECW eam 2+ 5+(a) 0 2 x (c) word (eam) <-- (eam) - 1 - - - - - * * * - * INCL ear 2 7 4 0 long (ear) <-- (ear) + 1 - - - - - * * * - - INCL eam 2+ 9+(a) 0 2 x (d) long (eam) <-- (eam) + 1 - - - - - * * * - * DECL ear 2 7 4 0 long (ear) <-- (ear) - 1 - - - - - * * * - - DECL eam 2+ 9+(a) 0 2 x (d) long (eam) <-- (eam) - 1 - - - - - * * * - * Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. Table B.8-5 11 Compare Instructions (byte, word, long word) Mnemonic # RG B Operation L H A H I S T N Z V C R M W CMP A 1 1 0 0 byte (AH) - (AL) - - - - - * * * * - CMP A,ear 2 2 1 0 byte (A) - (ear) - - - - - * * * * - CMP A,eam 2+ 3+(a) 0 (b) byte (A) - (eam) - - - - - * * * * - CMP A,#imm8 2 2 0 0 byte (A) - imm8 - - - - - * * * * - CMPW A 1 1 0 0 word (AH) - (AL) - - - - - * * * * - CMPW A,ear 2 2 1 0 word (A) - (ear) - - - - - * * * * - CMPW A,eam 2+ 3+(a) 0 (c) word (A) - (eam) - - - - - * * * * - CMPW A,#imm16 3 2 0 0 word (A) - imm16 - - - - - * * * * - CMPL A,ear 2 6 2 0 long (A) - (ear) - - - - - * * * * - CMPL A,eam 2+ 7+(a) 0 (d) long (A) - (eam) - - - - - * * * * - CMPL A,#imm32 5 3 0 0 long (A) - imm32 - - - - - * * * * - Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. 603 APPENDIX Table B.8-6 11 Unsigned Multiplication/division Instructions (word, long word) Mnemonic # RG B Operation L H A H I S T N Z V C R M W DIVU A 1 *1 0 0 word (AH) / byte (AL) quotient --> byte (AL) remainder --> byte (AH) - - - - - - - * * - DIVU A,ear 2 *2 1 0 word (A) / byte (ear) quotient --> byte (A) remainder --> byte (ear) - - - - - - - * * - - - - - - - - * * - DIVU A,eam 2+ *3 0 *6 word (A) / byte (eam) quotient --> byte (A) remainder --> byte (eam) DIVUW A,ear 2 *4 1 0 long (A) / word (ear) quotient --> word (A) remainder --> word (ear) - - - - - - - * * - DIVUW A,eam 2+ *5 0 *7 long (A) / word (eam) quotient --> word (A) remainder --> word (eam) - - - - - - - * * - MULU A 1 *8 0 0 byte (AH) * byte (AL) --> word (A) - - - - - - - - - - MULU A,ear 2 *9 1 0 byte (A) * byte (ear) --> word (A) - - - - - - - - - - MULU A,eam 2+ *10 0 (b) byte (A) * byte (eam) --> word (A) - - - - - - - - - - MULUW A 1 *11 0 0 word (AH) * word (AL) --> Long (A) - - - - - - - - - - MULUW A,ear 2 *12 1 0 word (A) * word (ear) --> Long (A) - - - - - - - - - - MULUW A,eam 2+ *13 0 (c) word (A) * word (eam) --> Long (A) - - - - - - - - - - *1: 3: Division by 0 7: Overflow 15: Normal *2: 4: Division by 0 8: Overflow 16: Normal *3: 6+(a): Division by 0 9+(a): Overflow 19+(a): Normal *4: 4: Division by 0 7: Overflow 22: Normal *5: 6+(a): Division by 0 8+(a): Overflow 26+(a): Normal *6: (b): Division by 0 or overflow 2 x (b): Normal *7: (c): Division by 0 or overflow 2 x (c): Normal *8: 3: Byte (AH) is 0. 7: Byte (AH) is not 0. *9: 4: Byte (ear) is 0. 8: Byte (ear) is not 0. *10: 5+(a): Byte (eam) is 0, 9+(a): Byte (eam) is not 0. *11: 3: Word (AH) is 0. 11: Word (AH) is not 0. *12: 4: Word (ear) is 0. 12: Word (ear) is not 0. *13: 5+(a): Word (eam) is 0. 13+(a): Word (eam) is not 0. Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. 604 APPENDIX B Instructions Table B.8-7 11 Signed Multiplication/division Instructions (word, long word) Mnemonic # RG B Operation L H A H I S T N Z V C R M W DIV A 2 *1 0 0 word (AH) / byte (AL) quotient --> byte (AL) remainder --> byte (AH) Z - - - - - - * * - DIV A,ear 2 *2 1 0 word (A) / byte (ear) quotient --> byte (A) remainder --> byte (ear) Z - - - - - - * * - Z - - - - - - * * - DIV A,eam 2+ *3 0 *6 word (A) / byte (eam) quotient --> byte (A) remainder --> byte (eam) DIVW A,ear 2 *4 1 0 long (A) / word (ear) quotient --> word (A) remainder --> word (ear) - - - - - - - * * - DIVW A,eam 2+ *5 0 *7 long (A) / word (eam) quotient --> word (A) remainder --> word (eam) - - - - - - - * * - MUL A 2 *8 0 0 byte (AH) * byte (AL) --> word (A) - - - - - - - - - - MUL A,ear 2 *9 1 0 byte (A) * byte (ear) --> word (A) - - - - - - - - - - MUL A,eam 2+ *10 0 (b) byte (A) * byte (eam) --> word (A) - - - - - - - - - - MULW A 2 *11 0 0 word (AH) * word (AL) --> Long (A) - - - - - - - - - - MULW A,ear 2 *12 1 0 word (A) * word (ear) --> Long (A) - - - - - - - - - - MULW A,eam 2+ *13 0 (c) word (A) * word (eam) --> Long (A) - - - - - - - - - - *1: 3: Division by 0, 8 or 18: Overflow, 18: Normal *2: 4: Division by 0, 11 or 22: Overflow, 23: Normal *3: 5+(a): Division by 0, 12+(a) or 23+(a): Overflow, 24+(a): Normal *4: When dividend is positive; 4: Division by 0, 12 or 30: Overflow, 31: Normal When dividend is negative; 4: Division by 0, 12 or 31: Overflow, 32: Normal *5: When dividend is positive; 5+(a): Division by 0, 12+(a) or 31+(a): Overflow, 32+(a): Normal When dividend is negative; 5+(a): Division by 0, 12+(a) or 32+(a): Overflow, 33+(a): Normal *6: (b): Division by 0 or overflow, 2 x (b): Normal *7: (c): Division by 0 or overflow, 2 x (c): Normal *8: 3: Byte (AH) is 0, 12: result is positive, 13: result is negative *9: 4: Byte (ear) is 0, 13: result is positive, 14: result is negative *10: 5+(a): Byte (eam) is 0, 14+(a): result is positive, 15+(a): result is negative *11: 3: Word (AH) is 0, 16: result is positive, 19: result is negative *12: 4: Word (ear) is 0, 17: result is positive, 20: result is negative *13: 5+(a): Word (eam) is 0, 18+(a): result is positive, 21+(a): result is negative Notes: • The execution cycle count found when an overflow occurs in a DIV or DIVW instruction may be a preoperation count or a post-operation count depending on the detection timing. • When an overflow occurs with DIV or DIVW instruction, the contents of the AL are destroyed. • See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. 605 APPENDIX Table B.8-8 39 Logic 1 Instructions (byte, word) Mnemonic # RG B Operation L H A H I S T N Z V C R M W AND A,#imm8 2 2 0 0 byte (A) <-- (A) and imm8 - - - - - * * R - - AND A,ear 2 3 1 0 byte (A) <-- (A) and (ear) - - - - - * * R - - AND A,eam 2+ 4+(a) 0 (b) byte (A) <-- (A) and (eam) - - - - - * * R - - AND ear,A 2 3 2 0 byte (ear) <-- (ear) and (A) - - - - - * * R - - AND eam,A 2+ 5+(a) 0 2 x (b) byte (eam) <-- (eam) and (A) - - - - - * * R - * OR A,#imm8 2 2 0 0 byte (A) <-- (A) or imm8 - - - - - * * R - - OR A,ear 2 3 1 0 byte (A) <-- (A) or (ear) - - - - - * * R - - OR A,eam 2+ 4+(a) 0 (b) byte (A) <-- (A) or (eam) - - - - - * * R - - OR ear,A 2 3 2 0 byte (ear) <-- (ear) or (A) - - - - - * * R - - OR eam,A 2+ 5+(a) 0 2 x (b) byte (eam) <-- (eam) or (A) - - - - - * * R - * XOR A,#imm8 2 2 0 0 byte (A) <-- (A) xor imm8 - - - - - * * R - - XOR A,ear 2 3 1 0 byte (A) <-- (A) xor (ear) - - - - - * * R - - XOR A,eam 2+ 4+(a) 0 (b) byte (A) <-- (A) xor (eam) - - - - - * * R - - XOR ear,A 2 3 2 0 byte (ear) <-- (ear) xor (A) - - - - - * * R - - XOR eam,A 2+ 5+(a) 0 2 x (b) byte (eam) <-- (eam) xor (A) - - - - - * * R - * NOT A 1 2 0 0 byte (A) <-- not (A) - - - - - * * R - - NOT ear 2 3 2 0 byte (ear) <-- not (ear) - - - - - * * R - - NOT eam 2+ 5+(a) 0 2 x (b) byte (eam) <-- not (eam) - - - - - * * R - * - ANDW A 1 2 0 0 word (A) <-- (AH) and (A) - - - - - * * R - ANDW A,#imm16 3 2 0 0 word (A) <-- (A) and imm16 - - - - - * * R - - ANDW A,ear 2 3 1 0 word (A) <-- (A) and (ear) - - - - - * * R - - ANDW A,eam 2+ 4+(a) 0 (c) word (A) <-- (A) and (eam) - - - - - * * R - - ANDW ear,A 2 3 2 0 word (ear) <-- (ear) and (A) - - - - - * * R - - ANDW eam,A 2+ 5+(a) 0 2 x (c) word (eam) <-- (eam) and (A) - - - - - * * R - * ORW A 1 2 0 0 word (A) <-- (AH) or (A) - - - - - * * R - - ORW A,#imm16 3 2 0 0 word (A) <-- (A) or imm16 - - - - - * * R - - ORW A,ear 2 3 1 0 word (A) <-- (A) or (ear) - - - - - * * R - - ORW A,eam 2+ 4+(a) 0 (c) word (A) <-- (A) or (eam) - - - - - * * R - - ORW ear,A 2 3 2 0 word (ear) <-- (ear) or (A) - - - - - * * R - - ORW eam,A 2+ 5+(a) 0 2 x (c) word (eam) <-- (eam) or (A) - - - - - * * R - * XORW A 1 2 0 0 word (A) <-- (AH) xor (A) - - - - - * * R - - XORW A,#imm16 3 2 0 0 word (A) <-- (A) xor imm16 - - - - - * * R - - XORW A,ear 2 3 1 0 word (A) <-- (A) xor (ear) - - - - - * * R - - XORW A,eam 2+ 4+(a) 0 (c) word (A) <-- (A) xor (eam) - - - - - * * R - - XORW ear,A 2 3 2 0 word (ear) <-- (ear) xor (A) - - - - - * * R - - XORW eam,A 2+ 5+(a) 0 2 x (c) word (eam) <-- (eam) xor (A) - - - - - * * R - * NOTW A 1 2 0 0 word (A) <-- not (A) - - - - - * * R - - NOTW ear 2 3 2 0 word (ear) <-- not (ear) - - - - - * * R - - NOTW eam 2+ 5+(a) 0 2 x (c) word (eam) <-- not (eam) - - - - - * * R - * Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. 606 APPENDIX B Instructions Table B.8-9 6 Logic 2 Instructions (long word) Mnemonic # RG B Operation L H A H I S T N Z V C R M W ANDL A,ear 2 6 2 0 long (A) <-- (A) and (ear) - - - - - * * R - - ANDL A,eam 2+ 7+(a) 0 (d) long (A) <-- (A) and (eam) - - - - - * * R - - ORL A,ear 2 6 2 0 long (A) <-- (A) or (ear) - - - - - * * R - - ORL A,eam 2+ 7+(a) 0 (d) long (A) <-- (A) or (eam) - - - - - * * R - - XORL A,ear 2 6 2 0 long (A) <-- (A) xor (ear) - - - - - * * R - - XORL A,eam 2+ 7+(a) 0 (d) long (A) <-- (A) xor (eam) - - - - - * * R - - Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. Table B.8-10 6 Sign Inversion Instructions (byte, word) Mnemonic # RG B Operation L H A H I S T N Z V C R M W NEG A 1 2 0 0 byte (A) <-- 0 - (A) X - - - - * * * * - NEG ear 2 3 2 0 byte (ear) <-- 0 - (ear) - - - - - * * * * - NEG eam 2+ 5+(a) 0 2 x (b) byte (eam) <-- 0 - (eam) - - - - - * * * * * NEGW A 1 2 0 0 word (A) <-- 0 - (A) - - - - - * * * * - NEGW ear 2 3 2 0 word (ear) <-- 0 - (ear) - - - - - * * * * - NEGW eam 2+ 5+(a) 0 2 x (c) word (eam) <-- 0 - (eam) - - - - - * * * * * Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. Table B.8-11 1 Normalization Instruction (long word) Mnemonic NRML A,R0 # 2 RG *1 1 B 0 Operation long (A) <-- Shifts to the position where '1' is set for the first time. byte (RD) <-- Shift count at that time L H A H I S T N Z V C R M W - - - - - - * - - - *1: 4 when all accumulators have a value of 0; otherwise, 6+(R0) 607 APPENDIX Table B.8-12 18 Shift Instructions (byte, word, long word) Mnemonic # RG B Operation L H A H I S T N Z V C R M W RORC A 2 2 0 0 byte (A) <-- With right rotation carry - - - - - * * - * - ROLC A 2 2 0 0 byte (A) <-- With left rotation carry - - - - - * * - * - RORC ear 2 3 2 0 byte (ear) <-- With right rotation carry - - - - - * * - * - RORC eam 2+ 5+(a) 0 2 x (b) byte (eam) <-- With right rotation carry - - - - - * * - * * ROLC ear 2 3 2 0 byte (ear) <-- With left rotation carry - - - - - * * - * - ROLC eam 2+ 5+(a) 0 2 x (b) byte (eam) <-- With left rotation carry - - - - - * * - * * ASR A,R0 2 *1 1 0 byte (A) <-- Arithmetic right shift (A, 1 bit) - - - - - * * - * - LSR A,R0 2 *1 1 0 byte (A) <-- Logical right barrel shift (A, R0) - - - - - * * - * - LSL A,R0 2 *1 1 0 byte (A) <-- Logical left barrel shift (A, R0) - - - - - * * - * - ASRW A 1 2 0 0 word (A) <-- Arithmetic right shift (A, 1 bit) - - - - * * * - * - LSRW A/SHRW A 1 2 0 0 word (A) <-- Logical right shift (A, 1 bit) - - - - * R * - * - LSLW A/SHLW A 1 2 0 0 word (A) <-- Logical left shift (A, 1 bit) - - - - - * * - * ASRW A,R0 2 *1 1 0 word (A) <-- Arithmetic right barrel shift (A, R0) - - - - * * * - * - LSRW A,R0 2 *1 1 0 word (A) <-- Logical right barrel shift (A, R0) - - - - * * * - * - LSLW A,R0 2 *1 1 0 word (A) <-- Logical left barrel shift (A, R0) - - - - - * * - * - ASRL A,R0 2 *2 1 0 long (A) <-- Arithmetic right barrel shift (A, R0) - - - - * * * - * - LSRL A,R0 2 *2 1 0 long (A) <-- Logical right barrel shift (A, R0) - - - - * * * - * - LSLL A,R0 2 *2 1 0 long (A) <-- Logical left barrel shift (A, R0) - - - - - * * - * - *1: 6 when R0 is 0; otherwise, 5 + (R0) *2: 6 when R0 is 0; otherwise, 6 + (R0) Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. 608 APPENDIX B Instructions Table B.8-13 31 Branch 1 Instructions Mnemonic # RG B Operation L H A H I S T N Z V C R M W BZ/BEQ rel 2 *1 0 0 Branch on (Z) = 1 - - - - - - - - - - BNZ/BNE rel 2 *1 0 0 Branch on (Z) = 0 - - - - - - - - - - BC/BLO rel 2 *1 0 0 Branch on (C) = 1 - - - - - - - - - - BNC/BHS rel 2 *1 0 0 Branch on (C) = 0 - - - - - - - - - - BN rel 2 *1 0 0 Branch on (N) = 1 - - - - - - - - - - BP rel 2 *1 0 0 Branch on (N) = 0 - - - - - - - - - - BV rel 2 *1 0 0 Branch on (V) = 1 - - - - - - - - - - BNV rel 2 *1 0 0 Branch on (V) = 0 - - - - - - - - - - BT rel 2 *1 0 0 Branch on (T) = 1 - - - - - - - - - - BNT rel 2 *1 0 0 Branch on (T) = 0 - - - - - - - - - - BLT rel 2 *1 0 0 Branch on (V) nor (N) = 1 - - - - - - - - - - BGE rel 2 *1 0 0 Branch on (V) nor (N) = 0 - - - - - - - - - - BLE rel 2 *1 0 0 Branch on ((V) xor (N)) or (Z) = 1 - - - - - - - - - - BGT rel 2 *1 0 0 Branch on ((V) xor (N)) or (Z) = 0 - - - - - - - - - - BLS rel 2 *1 0 0 Branch on (C) or (Z) = 1 - - - - - - - - - - BHI rel 2 *1 0 0 Branch on (C) or (Z) = 0 - - - - - - - - - - BRA rel 2 *1 0 0 Unconditional branch - - - - - - - - - - JMP @A 1 2 0 0 word (PC) <-- (A) - - - - - - - - - - JMP addr16 3 3 0 0 word (PC) <-- addr16 - - - - - - - - - - JMP @ear 2 3 1 0 word (PC) <-- (ear) - - - - - - - - - - JMP @eam 2+ 4+(a) 0 (c) word (PC) <-- (eam) - - - - - - - - - - JMPP @ear *3 2 5 2 0 word (PC) <-- (ear), (PCB) <-- (ear+2) - - - - - - - - - - JMPP @eam *3 2+ 6+(a) 0 (d) word (PC) <-- (eam), (PCB) <-- (eam+2) - - - - - - - - - - JMPP addr24 4 4 0 0 word (PC) <-- ad24 0-15, (PCB) <-- ad24 16-23 - - - - - - - - - - CALL @ear *4 2 6 1 (c) word (PC) <-- (ear) - - - - - - - - - - CALL addr16 *5 2+ 7+(a) 0 2 x (c) word (PC) <-- (eam) - - - - - - - - - - CALL @eam *4 3 6 0 (c) word (PC) <-- addr16 - - - - - - - - - - CALLV #vct4 *5 1 7 0 2 x (c) Vector call instruction - - - - - - - - - - CALLP @ear *6 2 10 2 2 x (c) word (PC) <-- (ear)0-15, (PCB) <-- (ear)16-23 - - - - - - - - - - CALLP @eam *6 2+ 11+(a) 0 *2 word (PC) <-- (eam)0-15, (PCB) <-- (eam)16-23 - - - - - - - - - - CALLP addr24 *7 4 10 0 2 x (c) word (PC) <-- addr0-15, (PCB) <-- addr16-23 - - - - - - - - - - *1: 4 when a branch is made; otherwise, 3 *2: 3 x (c) + (b) *3: Read (word) of branch destination address *4: W: Save to stack (word) R: Read (word) of branch destination address *5: Save to stack (word) *6: W: Save to stack (long word), R: Read (long word) of branch destination address *7: Save to stack (long word) Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. 609 APPENDIX Table B.8-14 19 Branch 2 Instructions Mnemonic # RG B Operation L A H H I S T N Z V C R M W CBNE A,#imm8,rel 3 *1 0 0 Branch on byte (A) not equal to imm8 - - - - - * * * * - CWBNE A,#imm16,rel 4 *1 0 0 Branch on word (A) not equal to imm16 - - - - - * * * * - CBNE ear,#imm8,rel 4 *2 1 0 Branch on byte (ear) not equal to imm8 - - - - - * * * * - CBNE eam,#imm8,rel *9 4+ *3 0 (b) Branch on byte (eam) not equal to imm8 - - - - - * * * * - CWBNE ear,#imm16,rel 5 *4 1 0 Branch on word (ear) not equal to imm16 - - - - - * * * * - CWBNE eam,#imm16,rel*9 5+ *3 0 (c) Branch on word (eam) not equal to imm16 - - - - - * * * * - DBNZ ear,rel 3 *5 2 0 Branch on byte (ear) = (ear) - 1, (ear) not equal to 0 - - - - - * * * - - DBNZ eam,rel 3+ *6 2 2 x (b) Branch on byte (eam) = (eam) - 1, (eam) not equal to 0 - - - - - * * * - * DWBNZ ear,rel 3 *5 2 0 Branch on word (ear) = (ear) - 1, (ear) not equal to 0 - - - - - * * * - - DWBNZ eam,rel 3+ *6 2 2 x (c) Branch on word (eam) = (eam) - 1, (eam) not equal to 0 - - - - - * * * - * INT #vct8 2 20 0 8 x (c) Software interrupt - - R S - - - - - - INT addr16 3 16 0 6 x (c) Software interrupt - - R S - - - - - - INTP addr24 4 17 0 6 x (c) Software interrupt - - R S - - - - - - INT9 1 20 0 8 x (c) Software interrupt - - R S - - - - - - RETI 1 *8 0 *7 Return from interrupt - - * * * * * * * - - - - - - - - - - - - - - - - - - - - - LINK #imm8 UNLINK 2 6 0 (c) Saves the old frame pointer in the stack upon entering the function, then sets the new frame pointer and reserves the local pointer area. 1 5 0 (c) Recovers the old frame pointer from the stack upon exiting the function. RET *10 1 4 0 (c) Return from subroutine - - - - - - - - - - RETP *11 1 6 0 (d) Return from subroutine - - - - - - - - - - *1: 5 when a branch is made; otherwise, 4 *2: 13 when a branch is made; otherwise, 12 *3: 7+(a) when a branch is made; otherwise, 6+(a) *4: 8 when a branch is made; otherwise, 7 *5: 7 when a branch is made; otherwise, 6 *6: 8+(a) when a branch is made; otherwise, 7+(a) *7: 3 x (b) + 2 x (c) when jumping to the next interruption request; 6 x (c) when returning from the current interruption *8: 15 when jumping to the next interruption request; 17 when returning from the current interruption *9: Do not use RWj+ addressing mode with a CBNE or CWBNE instruction. *10: Return from stack (word) *11: Return from stack (long word) Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. 610 APPENDIX B Instructions Table B.8-15 28 Other Control Instructions (byte, word, long word) Mnemonic # RG B Operation L H A H I S T N Z V C R M W PUSHW A 1 4 0 (c) word (SP) <-- (SP) - 2, ((SP)) <-- (A) - - - - - - - - - - PUSHW AH 1 4 0 (c) word (SP) <-- (SP) - 2, ((SP)) <-- (AH) - - - - - - - - - - PUSHW PS 1 4 0 (c) word (SP) <-- (SP) - 2, ((SP)) <-- (PS) - - - - - - - - - - PUSHW rlst 2 *3 *5 *4 (SP) <-- (SP) - 2n, ((SP)) <-- (rlst) - - - - - - - - - - POPW A 1 3 0 (c) word (A) <-- ((SP)), (SP) <-- (SP) + 2 - * - - - - - - - - POPW AH 1 3 0 (c) word (AH) <-- ((SP)), (SP) <-- (SP) + 2 - - - - - - - - - - POPW PS 1 4 0 (c) word (PS) <-- ((SP)), (SP) <-- (SP) + 2 - - * * * * * * * - POPW rlst 2 *2 *5 *4 (rlst) <-- ((SP)), (SP) <-- (SP) - - - - - - - - - - JCTX @A 1 14 0 6 x (c) Context switch instruction - - * * * * * * * - AND CCR,#imm8 2 3 0 0 byte (CCR) <-- (CCR) and imm8 - - * * * * * * * - OR CCR,#imm8 2 3 0 0 byte (CCR) <-- (CCR) or imm8 - - * * * * * * * - MOV RP,#imm8 2 2 0 0 byte (RP) <-- imm8 - - - - - - - - - - MOV ILM,#imm8 2 2 0 0 byte (ILM) <-- imm8 - - - - - - - - - - MOVEA RWi,ear 2 3 1 0 word (RWi) <-- ear - - - - - - - - - - MOVEA RWi,eam 2+ 2+(a) 1 0 word (RWi) <-- eam - - - - - - - - - - MOVEA A,ear 2 1 0 0 word (A) <-- ear - * - - - - - - - - MOVEA A,eam 2+ 1+(a) 0 0 word (A) <-- eam - * - - - - - - - - ADDSP #imm8 2 3 0 0 word (SP) <-- ext(imm8) - - - - - - - - - - ADDSP #imm16 3 3 0 0 word (SP) <-- imm16 - - - - - - - - - - MOV A,brg1 2 *1 0 0 byte (A) <-- (brg1) Z * - - - * * - - - MOV brg2,A 2 1 0 0 byte (brg2) <-- (A) - - - - - * * - - - NOP 1 1 0 0 No operation - - - - - - - - - - ADB 1 1 0 0 Prefix code for AD space access - - - - - - - - - - DTB 1 1 0 0 Prefix code for DT space access - - - - - - - - - - PCB 1 1 0 0 Prefix code for PC space access - - - - - - - - - - SPB 1 1 0 0 Prefix code for SP space access - - - - - - - - - - NCC 1 1 0 0 Prefix code for flag no-change - - - - - - - - - - CMR 1 1 0 0 Prefix code for common register bank - - - - - - - - - - *1: PCB, ADB, SSB, USB, SPB: 1, DTB, DPR: 2 *2: 7 + 3 x (POP count) + 2 x (POP last register number), 7 when RLST = 0 (no transfer register) *3: 29 + 3 x (PUSH count) - 3 x (PUSH last register number), 8 when RLST = 0 (no transfer register) *4: (POP count) x (c) or (PUSH count) x (c) *5: (POP count) or (PUSH count) Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. 611 APPENDIX Table B.8-16 21 Bit Operand Instructions Mnemonic # RG B Operation L H A H I S T N Z V C R M W MOVB A,dir:bp 3 5 0 (b) byte (A) <-- (dir:bp)b Z * - - - * * - - - MOVB A,addr16:bp 4 5 0 (b) byte (A) <-- (addr16:bp)b Z * - - - * * - - - MOVB A,io:bp 3 4 0 (b) byte (A) <-- (io:bp)b Z * - - - * * - - - MOVB dir:bp,A 3 7 0 2 x (b) bit (dir:bp)b <-- (A) - - - - - * * - - * MOVB addr16:bp,A 4 7 0 2 x (b) bit (addr16:bp)b <-- (A) - - - - - * * - - * MOVB io:bp,A 3 6 0 2 x (b) bit (io:bp)b <-- (A) - - - - - * * - - * SETB dir:bp 3 7 0 2 x (b) bit (dir:bp)b <-- 1 - - - - - - - - - * SETB addr16:bp 4 7 0 2 x (b) bit (addr16:bp)b <-- 1 - - - - - - - - - * SETB io:bp 3 7 0 2 x (b) bit (io:bp)b <-- 1 - - - - - - - - - * CLRB dir:bp 3 7 0 2 x (b) bit (dir:bp)b <-- 0 - - - - - - - - - * CLRB addr16:bp 4 7 0 2 x (b) bit (addr16:bp)b <-- 0 - - - - - - - - - * CLRB io:bp 3 7 0 2 x (b) bit (io:bp)b <-- 0 - - - - - - - - - * BBC dir:bp,rel 4 *1 0 (b) Branch on (dir:bp) b = 0 - - - - - - * - - - BBC addr16:bp,rel 5 *1 0 (b) Branch on (addr16:bp) b = 0 - - - - - - * - - - BBC io:bp,rel 4 *2 0 (b) Branch on (io:bp) b = 0 - - - - - - * - - - BBS dir:bp,rel 4 *1 0 (b) Branch on (dir:bp) b = 1 - - - - - - * - - - BBS addr16:bp,rel 5 *1 0 (b) Branch on (addr16:bp) b = 1 - - - - - - * - - - BBS io:bp,rel 4 *1 0 (b) Branch on (io:bp) b = 1 - - - - - - * - - - SBBS addr16:bp,rel 5 *3 0 2 x (b) Branch on (addr16:bp) b = 1, bit = 1 - - - - - - * - - * WBTS io:bp 3 *4 0 *5 Waits until (io:bp) b = 1 - - - - - - - - - - WBTC io:bp 3 *4 0 *5 Waits until (io:bp) b = 0 - - - - - - - - - - I S T N Z V C R M W *1: 8 when a branch is made; otherwise, 7 *2: 7 when a branch is made; otherwise, 6 *3: 10 when the condition is met; otherwise, 9 *4: Undefined count *5: Until the condition is met Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. Table B.8-17 6 Accumulator Operation Instructions (byte, word) Mnemonic # RG B Operation L H A H SWAP 1 3 0 0 byte (A)0-7 <--> (A)8-15 - - - - - - - - - - SWAPW 1 2 0 0 word (AH) <--> (AL) - * - - - - - - - - EXT 1 1 0 0 Byte sign extension X - - - - * * - - - EXTW 1 2 0 0 Word sign extension - X - - - * * - - - ZEXT 1 1 0 0 Byte zero extension Z - - - - R * - - - ZEXTW 1 1 0 0 Word zero extension - z - - - R * - - - 612 APPENDIX B Instructions Table B.8-18 10 String Instructions Mnemonic # RG B Operation L H A H I S T N Z V C R M W MOVS / MOVSI 2 *2 *5 *3 byte transfer @AH+ <-- @AL+, counter = RW0 - - - - - - - - - - MOVSD 2 *2 *5 *3 byte transfer @AH- <-- @AL-, counter = RW0 - - - - - - - - - - SCEQ / SCEQI 2 *1 *5 *4 byte search @AH+ <-- AL, counter RW0 - - - - - * * * * - SCEQD 2 *1 *5 *4 byte search @AH- <-- AL, counter RW0 - - - - - * * * * - FILS / FILSI 2 6m+6 *5 *3 byte fill @AH+ <-- AL, counter RW0 - - - - - * * - - - MOVSW / MOVSWI 2 *2 *5 *6 word transfer @AH+ <-- @AL+, counter = RW0 - - - - - - - - - - MOVSWD 2 *2 *5 *6 word transfer @AH- <-- @AL-, counter = RW0 - - - - - - - - - - SCWEQ / SCWEQI 2 *1 *5 *7 word search @AH+ - AL, counter = RW0 - - - - - * * * * - SCWEQD 2 *1 *5 *7 word search @AH- - AL, counter = RW0 - - - - - * * * * - FILSW / FILSWI 2 6m+6 *5 *6 word fill @AH+ <-- AL, counter = RW0 - - - - - * * - - - *1: 5 when RW0 is 0, 4 + 7 x (RW0) when the counter expires, or 7n + 5 when a match occurs *2: 5 when RW0 is 0; otherwise, 4 + 8 x (RW0) *3: (b) x (RW0) + (b) x (RW0) When the source and destination access different areas, calculate the (b) item individually. *4: (b) x n *5: 2 x (RW0) *6: (c) x (RW0) + (c) x (RW0) When the source and destination access different areas, calculate the (c) item individually. *7: (c) x n Note: m: RW0 value (counter value), n: Loop count See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. 613 APPENDIX B.9 Instruction Map Each F2MC-16LX instruction code consists of 1 or 2 bytes. Therefore, the instruction map consists of multiple pages. Table B.9-2 to Table B.9-21 summarize the F2MC-16LX instruction map. ■ Structure of Instruction Map Figure B.9-1 Structure of Instruction Map Basic page map : Byte 1 Bit operation instructions Character string operation instructions 2-byte instructions ea instructions x 9 : Byte 2 An instruction such as the NOP instruction that ends in one byte is completed within the basic page. An instruction such as the MOVS instruction that requires two bytes recognizes the existence of byte 2 when it references byte 1, and can check the following one byte by referencing the map for byte 2. Figure B.9-2 shows the correspondence between an actual instruction code and instruction map. 614 APPENDIX B Instructions Figure B.9-2 Correspondence between Actual Instruction Code and Instruction Map Some instructions do not contain byte 2. Length varies depending on the instruction. Instruction code Byte 1 Byte 2 Operand Operand ... [Basic page map] XY +Z [Extended page map] (*1) UV +W *1 The extended page map is a generic name of maps for bit operation instructions, character string operation instructions, 2-byte instructions, and ea instructions. Actually, there are multiple extended page maps for each type of instructions. An example of an instruction code is shown in Table B.9-1 . Table B.9-1 Example of an Instruction Code Byte 1 (from basic page map) Byte 2 (from extended page map) NOP 00 +0=00 - AND A, #8 30 +4=34 - MOV A, ADB 60 +F=6F 00 +0=00 @RW2+d8, #8rel 70 +0=70 F0 +2=F2 Instruction 615 616 2-byte instruction Character string operation instruction Bit operation instruction Ri,ea ea instruction 9 ea instruction 8 ea instruction 7 ea instruction 6 ea instruction 5 ea instruction 4 ea instruction 3 ea instruction 2 ea instruction 1 APPENDIX Table B.9-2 Basic Page Map APPENDIX B Instructions Table B.9-3 Bit Operation Instruction Map (first byte = 6CH) 617 APPENDIX Table B.9-4 Character String Operation Instruction Map (first byte = 6EH) 618 APPENDIX B Instructions A A DIVU MULW MUL A Table B.9-5 2-byte Instruction Map (first byte = 6FH) 619 620 Use prohibited Use prohibited Use prohibited Use prohibited Use prohibited Use prohibited Use prohibited Use prohibited APPENDIX Table B.9-6 ea Instruction 1 (first byte = 70H) APPENDIX B Instructions Table B.9-7 ea Instruction 2 (first byte = 71H) 621 APPENDIX Table B.9-8 ea Instruction 3 (first byte = 72H) 622 APPENDIX B Instructions Table B.9-9 ea Instruction 4 (first byte = 73H) 623 APPENDIX Table B.9-10 ea Instruction 5 (first byte = 74H) 624 APPENDIX B Instructions Table B.9-11 ea Instruction 6 (first byte = 75H) 625 APPENDIX Table B.9-12 ea Instruction 7 (first byte = 76H) 626 APPENDIX B Instructions Table B.9-13 ea Instruction 8 (first byte = 77H) 627 APPENDIX Table B.9-14 ea Instruction 9 (first byte = 78H) 628 APPENDIX B Instructions Table B.9-15 MOVEA RWi, ea Instruction (first byte = 79H) 629 APPENDIX Table B.9-16 MOV Ri, ea Instruction (first byte = 7AH) 630 APPENDIX B Instructions Table B.9-17 MOVW RWi, ea Instruction (first byte = 7BH) 631 APPENDIX Table B.9-18 MOV Ri, ea Instruction (first byte = 7CH) 632 APPENDIX B Instructions Table B.9-19 MOVW ea, Rwi Instruction (first byte = 7DH) 633 APPENDIX Table B.9-20 XCH Ri, ea Instruction (first byte = 7EH) 634 APPENDIX B Instructions Table B.9-21 XCHW RWi, ea Instruction (first byte = 7FH) 635 APPENDIX APPENDIX C Timing Diagrams in Flash Memory Mode Each timing diagram for the external pins of the Flash devices in MB90360 series during Flash Memory mode is shown below. ■ Data Read by Read Access Figure C-1 Timing Diagram for Read Access tRC AQ16 to AQ0 Address stable tACC CE tDF tOE OE tOEH WE tOH tCE DQ7 to DQ0 636 High-Z Output defined APPENDIX C Timing Diagrams in Flash Memory Mode ■ Write, Data Polling, Read (WE control) Figure C-2 Write, Data Polling, Read (WE control) Data polling 3rd bus cycle AQ18 to AQ0 FxAAAAH PA tAS tWC PA tAH tRC CE tCH tCS tCE OE tWP tWHWH1 tOE tGHWL WE tWPH tDS tDH DQ7 to DQ0 PA PD DQ7 DOUT A0H tDF PD DQ7 DOUT tOH DOUT : Write address : Write data : Reverse output of write data : Output of write data Note: • Describes the last 2-bus cycle of 4-bus cycle sequences. • "Fx" in "FxAAAA" described as address is any of FF. 637 APPENDIX ■ Write, Data Polling, Read (CE control) Figure C-3 Timing Diagram for Write Access (CE control) 3rd bus cycle AQ18 to AQ0 Data polling PA FxAAAAH tWC tAS PA tAH tWH WE tGHWL OE tCP tWHWH1 CE tCPH tWS tDH A0H DQ7 to DQ0 PD tDS PA PD DQ7 DOUT : Write address : Write data : Reverse output of write data : Output of write data Note: • Describes the last 2-bus cycle of 4-bus cycle sequences. • "Fx" in "FxAAAA" described as address is any of F. 638 DQ7 Dout APPENDIX C Timing Diagrams in Flash Memory Mode ■ Chip Erase/sector Erase Command Sequence Figure C-4 Timing Diagram for Write Access (chip erasing/sector erasing) tAS AQ18 to AQ0 FxAAAAH tAH Fx5555H FxAAAAH FxAAAAH SA* Fx5555H CE tGHWL OE tWP WE tWPH tCS tDH AAH DQ7 to DQ0 55H 80H AAH 55H 10H/30H tDS VCC tVCS Notes: • SA is the sector address at erasing sector. • The address is FxAAAAH at erasing sector. • "Fx" in "FxAAAA" described as address is any of F. 639 APPENDIX ■ Data Polling Figure C-5 Timing Diagram for Data Polling tCH CE tOE tDF OE tOEH WE tCE DQ7 tOH DQ7 = valid data DQ7 High-Z tWHWH1 or tWHWH2 DQ6 to DQ0 DQ6 to DQ0 flag output DQ6 to DQ0 = valid data tOE Note: DQ7 is valid data (The device terminates automatic operation). ■ Toggle Bit Figure C-6 Timing Diagram for Toggle Bit CE tOEH WE tOES OE Data (DQ7 to DQ0) DQ6 = Toggle DQ6 = Stop toggling DQ6 = Toggle tOE Note: DQ6 stops toggling (The device terminates automatic operation). 640 DQ7 to DQ0 = valid APPENDIX C Timing Diagrams in Flash Memory Mode ■ RY/BY Timing during Writing/erasing Figure C-7 Timing Diagram for Output of RY/BY Signal during Writing/erasing CE Rising edge of last write pulse WE Writing or erasing RY/BY tBUSY ■ RST and RY/BY Timing Figure C-8 Timing Diagram for Output of RY/BY Signal at Hardware Reset CE RY/BY tRP RST tReady 641 APPENDIX ■ Enable Sector Protect/verify Sector Protect Figure C-9 Enable Sector Protect/verify Sector Protect AQ18 to AQ9 SAX SAY (AQ8, AQ2, AQ1) = (0, 1, 0) AQ8, AQ2, AQ1 MD0 12 V 5V MD2 12 V 5V tVLHT tVLHT OE tWPP WE tOESP tCSP CE DQ7 to DQ0 01H tOE SAX: First sector address SAY: Next sector address 642 APPENDIX C Timing Diagrams in Flash Memory Mode ■ Temporary Sector Protect Cancellation Figure C-10 Temporary Sector Protect Cancellation MD1 12 V 5V 5V CE WE tVLHT Write/erase command sequence RY/BY 643 APPENDIX APPENDIX D List of Interrupt Vectors The interrupt vector table to be referenced for interrupt processing is allocated to FFFC00H to FFFFFFH in the memory area and also used for software interrupts. ■ List of Interrupt Vectors Table D-1 lists the interrupt vectors for the MB90360 series. Table D-1 Interrupt Vectors (1/2) Interrupt request Interrupt cause Interrupt control register Vector address Vector address Vector address Mode register L H bank Number Address INT 1* -- -- -- FFFFFCH FFFFFDH FFFFFEH Unused INT 2* -- -- -- FFFFF8H FFFFF9H FFFFFAH Unused . . . -- -- -- INT 7* -- -- -- FFFFE0H FFFFE1H FFFFE2H Unused INT 8 Reset -- -- FFFFDCH FFFFDDH FFFFDEH FFFFDFH INT 9 INT9 instruction -- -- FFFFD8H FFFFD9H FFFFDAH Unused INT 10 Exception -- -- FFFFD4H FFFFD5H FFFFD6H Unused INT 11 Reserved 0000B0H FFFFD0H FFFFD1H FFFFD2H Unused ICR00 FFFFCCH FFFFCDH FFFFCEH Unused FFFFC8H FFFFC9H FFFFCAH Unused FFFFC4H FFFFC5H FFFFC6H Unused FFFFC0H FFFFC1H FFFFC2H Unused FFFFBCH FFFFBDH FFFFBEH Unused FFFFB8H FFFFB9H FFFFBAH Unused FFFFB4H FFFFB5H FFFFB6H Unused FFFFB0H FFFFB1H FFFFB2H Unused FFFFACH FFFFADH FFFFAEH Unused FFFFA8H FFFFA9H FFFFAAH Unused FFFFA4H FFFFA5H FFFFA6H Unused FFFFA0H FFFFA1H FFFFA2H Unused FFFF9CH FFFF9DH FFFF9EH Unused FFFF98H FFFF99H FFFF9AH Unused FFFF94H FFFF95H FFFF96H Unused FFFF90H FFFF91H FFFF92H Unused FFFF8CH FFFF8DH FFFF8EH Unused FFFF88H FFFF89H FFFF8AH Unused FFFF84H FFFF85H FFFF86H Unused INT 12 Reserved INT 13 CAN1 RX ICR01 INT 14 INT 15 CAN1 TX/NS Reserved ICR02 INT 16 Reserved INT 17 Reserved ICR03 INT 18 Reserved INT 19 16-bit reloadtimer2 ICR04 INT 20 16-bit reloadtimer3 INT 21 Reserved ICR05 INT 22 Reserved INT 23 PPG C/D ICR06 INT 24 PPG E/F INT 25 Time base timer ICR07 INT 26 External interrupt 8 to 11 INT 27 Watch Timer ICR08 INT 28 External interrupt 12 to 15 INT 29 A/D Converter ICR09 INT 30 644 I/O Timer 0 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H . . . . . . . . . . . . APPENDIX D List of Interrupt Vectors Table D-1 Interrupt Vectors (2/2) Interrupt request INT 31 Interrupt cause Interrupt control register Vector address Vector address Vector address Mode register L H bank Number Address Reserved ICR10 INT 32 Reserved INT 33 Input capture 0 to 3 ICR11 INT 34 Reserved INT 35 UART 0 RX ICR12 INT 36 UART 0 TX INT 37 UART 1 RX ICR13 INT 38 UART 1 TX INT 39 Reserved ICR14 INT 40 Reserved INT 41 Flash Memory ICR15 0000BAH 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH FFFF80H FFFF81H FFFF82H Unused FFFF7CH FFFF7DH FFFF7EH Unused FFFF78H FFFF79H FFFF7AH Unused FFFF74H FFFF75H FFFF76H Unused FFFF70H FFFF71H FFFF72H Unused FFFF6CH FFFF6DH FFFF6EH Unused FFFF68H FFFF69H FFFF6AH Unused FFFF64H FFFF65H FFFF66H Unused FFFF60H FFFF61H FFFF62H Unused FFFF5CH FFFF5DH FFFF5EH Unused FFFF58H FFFF59H FFFF5AH Unused FFFF54H FFFF55H FFFF56H Unused FFFF50H FFFF51H FFFF52H Unused INT 42 Delayed interrupt module INT 43 -- -- -- . . . -- -- -- INT 254 -- -- -- FFFC04H FFFC05H FFFC06H Unused INT 255 -- -- -- FFFC00H FFFC01H FFFC02H Unused . . . . . . . . . . . . *: When PCB is FFH, the vector area for the CALLV instruction is the same as that for INT #vct8 (#0 to #7). Care must be taken when using the vector for the CALLV instruction. 645 APPENDIX ■ Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers Table D-2 summarizes the relationships among the interrupt causes, interrupt vectors, and interrupt control registers of the MB90360 series. Table D-2 Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers (1/2) Interrupt cause EI2OS clear DMA channel number Interrupt vector Interrupt control register Number ICR Address Reset N #08 FFFFDCH - - INT9 instruction N #09 FFFFD8H - - Exception N #10 FFFFD4H - - Reserved N #11 FFFFD0H ICR00 N #12 FFFFCCH 0000B0H Reserved CAN 1 RX N #13 FFFFC8H ICR01 N #14 FFFFC4H 0000B1H CAN 1 TX/NS Reserved N #15 FFFFC0H ICR02 N #16 FFFFBCH 0000B2H Reserved Reserved N #17 FFFFB8H ICR03 N #18 FFFFB4H 0000B3H Reserved 16-bit reload timer 2 Y1 #19 FFFFB0H ICR04 Y1 #20 FFFFACH 0000B4H 16-bit reload timer 3 Reserved N #21 FFFFA8H ICR05 N #22 FFFFA4H 0000B5H Reserved PPG C/D N #23 FFFFA0H ICR06 N #24 FFFF9CH 0000B6H PPG E/F Time base timer N #25 FFFF98H ICR07 Y1 #26 FFFF94H 0000B7H External interrupt 8 to 11 Watch timer N #27 FFFF90H ICR08 Y1 #28 FFFF8CH 0000B8H External interrupt 12 to 15 A/D converter Y1 #29 FFFF88H ICR09 N #30 FFFF84H 0000B9H I/O timer 0 Reserved N #31 FFFF80H ICR10 N #32 FFFF7CH 0000BAH Reserved Input capture 0 to 3 Y1 #33 FFFF78H ICR11 N #34 FFFF74H 0000BBH Reserved UART 0 RX Y2 #35 FFFF70H ICR12 Y1 #36 FFFF6CH 0000BCH UART 0 TX 646 APPENDIX D List of Interrupt Vectors Table D-2 Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers (2/2) Interrupt cause EI2OS clear DMA channel number Interrupt vector Number UART 1 RX Y2 #37 FFFF68H UART 1 TX Y1 #38 FFFF64H Reserved N #39 FFFF60H Reserved N #40 FFFF5CH Flash memory N #41 FFFF58H Delayed interrupt generation module N #42 FFFF54H Interrupt control register ICR Address ICR13 0000BDH ICR14 0000BEH ICR15 0000BFH Y1: An EI2OS interrupt clear signal or EI2OS register read access clears the interrupt request flag. Y2: An EI2OS interrupt clear signal or EI2OS register read access clears the interrupt request flag. A stop request is issued. N: An EI2OS interrupt clear signal does not clear the interrupt request flag. Note: For a peripheral module having two interrupt causes for one interrupt number, an EI2OS interrupt clear signal clears both interrupt request flags. When EI2OS ends, an EI2OS clear signal is sent to every interrupt flag assigned to each interrupt number. EI2OS is activated when one of two interrupts assigned to an interrupt control register (ICR) is caused while EI2OS is enabled. This means that an EI2OS descriptor that should essentially be specific to each interrupt cause is shared by two interrupts. Therefore, while one interrupt is enabled, the other interrupt must be disabled. 647 APPENDIX 648 INDEX INDEX The index follows on the next page. This is listed in alphabetic order. 649 INDEX Index Numerics 16-bit Free-run Timer Block Diagram of 16-bit Free-run Timer ............213 Explanation of Operation of 16-bit Free-run Timer .......................................................... 229 16-bit I/O Timer 16-bit I/O Timer Interrupt and EI2OS ................. 228 Block Diagram of 16-bit I/O Timer .................... 211 Functions of 16-bit I/O Timer............................ 210 Generation of Interrupt Request from 16-bit I/O Timer .......................................................... 216 Interrupts of 16-bit I/O Timer ............................ 227 Module Configuration of 16-bit I/O Timer.......... 210 Pins of 16-bit I/O Timer.................................... 216 Precautions when Using 16-bit I/O Timer ........... 233 Program Example of 16-bit I/O Timer ................ 234 16-bit PPG Output Operation Mode Setting for 16-bit PPG Output Operation Mode .......................................................... 304 16-bit Reload Registers 16-bit Reload Registers (TMRLR) ..................... 250 16-bit Reload Timer 16-bit Reload Timer Registers and Reset Value .......................................................... 243 Block Diagram of 16-bit Reload Timer............... 240 Correspondence between 16-bit Reload Timer Interrupt and EI2OS............................. 251 2 EI OS Function of 16-bit Reload Timer.............. 251 Generation of Interrupt Request from 16-bit Reload Timer ......................................244 Interrupts of 16-bit Reload Timer....................... 251 Operation Modes of 16-bit Reload Timer............238 Pins of 16-bit Reload Timer .............................. 242 Precautions when Using 16-bit Reload Timer......262 Setting of 16-bit Reload Timer .......................... 252 16-bit Timer Register 16-bit Timer Registers (TMR) ........................... 249 Operating State of 16-bit Timer Register ............253 Operation as 16-bit Timer Register Underflows .................................................. 255, 260 650 24-bit Operand 24-bit Operand Specification............................... 33 512K-bit Flash Memory 512K-bit Flash Memory Features ...................... 530 Sector Configuration of the 512K-bit Flash Memory ......................................................... 531 8+8-bit PPG Setting for 8+8-bit PPG Output Operation Mode ......................................................... 307 8-/10-bit A/D Converter 8-/10-bit A/D Converter Interrupt and EI2OS...... 358 A/D-converted Data Protection Function in 8-/10-bit A/D Converter....................... 367 Block Diagram of 8-/10-bit A/D Converter......... 341 Conversion Modes of 8-/10-bit A/D Converter ......................................................... 340 EI2OS Function of 8-/10-bit A/D Converter........ 358 Function of 8-/10-bit A/D Converter.................. 340 Generation of Interrupt from 8-/10-bit A/D Converter ......................................................... 345 List of Registers and Reset Values of 8-/10-bit A/D Converter .................................... 345 Pins of 8-/10-bit A/D Converter ........................ 344 Precautions when Using 8-/10-bit A/D Converter ......................................................... 369 8-/16-bit PPG Timer Block Diagram of 8-/16-bit PPG Timer C .......... 286 Block Diagram of 8-/16-bit PPG Timer D .......... 288 Functions of 8-/16-bit PPG Timer...................... 282 Generation of Interrupt Request from 8-/16-bit PPG Timer ......................................... 291 Interrupt of 8-/16-bit PPG Timer ....................... 299 List of Registers and Reset Values of 8-/16-bit PPG Timer ......................................... 291 Operation Modes of 8-/16-bit PPG Timer........... 283 Operation of 8-/16-bit PPG Timer ..................... 300 Pins of 8-/16-bit PPG Timer.............................. 290 Precautions when Using 8-/16-bit PPG Timer..... 310 8-bit PPG Output 2-channel Independent Operation Mode Setting for 8-bit PPG Output 2-channel Independent Operation Mode ............... 301 INDEX A A Accumulator (A) ................................................ 40 A/D Control Status Register A/D Control Status Register (High) (ADCS1)..... 346 A/D Control Status Register (Low) (ADCS0) ..... 349 A/D Converter 8-/10-bit A/D Converter Interrupt and EI2OS...... 358 A/D-converted Data Protection Function in 8-/10-bit A/D Converter....................... 367 Block Diagram of 8-/10-bit A/D Converter......... 341 Conversion Modes of 8-/10-bit A/D Converter .......................................................... 340 EI2OS Function of 8-/10-bit A/D Converter........ 358 Function of 8-/10-bit A/D Converter .................. 340 Generation of Interrupt from 8-/10-bit A/D Converter .......................................................... 345 Interrupt of A/D Converter................................ 358 List of Registers and Reset Values of 8-/10-bit A/D Converter .................................... 345 Pins of 8-/10-bit A/D Converter......................... 344 Precautions when Using 8-/10-bit A/D Converter .......................................................... 369 A/D Data Register A/D Data Register (ADCR0/ADCR1) ................ 351 A/D Setting Register A/D Setting Register (ADSR0/ADSR1) ............. 352 A/D-converted Data Protection A/D-converted Data Protection Function in 8-/10-bit A/D Converter ................... 367 Abstract Abstract .......................................................... 551 Acceptance Filter Acceptance Filtering ........................................ 490 Setting Acceptance Filter .................................. 494 Accessing Accessing Multi-byte Data.................................. 36 Accumulator Accumulator (A) ................................................ 40 ADCR A/D Data Register (ADCR0/ADCR1) ................ 351 ADCS A/D Control Status Register (High) (ADCS1)..... 346 A/D Control Status Register (Low) (ADCS0) ..... 349 Continuous Conversion Mode (ADCS:MD1,MD0= "10B" ) ................ 359 Pause-conversion Mode (ADCS:MD1,MD0= "11B" ) ................ 359 Single-shot Conversion Mode (ADCS:MD1,MD0= "00B" or "01B" ) .......................................................... 359 Address Detection Control Register Address Detection Control Register 0 (PACSR0) .......................................................... 509 Address Detection Control Register 1 (PACSR1) ..........................................................511 Address Match Detection Block Diagram of Address Match Detection Function ..........................................................507 List of Registers and Reset Values of Address Match Detection Function...............................508 Operation of Address Match Detection Function ..........................................................516 Operation of Address Match Detection Function at Storing Patch Program in E2PROM .......520 Overview of Address Match Detection Function ..........................................................506 Program Example for Address Match Detection Function .............................................522 Addressing Addressing.......................................................578 ADER Analog Input Enable Register (ADER5,ADER 6) ..........................................................356 Analog Input Enable Registers (ADER)..............175 ADSR A/D Setting Register (ADSR0/ADSR1)..............352 Alternative Mode Alternative Mode..............................................533 Analog Input Enable Register Analog Input Enable Register (ADER5,ADER 6) ..........................................................356 Analog Input Enable Registers (ADER)..............175 Asynchronous LIN Mode Operation in Asynchronous LIN Mode (operation mode 3)...............................429 Asynchronous Mode Operation in Asynchronous Mode ......................422 B Bank Addressing Bank Addressing Types.......................................34 Bank Select Prefix Bank Select Prefix ..............................................48 BAP Buffer Address Pointer (BAP) .............................77 Basic Configuration Basic Configuration of Serial Programming Connection with MB90F362/T(S), MB90F367/T(S) ..................................554 Baud Rate Calculating the Baud Rate .................................415 LIN-UART Baud Rate Selection........................413 Baud Rate Generator Register Baud Rate Generator Register (BGRn0/n1) .........405 BGR Baud Rate Generator Register (BGRn0/n1) .........405 651 INDEX Bidirectional Communication Bidirectional Communication Function .............. 433 Bit Timing Setting Bit Timing............................................494 Block Diagram Block Diagram of 16-bit Free-run Timer ............213 Block Diagram of 16-bit I/O Timer .................... 211 Block Diagram of 16-bit Reload Timer............... 240 Block Diagram of 8-/10-bit A/D Converter ......... 341 Block Diagram of 8-/16-bit PPG Timer C........... 286 Block Diagram of 8-/16-bit PPG Timer D........... 288 Block Diagram of Address Match Detection Function .......................................................... 507 Block Diagram of CAN Controller..................... 445 Block Diagram of Clock Supervisor...................111 Block Diagram of Delayed Interrupt Generation Module................................................. 85 Block Diagram of DTP/External Interrupt .......... 315 Block Diagram of Evaluation Chip ........................ 9 Block Diagram of Flash/Mask ROM Version........ 11 Block Diagram of Input Capture ........................ 214 Block Diagram of LIN-UART ........................... 387 Block Diagram of LIN-UART Pins.................... 391 Block Diagram of Low Voltage/CPU Operating Detection Reset Circuit ........................ 374 Block Diagram of Pull-up Control Register (PUCR) .......................................................... 174 Block Diagram of ROM Mirroring Function Select Module............................................... 526 Block Diagram of the Clock Generation Block...... 95 Block Diagram of the Entire Flash Memory........ 531 Block Diagram of the External Reset Pin............125 Block Diagram of the Low-Power Consumption Control Circuit .................................... 137 Block Diagram of Timebase Timer .................... 182 Block Diagram of Watch Timer.........................270 Block Diagram of Watchdog Timer ...................199 Buffer Address Pointer Buffer Address Pointer (BAP) ............................. 77 Bus Mode Memory Space in Each Bus Mode ..................... 165 Bus Operation Stop Conditions for Canceling Bus Operation Stop (HALT=0) .......................................... 457 Conditions for Setting Bus Operation Stop (HALT=1) .......................................................... 457 State during Bus Operation Stop (HALT=1) ....... 457 BVAL Caution for Disabling Message Buffers By BVAL Bits .......................................................... 503 BY Timing RST and RY/BY Timing................................... 641 RY/BY Timing during Writing/erasing............... 641 652 C CAN Controller Block Diagram of CAN Controller .................... 445 Canceling Transmission Request from CAN Controller........................................... 488 Features of CAN Controller .............................. 444 Reception Flowchart of the CAN Controller ....... 493 Starting Transmission of CAN Controller........... 488 Transmission Flowchart of CAN Controller ....... 489 CAN Direct Setting of CAN Direct Mode............................. 504 CAN Direct Mode Register CAN Direct Mode Register (CDMR) (Only MB90V340).............................. 502 CCR Condition Code Register (CCR) .......................... 42 CDMR CAN Direct Mode Register (CDMR) (Only MB90V340).............................. 502 CE Control Write,data Polling,read (CE control) .................. 638 Chip Erase Chip Erase/sector Erase Command Sequence ..... 639 CKSCR Configuration of the Clock Selection Register (CKSCR) ............................................. 98 Clock Frequency Oscillating Clock Frequency and Serial Clock Input Frequency .......................................... 556 Clock Generation Block Block Diagram of the Clock Generation Block ..... 95 Clock Mode Clock Mode..................................................... 103 Clock Mode Switching ..................................... 158 Clock Mode Transition..................................... 103 Internal Clock Mode ........................................ 238 Operation in Internal Clock Mode ..................... 255 Program Example in Internal Clock Mode.......... 263 Setting of Internal Clock Mode ......................... 254 Sub-clock Mode............................................... 116 Sub-clock Mode Transition Operating When Sub-clock Has Already Stopped ........... 116 Clock Selection Register Clock Selection Register and List of Reset Value ........................................................... 97 Clock Supervisor Block Diagram of Clock Supervisor .................. 111 Overview of Clock Supervisor .......................... 110 Prohibition Setting of CR Oscillation Circuit and Clock Supervisor ................................ 115 Reoperating Setting of CR Oscillation Circuit and Clock Supervisor ................................ 115 Reset Check by Clock Supervisor ...................... 117 INDEX Clock Supervisor Control Register Clock Supervisor Control Register (CSVCR)...... 113 Clock Supply Cycle of Clock Supply...................................... 269 Clocks Clocks............................................................... 92 CMR Common Register Bank Prefix (CMR)................. 49 Command Sequence Chip Erase/sector Erase Command Sequence...... 639 Command Sequence Table................................ 538 Common Register Bank Prefix Common Register Bank Prefix (CMR)................. 49 Communication Bidirectional Communication Function .............. 433 LIN-master-slave Communication Function ....... 438 Master-slave Communication Function .............. 435 Comparing Time Setting of Comparing Time (CT2 to CT0 bits) .......................................................... 355 Condition Code Register Condition Code Register (CCR) .......................... 42 Configuration of the Clock Selection Register Configuration of the Clock Selection Register (CKSCR) ............................................. 98 Configuration of the PLL/Subclock Control Register Configuration of the PLL/Subclock Control Register (PSCCR) ............................................ 101 Continuous Conversion Mode Continuous Conversion Mode (ADCS: MD1,MD0= "10B") ................ 359 Operation of Continuous Conversion Mode ........ 363 Setting of Continuous Conversion Mode ............ 362 Control Status Register Control Status Register (CSR) (Lower) .............. 453 Control Status Register (CSR) (upper) ............... 453 Control Status Register (CSR-lower) ................. 454 Conversion Conversion Using EI2OS .................................. 366 Conversion Mode Continuous Conversion Mode (ADCS:MD1,MD0= "10B") ................. 359 Conversion Modes of 8-/10-bit A/D Converter .......................................................... 340 Operation of Continuous Conversion Mode ........ 363 Operation of Pause-conversion Mode................. 365 Operation of Single-shot Conversion Mode ........ 361 Pause-conversion Mode (ADCS:MD1,MD0= "11B") .......................................................... 359 Setting of Continuous Conversion Mode ............ 362 Setting of Pause-conversion Mode ..................... 364 Setting of Single-shot Conversion Mode ............ 360 Single-shot Conversion Mode (ADCS:MD1,MD0= "00B" or "01B") ..........................................................359 Counting Example Counting Example ............................................417 CPU Outline of CPU Memory Space............................29 Outline of the CPU .............................................28 CPU Intermittent Operating Mode CPU Intermittent Operating Mode......................135 CPU Intermittent Operation Mode CPU Intermittent Operation Mode......................142 CPU Operating Detection Reset Circuit Block Diagram of Low Voltage/CPU Operating Detection Reset Circuit ........................374 CPU Operating Detection Reset Circuit ..............373 Notes on Using CPU Operating Detection Reset Circuit ................................................379 Operating of CPU Operating Detection Reset Circuit ..........................................................378 Operating of Low Voltage/CPU Operating Detection Reset Circuit .......................................378 Sample Program for Low Voltage/CPU Operating Detection Reset Circuit ........................380 CPU Operating Modes CPU Operating Modes and Current Consumption ..........................................................134 CR Oscillation Circuit Prohibition Setting of CR Oscillation Circuit and Clock Supervisor .................................115 Reoperating Setting of CR Oscillation Circuit and Clock Supervisor .................................115 CSR Control Status Register (CSR) (Lower)...............453 Control Status Register (CSR) (upper) ................453 Control Status Register (CSR-lower) ..................454 CSVCR Clock Supervisor Control Register (CSVCR) ......113 CT Setting of Comparing Time (CT2 to CT0 bits).....355 Current Consumption CPU Operating Modes and Current Consumption ..........................................................134 Cycle Count Execution Cycle Count......................................593 D Data Counter Data Counter (DCT) ...........................................76 Data Frame Processing for Reception of Data Frame and Remote frame..................................................491 Data Polling Data Polling .....................................................640 653 INDEX Data Polling Flag Data Polling Flag (DQ7) ................................... 541 Data Read Data Read by Read Access................................ 636 Data Register List of Message Buffer (data register)................. 451 List of Message Buffers (DLC registers and Data registers) ........ 450 DCT Data Counter (DCT) ........................................... 76 DDR Port Direction Register (DDR)........................... 172 Delayed Interrupt Generation Module Block Diagram of Delayed Interrupt Generation Module................................................. 85 Explanation of Operation of Delayed Interrupt Generation Module................................ 88 Overview of Delayed Interrupt Generation Module ............................................................ 84 Precautions when Using Delayed Interrupt Generation Module................................................. 89 Program Example of Delayed Interrupt Generation Module................................................. 90 Delayed Interrupt Request Generate/cancel Register Delayed Interrupt Request Generate/cancel Register (DIRR)................................................. 87 Descriptor Extended Intelligent I/O Service Descriptor (ISD) ............................................................ 76 Detailed Explanation Detailed Explanation of Flash Memory Write/erase .......................................................... 544 Detect Address Setting Detect Address......................................516 Detect Address Setting Registers Detect Address Setting Registers (PADR0 to PADR5) .......................................................... 513 Functions of Detect Address Setting Registers .......................................................... 514 Detection Level Setting Register Detection Level Setting Register (ELVR1) ......... 323 Device Handling the Device ........................................... 21 Direct Addressing Direct Addressing............................................. 580 Direct Pin Access LIN-UART Direct Pin Access ........................... 432 DIRR Delayed Interrupt Request Generate/cancel Register (DIRR)................................................. 87 DIV Precautions for Use of "DIV A,Ri" and "DIVW A,RWi" Instructions .................. 52 654 Use of the "DIV A,Ri" and "DIVW A,RWi" Instructions without Precautions ............ 53 DIVW Precautions for Use of "DIV A,Ri" and "DIVW A,RWi" Instructions.................. 52 Use of the "DIV A,Ri" and "DIVW A,RWi" Instructions without Precautions ............ 53 DLC Registers List of Message Buffers (DLC Registers and Data registers)....... 450 DQ5 Timing Limit Exceeded Flag (DQ5) .................. 543 DQ6 Toggle Bit Flag (DQ6) ..................................... 542 DQ7 Data Polling Flag (DQ7)................................... 541 DTP DTP Function .................................................. 332 Program Example of DTP Function ................... 336 DTP/External Interrupt Block Diagram of DTP/External Interrupt .......... 315 DTP/External Interrupt Function ....................... 314 DTP/External Interrupt Operation...................... 329 List of Registers and Reset Values in DTP/ External Interrupt................................ 318 Pins of DTP/External Interrupt .......................... 317 Precautions when Using DTP/External Interrupt ......................................................... 333 Program Example of DTP/External Interrupt Function ......................................................... 335 Setting of DTP/External Interrupt ...................... 327 DTP/External Interrupt Enable Register DTP/External Interrupt Enable Register (ENIR1) ......................................................... 321 DTP/External Interrupt Factor Register DTP/External Interrupt Factor Register (EIRR1) ......................................................... 319 E E2PROM E2PROM Memory Map.................................... 518 Operation of Address Match Detection Function at Storing Patch Program in E2PROM ...... 520 System Configuration and E2PROM Memory Map ......................................................... 517 ECCR Extended Communication Control Register (ECCR) ......................................................... 403 Effective Address Effective Address Field ............................ 579, 596 EI2OS 16-bit I/O Timer Interrupt and EI2OS................. 228 8-/10-bit A/D Converter Interrupt and EI2OS...... 358 Conversion Using EI2OS .................................. 366 INDEX Correspondence between 16-bit Reload Timer Interrupt and EI2OS............................. 251 Correspondence between Timebase Timer Interrupt and EI2OS .......................................... 187 Correspondence to EI2OS Function ................... 228 EI2OS Function of 16-bit Reload Timer ............. 251 EI2OS Function of 8-/10-bit A/D Converter........ 358 EI2OS Operation Flow........................................ 79 Extended Intelligent I/O Service (EI2OS) ....... 57, 74 LIN-UART Interrupts and EI2OS ...................... 408 EI2OS Status Register EI2OS Status Register (ISCS).............................. 78 EIRR DTP/External Interrupt Factor Register (EIRR1) .......................................................... 319 ELVR Detection Level Setting Register (ELVR1) ......... 323 Enable Sector Protect Enable Sector Protect/verify Sector Protect......... 642 ENIR DTP/External Interrupt Enable Register (ENIR1) .......................................................... 321 Erase Detailed Explanation of Flash Memory Write/erase .......................................................... 544 Erasing Erasing All Data in the Flash Memory (erasing chips) .......................................................... 548 Erasing Chip Erasing All Data in the Flash Memory (erasing chips) .......................................................... 548 Erasing Chip in the Flash Memory..................... 548 ESCR Extended Status/control Register (ESCR)........... 401 Evaluation Chip Block Diagram of Evaluation Chip ........................ 9 Event Count Mode Event Count Mode ........................................... 238 Operation in Event Count Mode ........................ 261 Setting of Event Count Mode ............................ 259 Event Counter Mode Program Example in Event Counter Mode.......... 264 Exceptions Exceptions......................................................... 58 Extended Communication Control Register Extended Communication Control Register (ECCR) .......................................................... 403 Extended Intelligent I/O Service Extended Intelligent I/O Service (EI2OS) ....... 57, 74 Extended Intelligent I/O Service Descriptor (ISD) ............................................................ 76 Extended Status/control Register Extended Status/control Register (ESCR)........... 401 External Clock Connection of an Oscillator or an External Clock to the Microcontroller ..........................108 External Interrupt Block Diagram of DTP/External Interrupt...........315 DTP/External Interrupt Enable Register (ENIR1) ..........................................................321 DTP/External Interrupt Factor Register (EIRR1) ..........................................................319 DTP/External Interrupt Function ........................314 DTP/External Interrupt Operation ......................329 External Interrupt Function................................331 List of Registers and Reset Values in DTP/ External Interrupt.................................318 Pins of DTP/External Interrupt...........................317 Precautions when Using DTP/External Interrupt ..........................................................333 Program Example of DTP/External Interrupt Function ..........................................................335 Selection of External Interrupt Factor .................325 Setting of DTP/External Interrupt.......................327 External Reset Block Diagrams of the External Reset Pin...........125 External Single Clock Sub-clock Mode with External Single Clock Product ..........................................................116 F F2MC-16LX F2MC-16LX Instruction List..............................600 Features Features ...............................................................7 FF Bank Access to FF Bank by ROM Mirroring Function ..........................................................526 Flag Change Disable Prefix Flag Change Disable Prefix (NCC).......................49 Flag Set Timing Reception Interrupt Generation and Flag Set Timing ..........................................................409 Transmission Interrupt Generation and Flag Set Timing................................................411 Flash Block Diagram of Flash/Mask ROM Version ........11 Flash Memory 512K-bit Flash Memory Features .......................530 Block Diagram of the Entire Flash Memory ........531 Detailed Explanation of Flash Memory Write/erase ..........................................................544 Erasing All Data in the Flash Memory (erasing chips) ..........................................................548 Erasing Chip in the Flash Memory .....................548 Flash Memory Control Signals...........................533 Notes on Using Flash Memory...........................550 655 INDEX Sector Configuration of the 512K-bit Flash Memory .......................................................... 531 Setting the Flash Memory to the Read/reset State .......................................................... 545 Writing Data to the Flash Memory ..................... 546 Writing to the Flash Memory............................. 546 Writing to/erasing Flash Memory....................... 530 Flash Memory Control Status Register Flash Memory Control Status Register (FMCS) .................................................. 530, 535 Flash Memory Mode Flash Memory Mode ........................................ 533 Flash Memory Write Detailed Explanation of Flash Memory Write/erase .......................................................... 544 Flash Microcomputer Programmer Example of Minimum Connection to Flash Microcomputer Programmer (Power supplied from programmer)....... 563 Example of Minimum Connection to Flash microcontroller Programmer ................ 561 Flash Security Behavior Under the Flash Security Feature ......... 551 How to Disable the Flash Security Feature.......... 551 How to Enable the Flash Security Feature........... 551 FMCS Flash Memory Control Status Register (FMCS) .................................................. 530, 535 Frame Format Setting Frame Format ....................................... 494 Free-run Timer Block Diagram of 16-bit Free-run Timer ............213 Explanation of Operation of 16-bit Free-run Timer .......................................................... 229 H HALT Conditions for Canceling Bus Operation Stop (HALT=0) .......................................... 457 Conditions for Setting Bus Operation Stop (HALT=1) .......................................................... 457 State during Bus Operation Stop (HALT=1) ....... 457 Hardware Interrupt Hardware Interrupt Operation.............................. 68 Hardware Interrupts...................................... 56, 67 Occurrence and Release of Hardware Interrupt...... 69 Structure of Hardware Interrupt ........................... 67 Hardware Sequence Flags Hardware Sequence Flags ................................. 539 I I/O Area I/O Area ............................................................ 30 656 I/O Maps I/O Maps (00XX Addresses) ............................. 568 I/O Pins Status of I/O Pins (Single-chip Mode)................ 156 I/O Port I/O Port Registers ............................................ 169 I/O Ports ......................................................... 168 I/O Timer 16-bit I/O Timer Interrupt and EI2OS................. 228 Block Diagram of 16-bit I/O Timer.................... 211 Functions of 16-bit I/O Timer ........................... 210 Generation of Interrupt Request from 16-bit I/O Timer ......................................................... 216 Interrupts of 16-bit I/O Timer............................ 227 Module Configuration of 16-bit I/O Timer ......... 210 Pins of 16-bit I/O Timer ................................... 216 Precautions when Using 16-bit I/O Timer........... 233 Program Example of 16-bit I/O Timer................ 234 ICE Input Capture Edge Register (ICE) .................... 224 ICR Interrupt Control Register (ICR).......................... 61 ICS Input Capture Control Status Registers (ICS01,ICS23) ......................................................... 221 ID Setting ID........................................................ 494 ID Registers List of Message Buffers (ID registers)................ 448 ILSR Input Level Select Register (ILSR) .................... 176 Indirect Addressing Indirect Addressing .......................................... 586 Initialized State Operating Mode in Initialized State ................... 115 Input Capture Block Diagram of Input Capture........................ 214 Setting of Input Capture.................................... 231 Input Capture Control Status Registers Input Capture Control Status Registers (ICS01,ICS23) ......................................................... 221 Input Capture Edge Register Input Capture Edge Register (ICE) .................... 224 Input Capture Register Input Capture Register (IPCP)........................... 223 Input Level Select Register Input Level Select Register (ILSR) .................... 176 Input-output Circuits Input-output Circuits .......................................... 17 Instruction Exception due to Execution of an Undefined Instruction ........................................... 82 Execution of an Undefined Instruction ................. 82 Interrupt Disable Instructions .............................. 51 INDEX Precautions for Use of "DIV A,Ri" and "DIVW A,RWi" Instructions.................. 52 Restrictions on Interrupt Disable Instructions and Prefix Instructions........................... 51 Use of the "DIV A,Ri" and "DIVW A,RWi" Instructions without Precautions ............ 53 Instruction List F2MC-16LX Instruction List ............................. 600 Instruction Map Structure of Instruction Map ............................. 614 Instruction Presentation Description of Instruction Presentation Items and symbols.............................................. 597 Instruction Types Instruction Types ............................................. 577 Inter-CPU Connection Inter-CPU Connection Method .......................... 421 Internal Clock Mode Internal Clock Mode......................................... 238 Operation in Internal Clock Mode...................... 255 Program Example in Internal Clock Mode.......... 263 Setting of Internal Clock Mode.......................... 254 Interrupt 16-bit I/O Timer Interrupt and EI2OS................. 228 8-/10-bit A/D Converter Interrupt and EI2OS...... 358 Cancellation of Standby Mode by Interrupt ........ 157 Correspondence between 16-bit Reload Timer Interrupt and EI2OS............................. 251 Correspondence between Timebase Timer Interrupt and EI2OS .......................................... 187 Generation of Interrupt from 8-/10-bit A/D Converter .......................................................... 345 Hardware Interrupt Operation.............................. 68 Hardware Interrupts ..................................... 56, 67 Interrupt Disable Instructions .............................. 51 Interrupt Flow.................................................... 65 Interrupt Number ............................................... 85 Interrupts of 16-bit Reload Timer ...................... 251 Interrupt of 8-/16-bit PPG Timer ....................... 299 Interrupts of 8-/16-bit PPG Timer ...................... 299 Interrupt of A/D Converter................................ 358 Interrupt of Timebase Timer ............................. 187 LIN-UART Interrupts....................................... 406 LIN-UART Interrupts and EI2OS ...................... 408 Multiple Interrupts ............................................. 71 Occurrence and Release of Hardware Interrupt ............................................................ 69 Reception Interrupt Generation and Flag Set Timing .......................................................... 409 Restrictions on Interrupt Disable Instructions and prefix Instructions ................................. 51 Software Interrupt Operation............................... 72 Software Interrupts....................................... 57, 72 Structure of Hardware Interrupt ........................... 67 Structure of Software Interrupts........................... 72 Transmission Interrupt Generation and Flag Set Timing................................................411 Watch Timer Interrupt.......................................275 Watch Timer Interrupt and EI2OS Transfer Function ..........................................................275 Interrupt Causes Interrupt Causes,interrupt Vectors,and Interrupt control Registers..................................646 Interrupt Control Register Interrupt Causes,interrupt Vectors,and Interrupt control Registers..................................646 Interrupt Control Register (ICR) ..........................61 Interrupt Disable Instructions Interrupt Disable Instructions...............................51 Restrictions on Interrupt Disable Instructions and Prefix Instructions ...........................51 Interrupt Number Details of Pins and Interrupt Number..................212 Details of Pins and Interrupt Numbers ................316 Interrupt Number................................................85 Interrupt Request Generation of Interrupt Request from 16-bit I/O Timer ..........................................................216 Generation of Interrupt Request from 16-bit Reload Timer .................................................244 Generation of Interrupt Request from 8-/16-bit PPG Timer ..........................................291 Generation of Interrupt Request from Timebase Timer ..........................................................184 Generation of Interrupt Request from Watch Timer ..........................................................272 Interrupt Vector Interrupt Causes,interrupt Vectors,and Interrupt control Registers..................................646 Interrupt Vector..................................................59 List of Interrupt Vectors ..............................72, 644 Interval Timer Interval Timer Function.............180, 188, 268, 276 IPCP Input Capture Register (IPCP) ...........................223 ISCS EI2OS Status Register (ISCS) ..............................78 ISD Extended Intelligent I/O Service Descriptor (ISD) ............................................................76 L Last Event Indicator Register Last Event Indicator Register (LEIR)..................458 LEIR Last Event Indicator Register (LEIR)..................458 LIN Master Device LIN-UART as LIN Master Device .....................439 657 INDEX LIN-master-slave Communication LIN-master-slave Communication Function........ 438 LIN-UART Block Diagram of LIN-UART ........................... 387 Block Diagram of LIN-UART Pins.................... 391 LIN-UART as LIN Master Device ..................... 439 LIN-UART Baud Rate Selection........................ 413 LIN-UART Direct Pin Access ........................... 432 LIN-UART Functions....................................... 382 LIN-UART Interrupts ....................................... 406 LIN-UART Interrupts and EI2OS....................... 408 LIN-UART Pins............................................... 391 LIN-UART Registers........................................ 392 Notes on Using LIN-UART............................... 441 Operation of LIN-UART................................... 420 LIN-UART Serial Mode Register LIN-UART Serial Mode Register (SMR) ........... 395 Low Voltage Block Diagram of Low Voltage/CPU Operating Detection Reset Circuit ........................ 374 Operating of Low Voltage/CPU Operating Detection Reset Circuit ....................................... 378 Sample Program for Low Voltage/CPU Operating Detection Reset Circuit ........................ 380 Low Voltage Detection Status of Reset Cause Bit and Low Voltage Detection Bit ..................................................... 130 Low Voltage Detection Reset Circuit Low Voltage Detection Reset Circuit ................. 372 Notes on Using Low Voltage Detection Reset Circuit .......................................................... 379 Low Voltage/CPU Operating Detection Reset Control Register Low Voltage/CPU Operating Detection Reset Control Register (LVRC) ..................... 376 Low-Power Consumption Block Diagram of the Low-Power Consumption Control Circuit .................................... 137 Low-Power Consumption Mode Control Register Low-Power Consumption Mode Control Register (LPMCR) ........................................... 139 Notes on Accessing the Low-Power Consumption Mode Control Register (LPMCR) to Enter the Standby Mode....................... 158 LPMCR Low-Power Consumption Mode Control Register (LPMCR) ........................................... 139 Notes on Accessing the Low-Power Consumption Mode Control Register (LPMCR) to Enter the Standby Mode....................... 158 LVRC Low Voltage/CPU Operating Detection Reset Control Register (LVRC) ................................. 376 658 M Machine Clock Machine Clock ................................................ 104 Mask ROM Block Diagram of Flash/Mask ROM Version ....... 11 Master-slave Communication Master-slave Communication Function .............. 435 MB90360 Series Features of MB90360 Series ................................. 2 MB90F362 Basic Configuration of Serial Programming Connection with MB90F362/T(S), MB90F367/T(S) ................................. 554 MB90F367 Basic Configuration of Serial Programming Connection with MB90F362/T(S), MB90F367/T(S) ................................. 554 MB90V340 CAN Direct Mode Register (CDMR) (Only MB90V340).............................. 502 MD Continuous Conversion Mode (ADCS:MD1,MD0= "10B" ) ................ 359 Pause-conversion Mode (ADCS:MD1,MD0= "11B" ) .................. 359 Single-shot Conversion Mode (ADCS:MD1,MD0= "00B" or "01B" ) ................................................................ 359 Memory Access Modes Outline of Memory Access Modes..................... 162 Memory Map E2PROM Memory Map.................................... 518 Memory Map..................................................... 32 System Configuration and E2PROM Memory Map ......................................................... 517 Memory Space Memory Space in Each Bus Mode ..................... 165 Multi-byte Data Allocation in Memory Space....... 36 Outline of CPU Memory Space ........................... 29 Message Buffer Caution for Disabling Message Buffers by BVAL Bits ......................................................... 503 List of Message Buffer (data register) ................ 451 List of Message Buffers (DLC registers and Data registers) ............................................ 450 List of Message Buffers (ID registers)................ 448 Message Buffers ...................................... 452, 481 Procedure for Reception by Message Buffer (x) ......................................................... 498 Procedure for Transmission by Message Buffer (x) ......................................................... 496 Setting Configuration of Multi-level Message Buffer ......................................................... 500 INDEX Message Buffer Control Registers Message Buffer Control Registers ..................... 452 Microcontroller Connection of an Oscillator or an External Clock to the Microcontroller.......................... 108 Minimum Connection Example of Minimum Connection to Flash Microcomputer Programmer ................ 563 Example of Minimum Connection to Flash microcontroller Programmer ................ 561 Mode Data Mode Data ...................................................... 164 Status of Pins after Mode Data is Read............... 132 Mode Fetch Mode Fetch ..................................................... 127 Mode Pins Mode Pins ............................................... 126, 163 Module Configuration Module Configuration of 16-bit I/O Timer ......... 210 Multi-byte Data Accessing Multi-byte Data.................................. 36 Multi-byte Data Allocation Multi-byte Data Allocation in Memory Space ....... 36 Multi-level Message Buffer Setting Configuration of Multi-level Message Buffer .......................................................... 500 Multiple Interrupts Multiple Interrupts ............................................. 71 Multiplier Selection of a PLL Clock Multiplier .................. 104 N NCC Flag Change Disable Prefix (NCC) ...................... 49 Node Status Correspondence between Node Status Bit and Node Status................................................. 456 O Operating Detection Reset Circuit Block Diagram of Low Voltage/CPU Operating Detection Reset Circuit........................ 374 Operating of Low Voltage/CPU Operating Detection Reset Circuit....................................... 378 Sample Program for Low Voltage/CPU Operating Detection Reset Circuit........................ 380 Operating Mode CPU Intermittent Operating Mode ..................... 135 CPU Operating Modes and Current Consumption .......................................................... 134 Operation Clock Supply of Operation Clock................................ 191 Operation Enable Bit Operation Enable Bit.........................................421 Operation Mode CPU Intermittent Operation Mode......................142 Operation in Asynchronous LIN Mode (operation mode 3)...............................429 Operation in Synchronous Mode (operation mode 2) ..........................................................426 Operation Modes of 16-bit Reload Timer............238 Setting for 16-bit PPG Output Operation Mode ..........................................................304 Setting for 8+8-bit PPG Output Operation Mode ..........................................................307 Setting for 8-bit PPG Output 2-channel Independent Operation Mode................301 Operation Status Operation Status during Standby Mode...............143 Oscillating Clock Frequency Oscillating Clock Frequency and Serial Clock Input Frequency...................................556 Oscillation Circuit Prohibition Setting of CR Oscillation Circuit and Clock Supervisor ...........................115 Reoperating Setting of CR Oscillation Circuit and Clock Supervisor ...........................115 Oscillation Stabilization Wait Oscillation Stabilization Wait and Reset State .....124 Oscillation Stabilization Wait Interval ................107 Oscillation Stabilization Wait Time Oscillation Stabilization Wait Time....................157 Oscillation Stabilization Wait Time Timer of Subclock .........................................277 Reset Causes and Oscillation Stabilization Wait Times ..........................................................123 Oscillator Connection of an Oscillator or an External Clock to the Microcontroller ..........................108 Others Others................................................................73 Overall Control Registers List of overall Control Registers.........................446 Overall Control Registers ..................................452 P Package Dimensions Package Dimensions ...........................................12 PACSR Address Detection Control Register 0 (PACSR0) ..........................................................509 Address Detection Control Register 1 (PACSR1) ..........................................................511 PADR Detect Address Setting Registers (PADR0 to PADR5) ..........................................................513 659 INDEX Patch Processing Flow of Patch Processing for Patch Program....... 520 Patch Program Flow of Patch Processing for Patch Program....... 520 Pause-conversion Mode Operation of Pause-conversion Mode ................. 365 Pause-conversion Mode (ADCS:MD1,MD0= "11B" ) ................ 359 Setting of Pause-conversion Mode ..................... 364 PC Program Counter (PC) ........................................ 45 PDR Port Data Register (PDR) .................................. 170 Pin Details of Pins and Interrupt Number ................. 212 Mode Pins ....................................................... 163 Pin Functions ..................................................... 14 Pins of 16-bit I/O Timer.................................... 216 Status of I/O Pins (Single-chip Mode) ................ 156 Status of Pins after Mode Data is Read ............... 132 Status of Pins During a Reset............................. 132 PLL Clock Multiplier Selection of a PLL Clock Multiplier...................104 Port Data Register Port Data Register (PDR) .................................. 170 Port Direction Register Port Direction Register (DDR)........................... 172 Power Supplied From Programmer Example of Serial Programming Connection (Power Supplied From Programmer) .......................................................... 559 PPG Channels and PPG Pins of PPG Timers .............. 285 Setting for 16-bit PPG Output Operation Mode .......................................................... 304 Setting for 8+8-bit PPG Output Operation Mode .......................................................... 307 Setting for 8-bit PPG Output 2-channel Independent Operation Mode ............... 301 PPG Reload Registers PPG Reload Registers (PRLLC/PRLHC,PRLLD/PRLHD)....... 298 PPG Timer Block Diagram of 8-/16-bit PPG Timer C........... 286 Block Diagram of 8-/16-bit PPG Timer D........... 288 Channels and PPG Pins of PPG Timers .............. 285 Functions of 8-/16-bit PPG Timer ...................... 282 Generation of Interrupt Request from 8-/16-bit PPG Timer.......................................... 291 Interrupt of 8-/16-bit PPG Timer........................ 299 Interrupts of 8-/16-bit PPG Timer ...................... 299 List of Registers and Reset Values of 8-/16-bit PPG Timer.......................................... 291 Operation Modes of 8-/16-bit PPG Timer ........... 283 Operation of 8-/16-bit PPG Timer...................... 300 660 Pins of 8-/16-bit PPG Timer.............................. 290 Precautions when Using 8-/16-bit PPG Timer..... 310 PPGC Operation Mode Control Register PPGC Operation Mode Control Register (PPGCC) ......................................................... 292 PPGC/D Count Clock Select Register PPGC/D Count Clock Select Register (PPGCD) ......................................................... 296 PPGCC PPGC Operation Mode Control Register (PPGCC) ......................................................... 292 PPGCD PPGC/D Count Clock Select Register (PPGCD) ......................................................... 296 PPGD Operation Mode Control Register (PPGCD) ......................................................... 294 PPGD Operation Mode Control Register PPGD Operation Mode Control Register (PPGCD) ......................................................... 294 Prefix Bank Select Prefix ............................................. 48 Common Register Bank Prefix (CMR)................. 49 Flag Change Disable Prefix (NCC) ...................... 49 Restrictions on Interrupt Disable Instructions and prefix Instructions ................................. 51 Prefix Instructions Restrictions on Interrupt Disable Instructions and Prefix Instructions........................... 51 Prescaler Settings Prescaler Settings............................................. 463 Processor Status Processor Status (PS) ......................................... 42 Program Counter Program Counter (PC)........................................ 45 Program Example Program Example for Address Match Detection Function............................................. 522 Program Example in Event Counter Mode.......... 264 Program Example in Internal Clock Mode.......... 263 Program Example of 16-bit I/O Timer................ 234 Program Example of Delayed Interrupt Generation Module ................................................ 90 Program Example of DTP Function ................... 336 Program Example of DTP/External Interrupt Function ......................................................... 335 Program Example of Timebase Timer ................ 193 Program Example of Watch Timer .................... 278 Program Examples of Watchdog Timer.............. 208 Program Execution Program Execution........................................... 516 PS Processor Status (PS) ......................................... 42 INDEX PSCCR Configuration of the PLL/Subclock Control Register (PSCCR) ............................................ 101 PUCR Block Diagram of Pull-up Control Register (PUCR) .......................................................... 174 Pull-up Control Register (PUCR) ...................... 174 Pull-up Control Register Block Diagram of Pull-up Control Register (PUCR) .......................................................... 174 Pull-up Control Register (PUCR) ...................... 174 R RAM RAM area ......................................................... 30 RDR Reception Data Register (RDR)......................... 399 Read Setting the Flash Memory to the Read/reset State .......................................................... 545 Read Access Data Read by Read Access................................ 636 Receive Overrun Receive Overrun .............................................. 491 Received Message Storing Received Message ................................ 490 Reception Completing Reception ...................................... 492 Procedure for Reception by Message Buffer (x) .......................................................... 498 Processing for Reception of Data Frame and Remote Frame ................................................ 491 Reception Flowchart of the CAN Controller ....... 493 Reception Data Register Reception Data Register (RDR)......................... 399 Reception Interrupt Reception Interrupt Generation and Flag Set Timing .......................................................... 409 Register Bank Register Bank .................................................... 46 Register Bank Pointer Register Bank Pointer (RP) ................................. 43 Reload Counter Function of Reload Counter .............................. 418 Reload Timer 16-bit Reload Timer Registers and Reset Value .......................................................... 243 Block Diagram of 16-bit Reload Timer .............. 240 Correspondence between 16-bit Reload Timer Interrupt and EI2OS............................. 251 2 EI OS Function of 16-bit Reload Timer ............. 251 Generation of Interrupt Request from 16-bit Reload Timer...................................... 244 Interrupts of 16-bit Reload Timer ...................... 251 Operation Modes of 16-bit Reload Timer............238 Pins of 16-bit Reload Timer...............................242 Precautions when Using 16-bit Reload Timer ..........................................................262 Setting of 16-bit Reload Timer...........................252 Remote Frame Processing for Reception of Data Frame and Remote Frame...............................491 Reset 16-bit Reload Timer Registers and Reset Value ..........................................................243 Block Diagrams of the External Reset Pin...........125 Causes of a Reset..............................................120 Clock Selection Register and List of Reset Value ............................................................97 List of Registers and Reset Values .......................86 List of Registers and Reset Values in DTP/ External Interrupt.................................318 List of Registers and Reset Values of 8-/10-bit A/D Converter.....................................345 List of Registers and Reset Values of 8-/16-bit PPG Timer ..........................................291 List of Registers and Reset Values of Address Match Detection Function ....................508 List of Registers and Reset Values of ROM Mirroring Function Select Module.........527 List of Registers and Reset Values of Timebase Timer ..........................................................184 List of Registers and Reset Values of Watch Timer ..........................................................272 List of Registers and Reset Values of Watchdog Timer ..........................................................201 Oscillation Stabilization Wait and Reset State .....124 Overview of Reset Operation .............................126 Reset Check By Clock Supervisor ......................117 Status of Pins during a Reset..............................132 Reset Cause Reset Cause Bits...............................................128 Reset Cause Notes about Reset Cause Bits.............................131 Reset Causes and Oscillation Stabilization Wait Times ..........................................................123 Status of Reset Cause Bit and Low Voltage Detection Bit......................................................130 Reset State Setting the Flash Memory to the Read/reset State ..........................................................545 ROM Mirroring Access to FF Bank by ROM Mirroring Function ..........................................................526 Block Diagram of ROM Mirroring Function Select Module ...............................................526 ROM Mirroring Function Select Module Block Diagram of ROM Mirroring Function Select Module ...............................................526 661 INDEX List of Registers and Reset Values of ROM Mirroring Function Select Module ....................... 527 ROM Mirroring Function Select Register ROM Mirroring Function Select Register (ROMM) .......................................................... 528 ROMM ROM Mirroring Function Select Register (ROMM) .......................................................... 528 ROM Security Function Overview of ROM Security Function ................. 566 RP Register Bank Pointer (RP) ................................. 43 RST RST and RY/BY Timing................................... 641 RY RST and RY/BY Timing................................... 641 RY/BY Timing during Writing/erasing............... 641 S Sample Program Sample Program for Low Voltage/CPU Operating Detection Reset Circuit ........................ 380 Sampling Time Setting of Sampling Time (ST2 to ST0 bits)........ 354 SCR Serial Control Register (SCR)............................ 393 Sector Configuration Sector Configuration of the 512K-bit Flash Memory .......................................................... 531 Sector Erase Command Chip Erase/sector Erase Command Sequence......639 Sector Protect Enable Sector Protect/verify Sector Protect......... 642 Temporary Sector Protect Cancellation............... 643 Serial Clock Oscillating Clock Frequency and Serial Clock Input Frequency .................................. 556 Serial Control Register Serial Control Register (SCR)............................ 393 Serial Programming Connection Basic Configuration of Serial Programming Connection with MB90F362/T(S), MB90F367/T(S).................................. 554 Example of Serial Programming Connection (Power Supplied From Programmer) ..... 559 Example of Serial Programming Connection (User Power Supply Used) ...................557 Serial Status Register Serial Status Register (SSR) .............................. 397 Setting Setting for 16-bit PPG Output Operation Mode .......................................................... 304 662 Signal Mode Signal Mode .................................................... 421 Single Clock Sub-clock Mode with External Single Clock Product ......................................................... 116 Single-chip Mode Status of I/O Pins (Single-chip Mode)................ 156 Single-shot Conversion Mode Operation of Single-shot Conversion Mode ........ 361 Setting of Single-shot Conversion Mode ............ 360 Single-shot Conversion Mode (ADCS:MD1,MD0= "00B" or "01B" ) ......................................................... 359 Sleep Mode Return from Sleep Mode................................... 146 Switching to Sleep Mode .................................. 145 SMR LIN-UART Serial Mode Register (SMR) ........... 395 Software Interrupt Software Interrupt Operation............................... 72 Software Interrupts....................................... 57, 72 Structure of Software Interrupts........................... 72 Special Registers Special Registers................................................ 37 SSP User Stack Pointer (USP) and System Stack Pointer (SSP) ................................................... 41 SSR Serial Status Register (SSR).............................. 397 ST Setting of Sampling Time (ST2 to ST0 bits) ....... 354 Standby Mode Cancellation of Standby Mode by Interrupt ........ 157 Notes on Accessing the Low-Power Consumption Mode Control Register (LPMCR) to Enter the Standby Mode ...................... 158 Note on Canceling Standby Mode ..................... 157 Notes on the Transition to Standby Mode........... 157 Operation Status during Standby Mode .............. 143 Standby Mode ................................................. 135 Transition to Standby Mode .............................. 157 Status Bit Correspondence between Node Status Bit and Node Status................................................. 456 Status Change Status Change Diagram .................................... 155 Stop Mode Stop Mode............................................... 116, 152 Storing Patch Program Operation of Address Match Detection Function at Storing Patch Program in E2PROM ......................................................... 520 Structure Structure ........................................................... 75 INDEX Sub-clock Oscillation Stabilization Wait Time Timer of Subclock ............................................ 277 Sub-clock Mode............................................... 116 Sub-clock Mode Transition Operating When Sub-clock Has Already Stopped ........... 116 Sub-clock Mode with External Single Clock Product .......................................................... 116 Symbols Description of Instruction Presentation Items and symbols.............................................. 597 Synchronization Methods Synchronization Methods ................................. 421 Synchronous Mode Operation in Synchronous Mode (operation mode 2) .......................................................... 426 System Configuration System Configuration and E2PROM Memory Map .......................................................... 517 System Stack Pointer User Stack Pointer (USP) and System Stack Pointer (SSP) ................................................... 41 T TBTC Timebase Timer Control Register (TBTC).......... 185 TCCSH Timer Control Starus Register (Upper) (TCCSH) .......................................................... 217 TCCSL Timer Control Status Register (Lower) (TCCSL) .......................................................... 218 TCDT Timer Data Register (TCDT) ............................ 220 TDR Transmission Data Register (TDR) .................... 400 Temporary Sector Protect Temporary Sector Protect Cancellation .............. 643 Timebase Timer Block Diagram of Timebase Timer .................... 182 Correspondence between Timebase Timer Interrupt and EI2OS............................. 187 Generation of Interrupt Request from Timebase Timer .......................................................... 184 Interrupt of Timebase Timer ............................. 187 List of Registers and Reset Values of Timebase Timer .......................................................... 184 Precautions when Using Timebase Timer ........... 192 Program Example of Timebase Timer ................ 193 Timebase Timer Control Register Timebase Timer Control Register (TBTC).......... 185 Timebase Timer Mode Return from Timebase Timer Mode ................... 150 Switching to the Timebase Timer Mode ............. 150 Timer Control Status Register Timer Control Status Register (Lower) (TCCSL) ..........................................................218 Timer Control Status Register (Upper) (TCCSH) ..........................................................217 Timer Control Status Registers (High) (TMCSR:H) ..........................................................245 Timer Control Status Registers (Low) (TMCSR:L) ..........................................................247 Timer Data Register Timer Data Register (TCDT) .............................220 Timer Register Operating State of 16-bit Timer Register.............253 Timing RST and RY/BY Timing ...................................641 RY/BY Timing during Writing/erasing...............641 Timing Limit Exceeded Flag Timing Limit Exceeded Flag (DQ5) ...................543 TMCSR Timer Control Status Registers (High) (TMCSR:H) ..........................................................245 Timer Control Status Registers (Low) (TMCSR:L) ..........................................................247 TMR 16-bit Timer Registers (TMR) ...........................249 TMRLR 16-bit Reload Registers (TMRLR) .....................250 Toggle Bit Toggle Bit........................................................640 Toggle Bit Flag Toggle Bit Flag (DQ6) ......................................542 Transition Clock Mode Transition......................................103 Notes on the Transition to Standby Mode............157 Sub-clock Mode Transition Operating When Sub-clock Has Already Stopped ............116 Transition to Standby Mode...............................157 Transmission Canceling Transmission Request from CAN Controller ...........................................488 Procedure for Transmission by Message Buffer (x) ..........................................................496 Starting Transmission of CAN Controller ...........488 Transmission Flowchart of CAN Controller ........489 Transmission Data Register Transmission Data Register (TDR).....................400 Transmission Interrupt Transmission Interrupt Generation and Flag Set Timing................................................411 U UART Block Diagram of LIN-UART ...........................387 Block Diagram of LIN-UART Pins ....................391 663 INDEX LIN-UART as LIN Master Device ..................... 439 LIN-UART Baud Rate Selection........................ 413 LIN-UART Direct Pin Access ........................... 432 LIN-UART Functions....................................... 382 LIN-UART Interrupts ....................................... 406 LIN-UART Interrupts and EI2OS....................... 408 LIN-UART Pins............................................... 391 LIN-UART Registers........................................ 392 LIN-UART Serial Mode Register (SMR) ........... 395 Notes on Using LIN-UART............................... 441 Operation of LIN-UART................................... 420 Undefined Instruction Exception Due to Execution of an Undefined Instruction ............................................ 82 Execution of an Undefined Instruction ................. 82 Underflow Operation as 16-bit Timer Register Underflows .................................................. 255, 260 Operation at Underflow .................................... 239 Use Use of the "DIV A,Ri" and "DIVW A,RWi" Instructions without Precautions ............ 53 User Power Supply Example of Serial Programming Connection (User Power Supply Used) ...................557 User Stack Pointer User Stack Pointer (USP) and System Stack Pointer (SSP) ................................................... 41 USP User Stack Pointer (USP) and System Stack Pointer (SSP) ................................................... 41 V Verify Sector Protect Enable Sector Protect/verify Sector Protect......... 642 664 W Watch Mode Return from Watch Mode ................................. 148 Switching to the Watch Mode ........................... 148 Watch Timer Block Diagram of Watch Timer ........................ 270 Generation of Interrupt Request from Watch Timer ......................................................... 272 List of Registers and Reset Values of Watch Timer ......................................................... 272 Program Example of Watch Timer .................... 278 Watch Timer Counter....................................... 276 Watch Timer Interrupt...................................... 275 Watch Timer Interrupt and EI2OS Transfer Function ......................................................... 275 Watch Timer Control Register Watch Timer Control Register (WTC) ............... 273 Watchdog Timer Block Diagram of Watchdog Timer ................... 199 Functions of Watchdog Timer ........................... 196 List of Registers and Reset Values of Watchdog Timer ......................................................... 201 Operations of Watchdog Timer ......................... 204 Precautions when Using Watchdog Timer .......... 207 Program Examples of Watchdog Timer.............. 208 Setting Operation Clock of Watchdog Timer ...... 277 Watchdog Timer Control Register Watchdog Timer Control Register (WDTC) ....... 202 WDTC Watchdog Timer Control Register (WDTC) ....... 202 WE Control Write,data Polling,read (WE control) ................. 637 Writing to/erasing Flash Memory Writing to/erasing Flash Memory ...................... 530 WTC Watch Timer Control Register (WTC) ............... 273 CM44-10136-1E FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL F2MCTM-16LX 16-BIT MICROCONTROLLER MB90360 Series HARDWARE MANUAL April 2005 the first edition Published FUJITSU LIMITED Edited Business Promotion Dept. Electronic Devices