ds90820-ds07-13738-2e.pdf

FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13738-2E
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90820 Series
MB90822/823/F822A/F823A/V820
■ DESCRIPTION
The MB90820 series is a line of general-purpose, Fujitsu 16-bit microcontrollers designed for process control
applications which require high-speed real-time processing, such as consumer products.
While inheriting the AT architecture of the F2MC* family, the instruction set for the F2MC-16LX CPU core of the
MB90820 series incorporates additional instructions for high-level languages, supports extended addressing
modes, and contains enhanced multiplication and division instructions as well as a substantial collection of
improved bit manipulation instructions. In addition, the MB90820 series has an on-chip 32-bit accumulator which
enables processing of long-word data.
The peripheral resources integrated in the MB90820 series include : an 8/10-bit A/D converter, 8-bit D/A converters, UARTs (SCI) 0, 1, multi-functional timer (16-bit free-running timer, input capture units (ICUs) 0 to 3, output
compare units (OCUs) 0 to 5, 16-bit PPG timer 0, waveform generator), 16-bit PPG timer 1, 2, PWC 0, 1, 16-bit
reload timer 0, 1 and DTP/external interrupt.
*: F2MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED.
■ FEATURES
• Minimum execution time of instruction : 42 ns / 4 MHz oscillation (uses PLL clock multiplication) maximum
multiplier = 6
• Maximum memory space
16M bytes
Linear/bank access
(Continued)
■ PACKAGES
80-pin plastic QFP
80-pin plastic LQFP
80-pin plastic LQFP
(FPT-80P-M06)
(FPT-80P-M05)
(FPT-80P-M11)
MB90820 Series
(Continued)
• Instruction set optimized for controller applications
Supported data types : bit, byte, word, and long-word types
Standard addressing modes : 23 types
32-bit accumulator enhancing high-precision operations
Enhanced multiplication/division and RETI instructions
• Enhanced high level language (C) and multi-tasking support instructions
Use of a system stack pointer
Symmetrical instruction set and barrel shift instructions
• Program patch function (for two address pointers)
• Increased execution speed : 4-byte instruction queue
• Powerful interrupt function
Up to eight priority levels programmable
External interrupt inputs : 8 channels
• Automatic data transmission function independent of CPU operation
Up to 16 channels for the extended intelligent I/O service
DTP request inputs : 8 channels
• Internal ROM
Flash memory : 64K/128K bytes with flash security
Mask ROM : 64K/128K bytes
• Internal RAM
EVA : 16K bytes
Flash memory : 4K bytes
Mask ROM : 4K bytes
• General-purpose ports
Up to 66 channels (pull-up resistor settable port for : 32 channels)
• A/D Converter (RC) : 16 channels
8/10-bit resolution selectable
Conversion time : Min 3 µs (24 MHz operation, including sampling time)
• 8-bit D/A Converter : 2 channels
• UART : 2 channels
• 16-bit PPG timer : 3 channels
Mode switching function provided (PWM mode or one-shot mode)
ch0 can be worked with multi-functional timer or independently
• 16-bit reload timer : 2 channels
• 16-bit PWC timer : 2 channels
• Multi-functional timer
Input capture : 4 channels
Output compare with selectable buffer : 6 channels
Free-running timer with up or up-down mode selection and selectable buffer: 1 channel
16-bit PPG timer : 1 channel
Waveform generator : (16-bit timer : 3 channels, 3-phase waveform or dead time)
• Timebase counter/watchdog timer : 18-bit
• Low-power consumption mode :
Sleep mode
Stop mode
CPU intermittent operation mode
(Continued)
2
MB90820 Series
(Continued)
• Package :
LQFP-80 (FPT-80P-M05 : 0.50 mm pitch)
LQFP-80 (FPT-80P-M11 : 0.65 mm pitch)
QFP-80 (FPT-80P-M06 : 0.80 mm pitch)
• CMOS technology
3
MB90820 Series
■ PRODUCT LINEUP
Part number
Item
MB90V820
Classification
Evaluation product
ROM size
—
RAM size
16K bytes
CPU function
I/O port
MB90F822A
MB90F823A
MB90822
Flash memory product
with flash security
64K bytes
MB90823
Mask ROM product
128K bytes
64K bytes
128K bytes
4K bytes
Number of instruction : 351
Minimum execution time : 42 ns / 4 MHz (PLL × 6)
Addressing mode : 23
Data bit length : 1, 8, 16 bits
Maximum memory space: 16M bytes
I/O port (CMOS) : 66
Pulse width counter timer : 2 channels
PWC
UART
16-bit reload
timer
16-bit PPG
timer
Timer function (select the counter timer from three internal clocks)
Various pulse width measuring function (“H” pulse width, “L” pulse width, rising edge to falling
edge period, falling edge to rising edge period, rising edge to rising edge period and falling edge
to falling edge period)
UART : 2 channels
With full-duplex double buffer (8-bit length)
Clock asynchronized or clock synchronized transmission (with start and stop bits) can be
selected and used.
Transmission can be one-to-one (bidirectional communication) or one-to-n (master-slave communication).
Reload timer : 2 channels
Reload mode, single-shot mode or event count mode selectable
PPG timer : 3 channels
PWM mode or single-shot mode selectable
Ch0 can be worked with multi-functional timer or independently.
16-bit free-running timer with up or up-down mode selection and buffer : 1 channel
Multi-functional
16-bit output compare : 6 channels
timer
16-bit input capture : 4 channels
(for AC/DC
16-bit PPG timer : 1 channel
motor control)
Waveform generator (16-bit timer : 3 channels, 3-phase waveform or dead time)
8/10-bit A/D
converter
8-bit D/A
converter
8/10-bit resolution (16 channels)
Conversion time : Min 3 µs (24 MHz internal clock, including sampling time)
8-bit resolution (2 channels)
DTP/External
interrupt
8 independent channels
Interrupt factors : Rising edge, falling edge, “L” level or “H” level
Low-power
consumption
Stop mode / Sleep mode / CPU intermittent operation mode
(Continued)
4
MB90820 Series
(Continued)
Part number
MB90V820
Item
Package
Power supply
voltage for
operation*1
MB90F822A
MB90F823A
MB90822
MB90823
PGA-299
LQFP-80 (FPT-80P-M05 : 0.50 mm pitch)
LQFP-80 (FPT-80P-M11 : 0.65 mm pitch)
QFP-80 (FPT-80P-M06 : 0.80 mm pitch)
4.5 V to 5.5 V*1
3.5 V to 5.5 V : Normal operation when A/D converter and
D/A converter are not used
4.0 V to 5.5 V : Normal operation when D/A converter is not used
4.5 V to 5.5 V : Normal operation when A/D converter and
D/A converter are used
Process
CMOS
Emulator power
supply*2
⎯
Included
*1 : MB90V820 is operating guaranteed temperature 0 °C to + 25 °C.
*2 : It is setting of Jumper switch (TOOL VCC) when emulator (MB2147-01) is used.
Please refer to the MB2147-01 or MB2147-20 hardware manual (3.3 Emulator-dedicated Power Supply
switching) about details.
■ PACKAGE AND CORRESPONDING PRODUCTS
Package
MB90V820
PGA-299
MB90F822A MB90F823A
X
FPT-80P-M05
X
FPT-80P-M11
X
FPT-80P-M06
X
X
MB90822
MB90823
X
X
: Available
X : Not available
Note: For more information about each package, see “■ PACKAGE DIMENSIONS”.
5
MB90820 Series
■ DIFFERENCES AMONG PRODUCTS
Memory Size
In evaluation with an evaluation product, note the difference between the evaluation product and the product
actually used. The following items must be taken into consideration.
• The MB90V820 does not have an internal ROM, however, operations equivalent to chips with an internal ROM
can be evaluated by using a dedicated development tool, enabling selection of ROM size by settings of the
development tool.
• In the MB90V820, images from FF8000H to FFFFFFH are mapped to bank 00, and FE0000H to FF7FFFH are
mapped to bank FE and bank FF only. (This setting can be changed by configuring the development tool.)
• In the MB90822/F822A, images from FF8000H to FFFFFFH are mapped to bank 00, and FF0000H to FF7FFFH
are mapped to bank FF only. In the MB90823/F823A, images from FF8000H to FFFFFFH are mapped to bank
00, and FE0000H to FF7FFFH are mapped to bank FE and bank FF only.
6
MB90820 Series
■ PIN ASSIGNMENT
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
P70/DA0/AN8
P71/DA1/AN9
P72/SIN1/AN10
P73/SOT1/AN11
P74/SCK1/AN12
P75/FRCK/AN13
P76/IN0/AN14
P77/IN1/AN15
P80/IN2
P81/IN3
P82/RTO0(U) *
P83/RTO1(X) *
P84/RTO2(V) *
P85/RTO3(Y) *
P86/RTO4(W) *
P87/RTO5(Z) *
(TOP VIEW)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
C
Vss
Vcc
P00 *
P01 *
P02 *
P03 *
P04 *
P05 *
P06/PWI0 *
P07/PWO0 *
P10/INT0/DTTI
P11/INT1
P12/INT2
P13/INT3
P14/INT4
P15/INT5
P16/INT6
P17
P20/TIN1
P21/TO1
P22
Vcc
P23
MD0
MD1
MD2
P40/PPG1
P37/PPG0
P36
P35
P34
P33
P32
P31
P30
P27
P26
P25
P24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
AVR
AVcc
AVss
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
P61/AN1
P60/AN0
P51/INT7
P50/PPG2
P47/PWO1
P46/PWI1
P45/SIN0
P44/SOT0
P43/SCK0
RST
P42/TO0
P41/TIN0
Vss
X0
X1
(FPT-80P-M06)
* : High current pin.
(Continued)
7
MB90820 Series
(Continued)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
AVcc
AVR
P70/DA0/AN8
P71/DA1/AN9
P72/SIN1/AN10
P73/SOT1/AN11
P74/SCK1/AN12
P75/FRCK/AN13
P76/IN0/AN14
P77/IN1/AN15
P80/IN2
P81/IN3
P82/RTO0(U) *
P83/RTO1(X) *
P84/RTO2(V) *
P85/RTO3(Y) *
P86/RTO4(W) *
P87/RTO5(Z) *
C
Vss
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
X0
X1
MD0
MD1
MD2
P40/PPG1
P37/PPG0
P36
P35
P34
P33
P32
P31
P30
P27
P26
P25
P24
P23
Vcc
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
AVss
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
P61/AN1
P60/AN0
P51/INT7
P50/PPG2
P47/PWO1
P46/PWI1
P45/SIN0
P44/SOT0
P43/SCK0
RST
P42/TO0
P41/TIN0
Vss
(FPT-80P-M11)
(FPT-80P-M05)
* : High current pin.
8
Vcc
P00 *
P01 *
P02 *
P03 *
P04 *
P05 *
P06/PWI0 *
P07/PWO0 *
P10/INT0/DTTI
P11/INT1
P12/INT2
P13/INT3
P14/INT4
P15/INT5
P16/INT6
P17
P20/TIN1
P21/TO1
P22
MB90820 Series
■ PIN DESCRIPTION
Pin no.
Pin name
I/O
circuit *3
LQFP *1
QFP *2
21, 22
23, 24
X0,X1
A
17
19
RST
B
59 to 54
61 to 56
P00 to P05
C
53
55
52
54
P06
PWI0
P07
PWO0
Pin status
during
reset
Oscillating Oscillation pins.
Reset
input
General-purpose I/O ports.
C
PWC ch0 signal input pin.
General-purpose I/O ports.
C
PWC ch0 signal output pin.
General-purpose I/O ports.
INT0
53
External reset input pin.
General-purpose I/O ports.
P10
51
Function
External interrupt request input ch0 pin.
D
RTO0 to RTO5 pins for fixed-level input. This function is enabled when the waveform generator specifies its input bits.
DTTI
P11 to P16
General-purpose I/O ports.
50 to 45
52 to 47
INT1 to
INT6
D
44
46
P17
D
43
45
42
44
41,
39 to 35
43,
41 to 37
P22 to P27
D
General-purpose I/O ports.
34 to 28
36 to 30
P30 to P36
E
General-purpose I/O ports.
27
29
26
28
19
21
18
20
P20
TIN1
P21
TO1
P37
PPG0
P40
PPG1
P41
TIN0
P42
TO0
D
D
E
F
F
F
External interrupt request input ch1 to ch6 pins.
General-purpose I/O ports.
Port input
General-purpose I/O ports.
External clock input pin for reload timer ch1.
General-purpose I/O ports.
Event output pin for reload timer ch1.
General-purpose I/O ports.
Output pins for PPG timer ch0.
General-purpose I/O ports.
Output pins for PPG timer ch1.
General-purpose I/O ports.
External clock input pin for reload timer ch0.
General-purpose I/O ports.
Event output pin for reload timer ch0.
*1: FPT-80P-M05, FPT-80P-M11
*2: FPT-80P-M06
*3: See “■ I/O CIRCUIT TYPE”.
(Continued)
9
MB90820 Series
Pin no.
LQFP *1
QFP *2
16
18
15
17
14
16
13
15
12
14
11
13
10
12
9 to 2
11 to 4
Pin name
P43
SCK0
P44
SOT0
P45
SIN0
P46
PWI1
P47
PWO1
P50
PPG2
P51
INT7
P60 to P67
AN0 to AN7
I/O
circuit *3
Pin status
during
reset
General-purpose I/O ports.
F
Serial clock I/O pin for UART ch0.
General-purpose I/O ports.
F
Serial data output pin for UART ch0.
General-purpose I/O ports.
G
F
Serial data input pin for UART ch0.
Port Input
80, 79
DA0, DA1
General-purpose I/O ports.
F
Output pins for PPG timer ch2.
General-purpose I/O ports.
F
External interrupt request input ch7 pin.
General-purpose I/O ports.
H
A/D converter analog input pins.
General-purpose I/O ports.
I
D/A converter analog output pins.
A/D converter analog input pins.
P72
78
SIN1
General-purpose I/O ports.
J
Serial data input pin for UART ch1.
AN10
A/D converter analog input pins.
Analog
input
P73
75
77
SOT1
K
AN11
76
SCK1
K
FRCK
AN13
Serial clock I/O pin for UART ch1.
A/D converter analog input pins.
P75
75
Serial data output pin for UART ch1.
General-purpose I/O port.
AN12
73
General-purpose I/O ports.
A/D converter analog input pins.
P74
74
PWC ch1 signal input pin.
PWC ch1 signal output pin.
AN8, AN9
76
General-purpose I/O ports.
General-purpose I/O ports.
F
P70, P71
78, 77
Function
General-purpose I/O ports.
K
External clock input pin for free-running timer.
A/D converter analog input pins.
*1: FPT-80P-M05, FPT-80P-M11
*2: FPT-80P-M06
*3: See “■ I/O CIRCUIT TYPE”.
(Continued)
10
MB90820 Series
(Continued)
Pin no.
LQFP *1
QFP *2
Pin name
I/O
circuit *3
Pin status
during
reset
P76, P77
72, 71
74, 73
IN0, IN1
General-purpose I/O ports.
K
AN14,
AN15
70, 69
72, 71
P80, P81
IN2, IN3
Function
Analog
input
Trigger input pins for input capture ch0, ch1.
A/D converter analog input pins.
General-purpose I/O ports.
F
Trigger input pins for input capture ch2, ch3.
P82 to P87
General-purpose I/O ports.
Port input
68 to 63
70 to 65
RTO0 (U)
to
RTO5 (Z)
L
25
27
MD2
M
24, 23
26, 25
MD1, MD0
N
80
2
AVCC
–
79
1
AVR
–
1
3
AVSS
–
20, 61
22, 63
Vss
–
40, 60
42, 62
Vcc
–
62
64
C
–
Mode input
Waveform generator output pins. These pins output
the waveforms specified at the waveform generator.
Output is generated when waveform generator
output is enabled.
Input pin for operation mode specification.
Input pin for operation mode specification.
Analog power supply pin.
–
Vref + pin for the A/D converter.
Vref - is fixed to AVss internally.
Analog power supply (Ground) pin.
–
–
Power (Ground) pin.
Power pin.
Connect pin for smoothing capacitor to stabilize internal power supply.
*1: FPT-80P-M05, FPT-80P-M11
*2: FPT-80P-M06
*3: See “■ I/O CIRCUIT TYPE”.
11
MB90820 Series
■ I/O CIRCUIT TYPE
Classification
Type
Remarks
X1
P-ch
Clock
input
N-ch
Main clock (main clock crystal oscillator)
• Oscillation feedback resistor :
approx. 1 MΩ
X0
A
Standby control signal
B
• Hysteresis input
• Pull-up resistor : approx. 50 kΩ
R
R
P-ch
Pull-up control
P-ch
Digital output
C
• CMOS output
• Hysteresis input
• Selectable pull-up resistor :
approx. 50 kΩ
• IOL = 12 mA
Digital output
N-ch
Hysteresis input
Standby mode control
R
P-ch
Pull-up control
P-ch
D
Digital output
• CMOS output
• Hysteresis input
• Selectable pull-up resistor :
approx. 50 kΩ
• IOL = 4 mA
Digital output
N-ch
Hysteresis input
Standby mode control
R
P-ch
Pull-up control
P-ch
E
N-ch
Digital output
•
•
•
•
CMOS output
CMOS input
With pull-up control
IOL = 4 mA
Digital output
CMOS input
Standby mode control
(Continued)
12
MB90820 Series
Classification
Type
P-ch
F
N-ch
Remarks
Digital output
• CMOS output
• Hysteresis input
• IOL = 4 mA
Digital output
Hysteresis input
Standby mode control
P-ch
N-ch
Digital output
Digital output
• CMOS output
• Hysteresis input
• CMOS input (selectable for
UART ch0 data input pin)
• IOL = 4 mA
Hysteresis input
G
CMOS input
Standby mode control
P-ch
H
N-ch
Pout
Nout
•
•
•
•
CMOS output
CMOS input
Analog input
IOL = 4 mA
•
•
•
•
•
CMOS output
Hysteresis input
Analog output
Analog input
IOL = 4 mA
CMOS input
Analog input control
Analog input
P-ch
N-ch
I
Digital output
Digital output
Hysteresis input
Analog I/O control
Analog output
Analog input
(Continued)
13
MB90820 Series
(Continued)
Classification
Type
P-ch
N-ch
Remarks
Digital output
Digital output
• CMOS output
• Hysteresis input
• CMOS input (selectable for
UART ch1 data input pin)
• IOL = 4 mA
Hysteresis input
J
CMOS input
Analog input control
Analog input
P-ch
N-ch
K
Digital output
Digital output
•
•
•
•
CMOS output
Hysteresis input
Analog input
IOL = 4 mA
Hysteresis input
Analog input control
Analog input
P-ch
N-ch
L
Digital output
• CMOS output
• Hysteresis input
• IOL = 12 mA
Digital output
Hysteresis input
Standby mode control
M
N
14
R
Mask ROM / evaluation product
• Hysteresis input
• Pull-down resistor :
approx. 50 kΩ
Flash memory product
• CMOS input
• No pull-down resistor
Mask ROM / evaluation product
• Hysteresis input
Flash memory product
• CMOS input
MB90820 Series
■ HANDLING DEVICES
Special care is required for the following when handling the device :
• Preventing latch-up
• Stabilization of supply voltage
• Treatment of unused pins
• Using external clock
• Power supply pins (VCC /VSS )
• Pull-up/pull-down resistors
• Crystal Oscillator Circuit
• Turning-on Sequence of Power Supply to A/D Converter and D/A Converter, and Analog Inputs
• Connection of Unused Pins of A/D Converter and D/A Converter if A/D Converter and D/A Converter are unused
• Notes on energization
• Notes on During Operation of PLL Clock Mode
1. Preventing latch-up
CMOS IC chips may suffer latch-up under the following conditions :
• A voltage higher than VCC or lower than VSS is applied to an input or output pin.
• A voltage higher than the rated voltage is applied between VCC and VSS.
• The AVCC power supply is applied before the VCC voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the device.
In using the devices, take sufficient care to avoid exceeding maximum ratings.
For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVR) exceed the digital
power-supply voltage.
2. Stabilization of supply voltage
A sudden change in the supply voltage may cause the device to malfunction even within the specified VCC supply
voltage operation range. Therefore, the VCC supply voltage should be stabilized.
For reference, the supply voltage should be controlled so that VCC ripple variations (peak-to-peak values) at
commercial frequencies (50 Hz to 60 Hz) fall below 10% of the standard VCC supply voltage and the coefficient
of fluctuation does not exceed 0.1 V/ms at instantaneous power switching.
3. Treatment of unused pins
Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the
device. Therefore they must be pulled up or pulled down through resistors. In this case those resistors should
be more than 2 kΩ.
Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above
described connection.
4. Using external clock
To use external clock, drive the X0 pin and leave X1 pin open.
MB90820 series
X0
Open
X1
15
MB90820 Series
5. Power supply pins (VCC/VSS)
• If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential
are connected the inside of the device to prevent such malfunctioning as latch up.
To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level,
and observe the standard for total output current, be sure to connect the VCC and VSS pins to the power supply
and ground externally.
• Connect VCC and VSS to the device from the current supply source at a low impedance.
• As a measure against power supply noise, connect a capacitor of about 0.1 µF as a bypass capacitor between
VCC and VSS in the vicinity of VCC and VSS pins of the device.
VCC
VSS
VCC
VSS
VSS
VCC
MB90820
Series
VCC
VSS
VSS
VCC
6. Pull-up/pull-down resistors
The MB90820 series does not support internal pull-up/pull-down resistors option (Port 0 to Port 3 : built-in pullup resistors) . Use external components where needed.
7. Crystal oscillator circuit
Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass
capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic oscillator) and ground lines, and
make sure, to the utmost effort, that lines of oscillation circuit do not cross the lines of other circuits while you
design a printed circuit board.
It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with a ground
area for stabilizing the operation.
8. Turning-on sequence of power supply to A/D converter and D/A converter, and analog inputs
Make sure to turn on the A/D converter power supply, D/A converter power supply (AVCC, AVRH, AVR) and analog
inputs (AN0 to AN15) after turning-on the digital power supply (VCC).
Turn-off the digital power after turning off the A/D converter power supply, D/A converter power supply, and
analog inputs. In this case, make sure that the voltage not exceed AVR or AVCC (turning on/off the analog and
digital power supplies simultaneously is acceptable).
9. Connection of unused pins of A/D converter and D/A converter if A/D converter and
D/A converter are unused
Connect unused pins of A/D converter and D/A converter to AVCC = VCC, AVSS = AVRH = AVRL = VSS.
10. Notes on energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at
50 µs or more (0.2 V to 2.7 V) .
16
MB90820 Series
11. Notes on During Operation of PLL Clock Mode
If the PLL clock mode is selected, the microcontroller attempts to be working with the self-oscillating circuit even
when there is no external oscillator or external clock input is stopped. Performance of this operation, however,
cannot be guaranteed.
17
MB90820 Series
■ BLOCK DIAGRAM
X0
Clock control
circuit
X1
CPU
F2MC-16LX core
Timebase timer
Reset circuit
(Watchdog timer)
RST
Other pins
Vss × 2, Vcc × 2, MD0 to MD2, C
Delayed interrupt generator
Interrupt controller
7
P30 to P36
Multi-functional timer
8
P51/INT7
6
P45/SIN0
P44/SOT0
P43/SCK0
16-bit input capture
(ch0 to ch3)
UART
(ch0)
P72/SIN1/AN10
P73/SOT1/AN11
P74/SCK1/AN12
UART
(ch1)
P40/PPG1
16-bit PPG
(ch1)
P50/PPG2
16-bit PPG
(ch2)
PWC
(ch1)
P46/PWI1
P47/PWO1
4
4
16-bit free-running
timer
F2MC-16LX bus
P16/INT6 to
P11/INT1
P37/PPG0
16-bit PPG timer
(ch0)
DTP/External interrupt
P76/IN0/AN14
P77/IN1/AN15
P80/IN2
P81/IN3
P75/FRCK/AN13
P82/RTO0 (U) *
P83/RTO1 (X) *
P84/RTO2 (V) *
P85/RTO3 (Y) *
P86/RTO4 (W) *
P87/RTO5 (Z) *
16-bit output
compare
(ch0 to ch5)
Waveform
generator
P10/INT0/DTTI
P17
P06/PWI0 *
P07/PWO0 *
PWC
(ch0)
6
16-bit reload timer
(ch0)
P42/TO0
P41/TIN0
16-bit reload timer
(ch1)
P21/TO1
P20/TIN1
P22 to P27
6
CMOS I/O port 0, 1, 3, 7, 8
P00 to P05 *
CMOS I/O port 6
A/D converter
(8/10-bit)
CMOS I/O port 1, 2, 4, 5, 7
RAM
16
P60/AN0
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7
AVR
AVCC
AVSS
ROM
8-bit D/A converter
P70/DA0/AN8
P71/DA1/AN9
ROM correction
ROM mirroring
CMOS I/O port 7
Note : P00 to P07, P10 to P17, P20 to P27 and P30 to P37: With build-in resistors that can be used
as input pull-up resistors.
* : High current drive pin.
18
MB90820 Series
■ MEMORY MAP
FFFFFFH
Address #1
ROM area
Address #1 - 1H
010000H
00FFFFH
Address #2
ROM area*
(FF bank image)
: Internal access memory
Address #2 - 1H
: Access not allowed
Address #3 + 1H
Address #3
000100H
0000FFH
0000F0H
0000EFH
000000H
RAM Register
area
Peripheral area
* : In Single chip mode, the mirror function is supported.
Parts no.
Address#1
Address#2
Address#3
MB90822
FF0000H
008000H
0010FFH
MB90823
FE0000H
008000H
0010FFH
MB90F822A
FF0000H
008000H
0010FFH
MB90F823A
FE0000H
008000H
0010FFH
MB90V820
(FE0000H)
008000H
0040FFH
Note: The ROM data of bank FF is reflected to the upper address of bank 00, realizing effective use of the C
compiler small model. The lower 16-bit is assigned to the same address, enabling reference of the table on
the ROM without stating “far”. For example, if an attempt has been made to access 00C000H, the contents
of the ROM at FFC000H are accessed actually. Since the ROM area of the FF bank exceeds 32K bytes, the
whole area cannot be reflected in the image for the 00 bank. The ROM data at FF8000H to FFFFFFH looks,
therefore, as if it were the image for 008000H to 00FFFFH. Thus, it is recommended that the ROM data table
be stored in the area of FF8000H to FFFFFFH.
19
MB90820 Series
■ F2MC-16LX CPU PROGRAMMING MODEL
• Dedicated registers
AH
: Accumulator (A)
Dual 16-bit register used for storing results of calculation
etc. The two 16-bit registers can be combined to be used as
a sequence of 32-bit register.
AL
USP
: User stack pointer (USP)
The 16-bit pointer indicating the user stack address.
SSP
: System stack pointer (SSP)
The 16-bit pointer indicating the system stack address.
: Processor status (PS)
The 16-bit register indicating the system status.
PS
PC
DPR
PCB
: Program bank register (PCB)
The 8-bit register indicating the program space.
DTB
: Data bank register (DTB)
The 8-bit register indicating the data space.
USB
: User stack bank register (USB)
The 8-bit register indicating the user stack space.
SSB
: System stack bank register (SSB)
The 8-bit register indicating the system stack space.
ADB
: Additional data bank register (ADB)
The 8-bit register indicating the additional
8 bit
16 bit
32 bit
20
: Program counter (PC)
The 16-bit register indicating storing location of the current
instruction code.
: Direct page register (DPR)
The 8-bit register indicating bit 8 through 15 of the operand
address in executing of the short direct addressing.
MB90820 Series
• General-purpose registers
Maximum of 32 banks
R7
R6
RW7
R5
R4
RW6
R3
R2
RW5
R1
R0
RW4
RL3
RL2
RW3
RL1
RW2
RW1
RL0
RW0
000180H + (RP × 10H)
16-bit
• Processor status (PS)
ILM
RP
CCR
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
PS
Initial value
⎯
X
ILM2 ILM1 ILM0
0
0
0
B4
B3
B2
B1
B0
⎯
I
S
T
N
Z
V
C
0
0
0
0
0
⎯
0
1
X
X
X
X
X
: Unused
: Undefined
21
MB90820 Series
■ I/O MAP
Byte access
Word
access
Resource name
Initial
value
Port 0 data register
R/W
R/W
Port 0
XXXXXXXXB
PDR1
Port 1 data register
R/W
R/W
Port 1
XXXXXXXXB
000002H
PDR2
Port 2 data register
R/W
R/W
Port 2
XXXXXXXXB
000003H
PDR3
Port 3 data register
R/W
R/W
Port 3
XXXXXXXXB
000004H
PDR4
Port 4 data register
R/W
R/W
Port 4
XXXXXXXXB
000005H
PDR5
Port 5 data register
R/W
R/W
Port 5
XXXXXXXXB
000006H
PDR6
Port 6 data register
R/W
R/W
Port 6
XXXXXXXXB
000007H
PDR7
Port 7 data register
R/W
R/W
Port 7
XXXXXXXXB
000008H
PDR8
Port 8 data register
R/W
R/W
Port 8
XXXXXXXXB
Address
Abbreviation
000000H
PDR0
000001H
Register
000009H to
00000FH
Prohibited area
000010H
DDR0
Port 0 data direction register
R/W
R/W
Port 0
0 00 00 00 0 B
000011H
DDR1
Port 1 data direction register
R/W
R/W
Port 1
0 00 00 00 0 B
000012H
DDR2
Port 2 data direction register
R/W
R/W
Port 2
0 00 00 00 0 B
000013H
DDR3
Port 3 data direction register
R/W
R/W
Port 3
0 00 00 00 0 B
000014H
DDR4
Port 4 data direction register
R/W
R/W
Port 4
0 00 00 00 0 B
000015H
DDR5
Port 5 data direction register
R/W
R/W
Port 5
XXXXXX00B
000016H
DDR6
Port 6 data direction register
R/W
R/W
Port 6
0 00 00 00 0 B
000017H
DDR7
Port 7 data direction register
R/W
R/W
Port 7
0 00 00 00 0 B
000018H
DDR8
Port 8 data direction register
R/W
R/W
Port 8
0 00 00 00 0 B
000019H to
00001FH
Prohibited area
000020H
SMR0
Serial mode register ch0
000021H
SCR0
Serial control register ch0
000022H
SIDR0 /
SODR0
000023H
SSR0
Serial status register ch0
000024H
SMR1
Serial mode register ch1
000025H
SCR1
Serial control register ch1
000026H
SIDR1 /
SODR1
000027H
SSR1
000028H
PWCSL1
000029H
PWCSH1
00002AH
00002BH
00002CH
PWC1
DIV1
Serial input data register ch0 /
Serial output data register ch0
Serial input data register ch1 /
Serial output data register ch1
Serial status register ch1
PWC control status register
ch1
PWC data buffer register ch1
Divide ratio control register
ch1
R/W
R/W
00000000B
W, R/W W, R/W
R/W
R/W
0 00 00 10 0 B
UART ch0
R, R/W R, R/W
R/W
0 00 01 00 0 B
R/W
00000000B
W, R/W W, R/W
R/W
R/W
0 00 00 10 0 B
UART ch1
R, R/W R, R/W
R/W
00000000B
R, R/W R, R/W
R/W
R/W
R/W
XXXXXXXXB
0 00 01 00 0 B
R/W
⎯
XXXXXXXXB
0 00 00 00 0 B
PWC timer ch1
XXXXXXXXB
XXXXXXXXB
XXXXXX00B
(Continued)
22
MB90820 Series
Address
Abbreviation
Byte ac- Word access
cess
Register
00002DH,
00002EH
PCKCR
000030H
ENIR
000031H
W
W
DTP / Interrupt enable register
R/W
R/W
EIRR
DTP / Interrupt cause register
R/W
R/W
000032H
ELVRL
Request level setting register
(lower byte)
R/W
R/W
000033H
ELVRH
Request level setting register
(higher byte)
R/W
R/W
PLL clock control register
000034H
000038H
000039H
00003AH
00003BH
00003CH
00003DH
CDCR0
000044H
000045H
Clock division ratio control register
ch0
00004CH
00004DH
Communication
prescaler ch0
00XXX000 B
R/W
R/W
Communication
prescaler ch1
00XXX000 B
PCSR0
PPG period setting register ch0
⎯
W
⎯
W
R/W
R/W
XX000000 B
R/W
R/W
00000000B
PDUT0
PPG duty setting register ch0
PPG control status register ch0
11111111B
11111111B
XXXXXXXXB
16-bit PPG timer
ch0
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
11111111B
PDCR1
PPG down counter register ch1
⎯
R
PCSR1
PPG period setting register ch1
⎯
W
⎯
W
R/W
R/W
XX000000 B
R/W
R/W
00000000B
PDUT1
PCNTH1
00004BH
R/W
R/W
R
000047H
00004AH
00000000B
⎯
PCNTL1
000049H
00000000B
PPG down counter register ch0
000046H
000048H
XXXXXXXXB
PDCR0
PCNTH0
000043H
DTP/
external interrupt
ch0 to ch7
Clock division ratio control register
ch1
00003FH
000042H
00000000B
CDCR1
PCNTL0
000041H
XXXX0000 B
Prohibited area
00003EH
000040H
PLL
Prohibited area
000036H
000037H
Initial
value
Prohibited area
00002FH
000035H
Resource name
PPG duty setting register ch1
PPG control status register ch1
11111111B
XXXXXXXXB
16-bit PPG timer
ch1
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
11111111B
PDCR2
PPG down counter register ch2
⎯
R
PCSR2
PPG period setting register ch2
⎯
W
⎯
W
R/W
R/W
XX000000 B
R/W
R/W
00000000B
PDUT2
00004EH
PCNTL2
00004FH
PCNTH2
PPG duty setting register ch2
PPG control status register ch2
11111111B
XXXXXXXXB
16-bit PPG timer
ch2
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(Continued)
23
MB90820 Series
Address
000050H
Abbreviation
Byte
Word
access access
Register
Resource name
Initial
value
XXXXXXXXB
TMRR0
16-bit timer register ch0
⎯
R/W
TMRR1
16-bit timer register ch1
⎯
R/W
TMRR2
16-bit timer register ch2
⎯
R/W
000056H
DTCR0
16-bit timer control register ch0
R/W
R/W
0 00 0 00 00 B
000057H
DTCR1
16-bit timer control register ch1
R/W
R/W
0 00 0 00 00 B
000058H
DTCR2
16-bit timer control register ch2
R/W
R/W
0 00 0 00 00 B
000059H
SIGCR
Waveform control register
R/W
R/W
0 00 0 00 00 B
00005AH
CPCLRB /
CPCLR
Compare clear buffer register/
Compare clear register
⎯
R/W
Timer data register
⎯
R/W
000051H
000052H
000053H
000054H
000055H
00005BH
00005CH
00005DH
TCDT
TCCSL
Timer control status register
(lower)
R/W
R/W
00005FH
TCCSH
Timer control status register
(upper)
R/W
R/W
IPCP0
Input capture data register ch0
⎯
R
IPCP1
Input capture data register ch1
⎯
R
IPCP2
Input capture data register ch2
⎯
R
IPCP3
Input capture data register ch3
⎯
R
000061H
000062H
000063H
000064H
000065H
000066H
000067H
XXXXXXXXB
XXXXXXXXB
Waveform generator
XXXXXXXXB
XXXXXXXXB
11111111B
16-bit free-running
timer
00005EH
000060H
XXXXXXXXB
11111111B
00000000B
00000000B
16-bit free-running
timer
X0000000B
00000000B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
16-bit input capture
(ch0 to ch3)
XXXXXXXXB
000068H
PICSL01
Input capture control status
register ch0,ch1 (lower)
R/W
R/W
00000000B
000069H
PICSH01
PPG output control / Input
capture control status register
ch0,ch1 (upper)
R/W
R/W
00000000B
00006AH
ICSL23
Input capture control status
register ch2,ch3 (lower)
R/W
R/W
00000000B
00006BH
ICSH23
Input capture control status
register ch2,ch3 (upper)
R
R
XXXXXX00 B
00006CH
to
00006EH
Prohibited area
(Continued)
24
MB90820 Series
Address
Abbreviation
00006FH
ROMM
000070H
Byte
Word
access access
Register
Resource name
Initial
value
ROM mirroring
function
XXXXXXX1B
ROM mirroring function
selection register
W
W
OCCPB0 /
OCCP0
Output compare buffer register /
Output compare register ch0
⎯
R/W
OCCPB1 /
OCCP1
Output compare buffer register /
Output compare register ch1
⎯
R/W
OCCPB2 /
OCCP2
Output compare buffer register /
Output compare register ch2
⎯
R/W
OCCPB3 /
OCCP3
Output compare buffer register /
Output compare register ch3
⎯
R/W
OCCPB4 /
OCCP4
Output compare buffer register /
Output compare register ch4
⎯
R/W
00007BH
OCCPB5 /
OCCP5
Output compare buffer register /
Output compare register ch5
⎯
R/W
00007CH
OCS0
Compare control register ch0
R/W
R/W
0 00 01 10 0 B
00007DH
OCS1
Compare control register ch1
R/W
R/W
X 1 10 00 00 B
00007EH
OCS2
Compare control register ch2
R/W
R/W
0 00 01 10 0 B
00007FH
OCS3
Compare control register ch3
R/W
R/W
X 1 10 00 00 B
000080H
OCS4
Compare control register ch4
R/W
R/W
0 00 01 10 0 B
000081H
OCS5
Compare control register ch5
R/W
R/W
X 1 10 00 00 B
000082H
TMCSRL0
Timer control status register ch0
(lower)
R/W
R/W
00000000B
000083H
TMCSRH0
Timer control status register ch0
(upper)
R/W
R/W
000084H
000085H
TMR0 /
TMRD0
⎯
R/W
000086H
TMCSRL1
Timer control status register ch1
(lower)
R/W
R/W
000087H
TMCSRH1
Timer control status register ch1
(upper)
R/W
R/W
000088H
TMR1 /
TMRD1
⎯
R/W
000071H
000072H
000073H
000074H
000075H
000076H
000077H
000078H
000079H
00007AH
000089H
00008AH,
00008BH
16 bit timer register ch0 /
16-bit reload register ch0
16 bit timer register ch1 /
16-bit reload register ch1
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Output compare
(ch0 to ch5)
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
16-bit reload timer
(ch0)
XXX1 0000 B
XXXXXXXXB
XXXXXXXXB
00000000B
16-bit reload timer
(ch1)
XXX1 0000 B
XXXXXXXXB
XXXXXXXXB
Prohibited area
00008CH
RDR0
Port 0 pull-up resistor setting
register
R/W
R/W
Port 0
00000000B
00008DH
RDR1
Port 1 pull-up resistor setting
register
R/W
R/W
Port 1
00000000B
(Continued)
25
MB90820 Series
Byte ac- Word
cess
access
Address
Abbreviation
Register
00008EH
RDR2
Port 2 pull-up resistor setting
register
R/W
00008FH
RDR3
Port 3 pull-up resistor setting
register
R/W
000090H to
00009DH
Resource name
Initial
value
R/W
Port 2
00000000B
R/W
Port 3
00000000B
Address match
detection
XXXX00 00 B
Prohibited area
Program address detection
control status register
R/W
R/W
Delayed interrupt cause /
clear register
R/W
R/W
00009EH
PACSR
00009FH
DIRR
0000A0H
LPMCR
Low-power consumption mode
W, R/W W, R/W
control register
0000A1H
CKSCR
Clock selection register
0000A2H to
0000A7H
R, R/W R, R/W
Delayed interrupt XXXXXXX0 B
Low-power
consumption
control register
00011000B
1 11 11 10 0 B
Prohibited area
0000A8H
WDTC
Watchdog timer control register R, R/W R, R/W
Watchdog timer
XXXXX111 B
0000A9H
TBTC
Timebase timer control register W, R/W W, R/W
Timebase timer
1 XX0 0 10 0 B
Flash memory
interface circuit
000X0000 B
0000AAH to
0000ADH
0000AEH
Prohibited area
FMCS
Flash memory control status
register
0000AFH
R, R/W R, R/W
Prohibited area
0000B0H
ICR00
Interrupt control register 00
R/W
R/W
00000111B
0000B1H
ICR01
Interrupt control register 01
R/W
R/W
0 00 00 11 1 B
0000B2H
ICR02
Interrupt control register 02
R/W
R/W
0 00 00 11 1 B
0000B3H
ICR03
Interrupt control register 03
R/W
R/W
0 00 00 11 1 B
0000B4H
ICR04
Interrupt control register 04
R/W
R/W
0 00 00 11 1 B
0000B5H
ICR05
Interrupt control register 05
R/W
R/W
0 00 00 11 1 B
0000B6H
ICR06
Interrupt control register 06
R/W
R/W
0 00 00 11 1 B
0000B7H
ICR07
Interrupt control register 07
R/W
R/W
0000B8H
ICR08
Interrupt control register 08
R/W
R/W
0000B9H
ICR09
Interrupt control register 09
R/W
R/W
0 00 00 11 1 B
0000BAH
ICR10
Interrupt control register 10
R/W
R/W
0 00 00 11 1 B
0000BBH
ICR11
Interrupt control register 11
R/W
R/W
0 00 00 11 1 B
0000BCH
ICR12
Interrupt control register 12
R/W
R/W
0 00 00 11 1 B
0000BDH
ICR13
Interrupt control register 13
R/W
R/W
0 00 00 11 1 B
0000BEH
ICR14
Interrupt control register 14
R/W
R/W
0 00 00 11 1 B
0000BFH
ICR15
Interrupt control register 15
R/W
R/W
0 00 00 11 1 B
Interrupt
controller
0 00 00 11 1 B
0 00 00 11 1 B
(Continued)
26
MB90820 Series
(Continued)
Address
Abbreviation
0000C0H
PWCSL0
0000C1H
PWCSH0
PWC control status register
ch0
PWC0
PWC data buffer register ch0
0000C2H
0000C3H
Byte ac- Word
cess
access
Register
R/W
Resource name
R/W
00000000B
R, R/W R, R/W
⎯
R/W
Initial
value
0 00 00 00 0 B
PWC timer (ch0)
XXXXXXXXB
XXXXXXXXB
0000C4H
DIV0
Divide ratio control register
ch0
R/W
R/W
0000C5H
ADER0
A/D input enable register 0
R/W
R/W
0000C6H
ADCS0
A/D control status register 0
R/W
R/W
0000C7H
ADCS1
A/D control status register 1 W, R/W W, R/W
0000C8H
ADCR0
A/D data register 0
R
R
0000C9H
ADCR1
A/D data register 1
R
R
0000CAH
ADSR0
A/D setting register 0
R/W
R/W
0 00 00 00 0 B
0000CBH
ADSR1
A/D setting register 1
R/W
R/W
0 00 00 00 0 B
0000CCH
DAT0
D/A data register 0
R/W
R/W
XXXXXXXXB
0000CDH
DAT1
D/A data register 1
R/W
R/W
0000CEH
DACR0
D/A control register 0
R/W
R/W
0000CFH
DACR1
D/A control register 1
R/W
R/W
0000D0H
ADER1
A/D input enable register 1
R/W
R/W
0000D1H to
0000EFH
Prohibited area
0000F0H to
0000FFH
External area
XXXXXX00B
Port 6, A/D
1 11 11 11 1 B
000XXXX0 B
00 00 00 0 X B
8/10-bit A/D converter
8-bit D/A converter
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXX0B
XXXXXXX0B
Port 7, A/D
1 11 11 11 1 B
001FF0H
PADRL0
Program address detection
register 0 (lower)
R/W
R/W
XXXXXXXXB
001FF1H
PADRM0
Program address detection
register 0 (middle)
R/W
R/W
XXXXXXXXB
001FF2H
PADRH0
Program address detection
register 0 (higher)
R/W
R/W
001FF3H
PADRL1
Program address detection
register 1 (lower)
R/W
R/W
001FF4H
PADRM1
Program address detection
register 1 (middle)
R/W
R/W
XXXXXXXXB
001FF5H
PADRH1
Program address detection
register 1 (higher)
R/W
R/W
XXXXXXXXB
Address match
detection
XXXXXXXXB
XXXXXXXXB
• Meaning of abbreviations used for reading and writing
R/W: Read and write enabled
R : Read-only
W : Write-only
• Explanation of initial values
0 : The bit is initialized to “0”.
1 : The bit is initialized to “1”.
X : The initial value of the bit is undefined.
27
MB90820 Series
■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER
Interrupt cause
Reset
INT9 instruction
Exception processing
A/D converter conversion termination
Output compare ch0 match
End of measurement by PWC timer ch0 /
PWC timer ch0 overflow
16-bit PPG timer ch0
Output compare ch1 match
16-bit PPG timer ch1
Output compare ch2 match
16-bit reload timer ch1 underflow
Output compare ch3 match
DTP/ext. interrupt ch0/ch1 detection
DTTI
Output compare ch4 match
DTP/ext. interrupt ch2/ch3 detection
Output compare ch5 match
End of measurement by PWC timer ch1 /
PWC timer ch1 overflow
DTP/ext. interrupt ch4 detection
DTP/ext. interrupt ch5 detection
DTP/ext. interrupt ch6 detection
DTP/ext. interrupt ch7 detection
Waveform generator 16-bit timers ch0/ch1/
ch2
underflow
16-bit reload timer ch0 underflow
16-bit free-running timer zero detect
16-bit PPG timer ch2
Input capture ch0/ch1
16-bit free-running timer compare clear
Input capture ch2/ch3
Timebase timer
UART ch1 receive
UART ch1 send
UART ch0 receive
UART ch0 send
Flash memory status
Delayed interrupt generator module
EI2OS
support
×
×
×
Interrupt vector
Number
Address
#08
#09
#10
#11
#12
08H
09H
0AH
0BH
0CH
FFFFDCH
FFFFD8H
FFFFD4H
FFFFD0H
FFFFCCH
#13
0DH
FFFFC8H
#14
#15
#16
#17
#18
#19
0EH
0FH
10H
11H
12H
13H
FFFFC4H
FFFFC0H
FFFFBCH
FFFFB8H
FFFFB4H
FFFFB0H
#20
14H
FFFFACH
#21
#22
#23
15H
16H
17H
FFFFA8H
FFFFA4H
FFFFA0H
#24
18H
FFFF9CH
#25
#26
#27
#28
19H
1AH
1BH
1CH
FFFF98H
FFFF94H
FFFF90H
FFFF8CH
#29
1DH
FFFF88H
#30
#31
#32
#33
#34
#35
#36
#37
#38
#39
#40
#41
#42
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
FFFF84H
FFFF80H
FFFF7CH
FFFF78H
FFFF74H
FFFF70H
FFFF6CH
FFFF68H
FFFF64H
FFFF60H
FFFF5CH
FFFF58H
FFFF54H
Interrupt control
register
ICR
Address
⎯
⎯
⎯
⎯
⎯
⎯
ICR00
0000B0H
ICR01
0000B1H
ICR02
0000B2H
ICR03
0000B3H
ICR04
0000B4H
ICR05
0000B5H
ICR06
0000B6H
ICR07
0000B7H
ICR08
0000B8H
ICR09
0000B9H
ICR10
0000BAH
ICR11
0000BBH
ICR12
0000BCH
ICR13
0000BDH
ICR14
0000BEH
ICR15
0000BFH
: Can be used and support the EI2OS stop request.
: Can be used and interrupt request flag is cleared by EI2OS interrupt clear signal.
× : Cannot be used.
: Usable when an interrupt cause that shares the ICR is not used.
28
Priority
High
Low
MB90820 Series
■ PERIPHERAL RESOURCES
1. Low-power Consumption Control Circuit
The MB90820 series has the following CPU operating mode configured by selection of an operating clock and
clock operation control.
• Clock mode
PLL clock mode : A PLL clock that is a multiple of the oscillation clock (HCLK) frequency is used to operate
the CPU and peripheral functions.
Main clock mode : The main clock, with a frequency one-half that of the oscillation clock (HCLK), is used to
operate the CPU and peripheral functions. In main clock mode, the PLL divide circuit
is inactive.
• CPU intermittent operation mode
CPU intermittent operation mode causes the CPU to operate intermittently, while high-speed clock pulses are
supplied to peripheral functions, reducing power consumption. In CPU intermittent operation mode, clock
pulses are supplied intermittently to the CPU when it is accessing a register, internal memory, a peripheral
function, or an external unit.
• Standby mode
In standby mode, the low power consumption control circuit reduces power consumption by stopping;
• The supply of the clock to CPU (sleep mode)
• CPU and peripheral functions (timebase timer mode)
• The oscillation clock itself (stop mode)
• PLL sleep mode
PLL sleep mode is activated to stop the CPU operating clock when the microcontroller enters PLL clock mode;
other components continue to operate on the PLL clock.
• Main sleep mode
Main sleep mode is activated to stop the CPU operating clock when the microcontroller enters main clock
mode; other components continue to operate on the main clock.
• PLL timebase timer mode
PLL timebase timer mode causes microcontroller operation, with the exception of the oscillation clock, PLL
clock and timebase timer, to stop. All functions other than the timebase timer are deactivated.
• Main timebase timer mode
Main timebase timer mode causes microcontroller operation, with the exception of the oscillation clock, main
clock and the timebase timer, to stop. All functions other than the timebase timer are deactivated.
• Stop mode
Stop mode causes the source oscillation to stop. All functions are deactivated.
29
MB90820 Series
(1) Register configuration
Clock Selection Register
Address: 00000A1H
Read/write
Initial value
15
14
13
12
11
10
9
8
Reserved
MCM
WS1
WS0
Reserved
MCS
CS1
CS0
R/W
1
R
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
0
R/W
0
15
14
13
12
11
10
9
8
−
−
−
−
−
−
−
−
X
X
X
X
W
0
PLL Clock Control Register
Address: 000002FH
Read/write
Initial value
Reserved Reserved Reserved
W
0
W
0
Bit
CKSCR
Bit
CS2
PCKCR
W
0
Low-power Consumption Mode Control Register
Address: 0000A0H
Read/write
Initial value
30
7
6
5
4
3
2
1
0
STP
SLP
SPL
RST
TMD
CG1
CG0
Reserved
W
0
W
0
R/W
0
W
1
W
1
R/W
0
R/W
0
R/W
0
Bit
LPMCR
MB90820 Series
(2) Block diagram
Low power mode control register (LPMCR)
STP
RST
SLP
SPL
TMD
RST
CG1 CG0 RESV
Pin
Pin high
impedance
control circuit
Pin Hi-z control
Internal reset
generation
circuit
Internal reset
CPU intermittent
operation selecter
Select intermittent cycles
CPU clock
control circuit
Release reset
3
CPU clock
Stop and sleep signals
Standby control
circuit
Cancel interruption
Stop signal
Machine clock
Peripheral clock
control circuit
Oscillation
stabilization waiting
time is passed
Clock generator
Peripheral clock
Clock selector
Oscillation stabilization
waiting time interval selector
3
2
×1 ×2 ×3 ×4 ×6
PLL multiplier
circuit
Reserved
MCM WS1 WS0
Reserved
MCS CS1
CS0
Clock selection register (CKSCR)
X0
X1
Divided
by 2
Pin
Pin
System clock
generation circuit
Main clock
Divided
by 512
Divided
by 2
CS2
PLL clock control
register (PCKCR)
Divided
by 4
Divided
by 2
Divided
by 2
Timebase timer
31
MB90820 Series
2. I/O Ports
(1) Outline of I/O ports
Each I/O port outputs data from CPU to I/O pins or inputs signals from I/O pins to CPU through port data register
(PDR). Direction of the data flow (input or output) for each I/O pin can be designated in bit unit by port data
direction register (DDR). The function of each port and the resource I/O multiplexed with it are described below:
•
•
•
•
•
•
•
•
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
:
:
:
:
:
:
:
:
General-purpose I/O port/resource (PWC timer)
General-purpose I/O port/resources (DTP / Multi-functional timer)
General-purpose I/O port/resource (16-bit reload timer)
General-purpose I/O port/resource (16-bit PPG timer)
General-purpose I/O port/resources (16-bit PPG timer / 16-bit reload timer / UART / PWC)
General-purpose I/O port/resources (16-bit PPG timer / DTP)
General-purpose I/O port/resource (8/10-bit A/D converter)
General-purpose I/O port/resources (8/10-bit A/D converter / 8-bit D/A converter / UART/
16-bit free-running timer / 16-bit input capture)
• Port 8 : General-purpose I/O port/resources (16-bit input capture / Multi-functional timer)
(2) Register configuration
Register
Read/Write
Address
Initial value
Port 0 data register (PDR0)
R/W
000000H
XXXXXXXXB
Port 1 data register (PDR1)
R/W
000001H
XXXXXXXXB
Port 2 data register (PDR2)
R/W
000002H
XXXXXXXXB
Port 3 data register (PDR3)
R/W
000003H
XXXXXXXXB
Port 4 data register (PDR4)
R/W
000004H
XXXXXXXXB
Port 5 data register (PDR5)
R/W
000005H
XXXXXXXXB
Port 6 data register (PDR6)
R/W
000006H
XXXXXXXXB
Port 7 data register (PDR7)
R/W
000007H
XXXXXXXXB
Port 8 data register (PDR8)
R/W
000008H
XXXXXXXXB
Port 0 data direction register (DDR0)
R/W
000010H
00000000 B
Port 1 data direction register (DDR1)
R/W
000011H
00000000 B
Port 2 data direction register (DDR2)
R/W
000012H
00000000 B
Port 3 data direction register (DDR3)
R/W
000013H
00000000 B
Port 4 data direction register (DDR4)
R/W
000014H
00000000 B
Port 5 data direction register (DDR5)
R/W
000015H
XXXXXX00B
Port 6 data direction register (DDR6)
R/W
000016H
00000000 B
Port 7 data direction register (DDR7)
R/W
000017H
00000000 B
Port 8 data direction register (DDR8)
R/W
000018H
00000000 B
A/D input enable register (ADER0)
R/W
0000C5H
11111111 B
A/D input enable register (ADER1)
R/W
0000D0H
11111111 B
Port 0 pull-up resistor setting register (RDR0)
R/W
00008CH
00000000 B
Port 1 pull-up resistor setting register (RDR1)
R/W
00008DH
00000000 B
Port 2 pull-up resistor setting register (RDR2)
R/W
00008EH
00000000 B
Port 3 pull-up resistor setting register (RDR3)
R/W
00008FH
00000000 B
R/W: Read/write enabled
X : Undefined
32
MB90820 Series
(3) Block diagram
• Block diagram of Port 0 (P00 to P06), Port 1 (P17) and Port 2 (excluding P21) pins
Standby control (SPL=1)
RDR
Resource input
Port data register (PDR)
Internal data bus
Pull-up resistor
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
• Block diagram of Port 0 (P07) and Port 2 (P21) pins
Standby control (SPL=1)
RDR
Resource output
Port data register (PDR)
Resource input
Resource output enable
Internal data bus
Pull-up resistor
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
33
MB90820 Series
• Block diagram of Port 1 (P10 to P16) pins
Standby control (SPL=1)
RDR
Resource input
Port data register (PDR)
Pull-up resistor
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
External
interrupt
enable
DDR write
DDR read
Standby control (SPL=1)
• Block diagram of Port 3 (excluding P37) pins
Standby control (SPL=1)
RDR
Port data register (PDR)
Pull-up resistor
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
34
MB90820 Series
• Block diagram of Port 3 (P37) pin
Standby control (SPL=1)
RDR
Resource output
Port data register (PDR)
Resource output enable
Pull-up resistor
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
• Block diagram of Port 4 pins (excluding P41, P45 and P46) pins
Resource output
Port data register (PDR)
Resource input
Resource output enable
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
35
MB90820 Series
• Block diagram of Port 4 (P41 and P46) pins
Resource input
Port data register (PDR)
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
• Block diagram of P45 pin
UART ch0 data input
UART ch0 data input
level selection bit
Port data register (PDR)
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
36
MB90820 Series
• Block diagram of Port 5 (P50) pin
Resource output
Port data register (PDR)
Resource input
Resource output enable
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
• Block diagram of Port 5 (P51) pin
Resource input
Port data register (PDR)
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
External
interrupt
enable
DDR write
DDR read
Standby control (SPL=1)
37
MB90820 Series
• Block diagram of Port 6 pins
A/D converter input
A/D converter channel selection bit
Port data register (PDR)
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
ADER
• Block diagram of Port 7 (P70 and P71) pins
A/D converter channel selection bit
A/D converter input
Port data register (PDR)
D/A converter output
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
ADER
D/A converter output enable bit
38
Standby control (SPL=1)
MB90820 Series
• Block diagram of P72 pin
A/D converter channel selection bit
A/D converter input
UART ch1 data input
UART ch1 data input
level selection bit
Port data register (PDR)
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
ADER
• Block diagram of Port 7(P73 and P74) pins
A/D converter input
A/D converter channel selection bit
Resource input
Resource output
Port data register (PDR)
Resource output enable
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
ADER
39
MB90820 Series
• Block diagram of Port 7 (P75 to P77) pins
A/D converter input
A/D converter channel selection bit
Resource input
Port data register (PDR)
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
ADER
• Block diagram of Port 8 (P80 and P81) pins
Resource input
Port data register (PDR)
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
40
MB90820 Series
• Block diagram of Port 8 (P82 to P87) pins
Resource output
Port data register (PDR)
Resource input
Resource output enable
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
41
MB90820 Series
3. Timebase Timer
The timebase timer is an 18-bit free-running counter (timebase counter) that counts up in synchronization with
the internal count clock (divided by 1/2 of oscillation clock).
Features of timebase timer :
• Generates the interruption at counter-overflow
• Supports for EI2OS
• Interval timer function:
Generates an interrupt at four different time intervals
• Clock supply function:
Four different clock can be selected as watchdog timer’s count clock
Supply clock for oscillation stabilization
(1) Register configuration
Timebase Timer Control Register
15
Address: 0000A9H
Reserved
Read/write
Initial value
R/W
1
14
13
12
11
10
9
8
−
−
TBIE
TBOF
TBR
TBC1
TBC0
−
−
X
X
R/W
0
R/W
0
W
1
R/W
0
R/W
0
Bit number
TBTC
(2) Block diagram
To watchdog timer
Timebase
timer counter
Divided by
2 of HCLK
× 2 1 × 22 × 2 3 . . .
...
× 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
OF
OF
OF
OF
⎞ To the oscillation
⎟ setting time selector
⎠ in the clock control
section
Counter clear
Power-on reset
Stop mode start
CKSCR: MCS = 1, 0*1
Counter
clear circuit
Interval
timer selector
TBOF set
TBOF clear
Timebase timer
interrupt signal
#36 (24H)*2
Reserved
—
—
TBIE TBOF
OF: Overflow
HCLK: Oscillation clock
*1: Switching of the machine clock from the oscillation clock to the PLL clock
*2: Interrupt number
42
Timebase timer
TBR TBC1 TBC0 control register
(TBTC)
MB90820 Series
4. Watchdog Timer
The watchdog timer is a 2-bit counter that uses the timebase timer’s supply clock as the count clock. After
activation, if the watchdog timer is not cleared within a given period, the CPU will be reset.
• Features of watchdog timer :
Reset CPU at four different time intervals
Indicate the reset causes by status bits
(1) Register configuration
Watchdog Timer Control Register
Address: 0000A8H
7
6
5
4
3
2
1
0
Bit
PONR
−
WRST
ERST
SRST
WTE
WT1
WT0
WDTC
R
X
R
X
R
X
W
1
W
1
W
1
Read/write
Initial value
−
R
X
X
(2) Block diagram
Watchdog timer control register (WDTC)
PONR
WRST ERST SRST WTE
WT1
WT0
2
Watchdog timer
Activation
with CLR
Start of sleep mode
Start of hold status mode
Start of stop mode
Counter clear
control circuit
Count clock
selector
2-bit
counter
CLR
Over
flow
Watchdog
reset generator
To the internal
reset generator
CLR
Clear
4
Timebase timer counter
Divided by 1/2 of HCLK
×21
×22
…
×28 ×29 ×210 ×211 ×212 ×213 ×214 ×215 ×216 ×217 ×218
HCLK : Oscillation clock frequency
43
MB90820 Series
5. 16-bit reload timer ( × 2)
The 16-bit reload timer provides two operating mode, internal clock mode and event count mode. In each
operating mode, the 16-bit down counter can be reloaded (reload mode) or stopped by underflow (one-shot
mode).
Output pins TO1 and TO0 are able to output different waveform according to the counter operating mode. TO1
and TO0 toggles when counter underflows if counter is operated as reload mode. TO1 and TO0 output specified
level (H or L) during counting if the counter is in one-shot mode.
Features of the 16-bit reload timer :
• Interrupt when timer underflows
• Supports for EI2OS
• Internal clock operating mode :
Three internal count clocks can be selected.
Counter can be activated by software or external trigger (signal at TIN1 and TIN0 pins).
Counter can be reloaded or stopped when underflow after activated.
• Event count operating mode :
Counter counts down one by one with specified edge at TIN1 and TIN0 pins.
Counter can be reloaded or stopped when underflow.
(1) Register configuration
16-bit Timer Register (Upper)/16-bit Reload Timer Register (Upper)
15
14
13
12
11
10
8
Address: ch0 000085H
ch1 000089H
D15
D14
D13
D12
D11
D10
D09
D08
Read/write
Initial value
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
3
2
1
16-bit Timer Register (Lower)/16-bit Reload Timer Register (Lower)
7
6
5
4
Address: ch0 000084H
ch1 000088H
Read/write
Initial value
D06
D05
D04
D03
D02
D01
D00
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
Address: ch0 000083H
ch1 000087H
−
Read/write
Initial value
Read/write
Initial value
13
12
11
10
9
−
FSEL
CSL1
CSL0 MOD2 MOD1
−
−
−
X
X
X
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
5
4
3
2
1
7
6
MOD0 OUTE OUTL RELD
R/W
0
R/W
0
R/W
0
R/W
0
0
INTE
UF
CNTE
TRG
R/W
0
R/W
0
R/W
0
R/W
0
Note : Registers TMR0, TMR1/TMRD0, TMRD1 are word access only.
Bit
TMR0, TMR1 /
TMRD0, TMRD1
8
−
Timer Control Status Register (Lower)
Address: ch0 000082H
ch1 000086H
14
Bit
TMR0, TMR1 /
TMRD0, TMRD1
D07
Timer Control Status Register (Upper)
15
44
9
Bit
TMCSRH0,
TMCSRH1
0
Bit
TMCSRL0,
TMCSRL1
MB90820 Series
(2) Block diagram
Internal data bus
TMRD0*1
<TMRD1>
16-bit reload register
Reload signal
TMR0*1
<TMR1>
16-bit timer register (down-counter)
CLK
Clock 1
selector
0
Reload
control
circuit
UF
1-bit
down-counter
FSEL: Initial value "1"
Machine
clock φ
Gate
input
Prescaler
3
Clock
judgement
circuit
Clear
Output control circuit
Input
control
circuit
P41/TIN0*1
<P20/TIN1>
Clock
selector
Reversed
Output signal
generation
circuit
External clock
Count clock generation circuit
3
Function select
_
to UART ch0, ch1*1
<to A/D converter>
CLK
Internal
clock
Pin
Wait signal
_
_
2
P42/TO0*1
<P21/TO1>
EN
Select
signal
FSEL CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE
Timer control status register (TMCSR0) *1
<TMCSR1>
*1: Used for ch0/1. <> indicates ch1.
*2: Interrupt number
Pin
Operation
control
circuit
UF CNTE TRG
Interrupt request signal
#30*2
<#18>
45
MB90820 Series
6. 16-bit PPG Timer ( × 3)
The 16-bit PPG timer consists of a 16-bit down counter, prescaler, 16-bit period setting register, 16-bit duty
setting register, 16-bit control register and a PPG output pin. This module can be used to output pulses synchronized by software trigger or GATE signal from Multi-functional timer, refer to “7. Multi-functional Timer”.
Features of 16-bit PPG timer :
• Two operating mode : PWM and One-shot mode
• 8 types of counter operation clock (φ, φ/2, φ/4, φ/8, φ/16, φ/32, φ/64, φ/128) can be selected
• Interrupt is generated when trigger signal or counter borrow occurs, or when PPG output is changed
• Supports for EI2OS
(1) Register configuration
PPG Control Status Register (Upper)
Address: ch0 00003FH
ch1 000047H
ch2 00004FH
15
14
13
12
11
R/W
0
R/W
0
R/W
0
R/W
0
9
R/W
0
R/W
0
R/W
0
Bit
8
PCNTH0 to
PCNTH2
CKS1 CKS0 PGMS
CNTE STGR MDSE RTRG CKS2
Read/write
Initial value
10
R/W
0
PPG Control Status Register (Lower)
7
Address: ch0 00003EH
ch1 000046H
ch2 00004EH
Read/write
Initial value
−
−
−
−
X
X
6
5
4
3
2
1
IREN
IRQF
IRS1
IRS0
POEN OSEL
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
Bit
PCNTL0 to
PCNTL2
R/W
0
PPG Duty Setting Register (Upper)
15
14
13
12
11
10
9
8
Address: ch0 00003DH
ch1 000045H
DU15 DU14 DU13 DU12 DU11 DU10 DU09 DU08
ch2 00004DH
Read/write
Initial value
W
X
W
X
PPG Duty Setting Register (Lower)
Address: ch0 00003CH
ch1 000044H
ch2 00004CH
DU07
W
X
W
X
W
X
W
X
W
X
7
6
5
4
3
DU06
DU05
DU04
DU03 DU02
Bit
PDUT0 to
PDUT2
W
X
2
1
DU01
DU00
Bit
0
PDUT0 to
PDUT2
Read/write
Initial value
W
W
W
W
W
W
W
W
X
X
X
X
X
X
X
X
PPG Period Setting Register (Upper)
15
14
13
12
11
10
9
8
Address: ch0 00003BH
ch1 000043H
CS15 CS14 CS13 CS12 CS11 CS10 CS09 CS08
ch2 00004BH
Read/write
Initial value
W
X
W
X
W
X
W
X
W
X
W
X
W
X
Bit
PCSR0 to
PCSR2
W
X
(Continued)
46
MB90820 Series
(Continued)
PPG Period Setting Register (Lower)
Address: ch0 00003AH
ch1 000042H
ch2 00004AH
CS07
Read/write
Initial value
7
6
5
CS06 CS05
W
X
W
X
4
CS04 CS03
W
X
W
X
3
2
1
CS02
CS01
CS00
W
X
W
X
W
X
W
X
PPG Down Counter Register (Upper)
15
14
13
12
11
10
Address: ch0 000039H
ch1 000041H
DC15 DC14 DC13 DC12 DC11 DC10 DC09
ch2 000049H
Read/write
Initial value
R
1
0
9
PCSR0 to
PCSR2
8
Bit
PDCR0 to
PDCR2
DC08
R
1
R
1
R
1
R
1
R
1
R
1
R
1
7
6
5
4
3
2
1
DC04
DC03
DC02
DC01
DC00
R
1
R
1
R
1
R
1
R
1
Bit
PPG Down Counter Register (Lower)
Address: ch0 000038H
ch1 000040H
ch2 000048H
Read/write
Initial value
DC07 DC06 DC05
R
1
R
1
R
1
Bit
0
PDCR0 to
PDCR2
Note : Registers PDCR0 to PDCR2, PCSR0 to PCSR2 and PDUT0 to PDUT2 are word access only.
47
MB90820 Series
(2) Block diagram
P eriod S etting B uffer R egister 0/1/2
D uty S etting B uffer R egister 0/1/2
Prescaler
CKS1
CKS0
Period Setting Register 0/1/2
1/1
1/2
1/4
1/8
1/16
1/32
1/64
1/128
CLK
LOAD
16-bit down counter
MDSE PGMS OSEL POEN
STOP
START
BORROW
P in
S
Q
PPG0 (multi-functional timer)
or
PPG1 (multi-pulse generator)
or
PPG2
R
Interrupt
selection
Interrupt
#14, #16, #32
GATE - from multi-functional
timer (for PPG0 only)
IRS1
Edge detection
(for PPG1 & PPG2)
STGR CNTE RTRG
48
P37/PPG0
or
P40/PPG1
or
P50/PPG2
Machine clock φ
Down Counter Register 0/1/2
F2MC-16LX bus
Duty Setting Register 0/1/2
Comparator
CKS2
IRS0
IRQF
IREN
MB90820 Series
7. Multi-functional Timer
The 16-bit multi-functional timer module consists of one 16-bit free-running timer, four input capture circuits, six
output comparators and one channel of 16-bit PPG timer. This module allows six independent waveforms
generated by PPG timer or waveform generator to be outputted. With the 16-bit free-running timer and the input
capture circuit, input pulse width and external clock period measurement can be done.
(1) 16-bit free-running timer (1 channel)
• The 16-bit free-running timer consists of a 16-bit up counter, 16-bit up-down counter, timer control status
register, 16-bit compare clear register (with buffer register) and a prescaler.
• 8 types of counter operation clock (φ, φ/2, φ/4, φ/8, φ/16, φ/32, φ/64, φ/128) can be selected. (φ is the machine
clock.)
• Two types of interrupt causes :
- Compare clear interrupt is generated when there is a comparing match with compare clear register and 16bit free-running timer.
- Zero detection interrupt is generated while 16-bit free-running timer is detected as zero in count value.
• EI2OS supported.
• Compare-clear register buffer provided :
The selectable buffer enables the 16-bit free-running timer update its compare-clear register automatically
without stop the timer operation. User can read the next compare-clear value to the compare-clear register
when the timer is running. The compare-clear register will be updated when the timer value is “0000H”
• Reset, software clear, compare match with compare clear register in up-count mode will reset the counter
value to “0000H”.
• Supply clock to output compare module :
The prescaler output is acted as the count clock of the output compare.
(2) Output compare module ( 6 channels)
• The output compare module consists of six 16-bit output compare registers (with selectable buffer register),
compare output latch and compare control registers. An interrupt is generated and output level is inverted
when the value of 16-bit free-running timer and output compare register are matched.
• 6 output compare registers can be operated independently.
• Output pins and interrupt flag are corresponding to each output compare register.
• 2 output compare registers can be paired to control the output pins.
• Inverts output pins by using 2 output compare registers together.
• Setting the initial value for each output pin is possible.
• Interrupt is generated when there is a comparing match with output compare register and 16-bit free-running
timer.
• EI2OS supported.
(3) Input capture module (4 channels)
Input capture consists of 4 independent external input pins, the corresponding input capture data register and
input capture control status register. By detecting any edge of the input signal from the external pin, the value
of the 16-bit free-running timer can be stored in the capture register and an interrupt is generated simultaneously.
• Operations synchronized with the 16-bit free-running timer’s count clock.
• 3 types of trigger edge (rising edge, falling edge and both edge) of the external input signal can be selected
and there is indication bit to show the trigger edge is rising or falling.
• 4 input captures can be operated independently.
• Two independent interrupts are generated when detecting a valid edge from external input.
• EI2OS supported.
49
MB90820 Series
(4) 16-bit PPG timer (1 channel)
The 16-bit PPG timer 0 is used to provide a PPG signal for waveform generator. (See section “6. 16-bit PPG
Timer (× 3) ”.)
(5) Waveform generator module
The waveform generator consists of three 16-bit timer registers, three 16-bit timer control registers and a waveform control register.
With waveform generator, it is possible to generate real time output, 16-bit PPG waveform output, non-overlap
3-phase waveform output for inverter control and DC chopper waveform output.
• It is possible to generate a non-overlap waveform output based on dead-time of 16-bit timer. (Dead-time timer
function)
• It is possible to generate a non-overlap waveform output when realtime output is operated in 2-channel mode.
(Dead-time timer function)
• By detecting realtime output compare match, GATE signal of the PPG timer operation will be generated to
start or stop PPG timer operation. (GATE function)
• When a match is detected by real time output compare, the 16-bit timer is activated. The PPG timer can be
started or stopped easily by generating a GATE signal for PPG operation until the 16-bit timer stops. (GATE
function)
• Force to stop output waveform using DTTI pin input.
• Interrupt is generated when DTTI active or 16-bit timer underflow.
• EI2OS is supported.
(6) Register configuration
• 16-bit free-running timer registers
Timer Control Status Register (Upper)
15
14
Address: 00005FH
12
11
10
9
8
ECKE IRQZF IRQZE
MSI2
MSI1
MSI0
ICLR
ICRE
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
4
3
2
1
0
SCLR
CLK2
CLK1
CLK0
Read/write
Initial value
R/W
0
Timer Control Status Register (Lower)
7
6
Address: 00005EH
Read/write
Initial value
−
−
BFE
13
R/W
0
5
STOP MODE
R/W
0
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
Address: 00005DH
T15
T14
T13
T12
T11
T10
T09
T08
Read/write
Initial value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Timer Data Register (Lower)
7
6
5
4
3
2
1
0
Address: 00005CH
T07
T06
T05
T04
T03
T02
T01
T00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Timer Data Register (Upper)
Read/write
Initial value
X
Bit
TCCSH
Bit
TCCSL
Bit
TCDT
Bit
TCDT
(Continued)
50
MB90820 Series
(Continued)
Compare Clear Buffer Register / Compare Clear Register (Upper)
15
14
13
12
11
10
9
8
Address: 00005BH
CL15
CL14
CL13
CL12
CL11
CL10
CL09
CL08
Read/write
Initial value
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Compare Clear Buffer Register / Compare Clear Register (Lower)
7
6
5
4
3
Address: 00005AH
2
1
0
Bit
CPCLRB/CPCLR
Bit
CL07
CL06
CL05
CL04
CL03
CL02
CL01
CL00
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Read/write
Initial value
CPCLRB/CPCLR
Note : Registers TCDT, CPCLRB/CPCLR are word access only.
• Output compare registers
Compare Control Register (Upper)
15
Address: ch1 00007DH
ch3 00007FH
ch5 000081H
−
Read/write
Initial value
X
14
13
12
11
10
9
8
Bit
OCS1/3/5
BTS1
BTS0 CMOD OTE1
R/W
1
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
IOP1
IOP0
IOE1
IOE0
BUF1
BUF0
CST1 CST0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
R/W
1
−
OTE0 OTD1
OTD0
Compare Control Register (Lower)
Address: ch0 00007CH
ch2 00007EH
ch4 000080H
Read/write
Initial value
OCS0/2/4
R/W
0
R/W
0
Output Compare Buffer Register / Output Compare Register (Upper)
Address: ch0 000071H
ch1 000073H
ch2 000075H
15
14
13
12
11
10
9
8
ch3 000077H
ch4 000079H
ch5 00007BH
OP15 OP14 OP13 OP12 OP11 OP10 OP09 OP08
Read/write
Initial value
Bit
0
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
2
1
Bit
OCCPB0 to
OCCPB5/
OCCP0 to
OCCP5
Output Compare Buffer Register / Output Compare Register (Lower)
Address: ch0 000070H
ch1 000072H
ch2 000074H
ch3 000076H
ch4 000078H
ch5 00007AH
Read/write
Initial value
7
6
5
4
3
OP07
OP06
OP05
OP04
OP03
OP02 OP01
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
OP00
R/W
X
0
Bit
OCCPB0 to
OCCPB5/
OCCP0 to
OCCP5
Note : Register OCCPB0 to OCCPB5 and OCCP0 to OCCP5 are word access only.
51
MB90820 Series
• Input capture registers
Input Capture Control Status Register (2/3) (Upper)
15
14
13
12
11
10
9
8
Address: 00006BH
−
−
−
−
−
−
IEI3
IEI2
Read/write
Initial value
−
−
−
−
−
−
X
X
X
X
X
X
R
0
R
0
Bit
ICSH23
Input Capture Control Status Register (2/3) (Lower)
7
6
5
4
3
2
1
0
Address: 00006AH
ICP3
ICP2
ICE3
ICE2
EG31
EG30
EG21
EG20
Read/write
Initial value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
9
8
IEI1
IEI0
R
0
R
0
PPG output control/ Input Capture Control Status Register (0/1) (Upper)
15
14
13
12
11
10
Address: 000069H
Read/write
Initial value
PGEN5 PGEN4 PGEN3 PGEN2 PGEN1 PGEN0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
ICSL23
Bit
PICSH01
Input Capture Control Status Register (0/1) (Lower)
Address: 000068H
Read/write
Initial value
Bit
7
6
5
4
3
2
1
0
ICP1
ICP0
ICE1
ICE0
EG11
EG10
EG01
EG00
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
PICSL01
Input Capture Data Register (Upper)
Address: ch0 000061H
ch1 000063H
ch2 000065H
ch3 000067H
Read/write
Initial value
15
14
13
12
11
10
9
Bit
8
CP15
CP14
CP13
CP12
CP11
CP10
CP09
CP08
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
7
6
5
4
3
2
1
CP07
CP06
CP05
CP04
CP03
CP02
CP01
CP00
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
IPCP0 to
IPCP3
Input Capture Data Register (Lower)
Address: ch0 000060H
ch1 000062H
ch2 000064H
ch3 000066H
Read/write
Initial value
Note : Registers IPCP0 to IPCP3 are word access only.
52
0
Bit
IPCP0 to
IPCP3
MB90820 Series
• Waveform generator registers
Waveform Control Register
15
Address: 000059H
Read/write
Initial value
14
13
12
11
10
DTIE
DTIF
NRSL
DCK2
DCK1
DCK0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
9
Bit
8
NWS1 NWS0
R/W
0
SIGCR
R/W
0
16-bit Timer Control Register
Address: ch0 000056H
ch2 000058H
3
2
1
0
Bit
DTCR0, DTCR2
DMOD GTEN1 GTEN0 TMIF
Read/write
Initial value
R/W
0
R/W
0
16-bit Timer Control Register
15
Address: ch1 000057H
4
R/W
0
14
R/W
0
13
R/W
0
R/W
0
R/W
0
12
11
DMOD GTEN1 GTEN0 TMIF
Read/write
Initial value
TMIE TMD2 TMD1 TMD0
R/W
0
TMIE
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
10
9
8
Bit
TMD2 TMD1 TMD0
R/W
0
R/W
0
DTCR1
R/W
0
16-bit Timer Register (Upper)
15
Address: ch0 000051H
ch1 000053H
ch2 000055H
Read/write
Initial value
Read/write
Initial value
13
12
11
10
9
8
TR15
TR14
TR13
TR12
TR11
TR10
TR09
TR08
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
7
6
5
4
3
2
1
TR07
TR06
TR05
TR04
TR03
TR02
TR01
TR00
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
16-bit Timer Register (Lower)
Address: ch0 000050H
ch1 000052H
ch2 000054H
14
Bit
TMRR0 to
TMRR2
0
Bit
TMRR0 to
TMRR2
Note : Registers TMRR0 to TMRR2 are word access only.
53
MB90820 Series
• MCU to 3-phase Motor Interface Circuit
VCC
RTO4(W)
RTO2(V)
RTO0(U)
RTO5(Z)
RTO3(Y)
RTO1(X)
(W)
(V)
(U)
RTO0 (U) , RTO2 (V) , RTO4 (W) are called “UPPER ARM”.
RTO1 (X) , RTO3 (Y) , RTO5 (Z) are called “LOWER ARM”.
RTO0 (U) and RTO1 (X) are called “non-overlapping output pair”.
RTO2 (V) and RTO3 (Y) are called “non-overlapping output pair”.
RTO4 (W) and RTO5 (Z) are called “non-overlapping output pair”.
(U) , (V) , (W) are the 3-phase coil connection.
• 3-phase Motor Coil Connection Circuit
(U)
Star Connection Circuit
(V)
(W)
Delta Connection Circuit
(U)
(W)
54
(V)
MB90820 Series
(7) Block diagram
• Block diagram of Multi-functional timer
Real time I/O
Interrupt #12
Interrupt #15
Interrupt #17
Interrupt #19
Interrupt #21
Interrupt #23
16-bit output
compare
Output compare 0
Output compare 1
Output compare 2
Output compare 3
Output compare 4
Output compare 5
F2MC-16LX bus
Pin
P82/RTO0 (U)
RTO1
Pin
P83/RTO1 (X)
RTO2
Pin
P84/RTO2 (V)
RTO3
Pin
P85/RTO3 (Y)
RTO4
Pin
P86/RTO4 (W)
RTO5
Pin
P87/RTO5 (Z)
DTTI
Pin
P10/INT0/DTTI
RT0 to 5
RT0 to RT5
Waveform
generator
Buffer transfer
RTO0
Counter value
Interrupt #31
Interrupt #34
16-bit
free-running
timer
A/D trigger
Zero detect
Compare clear
Interrupt #29
16-bit timer 0/1/2
underflow
Interrupt #20
DTTI falling edge detect
A/D trigger
EXCK
PPG0
PPG0
GATE
GATE
Pin
P75/FRCK/AN13
Counter value
Interrupt #33
Interrupt #35
16-bit input
capture
Input capture 0/1
Input capture 2/3
IN0
Pin
P76/IN0/AN14
IN1
Pin
P77/IN1/AN15
IN2
Pin
P80/IN2
IN3
Pin
P81/IN3
Interrupt #12
Output compare 0
Interrupt #31
Zero detect
Interrupt #15
Output compare 1
Interrupt #34
Compare clear
Interrupt #17
Output compare 2
Interrupt #33
input compare 0/1
Interrupt #19
Output compare 3
Interrupt #35
input compare 2/3
Interrupt #21
Output compare 4
Interrupt #23
Output compare 5
55
MB90820 Series
• Block diagram of 16-bit free-running timer
φ
STOP MODE SCLR CLK2 CLK1 CLK0
UP/
CLR
UP-Down
STOP
Prescaler
Zero detect
circuit
16-bit free-running
timer
CK
Zero detect
(to output compare)
To input compare &
output compare
F2MC-16LX bus
Transfer
16-bit compare
clear register
compare
circuit
Compare clear match
to output compare
16-bit compare clear
buffer register
I0 I1
Selector
O
Mask circuit
I0
O
I1
Selector
Interrupt #34 (22H)
I0
O
I1
Selector
Interrupt #31 (1FH)
A/D trigger
MSI2
MSI1
MSI0
ICLR
ICRE IRQZF IRQZE
I1
O
I0
Selector
56
MB90820 Series
• Block diagram of 16-bit output compare
Count value from free-running timer
BTS0
BUF0
Output compare buffer
register 0/2/4
O
Output compare register 0/2/4
F2MC-16LX bus
Zero detect from
free-running timer
Compare clear match from
free-running timer
I0
Transfer
I1
Selector
BTS1
BUF1
Compare circuit
I0
O
Output compare buffer
register 1/3/5
Selector
Transfer
Output compare register 1/3/5
I1
CMOD
Compare circuit
IOP1
IOP0
IOE1
T
Q
RT0/2/4
(Waveform
generator)
T
Q
RT1/3/5
(Waveform
generator)
IOE0
Interrupt
#12, #17, #21
#15, #19, #23
• Block diagram of 16-bit input capture
Count value from free-running timer
F2MC-16LX bus
Input capture data
register 0/2
Edge detect
EG11 EG10 EG01 EG00
Input capture data register 1/3
Edge detect
ICP0
ICP1
ICE0
IN0/2
IEI1
IEI0
IN1/3
ICE1
Interrupt
#33, #35
#33, #35
57
MB90820 Series
• Block diagram of waveform generator
DCK2 DCK1 DCK0 NRSL DTIF DTIE NWS1 NWS0
φ
DTTI control circuit
Divider
SIGCR
Noise cancellation
DTTI
PICSH01 PGEN1 PGEN0
DTCR0 TMD2 TMD1 TMD0 GTEN1 GTEN0
GATE 0/1
GATE
(to PPG0)
TO0
TO1
RT1
Selector
16-bit timer 0
Compare circuit
Selector
Output control
Waveform control
RT0
RTO1 (X)
U
16-bit timer register 0
RTO0 (U)
Dead time generator
X
DTCR1 TMD2 TMD1 TMD0 GTEN1 GTEN0
GATE 2/3
TO2
Waveform control
RT2
TO3
RT3
Selector
16-bit timer 1
Compare circuit
Selector
Output control
F2MC-16LX bus
PICSH01 PGEN3 PGEN2
RTO3 (Y)
V
16-bit timer register 1
RTO2 (V)
Dead time generator
Y
DTCR2 TMD2 TMD1 TMD0 GTEN1 GTEN0
GATE 4/5
PICSH01 PGEN5 PGEN4
TO4
RT4
TO5
RT5
Selector
16-bit timer 2
Compare circuit
Selector
W
16-bit timer register 2
Dead time generator
PPG0
Z
58
Output control
Waveform control
RTO4 (W)
RTO5 (Z)
MB90820 Series
8. PWC Timer ( × 2)
The PWC (pulse width count) timer is a 16-bit multi-functional up counter with reload timer functions and input
signal pulse width count functions.
The PWC timer consists of a 16-bit counter, an input pulse divider, a division ratio control register, a count input
pin, a pulse output pin, and a 16-bit control register.
The PWC timer has the following features:
• Interruption is generated when timer overflow or end of PWC measurement.
• EI2OS is supported.
• Timer functions :
- Generates an interrupt request at set time intervals.
- Outputs pulse signals synchronized with the timer cycle.
- Selects the counter clock from three internal clocks.
• Pulse-width count functions:
- Counts the time between external pulse input events.
- Selects the counter clock from three internal clocks.
- Count mode:
• H pulse width (rising edge to falling edge) / L pulse width (falling edge to rising edge)
• Rising-edge cycle (rising edge to falling edge) / Falling-edge cycle (falling edge to rising edge)
• Count between edges (rising or falling edge to falling or rising edge)
Capable of counting cycles by dividing input pulses by 22, 24, 26, 28 using an 8-bit input divider.
Generates an interrupt request upon the completion of count operation.
Selects single or consecutive count operation.
(1) Register configuration
Division Ratio Control Register
Address: ch0 0000C4H
ch1 00002CH
Read/write
Initial value
7
6
5
4
3
−
−
−
−
−
−
−
−
−
−
−
−
X
X
X
X
X
X
2
1
DIV1
DIV0
R/W
0
R/W
0
0
DIV0, DIV1
PWC Data Buffer Register (Upper)
15
14
13
12
11
10
9
8
Address: ch0 0000C3H
ch1 00002BH
R/W
X
PWC Data Buffer Register (Lower)
Address: ch0 0000C2H
ch1 00002AH
Read/write
Initial value
Bit
PWC0, PWC1
PW15 PW14 PW13 PW12 PW11 PW10
Read/write
Initial value
Bit
PW09 PW08
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
7
6
5
4
3
2
1
PW07 PW06 PW05 PW04 PW03 PW02 PW01 PW00
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
0
Bit
PWC0, PWC1
R/W
X
Note : Registers PWC0, PWC1 are word access only.
(Continued)
59
MB90820 Series
(Continued)
PWC Control Status Register (Upper)
15
14
13
12
11
10
9
STRT
STOP
EDIR
EDIE
OVIR
OVIE
ERR
POUT
R/W
0
R/W
0
R
0
R/W
0
R/W
0
R/W
0
R
0
R/W
0
5
4
3
Bit
8
Address: ch0 0000C1H
ch1 000029H
Read/write
Initial value
PWC Control Status Register (Lower)
Address: ch0 0000C0H
ch1 000028H
7
6
CKS1
CKS0
R/W
0
R/W
0
Read/write
Initial value
Reserved Reserved
R/W
0
R/W
0
S/C
2
1
PWCSH0,
PWCSH1
0
PWCSL0,
PWCSL1
MOD2 MOD1 MOD0
R/W
0
R/W
0
R/W
0
Bit
R/W
0
Note : Registers PWC0, PWC1 are word access only.
(2) Block diagram
PWC read
Error
detection
ERR
16
PWC
16
Write enabled
16
Overflow
Reload
P07/PWO0,
P47/PWO1
F.F.
Data transfer
16
Clock
Overflow
22
16-bit up counter
23
Timer clear
F2MC-16LX bus
Count
enabled
Count bit
output
Flag setting
Control circuit
Start edge
selection
Count end
edge
Overflow interrupt request
60
CKS1, CKS0
Divider clear
Internal clock
(machine clock / 4)
Divider ON/OFF
P06/PWI0,
P46/PWI1
Edge
detection
Count start edge
Count end interrupt request
15
End edge
selection
PWCS
Clock
Clock
divider
8-bit
divider
CKS1,
ERR CKS0
Division
ratio
selection
2
DIVR
MB90820 Series
9. UART ( × 2)
The UART is a serial I/O port for asynchronous (start-stop) communication or clock-synchronous communication.
The UART has the following features :
• Full-duplex double buffering
• Capable of asynchronous (start-stop bit) and CLK-synchronous communications
• Support for the multiprocessor mode
• Various method of baud rate generation :
- External clock input possible
- Internal clock (a clock supplied from 16-bit reload timer can be used.)
- Embedded dedicated baud rate generator
Operation
Baud rate
Asynchronous
31250/9615/4808/2404/1202 bps
CLK synchronous 2 M/1 M/500 K/250 K/125 K/62.5K bps
Note : Assuming internal machine clock frequencies of 6 MHz, 8 MHz, 10 MHz, 12 MHz, and 16 MHz.
• Error detection functions (parity, framing, overrun)
• NRZ (Non Return to Zero) signal format
• Interrupt request :
- Receive interrupt (receive complete, receive error detection)
- Transmit interrupt (transmission complete)
- Transmit / receive conforms to extended intelligent I/O service (EI2OS).
61
MB90820 Series
(1) Register configuration
Serial Status Register
15
14
13
12
RDRF TDRE
11
10
9
8
Address: ch0 000023H
ch1 000027H
Read/write
Initial value
SSR0, SSR1
PE
ORE
FRE
R
0
R
0
R
0
R
0
Serial Input Data Register / Serial Output Data Register
7
6
5
Address: ch0 000022H
ch1 000026H
D7
D6
D5
D4
Read/write
Initial value
R/W
X
R/W
X
R/W
X
R/W
X
R
1
4
BDS
RIE
TIE
R/W
0
R/W
0
R/W
0
3
2
1
0
D3
D2
D1
D0
R/W
X
R/W
X
R/W
X
R/W
X
15
14
13
12
11
10
9
8
Address: ch0 000021H
ch1 000025H
Read/write
Initial value
P
SBL
CL
A/D
REC
RXE
TXE
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
W
1
R/W
0
R/W
0
7
6
5
4
2
1
CS2
CS1
CS0
RST
SCKE
SOE
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
3
0
R/W
0
R/W
0
15
Read/write
Initial value
62
Bit
SMR0, SMR1
MOD1 MOD0
Clock Division Control Register
Address: ch0 000035H
ch1 000037H
Bit
SCR0, SCR1
PEN
Serial Mode Register
Address: ch0 000020H
ch1 000024H
Bit
SIDR0, SIDR1/
SODR0, SODR1
Serial Control Register
Read/write
Initial value
Bit
14
13
12
MD
ILS
−
−
−
R/W
0
R/W
0
−
−
−
X
X
X
11
10
9
DIV2
DIV1
DIV0
R/W
0
R/W
0
R/W
0
8
Bit
CDCR0,
CDCR1
MB90820 Series
(2) Block diagram
Reception interrupt
#39 (27H)*
<#37 (25H)*>
From communication
prescaler
Baud rate
generator
Clock
selector
Reception clock
P43/SCK0
External clock
<P74/SCK1/AN12>
P45/SIN0
<P72/SIN1/AN10>
Reception control
circuit
Transmission control
circuit
Start bit detection
circuit
Transmission
start circuit
Reception bit
counter
Transmission bit
counter
Reception parity
counter
Transmission
parity counter
Shift register
for reception
Reception state
judgment circuit
End of reception
16-bit reload timer
Start of transmission
Control bus
Transmission
interrupt
#40 (28H)*
<#38 (26H)*>
Transmission clock
P44/SOT0
<P73/SOT1/AN11>
Shift register
for transmission
SIDR0/1
SODR0/1
Reception error
generating
circuit for EI2OS
F2MC-16LX bus
SMR0/1
register
*: Interrupt number
MD1
MD0
CS2
CS1
CS0
RST
SCKE
SOE
SCR0/1
register
PEN
P
SBL
CL
A/D
REC
RXE
TXE
SSR0/1
register
PE
ORE
FRE
RDRF
TDRE
BDS
RIE
TIE
Control signal
63
MB90820 Series
10. DTP/External Interrupts
The DTP/external interrupt circuit is activated by the signal supplied to a DTP/external interrupt pin. The CPU
accepts the signal using the same procedure it uses for normal hardware interrupts and generates external
interrupts or activates the extended intelligent I/O service (EI2OS).
Features of DTP/External Interrupt :
• Total 8 external interrupt channels.
• Two request levels (“H” and “L”) are provided for the intelligent I/O service.
• Four request levels (rising edge, falling edge, “H” level and “L” level) are provided for external interrupt requests.
(1) Register configuration
DTP/Interrupt Source Register
15
14
13
12
11
10
9
8
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
Address: 000030H
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
Read/write
Initial value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Address: 0000031H
Read/write
Initial value
DTP/Interrupt Enable Register
Bit
EIRR
Bit
ENIR
Request Level Setting Register (Upper)
Address: 0000033H
Read/write
Initial value
15
14
13
12
11
10
9
8
LB7
LA7
LB6
LA6
LB5
LA5
LB4
LA4
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
5
4
3
2
1
0
Request Level Setting Register (Lower)
7
6
64
Address: 000032H
LB3
LA3
LB2
LA2
LB1
LA1
LB0
LA0
Read/write
Initial value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
ELVRH
Bit
ELVRL
MB90820 Series
(2) Block diagram
Request level setting register (ELVR)
LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0
2
Pin
P51/INT7
2
2
2
2
2
Selector
2
Selector
Pin
P10/INT0/DTTI
Pin
Selector
Selector
P16/INT6
Internal data bus
2
Pin
P11/INT1
Pin
Selector
Selector
P15/INT5
Pin
P12/INT2
Pin
Selector
Selector
Pin
P14/INT4
P13/INT3
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
Interrupt request number
#20(14H)
#22(16H)
#25(19H)
#26(1AH)
#27(1BH)
#28(1CH)
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
65
MB90820 Series
11. Delayed Interrupt Generation Module
The delayed interrupt generation module is used to generate a task switching interrupt. Interrupt requests to the
F2MC-16LX CPU can be generated and cleared by software using this module.
(1) Register configuration
Delay interrupt cause/clear register
15
14
13
12
11
10
9
8
Address: 00009FH
−
−
−
−
−
−
−
R0
Read/write
Initial value
−
−
−
−
−
−
−
X
X
X
X
X
X
X
R/W
0
F2MC-16LX bus
(2) Block diagram
66
Delayed interrupt cause generating/cancellation decoder
Interrupt cause latch
Bit
DIRR
MB90820 Series
12. A/D Converter
The A/D converter converts the analog voltage input (input voltage) to an analog input pin to a digital value. It
has the following features :
• The minimum conversion time is 3 µs (for a machine clock of 24 MHz; including sampling time).
• The converter uses the RC-type successive approximation conversion method with a sample and hold circuit.
• A resolution of 10 bits or 8 bits can be set.
• Up to 16 channels for analog input pins can be selected by a program.
• Various conversion mode :
- Single conversion mode : Selectively convert one channel.
- Scan conversion mode : Continuously convert multiple channels. Maximum of 16 selectable channels.
- Continuous conversion mode : Repeatedly convert specified channels.
- Stop conversion mode : Convert one channel then halt until the next activation (enables synchronization of
the conversion start timing).
• At the end of A/D conversion, an interrupt request can be generated and EI²OS can be activated.
• In the interrupt-enabled state, the conversion data protection function prevents any part of the data from being
lost through continuous conversion.
• The conversion can be activated by software, 16-bit reload timer 1 (rising edge) and 16-bit free-running timer
zero detection edge.
(1) Register configuration
A/D Control Status Register 1 (upper)
Address: 00000C7H
Read/write
Initial value
15
14
13
12
11
10
9
8
Bit
BUSY
INT
INTE
PAUS
STS1
STS0
STRT
−
ADCS1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
W
0
X
5
4
3
2
1
0
−
−
−
Reserved
−
−
A/D Control Status Register 0 (lower)
7
6
−
Address: 0000C6H
MD1
MD0
S10
−
Read/write
Initial value
R/W
0
R/W
0
R/W
0
−
−
X
X
−
X
X
15
14
13
12
11
10
9
8
−
−
−
−
−
−
D9
D8
−
−
−
−
−
−
X
X
X
X
X
X
R
X
R
X
Bit
ADCS0
0
A/D Data Register 1 (upper)
Address: 00000C9H
Read/write
Initial value
A/D Data Register 0 (lower)
7
6
5
4
3
2
1
0
Address: 0000C8H
D7
D6
D5
D4
D3
D2
D1
D0
Read/write
Initial value
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
Bit
ADCR1
Bit
ADCR0
(Continued)
67
MB90820 Series
(Continued)
A/D Setting Register 1 (upper)
Address: 00000CBH
Read/write
Initial value
15
14
13
12
11
10
9
ST2
ST1
ST0
CT2
CT1
CT0
Reserved
ANS3
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
6
5
4
3
2
1
0
ANS2
ANS1
ANS0
Reserved
ANE3
ANE2
ANE1
ANE0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
ADE7
ADE6
ADE5
ADE4
ADE3
ADE2
ADE1
ADE0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
7
6
5
4
3
2
1
0
ADE15 ADE14 ADE13 ADE12 ADE11 ADE10
ADE9
ADE8
R/W
1
R/W
1
R/W
1
A/D Setting Register 0 (lower)
7
Address: 0000CAH
Read/write
Initial value
8
Bit
ADSR1
Bit
ADSR0
A/D Input Enable Register 0
Address: 00000C5H
Read/write
Initial value
A/D Input Enable Register 1
Address: 0000D0H
Read/write
Initial value
68
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit
ADER0
Bit
ADER1
MB90820 Series
(2) Block diagram
AVCC
AVR AVSS
D/A converter
MPX
Input circuit
F2MC-16LX bus
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15
Sequential
compare register
Comparator
Sample and
hold circuit
Decorder
Input circuit
Port 7
Port 6
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Data register
ADCR0/1
A/D setting register 0
A/D setting register 1
ADSR0/1
Operation clock
φ
Prescaler
A/D input enable register 0
A/D input enable register 1
ADER0/1
A/D control status register 0
A/D control status register 1
ADCS0/1
16-bit reload timer 1
16-bit free-running timer zero detection
φ : Machine clock
69
MB90820 Series
13. D/A Converter
The D/A converter is used to generate an analog output from an 8-bit digital input. By setting the enable bit in
the D/A control register (DACR) to 1, it will enable the corresponding D/A output channel. Hence, setting this bit
to 0 will disable that channel.
If D/A output is disabled, the analog switch inserted to the output of each D/A converter channel in series is
turned off. In the D/A converter, the bit is cleared to 0 and the direct-current path is shut off. The above is also
true in the stop mode.
The output voltage of the D/A converter ranges from 0 V to 255/256 × AVCC. To change the output voltage range,
adjust the AVCC voltage externally.
The D/A converter output does not have the internal buffer amplifier. The analog switch (= 100 Ω) is inserted to
the output in series. To apply load to the output externally, estimate a sufficient stabilization time.
Table below lists the theoretical values of output voltage of the D/A converter.
70
Value written to DA07 to DA00
and DA17 to DA10
Theoretical value of output voltage
00H
0/256 × AVCC (= 0 V)
01H
1/256 × AVCC
02H
2/256 × AVCC
:
:
FDH
253/256 × AVCC
FEH
254/256 × AVCC
FFH
255/256 × AVCC
MB90820 Series
(1) Register configuration
D/A data register 1
Bit
Address:0000CDH
Read/write
Initial value
15
14
13
12
DA17 DA16 DA15 DA14
11
10
DA13
DA12
R/W
X
9
8
DA11 DA10 DAT1
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
7
6
5
4
3
2
1
0
DA03
DA02
R/W
X
R/W
X
R/W
X
R/W
X
8
D/A data register 0
Bit
Address:0000CCH
Read/write
Initial value
DA07
DA06 DA05 DA04
DA01 DA00 DAT0
R/W
X
R/W
X
R/W
X
R/W
X
15
14
13
12
11
10
9
-
-
-
-
-
-
-
DAE1 DACR1
X
X
X
X
X
X
X
R/W
0
Bit
7
6
5
4
3
2
1
0
Address:0000CEH
-
-
-
-
-
-
-
DAE0 DACR0
X
X
X
X
X
X
X
R/W
0
D/A control register 1
Bit
Address:0000CFH
Read/write
Initial value
D/A control register 0
Read/write
Initial value
71
MB90820 Series
(2) Block diagram
F 2 MC-16LX bus
DA DA DA DA DA DA DA DA
17 16 15 14 13 12 11 10
DA DA DA DA DA DA DA DA
07 06 05 04 03 02 01 00
AVCC
AVCC
DA17
DA07
2R
2R
R
DA16
R
DA06
2R
2R
R
R
DA15
DA05
DA11
DA01
2R
2R
R
DA10
R
DA00
2R
2R
2R
DAE1
DAE0
Standby control
Standby control
DA output ch1
72
2R
DA output ch0
MB90820 Series
14. ROM Correction Function
When the corresponding address matches the value set in the address detection register, the instruction code
to be loaded into the CPU is forced to be replaced with the INT9 instruction code (01H). When executing a set
instruction, the CPU executes the INT9 instruction. The address detection function is implemented by processing
using the INT9 instruction routine.
The device contains two address detection registers, each provided with a compare enable bit. When the value
set in the address detection register matches an address and the interrupt enable bit is “1”, the instruction code
to be loaded into the CPU is forced to be replaced with the INT9 instruction code.
(1) Register configuration
Program Address Detection Control Status Register
7
6
5
4
3
2
1
0
−
−
AD1E
AD1D
AD0E
AD0D
−
X
R/W
0
R/W
0
R/W
0
1
0
Address: 00009EH
Read/write
Initial value
−
−
−
−
−
X
X
X
R/W
0
4
3
Bit
PACSR
Program Address Detection Register 0 (Upper Byte)
7
6
5
2
Bit
Address: 001FF2H
Read/write
Initial value
PADRH0
R/W
X
R/W
X
R/W
X
R/W
X
Program Address Detection Register 0 (Middle Byte)
15
14
13
12
R/W
X
11
R/W
X
R/W
X
10
R/W
X
9
8
Address: 001FF1H
Read/write
Initial value
Bit
PADRM0
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
1
0
Program Address Detection Register 0 (Lower Byte)
7
6
5
4
3
2
Address: 001FF0H
Read/write
Initial value
Bit
PADRL0
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
11
10
9
8
Program Address Detection Register 1 (Upper Byte)
15
14
13
12
Address: 001FF5H
Read/write
Initial value
Bit
PADRH1
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
(Continued)
73
MB90820 Series
(Continued)
Program Address Detection Register 1 (Middle Byte)
7
6
5
4
3
2
1
0
Address: 001FF4H
Read/write
Initial value
PADRM1
R/W
X
R/W
X
R/W
X
R/W
X
Program Address Detection Register 1 (Lower Byte)
15
14
13
12
R/W
X
R/W
X
R/W
X
11
10
9
R/W
X
8
Address: 001FF3H
Read/write
Initial value
Bit
Bit
PADRL1
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
(2) Block diagram
Address latch
Comparator
INT9
command
F2MC-16LX bus
Program address detection
register 0/1
74
F2MC-16LX
AD0E/AD1E AD0D/AD1D
PACSR
CPU
MB90820 Series
15. ROM Mirroring Function Selection Module
The ROM mirror function selection module sets the data in ROM assigned to FF bank so that the data is read
by access to 00 bank.
(1) Register configuration
ROM Mirror Function Selection Register
Address : 00006FH
Read/write
Initial value
15
14
13
12
11
10
9
8
−
−
−
−
−
−
−
M1
−
−
−
−
−
−
−
R/W
X
X
X
X
X
X
X
1
Bit
ROMM
(2) Block diagram
F2MC-16LX bus
ROM mirroring function
selection register
Address area
FF bank
00 bank
ROM
75
MB90820 Series
16. 512K/1024K bits Flash Memory
The 512K bits flash memory is allocated in the FFH banks on the CPU memory map.
The 1024K bits flash memory is allocated in the FEH and FFH banks on the CPU memory map.
Like Mask ROM, flash memory is read-accessible and program-accessible to the CPU using the flash memory
interface circuit. The flash memory can be programmed/erased by the instruction from the CPU via the flash
memory interface circuit. The flash memory can therefore be reprogrammed (updated) while still on the circuit
board under integrated CPU control, allowing program code and data to be improved efficiently.
Note that sector operations such as “enable sector protect” cannot be used.
Features of 512K/1024K bits flash memory
• 64K × 8 bits/32K × 16 bits (32K + 8K × 2 + 16K) sector configuration for 512K bits flash memory
• 128K × 8 bits/64K × 16 bits (64K + 32K + 8K × 2 + 16K) sector configuration for 1024K bits flash memory
• Automatic program algorithm (same as the Embedded Algorithm* : MBM29F400TA)
• Installation of the deletion temporary stop/delete restart function
• Write/delete completion detected by the data polling or toggle bit
• Write/delete completion detected by the CPU interrupt
• Compatibility with the JEDEC standard-type command
• Each sector deletion can be executed (sectors can be freely combined)
• Flash security function
• Number of write/delete operations are guaranteed 10,000 times.
* : Embedded Algorithm is a trademark of Advanced Micro Devices, Inc.
(1) Register configuration
Flash Memory Control Status Register
7
6
Address: 0000AEH
Read/write
Initial value
76
5
4
INTE RDYINT
WE
RDY
R/W
0
R/W
0
R
X
R/W
0
3
2
1
0
Reserved Reserved Reserved Reserved
−
0
−
0
−
0
−
0
Bit
FMCS
MB90820 Series
(2) Sector configuration of flash memory
The flash memory has the sector configuration illustrated below. The addresses in the illustration are the upper
and lower addresses of each sector.
When 512K bits flash memory is accessed from the CPU, SA0 to SA3 are allocated in the FF bank.
Flash memory
SA3 (16K bytes)
SA2 (8K bytes)
SA1 (8K bytes)
SA0 (32K bytes)
CPU address
*Writer address
FFFFFFH
7FFFFH
FFC000H
FFBFFFH
7C000H
7BFFFH
FFA000H
7A000H
FF9FFFH
79FFFH
FF8000H
FF7FFFH
78000H
77FFFH
FF0000H
70000H
When 1024K bits flash memory is accessed from the CPU, SA0 to SA4 are allocated in the FE and FF bank.
Flash memory
SA4 (16K bytes)
SA3 (8K bytes)
SA2 (8K bytes)
SA1 (32K bytes)
CPU address
FFFFFFH
7FFFFH
FFC000H
FFBFFFH
7C000H
7BFFFH
FFA000H
7A000H
FF9FFFH
79FFFH
FF8000H
78000H
77FFFH
FF7FFFH
FF0000H
SA0 (64K bytes)
*Writer address
FE7FFFH
70000H
6FFFFH
FE0000H
60000H
* : The writer address is the address corresponding to the CPU address when writing data from a parallel flash
memory writer. Use the writer address when programming or erasing using a general-purpose parallel writer.
77
MB90820 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Symbol
Parameter
Rating
Unit
Remarks
Min
Max
VCC
VSS − 0.3
VSS + 6.0
V
AVCC
VSS − 0.3
VSS + 6.0
V
VCC = AVCC *2
AVR
VSS − 0.3
VSS + 6.0
V
AVCC ≥ AVR, AVR ≥ AVss
VI
VSS − 0.3
VSS + 6.0
V
*3
VO
VSS − 0.3
VSS + 6.0
V
*3
ICLAMP
− 2.0
+ 2.0
mA
*5
Σ | ICLAMP |
⎯
20
mA
*5
IOL
⎯
15
mA
*4
IOLAV1
⎯
4
mA
Except for P00 to P07, P82 to P87
IOLAV2
⎯
12
mA
P00 to P07, P82 to P87
ΣIOL
⎯
100
mA
ΣIOLAV
⎯
50
mA
IOH
⎯
−15
mA
“H” level average output current
IOHAV
⎯
−4
mA
“H” level total maximum output
current
ΣIOH
⎯
−100
mA
ΣIOHAV
⎯
−50
mA
Power consumption
PD
⎯
430
mW
Operating temperature
TA
−40
+85
°C
Tstg
−55
+150
°C
1
Power supply voltage*
Input voltage*
1
Output voltage*
1
Maximum clamp current
Total maximum clamp current
“L” level maximum output
current
“L” level average output current
“L” level total maximum output
current
“L” level total average
output current
“H” level maximum output
current
“H” level total average
output current
Storage temperature
*4
*1 : This parameter is based on VSS = AVSS = 0.0 V.
*2 : AVCC must never exceed VCC when the power is turned on.
*3 : VI and VO must never exceed VCC + 0.3 V. However if the maximum current to/from an input is limited by some
means with external components, the ICLAMP rating supersedes the VI rating.
*4 : The maximum output current is a peak value for a corresponding pin.
*5 : •
•
•
•
Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50, P51, P80 to P87.
Use within recommended operating conditions.
Use at DC voltage (current).
The +B signal is an input signal exceeding VCC voltage. The +B signal should always be applied a limiting
resistance placed between the +B signal and the microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the Vcc pin, and this may affect
other devices.
78
MB90820 Series
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V), the power
supply is provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the
resulting supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the +B input pin open.
• Note that analog system input/output pins (LCD drive pins and comparator input pins, etc.) other than the
A/D input pins cannot accept +B input.
• Sample recommended circuits:
Input/output equivalent circuits
Protective diode
Vcc
P-ch
Limiting
resistance
+B input (0 V to 16 V)
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
79
MB90820 Series
2. Recommended Operating Conditions
(VSS = AVSS = 0.0 V)
Parameter
Power
supply
voltage
“H” level
input voltage
Symbol
Smoothing
capacitor
Condition
Min
Max
⎯
⎯
4.5
5.5
V
At normal operation
TA = −40 °C to +85 °C
⎯
⎯
4.0
5.5
V
Normal operation when
D/A converter is not used
TA = −40 °C to +85 °C
Unit
VCC
AVCC
Remarks
⎯
⎯
3.5
5.5
V
Normal operation when
A/D converter and D/A
converter are not used
TA = −40 °C to +85 °C
⎯
⎯
3.0
5.5
V
Maintains state in stop
mode
VIH
P30 to P37, P60 to P67
0.7 VCC
VCC + 0.3
V
CMOS input
VIHS
P00 to P07, P10 to P17
P20 to P27, P40 to P44,
P45*1, P46, P47, P50,
P51, P70, P71, P72*1,
P73 to P77, P80 to P87,
RST
0.8 VCC
VCC + 0.3
V
CMOS hysteresis input
VIHM
MD0, MD1, MD2
VCC = 5 V VCC − 0.3 VCC + 0.3
P30 to P37, P60 to P67 ± 10% VSS − 0.3 0.3 VCC
V
MD input
V
CMOS input
V
CMOS hysteresis input
V
MD input
*2
VIL
“L” level
input voltage
Value
Pin name
VILS
P00 to P07, P10 to P17
P20 to P27, P40 to P44,
P45*1, P46, P47, P50,
P51, P70, P71, P72*1,
P73 to P77, P80 to P87
RST
VSS − 0.3
VILM
MD0, MD1, MD2
VSS − 0.3 VSS + 0.3
0.2 VCC
CS
⎯
⎯
0.1
1.0
µF
Reference
input voltage
of A/D
converter
AVR
⎯
⎯
2.7
AVCC
V
Operating
temperature
TA
⎯
⎯
−40
+85
°C
*1 : UART ch0/1 data input pins P45/SIN0, P72/SIN1/AN10 can be used as CMOS input by the communication
prescaler control register (CDRR).
*2 : Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. On the VCC pin, connect a
bypass capacitor that has a larger capacity than that of CS. Refer to the following figure for connection of
smoothing capacitor CS.
80
MB90820 Series
• C pin connection circuit
C
CS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
81
MB90820 Series
3. DC Characteristics
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Condition
Unit
Remarks
Min
Typ
Max
Parameter
Symbol
Pin name
“H” level output
voltage
VOH
All output pins
VOL1
All pins except
VCC = 4.5 V,
P00 to P07
IOL1 = 4.0 mA
P82 to P87
VOL2
P00 to P07
P82 to P87
All input pins
“L” level output
voltage
Input leakage
current
IIL
Pull-up
resistance
RUP
Pull-down
resistance
RDOWN
VCC = 4.5 V,
IOH = −4.0 mA
VCC − 0.5
⎯
⎯
V
⎯
⎯
0.4
V
VCC = 4.5 V,
IOL2 = 12.0 mA
⎯
⎯
0.4
V
VCC = 5.5 V,
VSS < VI< VCC
−5
⎯
5
µA
P00 to P07
P10 to P17
P20 to P27
P30 to P37
RST
⎯
25
50
100
kΩ
MD2
⎯
25
50
100
kΩ
At pull-up
disabled
Mask ROM
product
(Continued)
82
MB90820 Series
(Continued)
Parameter
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Symbol
Pin name
Condition
Power supply
current*
Max
⎯
35
50
mA Mask ROM product
⎯
45
60
mA
Flash memory product
VCC = 5.0 V,
Internal frequency:
24 MHz,
At writing in flash
memory
⎯
60
75
mA
Flash memory product
VCC = 5.0 V,
Internal frequency:
24 MHz,
At erasing memory
⎯
65
80
mA
Flash memory product
Input
capacitance
⎯
⎯
ICTS
VCC = 5.0 V,
Internal frequency:
2 MHz,
At main timer mode
⎯
ICCT
VCC = 5.0 V,
Internal frequency:
8 MHz,
At timer mode,
TA = +25 °C
ICCH
In stop mode,
TA = +25 °C
CIN
VCC
Except AVCC,
AVSS, AVR, C,
VCC and VSS
Remarks
Typ
VCC = 5.0 V,
Internal frequency:
24 MHz,
At sleep mode
ICCS
Unit
Min
VCC = 5.0 V,
Internal frequency:
24 MHz,
At normal operation
ICC
Value
⎯
⎯
⎯
⎯
mA Mask ROM product
15
25
⎯
Flash memory product
mA Mask ROM product
0.3
0.8
mA
Flash memory product
mA Mask ROM product
3
7
⎯
⎯
mA
µA
Flash memory product
mA Mask ROM product
5
20
5
15
µA
Flash memory product
pF
* : The power supply current is regulated with an external clock.
83
MB90820 Series
4. AC Characteristics
(1) Clock Timings
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Symbol Pin name
Unit
Remarks
Min
Typ
Max
Parameter
Clock frequency
X0, X1
FC
Clock cycle time
3
⎯
16
When using
oscillation circuit
3
⎯
24
When using external
clock
4
⎯
24
4
⎯
12
MHz 1 multiplied PLL
2 multiplied PLL
4
⎯
8
3 multiplied PLL
4
⎯
6
4 multiplied PLL
4
⎯
4
6 multiplied PLL
62.5
⎯
333
ns
When using
oscillation circuit
41.67
⎯
333
ns
When using external
clock
X0, X1
tHCYL
Input clock pulse width
PWH
PWL
X0
10
⎯
⎯
ns
When using external
clock, duty ratio is
about 30% to 70%.
Input clock rise/fall time
tCR
tCF
X0
⎯
⎯
5
ns
When using external
clock
Internal operating clock frequency
frequency
fCP
⎯
1.5
⎯
24
MHz
Internal operating clock cycle time
tCP
⎯
41.67
⎯
666
ns
tHCYL
0.8 VCC
X0
0.2 VCC
PWH
PWL
tCF
84
tCR
MB90820 Series
Power supply voltage VCC (V)
Relationship between internal operating clock frequency and power supply voltage
Guaranteed D/A Converter operating range
5.5
4.5
Operation guarantee range of PLL
4.0
Guaranteed A/D Converter
operating range
3.5
Normal operation guarantee range
1.5 4
24
Internal operating clock frequency fCp (MHz)
Internal operating clock frequency fCp (MHz)
Relationship between clock frequency and internal operating clock frequency
X6
X4
X3
X2
X1
24
16
Not multiplied
12
8
4
1.5
3 4
8
12
16
Clock frequency FC (MHz)
24
The AC ratings are measured for the following measurement reference voltages
• Input signal waveform
• Output signal waveform
Hysteresis input pin
Output pin
0.8 VCC
2.4 V
0.2 VCC
0.8 V
Pins other than hysteresis input/MD input
0.7 VCC
0.3 VCC
85
MB90820 Series
(2) External Reset
Parameter
Symbol
Reset input time
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Unit
Remarks
Min
Max
Pin name
tRSTL
RST
500
⎯
ns
In normal operation
Oscillation time of
oscillator* + 100
⎯
µs
In stop mode
100
⎯
µs
In timebase timer mode
* : Oscillation time of oscillator is the time to reach to 90% of the oscillation amplitude from stand still. In the crystal
oscillator, the oscillation time is between several ms to tens of ms. In FAR/ceramic oscillator, the oscillation time
is between hundreds of µs to several ms. In the external clock, the oscillation time is 0 ms.
• In normal operation mode
tRSTL
RST
0.2 VCC
0.2 VCC
• In stop mode, at power on
tRSTL
RST
0.2 VCC
0.2 VCC
90% of the oscillation amplitude
X0
Internal
operation
clock
Oscillation time of
oscillator
100 µs
Oscillator stabilization time
Instruction
execution
Internal reset
86
MB90820 Series
(3) Power-on Reset
Parameter
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Symbol Pin name Condition
Unit
Remarks
Min
Max
Power supply rising time
tR
VCC
Power supply cut-off time
tOFF
VCC
0.05
30
ms
1
⎯
ms
⎯
Waiting time for power
supply on
tR
VCC
2.7 V
0.2 V
0.2 V
0.2 V
tOFF
Note : Sudden changes in the power supply voltage may cause a power-on reset.
To change the power supply voltage while the device is in operation, be sure to set the slope of rising within
50 mV/ms or less as shown below.
VCC
3.0 V
VSS
RAM data hold time
Be sure to set the slope of rising
within 50mV/ms or less.
87
MB90820 Series
(4) UART0 and UART1
Parameter
Symbol
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Pin name
Condition
Unit Remarks
Min
Max
8 tCP
⎯
ns
−80
+ 80
ns
100
⎯
ns
SCK0 to SCK1
SIN0 to SIN1
60
⎯
ns
tSHSL
SCK0 to SCK1
4 tCP
⎯
ns
Serial clock “L” pulse width
tSLSH
SCK0 to SCK1
4 tCP
⎯
ns
SCK ↓ → SOT delay time
tSLOV
SCK0 to SCK1
SOT0 to SOT1
⎯
150
ns
Valid SIN → SCK ↑
tIVSH
SCK0 to SCK1
SIN0 to SIN1
60
⎯
ns
SCK ↑ → valid SIN hold time
tSHIX
SCK0 to SCK1
SIN0 to SIN1
60
⎯
ns
Serial clock cycle time
tSCYC
SCK0 to SCK1
SCK ↓ → SOT delay time
tSLOV
SCK0 to SCK1
SOT0 to SOT1
Valid SIN → SCK ↑
tIVSH
SCK0 to SCK1
SIN0 to SIN1
SCK ↑ → valid SIN hold time
tSHIX
Serial clock “H” pulse width
CL = 80 pF + 1 TTL
for an output pin of
internal shift clock
mode
CL = 80 pF + 1 TTL
for an output pin of
external shift clock
mode
Notes : • These are AC ratings in the CLK synchronous mode.
• CL is the load capacitance value connected to pins while testing.
• tCP is machine cycle time (unit : ns).
88
MB90820 Series
• Internal shift clock mode
tSCYC
2.4 V
SCK
0.8 V
0.8 V
tSLOV
2.4 V
SOT
0.8 V
tIVSH
SIN
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
• External shift clock mode
tSLSH
SCK
0.2 VCC
tSHSL
0.8 VCC
0.8 VCC
0.2 VCC
tSLOV
2.4 V
SOT
0.8 V
tIVSH
SIN
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
89
MB90820 Series
(5) Resources Input Timing
Parameter
Input pulse width
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Pin name
Condition
Unit Remarks
Min
Max
Symbol
tTIWH
tTIWL
IN0 to IN3,
TIN0 to TIN1,
PWI0 to PWI1,
DTTI
0.8 VCC
⎯
4 tCP
⎯
ns
0.8 VCC
0.2 VCC
0.2 VCC
tTIWH
tTIWL
(6) Trigger Input Timing
Parameter
Input pulse width
Symbol
tTRGH
tTRGL
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Pin name
Condition
Unit Remarks
Min
Max
⎯
INT0 to INT7
0.8 VCC
0.8 VCC
0.2 VCC
tTRGH
90
5 tCP
0.2 VCC
tTRGL
⎯
ns
MB90820 Series
5. A/D Converter Electrical Characteristics
Parameter
Resolution
(3.0 V ≤ AVR − AVSS, VCC = AVCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Pin
Unit
Remarks
Symbol
name
Min
Typ
Max
⎯
⎯
⎯
10
⎯
bit
Total error
⎯
⎯
⎯
⎯
±3.0
LSB
Non-linearity error
⎯
⎯
⎯
⎯
±2.5
LSB
Differential linearity
error
⎯
⎯
⎯
⎯
±1.9
LSB
Zero transition
voltage
VOT
AN0 to
AN15
AVSS −
1.5 LSB
AVSS +
0.5 LSB
AVSS +
2.5 LSB
mV
Full-scale
transition voltage
VFST
AN0 to
AN15
AVR −
3.5 LSB
AVR −
1.5 LSB
AVR +
0.5 LSB
mV
Compare time
⎯
⎯
1.0
⎯
⎯
µs
4.5 V < AVcc < 5.5 V
2.0
⎯
⎯
µs
4.0 V < AVcc < 4.5 V
Sampling time
⎯
⎯
0.5
⎯
⎯
µs
4.5 V < AVcc < 5.5 V
1.2
⎯
⎯
µs
4.0 V < AVcc < 4.5 V
Analog port input
current
IAIN
AN0 to
AN15
- 0.3
⎯
+ 0.3
µA
Analog input
voltage
VAIN
AN0 to
AN15
AVSS
⎯
AVR
V
Reference voltage
⎯
AVR
AVSS + 2.7
⎯
AVCC
V
Power supply
current
⎯
2.4
4.7
mA
IAH
⎯
⎯
5
⎯
600
900
⎯
⎯
5
⎯
⎯
4
Reference voltage
supply current
Offset between
channels
IA
IR
IRH
—
AVCC
AVR
AN0 to
AN15
µA *
µA
µA *
LSB
* : The current when the A/D converter is not operating or the CPU is in stop mode (for VCC = AVCC = AVR = 5.0 V)
Note : The error increases proportionally as |AVR - AVSS| decreases.
91
MB90820 Series
6. A/D Converter Glossary
Resolution
Non linearity error
: Analog variation that is recognized by an A/D converter.
: Deviation between a line across zero-transition line (“00 0000 0000”↔
“00 0000 0001”) and full-scale transition line (“11 1111 1110”↔“11 1111 1111”) and
actual conversion characteristics.
Differential linearity error : Deviation of input voltage, which is required for changing output code by 1 LSB, from
an ideal value
Total error
: Difference between an actual value and an ideal value. A total error includes zero
transition error, full-scale transition error, and linear error.
Total error
3FFH
3FEH
0.5 LSB
Actual conversion
characteristics
Digital output
3FDH
{1 LSB × (N − 1) + 0.5 LSB}
004H
VNT
(Measurement value)
003H
Actual
conversion
characteristics
002H
001H
Ideal
characteristics
0.5 LSB
AVRL
AVRH
Analog input
Total error for digital output N =
1 LSB = (Ideal value)
VNT − {1 LSB × (N − 1) + 0.5 LSB}
1 LSB
AVR − AVss [V]
1024
[LSB]
N : A/D converter digital output value
VOT(Ideal value) = AVss + 0.5 LSB [V]
VFST(Ideal value) = AVR − 1.5 LSB [V]
VNT : Voltage at which of digital output transitions from (N − 1) to N.
(Continued)
92
MB90820 Series
(Continued)
Linearity error
3FEH
Digital output
3FDH
Ideal
characteristics
Actual conversion
characteristics
VFST
(Measurement
value)
VNT
(Measurement value)
004H
Actual
conversion
characteristics
003H
002H
N
V(N + 1)T
N−1
(Measurement value)
VNT
(Measurement value)
Ideal
characteristics
001H
Actual conversion
characteristics
N+1
{1 LSB × (N − 1)
+ VOT }
Digital output
3FFH
Differential linearity error
Actual conversion
characteristics
N−2
VOT (Measurement value)
AVss
AVR
AVss
Linearity error of
=
digital output N
VNT − {1 LSB × (N − 1) + VOT}
1 LSB
Differential linearity error
V (N + 1) T − VNT
=
1 LSB
of digital output N
1 LSB =
N
AVR
Analog input
Analog input
VFST − VOT
1022
[LSB]
− 1 [LSB]
[V]
: A/D converter digital output value
VOT : Voltage at which of digital output transmissions from “000H” to “001H”.
VFST : Voltage at which of digital output transmissions from “3FEH” to “3FFH”.
93
MB90820 Series
7. Notes on Using A/D Converter
• About the external impedance of the analog input and its sampling time
• A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting
A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relationship
between the external impedance and minimum sampling time and either adjust the resistor value and operating
frequency or decrease the external impedance so that the sampling time is longer than the minimum value.
And if the sampling time cannot be sufficient, connect a capacitor of about 0.1 mF to the analog input pin.
• Analog input circuit model
R
Analog input
Comparator
C
During sampling : ON
MB90822/823
MB90F822A/F823A
R
2.0 kΩ (Max)
2.0 kΩ (Max)
C
14.4 pF (Max)
16.0 pF (Max)
Note : The values are reference values.
• The relationship between the external impedance and minimum sampling time
(External impedance = 0 kΩ to 100 kΩ)
(External impedance = 0 kΩ to 20 kΩ)
20
100
18
MB90822/
823
80
70
External impedance [kΩ]
External impedance [kΩ]
90
MB90F822A/F823A
60
50
40
30
20
10
MB90F822A/F823A
14
12
10
8
6
4
2
0
0
0
5
10
15
20
25
30
35
Minimum sampling time [µs]
• About the error
The accuracy gets worse as | AVR−AVSS | becomes smaller.
94
MB90822/
823
16
0
1
2
3
4
5
6
Minimum sampling time [µs]
7
8
MB90820 Series
8. Electrical Characteristics of D/A convertor
Parameter
(VCC = AVCC = 4.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Symbol Pin name Condition
Unit Remarks
Min
Typ
Max
Resolution
⎯
⎯
⎯
8
⎯
bit
Differential linearity error
⎯
⎯
⎯
⎯
±0.5
LSB
Conversion time
⎯
⎯
⎯
0.45
⎯
µs
Analog output impedance
⎯
⎯
⎯
2.9
3.8
kΩ
⎯
160
920
µA
⎯
0.1
⎯
µA
Power supply current
IDVR
IDVRS
AVCC
⎯
*
D/A stops
* : With load capacitance 20 pF.
95
MB90820 Series
9. Flash Memory Program/Erase Characteristics
Parameter
Condition
Sector erase time
Chip erase time
TA = +25 °C
VCC = 5.0 V
Word (16 bit width)
programing time
Value
Unit
Remarks
Min
Typ
Max
⎯
1
15
s
Excludes programming prior to
erasure
⎯
9
⎯
s
Excludes programming prior to
erasure
⎯
16
3,600
µs
Except for the overhead time of
the system
Program/Erase cycle
⎯
10,000
⎯
⎯
cycle
Flash data retention
time
Average
TA = +85 °C
20
⎯
⎯
year
*
* : This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at + 85 °C) .
■ ORDERING INFORMATION
Part number
96
Package
MB90F823APFV
MB90F822APFV
MB90822PFV
MB90823PFV
80-pin Plastic LQFP
(FPT-80P-M05)
MB90F823APFM
MB90F822APFM
MB90822PFM
MB90823PFM
80-pin Plastic LQFP
(FPT-80P-M11)
MB90F823APF
MB90F822APF
MB90822PF
MB90823PF
80-pin Plastic QFP
(FPT-80P-M06)
Remarks
MB90820 Series
■ PACKAGE DIMENSIONS
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
80-pin plastic QFP
(FPT-80P-M06)
23.90±0.40(.941±.016)
* 20.00±0.20(.787±.008)
64
41
40
65
0.10(.004)
17.90±0.40
(.705±.016)
* 14.00±0.20
(.551±.008)
INDEX
Details of "A" part
25
80
0.25(.010)
+0.30
3.05 –0.20
+.012
.120 –.008
(Mounting height)
1
24
0.80(.031)
"A"
C
0.37±0.05
(.015±.002)
0.16(.006)
0~8˚
M
0.17±0.06
(.007±.002)
0.80±0.20
(.031±.008)
0.88±0.15
(.035±.006)
+0.10
0.30 –0.25
+.004
.012 –.010
(Stand off)
2002 FUJITSU LIMITED F80010S-c-6-5
Dimensions in mm (inches)
Note : The values in parentheses are reference values.
(Continued)
97
MB90820 Series
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
80-pin plastic LQFP
(FPT-80P-M11)
16.00±0.20(.630±.008)SQ
* 14.00±0.10(.551±.004)SQ
60
0.145±0.055
(.006±.002)
41
40
61
0.10(.004)
Details of "A" part
+0.20
+.008
1.50 –0.10 .059 –.004
(Mounting height)
0.25(.010)
INDEX
0~8˚
21
80
1
0.65(.026)
C
"A"
20
0.32±0.05
(.013±.002)
0.13(.005)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.10±0.10
(.004±.004)
(Stand off)
M
2003 FUJITSU LIMITED F80016S-c-3-6
Dimensions in mm (inches)
Note : The values in parentheses are reference values.
(Continued)
98
MB90820 Series
(Continued)
80-pin plastic LQFP
(FPT-80P-M05)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
14.00±0.20(.551±.008)SQ
* 12.00±0.10(.472±.004)SQ
60
0.145±0.055
(.006±.002)
41
61
40
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
.059 –.004
INDEX
0˚~8˚
80
0.10±0.10
(.004±.004)
(Stand off)
21
"A"
LEAD No.
1
20
0.50(.020)
C
(Mounting height)
0.20±0.05
(.008±.002)
0.08(.003)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)
M
2003 FUJITSU LIMITED F80008S-c-4-8
Dimensions in mm (inches)
Note : The values in parentheses are reference values.
99
MB90820 Series
The information for microcontroller supports is shown in the following homepage.
http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
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circuit examples, in this document are presented solely for the
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operation of the device with respect to use based on such
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device based on such information, you must assume any
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assumes no liability for any damages whatsoever arising out of
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function and schematic diagrams, shall not be construed as license
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and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
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and manufactured as contemplated (1) for use accompanying fatal
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satellite).
Please note that Fujitsu will not be liable against you and/or any
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F0510
© 2005 FUJITSU LIMITED Printed in Japan
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