CM71-10155-2E

FUJITSU SEMICONDUCTOR
CONTROLLER MANUAL
CM71-10155-2E
FR60
32-BIT MICROCONTROLLER
MB91490 Series
HARDWARE MANUAL
FR60
32-BIT MICROCONTROLLER
MB91490 Series
HARDWARE MANUAL
For the information for microcontroller supports, see the following web site.
http://edevice.fujitsu.com/micom/en-support/
FUJITSU SEMICONDUCTOR LIMITED
PREFACE
■ Objectives and intended reader
Thank you very much for your continued patronage of Fujitsu semiconductor products.
The MB91490 series is a standard microcontroller that has a 32-bit high-performance RISC CPU as well as
built-in I/O resources and bus control mechanisms for embedded controller that requires high-performance
and high-speed CPU processing. The MB91490 series has built-in RAM (for data) to increase the speed at
which the CPU executes instructions.
This manual is intended for engineers who will develop products using the MB91490 series and describes
the functions and operations of the MB91490 series. Read this manual thoroughly.
For more information on instructions, see the "Instructions Manual".
■ Trademark
The company names and brand names herein are the trademarks or registered trademarks of their respective
owners.
FR, the abbreviation of FUJITSU RISC controller, is a line of products of Fujitsu Semiconductor Limited.
■ Structure of This Manual
This manual consists of the following 23 chapters and an appendix.
CHAPTER 1 OVERVIEW
This chapter provides basic information required to understand the MB91490 series, and covers features,
a block diagram, and package dimension.
CHAPTER 2 HANDLING DEVICES
This chapter provides precautions on handling the device.
CHAPTER 3 CPU AND CONTROL UNIT
This chapter provides basic information required to understand the CPU core functions of the MB91490
series. It covers architecture, specifications, and instructions.
CHAPTER 4 I/O PORTS
This chapter outlines the I/O ports and describes the configuration and functions of their registers.
CHAPTER 5 INTERRUPT CONTROLLER
This chapter explains the overview of the interrupt controller, the configuration and functions of
registers, and interrupt controller operation.
CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER
This chapter describes the overview of the external interrupt and NMI controller, the configuration and
functions of registers, and operation of the external interrupt and NMI controller.
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CHAPTER 7 REALOS-RELATED HARDWARE
The REALOS-related hardware is used by the real-time OS. Accordingly, these functions cannot be used
by user programs if using REALOS. This chapter explains the overview of the delayed interrupt module
and bit search module, the configuration and functions of the registers, and the operation of the delayed
interrupt module and bit search module.
CHAPTER 8 16-BIT RELOAD TIMER
This chapter describes the overview of the reload timer, the configuration and functions of registers, and
the reload timer operation.
CHAPTER 9 TIMING GENERATOR
This chapter explains the overview of the timing generator, the configuration and functions of registers,
and operation of the timing generator.
CHAPTER 10 PPG
This chapter explains the overview of the timing generator, the configuration and functions of registers,
and operation of the timing generator.
CHAPTER 11 MULTI-FUNCTION TIMER
This chapter explains the overview of the multi-function timer, the configuration and functions of
registers, and operation of the multi-function timer.
CHAPTER 12 BASE TIMER
This chapter provides an overview of the base timer, summarizes its register configuration and functions,
and describes its operations.
CHAPTER 13 UP/DOWN COUNTER
This chapter describes the function and operation of 8/16-bit up/down counter.
CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
This chapter describes the functions and operations of the multi-function serial interface.
CHAPTER 15 8/10-BIT A/D CONVERTER
This chapter describes the overview of the 8/10-bit A/D converter, the configuration and functions of
registers, and the operation of the 8/10-bit A/D converter.
CHAPTER 16 DMA CONTROLLER (DMAC)
This chapter describes the DMAC, the configuration and functions of registers, and DMAC operation.
CHAPTER 17 FLASH MEMORY
This chapter explains the overview of the flash memory, the configuration and functions of registers, and
the flash memory operation.
CHAPTER 19 SERIAL PROGRAMMING CONNECTION
MB91F49x supports serial onboard write (Fujitsu Semiconductor standard) to flash memory.
CHAPTER 20 WILD REGISTER CONTROL BLOCK
This chapter describes the register configuration, functions and timer operations of the wild register
control block.
APPENDIX
The appendix describes pin states in each CPU state, notes on using the little-endian areas, a list of FR
family instructions, and notes on using MB91490 series.
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The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU
SEMICONDUCTOR does not warrant proper operation of the device with respect to use based on such information. When you
develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such
use of the information. FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of
the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU
SEMICONDUCTOR or any third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's
intellectual property right or other right by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any
infringement of the intellectual property rights or other rights of third parties which would result from the use of information
contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured,
could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss
(i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life
support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible
repeater and artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages
arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the
regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Copyright ©2009-2010 FUJITSU SEMICONDUCTOR LIMITED All rights reserved.
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CONTENTS
CHAPTER 1
1.1
1.2
1.3
1.4
1.5
1.6
CHAPTER 2
2.1
OVERVIEW ................................................................................................... 1
Overview ............................................................................................................................................. 2
Block Diagram .................................................................................................................................... 7
Pin Assignment ................................................................................................................................... 8
Package Dimension ............................................................................................................................ 9
List of Pin Functions ......................................................................................................................... 11
I/O Circuit Type ................................................................................................................................. 16
HANDLING DEVICES ................................................................................ 19
Precautions on Handling the Device ................................................................................................. 20
CHAPTER 3
CPU AND CONTROL UNIT ....................................................................... 25
3.1
Memory Space ..................................................................................................................................
3.2
Memory Map .....................................................................................................................................
3.3
Internal Architecture ..........................................................................................................................
3.4
Programming Model .........................................................................................................................
3.4.1
Registers .....................................................................................................................................
3.5
Data Structure ...................................................................................................................................
3.6
Memory Map .....................................................................................................................................
3.7
Divergence Instructions ....................................................................................................................
3.8
EIT (Exception, Interruption, and Trap) ............................................................................................
3.9
Operating Mode ................................................................................................................................
3.9.1
Mode Setting ...............................................................................................................................
3.9.2
Note .............................................................................................................................................
3.10 Reset (Device Initialization) ..............................................................................................................
3.10.1 Reset Level ..................................................................................................................................
3.10.2 Reset Factor ................................................................................................................................
3.10.3 Reset Sequence ..........................................................................................................................
3.10.4 Oscillation Stabilization Wait Time ..............................................................................................
3.10.5 Reset Operation Mode ................................................................................................................
3.11 Clock Generation Control .................................................................................................................
3.11.1 Selection of the Source Clock .....................................................................................................
3.11.2 PLL Control ..................................................................................................................................
3.11.3 Oscillation Stabilization Wait and PLL Lock Wait Time ...............................................................
3.11.4 Clock Distribution .........................................................................................................................
3.11.5 Clock Divider ...............................................................................................................................
3.11.6 Block Diagram of Clock Generation Control Unit ........................................................................
3.11.7 Explanation of Register Details for Clock Generation Control Unit .............................................
3.11.8 Peripheral Circuit Functions in the Clock Controller ....................................................................
3.12 Device State Control .........................................................................................................................
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CHAPTER 4
I/O PORTS ................................................................................................ 109
4.1
Overview of I/O Port .......................................................................................................................
4.2
Block Diagrams of I/O Port .............................................................................................................
4.2.1
Normal I/O Port ..........................................................................................................................
4.2.2
External Interrupt Input I/O Port .................................................................................................
4.2.3
Analog Input I/O Port .................................................................................................................
4.2.4
Multi-Function Timer I/O Port ....................................................................................................
4.3
I/O Port Registers ...........................................................................................................................
CHAPTER 5
5.1
5.2
5.3
5.4
5.5
6.1
6.2
6.3
EXTERNAL INTERRUPT AND NMI CONTROLLER ............................... 143
REALOS-RELATED HARDWARE .......................................................... 153
Delayed Interrupt Module ............................................................................................................... 154
Bit Search Module .......................................................................................................................... 156
CHAPTER 8
16-BIT RELOAD TIMER ........................................................................... 161
8.1
Overview of 16-bit Reload Timer ....................................................................................................
8.2
16-bit Reload Timer Register ..........................................................................................................
8.2.1
Control Status Register (TMCSR) .............................................................................................
8.2.2
16-bit Timer Register (TMR) ......................................................................................................
8.2.3
16-bit Reload Register (TMRLR) ...............................................................................................
8.3
Operation of 16-bit Reload Timer ...................................................................................................
CHAPTER 9
9.1
9.2
9.3
9.3.1
9.3.2
9.4
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Overview of External Interrupt/NMI Controller ................................................................................ 144
Registers of External Interrupt/NMI Controller ................................................................................ 146
Operation of External Interrupt/NMI Controller ............................................................................... 148
CHAPTER 7
7.1
7.2
INTERRUPT CONTROLLER ................................................................... 129
Overview of Interrupt Controller ......................................................................................................
Interrupt Controller Registers ..........................................................................................................
Block Diagram of Interrupt Controller .............................................................................................
Register Details Explanation of Interrupt Controller ........................................................................
Operation of Interrupt Controller .....................................................................................................
CHAPTER 6
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TIMING GENERATOR ............................................................................. 171
Overview of Timing Generator ........................................................................................................
Block Diagram of Timing Generator ...............................................................................................
Registers of Timing Generator ........................................................................................................
Timing Generator Control Register (TTCR0) .............................................................................
Compare Register (COMP0/COMP2/COMP4/COMP6) ............................................................
Operation of Timing Generator .......................................................................................................
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CHAPTER 10 PPG .......................................................................................................... 181
10.1 Overview of PPG ............................................................................................................................
10.2 Block Diagram of PPG ....................................................................................................................
10.3 Registers of PPG ............................................................................................................................
10.3.1 PPG Operation Mode Control Registers (PPGC0 to PPGC7) ...................................................
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10.3.2 Reload Registers (PRLH0 to PRLH7, PRLL0 to PRLL7) ..........................................................
10.3.3 PPG Trigger Register (TRG) .....................................................................................................
10.3.4 Output Inversion Register (REVC) ............................................................................................
10.3.5 GATE Function Control Registers (GATEC0/GATEC4) ............................................................
10.4 Operation Explanation of PPG ........................................................................................................
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CHAPTER 11 MULTI-FUNCTION TIMER ....................................................................... 201
11.1 Overview of the Multi-function Timer .............................................................................................. 202
11.2 Block Diagram of the Multi-function Timer ...................................................................................... 205
11.3 Pins of the Multi-function Timer ...................................................................................................... 211
11.4 Multi-function Timer Register .......................................................................................................... 212
11.4.1 Compare Clear Buffer Register (CPCLRBH0 to CPCLRBH2, CPCLRBL0 to CPCLRBL2) /
Compare Clear Register (CPCLRH0 to CPCLRH2, CPCLRL0 to CPCLRL2) ........................... 219
11.4.2 Timer Data Register (TCDTH0 to TCDTH2, TCDTL0 to TCDTL2) ............................................ 221
11.4.3 Timer State Control Register (TCCSH0 to TCCSH2, TCCSL0 to TCCSL2, TCCSM0 to TCCSM2)
...................................................................................................................................................... 222
11.4.4 A/D Trigger Control Register (ADTRGC0 to ADTRGC2) ........................................................... 229
11.4.5 Free-run Timer Selection Register (FRS0 to FRS4) .................................................................. 231
11.4.6 Output Compare Buffer Register (OCCPBH0 to OCCPBH5, OCCPBL0 to OCCPBL5) /
Output Compare Register (OCCPH0 to OCCPH5, OCCPL0 to OCCPL5) ................................ 236
11.4.7 Compare Control Register (OCSH0 to OCSH5, OCSL0 to OCSL5) ......................................... 238
11.4.8 Compare Mode Control Register (OCMOD0) ............................................................................ 243
11.4.9 Input Capture Data Register (IPCPH0 to IPCPH3, IPCPL0 to IPCPL3) .................................... 245
11.4.10 Input Capture State Control/PPG Output Control Register (ICSH23, ICSL23, PICSH01, PICSL01)
..................................................................................................................................................... 246
11.4.11 16-bit Dead Timer Register (TMRRH0 to TMRRH2, TMRRL0 to TMRRL2) ............................. 254
11.4.12 16-bit Dead Timer Control Register (DTCR0 to DTCR2) ........................................................... 255
11.4.13 Waveform Control Register (SIGCR1/SIGCR2) ........................................................................ 261
11.4.14 A/D Activation Compare Register (ADCOMPB0, ADCOMPB2, ADCOMP0, ADCOMP2,
ADTGCE0, ADTGSEL0, ADTGBUF0) ...................................................................................... 265
11.5 Multi-function Timer Interrupt .......................................................................................................... 273
11.6 Operation of the Multi-function Timer ............................................................................................. 276
11.6.1 Operation of 16-bit Free-run Timer ............................................................................................ 277
11.6.2 Operation of Free-run Timer Selector ........................................................................................ 285
11.6.3 Operation of 16-bit Output Compare ......................................................................................... 286
11.6.4 16-bit Input Capture Operation .................................................................................................. 299
11.6.5 Waveform Generator Operation ................................................................................................ 301
11.6.6 A/D Activation Compare Operation ........................................................................................... 311
11.7 Notes on Using the Multi-function Timer ......................................................................................... 317
11.8 Example Program for Multi-function Timer ..................................................................................... 319
CHAPTER 12 BASE TIMER ............................................................................................ 323
12.1
12.2
12.3
12.4
12.5
12.6
Overview of the Base Timer ...........................................................................................................
Block Diagrams of the Base Timer .................................................................................................
Base Timer's Registers ...................................................................................................................
Operations of the Base Timer .........................................................................................................
32-bit Mode Operations ..................................................................................................................
Notes of Using the Base Timer .......................................................................................................
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12.7 Base Timer Interrupts .....................................................................................................................
12.8 Base Timer Description by Function Mode .....................................................................................
12.8.1 PWM Function ...........................................................................................................................
12.8.2 PPG Function ............................................................................................................................
12.8.3 Reload Timer Function ..............................................................................................................
12.8.4 PWC Function ...........................................................................................................................
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CHAPTER 13 UP/DOWN COUNTER .............................................................................. 399
13.1 Overview of Up/Down Counter .......................................................................................................
13.2 Block Diagram of Up/Down Counter ...............................................................................................
13.3 Register of Up/Down Counter .........................................................................................................
13.3.1 Up/Down Count Register (UDCR) .............................................................................................
13.3.2 Reload Compare Register (RCR) ..............................................................................................
13.3.3 Counter Status Register (CSR) .................................................................................................
13.3.4 Counter Control Register (CCR) ................................................................................................
13.4 Operation of Up/Down Counters .....................................................................................................
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE ............................................... 419
14.1 Characteristics of Multi-function Serial Interface ............................................................................ 421
14.2 UART (Asynchronous Serial Interface) ........................................................................................... 422
14.3 Overview of UART (Asynchronous Serial Interface) ....................................................................... 423
14.4 Registers of UART (Asynchronous Serial Interface) ...................................................................... 424
14.4.1 Serial Control Register (SCR) ................................................................................................... 426
14.4.2 Serial Mode Register (SMR) ...................................................................................................... 428
14.4.3 Serial Status Register (SSR) ..................................................................................................... 430
14.4.4 Extended Communication Control Register (ESCR) ................................................................. 432
14.4.5 Reception Data Register / Transmission Data Register (RDR0 to RDR2/TDR0 to TDR2) ....... 434
14.4.6 Baud Rate Generator Registers 1, 0 (BGR1, BGR0) ................................................................ 436
14.5 Interrupts of UART .......................................................................................................................... 438
14.5.1 Occurrence of Reception Interrupts and Flag Set Timing ......................................................... 439
14.5.2 Occurrence of Transmission Interrupts and Flag Set Timing .................................................... 440
14.6 Operation of UART ......................................................................................................................... 441
14.7 Dedicated Baud Rate Generator .................................................................................................... 445
14.7.1 Setting Baud Rate ..................................................................................................................... 446
14.8 Setup Procedure and Program Flow for Operation Mode 0 (Asynchronous Normal Mode) ........... 450
14.9 Setup Procedure and Program Flow for Operation Mode 1 (Asynchronous Multi-processor Mode)
......................................................................................................................................................... 451
14.10 Notes on UART Mode ..................................................................................................................... 454
14.11 CSIO (Clock Synchronous Serial Interface) ................................................................................... 455
14.12 Overview of CSIO (Clock Synchronous Serial Interface) ............................................................... 456
14.13 Registers of CSIO (Clock Synchronous Serial Interface) ............................................................... 457
14.13.1 Serial Control Register (SCR) ................................................................................................... 458
14.13.2 Serial Mode Register (SMR) ...................................................................................................... 460
14.13.3 Serial Status Register (SSR) ..................................................................................................... 462
14.13.4 Extended Communication Control Register (ESCR) ................................................................. 464
14.13.5 Reception Data Register / Transmission Data Register (RDR/TDR) ......................................... 466
14.13.6 Baud Rate Generator Registers 1, 0 (BGR1, BGR0) ................................................................ 468
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14.14 Interrupts of CSIO (Clock Synchronous Serial Interface) ...............................................................
14.14.1 Occurrence of Reception Interrupts and Flag Set Timing .........................................................
14.14.2 Occurrence of Transmission Interrupts and Flag Set Timing ....................................................
14.15 Operation of CSIO (Clock Synchronous Serial Interface) ...............................................................
14.16 Dedicated Baud Rate Generator ....................................................................................................
14.16.1 Setting Baud Rate .....................................................................................................................
14.17 Setup Procedure and Program Flow for CSIO (Clock Synchronous Serial Interface) ....................
14.18 Notes on CSIO Mode ......................................................................................................................
14.19 I2C Interface ....................................................................................................................................
14.20 Overview of I2C Interface ................................................................................................................
14.21 Registers of I2C Interface ...............................................................................................................
14.21.1 I2C Bus Control Register (IBCR) ...............................................................................................
14.21.2 Serial Mode Register (SMR) ......................................................................................................
14.21.3 I2C Bus Status Register (IBSR) .................................................................................................
14.21.4 Serial Status Register (SSR) .....................................................................................................
14.21.5 Reception Data Register / Transmission Data Register (RDR/TDR) .........................................
14.21.6 7-bit Slave Address Mask Register (ISMK) ...............................................................................
14.21.7 7-bit Slave Address Register (ISBA) .........................................................................................
14.21.8 Baud Rate Generator Registers 1, 0 (BGR1, BGR0) ................................................................
14.22 Interrupts of I2C Interface ...............................................................................................................
14.22.1 Operation of I2C Interface Communication ................................................................................
14.22.2 Master Mode ..............................................................................................................................
14.22.3 Slave Mode ................................................................................................................................
14.22.4 Bus Error ...................................................................................................................................
14.23 Dedicated Baud Rate Generator ....................................................................................................
14.23.1 Example of I2C Flowcharts ........................................................................................................
14.24 Notes on I2C Mode .........................................................................................................................
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CHAPTER 15 8/10-BIT A/D CONVERTER ..................................................................... 535
15.1 Overview of the 8/10-bit A/D Converter ..........................................................................................
15.2 Configuration of the 8/10-bit A/D Converter ....................................................................................
15.3 Pin of the 8/10-bit A/D Converter ....................................................................................................
15.4 Registers of the 8/10-bit A/D Converter .........................................................................................
15.4.1 A/D Channel Control Register (ADCH) ......................................................................................
15.4.2 A/D Mode Setting Register (ADMD) ..........................................................................................
15.4.3 A/D Control Status Register (ADCS) .........................................................................................
15.4.4 A/D Data Register (ADCD) ........................................................................................................
15.4.5 Analog Input Control Register (AICR) .......................................................................................
15.5 Interrupt of the 8/10-bit A/D Converter ............................................................................................
15.6 Operation Explanation of the 8/10-bit A/D Converter .....................................................................
15.7 A/D Conversion Data Protection Function of the 8/10-bit A/D Converter .......................................
15.8 Using Memorandum of the 8/10-bit A/D Converter .........................................................................
15.9 Notes on Using the 8/10-bit A/D Converter ....................................................................................
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CHAPTER 16 DMA CONTROLLER (DMAC) .................................................................. 563
16.1
16.2
Overview of the DMAC ................................................................................................................... 564
Detailed Explanation of the DMAC Registers ................................................................................. 567
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16.2.1 DMAC ch.0,ch.1,ch.2,ch.3,ch.4 Control/Status Registers A ......................................................
16.2.2 DMAC ch.1,ch.2,ch.3,ch.4 Control/Status Registers B .............................................................
16.2.3 DMAC ch.1,ch.2,ch.3,ch.4 Transfer Source/Transfer Destination Address Setting Registers ..
16.2.4 DMAC ch.1,ch.2,ch.3,ch.4 DMAC All-Channel Control Register ...............................................
16.3 Explanation of the DMAC Operation ...............................................................................................
16.3.1 Overview of the DMAC Operation .............................................................................................
16.3.2 Setting a Transfer Request ........................................................................................................
16.3.3 Transfer Sequence ....................................................................................................................
16.3.4 General Aspects of DMA Transfer .............................................................................................
16.3.5 Addressing Mode .......................................................................................................................
16.3.6 Data Types ................................................................................................................................
16.3.7 Transfer Count Control ..............................................................................................................
16.3.8 CPU Control ..............................................................................................................................
16.3.9 Operation Start ..........................................................................................................................
16.3.10 Transfer Request Acceptance and Transfer ..............................................................................
16.3.11 Clearing Peripheral Interrupts by DMA ......................................................................................
16.3.12 Temporary Stopping ..................................................................................................................
16.3.13 Operation End/Stopping ............................................................................................................
16.3.14 Stopping due to an Error ...........................................................................................................
16.3.15 DMAC Interrupt Control .............................................................................................................
16.3.16 DMA Transfer during Sleep .......................................................................................................
16.3.17 Channel Selection and Control ..................................................................................................
16.4 Operation Flowcharts of the DMAC ................................................................................................
16.5 Data Bus of the DMAC ...................................................................................................................
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CHAPTER 17 FLASH MEMORY ..................................................................................... 607
17.1 Overview of Flash Memory .............................................................................................................
17.2 Flash Memory Registers .................................................................................................................
17.2.1 Flash Control/Status Register (FLCR) .......................................................................................
17.2.2 Flash Wait Register (FLWC) ......................................................................................................
17.3 Explanation of Flash Memory Operation ........................................................................................
17.4 Flash Memory Automatic Algorithms ..............................................................................................
17.4.1 Command Sequence .................................................................................................................
17.4.2 Confirming Automatic Algorithm Execution States ....................................................................
17.5 Details of Programming and Erasing Flash Memory ......................................................................
17.5.1 Read/Reset State ......................................................................................................................
17.5.2 Programming Data ....................................................................................................................
17.5.3 Erasing Data (Chip Erase) .........................................................................................................
17.5.4 Erasing Data (Sector Erase) ......................................................................................................
17.5.5 Suspending Sector Erasure .......................................................................................................
17.5.6 Resuming Sector Erasure .........................................................................................................
17.6 Flash Security Feature ....................................................................................................................
17.7 Notes on Flash Memory Programming ...........................................................................................
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CHAPTER 18 LOW VOLTAGE DETECTION INTERRUPT / RESET ............................. 641
18.1
18.2
18.3
18.4
18.5
18.6
18.7
Overview of the Low Voltage Detection Interrupt / Reset ...............................................................
Block Diagram of Low Voltage Detection Interrupt / Reset .............................................................
Low Voltage Detection Interrupt Register .......................................................................................
Detailed Explanation for Registers of Low Voltage Detection Interrupt ..........................................
Operation of Low Voltage Detector 0 ..............................................................................................
Operation of Low Voltage Detection Interrupt .................................................................................
Operation of Low Voltage Detector 1 ..............................................................................................
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CHAPTER 19 SERIAL PROGRAMMING CONNECTION .............................................. 653
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CHAPTER 20 WILD REGISTER CONTROL BLOCK ..................................................... 659
20.1 Overview of Wild Register Control Block ........................................................................................
20.2 Registers of Wild Register Control Block ........................................................................................
20.2.1 Wild Register Enable Register (WREN) ....................................................................................
20.2.2 Wild Register Address Register (WA) .......................................................................................
20.2.3 Wild Register Data Register (WD) .............................................................................................
20.3 Operations of Wild Register Control Block .....................................................................................
20.4 Restrictions and Notes ....................................................................................................................
660
661
662
663
664
665
666
APPENDIX ......................................................................................................................... 667
APPENDIX A I/O Map ................................................................................................................................
APPENDIX B Interrupt Vector ....................................................................................................................
APPENDIX C Pin States in Each CPU State ..............................................................................................
APPENDIX D Notes when Little Endian Area is used ................................................................................
APPENDIX E INSTRUCTION LISTS .........................................................................................................
E.1 FR Family Instruction Lists .............................................................................................................
APPENDIX F Precautions when Using ......................................................................................................
668
682
686
688
693
698
715
INDEX................................................................................................................................... 719
CM71-10155-2E
FUJITSU SEMICONDUCTOR LIMITED
xi
MB91490 Series
xii
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
MB91490 Series
Major changes in this edition
Page
Changes (For details, refer to main body.)
209
CHAPTER 11 MULTI-FUNCTION
TIMER
11.2 Block Diagram of the Multifunction Timer
Corrected Figure in "■ Block Diagram of the Waveform Generator".
(RT0/RT1  RT2/RT3)
292
CHAPTER 11 MULTI-FUNCTION
TIMER
11.6.3 Operation of 16-bit Output
Compare
■ Operation of 16-bit Output Compare
and Free-run Timerì
Corrected Figure in "● When the free-run timer up-counts".
295
296
Corrected "Notes:".
Added Figure of "Buffer transfer: compare match, CMOD=0".
Corrected "Notes:".
Added Figure of "Buffer transfer: zero detection, CMOD=0".
297
Corrected "Notes:".
Added Figure of "Buffer transfer: compare match, CMOD=1".
298
Corrected "Notes:".
Added Figure of "Buffer transfer: zero detection, CMOD=1".
306
307
454
488
CHAPTER 11 MULTI-FUNCTION
TIMER
11.6.5.2 Operation during Dead Time
Timer Mode
■ Operation During Dead Time Timer
Mode
Changed explanation in "● This non-overlapping signal is generated
via normal-polarity RT 1, RT 3, and RT 5 (16-bit dead timer control
registers (DTCR0, DTCR1, and DTCR2)TMD8 to TMD0 (higherorder bits are 10 to 8; lowerorder
bits are 2 to 0) =100B)"
CHAPTER 11 MULTI-FUNCTION
TIMER
11.6.5.2 Operation during Dead Time
Timer Mode
Added "■ Notes on using the dead time timer mode".
CHAPTER 14 MULTI-FUNCTION
SERIAL INTERFACE
Added "14.10 Notes on UART Mode".
533
Changed explanation in "● This non-overlapping signal is generated
via reverse-polarity RT1, RT3, and RT5 (16-bit dead timer control
registers (DTCR0, DTCR1, and DTCR2) TMD8 to TMD0 (higherorder bits are 10 to 8; lowerorder bits are 2 to 0) = 100B).
Added "14.18 Notes on CSIO Mode".
Added "14.24 Notes on I2C Mode".
694
APPENDIX E INSTRUCTION LISTS
■ How to Read the Instruction Lists
Changed explanation 5) .
ST Rs, or @R15 instruction  "ST Rs, @-R15" instruction
704
E.1 FR Family Instruction Lists
■ Memory Load Instructions
Corrected "Note:".
04  u4
705
■ Memory Store Instructions
Corrected "Note:".
04  u4
The vertical lines marked in the left side of the page show the changes.
CM71-10155-2E
FUJITSU SEMICONDUCTOR LIMITED
xiii
MB91490 Series
xiv
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
CHAPTER 1
OVERVIEW
This chapter provides basic information required to
understand the MB91490 series, and covers features, a
block diagram, and package dimension.
1.1 Overview
1.2 Block Diagram
1.3 Pin Assignment
1.4 Package Dimension
1.5 List of Pin Functions
1.6 I/O Circuit Type
CM71-10155-2E
FUJITSU SEMICONDUCTOR LIMITED
1
CHAPTER 1 OVERVIEW
1.1 Overview
1.1
MB91490 Series
Overview
The MB91490 series is a line of Fujitsu Semiconductor’s general-purpose 32-bit RISC
microcontrollers designed for embedded control applications which require high-speed
processing.
■ Features of FR CPU
• 32-bit RISC, load/store architecture, 5-stage pipeline
• Maximum operating frequency of 50MHz to 80MHz (PLL clock multiplier)
• 16-bit fixed-length instructions (basic instruction)
• Instruction execution speed: One instruction per cycle
• Memory-to-memory transfer instructions, bit processing instructions, and barrel shift instructions:
instructions appropriate for embedded applications
• Function entry and exit instructions, multi-load/store instructions of register content: instructions
compatible with C language
• Register interlock function: facilitate assembly-language coding
• Built-in multiplier/instruction-level support
Signed 32-bit multiplication: 5 cycles
Signed 16-bit multiplication: 3 cycles
• Interrupts (saving of PC and PS): 6 cycles (16 priority levels)
• Harvard architecture enabling simultaneous execution of both program access and data access
• Instruction compatible with the FR family
■ I/O Port
• Capable of pull-up control per pin
• Capable of reading pin level directly
■ External Interrupt Input
• Include one non-maskable interrupt (NMI) pin
• Use for wake up at stop
■ Bit Search Module (for REALOS)
Function for searching for the first 1-to-0 change bit position from MSB (upper bit) in each word.
■ 16-bit Reload Timer
• Includes 1 channel for REALOS
• Internal clock can be selected using divide by 2/8/32
■ Timing Generator
The delay start of the PPG timers can be executed synchronously between the timers.
■ 8/16-bit PPG Timer
■ Multi-function Timer
● 16-bit free-run timer
● Input capture
Interface with free-run timer
2
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
CHAPTER 1 OVERVIEW
1.1 Overview
MB91490 Series
● Output compare
Interface with free-run timer
● A/D activating compare
Interface with free-run timer
● Waveform generator
Various waveforms are generated by using output compare output, 16-bit PPG timer and 16-bit dead timer.
■ Base Timer
Only one timer function can be selected from the 16-bit PWM timer, 16-bit PPG timer, 16/32-bit reload
timer, and 16/32-bit PWC timer.
■ 8/16-bit Up-Down Counter
■ Multi-function Serial Interface
• Full-duplex double buffer
• Asynchronous (start-stop synchronization) communication, clock synchronous communication, I2C
standard mode (Max 100kbps), I2C high-speed mode (selectable various modes at maximum of
400kbps)
• Selectable parity On/Off
• Each channel has built-in baud rate generator
• Error detection function for parity, frame and overrun errors
• External clock can be used as transfer clock
• With I2C function
■ 8/10-bit A/D Converter (Successive Comparison Type)
• 8/10-bit resolution selectable
• Conversion Time:
1.2s (minimum conversion time for 33 MHz peripheral clock (CLKP))
1.2s (minimum conversion time for 40 MHz peripheral clock (CLKP))
■ DMAC (DMA Controller)
• Five channels or less can operate at the same time
• The transfer can be started by two transfer factors (built-in peripheral interrupt and software)
• Addressing mode: 32-bit full addressing (increase/decrease/fix)
• Transfer mode (burst transfer/step transfer/block transfer)
• The transferring data size can be selected from 8/16/32 bits
• Multi-byte can be transferred (by software)
■ Wild Register Function
Replace instruction/data at the target address (within the built-in Flash area only)
■ Low Voltage Detection Interrupt / Reset
• Detects low voltage (3.7V + 0.3V) and generate external interrupt
• Detects low voltage (3.0V + 0.24V) and generate system initialization reset
■ Flash Memory Security Feature
• Protects the content of flash memory
CM71-10155-2E
FUJITSU SEMICONDUCTOR LIMITED
3
CHAPTER 1 OVERVIEW
1.1 Overview
MB91490 Series
■ Other Features
• Has a built-in oscillation circuit as a clock source for which PLL multiplication can be selected
• INITX is provided as a reset pin
• Additionally, a watchdog timer reset and software resets are provided
• Stop mode and sleep mode supported as low-power consumption modes
• Clock division ratio setting function
• Built-in time-base timer
• CMOS 0.18m technology
• Power supply: 1-power supply [Vcc=2.7V to 5.5V]
• 1.9V is supplied for the internal circuit by the internal step-down circuit
4
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
CHAPTER 1 OVERVIEW
1.1 Overview
MB91490 Series
■ Package Lineup
Product name
MB91F492
Package
FPT-64P-M23
(LQFP-0.65 mm)
FPT-64P-M24
(LQFP-0.50 mm)
: Supported
Note: For details of each package, refer to "1.4 Package Dimension".
■ Components of Each Model
Series common EVA
MB91490 series
MB91FV470
MB91F492
512 Kbytes
(Flash)
256 Kbytes
(Flash)
Characteristics
Built-in Flash capacity
Flash security
Built-in RAM capacity
40 Kbytes
12 Kbytes
160
49
NMI + 16 channels
NMI + 7 channels
2 channels
2 channels
2 units
1 unit
8-bit × 16 channels
16-bit × 8 channels
8-bit × 8 channels
16-bit x 4 channels
(PPG output: 3 channels)
2 units
1 unit
Free-run timer
6 channels
3 channels
OCU
12 channels
6 channels
ICU
8 channels
4 channels
A/D activation compare
6 channels
2 channels
Waveform generator
12 channels
6 channels
Base timer
6 channels
2 channels
I/O ports
External interrupts
Reload timer
Timing generator
PPG
Multi-function timer
(Continued)
CM71-10155-2E
FUJITSU SEMICONDUCTOR LIMITED
5
CHAPTER 1 OVERVIEW
1.1 Overview
MB91490 Series
(Continued)
Series common EVA
MB91490 series
MB91FV470
MB91F492
2 channels
1 channel
6 units (w FIFO)
3 units (w/o FIFO)
4 channels × 2 units
16 channels × 1 unit
4 channels × 1 unit
8 channels × 1 unit
Low voltage detection
interrupt
-
1 channel
Low voltage detection
reset
-
1 channel
DMAC
5 channels
5 channels
Wild register
16 channels
16 channels
DSU4
-
Characteristics
Up/down counter
Multi-function serial
interface
8/10-bit A/D converter
Debug function
: Supported
6
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
CHAPTER 1 OVERVIEW
1.2 Block Diagram
MB91490 Series
1.2
Block Diagram
This section shows the block diagram of the MB91490 series.
■ Block Diagram
Figure 1.2-1 Block Diagram
VCC
VSS
C
FR60 CPU core
Voltage
regulator
Watchdog timer
Bit search
(with security
Max-256Kbytes)
32
32
D-bus RAM
(Max-8Kbytes)
F-bus RAM
5 channels DMAC
Bus converter
(Max-4Kbytes)
32
32
2 channels
Low voltage
detection
MD2 to MD0
INITX
X0
X1
32 ↔ 16
adapter
Clock control
16
16
NMIX
INT0 to INT6
1+7 channels
external interrupt
Interrupt controller
SCK0 to SCK2
SIN0 to SIN2
SOT0 to SOT2
Port I/F
3 units
multi-function
serial interface
1 channel
up/down counter
1 channel
timing generator
GPIO
AIN0
BIN0
ZIN0
2 channels
reload timer
8 channels
PPG
PPG4 to PPG6
AVCC10
AVSS10
AVRH2
ADTG1
AN1-0 to AN1-3
4 channels input
8/10-bit A/D converter 1
ADTG2
AN2-0 to AN2-7
8 channels input
8/10-bit A/D converter 2
2 channels
base timer
TIN0, TIN1
TOUT0, TOUT1
- PWC
- Reload timer
- PWM
- PPG
Multifunction timer
2 channels
A/D activating
compare
4 channels
input capture
IC0 to IC3
3 channels
free-run timer
CKI0
6 channels
output compare
6 channels
waveform
generator
CM71-10155-2E
RTO0 to RTO5
DTTI0
FUJITSU SEMICONDUCTOR LIMITED
7
CHAPTER 1 OVERVIEW
1.3 Pin Assignment
1.3
MB91490 Series
Pin Assignment
This section shows the pin assignment and package dimension of MB91490 series.
■ Pin Assignment
Figure 1.3-1 Pin Layout
VSS
X1
X0
MD0
MD1
MD2
PA1/ADTG1
PA2/ADTG2
P80/INT0
P81/INT1
P82/INT2
P83/INT3
P84/PPG4/INT4
P85/PPG5/INT5
P86/PPG6/INT6
NMIX
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
PG0/SCK0
PG1/SIN0
PG2/SOT0
PG3/SCK1
PG4/SIN1
PG5/SOT1
PH0/SCK2
PH1/SIN2
PH2/SOT2
PQ0/RTO0
PQ1/RTO1
PQ2/RTO2
PQ3/RTO3
PQ4/RTO4
PQ5/RTO5
VCC
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VCC
PC7/AN2-7
PC6/AN2-6
PC5/AN2-5
PC4/AN2-4
PC3/AN2-3
PC2/AN2-2
PC1/AN2-1
PC0/AN2-0
AVSS10
AVRH2
AVCC10
PB7/AN1-3
PB6/AN1-2
PB5/AN1-1
PB4/AN1-0
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
INITX
PJ3/TOUT1
PJ2/TIN1
PJ1/TOUT0
PJ0/TIN0
PL2/ZIN0
PL1/BIN0
PL0/AIN0
PP5/DTTI0
PP4/CKI0
PP3/IC3
PP2/IC2
PP1/IC1
PP0/IC0
C
VSS
(FPT-64P-M23/FPT-64P-M24)
8
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
CHAPTER 1 OVERVIEW
1.4 Package Dimension
MB91490 Series
1.4
Package Dimension
This section shows the package dimension used in MB91490 series.
■ Package Dimension (FPT-64P-M23)
Figure 1.4-1 Package Dimension of FPT-64P-M23
64-pin plastic LQFP
Lead pitch
0.65 mm
Package width ×
package length
12.0 × 12.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.47 g
Code
(Reference)
P-LQFP64-12×12-0.65
(FPT-64P-M23)
64-pin plastic LQFP
(FPT-64P-M23)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
14.00±0.20(.551±.008)SQ
*12.00±0.10(.472±.004)SQ
48
0.145±0.055
(.006±.002)
33
49
32
0.10(.004)
Details of "A" part
+0.20
1.50 –0.10
+.008
(Mounting height)
.059 –.004
0.25(.010)
INDEX
0~8°
64
17
1
0.65(.026)
C
0.32±0.05
(.013±.002)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
"A"
16
0.13(.005)
0.10±0.10
(.004±.004)
(Stand off)
M
2003-2010 FUJITSU SEMICONDUCTOR LIMITED F64034S-c-1-4
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
CM71-10155-2E
FUJITSU SEMICONDUCTOR LIMITED
9
CHAPTER 1 OVERVIEW
1.4 Package Dimension
MB91490 Series
■ Package Dimension (FPT-64P-M24)
Figure 1.4-2 Package Dimension of FPT-64P-M24
64-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
10.0 mm × 10.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Code
(Reference)
P-LFQFP64-10×10-0.50
(FPT-64P-M24)
64-pin plastic LQFP
(FPT-64P-M24)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
12.00±0.20(.472±.008)SQ
Details of "A" part
*10.00±0.10(.394±.004)SQ
48
0.145±0.055
(.006±.002)
33
49
0.15(.006)
MAX
0.40(.016)
MAX
32
0.08(.003)
Details of "B" part
11.00(.433)
NOM.
+0.20
1.50 –0.10
+.008
(Mounting height)
.059 –.004
0.25(.010)
INDEX
"A"
64
LEAD No.
1
0.20±0.05
(.008±.002)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
"B"
16
0.50(.020)
C
0~8°
17
0.08(.003)
M
2006-2010 FUJITSU SEMICONDUCTOR LIMITED F64036S-1c(D)-1-3
0.10±0.10
(.004±.004)
(Stand off)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
10
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
CHAPTER 1 OVERVIEW
1.5 List of Pin Functions
MB91490 Series
1.5 List of Pin Functions
Table 1.5-1 lists the pin functions.
■ List of Pin Functions
Table 1.5-1 List of Pin Functions (1 / 4)
Pin No.
Pin Name
I/O
Circuit
Type *
Function
54
MD2
K
Mode terminal 2.
Setting terminal determines the basic operation mode.
During normal communication, input must be at the "L" level.
During serial programming to flash memory, input must be at the "H" level.
53
MD1
K
Mode terminal 1.
Setting terminal determines the basic operation mode.
Input must always be at the "L" level.
52
MD0
K
Mode terminal 0.
Setting terminal determines the basic operation mode.
Input must always be at the "L" level.
51
X0
A
Clock (oscillator) input
50
X1
A
Clock (oscillator) output
32
INITX
I
External reset input
64
NMIX
H
NMI (Non Maskable Interrupt) input
57
58
59
60
INT0
P80
INT1
P81
INT2
P82
INT3
P83
D
D
D
D
PPG4
D
D
D
ADTG1
CM71-10155-2E
PA1
External interrupt 3 input
General purpose input/output port
PPG timer 4 output
PPG timer 5 output
PPG timer 6 output
General purpose input/output port
P86
55
General purpose input/output port
External interrupt 6 input
INT6
PPG6
External interrupt 2 input
General purpose input/output port
P85
63
General purpose input/output port
External interrupt 5 input
INT5
PPG5
External interrupt 1 input
General purpose input/output port
P84
62
General purpose input/output port
External interrupt 4 input
INT4
61
External interrupt 0 input
D
8/10-bit A/D converter 1 external trigger input
General purpose input/output port
FUJITSU SEMICONDUCTOR LIMITED
11
CHAPTER 1 OVERVIEW
1.5 List of Pin Functions
MB91490 Series
Table 1.5-1 List of Pin Functions (2 / 4)
Pin No.
56
33
34
35
36
40
41
42
43
44
45
46
47
1
Pin Name
ADTG2
PA2
AN1-0
PB4
AN1-1
PB5
AN1-2
PB6
AN1-3
PB7
AN2-0
PC0
AN2-1
PC1
AN2-2
PC2
AN2-3
PC3
AN2-4
PC4
AN2-5
PC5
AN2-6
PC6
AN2-7
PC7
SCK0
(SCL0)
I/O
Circuit
Type *
D
G
G
G
G
G
G
G
G
G
G
G
G
D
3
SIN0
PG1
SOT0
(SDA0)
D
D
SCK1
(SCL1)
PG3
12
General purpose input/output port
8/10-bit A/D converter 1 analog 0 input
General purpose input/output port
8/10-bit A/D converter 1 analog 1 input
General purpose input/output port
8/10-bit A/D converter 1 analog 2 input
General purpose input/output port
8/10-bit A/D converter 1 analog 3 input
General purpose input/output port
8/10-bit A/D converter 2 analog 0 input
General purpose input/output port
8/10-bit A/D converter 2 analog 1 input
General purpose input/output port
8/10-bit A/D converter 2 analog 2 input
General purpose input/output port
8/10-bit A/D converter 2 analog 3 input
General purpose input/output port
8/10-bit A/D converter 2 analog 4 input
General purpose input/output port
8/10-bit A/D converter 2 analog 5 input
General purpose input/output port
8/10-bit A/D converter 2 analog 6 input
General purpose input/output port
8/10-bit A/D converter 2 analog 7 input
General purpose input/output port
Multi-function serial interface 0 clock input/output
(SCL0 at I2C mode)
Multi-function serial interface 0 data input (Not used at I2C mode)
General purpose input/output port
Multi-function serial interface 0 data output (SDA0 at I2C mode)
General purpose input/output port
PG2
4
8/10-bit A/D converter 2 external trigger input
General purpose input/output port
PG0
2
Function
D
Multi-function serial interface 1 clock input/output
(SCL1 at I2C mode)
General purpose input/output port
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
CHAPTER 1 OVERVIEW
1.5 List of Pin Functions
MB91490 Series
Table 1.5-1 List of Pin Functions (3 / 4)
Pin No.
5
6
Pin Name
SIN1
PG4
SOT1
(SDA1)
I/O
Circuit
Type *
D
D
SCK2
(SCL2)
D
9
SIN2
PH1
SOT2
(SDA2)
D
D
29
30
31
25
26
27
TIN0
PJ0
TOUT0
PJ1
TIN1
PJ2
TOUT1
PJ3
AIN0
PL0
BIN0
PL1
ZIN0
PL2
IC0
19
PP0
IC1
20
PP1
IC2
21
PP2
IC3
22
23
PP3
CKI0
CM71-10155-2E
PP4
Multi-function serial interface 1 data output (SDA1 at I2C mode)
Multi-function serial interface 2 clock input/output
(SCL2 at I2C mode)
Multi-function serial interface 2 data input (Not used at I2C mode)
General purpose input/output port
Multi-function serial interface 2 data output (SDA2 at I2C mode)
General purpose input/output port
PH2
28
General purpose input/output port
General purpose input/output port
PH0
8
Multi-function serial interface 1 data input (Not used at I2C mode)
General purpose input/output port
PG5
7
Function
D
D
D
D
D
D
D
D
D
D
D
D
Base timer 0 input
General purpose input/output port
Base timer 0 output
General purpose input/output port
Base timer 1 input
General purpose input/output port
Base timer 1 output
General purpose input/output port
8/16-bit up count input terminal for up/down counter 0
General purpose input/output port
8/16-bit down count input terminal for up/down counter 0
General purpose input/output port
8/16-bit reset input terminal for up/down counter 0
General purpose input/output port
Trigger input of input capture 0
General purpose input/output port
Trigger input of input capture 1
General purpose input/output port
Trigger input of input capture 2
General purpose input/output port
Trigger input of input capture 3
General purpose input/output port
External clock input terminal of free-run timer ch.0 to ch.2
General purpose input/output port
FUJITSU SEMICONDUCTOR LIMITED
13
CHAPTER 1 OVERVIEW
1.5 List of Pin Functions
MB91490 Series
Table 1.5-1 List of Pin Functions (4 / 4)
Pin No.
24
Pin Name
DTTI0
I/O
Circuit
Type *
D
11
12
13
14
15
RTO0
PQ0
RTO1
PQ1
RTO2
PQ2
RTO3
PQ3
RTO4
PQ4
RTO5
PQ5
Input signal controlled multi-function timer 0 waveform generator output RTO0 to
RTO5
General purpose input/output port
PP5
10
Function
J
J
J
J
J
J
Waveform generator output of multi-function timer 0
General purpose input/output port
Waveform generator output of multi-function timer 0
General purpose input/output port
Waveform generator output of multi-function timer 0
General purpose input/output port
Waveform generator output of multi-function timer 0
General purpose input/output port
Waveform generator output of multi-function timer 0
General purpose input/output port
Waveform generator output of multi-function timer 0
General purpose input/output port
*: For the I/O circuit type, refer to "1.6 I/O Circuit Type".
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FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
CHAPTER 1 OVERVIEW
1.5 List of Pin Functions
MB91490 Series
[Power supply and GND pins]
Pin No.
Pin Name
16
48
VCC
Power-supply pins. Use all of these pins at equal potential.
17
49
VSS
GND pins. Use all of these pins at equal potential.
18
C
37
AVCC10
Analog power-supply pin for 8/10-bit A/D converter 1/2
39
AVSS10
Analog GND pin for 8/10-bit A/D converter 1/2
38
AVRH2
Analog reference power-supply pin for 8/10-bit A/D converter 1/2
CM71-10155-2E
Function
Capacitor coupling pin for internal regulator
FUJITSU SEMICONDUCTOR LIMITED
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CHAPTER 1 OVERVIEW
1.6 I/O Circuit Type
1.6
MB91490 Series
I/O Circuit Type
Table 1.6-1 shows the I/O circuit type.
■ I/O Circuit Type
Table 1.6-1 I/O Circuit Type (1 / 3)
Type
Circuit
Remarks
X1
A
Clock input
Approx. 1M oscillation feedback resistor for highspeed (source oscillation for main clock)
X0
Standby control
R
P-ch
Pull-up control
• CMOS-level output
• CMOS level hysteresis input
Digital output
• Standby control provided
• With pull-up control
P-ch
D
Digital output
R
N-ch
Digital input
Standby control
Pull-up control
R
Digital output
P-ch
P-ch
G
• Analog/CMOS level hysteresis I/O pin
• CMOS-level output
• CMOS level hysteresis input
(with standby control)
• Analog input (Operates as an analog input when the
corresponding AICR register bit is "1".)
• With pull-up control
Digital output
R
N-ch
Digital input
Standby control
Analog input
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FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
CHAPTER 1 OVERVIEW
1.6 I/O Circuit Type
MB91490 Series
Table 1.6-1 I/O Circuit Type (2 / 3)
Type
Circuit
Remarks
• CMOS level hysteresis input
• No standby control
P-ch
H
R
N-ch
Digital input
• CMOS level hysteresis input
R
• With pull-up resistance
• No standby control
P-ch
P-ch
I
R
N-ch
Digital input
Pull-up control
R
• CMOS-level output
• CMOS level hysteresis input
• Standby control provided
Digital output
P-ch
• With pull-up control
P-ch
J
Digital output
R
N-ch
Digital input
Standby control
CM71-10155-2E
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CHAPTER 1 OVERVIEW
1.6 I/O Circuit Type
MB91490 Series
Table 1.6-1 I/O Circuit Type (3 / 3)
Type
Circuit
Remarks
Flash memory models only
• CMOS-level input
N-ch
• With high voltage control for Flash test
N-ch
K
N-ch
Control signal
N-ch
Mode input
N-ch
18
R
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
CHAPTER 2
HANDLING DEVICES
This chapter provides precautions on handling the
device.
2.1 Precautions on Handling the Device
CM71-10155-2E
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19
CHAPTER 2 HANDLING DEVICES
2.1 Precautions on Handling the Device
2.1
MB91490 Series
Precautions on Handling the Device
This section explains precautions on handling the device.
■ Precautions on Handling Device
● Preventing latch-up
Latch up phenomenon may occur with CMOS IC, when a voltage higher than VCC or lower than VSS is
applied to either the input or output terminals, or when a voltage is applied between VCC and VSS that
exceeds the rated voltage. When latch up occurs, a significant power-supply current surge results, which
may damage some elements due to the excess heat, so great care must be taken to ensure that the maximum
rating is never exceeded during use.
● Treatment of Unused Input Pins
Do not leave an unused input pin open, since it may cause a malfunction. Handle by, for example, using a
pull-up or pull-down resistor.
● Power pins
In products with multiple VCC and VSS pins, the pins of the same potential are internally connected in the
device to avoid abnormal operations including latch-up. However, you must connect the pins to the same
potential power supply and a ground line externally to lower the electro-magnetic emission level, to prevent
abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total
output current rating.
Moreover, connect the current supply source with the VCC and VSS pins of this device at the low
impedance.
It is also advisable to connect a ceramic capacitor of approximately 0.1 F as a bypass capacitor between
VCC and VSS near this device.
● Crystal oscillator circuit
Noise near the X0 and X1 pins may cause the device to malfunction. Design the printed circuit board so
that X0, X1, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as
close to the device as possible.
It is strongly recommended to design the PC board artwork with the X0 and X1pins surrounded by ground
plane because stable operation can be expected with such a layout. Please ask the crystal maker to evaluate
the oscillational characteristics of the crystal and this device.
● About mode pins (MD0 to MD2)
Connect mode pins (MD0 to MD2) direct to VCC or VSS pins.
If pull-up or pull-down is necessary to change the mode pin level in rewriting the built-in FLASH or other
processes, to prevent a device from accidentally entering the test mode due to noise, suppress the value of
the resistor to use for pull-up or pull-down as low as possible, design the printed circuit board so that the
layouts of the mode pins and VCC or VSS pins can be as near as possible to minimize the connection
impedance.
20
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
CHAPTER 2 HANDLING DEVICES
2.1 Precautions on Handling the Device
MB91490 Series
● Operation at start-up
Be sure to execute setting initialized reset (INIT) with INITX pin immediately after start-up.
Immediately after that, also, hold the "L"-level input to the INITX pin for the stabilization wait time
required for the oscillator circuit to take the oscillation stabilization wait time for the oscillator circuit and
the stabilization wait time for the regulator (For INIT via the INITX pin, the oscillation stabilization wait
time setting is initialized to the minimum value).
● Order of power turning ON/OFF
Use the following procedure for turning the power on or off. If not using the A/D converter, connect AVCC =
VCC and AVSS = VSS. Turn on the power supply in the sequence VCC  AVCC  AVRH2, and turn
off the power in the reverse sequence.
● Source oscillation input when turning on the power
When turning the power on, maintain clock input until the device is released from the oscillation
stabilization wait state.
● Caution for operation during PLL clock mode
Even if the oscillator comes off or the clock input stops with the PLL clock selected for MB91490 series,
MB91490 series may continue to operate at the free-run frequency of the PLL’s internal self-oscillating
oscillator circuit.
Performance of this operation, however, cannot be guaranteed.
● Using an external clock
When using an external clock, you must always input clock signals with opposite phase from X0 pin to X1
pin simultaneously. However, as the X1 pin halts with an output at the "H" level during STOP mode, insert
a resistor of approximately 1k externally to prevent a conflict between the two outputs if using STOP
mode (oscillation stop mode).
The figure below shows an example of how to use an external clock.
Figure 2.1-1 Example of Using External Clock
X0
MB91490 series
X1
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CHAPTER 2 HANDLING DEVICES
2.1 Precautions on Handling the Device
MB91490 Series
● C pin
As MB91490 series includes an internal regulator, always connect a bypass capacitor of approximately
4.7F to the C pin for use by the regulator.
Figure 2.1-2 Example of C Pin Connection
C
MB91490 series
VSS
GND
● Software reset on the synchronous mode
Be sure to meet the following two conditions before setting 0 to the SRST bit of STCR (standby control
register) when the software reset is used on the synchronous mode.
• Set the interrupt enable flag (I-Flag) to interrupt disable (I-Flag=0).
• Not used NMI
● Precautions at power-on
To prevent the device from malfunctioning due to overshoot of the embedded voltage reduction circuit, the
voltage rising time at power-on is required to be 600s (between 0.0V and 5.0V) or more. In addition, as it
takes 600s since the power voltage stabilization (after rising) until the internal voltage becomes stabilized,
during which time INITX is required to be input continuously.
When the voltage rising time is less than 600s (between 0.0V and 5.0V), as it takes 2ms* since the power
voltage stabilization (after rising) until the internal voltage becomes stabilized, during which time INITX is
required to be input continuously.
*: The internal power stabilization wait time when the voltage rising time is less than 600s (between
0.0V and 5.0V) is in portion to the capacitance value of the bypass capacitor attached to pin C of this
device. This 2ms is the value when pin C=4.7F, and when pin C=9.4F, the internal power
stabilization wait time is 4ms.
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CM71-10155-2E
CHAPTER 2 HANDLING DEVICES
2.1 Precautions on Handling the Device
MB91490 Series
Figure 2.1-3 Power Supply Rising Standard
• When the voltage rising time is 600μs (between 0.0 and 5.0V) or more:
VCC [V]
5.0
0
t
600μs
Allow 600μs or more
INITX
Power on
Internal power
voltage
stabilization wait
Operation start
• When the voltage rising time is 600μs (between 0.0 and 5.0V) or less:
VCC [V]
5.0
0
t
600μs
Secure 2ms or more
INITX
Power on
CM71-10155-2E
Internal power voltage
stabilization wait
Operation start
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CHAPTER 2 HANDLING DEVICES
2.1 Precautions on Handling the Device
24
FUJITSU SEMICONDUCTOR LIMITED
MB91490 Series
CM71-10155-2E
CHAPTER 3
CPU AND CONTROL UNIT
This chapter provides basic information required to
understand the CPU core functions of the MB91490
series. It covers architecture, specifications, and
instructions.
3.1 Memory Space
3.2 Memory Map
3.3 Internal Architecture
3.4 Programming Model
3.5 Data Structure
3.6 Memory Map
3.7 Divergence Instructions
3.8 EIT (Exception, Interruption, and Trap)
3.9 Operating Mode
3.10 Reset (Device Initialization)
3.11 Clock Generation Control
3.12 Device State Control
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CHAPTER 3 CPU AND CONTROL UNIT
3.1 Memory Space
3.1
MB91490 Series
Memory Space
The logical address space of the MB91490 series is 4GB (232 addresses) and the CPU
performs linear access.
■ Direct Addressing Area
The undermentioned area of the address space is used for I/O.
This area is called the direct addressing area and the operand address can be specified directly in the
instruction.
A direct area is different depending on the size of the accessed data as follows.
• Byte data access:
000H to 0FFH
• Half word data access: 000H to 1FFH
• Word data access:
000H to 3FFH
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CM71-10155-2E
CHAPTER 3 CPU AND CONTROL UNIT
3.2 Memory Map
MB91490 Series
3.2
Memory Map
This section shows the memory map of the MB91490 series.
■ Memory Map
Single-chip mode
0000 0000H
I/O
0000 0400H
Direct
addressing Refer to "APPENDIX A I/O Map".
area
I/O
0001 0000H
Access inhibit
0003 F000 H
0004 0000H
F-bus RAM 4Kbytes
D-bus RAM 8Kbytes
0004 2000H
Access inhibit
000C 0000H
256Kbytes Flash
0010 0000H
Access inhibit
FFFF FFFFH
The setting of the mode is determined by the mode vector fetch after negating INITX.
(For mode setting, refer to "3.9 Operating Mode ■ Operating Mode".)
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CHAPTER 3 CPU AND CONTROL UNIT
3.3 Internal Architecture
3.3
MB91490 Series
Internal Architecture
As well as adopting RISC architecture, the MB91490 series CPU is a high performance
core featuring high function commands for embedded applications.
■ Features of Internal Architecture
● Adoption of RISC architecture
Basic instruction: one instruction one cycle
● 32-bit architecture
General-purpose registers: 32 bits  16 registers
● Linear memory space of 4GB
● Installing of multipliers
• 32-bit by 32-bit multiplication: 5 cycles
• 16-bit by 16-bit multiplication: 3 cycles
● Reinforcement of interruption processing function
• High-speed response speed (6 cycles)
• Support of multiple interruption
• Level mask function (16 levels)
● Reinforcement of instruction for I/O operation
• Memory-to-memory transfer instruction
• Bit manipulation instruction
● High code efficiency
Basic instruction word length: 16 bits
● Low-power consumption
Sleep mode, stop mode
● Clock division ratio setting function
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CM71-10155-2E
CHAPTER 3 CPU AND CONTROL UNIT
3.3 Internal Architecture
MB91490 Series
■ Internal Architecture
The CPU of the FR family uses the Harvard architecture with separate instruction bus and data bus.
A 32-bit  16-bit bus converter is connected to the 32-bit bus (F-bus) to provide an interface between the
CPU and peripheral resources. A Harvard  Princeton bus converter is connected to the I-bus and D-bus to
provide an interface between the CPU and the bus controller.
Figure 3.3-1 Internal Architecture
FR CPU
I-bus
Built-in
RAM
(Instruction/
Data)
Built-in
Flash
D-bus
32
32
32
32
Built-in
RAM
(Data)
Harvard
Princeton
Bus converter
F-bus
32
32
32-bit
32
16-bit
Bus controller
Bus converter
16
X-bus 32
R-bus
Peripheral resource/Port
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CHAPTER 3 CPU AND CONTROL UNIT
3.3 Internal Architecture
MB91490 Series
■ CPU
CPU is compactly implementation for the FR family architecture for 32-bit RISC.
A five-stage instruction pipeline is used to enable execution of one instruction per cycle.
The pipeline is composed of the following stages.
•
•
•
•
•
Instruction fetch (IF):
Instruction decipherment (ID):
Execution (EX):
Memory access (MA):
Write-back (WB):
The instruction address is output, and the instruction is fetched.
The decipherment does the fetched instruction. The register is read.
The operation is executed.
Loading into or storing the memory is accessed.
Writes the result of operation (or loaded memory data) to a register.
Figure 3.3-2 Instruction Pipeline
CLK
Instruction 1
Instruction 2
Instruction 3
Instruction 4
Instruction 5
Instruction 6
WB
MA
WB
EX
MA
WB
ID
EX
MA
WB
IF
ID
EX
MA
WB
IF
ID
EX
MA
WB
The instruction is always executed in correct order. Accordingly, if instruction A enters the pipeline before
instruction B, instruction A always reaches write-back stage before instruction B.
As a rule, the instruction is executed at the speed of one instruction per cycle. A number of cycles are
required to execute commands for the load store commands accompanying memory wait, branch
commands that do not have delay slots and multiple cycle commands. Also, instruction execution speed
drops if supply of instructions is delayed.
■ 32-bit 16-bit Bus Converter
Acts as an interface between the F-bus which uses high-speed 32-bit access and the R-bus which uses 16bit access to enable the CPU to access data to the internal peripheral circuits.
The bus converter converts 32-bit access from the CPU into two 16-bit accesses and performs R-bus
access. Restrictions on the access width apply for some internal peripheral circuits.
■ Harvard  Princeton Bus Converter
Arbitrates instruction access and data access from the CPU to provide a smooth interface to the external
buses.´
In CPU, the instruction bus and the data bus are the independent Harvard architecture structures. On the
other hand, the bus controller that controls the external bus has a single-bus Princeton architecture
structure. This bus converter ranks the priority order for command access and data access of the CPU and
controls access to the bus controller. This mechanism causes the prioritizing of external bus access to be
optimized.
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CM71-10155-2E
CHAPTER 3 CPU AND CONTROL UNIT
3.3 Internal Architecture
MB91490 Series
■ Overview of Instructions
FR family supports logic operation, bit operation, and direct addressing commands that are optimized for
embedded applications, as well as the command system of the normal RISC. The list of the instruction set
is shown in "APPENDIX E INSTRUCTION LISTS". Excellent memory efficiency is achieved because
each instruction is 16-bit long (some instructions are 32 or 48 bits in length).
The instruction set can be divided into the following function groups.
• Arithmetic operation
• Loading and store
• Divergence
• Logical operation and bit operation
• Direct addressing
• The others
● Arithmetic operation
It has standard arithmetic operation commands (addition, subtraction, and comparison) and shift commands
(logic shift and arithmetic operation shift). Operations with carry that are used for multi-word length
operations and operations that do not change the flag which are convenient for address calculations are
enabled for addition and subtraction.
32-bit  32-bit and 16-bit  16-bit multiplication instructions and a 32-bit/32-bit step division instruction
are also provided.
Immediate value transfer instructions for setting immediate values to registers and register-to-register
transfer instructions are also provided.
All arithmetic operation instructions use the multiplication and division register and the general-purpose
registers in the CPU to perform the operation.
● Loading and store
Load and store instructions read or write to the peripheral resources (I/O) on the chip.
Loading and store have three kinds of access lengths of the byte, the half-word, and the word. In addition to
general register indirect memory addressing, the register indirect memory addressing with displacement
and register indirect memory addressing with register increment/decrement are possible for certain
commands.
● Divergence
It is an instruction of the divergence, the call, the interruption, and the return. There are two types of branch
commands; one type features a delay slot while the other does not. They can be optimized in accordance
with the purpose. See Section "3.7 Divergence Instructions" for details of the divergence instruction.
● Logical operation and bit operation
Logical operation commands can perform AND, OR, and EOR logical operations between general-purpose
registers or between a general-purpose register and the memory (and I/O). Moreover, the bit operation
instruction can operate the content of the memory (and I/O) directly. The register of the memory addressing
is generally indirect.
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CHAPTER 3 CPU AND CONTROL UNIT
3.3 Internal Architecture
MB91490 Series
● Direct addressing
Direct addressing commands are used to access between I/O and general-purpose registers or between I/O
and the memory. The I/O address can be accessed quickly and efficiently by direct specification within the
command instead of indirectly to the register. Indirect memory addressing to the register with register
increment/decrement is also enabled for some commands.
● The others
Other instructions include instructions for setting the flags in the PS register, performing stack operations,
and performing sign and zero-extended operations. Function entry and exit instructions for use with highlevel languages and register multi-load/store instructions are also provided.
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CHAPTER 3 CPU AND CONTROL UNIT
3.4 Programming Model
MB91490 Series
3.4
Programming Model
This section explains the basic programming model and each register.
■ Basic Programming Model
Figure 3.4-1 Basic Programming Model
32-bit
[Initial value]
R0
XXXX XXXXH
R1
General-purpose
register
R12
R13
AC
R14
FP
XXXX XXXXH
R15
SP
0000 0000H
Program counter
PC
Program status
PS
Table base register
TBR
Return pointer
RP
System stack pointer
SSP
User stack pointer
USP
Multiplication and
division result register
MDH
MDL
CM71-10155-2E
ILM
SCR
FUJITSU SEMICONDUCTOR LIMITED
CCR
33
CHAPTER 3 CPU AND CONTROL UNIT
3.4 Programming Model
3.4.1
MB91490 Series
Registers
This section explains each register.
■ General-purpose Register
Figure 3.4-2 General-purpose Register
32-bit
[Initial value]
R0
R1
XXXX XXXXH
R12
R13
R14
R15
AC
FP
SP
XXXX XXXXH
0000 0000H
Registers R0 to R15 are a general-purpose register. They are used as accumulator for various types of
operation and as pointer for memory access.
The following of the 16 registers are expected to have special uses, so some commands are emphasized.
R13: Virtual accumulator
R14: Frame pointer
R15: Stack pointer
R0 to R14 of the initial value by reset are undefined. R15 is 00000000H (SSP value).
■ Program Status (PS)
This register retains the program status and is separated into three parts, namely, ILM, SCR, and CCR.
All bits undefined in figure are reserved bit. Reading always returns "0".
Writing has no effect.
bit 31
bit 20
ILM
34
bit 16
bit 10 bit 8 bit 7
SCR
FUJITSU SEMICONDUCTOR LIMITED
bit 0
CCR
CM71-10155-2E
CHAPTER 3 CPU AND CONTROL UNIT
3.4 Programming Model
MB91490 Series
■ Condition Code Register (CCR)
bit7
-
bit6
-
bit5
S
bit4
I
bit3
N
bit2
Z
bit1
V
bit0
C
Initial value
--00XXXXB
[bit5] S: Stack flag
The stack pointer used as R15 is specified.
Value
Description
0
SSP is used as R15.
Automatically goes to "0" when an EIT occurs.
(However, the value saved on the stack is the value before the bit is cleared.)
1
USP is used as R15.
Cleared to "0" by a reset.
Set to "0" when executing the RETI instruction.
[bit4] I: Interrupt enable flag
Permission and interdiction of the user interruption demand are controlled.
Value
Description
0
User interruption interdiction.
Cleared to "0" when the INT instruction is executed.
(However, the value saved on the stack is the value before the bit is cleared.)
1
User interruption permission.
Masking of user interrupt requests is controlled by the value stored in the ILM.
Cleared to "0" by a reset.
[bit3] N: Negative flag
Indicates the sign when an operation result is represented as a two’s-complement integer.
Value
Description
0
It is indicated that operation result was a positive value.
1
It is indicated that operation result was a negative value.
Initial state by reset is irregular.
[bit2] Z: Zero flag
It is shown operation result was 0.
Value
Description
0
It is indicated that operation result was the values other than 0.
1
It is indicated that operation result was 0.
Initial state by reset is undefined.
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CHAPTER 3 CPU AND CONTROL UNIT
3.4 Programming Model
MB91490 Series
[bit1] V: Overflow flag
Operands used for calculations are defined as integers expressed in complements of 2, and whether or not
an overflow occurs as a result of the calculation is indicated.
Value
Description
0
It is indicated not to have caused the overflow as a result of the operation.
1
It is indicated to have caused the overflow as a result of the operation.
Initial state by reset is undefined.
[bit0] C: Carrying flag
Indicates whether an operation resulted in a borrow or a carry from the most significant bit.
Value
Description
0
It is indicated that neither a carry nor a borrow occurred.
1
It is indicated that a carry or a borrow occurred.
Initial state by reset is undefined.
■ System Condition Code Register (SCR)
bit10
D1
bit9
D0
bit8
T
Initial value
XX0B
[bit10, bit9] D1, D0: Flag for step division
The middle data of step division execution time is maintained.
Do not change while executing the division processing.
During step division when other processing is performed, re-start of the step division is guaranteed by
saving and returning to the PS register value.
Initial state by reset is irregular.
Set based on the value of the dividend and divisor during the execution of the DIV0S instruction.
Forcibly cleared by execution of the DIV0U instruction.
[bit8] T: Step trace trap flag
It is a flag which specifies whether to make the step trace trap effective.
Value
Description
0
Step trace trap invalidity.
1
Step trace trap effective.
In this case, all user NMIs and user interrupts are disabled.
Initialized to "0" by a reset.
The emulator uses the function of the step trace trap. When the emulator is used, the use cannot be done
in user program.
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CM71-10155-2E
CHAPTER 3 CPU AND CONTROL UNIT
3.4 Programming Model
MB91490 Series
■ ILM
bit20
ILM4
bit19
ILM3
bit18
ILM2
bit17
ILM1
bit16
ILM0
Initial value
01111B
This register stores the interrupt level mask value and the value set in the ILM is used as the level mask.
The interrupt request to be input to the CPU is accepted only when its interrupt level is stronger than the
level indicated by this ILM.
As for the level value, 0 ("00000B") is the strongest, and 31 ("11111B") is weakest.
There is a limitation in the value which can be set from the program.
When former value is 16 to 31
New values can only be set in the range 16 to 31. Executing an instruction that sets a value between 0 and
15 results in (specified value + 16) being transferred.
When former value is 0 to 15
Any value of 0 to 31 can be set.
Initialized to 15 ("01111B") by reset.
[Notes of PS register]
As some instructions pre-process the PS register, the following exception operations may cause a break to
occur in an interrupt processing routine when using the debugger or the updating of the PS flag.
In either case, the system is designed to re-execute correctly after the EIT returns and therefore processing
before and after the EIT is executed correctly.
1. The following operations may occur when (a) user interrupt/NMI is received, (b) step execution is
performed, (c) break occurs in a data event or emulator menu in an instruction immediately preceding
DIV0U/DIV0S instruction.
(1) D0 and D1 flags precede and are renewed.
(2) EIT processing routine (user interruption, NMI, or emulator) is executed.
(3) After returning from EIT, DIV0U/DIV0S instructions are executed and the D0 and D1 flags are
updated to the same value as (1).
2. When each ORCCR/STILM/MOV Ri, PS instructions are executed to permit interrupting with the user
interruption and the NMI factor generated, the following operations are done.
(1) The PS register precedes and is updated.
(2) Execute an EIT processing routine (user interrupt or NMI).
(3) After returning from EIT, the above instructions are executed and the PS register is updated to the
same value as (1).
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CHAPTER 3 CPU AND CONTROL UNIT
3.4 Programming Model
MB91490 Series
■ Program Counter (PC)
bit 31
bit0
PC
Initial value
XXXXXXXXH
The address of the executed instruction is shown with the program counter.
Bit0 is set to "0" when the PC is updated during instruction execution. Bit0 can only go to "1" in the case
when an odd-numbered address is specified as a branch destination address.
However, bit0 is ignored in this case also and instructions must be located at addresses that are a multiple
of two.
The initial value by reset is irregular.
■ Table Base Register (TBR)
bit 31
bit0
TBR
Initial value
000FFC00H
The table base register stores the start address of the vector table used in EIT processing.
The initial value by reset is "000FFC00H".
■ Return Pointer (RP)
bit 31
bit0
RP
Initial value
XXXXXXXXH
The address which returns from the sub routine is maintained with the return pointer.
The value of PC is forwarded to this RP at CALL instruction execution time.
The content of RP is forwarded to PC at RET instruction execution time.
The initial value by reset is irregular.
■ System Stack Pointer (SSP)
bit 31
bit0
SSP
Initial value
00000000H
The SSP is the system stack pointer.
Functions as R15 when the S flag is "0".
The SSP can also be specified explicitly.
Also used as the stack pointer specifying the stack that saves the PS and PC when EIT occurs.
The initial value by reset is "00000000H".
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CHAPTER 3 CPU AND CONTROL UNIT
3.4 Programming Model
MB91490 Series
■ User Stack Pointer (USP)
bit 31
bit0
USP
Initial value
XXXXXXXXH
The USP is the user stack pointer.
Functions as R15 when the S flag is "1".
The USP can also be specified explicitly.
The initial value by reset is irregular.
The use cannot be done in the RETI instruction.
■ Multiplication and Division Register (Multiply & Divide Register) (MDH/MDL)
bit 31
bit0
MDH
MDL
This register is the register for multiplication and division, and 32-bit lengths respectively.
The initial value by reset is irregular.
Multiplication execution time
When performing 32-bit × 32-bit multiplication, 64-bit length calculation results are stored in the
multiplication/division results storage register in the following format.
MDH: Higher 32 bits
MDL: Lower 32 bits
When 16 bits  16 bits are multiplied, the result is stored as follows.
MDH: Undefined
MDL: Result of 32 bits
Division execution time
When beginning to calculate, the dividend is stored in MDL.
When division is performed using the DIV0S/DIV0U, DIV1, DIV2, DIV3, and DIV4S commands, the
results are stored in MDL and MDH.
MDH: Surplus
MDL: Quotient
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CHAPTER 3 CPU AND CONTROL UNIT
3.5 Data Structure
3.5
MB91490 Series
Data Structure
This section explains the bit ordering, byte ordering, and word alignment.
■ Bit Ordering
In the FR family, the little endian has been adopted as a bit ordering.
Figure 3.5-1 Bit Ordering
bit
31
29
30
27
28
25
26
23
24
21
22
19
20
17
18
15
16
13
14
11
12
9
10
MSB
7
8
5
6
3
4
1
2
0
LSB
■ Byte Ordering
In the FR family, the big endian has been adopted as byte ordering.
Figure 3.5-2 Byte Ordering
Memory
bit
7
40
MSB
LSB
bit31
bit23
bit15
bit7
bit0
10101010 11001100 11111111 00010001
bit
0
Address n
10101010
Address (n+1)
11001100
Address (n+2)
11111111
Address (n+3)
00010001
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CM71-10155-2E
CHAPTER 3 CPU AND CONTROL UNIT
3.5 Data Structure
MB91490 Series
■ Word Alignment
● Program access
It is necessary to arrange the program of the FR family in the address of the multiple of two.
Bit0 of PC is set to "0" when the PC is updated during instruction execution. The bit can only go to "1" in
the case when an odd-numbered address is specified as a branch destination address.
However, bit0 is ignored in this case also and instructions must be located at addresses that are a multiple
of two.
There is no odd-number address exception.
● Data access
In the FR family, when data access is performed, forced alignment is provided to addresses as follows in
accordance with their width.
Word access
: The address is a multiple of four (The lowest 2 bits are forcibly set to "00B").
Half-word access
: The address is a multiple of two (The lowest bit is forcibly set to "0").
Byte access
: ----
When word or half-word data is accessed, 0 is forcibly set to some bits, which are the calculation results of
the effective address. For example, in the @(R13, Ri) addressing mode, the pre-addition register is used for
calculations as it is (even though the lowest bit is 1), and the lower bits of the addition results will be
masked. The register prior to the calculation is not masked.
[Example] LD@ (R13, R2), R0
R13
0 0 0 0 2 2 2 2
H
R2
0 0 0 0 0 0 0 3
H
Addition result 0 0 0 0 2 2 2 5 H
Compulsion mask of lower two bits
Address pin 0 0 0 0 2 2 2 4 H
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CHAPTER 3 CPU AND CONTROL UNIT
3.6 Memory Map
3.6
MB91490 Series
Memory Map
This section describes a memory map of the MB91490 series.
■ Memory Map
The address space is 32-bit linear.
Figure 3.6-1 Memory Map
0000 0000H
Byte data
0000 0100H
Half-word
data
0000 0200H
Direct addressing area
Word data
0000 0400H
000F FC00H
Vector table
000F FFFFH
FFFF FFFFH
■ Direct Addressing Area
The undermentioned area of the address space is an area for I/O. This area can directly specify the operand
address in the instruction using the direct addressing.
The size of the address area of direct possible addressing is different in each data length.
• Byte data
(8-bit)
: 000H to 0FFH
• Half-word data (16-bit) : 000H to 1FFH
• Word data
(32-bit) : 000H to 3FFH
■ Vector Table Initial Area
The area of 000FFC00H to 000FFFFFH is EIT vector table initial area.
The vector table used for EIT processing can be allocated to an arbitrary address by rewriting the TBR, but
it is allocated to this address on initialization through reset.
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CHAPTER 3 CPU AND CONTROL UNIT
3.7 Divergence Instructions
MB91490 Series
3.7
Divergence Instructions
In the FR family, whether the operations are with or without delay slots can be specified
for the branch command.
■ Operation with Delay Slot
● Instruction
The instructions with the notation shown below perform a branch operation with a delay slot.
JMP:D
@Ri
CALL:D label12
CALL:D @Ri
RET:D
BRA:D
label9
BNO:D
label9
BEQ:D
label9
BNE:D
label9
BC:D
label9
BNC:D
label9
BN:D
label9
BP:D
label9
BV:D
label9
BNV:D
label9
BLT:D
label9
BGE:D
label9
BLE:D
label9
BGT:D
label9
BLS:D
label9
BHI:D
label9
● Operation explanation
Operations with delay slots branch out after executing the command placed just after the branch command
(called a "delay slot") before executing the branch destination command. As the instruction in the delay slot
is executed prior to the branch, the apparent execution speed is one cycle. The NOP command must be
placed as an alternative if an effective command cannot be inserted in the delay slot.
[Example]
;
Row of instruction
ADD
R1, R2
BRA:D LABEL
MOV
R2, R3
...
LABEL:ST
R3,@R4
;
; Divergence instructions
; Delay slot ... Executed before branch.
; Branch destination
The command placed in the delay slot is executed regardless of whether the branch condition for the
condition branch command will be met or not.
For delay branch commands, the execution order of the partial command seems to be reversed, but this
applies only to PC update operations, and other operations (i.e. update and refer to register) are absolutely
executed in the described order.
A concrete explanation is done as follows.
• The Ri to be referred to for the JMP:[email protected]/CALL:[email protected] command will not be affected even if the
command within the delay slot updates the Ri.
[Example]
LDI:32
JMP:D
LDI:8
...
CM71-10155-2E
#Label,
@R0
#0,
R0
R0
; Branches out to Label
; Has no effect on branch destination address
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CHAPTER 3 CPU AND CONTROL UNIT
3.7 Divergence Instructions
MB91490 Series
• The RP to be referred by the RET:D command will not be affected even if the command within the
delay slot updates the RP.
[Example]
RET:D
MOV
...
R8,
RP
; Branches to the address in RP set previously.
; Has no effect on return operation.
• Flags to be referred by the Bcc:D rel instruction are also not affected by the delay slot instruction.
[Example]
ADD
BC:D
AND CCR
#1,
R0
Overflow
#0
; Flag change
; Branches based on execution result of above instruction.
; Do not refer to this flag update in the above-mentioned branch
instruction.
...
• If the instruction in the delay slot for the CALL:D instruction refers RP, it reads the value after updating
by CALL:D instruction.
[Example]
CALL:D
MOV
Label
RP,
R0
; Updating RP and branching
; RP of an execution result in the above-mentioned
CALL:D is forwarded.
...
● Restrictions
• Instruction that can be placed in the delay slot
Only instructions that satisfy the following conditions can be executed in the delay slot.
• 1-cycle command
• No branch instruction
• Instruction whose operation is not affected even though the order is changed
The "1-cycle command" is a command with "1", "a", "b", "c", or "d" described in the cycle number
column within the command list.
• Step trace trap
Step trace trap is not generated between executing the branch command with the delay slot and the delay
slot.
• Interrupts and NMI
Interrupts and NMI cannot be received between execution of a branch instruction with a delay slot and
the delay slot.
• Undefined instruction exception
No undefined instruction exception occurs if the delay slot contains an undefined instruction. At this
time, undefined instruction operates as NOP instruction.
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CHAPTER 3 CPU AND CONTROL UNIT
3.7 Divergence Instructions
MB91490 Series
■ Operation without Delay Slot
● Instruction
Instructions written as follows perform a branch operation without a delay slot:
JMP
@Ri
CALL label12
CALL @Ri
RET
BRA
label9
BNO
label9
BEQ label9
BNE label9
BC
label9
BNC
label9
BN
BV
label9
BNV
label9
BLT label9
BGE label9
BLE
label9
BGT
label9
BLS
BHI
label9
label9
BP
label9
label9
● Operation explanation
When the delay slot is not used, instructions are executed in the sequence they are coded. The next
instruction will not be executed prior to the branch.
[Example]
;
Row of instruction
ADD
R1, R2
;
BRA
LABEL
; Branch instruction (delay slot none)
MOV
R2, R3
; Not executed
...
LABEL:
ST
R3, @R4 ; Divergence destination
Execution cycle number for branch commands without delay slots will be 2 cycles branched, or 1 cycle
non-branched.
As the appropriate command cannot be inserted into the delay slot, the command code efficiency can be
improved more than the branch command with delay slot described the NOP.
A balance between execution speed and code efficiency can be struck by selecting either the operation with
the delay slot when effective commands can be set in the delay slot or the operation without the delay slot
when effective commands cannot be set.
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CHAPTER 3 CPU AND CONTROL UNIT
3.8 EIT (Exception, Interruption, and Trap)
3.8
MB91490 Series
EIT (Exception, Interruption, and Trap)
EIT, which is the generic term for "Exception", "Interrupt", and "Trap" indicates that the
program is suspended due to events generated while running the current program and
another program is being executed.
The exception is an event which occurs in relation to the context under execution.
Execution continues from the instruction that caused the exception.
The interruption is an event which occurs without any relation to the context under
execution. The event factor is hardware.
The trap is an event which occurs in relation to the context under execution. Some
traps, such as system calls, are specified in program. Execution continues from the
instruction after the instruction that caused the trap.
■ Feature of EIT
• Multiple interrupt is supported to the interruption.
• It is a level mask function (15 levels are available to the user) to the interruption.
• Trap instruction (INT)
• EIT (hardware/software) for emulator startup
■ EIT Factor
The following is used as an EIT factor.
• Reset
• User interruption (internal resource and external interruption)
• NMI
• Delayed interrupt
• Undefined instruction exception
• Trap instruction (INT)
• Trap instruction (INTE)
• Step trace trap
• Coprocessor absent trap
• Coprocessor error trap
■ Return from EIT
To return from EIT, RETI instruction is executed.
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CHAPTER 3 CPU AND CONTROL UNIT
3.8 EIT (Exception, Interruption, and Trap)
MB91490 Series
■ Interrupt Level
Interrupt levels are 0 to 31 and are managed by five bits.
The allocation of each level is as follows.
Table 3.8-1 Interrupt Level
Level
Interrupt Factor
Binary
Decimal
00000
0
...
...
...
...
...
...
00011
3
(System reservation)
(System reservation)
INTE instruction
00100
Note
4
Step trace trap
00101
5
...
...
...
...
...
...
01110
14
(System reservation)
01111
15
NMI (for user)
10000
16
Interrupt
10001
17
Interrupt
...
...
...
...
...
...
11110
30
11111
31
If the original value of ILM is between 16 and 31,
the value of this range cannot be set in the ILM
with program.
(System reservation)
When ILM is set, it is a user interruption
interdiction.
Interrupt
-
When ICR is set, it is an interruption interdiction.
It is a level of 16 to 31 that the operation is possible.
Undefined command exceptions, coprocessor absent traps, coprocessor error traps, and INT commands
dare not affected for interruption levels. Moreover, ILM may not be changed.
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CHAPTER 3 CPU AND CONTROL UNIT
3.8 EIT (Exception, Interruption, and Trap)
MB91490 Series
■ I Flag
It is a flag which specifies the permission and interdiction of the interruption. Contained in bit4 of CCR in
the PS register.
Value
Description
0
Interruption interdiction.
Cleared to "0" when the INT instruction is executed.
(However, the value saved on the stack is the value before the bit is cleared.)
1
Interruption permission.
The mask processing of the interruption demand is controlled by the value which ILM
maintains.
■ ILM
It is PS register (bit20 to bit16) which maintains the interrupt level mask value.
The interrupt request to be input to the CPU is accepted only when its interrupt level is stronger than the
level indicated by this ILM.
The highest level is 0 ("00000B") and the lowest level is 31 ("11111B").
There is a limitation in the value which can be set from the program. When the original value is between 16
and 31, new values can only be set in the range 16 to 31. Executing an instruction that sets a value between
0 and 15 results in (specified value + 16) being transferred.
When former value is 0 to 15, any value of 0 to 31 can be set. Use the STILM instruction to set the ILM.
■ Level Mask to Interruption and NMI
When an NMI or interrupt request occurs, the interrupt level (see Table 3.8-1) corresponding to the
interrupt factor is compared with the level mask set in the ILM. And, when the following condition
consists, the mask is done, and the demand is not accepted.
Interrupt levels of factor  level mask value
■ Interrupt Control Register (ICR)
This register is located in the interrupt controller and specifies the level for each interrupt request. ICR is
prepared for each of the interruption demand input. ICR is mapped on the I/O space and is accessed by
CPU through the bus.
● The ICR bit make-up
bit7
-
bit6
-
bit5
-
bit4
ICR4
R
bit3
ICR3
R/W
bit2
ICR2
R/W
bit1
ICR1
R/W
bit0
ICR0
R/W
Initial value
---11111B
[bit4] ICR4
This bit is always "1".
[bit3 to bit0] ICR3 to ICR0
Lower four bits of the interrupt level for the corresponding interrupt factor. The read and write are
possible.
ICR can set the value within the range of 16 to 31 together with bit4.
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CHAPTER 3 CPU AND CONTROL UNIT
3.8 EIT (Exception, Interruption, and Trap)
MB91490 Series
● ICR mapping
Table 3.8-2 Interruption Factor, Interruption Control Register, and Interruption Vector
Corresponding Interruption Vector
Interrupt
Factor
Interrupt Control Register
Number
Address
Hexadecimal
Decimal
IRQ00
ICR00
00000440H
10H
16
TBR + 3BCH
IRQ01
ICR01
00000441H
11H
17
TBR + 3B8H
IRQ02
ICR02
00000442H
12H
18
TBR + 3B4H
...
...
...
...
...
...
...
...
...
...
...
...
IRQ45
ICR45
0000046DH
3DH
61
TBR + 308H
IRQ46
ICR46
0000046EH
3EH
62
TBR + 304H
IRQ47
ICR47
0000046FH
3FH
63
TBR + 300H
TBR initial value: 000F FC00H
Reference: Refer to "CHAPTER 5 INTERRUPT CONTROLLER".
■ System Stack Pointer (SSP)
bit 31
bit0
SSP
Initial value
00000000H
The SSP is used as the pointer to the stack used to save and restore data when an EIT is accepted or a return
operation occurs.
8 is deducted from the content during EIT processing, and 8 is added when returning from EIT in line with
execution of the RETI command.
The initial value by reset is "00000000H".
The SSP can also be used as general-purpose register R15 when the S flag in the CCR is "0".
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CHAPTER 3 CPU AND CONTROL UNIT
3.8 EIT (Exception, Interruption, and Trap)
MB91490 Series
■ Interrupt Stack
The value in the PC or PS is saved to or restored from an area pointed to by the system stack pointer (SSP).
After an interrupt, the PC is stored at the address contained in the SSP and PS is stored at the (SSP + 4)
address.
Figure 3.8-1 Interrupt Stack
[Example]
[Before interrupt]
SSP
80000000H
[After interrupt]
SSP
7FFFFFF8H
Memory
80000000H
7FFFFFFCH
7FFFFFF8H
80000000H
7FFFFFFCH
7FFFFFF8H
PS
PC
■ Table Base Register (TBR)
bit 31
bit0
TBR
Initial value
000FFC00H
It is a register which shows the first address of the vector table for EIT.
The vector address is generated by adding the TBR and the offset value determined for each EIT factor.
The initial value by reset is "000FFC00H".
■ EIT Vector Table
The vector region for EIT is 1 KB region starting at address indicated by the TBR.
Each vector consists of four bytes and the relationship between the vector number and vector address is as
follows.
vctadr = TBR + vctofs
= TBR + (3FCH - 4 × vct)
vctadr:
Vector address
vctofs:
Vector offset
vct:
Vector number
The lower two bits of the addition result are always treated as "00B".
The region of 000FFC00H to 000FFFFFH is an initial region of the vector table by reset.
A special function is partially allocated to the vector.
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CHAPTER 3 CPU AND CONTROL UNIT
3.8 EIT (Exception, Interruption, and Trap)
MB91490 Series
■ Multiple EIT Processing
When a number of EIT factors are simultaneously generated, the CPU selects and accepts one EIT factor,
and after executing the EIT sequence, the detection of EIT factors is repeated.
When EIT factors are detected if there are no more EIT factors that can be accepted, the handler command
for the last EIT factor accepted will be executed.
Accordingly, if more than one EIT factor occurs at the same time, the sequence for executing the handler
for each EIT is determined by the following two elements:
(1)
Priority level of EIT factor acceptance
(2)
How other factors can be masked when one factor is accepted
■ Priority of EIT Factor
The priority for accepting EIT factors is the order for selecting factors executing EIT sequence that saves
the PS and PC, updates the PC (on demand), and executes mask processing for other factors.
The handler of the factor previously accepted is not previously executed necessarily.
The priority of the EIT factor acceptance is shown in Table 3.8-3.
Table 3.8-3 Priority of EIT Factor Acceptance and Mask to Other Factors
Priority of acceptance
Factor
Mask to other factors
1
Reset
Other factors are annulled.
2
Undefined instruction exception
Cancellation
3
INTE instruction
ILM = 4
Other factors are annulled.
4
INT instruction
I flag = 0
5
Coprocessor absent trap
Coprocessor error trap
6
User interrupt
ILM = level of accepted factor
7
NMI (for user)
ILM = 15
8
NMI (for emulator)
ILM = 4
9
Step trace trap
ILM = 4
-
Considering the mask processing for other EIT factors after an EIT factor is accepted, the sequence for
executing the handlers for EIT factors that occur simultaneously is as shown in Table 3.8-4.
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CHAPTER 3 CPU AND CONTROL UNIT
3.8 EIT (Exception, Interruption, and Trap)
MB91490 Series
Table 3.8-4 Execution Sequence of EIT Handler
Execution sequence of handler
Factor
1
Reset *
2
Undefined instruction exception
3
INTE instruction *
4
Step trace trap
5
NMI (for user)
6
INT instruction
7
User interrupt
8
Coprocessor absent trap and coprocessor error trap
*: Other factors are annulled.
[Example]
Figure 3.8-2 Multiple EIT Processing
Main routine
NMI handler
INT instruction
handler
Priority
(High) NMI occurring
(Low) INT instruction
executed
(1) Executed first
(2) Executed next
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CHAPTER 3 CPU AND CONTROL UNIT
3.8 EIT (Exception, Interruption, and Trap)
MB91490 Series
■ EIT Operation
In the following explanation, the transfer source "PC" is address of the instruction at which each EIT factor
was detected.
Similarly, the "address of the following instruction" has the following meaning depending on the
instruction at which each EIT was detected.
• At LDI: 32  PC + 6
• At LDI: 20, COPOP, COPLD, COPST, COPSV  PC + 4
• At the other instructions  PC + 2
● Operation of user interruption and NMI
When a user interrupt or user NMI interrupt request occurs, the following sequence is used to determine
whether or not to accept the request.
[Right or wrong judgment of interruption demand acceptance]
(1) The interruption levels of requests that are generated simultaneously are compared, and the one with the
highest level (the smallest numeric value) will be selected.
For the level used for the comparison, the value held in the corresponding ICR is used for a maskable
interrupt and the predefined constant is used for the NMI.
(2) If a number of interruption requests with the same level are generated, the interruption request with the
smallest interruption number will be selected.
(3) When the interrupt level is greater than or equal to the level mask value, the interrupt request is masked
and is not accepted.
To (4) at interrupt levels < level mask value.
(4) When the selected interruption request is an interruption that can be masked, the interruption request
will be masked and will not be accepted if the I flag is 0. To (5) if I flag is one.
To (5) regardless of the I flag value when the selected interruption demand is NMI.
(5) If the above conditions are satisfied, the interrupt request is accepted at the instruction processing
boundary.
If a user interrupt or NMI request is accepted when an EIT request is detected, the CPU operation is as
follows based on the interrupt number of the accepted interrupt request.
Note: () in the [operation] shows the address which the register indicates.
[Operation]
(1) SSP - 4
 SSP
(2) PS
 (SSP)
(3) SSP - 4
 SSP
(4) Address of the following instruction
 (SSP)
(5) Interrupt levels of accepted demand
 ILM
(6) "0"
 S flag
(7) (TBR + vector offset of accepted interruption demand)  PC
Detection of any new EITs is performed after the interrupt sequence completes and before the initial
instruction of the interrupt handler is executed. If an EIT that is able to be accepted is found at this time, the
CPU changes to the EIT processing sequence.
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CHAPTER 3 CPU AND CONTROL UNIT
3.8 EIT (Exception, Interruption, and Trap)
MB91490 Series
● Operation of INT instruction
INT # u8
Branches to the interrupt handler at the vector indicated by u8.
[Operation]
(1) SSP - 4
 SSP
(2) PS
 (SSP)
(3) SSP - 4
 SSP
(4) PC + 2
 (SSP)
(5) "0"
 I flag
(6) "0"
 S flag
(7) (TBR + 3FCH - 4 × u8)  PC
● Operation of INTE instruction
INTE
Branches to the interrupt handler for the vector with vector number #9.
[Operation]
(1) SSP - 4
 SSP
(2) PS
 (SSP)
(3) SSP - 4
 SSP
(4) PC + 2
 (SSP)
(5) "00100B"
 ILM
(6) "0"
 S flag
(7) (TBR + 3D8H)
 PC
Do not use the INTE command during the INTE command and step trace trap processing routine.
Moreover, EIT is not generated while executing the step by INTE.
● Operation of step trace trap
If the T flag in the SCR in the PS is set to enable the step trace function, a trap occurs after each instruction
and execution breaks.
[Condition of step trace trap detection]
(1) T flag = 1
(2) Not a delayed branch instruction.
(3) Executing code other than an INTE instruction or step trace trap processing routine.
(4) If the above conditions are satisfied, execution breaks at each instruction boundary.
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CHAPTER 3 CPU AND CONTROL UNIT
3.8 EIT (Exception, Interruption, and Trap)
MB91490 Series
[Operation]
(1) SSP - 4
 SSP
(2) PS
 (SSP)
(3) SSP - 4
 SSP
(4) Address of the following instruction  (SSP)
(5) "00100B"
 ILM
(6) "0"
 S flag
(7) (TBR + 3CCH)
 PC
When step trace traps are enabled by setting the T flag, NMI for users and user interruption are disabled.
Moreover, EIT by the INTE instruction is not generated.
In the FR family, the trap is generated from the following instruction by which T flag is set.
● Operation of undefined instruction exception
An undefined instruction exception occurs if an undefined instruction is detected during instruction
decoding.
[Detection condition of undefined instruction exception]
(1) It is detected that it is undefined instruction at the decipherment of the instruction.
(2) Located at other than a delay slot. (Not located immediately after a delayed branch instruction.)
(3) If the above conditions are satisfied, an undefined instruction exception is triggered and execution
breaks.
[Operation]
(1) SSP - 4
 SSP
(2) PS
 (SSP)
(3) SSP - 4
 SSP
(4) PC
 (SSP)
(5) "0"
 S flag
(6) (TBR + 3C4H)
 PC
The address saved as the PC is the address of the instruction at which the undefined instruction exception
was detected.
● Coprocessor absent trap
When a coprocessor command using an unmounted coprocessor is executed, a coprocessor absent trap will
be generated.
[Operation]
(1) SSP - 4
 SSP
(2) PS
 (SSP)
(3) SSP - 4
 SSP
(4) Address of the following instruction  (SSP)
CM71-10155-2E
(5) "0"
 S flag
(6) (TBR + 3E0H)
 PC
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CHAPTER 3 CPU AND CONTROL UNIT
3.8 EIT (Exception, Interruption, and Trap)
MB91490 Series
● Coprocessor error trap
If an error occurs when the coprocessor is used and then the coprocessor instruction that operates the
coprocessor is executed, a coprocessor error trap will be generated.
[Operation]
(1) SSP - 4
 SSP
(2) PS
 (SSP)
(3) SSP - 4
 SSP
(4) Address of the following instruction  (SSP)
(5) "0"
 S flag
(6) (TBR + 3DCH)
 PC
● Operation of RETI instruction
The RETI instruction is an instruction which returns from EIT processing routine.
[Operation]
(1) (R15)
 PC
(2) R15 + 4
 R15
(3) (R15)
 PS
(4) R15 + 4
 R15
The RETI instruction must be executed with the S flag set to "0".
■ Note
● Delay slot
In the delay slot of the branch instruction, there is a restriction concerning EIT.
Please refer to Section "3.7 Divergence Instructions" for details of the divergence instruction.
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CHAPTER 3 CPU AND CONTROL UNIT
3.9 Operating Mode
MB91490 Series
3.9
Operating Mode
This section explains the operating mode of the MB91490 series.
■ Operating Mode
It supports the single chip mode only.
In this mode, internal I/O, internal RAM, and internal Flash are enabled, and access to all other areas is
disabled. The external pins can be used by either the peripheral resources or general-purpose ports.
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CHAPTER 3 CPU AND CONTROL UNIT
3.9 Operating Mode
3.9.1
MB91490 Series
Mode Setting
In FR family, the operation mode is set by the mode pins (MD2, MD1, and MD0) and
mode data.
■ Mode Pin
The MD2, MD1, and MD0 pins specify operation in relation to the mode vector and reset vector fetch.
Settings other than those listed in the table are prohibited.
Mode pins
MD2
MD1
MD0
0
0
0
Mode name
Reset vector
access area
Internal ROM mode vector
Internal
Remarks
● Mode Data
The data written to the internal mode register (MODR) by the mode vector fetch (see Section "3.10.3 Reset
Sequence") is called the mode data.
After the mode register is set, the device operates in accordance with the operation mode set in the register.
The mode data is set by all types of reset. The mode data cannot be set by the user program.
<Detailed explanation of mode data>
bit23
bit22
bit21
bit20
bit19
bit18
bit17
bit16
0
0
0
0
0
1
1
1
Operation mode setting bits
[bit23 to bit16] Reserved bits
Always set to "00000111B". Operation is not guaranteed if a value other than "00000111B" is set.
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3.9 Operating Mode
MB91490 Series
3.9.2
Note
This section describes the note on operation mode setting.
■ Note
The mode data set in the mode vector must be located as byte data at "000FFFF8H".
As the FR family uses big endian as byte endian, place in the most significant byte (bit31 to bit24) as
shown below.
bit31
bit24 bit23
bit16 bit15
bit8bit7
bit0
Incorrect
000FFFF8H
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Mode Data
Correct
000FFFF8H
Mode Data
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
000FFFFCH
CM71-10155-2E
Reset Vector
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CHAPTER 3 CPU AND CONTROL UNIT
3.10 Reset (Device Initialization)
3.10
MB91490 Series
Reset (Device Initialization)
This section describes the reset operation.
■ Overview
When reset factors are generated, the device suspends all programs and hardware operations and initializes
the status. This state is called the reset state.
On removal of the reset factor, the device starts the program and hardware operation from its initialized
state. The series of operations from the reset state to the start of operations is called the reset sequence.
The following table shows the reset factor, reset level, reset operation mode, and oscillation stabilization
wait time after releasing set initialization reset (INIT).
Reset level
Reset factor
System
initialization reset
(SINIT)
- High -
Set initialization
reset (INIT)
- Medium -
Operation
initialization reset
(RST)
- Low -
External INITX
pin
Issue
Issue
Issue
Low voltage
detection reset
Watchdog reset
Software reset
60
Do not issue
Do not issue
Issue
Do not issue
Reset operation
mode
Normal
(asynchronous)
reset operation
only
Oscillation
stabilization wait
time after
releasing set
initialization reset
(INIT)
Minimum wait
time
(OS1, OS0=00B)
Medium wait time
(OS1, OS0=10B)
Issue
Normal
(asynchronous)
reset operation
only
No oscillation
stabilization wait
time
Issue
Normal
(asynchronous)
reset operation or
synchronous reset
operation
No oscillation
stabilization wait
time
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3.10 Reset (Device Initialization)
MB91490 Series
3.10.1
Reset Level
The reset operation for MB91490 series is divided into three levels, each of which is
triggered by different causes and performs different initialization. The following
describes each reset level.
■ System Initialization Reset (SINIT)
Reset to initialize all systems is called a system initialization reset (SINIT). The main content initialized by
system initialization reset (SINIT) is as follows.
[Initialization part by system initialization reset (SINIT)]
• Oscillation stabilization wait time (OS1 and OS0 bits in standby control register (STCR))
• All parts initialized by set initialization reset (INIT)
Please refer to the explanation of each function for details.
Always use the INITX pin to trigger a system initialization reset (SINIT) after the power is turned on.
■ Set Initialization Reset (INIT)
Reset to initialize all settings except for the oscillation stabilization wait time is called set initialization
reset (INIT).
The main content initialized by set initialization reset (INIT) is as follows.
[Initialization part by set initialization reset (INIT)]
• All settings related to internal clock (clock source selection, PLL control, divide ratio setting)
• All settings concerning state of other terminal
• All parts initialized by operation initialization reset (RST)
Please refer to the explanation of each function for details.
■ Operation Initialization Reset (RST)
Reset to initialize program operation is called an operation initialization reset (RST).
When a set initialization reset (INIT) is performed, the operation initialization reset (RST) is performed
also.
The main content initialized by operation initialization reset (RST) is as follows.
[Initialization part by operation initialization reset (RST)]
• Program operation
• CPU and internal bus
• Register settings in peripheral circuits
• I/O port setting
• Operation mode of device (setting of bus mode)
Please refer to the explanation of each function for details.
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CHAPTER 3 CPU AND CONTROL UNIT
3.10 Reset (Device Initialization)
3.10.2
MB91490 Series
Reset Factor
This section describes each reset factor and the associated reset level of this device.
■ Reset Factor
Reset factors that were generated in the past can be identified by reading the reset source register (RSRR).
(Refer to Section "3.11.6 Block Diagram of Clock Generation Control Unit" and Section "3.11.7
Explanation of Register Details for Clock Generation Control Unit" in the Section "3.11 Clock Generation
Control" for details of the registers and flags referred to below.)
■ INITX Terminal Input (System Initialization Reset Terminal)
The INITX external pin acts as the system initialization reset terminal.
A system initialization reset (SINIT) request is generated while a low level input is applied to this pin.
System initialization reset (SINIT) demand is released by inputting the High level to this terminal.
When system initialization reset (SINIT) is generated at the request of this terminal, the bit15: INIT bit
within the reset source register (RSRR) will be set.
The system initialization reset (SINIT) at the request of this terminal is the strongest of all reset factors and
will be handled in priority to all other inputs, operations, and statuses.
Always use the INITX pin to trigger a system initialization reset (SINIT) after turning on the power.
Immediately after the power is turned on, maintain low level input to the INITX terminal for the oscillation
stabilization wait time requested by the oscillation circuit to acquire the oscillation stabilization wait time
for the oscillation circuit. (When an SINIT is triggered by the INITX pin, the oscillation stabilization wait
time is initialized to its minimum value.)
• Generation factor:
Low level input to external INITX terminal
• Release factor:
High level input to external INITX terminal
• Generation level:
System initialization reset (SINIT)
• Correspondence flag:
bit15: INIT
■ Low Voltage Detection Reset (System Initialization Reset)
A system initialization reset (SINIT) request is generated by detecting below fixed voltage level of power
supply pin (VCC).
A system initialization reset (SINIT) request is released by detecting above fixed voltage level of Power
supply pin (VCC).
When system initialization reset (SINIT) is generated at the request of this factor, the bit 15:INIT within the
reset source register (RSRR) will be set.
When system initialization reset (SINIT) is generated at the request of this factor, oscillation stabilization
wait time will be initialized to wait time (medium) (OS1, OS0=10B).
• Generation factor:
Detect below fixed voltage level of Power Supply pin (VCC).
• Release factor:
Detect above fixed voltage level of Power Supply pin (VCC).
• Generation level:
System initialization reset (SINIT)
• Correspondence flag:
bit15: INIT
■ Watchdog Reset
The watchdog timer will be activated by writing to the watchdog timer control register (RSRR). Then a
watchdog reset request occurs per cycle specified in bit9 and bit8: WT1 and WT0 bits in the RSRR.
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MB91490 Series
Watchdog reset request is set initialization reset (INIT) demand. After the request is accepted, and when a
set initialization reset (INIT) or operation initialization reset (RST) is generated, the watchdog reset request
will be cancelled.
When a set initialization reset (INIT) is generated by a watchdog reset request, the bit13: WDOG bit within
the reset source register (RSRR) will be set.
When a set initialization reset (INIT) is generated by a watchdog reset request, the setup for the oscillation
stabilization wait time will not be initialized.
• Generation factor:
Specified cycle elapsed on the watchdog timer.
• Release factor:
Generation of a set initialization reset (INIT) or operation initialization reset
(RST).
• Generation level:
Set initialization reset (INIT)
• Correspondence flag:
bit13: WDOG
■ STCR: SRST Bit Writing (Software Reset)
When "0" is written to the bit4: SRST bit within the standby control register (STCR), a software reset
request will be generated.
Software reset request is operation initialization reset (RST) demand.
When the request is accepted and operation initialization reset (RST) is generated, the software reset
request will be cancelled.
When operation initialization reset (RST) is generated by a software reset request, the bit11: SRST bit
within the reset source register (RSRR) will be set.
Operation initialization reset (RST) through the software reset request is generated only after all bus
accesses are stopped when the bit9: SYNCR bit within the time-base counter control register (TBCR) is set
(synchronous reset mode).
• Generation factor:
Writing "0" to bit4: SRST bit of the standby control register (STCR).
• Release factor:
Generation of operation initialization reset (RST)
• Generation level:
Operation initialization reset (RST)
• Correspondence flag:
bit11: SRST
Note:
For using software reset on the synchronous mode, see the limitations of the bit9:SYNCR bit of
TBCR (time-base counter control register).
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3.10 Reset (Device Initialization)
3.10.3
MB91490 Series
Reset Sequence
The device begins the execution of the reset sequence by the disappearance of the
reset factor. The operation of the reset sequence is different depending on the reset
level. The content of the operation for the reset sequence at each reset level is
explained.
■ System Initialization Reset (SINIT) Release Sequence
This reset is triggered by an external INITX pin input or low voltage detection reset.
On release of a system initialization reset (SINIT) request, the device performs the following operations in
the order.
(1) Releasing the system initialization reset (SINIT)
(2) Set initialization reset (INIT) state and beginning of internal clock operation
(3) Releases the set initialization reset (INIT) and changes to the oscillation stabilization wait state
(4) [In case of the system initialization reset (SINIT) is triggered by the external INITX pin input.]
The device remains in the operation initialization reset (RST) state, and the internal clock operation
stops during the minimum oscillation stabilization wait time (bit3, bit2 of STCR:OS1, OS0=00B).
[In case of the system initialization reset (SINIT) is triggered by low voltage detection reset]
The device remains in the operation initialization reset (RST) state, and the internal clock stops during
the oscillation stabilization wait time (medium) (bit3, bit2 of STCR:OS1, OS0=10B).
(5) Operation initialization reset (RST) state and beginning of internal clock operation
(6) Releases the operation initialization reset (RST) and changes to the normal operating state
(7) Reading of mode vector from address 000FFFF8H
(8) Writes the mode vector to the MODR (mode register)
(9) Reading of reset vector from address 000FFFFCH
(10) Writing of the reset vector in PC (program counter)
(11) Starting a program from the address contained in the PC (program counter)
■ Set Initialization Reset (INIT) Release Sequence
This reset is triggered by a watchdog reset.
On release of a set initialization reset (INIT) request, the device performs the following operations in the
order.
(1) Releasing the set initialization reset (INIT)
(2) Operation initialization reset (RST) state and beginning of internal clock operation
(3) Releases the operation initialization reset (RST) and changes to the normal operating state
(4) Reading of mode vector from address 000FFFF8H
(5) Writes the mode vector to the MODR (mode register)
(6) Reading of reset vector from address 000FFFFCH
(7) Writing of the reset vector in PC (program counter)
(8) Starting a program from the address contained in the PC (program counter)
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3.10 Reset (Device Initialization)
MB91490 Series
■ Operation Initialization Reset (RST) Release Sequence
This reset is triggered by a software reset.
On release of an operation initialization reset (RST) request, the device performs the following operations
in the order.
(1) Releases the operation initialization reset (RST) and changes to the normal operating state
(2) Reading of mode vector from address 000FFFF8H
(3) Writes the mode vector to the MODR (mode register)
(4) Reading of reset vector from address 000FFFFCH
(5) Writing of the reset vector in PC (program counter)
(6) Starting a program from the address contained in the PC (program counter)
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CHAPTER 3 CPU AND CONTROL UNIT
3.10 Reset (Device Initialization)
3.10.4
MB91490 Series
Oscillation Stabilization Wait Time
Automatically transits to oscillation stabilization waiting status when the source
oscillation of the device has been suspended or when returning from a status with such
possibility. This function prevents the unstable oscillator output that occurs when the
oscillation first starts from being used.
During the oscillation stabilization wait time, the internal and external clock provision is
suspended, only built-in time-base counter operates, and pauses until the stabilization
waiting time set by the standby control register (STCR) has expired.
Hereafter, details of oscillate stabilization wait operation are explained.
■ Triggers for the Oscillation Stabilization Wait
The factor is shown below.
• When set initialization reset (INIT) is released by INITX pin factor or low voltage detection reset factor
The device goes to the oscillation stabilization wait state immediately after a set initialization reset (INIT)
is released by INITX pin factor or low voltage detection reset factor.
The device goes to the operation initialization reset (RST) state after the oscillation stabilization wait
time elapses.
The oscillation stabilization wait time is set to its minimum value by an INITX pin, therefore the
oscillation stabilization wait time is required by an input width of the INITX pin.
Furthermore, the device transits to the operation initialization reset (RST) state without changing to the
oscillation stabilization wait state immediately after the set initialization reset (INIT) due to the watchdog
reset factor is canceled.
• Recovery from stop mode
The device goes to the oscillation stabilization wait state immediately after the stop mode is released by
an input of a valid external interrupt request (including NMIs). If the mode is released by the INITX pin
or low voltage detection reset factor, it goes to the set initialization reset (INIT) state, and then to the
oscillation stabilization wait state after INIT is canceled.
The device goes to the state corresponding to the factor that stop mode is released after the oscillation
stabilization wait time elapses.
•When recovering due to input of a valid external interrupt request (including NMIs) 
Transits to normal operation state
•When recovering due to a system initialization reset (SINIT) request by INITX pin factor or low
voltage detection reset factor Transits to system initialization reset (SINIT) state
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MB91490 Series
■ Select Oscillation Stabilization Wait Time
The oscillation stabilization wait time is timed with built-in time-base counter.
When generation factors for oscillation stabilization waiting arise and it transits to the oscillation
stabilization waiting status, built-in time-base counter begins measurement of the oscillation stabilization
wait time after being initialized once.
4 types of oscillation stabilization wait time can be selected and set using the bit3 and bit2: OS1 and OS0
bits of the standby control register (STCR).
The setting that has been once selected will not be initialized by other than system initialization reset
(SINIT) using the external INITX pin or low voltage detection reset. Set initialization resets (INIT) and
operation initialization resets (RST) maintain the oscillation stabilization wait time setting before reset.
The four available oscillation stabilization wait time settings are intended for use in the following
situations.
• OS1, OS0 = 00B
: No oscillation stabilization wait time
(used when the PLL and oscillator do not halt in stop mode)
• OS1, OS0 = 01B
: Oscillation stabilization wait time (short)
(used with an external clock input or when the oscillator does not halt in stop
mode)
• OS1, OS0 = 10B
: Oscillation stabilization wait time (medium)
(used with an oscillator that is quick to stabilize such as a ceramic oscillator)
• OS1, OS0 = 11B
: Oscillation stabilization wait time (long)
(used with a standard crystal oscillator or similar)
Always use the INITX pin to trigger a system initialization reset (SINIT) after turning on the power.
In the following cases, maintain the low level input to the INITX pin for the stabilization wait time required
by the oscillation circuit to acquire the oscillation stabilization wait time of the oscillation circuit. (When an
SINIT is triggered by the INITX pin, the oscillation stabilization wait time is initialized to its minimum
value.)
• INITX pin input immediately after power on
• INITX pin input during STOP mode with the oscillation halted
Accordingly, input a "L" level to the INITX pin for a period that satisfies the oscillation stabilization wait
time for the main clock to allow the oscillation to stabilize.
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3.10 Reset (Device Initialization)
3.10.5
MB91490 Series
Reset Operation Mode
There are two modes for operation initialization resets (RST), namely, normal
(asynchronous) reset mode and synchronous reset mode, and which operation mode is
to be used is set by the bit9: SYNCR bit of the time-base counter control register
(TBCR).
This mode setting is initialized only by set initialization reset (INIT).
Set initialization reset (INIT) always does the reset action asynchronously.
Hereafter, each mode operation is explained.
■ Normal Reset Operation
The operation whereby the device goes to the operation initialization reset (RST) state immediately after an
operation initialization reset (RST) request occurs is called normal reset operation.
When a reset (RST) request is received in this mode, the device goes to the reset (RST) state immediately
regardless of the current status of internal bus access.
Results of the bus access performed at the time of transition to each status cannot be guaranteed under this
mode. However, the operation initialization reset (RST) request can be accepted reliably.
It will be normal reset mode when the bit9: SYNCR bit within the time-base counter control register
(TBCR) is "0".
The initial value after a set initialization reset (INIT) is normal reset mode.
■ Synchronous Reset Operation
The operation whereby the device goes to the operation initialization reset (RST) state only once all bus
access halts after an operation initialization reset (RST) request occurs is called synchronous reset
operation.
In this mode, the device does not change to the reset (RST) state while internal bus access is in progress
even though a reset (RST) request may be present.
When the above request is accepted, a sleep request is issued to the internal bus. The device goes to the
operation initialization reset (RST) state once each bus halts operation and goes to the sleep state.
As all bus accesses are stopped when transiting to each status under this mode, the results of all bus
accesses can be guaranteed.
However, if bus access does not stop for some reason, no requests can be accepted during that time.
However, even in this case, a set initialization reset (INIT) still occurs immediately.
This will be the synchronous reset mode when the bit9: SYNCR bit within the time-base counter control
register (TBCR) is "1".
The initial value after a set initialization reset (INIT) is to return to normal reset mode.
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CHAPTER 3 CPU AND CONTROL UNIT
3.10 Reset (Device Initialization)
Notes:
• Transfer of the DMA controller will be stopped on receiving each request, so transition to each
status does not need to be delayed.
• Refer to the limitations of the bit9:SYNCR bit of TBCR (time-base counter control register) for the
using software reset of the synchronous mode.
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CHAPTER 3 CPU AND CONTROL UNIT
3.11 Clock Generation Control
3.11
MB91490 Series
Clock Generation Control
This section explains the clock generation control.
■ Overview of Clock Generation Control
The internal operation clocks on this model are generated as follows.
• Source clock generation: The base clock is generated from the main clock divided by two or by using
the PLL oscillation.
• Generation of each internal clock: The source clock is divided to generate the operation clocks supplied
to each block.
Hereafter, each clock generation and the control are explained.
Refer to Section "3.11.6 Block Diagram of Clock Generation Control Unit" and "3.11.7 Explanation of
Register Details for Clock Generation Control Unit" for details of the registers and flags.
Internal clock
Main clock
Main clock
divided by 2
Divided
by 1 to 16
(DIVR0[7:4])
CPU clock (CLKB)
Source clock
Internal clock
Divided by 2
X0
X1
Oscillation
circuit
Divided
by 1 to 16
(DIVR0[3:0])
Selector
(CLKR[9:8])
Peripheral clock (CLKP)
PLL multiplied
by 2 to 8
(CLKR[14:12])
Main PLL clock
CLKR : Clock source control register
DIVR0 : Internal clock dividing frequency control register 0 (CLKB/CLKP)
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3.11 Clock Generation Control
MB91490 Series
3.11.1
Selection of the Source Clock
This section describes how the source clock is selected.
■ Selection of the Source Clock
All clock sources are supplied from within MB91490 series.
The external oscillator pins and internal oscillation circuit can switched at any time while the main clock is
in operation.
• Main clock: Generated from the X0 and X1 pin inputs and intended for use as the high-speed clock.
The source clock can be selectively generated from the following clocks.
• Main clock divided by two
• Main clock multiplied using the PLL
Selection of the source clock is controlled by the clock source control register (CLKR) setting.
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CHAPTER 3 CPU AND CONTROL UNIT
3.11 Clock Generation Control
3.11.2
MB91490 Series
PLL Control
Operation (oscillation) enable and disable and the multiplier ratio setting can be set for
the PLL oscillation circuit for the main clock.
Each control is done by setting clock source control register (CLKR).
Hereafter, the content of each control is explained.
■ PLL Enabling Operation
The value of bit10: PLL1EN bit of the clock source control register (CLKR) enables or halts the main PLL
oscillation.
The PLL1EN bit is initialized to "0" after a set initialization reset (INIT) to halt the main PLL oscillation.
The output of the main PLL cannot be selected as the source clock while it is halted.
Once program operation has started, set the multiplier ratio for the main PLL to use it as the source clock
and enable operation, and then wait for the PLL lock wait time to elapse before switching the source clock.
Using the time-base timer interrupt to time the PLL lock wait is recommended.
The PLL cannot be halted while the main PLL output is selected as the source clock.
When you wish to stop the PLL such as when changing to stop mode, select the main clock divided by two
as the source clock first before halting the PLL.
■ PLL Multiplication Rate
The multiplication rate for the main PLL is set up by the bit14 to bit12: PLL1S2, PLL1S1, and PLL1S0 bits
of the clock source control register (CLKR).
All bits are initialized to "0" after a set initialization reset (INIT).
After program operation starts when changing the PLL multiplier ratio to a value different to its initial
setting, always make the change before or at the same time as enabling PLL operation. After changing the
multiplier ratio, wait for the lock wait time before switching the source clock. Using the time-base timer
interrupt to time the PLL lock wait is recommended.
If you want to change the PLL multiplier ratio during operation, first change the source clock to something
other than the PLL. After changing the multiplier ratio, wait for the lock wait time before switching the
source clock, as in the case above.
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MB91490 Series
[Procedure for enabling main PLL operation => Switching source clock]
[Procedure for changing main PLL multiplication rate]
Source clock
Main PLL
Source clock
Main PLL
Main clock
divided by 2
Halt
Main PLL clock
Operation
(Stable)
Set PLL multiplication rate
(CLKR[14:12] )
Switch source clock
(CLKR[9:8]=00 B )
Main clock
divided by 2
Halt
Main clock
divided by 2
Enable PLL operation
Set PLL multiplication rate
(CLKR[14:12] )
(CLKR[10]= PLL1EN=1B )
Operation
(Unstable)
Main clock
divided by 2
Acquire PLL lock wait time
(600[μs] or more)
Operation
(Stable)
Operation
(Stable)
Main clock
divided by 2
Switch source clock
Switch source clock
(CLKR [9:8]= 10B )
(CLKR[9:8]=10 B )
Operation
(Stable)
Main PLL clock
Operation
(Unstable)
Main clock
divided by 2
Acquire PLL lock wait time
(600[μs] or more)
Main clock
divided by 2
Operation
(Stable)
Main PLL clock
Operation
(Stable)
[Procedure for halting main PLL operation]
Source clock
Main PLL
Main PLL clock
Operation
(Stable)
Switch source clock
(CLKR[9:8]= 00B )
Main clock
divided by 2
Operation
(Stable)
Halt PLL operation
(CLKR[10]= PLL1EN =0B )
Main clock
divided by 2
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Halt
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[Traansition to stop mode at OSCD=1B]
[Transition to stop mode at OSCD=1B (at PLL1EN=1B)]
Source clock
Main PLL
Source clock
Main PLL
Main PLL clock
Operation
(Stable)
Main PLL clock
Operation
(Stable)
Switch source clock
Switch source clock
(CLKR[ 9:8]=0 0B )
(CLKR [9:8]=00 B )
Operation
(Stable)
Main clock
divided by 2
Operation
(Stable)
Main clock
divided by 2
Set PLL multiplication rate
(CLKR [10]=PLL1EN=0B )
Main clock
divided by 2
Halt
Transit to stop mode
Transit to stop mode
(STCR[7] =STOP=1B )
(STCR[7]=S TOP=1B )
Halt
Halt
Halt
Halt
Return from stop mode
Return from stop mode
(STCR[7]=0B )
Main clock
divided by 2
(Unstable)
74
(STCR[7]=0B )
Halt
Main clock
divided by 2
(Unstable)
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Operation
(Unstable)
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MB91490 Series
3.11.3
Oscillation Stabilization Wait and PLL Lock Wait Time
If the operation of the clock selected as the source clock is not stable, an oscillation
stabilization wait time is required. (See Section "3.10.4 Oscillation Stabilization Wait
Time".)
A wait time while the PLL locks is required after the PLL starts operating to allow the
output to stabilize at the specified frequency.
This section describes the wait time used in various situations.
■ Wait Time after Power Supply is Turned on
An oscillation stabilization wait time for the main clock oscillation circuit is required first after the power is
turned on.
Setting for oscillation stabilization wait time is initialized to the minimum value through input from the
INITX terminal (system initialization reset terminal), so this oscillation stabilization wait time will be
acquired from the time for inputting the low level to the INITX terminal input.
As the PLL is still not enabled in this state, the lock wait time does not need to be considered in this case.
■ Wait Time after System/Setting is Initialized
When a set initialization reset (INIT) is released after the system initialization reset (SINIT) is canceled,
the device goes to the oscillation stabilization wait state. Here, the set oscillation stabilization wait time is
internally generated.
As the setting time is initialized to its minimum value for the initial oscillation stabilization wait state after
the INITX pin input ends, this state ends quickly and the device changes to the operation initialization reset
(RST) state.
Under such statuses, no operation of any PLL is enabled, so the lock wait time does not need to be
considered at this stage.
■ Wait Time after Enabling PLL Operation
If you intend to enable the PLL from the halted state after program operation starts, the output of the PLL
cannot be used until the lock wait time has elapsed.
If main PLL is not selected as the source clock, program execution can continue while waiting for the PLL
to lock. Using the time-base timer interrupt to time the PLL lock wait is recommended.
■ Wait Time after Changing the PLL Multiplier Ratio
After program operation starts if you want to change the multiplier ratio for the PLL while it is running, the
output of the PLL cannot be used until the lock wait time has elapsed.
If main PLL is not selected as the source clock, program execution can continue while waiting for the PLL
to lock. Using the time-base timer interrupt to time the PLL lock wait is recommended.
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■ Wait Time after Recovering from Stop Mode
After program operation starts, the oscillation stabilization wait time set by the program is generated
internally after recovering from stop mode.
If the device is set to halt the oscillation circuit for the clock selected as the source clock during stop mode,
the time which adds the oscillation stabilization wait time for the oscillation circuit and the lock wait time
for the PLL must be used as the wait time. Always set the oscillation stabilization wait times before
changing to stop mode.
If the device is set not to halt the oscillation circuit for the clock selected as the source clock during stop
mode, the PLL is not halted automatically. Accordingly, no oscillation stabilization wait time is required
unless you halt the PLL.
It is recommended that you set the minimum value of the oscillation stabilization wait time before changing
to stop mode.
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3.11.4
Clock Distribution
The internal clocks for each function are generated from the source clock which is
generated from the main clock respectively.
There are a total of two different internal clocks and the divide ratio can be set
independently for each clock.
The each internal clock is explained as follows.
■ CPU Clock (CLKB)
It is a clock used for CPU, an internal memory, and an internal bus.
The circuit which uses this clock is as follows.
• CPU
• Internal RAM, internal Flash
• Bit search module
• I-bus, D-bus, F-bus, X-bus
• DMA controller
Do not set a combination of multiplier ratio and divide ratio that results in the upper-limit frequency being
exceeded.
■ Peripheral Clock (CLKP)
This is the clock used by the peripheral resources and the peripheral bus.
The circuit which uses this clock is as follows.
• Peripheral (surrounding) bus
• Clock controller (bus interface part only)
• Interrupt controller
• I/O port
• Peripheral resources such as the external interrupt inputs and 16-bit timer.
Do not set a combination of multiplier ratio and divide ratio that results in the upper-limit frequency being
exceeded.
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3.11.5
MB91490 Series
Clock Divider
The source clock divide ratio can be set independently for each internal clock. The best
operation frequency for each circuit can be set by this function.
■ Clock Divider
The division rate is set up using internal clock dividing frequency set register 0 (DIVR0). There are 4
setting bits that support each clock, and (register set up value + 1) will be the division rate for the base
clock of that clock. The duty ratio is always 50% even if an odd-numbered divide ratio is set.
If the setting is modified, the new divide ratio applies from the next rising edge on the clock signal.
The divide ratio setting is not initialized by an operation initialization reset (RST) and the setting prior to
the reset remains. The setting is only initialized by a set initialization reset (INIT). If changing the source
clock from its initial setting to a higher speed, always set the divide ratio beforehand.
Operation is not guaranteed if the combination of the source clock selection, main PLL multiplier ratio
setting, and divide ratio setting results in the upper-limit frequency being exceeded. Great care must be
taken (in particular not to adopt the wrong order with modification settings for the source clock selection).
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3.11.6
Block Diagram of Clock Generation Control Unit
The block diagram of clock generation control unit is shown as follows. Refer to
Section "3.11.7 Explanation of Register Details for Clock Generation Control Unit" for
detailed explanations of the register within the figure.
R-bus
■ Block Diagram of Clock Generation Control Unit
[Clock generator]
DIVR0
register
CLKR register
CPU clock (CKLB)
Oscillation
circuit
Main clock
1/2
PLL
X1
Source clock
Peripheral clock
division
Stop control
X0
Selector
CPU clock division
Peripheral clock
(CLKP)
[Stop and sleep controller]
Interrupt
Stop status
STCR register
Sleep status
State transition
control circuit
System initialization reset
(SINIT)
Set initialization reset
(INIT)
Operation initialization reset
(RST)
INITX
Reset occurrence FF
Low voltage
detection reset
Reset occurrence FF
[Reset source circuit]
RSRR register
[Watchdog controller]
Watchdog
FF
CTBR register
Time-base
counter
Counter clock
Selector
TBCR register
Overflow
detection FF
Interrupt enable
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Time-base timer
interrupt
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3.11.7
MB91490 Series
Explanation of Register Details for Clock Generation
Control Unit
This section describes the register of the clock generation control unit.
■ Reset Source Register/Watchdog Timer Control Register (RSRR)
Address
00000480H
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
INIT
R
1
R
-
WDOG
R
0
R
-
SRST
R
0
R
-
WT1
R/W
0
WT0
R/W
0
*
x
*
x
x
*
x
*
*
x
0
0
0
0
Initial value (INITX pin or
Low voltage detection reset)
Initial value (INIT)
*
Initial value (RST)
x
R/W : Readable/writable
R : Read only
* : Vary depending on the source.
× : Not initialized
This register retains reset factors that were generated just beforehand and performs cycle setting and
initiation control of the watchdog timer.
After reading, the maintained reset factor is cleared when this register is read. If a number of resets are
generated before reading, the reset factor flags accumulate, and a number of the flags will be set.
Writing a synchronous setting value to the WT1 and WT0 bits in this register, starts the watchdog timer.
The watchdog timer keeps working until reset (RST) is generated after that.
[bit15] INIT (INITialize reset occurred)
Indicates whether a reset triggered by the INITX pin input or low voltage detection reset (SINIT) has
occurred.
0
No SINIT has occurred due to an INITX pin input or low voltage detection reset.
1
SINIT has occurred due to an INITX pin input or low voltage detection reset.
•Initialized to "0" after a read.
•read only. Writing has no effect on the bit values.
[bit14] (reserved bit)
[bit13] WDOG (WatchDOG reset occurred)
Indicates whether a reset triggered by the watchdog timer (INIT) has occurred.
0
No INIT has occurred due to the watchdog timer.
1
INIT has occurred due to the watchdog timer.
•Initialized to "0" after a read and after a reset triggered by the INITX pin input or low voltage detection
reset (SINIT).
•read only. Writing has no effect on the bit values.
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[bit12] (reserved bit)
[bit11] SRST (Software ReSeT occurred)
Indicates whether reset (RST) by the SRST bit (software reset) of the STCR register is generated or not.
0
No RST has occurred due to a software reset.
1
RST has occurred due to a software reset.
•Initialized to "0" after a read and after a reset triggered by the INITX pin input or low voltage detection
reset (SINIT).
•read only. Writing has no effect on the bit values.
•Refer to the limitations of the bit9:SYNCR bit of TBCR (time-base counter control register) for the
using software reset of the synchronous mode.
[bit10] (reserved bit)
[bit9, bit8] WT1,WT0 (Watchdog interval Time select)
Sets the period of the watchdog timer.
The period of the watchdog timer is selected from the following four settings based on the value written
to these bits.
WT1
WT0
Occurring watchdog reset
0
0
 × 217 (Initial value)
0
1
 × 219
1
0
 × 221
1
1
 × 223
( is the period of the source clock.)
•Initialized to "00B" by reset (RST).
•Read is enabled while write is valid only once after reset (RST), thereafter write will be invalid.
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■ Standby Control Register (STCR)
Address
00000481H
Initial value (INITX pin)
Initial value (Low
voltage detection reset)
Initial value (INIT)
Initial value (RST)
R/W : Readable/writable
× : Not initialized
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
STOP
R/W
0
0
SLEEP
R/W
0
0
HIZ
R/W
1
1
SRST
R/W
1
1
OS1
R/W
0
1
OS0
R/W
0
0
R/W
-
OSCD1
R/W
1
1
0
0
0
0
1
x
1
1
x
x
x
x
1
x
1
x
It is a register which controls the operation mode of the device.
Transits to two standby modes, namely stop and sleep, controls the terminals under the stop mode and
carries out oscillation stop control, sets up oscillation stabilization wait time, and issues software resets.
Note:
To place the device in standby mode, use the synchronous standby mode (set with bit8: SYNCS bit
of the time-base counter control register (TBCR)) and be sure to use the following sequence:
// -- STCR Write
LDI
#_STCR, R0
// STCR register (0481H)
LDI
#value_of_standby, R1
// value_of_standby is the data to write to STCR.
STB
R1, @R0
// Writing in standby control register (STCR)
// -- CTBR Write
; CTBR register (0483H)
LDI
#_CTBR,R2
LDI
#0xA5,R1
; Clear command (1)
STB
R1,@R2
; Write A5H to CTBR
LDI
#0x5A,R1
; Clear command (2)
STB
R1,@R2
; Write 5AH to CTBR (time-base counter clear)
LDUB
@R0, R1
; STCR read (start the synchronous standby shifting)
LDUB
@R0, R1
; Dummy re-read of STCR
NOP
; NOP for timing adjustment × 5
NOP
NOP
NOP
NOP
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The following describes the functions of each bit in the standby control register (STCR).
[bit7] STOP (STOP mode)
Changes the device to stop mode. When 1 is written to both bit6: SLEEP bit and this bit, this bit is given
priority and the device transits to the stop mode.
0
Does not change to stop mode. (Initial value)
1
Changes to stop mode.
•Initialized to "0" by a reset (RST) and by stop recovery factor.
•Read and write are possible.
[bit6] SLEEP (SLEEP mode)
The transition to sleep mode is directed. When 1 is written to both bit7: STOP bit and this bit, bit7: STOP
bit has precedence, and the device transits to the stop mode.
0
Does not change to sleep mode. (Initial value)
1
Changes to sleep mode.
•Initialized to "0" by a reset (RST) and by sleep recovery factor.
•Read and write are possible.
[bit5] HIZ (HIZ mode)
The state of the terminal at the stop mode is controlled.
0
The state of the terminal before shifting to the stop mode is maintained.
1
Terminal output is put into the state of high impedance in the stop mode. (Initial value)
•Initialized to "0" by reset (INIT).
•Read and write are possible.
[bit4] SRST (Software ReSeT)
Invokes a software reset (RST).
0
Generates a software reset.
1
Does not generate a software reset. (Initial value)
•Initialized to 1 by reset (RST).
•Read and write are possible. The value read is always "1".
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[bit3, bit2] OS1,OS0 (Oscillation Stabilization time select)
Sets the oscillation stabilization wait time to use after a reset (INIT) or recovery from stop mode.
The length of the oscillation stabilization wait time is selected from the following four settings based on
the value written to these bits.
OS1
OS0
Oscillation stabilization
wait time
When main oscillation
10MHz
When main oscillation
20MHz
0
0
 × 21 (Initial value)
400 ns
200 ns
0
1
 × 211
408 s
204 s
1
0
 × 216
13.1 ms
6.55 ms
1
1
 × 222
838 ms
419 ms
( is the period of the source clock and is twice the period of the main clock.)
•Initialized to "00B" by a reset triggered by the INITX pin input (SINIT).
•Initialized to "10B" by a reset triggered by low voltage detection reset (SINIT).
•Read and write are possible.
[bit1] (reserved bit)
Reserved bit. Always write "1" to this bit on MB91490 series.
[bit0] OSCD1 (Oscillation Disable mode for XIN1)
Controls whether the oscillation halts for the main oscillation input (X0 and X1) during stop mode.
0
The main oscillation does not halt during stop mode.
1
The main oscillation halts during stop mode. (Initial value)
•Initialized to "1" by reset (INIT).
•Read and write are possible.
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■ Time-base Counter Control Register (TBCR)
Address
00000482H
Initial value (INIT)
Initial value (RST)
R/W : Readable/writable
× : Not initialized
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
TBIF
R/W
0
0
TBIE
R/W
0
0
TBC2
R/W
x
x
TBC1
R/W
x
x
TBC0
R/W
x
x
R/W
x
SYNCR
R/W
0
x
SYNCS
R/W
0
x
It is a register which controls the time-base timer interruption etc.
Enables time-base timer interruption, selects interruption interval time, and also sets up option functions for
reset operations.
The following describes the functions of each bit in the time-base counter control register (TBCR).
[bit15] TBIF (time-base timer Interrupt Flag)
The interrupt flag for the time-base timer.
Indicates that the time-base counter has expired the set interval time (bit13 to bit11: TBC2 to TBC0 bits).
While interruption generation is enabled (TBIE = 1) by the bit14: TBIE bit, when this bit is "1", a timebase timer interruption request is generated.
Clear factor
Writing of 0 by instruction
Set factor
After specified interval time has elapsed (detection of a falling edge on the output of the
time-base counter)
•Initialized to 0 by reset (RST).
•Read and write are possible. However, only 0 can be written to this bit, and writing 1 does not change
the bit value.
Moreover, the read value in the read modification write (RMW) system instruction always becomes 1.
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[bit14] TBIE (time-base timer Interrupt Enable)
It is a time-base timer interruption demand output permission bit.
Controls output of interrupt requests when the interval time set for the time-base counter elapses. While
this bit is "1", bit15: TBIF bit will be "1", and a time-base timer interruption request is generated.
0
Disable output of time-base timer interrupt requests. (Initial value)
1
Enable output of time-base timer interrupt requests.
•Initialized to "0" by reset (RST).
•Read and write are possible.
[bit13 to bit11] TBC2,TBC1,TBC0 (time-base timer Counting time select)
The interval time of the time-base counter used with the time-base timer is set.
The interval time is selected from the following eight settings based on the value written to these bits.
TBC2
TBC1
TBC0
Timer interval time
For a 20MHz source oscillation
and a x4 PLL multiplier
0
0
0
 × 211
25 s
0
0
1
 × 212
51.2 s
0
1
0
 × 213
102.4 s
0
1
1
 × 222
52.4 ms
1
0
0
 × 223
104.9 ms
1
0
1
 × 224
209.7 ms
1
1
0
 × 225
419.4 ms
1
1
1
 × 226
838.9 ms
( is the period of the source clock.)
•The initial value is undefined. Be sure to set a value before enabling the interrupt.
•Read and write are possible.
[bit10] (reserved bit)
Reserved bit. The value when read is undefined. Writing has no effect on the operation.
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[bit9] SYNCR (SYNChronous Reset enable)
It is a synchronous reset operation permission bit.
This bit specifies whether normal reset operation or synchronous reset operation is executed when an
operation initialization reset (RST) request. Normal reset operation performs a reset (RST) immediately.
Synchronous reset operation performs an operation initialization reset (RST) after all bus accesses have
stopped.
0
Normal reset operation (Initial value)
1
Synchronous reset operation
•Initialized to "0" by reset (INIT).
•Read and write are possible.
Limitation:
Meet two the following requirement before setting 0 to the SRST bit of STCR (standby control register)
at using software reset of the synchronous mode.
•Set interrupt enable flag (I-Flag) to interrupt disable (I-Flag=0).
•Do not use NMI.
[bit8] SYNCS (SYNChronous Standby enable)
It is a synchronous standby operation permission bit.
Always set to "1" when using standby modes (sleep or stop mode).
0
Normal standby operation (Initial value)
1
Synchronous standby operation
•Initialized to "0" by reset (INIT).
•Read and write are possible.
Note:
Set to the synchronous standby operation by setting "1" for transiting to the standby mode.
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■ Time-base Counter Clear Register (CTBR)
Address
00000483H
W
×
Initial value (INIT)
Initial value (RST)
: Write only
: Not initialized
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
D7
W
x
x
D6
W
x
x
D5
W
x
x
D4
W
x
x
D3
W
x
x
D2
W
x
x
D1
W
x
x
D0
W
x
x
It is a register to initialize the time-base counter.
Successively writing "A5H" and then "5AH" to this register clears all bits of the time-base counter to "0"
immediately after the "5AH" value is written. Although there is no limit on the length of time between
writing "A5H" and "5AH", if you write a value other than "5AH" after writing "A5H", the counter is not
cleared the next time you write "5AH" unless you first write "A5H" again.
The reading value of this register is undefined.
Note:
When this register is used to clear the time-base counter, the oscillation stabilization wait time,
watchdog timer period, and time-base timer period change temporarily.
■ Clock Source Control Register (CLKR)
Address
00000484H
Initial value (INIT)
Initial value (RST)
R/W : Readable/writable
× : Not initialized
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
R/W
x
PLL1S2
R/W
0
x
PLL1S1
R/W
0
x
PLL1S0
R/W
0
x
R/W
x
PLL1EN
R/W
0
x
CLKS1
R/W
0
x
CLKS0
R/W
0
x
This register is used to select the source clock and to control the main PLL.
This register selects the source clock. The register is also used to enable the main PLL and set the
multiplier ratio.
[bit15] (reserved bit)
Reserved bit. Always write "0" to this bit on MB91490 series.
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[bit14 to bit12] PLL1S2,PLL1S1,PLL1S0 (PLL1 ratio Select 2 to 0)
The main PLL multiplier ratio selection bits.
The main PLL multiplier ratio can be selected from the following combinations.
Modifying these bits while the main PLL is selected as the source clock is prohibited.
Do not specify a setting that will result in the upper-limit frequency for the device being exceeded.
PLL1S2 PLL1S1 PLL1S0
Main PLL multiply-by
rate
When main oscillation
10MHz
When main oscillation
20MHz
0
0
0
 1 (equal)
Setting disabled
Setting disabled
0
0
1
 2 (2 multiplication)
Setting disabled
 = 25 ns (at 40 MHz)
0
1
0
 3 (3 multiplication)
Setting disabled
 = 16.6 ns (at 60 MHz)
0
1
1
 4 (4 multiplication)
 = 25.0 ns (at 40 MHz)
 = 12.5 ns (at 80 MHz)
1
0
0
 5 (5 multiplication)
 = 20.0 ns (at 50 MHz)
Setting disabled
1
0
1
 6 (6 multiplication)
 = 16.6 ns (at 60 MHz)
Setting disabled
1
1
0
 7 (7 multiplication)
 = 14.3 ns (at 70 MHz)
Setting disabled
1
1
1
 8 (8 multiplication)
 = 12.5 ns (at 80 MHz)
Setting disabled
( is the period of the main PLL clock.)
•Initialized to "000B" by reset (INIT).
•Read and write are possible.
[bit11] (reserved bit)
Reserved bit. Always write "0" to this bit on MB91490 series.
[bit10] PLL1EN (PLL1 ENable)
The operation enable bit for the main PLL.
Modifying this bit while the main PLL is selected as the source clock is prohibited.
Selecting the main PLL as the source clock while this bit is "0" is prohibited.
See the bit9 and bit8: CLKS1 and CLKS0 bits settings.
If bit0: OSCD1 of STCR is "1", the main PLL stops during stop mode even if this bit is "1".
After the device returns from the stop mode, the main PLL is enabled again.
0
Main PLL stopped (Initial value)
1
Main PLL enabled
•Initialized to "0" by reset (INIT).
•Read and write are possible.
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[bit9, bit8] CLKS1,CLKS0 (CLocK source Select)
Sets the source clock to use.
The source clock is selected from the following three settings based on the value written to these bits.
CLKS1
CLKS0
Source clock setting
0
0
Main divided by two (Initial value)
0
1
Setting disabled
1
0
Main PLL
1
1
Setting disabled
•Initialized to "00B" by reset (INIT).
•Read and write are possible.
Note:
Changing the value of bit8: CLKS0 when bit9: CLKS1 is "1" is prohibited.
[Combinations able to be modified]
00B  10B
10B  00B
Setting other than one of the above combinations is prohibited.
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■ Internal Clock Dividing Frequency Set Register 0 (DIVR0)
Address
00000486H
Initial value (INIT)
Initial value (RST)
R/W : Readable/writable
× : Not initialized
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
B3
R/W
0
x
B2
R/W
0
x
B1
R/W
0
x
B0
R/W
0
x
P3
R/W
0
x
P2
R/W
0
x
P1
R/W
1
x
P0
R/W
1
x
This register controls the ratios for dividing the source clock to generate each internal clock.
Under this register, the division rate between the CPU clock (CLKB) and peripheral clock (CLKP) will be
set.
Operation is not guaranteed if the combination of the source clock selection, main PLL multiplier ratio
setting, and divide ratio setting results in the upper-limit frequency being exceeded. Please take great care
with this point. Also take care not to make a mistake in the sequence when changing the source clock
selection.
When settings for this register are modified, after the set up, the division rate after modification from the
next clock will be valid.
[bit15 to bit12] B3,B2,B1,B0 (clkB divide select 3 to 0)
These are clock dividing frequency ratio set bits of the CPU clock (CLKB).
Sets the clock divide ratio for the CPU clock (CLKB).
The value written to these bits selects the division rate to the source clock (clock frequency) for the CPU
clock (CLKB) from the 16 types shown in the following table.
Do not set a divide ratio that will result in the upper-limit frequency for the device being exceeded.
B3
B2
B1
B0
Clock division ratio
0
0
0
0

0
0
0
1
 × 2 (divided by 2)
0
0
1
0
 × 3 (divided by 3)
0
0
1
1
 × 4 (divided by 4)
0
1
0
0
 × 5 (divided by 5)
0
1
0
1
 × 6 (divided by 6
0
1
1
0
 × 7 (divided by 7)
0
1
1
1
 × 8 (divided by 8)
...
...
...
...
...
1
1
1
1
 × 16 (divided by 16)
( is the period of the source clock.)
•Initialized to "0000B" by reset (INIT).
•Read and write are possible.
[bit11 to bit8] P3,P2,P1,P0 (clkP divide select 3 to 0)
These are clock dividing frequency ratio set bits of the peripheral clock (CLKP).
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Sets the clock divide ratio for the peripheral clock (CLKP).
The value written to these bits selects the division ratio to the source clock (clock frequency) for the
peripheral clock (CLKP) from the 16 types shown in the following table.
Do not set a divide ratio that will result in the upper-limit frequency for the device being exceeded.
P3
P2
P1
P0
Clock division ratio
0
0
0
0

0
0
0
1
 × 2 (divided by 2)
0
0
1
0
 × 3 (divided by 3)
0
0
1
1
 × 4 (divided by 4)
0
1
0
0
 × 5 (divided by 5)
0
1
0
1
 × 6 (divided by 6
0
1
1
0
 × 7 (divided by 7)
0
1
1
1
 × 8 (divided by 8)
...
...
...
...
...
1
1
1
1
 × 16 (divided by 16)
( is the period of the source clock.)
•Initialized to "0011B" by reset (INIT).
•Read and write are possible.
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3.11.8
Peripheral Circuit Functions in the Clock Controller
The following describes the peripheral circuit functions in the clock controller.
■ Time-base Counter
The clock controller includes a 26-bit time-base counter which runs on the source clock.
In addition to generating the oscillation stabilization wait time (see Section "3.10.4
Stabilization Wait Time"), the time-base counter is used for the following purposes.
Oscillation
• Watchdog timer
The watchdog timer is used to detect system runaway and measures the bit output of the time-base
counter.
• time-base timer
Uses the output of the time-base counter to generate interval interrupts.
Hereafter, these functions are explained.
● Watchdog timer
The watchdog timer uses the output of the time-base counter to detect program runaway.
If postponement of the watchdog reset is not generated between the intervals that have been set, due to a
program runaway or such like, the set initialization reset (INIT) request is generated as a watchdog reset.
[Starting the watchdog timer and setting the period]
The watchdog timer is activated by first writing a period setting value to the WT1 and WT0 bits in the
reset source register/watchdog timer control register (RSRR) after reset (RST). In this case, the interval
for the watchdog timer is set by the bit9 and bit8: WT1 and WT0 bits. For the interval setting, only the
time that has been set through this first writing will be valid, and all other writings after that will be
ignored.
[Generation of a watchdog reset]
The flag for generating watchdog resets is set by the falling edge of the time-base counter output for the
interval that has been set. If the flag is set when the 2nd falling edge is detected, a set initialization reset
(INIT) request is generated as the watchdog reset.
[Stopping watchdog timer]
Once the watchdog timer is activated, the watchdog timer cannot be stopped until an operation
initialization reset (RST) is generated.
Under the following status in which an operation initialization reset (RST) is generated, the watchdog
timer is stopped and does not function until activated by a re-program operation.
CM71-10155-2E
•
State of operation initialization reset (RST)
•
State of set initialization reset (INIT)
•
State of system initialization reset (SINIT)
•
State of oscillation stabilization wait reset (RST)
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[Temporarily halting the watchdog timer (automatically postpone generation)]
The watchdog timer initializes the flag to once generate a watchdog reset when the program operation of
the CPU is stopped and postpones generation of a watchdog reset. The stop of the program operation
concretely shows the following operations.
•Sleep state
•Stop state
•Oscillation stabilization wait RUN state
•During DMA transfer to the D-bus (data bus)
•During a break when using the emulator-debugger
When the time-base counter is cleared, the flag for generating watchdog resets is simultaneously
initialized, and generation of a watchdog reset will be postponed.
Note:
Clear the time-base counter immediately before reading standby control register (STCR) after setting
STOP mode bit/SLEEP mode bit, when the mode shifts to sleep mode/stop mode after starting the
watchdog timer. The program example is described as follows;
● Sample program
Standby (stop or sleep) mode shift processing
------------------------------------------------------------------------------------------------------------------// -- Write STCR
LDI
#_STCR,R0
// STCR register (0481H)
LDI
#value_of_standby, R1
// value_of_standby is a write data to STCR
STB
R1,@R0
// Write to STCR
// -- Write CTBR
LDI
#_CTBR,R2
// CTBR register (0483H)
LDI
#0xA5,R1
// Clear command (1)
STB
R1,@R2
// Write A5H to CTBR
LDI
#0x5A,R1
// Clear command (2)
STB
R1,@R2
// Write 5AH to CTBR (time-base counter clear)
LDUB
@R0,R1
// Read STCR (Start the synchronous stand-by shifting)
LDUB
@R0,R1
// Read dummy STCR
NOP
// NOP  5 for adjust timing
NOP
NOP
NOP
NOP
-------------------------------------------------------------------------------------------------------------------
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● time-base timer
The time-base timer uses the output of the time-base counter to generate interval interrupts.
The timer is suitable for measuring relatively long times, up to {Period of source clock  226} cycles such
as for the main PLL lock wait time.
The time-base timer interruption request is generated when the falling edge of the output for the time-base
counter that supports the set interval is detected.
[Setting of time-base timer at startup and intervals]
The time-base timer sets the interval using the bit13 to bit11: TBC2, TBC1, and TBC0 bits of the timebase counter control register (TBCR).
As the falling edge of the output for the time-base counter that supports the set interval is always
detected, after the interval is set, firstly clear the bit15: TBIF bit, and then enable interruption request
output by setting "1" as the bit14: TBIE bit.
Before changing the interval time, disable the interrupt request output by setting "0" as the bit14: TBIE
bit.
As the time-base counter always counts without being influenced by these settings, clear the time-base
counter before enabling interruption in order to get accurate interval interruption times. If this is not
done, an interrupt request may be generated immediately after interrupts are enabled.
[Clearness of time-base counter by program]
Writing "A5H" and then "5AH" to the time-base counter clear register (CTBR) clears all bits of the timebase counter to "0" immediately after writing "5AH". Although there is no limit on the length of time
between writing "A5H" and "5AH", if you write a value other than "5AH" after writing "A5H", the
counter is not cleared the next time you write "5AH" unless you first write "A5H" again.
The flag for generating watchdog resets is simultaneously initialized when this time-base counter is
cleared, and generation of watchdog resets will be postponed.
[Clearness of time-base counter by state of device]
The time-base counter is cleared all bits to "0" simultaneously when the device goes to the following
states.
•Stop state
•State of set initialization reset (INIT)
•State of system initialization reset (SINIT)
In particular, under the stop status, the time-base counter is used to measure oscillation stabilization wait
times, so an interval interruption of the time-base timer may be generated unintentionally. Thus, before
setting the stop mode, disable time-base timer interruption, and try not to use the time-base timer.
For statuses other than that, time-base timer interruption is automatically disabled as operation
initialization reset (RST) is generated.
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Note:
Clear the time-base counter immediately before reading standby control register (STCR) after setting
STOP mode bit/SLEEP mode bit, when the mode shifts to sleep mode/stop mode after starting the
watchdog timer. The program example is described as follows;
● Sample program
Standby (stop or sleep) mode shift processing
------------------------------------------------------------------------------------------------------------------// -- Write STCR
LDI
#_STCR,R0
// STCR register (0481H)
LDI
#value_of_standby, R1
// value_of_standby is a write data to STCR
STB
R1,@R0
// Write to STCR
// -- Write CTBR
LDI
#_CTBR,R2
// CTBR register (0483H)
LDI
#0xA5,R1
// Clear command (1)
STB
R1,@R2
// Write A5H to CTBR
LDI
#0x5A,R1
// Clear command (2)
STB
R1,@R2
// Write 5AH to CTBR (time-base counter clear)
LDUB
@R0,R1
// Read STCR (Start the synchronous stand-by shifting)
LDUB
@R0,R1
// Read dummy STCR
NOP
// NOP  5 for adjust timing
NOP
NOP
NOP
NOP
-------------------------------------------------------------------------------------------------------------------
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3.12 Device State Control
MB91490 Series
3.12
Device State Control
This section describes the various device states and how these are controlled.
■ State of Device and Each Transition
The figure below shows the state transitions for this device.
Figure 3.12-1 State of Device and Each Transition
0. INITX pin = 0 (SINIT)
1. INITX pin = 0 or Low voltage detection reset = 0 (SINIT)
2. INITX pin = 1 and Low voltage detection reset = 1 (SINIT)
3. INIT release (transition to 7)
4. INIT release (transition to 2)
5. Oscillation stabilization wait end
6. RST release
7. Watchdog reset (INIT)
Power on
8. Software reset (RST)
9. Stop (instruction write)
10. External interrupts which do not require a clock
0
11. Sleep (instruction write)
12. Interrupt
System initialization reset
(SINIT)
Priority order of transition request
Highest
System initialization reset (SINIT)
Set initialization reset (INIT)
2
Oscillation stabilization wait end
Set initialization reset
(INIT)
Operation initialization reset (RST)
1
Interrupt request
Stop
3
Lowest
Sleep
4
1
Oscillation stabilization
wait reset
Stop
10
1
5
9
1
Operation initialization
reset (RST)
Oscillation stabilization
wait RUN
5
1
6
8
1
Sleep
11
RUN
7
1
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The following has MB91490 series operation states.
● State of RUN (normal operation)
This is the program execution state.
All internal clocks are supplied, and all the circuits are operable.
Each status transition request is accepted, but when synchronous reset mode is selected, the status transition
operation for normal reset mode cases and for some requests is different. See "■ Synchronous Reset
Operation" in Section "3.10.5 Reset Operation Mode" for details.
● Sleep state
The program halts in this state. The device is set to this state by program operation.
Only the program execution of CPU stops, and the circuit in the surrounding is operable. All internal
memory and internal buses halt unless requested by the DMA controller.
The device recovers from this state when a valid interrupt request occurs and goes to the RUN state (normal
operation).
The device changes to the system initialization reset (SINIT) state when a system initialization reset
(SINIT) request occurs.
● Stop state
It is a stopped state of the device. The device is set to this state by program operation.
All internal circuits stop. All internal clocks halt. The oscillation circuit and main PLL can also be set to halt
in this state. Moreover, an external terminal can be made uniform high impedance by setting. (A part of pin
is excluded)
The device changes to the oscillation stabilization wait RUN state when certain interrupt requests occur
(interrupt requests able to be generated while the clock is halted).
The device changes to the system initialization reset (SINIT) state when a system initialization reset
(SINIT) request occurs.
● Oscillation stabilization wait RUN state
It is a stopped state of the device. The device changes to this state after recovering from stop mode.
All internal circuits except the clock generation control unit (time-base counter and device status control
unit) are stopped. All internal clocks halt, but the oscillation circuit and the main PLL (if enabled) continue
to operate.
The high impedance control of an external terminal in the state etc. of the stop is released.
The device goes to the RUN state (normal operation) after the specified oscillation stabilization wait time
elapses.
The device changes to the system initialization reset (SINIT) state when a system initialization reset
(SINIT) request occurs.
● Oscillation stabilization wait reset (RST) state
It is a stopped state of the device. The device goes to this state after recovering from a set initialization reset
(INIT) status.
All internal circuits except the clock generation control unit (time-base counter and device status control
unit) are stopped. All internal clocks halt, but the oscillation circuit continues to operate.
Operation initialization reset (RST) is output to an internal circuit.
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The device goes to the Operation initialization reset (RST) state after the specified oscillation stabilization
wait time elapses.
The device changes to the system initialization reset (SINIT) state when a system initialization reset
(SINIT) request occurs.
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● State of operation initialization reset (RST)
The program is being initialized. Transits by receiving the operation initialization reset (RST) request or
ending the oscillation stabilization wait reset (RST) status.
The program execution of CPU stops, and the program counter is initialized. The circuit in the surrounding
is initialized excluding part. All internal clocks, the oscillation circuit, and the main PLL (if enabled)
operate.
Operation initialization reset (RST) is output to an internal circuit.
Transits to the RUN status (normal operation) by diminishing the operation initialization reset (RST)
request, and operation initialization reset sequence is executed.
The device changes to the system initialization reset (SINIT) state when a system initialization reset
(SINIT) request occurs.
● State of set initialization reset (INIT)
The settings are being initialized. The device changes to this state on receiving a set initialization reset
(INIT) request.
The program execution of CPU stops, and the program counter is initialized. All the circuits in the
surrounding are initialized. The oscillation circuit operates, but the main PLL is halted. All internal clocks
and oscillation circuits operate.
Outputs a set initialization reset (INIT) and operation initialization reset (RST) to internal circuits.
This status is cancelled by diminishing the set initialization reset (INIT) request, and transits to the
oscillation stabilization wait reset (RST) status or the operation initialization reset (RST) status. Then the
operation initialization reset sequence is executed.
● State of system initialization reset (SINIT)
The system settings are being initialized. The device changes to this state on receiving a system
initialization reset (SINIT) request.
The program execution of CPU stops, and the program counter is initialized. All the circuits in the
surrounding are initialized. The oscillation circuit operates, but the main PLL and all internal clocks are
halted.
Outputs a system initialization reset (SINIT), set initialization reset (INIT), and operation initialization reset
(RST) to internal circuits.
This status is canceled by diminishing the system initialization reset (SINIT) request, and transits to the set
initialization reset (INIT) status.
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● Priority level of each state transition demand
In any state, each state transition demand conforms to the following priority levels. However, as certain
requests only occur in specific states, these are only meaningful in those states.
[Highest]
System initialization reset (SINIT) request
Set initialization reset (INIT) request
End of oscillation stabilization wait time (only occurs during oscillation
stabilization wait reset and oscillation stabilization wait RUN states)
Operation initialization reset (RST) demand
The effective interrupt request (Only RUN, the sleep, and the stop states are
generated).
Stop mode demand (register writing) (Only the state of RUN is generated).
[Lowest]
CM71-10155-2E
Sleep mode request (register writing) (Only the state of RUN is generated).
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■ Low-power Consumption Mode
The following describes the low-power consumption modes available on MB91490 series and how to use
them.
MB91490 series has the following low-power consumption modes.
• Sleep mode
The device is set to sleep mode by setting to a register.
• Stop mode
The device is set to stop mode by setting to a register.
The following describes each mode.
● Sleep mode
Writing "1" to bit6: SLEEP bit of standby control register (STCR) sets sleep mode and changes the device
to the sleep state. The device remains in the sleep state until something happens that causes the device to
recover from the sleep state.
See also "■State of Device and Each Transition ●Sleep state" in Section "3.12 Device State Control" for
details about sleep state.
[Transition to sleep mode]
If synchronous standby mode (set using bit8: SYNCS bit of the time-base counter control register
(TBCR)) is used when setting the device to sleep mode, always use the following sequence.
------------------------------------------------------------------------------------------------------------------// -- Write STCR
LDI
#_STCR,R0
// STCR register (0481H)
LDI
#value_of_standby, R1 // value_of_standby is a write data to STCR
STB
R1,@R0
// Write to STCR
// -- Write CTBR
LDI
#_CTBR,R2
// CTBR register (0483H)
LDI
#0xA5,R1
// Clear command (1)
STB
R1,@R2
// Write A5H to CTBR
LDI
#0x5A,R1
// Clear command (2)
STB
R1,@R2
// Write 5AH to CTBR (time-base counter clear)
LDUB
@R0,R1
// Read STCR (Start the synchronous stand-by shifting)
LDUB
@R0,R1
// Read dummy STCR
NOP
// NOP  5 for adjust timing
NOP
NOP
NOP
NOP
------------------------------------------------------------------------------------------------------------------If "1" is written to both this bit and bit7: STOP bit of the standby control register (STCR), bit7: STOP bit
has precedence and the device goes to the stop state.
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[Circuits that halt during sleep state]
• Program execution by the CPU
• Bit search module *
• Various internal memory *
• Internal bus *
*: The circuits operate if DMA transfer occurs.
[Circuits that do not halt during sleep state]
• Oscillation circuit
• Main PLL (if enabled)
• Clock generation control unit
• Interrupt controller
• Peripheral circuit
• DMA controller
• On chip Debug Support Unit (DSU)
[Events that recover the device from sleep state]
• Generation of a valid interrupt request
The device recovers from sleep mode when an interrupt request occurs that is not disabled interrupt
("1111B") in the ICR register and changes to the RUN state (normal operation). In this case, you should
set the I flag in the CPU’s PS register to "1" to enable interrupt acceptance and cause the interrupt
handler to be executed on recovering from sleep mode.
The device does not recover from sleep mode if an interrupt request occurs that is disabled interrupt
("1111B") in the ICR register.
• Generation of a system initialization reset (SINIT) request
The device always goes to the system initialization reset (SINIT) state unconditionally when a system
initialization reset (SINIT) request occurs.
Note: See "■State of Device and Each Transition ●Priority level of each state transition demand" in
Section "3.12 Device State Control" for details of the priority order for the different types of trigger.
[Synchronous standby operation]
Synchronous standby operation is enabled if bit8: SYNCS bit of the time-base counter control register
(TBCR) is set to "1". Transition to the sleep state is not caused only by a write to the SLEEP bit. Then,
transition to the sleep state occurs by reading the STCR register.
To enter the sleep mode, be sure to use the sequence in [Transition to sleep mode].
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Note:
Clear the time-base counter immediately before reading standby control register (STCR) after setting
STOP mode bit/SLEEP mode bit, when the mode shifts to sleep mode/stop mode after starting the
watchdog timer. The program example is described as follows;
● Sample program
Standby (stop or sleep) mode shift processing
------------------------------------------------------------------------------------------------------------------// -- Write STCR
LDI
#_STCR,R0
// STCR register (0481H)
LDI
#value_of_standby, R1
// value_of_standby is a write data to STCR
STB
R1,@R0
// Write to STCR
// -- Write CTBR
LDI
#_CTBR,R2
// CTBR register (0483H)
LDI
#0xA5,R1
// Clear command (1)
STB
R1,@R2
// Write A5H to CTBR
LDI
#0x5A,R1
// Clear command (2)
STB
R1,@R2
// Write 5AH to CTBR (time-base counter clear)
LDUB
@R0,R1
// Read STCR (Start the synchronous stand-by shifting)
LDUB
@R0,R1
// Read dummy STCR
NOP
// NOP  5 for adjust timing
NOP
NOP
NOP
NOP
-------------------------------------------------------------------------------------------------------------------
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● Stop mode
Writing "1" to bit7: STOP bit of the standby control register (STCR) sets stop mode and changes the device
to the stop state. The device remains in the stop state until something happens that causes the device to
recover from the stop state.
See also "■State of Device and Each Transition ●Stop mode" in Section "3.12 Device State Control" for
details about the stop state.
[Transition to stop mode]
If synchronous standby mode (set using bit8: SYNCS bit of the time-base counter control register
(TBCR)) is used when setting the device to stop mode, always use the following sequence.
------------------------------------------------------------------------------------------------------------------// -- Write STCR
// STCR register (0481H)
LDI
#_STCR,R0
LDI
#value_of_standby, R1 // value_of_standby is a write data to STCR
STB
R1,@R0
// Write to STCR
// -- Write CTBR
LDI
#_CTBR,R2
// CTBR register (0483H)
LDI
#0xA5,R1
// Clear command (1)
STB
R1,@R2
// Write A5H to CTBR
LDI
#0x5A,R1
// Clear command (2)
STB
R1,@R2
// Write 5AH to CTBR (time-base counter clear)
LDUB
@R0,R1
// Read STCR (Start the synchronous stand-by shifting)
LDUB
@R0,R1
// Read dummy STCR
NOP
// NOP  5 for adjust timing
NOP
NOP
NOP
NOP
------------------------------------------------------------------------------------------------------------------If "1" is written to both this bit and bit6: SLEEP bit of the standby control register (STCR), bit7: STOP
bit has precedence and the device goes to the stop state.
[Circuits that halt during stop state]
All circuits halt except the following.
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[Circuits that do not halt during stop state]
• Oscillation circuits that are not set to halt
The oscillation circuit for the main clock does not halt during the stop state if bit0: OSCD1 bit in standby
control register (STCR) is set to "0".
• Main PLL if enabled and if connected to an oscillation circuit that is not set to halt
The PLL for the main clock does not halt during the stop state if bit0: OSCD1 bit in standby control
register (STCR) is set to "0" and bit10: PLL1EN bit of the clock source control register (CLKR) is set to
"1".
[Pin high-impedance control during the stop state]
Pin outputs go to the high-impedance state during the stop state if bit5: HIZ bit of the standby control
register (STCR) is set to "1". The pins to which this control applies are listed in "APPENDIX C Pin
States in Each CPU State".
If bit5: HIZ bit of the standby control register (STCR) is set to "0" during the stop state, pin outputs
maintain the values they had prior to the device changing to the stop state. For details, refer to
"APPENDIX C Pin States in Each CPU State".
[Events that recover the device from stop mode]
• Generation of certain valid interrupt requests (clock is not required).
Only some enabled external interrupt and the NMI input pin are valid.
The device recovers from stop mode when an interrupt request occurs that is not disabled interrupt
("1111B") in the ICR register and changes to the oscillation stabilization wait RUN state. In this case,
you should set the I flag in the CPU’s PS register to "1" to enable acceptance of interrupts and cause the
interrupt handler to be executed on recovering from stop mode.
The device does not recover from stop mode if an interrupt request occurs that is disabled interrupt
("1111B") in the ICR register.
• Generation of a system initialization reset (SINIT) request
The device always goes to the system initialization reset (SINIT) state unconditionally when a system
initialization reset (SINIT) request occurs.
Note: See "■State of Device and Each Transition ●Priority level of each state transition demand" in
Section "3.12 Device State Control" for details of the priority order for the different types of
trigger.
[Source clock selection in stop mode]
Always set the clock source to the main clock divided by two before setting stop mode. See Section "3.11
Clock Generation Control", particularly Section "3.11.2 PLL Control" for details.
The same restrictions as in normal operation apply to the setting of the divide ratio.
[Synchronous standby operation]
Synchronous standby operation is enabled if bit8: SYNCS bit of the time-base counter control register
(TBCR) is set to "1". In this case, simply writing to the STOP bit will not change the device to the stop
state. Then, transition to the stop state occurs by reading the STCR register.
When using stop mode, always use the sequence described in [Transition to stop mode].
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3.12 Device State Control
MB91490 Series
Note:
Clear the time-base counter immediately before reading standby control register (STCR) after setting
STOP mode bit/SLEEP mode bit, when the mode shifts to sleep mode/stop mode after starting the
watchdog timer. The program example is described as follows;
● Sample program
Standby (stop or sleep) mode shift processing
------------------------------------------------------------------------------------------------------------------// -- Write STCR
LDI
#_STCR,R0
// STCR register (0481H)
LDI
#value_of_standby, R1
// value_of_standby is a write data to STCR
STB
R1,@R0
// Write to STCR
// -- Write CTBR
LDI
#_CTBR,R2
// CTBR register (0483H)
LDI
#0xA5,R1
// Clear command (1)
STB
R1,@R2
// Write A5H to CTBR
LDI
#0x5A,R1
// Clear command (2)
STB
R1,@R2
// Write 5AH to CTBR (time-base counter clear)
LDUB
@R0,R1
// Read STCR (Start the synchronous stand-by shifting)
LDUB
@R0,R1
// Read dummy STCR
NOP
// NOP  5 for adjust timing
NOP
NOP
NOP
NOP
-------------------------------------------------------------------------------------------------------------------
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CHAPTER 3 CPU AND CONTROL UNIT
3.12 Device State Control
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CM71-10155-2E
CHAPTER 4
I/O PORTS
This chapter outlines the I/O ports and describes the
configuration and functions of their registers.
4.1 Overview of I/O Port
4.2 Block Diagrams of I/O Port
4.3 I/O Port Registers
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CHAPTER 4 I/O PORTS
4.1 Overview of I/O Port
4.1
MB91490 Series
Overview of I/O Port
This section describes the I/O ports used in the MB91490 series.
■ Overview of Ports
MB91490 series can use its pins as I/O ports when they are set not to serve for input to or output from their
respective peripherals.
■ Configuration
The control section of the port comprises the following four registers:
● PFR: Port Function Register
This setup register switches the function of a pin to be used between a peripheral output and a generalpurpose port.
● DDR: Data Direction Register
This setup register switches the direction of data between input and output, when the pin is used as a
general-purpose port.
● PDR: Port Data Register
This register is used to set data.
● PCR: Pull-up Control Register
This setup register is used to enable the pull-up function.
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4.2 Block Diagrams of I/O Port
MB91490 Series
4.2
Block Diagrams of I/O Port
This section describes block diagrams of I/O ports.
■ Block Diagrams of Ports
In MB91490 series, four types of ports are available, depending on peripheral that is also used as the
general-purpose port.
● Normal I/O port
This dual-function I/O port has the most basic configuration and also serves as a peripheral input/output. It
is composed of PFR, DDR, PDR and PCR.
● External interrupt input I/O port
This I/O port also serves as an external interrupt input and comprises PFR, DDR, PDR, PCR and an
external interrupt input enabling signal.
● Analog input I/O port
This I/O port also functions as an analog input and comprises PFR, DDR, PDR, PCR and an analog input
enabling signal.
● Multi-function timer I/O port
This I/O port also functions as waveform generator output of a multi-function timer (RTO0 to RTO5) and
comprises PFR, DDR, PDR, PCR, and a DTTI interrupt flag signal. See Section "11.4.13 Waveform
Control Register (SIGCR1/SIGCR2)" for details of the DTTI interrupt flag.
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CHAPTER 4 I/O PORTS
4.2 Block Diagrams of I/O Port
4.2.1
MB91490 Series
Normal I/O Port
This section describes the block diagram of the normal I/O port.
■ Block Diagram of Normal I/O Port
Figure 4.2-1 Block Diagram of Normal I/O Port
R-bus
PCR = 0: No pull-up resistor
PCR = 1: Pull-up resistor provided
INITX
STOPHIZ
PCR
1
Pull-up resistor
(About 50 kΩ)
0
(Pull-up Control Register)
Peripheral output 1
Pin
PDR
0
(Port Data Register)
INITX
STOPHIZ
PFR
(Port Function Register)
DDR
(Data Direction Register)
Read-modify-write (RMW) system instruction
1
0
PDR read
STOPHIZ
Peripheral input
INITX: External INITX input or Low voltage detection reset ("L"-active)
STOPHIZ: STOP mode control signal (Output = "Hi-Z" mode)
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4.2 Block Diagrams of I/O Port
MB91490 Series
■ Modes of I/O Port
● In port input mode (PFR=0 & DDR=0)
PDR read:
The level at the corresponding external pin is read.
PDR read modify write (RMW) system instruction: The PDR value is read.
PDR write
A setting value is written to the PDR.
● In port output mode (PFR=0 & DDR=1)
PDR read:
The PDR value is read.
PDR read modify write (RMW) system instruction: The PDR value is read.
PDR write:
The PDR value is output to the corresponding external
pin.
● In peripheral output mode 1 (PFR=1 & DDR=0)
PDR read:
The output value from the corresponding peripheral is
read.
PDR read modify write (RMW) system instruction: The PDR value is read.
PDR write:
A setting value is written to the PDR.
● In peripheral output mode 2 (PFR=1 & DDR=1)
PDR read:
The PDR value is read.
PDR read modify write (RMW) system instruction: The PDR value is read.
PDR write:
A setting value is written to the PDR.
■ Setting Value in Pull-up Resistor Control Register
In the following modes, the setting in the pull-up resistor control register is invalid.
• When external INITX input or low voltage detection reset is active (when "L" is selected for input)
• When STOP mode is selected (HIZ=1)
• When peripheral output mode is selected (PFR=1)
• When port output mode is selected (DDR=1)
In any mode other than the above, the setting in the pull-up resistor control register has priority.
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CHAPTER 4 I/O PORTS
4.2 Block Diagrams of I/O Port
4.2.2
MB91490 Series
External Interrupt Input I/O Port
This section describes the block diagram of the external interrupt input I/O port.
■ Block Diagram of External Interrupt Input I/O Port
Figure 4.2-2 Block Diagram of External Interrupt Input I/O Port
R-bus
PCR = 0: No pull-up resistor
PCR = 1: Pull-up resistor provided
INITX
STOPHIZ
PCR
1
Pull-up resistor
(About 50 kΩ)
0
(Pull-up Control Register)
Peripheral output 1
Pin
PDR
0
(Port Data Register)
INITX
STOPHIZ
PFR
(Port Function Register)
DDR
(Data Direction Register)
Read-modify-write (RMW) instruction
1
STOPHIZ
0
PDR read
Peripheral input
INTnEN
INITX: External INITX input or Low voltage detection reset ("L"-active)
STOPHIZ: STOP mode control signal (Output = "Hi-Z" mode)
INTnEN: External interrupt enabling signal
(when external interrupt is enabled: "1")
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4.2 Block Diagrams of I/O Port
MB91490 Series
■ Modes of I/O Port
Same as the normal I/O port
■ Setting Value in Pull-up Resistor Control Register
Same as the normal I/O port
■ Controlling the Enabling of Input
While the normal I/O port has its input fixed to "L" in STOP mode (HIZ=1), this dual-function port has the
respective port enabled to be input even in STOP mode (HIZ=1), when external interrupt input is enabled
(INTnEN=1).
Note:
When external interrupt input is enabled in STOP mode (HIZ=1), the respective port can be input but
the setting in the pull-up resistor control register is invalid.
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CHAPTER 4 I/O PORTS
4.2 Block Diagrams of I/O Port
4.2.3
MB91490 Series
Analog Input I/O Port
This section describes the block diagram of the analog input I/O port.
■ Block Diagram of Analog Input I/O Port
Figure 4.2-3 Block Diagram of Analog Input I/O Port
R-bus
PCR = 0: No pull-up resistor
PCR = 1: Pull-up resistor provided
INITX
STOPHIZ
Pull-up resistor
(About 50 kΩ)
PCR
1
0
(Pull-up Control Register)
Peripheral output 1
Pin
PDR
0
(Port Data Register)
INITX
STOPHIZ
ANINnEN
PFR
(Port Function Register)
Analog input
DDR
(Data Direction Register)
Read-modify-write (RMW) instruction
1
0
PDR read
Peripheral input
STOPHIZ
ANINnEN
INITX: External INITX input or Low voltage detection reset ("L"-active)
STOPHIZ: STOP mode control signal (Output = "Hi-Z" mode)
ANINnEN: A/D analog input enabling signal
(when analog input is enabled: "1")
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4.2 Block Diagrams of I/O Port
MB91490 Series
■ Modes of I/O Port
In any mode other than analog input mode (ANINnEN=0), the same specifications as for the normal I/O
port apply. In analog input mode (ANINnEN=1), however, the specifications below are followed.
● In port input mode (DDR=0)
PDR read:
"0" is always read.
PDR read modify write (RMW) system instruction: The PDR value is read.
PDR write:
A setting value is written to the PDR.
● In port output mode (DDR=1)
PDR read:
The PDR value is read.
PDR read modify write (RMW) system instruction: The PDR value is read.
PDR write:
The PDR value is output to the corresponding external
pin.
■ Setting Value in Pull-up Resistor Control Register
Same as the normal I/O port
■ Controlling the Enabling of Input
While the normal I/O port has its input fixed to "L" in STOP mode (HIZ=1), this dual-function port also
has its input fixed to "L" even in analog input mode (ANINnEN=1).
Note:
The setting in the pull-up resistor control register is valid even in analog input mode (ANINnEN=1).
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CHAPTER 4 I/O PORTS
4.2 Block Diagrams of I/O Port
4.2.4
MB91490 Series
Multi-Function Timer I/O Port
This section describes the block diagram of the multi-function timer I/O port.
■ Block Diagram of Multi-Function Timer I/O Port
Figure 4.2-4 Block Diagram of Multi-Function Timer I/O Port
R-bus
PCR = 0: No pull-up resistor
PCR = 1: Pull-up resistor provided
INITX
STOPHIZ
PCR
Pull-up resistor
(About 50 kΩ)
1
0
(Pull-up Control Register)
Waveform generator output 1
Pin
PDR
0
(Port Data Register)
INITX
STOPHIZ
DTIF
PFR
(Port Function Register)
DDR
(Data Direction Register)
Read-modify-write (RMW) instruction
1
0
PDR read
STOPHIZ
External bus interface input
INITX: External INITX input or Low voltage detection reset ("L"-active)
STOPHIZ: STOP mode control signal (Output = "Hi-Z" mode)
DTIF: DTTI interrupt flag, “1” when an interrupt occurs
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4.2 Block Diagrams of I/O Port
MB91490 Series
■ Modes of I/O Port
● In port input mode (DTIF=1 & DDR=0, or, DTIF=0 & PFR=0 & DDR=0)
PDR read:
The level at the corresponding external pin is read.
PDR read modify write (RMW) system instruction: The PDR value is read.
PDR write:
A setting value is written to the PDR.
● In port output mode(DTIF=1 & DDR=1, or, DTIF=0 & PFR=0 & DDR=1)
PDR read:
The PDR value is read.
PDR read modify write (RMW) system instruction: The PDR value is read.
PDR write:
A setting value is written to the PDR.
● In waveform generator output mode 1 (DTIF=0 & PFR=1 & DDR=0)
PDR read:
The value of the waveform generator output is read.
PDR read modify write (RMW) system instruction: The PDR value is read.
PDR write:
A setting value is written to the PDR.
● In waveform generator output mode 2 (DTIF=0 & PFR=1 & DDR=1)
PDR read:
The PDR value is read.
PDR read modify write (RMW) system instruction: The PDR value is read.
PDR write:
A setting value is written to the PDR.
■ Setting Value in Pull-up Resistor Control Register
In the following modes, the setting in the pull-up resistor control register is invalid.
• When external INITX input or low voltage detection reset is active (when "L" is selected for input)
• When STOP mode is selected (HIZ=1)
• When port output mode is selected (DDR=1)
• When waveform generator output mode is selected (DTIF=0 & PFR=1)
Otherwise, the setting in the pull-up resistor control register has priority.
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CHAPTER 4 I/O PORTS
4.3 I/O Port Registers
4.3
MB91490 Series
I/O Port Registers
This section explains registers of I/O port.
■ Port Data Registers (PDR)
PDR8
Address
00000006H
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-
P86
P85
P84
P83
P82
P81
P80
- XXXXXXXB
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-
-
-
-
-
PA2
PA1
-
- - - - - XX- B
-
-
-
-
-
R/W
R/W
-
PDRA
Address
00000008H
PDRB
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
00000009H
PB7
PB6
PB5
PB4
-
-
-
-
R/W
R/W
R/W
R/W
-
-
-
-
Initial value
XXXX- - - - B
PDRC
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
0000000AH
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-
-
PG5
PG4
PG3
PG2
PG1
PG0
- - XXXXXXB
-
-
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-
-
-
-
-
PH2
PH1
PH0
- - - - - XXXB
-
-
-
-
-
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-
-
-
-
PJ3
PJ2
PJ1
PJ0
- - - - XXXXB
-
-
-
-
R/W
R/W
R/W
R/W
PDRG
Address
0000000EH
PDRH
Address
0000000FH
PDRJ
Address
00000010H
(Continued)
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4.3 I/O Port Registers
MB91490 Series
(Continued)
PDRL
Address
00000012H
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-
-
-
-
-
PL2
PL1
PL0
- - - - - XXXB
-
-
-
-
-
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-
-
PP5
PP4
PP3
PP2
PP1
PP0
- - XXXXXXB
-
-
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-
-
PQ5
PQ4
PQ3
PQ2
PQ1
PQ0
- - XXXXXXB
-
-
R/W
R/W
R/W
R/W
R/W
R/W
PDRP
Address
00000014H
PDRQ
Address
00000015H
R/W: Readable/writable
-:
Undefined bit
PDR is I/O data register of the I/O port. This is controlled for input/output by the corresponding DDR and
PFR.
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4.3 I/O Port Registers
MB91490 Series
■ Data Direction Registers (DDR)
DDR8
Address
00000406H
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
- 0000000B
-
P86
P85
P84
P83
P82
P81
P80
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-
-
-
-
-
PA2
PA1
-
- - - - - 00- B
-
-
-
-
-
R/W
R/W
-
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
0000- - - - B
DDRA
Address
00000408H
DDRB
Address
PB7
PB6
PB5
PB4
-
-
-
-
R/W
R/W
R/W
R/W
-
-
-
-
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
0000040AH
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-
-
PG5
PG4
PG3
PG2
PG1
PG0
- - 000000B
-
-
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-
-
-
-
-
PH2
PH1
PH0
- - - - - 000B
-
-
-
-
-
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-
-
-
-
PJ3
PJ2
PJ1
PJ0
- - - - 0000B
-
-
-
-
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-
-
-
-
-
PL2
PL1
PL0
- - - - - 000B
-
-
-
-
-
R/W
R/W
R/W
00000409H
DDRC
DDRG
Address
0000040EH
DDRH
Address
0000040FH
DDRJ
Address
00000410H
DDRL
Address
00000412H
(Continued)
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4.3 I/O Port Registers
MB91490 Series
(Continued)
DDRP
Address
00000414H
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-
-
PP5
PP4
PP3
PP2
-
-
R/W
R/W
R/W
R/W
PP1
PP0
- - 000000B
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-
-
PQ5
PQ4
PQ3
PQ2
PQ1
PQ0
- - 000000B
-
-
R/W
R/W
R/W
R/W
R/W
R/W
DDRQ
Address
00000415H
R/W: Readable/writable
-:
Undefined bit
DDR controls the I/O direction of the corresponding I/O port for each bit.
When PFR = 0
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DDR = 0: Port input
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MB91490 Series
■ Pull-up Control Registers (PCR)
PCR8
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-
P86
P85
P84
P83
P82
P81
P80
- 0000000B
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-
-
-
-
-
PA2
PA1
-
- - - - - 00- B
-
-
-
-
-
R/W
R/W
-
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
00000609H
PB7
PB6
PB5
PB4
-
-
-
-
0000- - - - B
R/W
R/W
R/W
R/W
-
-
-
-
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
0000060AH
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-
-
PG5
PG4
PG3
PG2
PG1
PG0
- - 000000B
-
-
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-
-
-
-
-
PH2
PH1
PH0
- - - - - 000B
-
-
-
-
-
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-
-
-
-
PJ3
PJ2
PJ1
PJ0
- - - - 0000B
-
-
-
-
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-
-
-
-
-
PL2
PL1
PL0
- - - - - 000B
-
-
-
-
-
R/W
R/W
R/W
00000606H
PCRA
Address
00000608H
PCRB
PCRC
PCRG
Address
0000060EH
PCRH
Address
0000060FH
PCRJ
Address
00000610H
PCRL
Address
00000612H
(Continued)
124
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CM71-10155-2E
CHAPTER 4 I/O PORTS
4.3 I/O Port Registers
MB91490 Series
(Continued)
PCRP
Address
00000614H
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-
-
PP5
PP4
PP3
PP2
PP1
PP0
- - 000000B
-
-
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-
-
PQ5
PQ4
PQ3
PQ2
PQ1
PQ0
- - 000000B
-
-
R/W
R/W
R/W
R/W
R/W
R/W
PCRQ
Address
00000615H
R/W: Readable/writable
-:
Undefined bit
PCR controls the pull-up resistor for the corresponding I/O port.
PCR = 0: No pull-up resistor
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CHAPTER 4 I/O PORTS
4.3 I/O Port Registers
MB91490 Series
■ Port Function Control Registers (PFR)
PFR8
Address
00000426H
bit7
-
bit6
bit5
bit4
PPG6E PPG5E PPG4E
bit3
bit2
bit1
bit0
Initial value
- 000- - - - B
-
-
-
-
-
R/W
R/W
R/W
-
-
-
-
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
-
-
SOT1E
-
-
-
R/W
-
R/W
R/W
-
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
-
-
-
-
-
SOT2E
-
-
-
-
-
-
R/W
-
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-
-
-
-
TOUT1E
-
TOUT0E
-
- - - - 0- 0- B
-
-
-
-
R/W
-
R/W
-
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
-
-
-
-
PFRG
Address
0000042EH
SCK1E SOT0E
-
Initial value
SCK0E - - 0- 00- 0B
PFRH
Address
0000042FH
Initial value
SCK2E - - - - - 0- 0B
PFRJ
Address
00000430H
PFRQ
Address
00000435H
Initial value
RTO5E RTO4E RTO3E RTO2E RTO1E RTO0E - - 000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Readable/writable
-:
Undefined bit
PFR controls each bit in the output of the corresponding peripheral.
Be sure to write "0" to undefined bits.
126
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CM71-10155-2E
CHAPTER 4 I/O PORTS
4.3 I/O Port Registers
MB91490 Series
The following table lists individual PFR registers, their initial values and functions:
Table 4.3-1 Initial Value and Function of PFR Register
Register Name
PFR8
Bit
Bit Name
4
PPG4E
5
PPG5E
6
PPG6E
0
SCK0E
2
SOT0E
3
SCK1E
5
SOT1E
0
SCK2E
2
SOT2E
1
TOUT0E
3
TOUT1E
0
RTO0E
1
RTO1E
2
RTO2E
3
RTO3E
4
RTO4E
5
RTO5E
PFRG
PFRH
PFRJ
PFRQ
CM71-10155-2E
Setting value
Function
0
General-purpose port
1
Outputs PPG timer 4
0
General-purpose port
1
Outputs PPG timer 5
0
General-purpose port
1
Outputs PPG timer 6
0
General-purpose port
1
Outputs clock for multi-function serial interface0
0
General-purpose port
1
Outputs data for multi-function serial interface0
0
General-purpose port
1
Outputs clock for multi-function serial interface1
0
General-purpose port
1
Outputs data for multi-function serial interface1
0
General-purpose port
1
Outputs clock for multi-function serial interface2
0
General-purpose port
1
Outputs data for multi-function serial interface2
0
General-purpose port
1
Outputs data for base timer 0
0
General-purpose port
1
Outputs data for base timer 1
0
General-purpose port
1
Outputs waveform 0 of waveform generator 0
0
General-purpose port
1
Outputs waveform 1 of waveform generator 0
0
General-purpose port
1
Outputs waveform 2 of waveform generator 0
0
General-purpose port
1
Outputs waveform 3 of waveform generator 0
0
General-purpose port
1
Outputs waveform 4 of waveform generator 0
0
General-purpose port
1
Outputs waveform 5 of waveform generator 0
FUJITSU SEMICONDUCTOR LIMITED
[Initial value]
[Initial value]
[Initial value]
[Initial value]
[Initial value]
[Initial value]
[Initial value]
[Initial value]
[Initial value]
[Initial value]
[Initial value]
[Initial value]
[Initial value]
[Initial value]
[Initial value]
[Initial value]
[Initial value]
127
CHAPTER 4 I/O PORTS
4.3 I/O Port Registers
MB91490 Series
Notes:
• PPG are also used as INT4 to INT6, external interrupts. Therefore, make sure to disable the
corresponding external interrupt input before setting the respective PFR8, when enabling PPG to
be output.
• The settings in PFRQ is invalid when the DTIF (DTTI interrupt flag) in the waveform generator 0 is
"1", and the respective ports are always used as general-purpose ports.
128
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
CHAPTER 5
INTERRUPT CONTROLLER
This chapter explains the overview of the interrupt
controller, the configuration and functions of registers,
and interrupt controller operation.
5.1 Overview of Interrupt Controller
5.2 Interrupt Controller Registers
5.3 Block Diagram of Interrupt Controller
5.4 Register Details Explanation of Interrupt Controller
5.5 Operation of Interrupt Controller
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CHAPTER 5 INTERRUPT CONTROLLER
5.1 Overview of Interrupt Controller
5.1
MB91490 Series
Overview of Interrupt Controller
The interrupt controller manages interrupt reception and arbitration processing.
■ Hardware Configuration of the Interrupt Controller
The interrupt controller consists of the following register and circuit.
• ICR register
• Interrupt priority judgment circuit
• Interrupt level and interrupt number (vector) generation unit
• Unit for generating HOLD request cancel requests
■ Major Functions
The main functions of this module are as follows.
• Detection of NMI requests and interrupt requests
• Judgment of priorities (based on interrupt level and number)
• Pass the interrupt level for the interrupt selected by judgment result (to the CPU)
• Pass the interrupt number for the interrupt selected by judgment result (to the CPU)
• Send a stop mode recovery notification (to the CPU) if an NMI or interrupt with a level other than
"11111B" occurs.
• Generates the HOLD request cancel request to the DMAC.
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CM71-10155-2E
CHAPTER 5 INTERRUPT CONTROLLER
5.2 Interrupt Controller Registers
MB91490 Series
5.2
Interrupt Controller Registers
Figure 5.2-1 shows the interrupt controller registers.
■ Interrupt Controller Registers
Figure 5.2-1 Interrupt Controller Registers
ICR00
Address:
00000440H
bit7
-
bit6
-
bit5
-
bit4
ICR4
R
bit3
ICR3
R/W
bit2
ICR2
R/W
bit1
ICR1
R/W
bit0
ICR0
R/W
Initial value
---11111B
bit7
-
bit6
-
bit5
-
bit4
ICR4
R
bit3
ICR3
R/W
bit2
ICR2
R/W
bit1
ICR1
R/W
bit0
ICR0
R/W
Initial value
---11111B
bit7
-
bit6
-
bit5
-
bit4
ICR4
R
bit3
ICR3
R/W
bit2
ICR2
R/W
bit1
ICR1
R/W
bit0
ICR0
R/W
Initial value
---11111B
bit7
-
bit6
-
bit5
-
bit4
ICR4
R
bit3
ICR3
R/W
bit2
ICR2
R/W
bit1
ICR1
R/W
bit0
ICR0
R/W
Initial value
---11111B
bit7
-
bit6
-
bit5
-
bit4
ICR4
R
bit3
ICR3
R/W
bit2
ICR2
R/W
bit1
ICR1
R/W
bit0
ICR0
R/W
Initial value
---11111B
bit7
-
bit6
-
bit5
-
bit4
ICR4
R
bit3
ICR3
R/W
bit2
ICR2
R/W
bit1
ICR1
R/W
bit0
ICR0
R/W
Initial value
---11111B
bit7
-
bit6
-
bit5
-
bit4
ICR4
R
bit3
ICR3
R/W
bit2
ICR2
R/W
bit1
ICR1
R/W
bit0
ICR0
R/W
Initial value
---11111B
bit7
-
bit6
-
bit5
-
bit4
ICR4
R
bit3
ICR3
R/W
bit2
ICR2
R/W
bit1
ICR1
R/W
bit0
ICR0
R/W
Initial value
---11111B
bit7
-
bit6
-
bit5
-
bit4
ICR4
R
bit3
ICR3
R/W
bit2
ICR2
R/W
bit1
ICR1
R/W
bit0
ICR0
R/W
Initial value
---11111B
bit7
-
bit6
-
bit5
-
bit4
ICR4
R
bit3
ICR3
R/W
bit2
ICR2
R/W
bit1
ICR1
R/W
bit0
ICR0
R/W
Initial value
---11111B
bit7
-
bit6
-
bit5
-
bit4
ICR4
R
bit3
ICR3
R/W
bit2
ICR2
R/W
bit1
ICR1
R/W
bit0
ICR0
R/W
Initial value
---11111B
ICR01
Address:
00000441H
ICR02
Address:
00000442H
ICR03
Address:
00000443H
ICR04
Address:
00000444H
ICR05
Address:
00000445H
ICR06
Address:
00000446H
ICR07
Address:
00000447H
ICR08
Address:
00000448H
ICR09
Address:
00000449H
ICR10
Address:
0000044AH
(Continued)
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131
CHAPTER 5 INTERRUPT CONTROLLER
5.2 Interrupt Controller Registers
MB91490 Series
(Continued)
ICR11
Address:
0000044BH
bit7
-
bit6
-
bit5
-
bit4
ICR4
R
bit3
ICR3
R/W
bit2
ICR2
R/W
bit1
ICR1
R/W
bit0
ICR0
R/W
Initial value
---11111B
bit7
-
bit6
-
bit5
-
bit4
ICR4
R
bit3
ICR3
R/W
bit2
ICR2
R/W
bit1
ICR1
R/W
bit0
ICR0
R/W
Initial value
---11111B
bit7
-
bit6
-
bit5
-
bit4
ICR4
R
bit3
ICR3
R/W
bit2
ICR2
R/W
bit1
ICR1
R/W
bit0
ICR0
R/W
Initial value
---11111B
bit7
-
bit6
-
bit5
-
bit4
ICR4
R
bit3
ICR3
R/W
bit2
ICR2
R/W
bit1
ICR1
R/W
bit0
ICR0
R/W
Initial value
---11111B
bit7
-
bit6
-
bit5
-
bit4
ICR4
R
bit3
ICR3
R/W
bit2
ICR2
R/W
bit1
ICR1
R/W
bit0
ICR0
R/W
Initial value
---11111B
bit7
-
bit6
-
bit5
-
bit4
ICR4
R
bit3
ICR3
R/W
bit2
ICR2
R/W
bit1
ICR1
R/W
bit0
ICR0
R/W
Initial value
---11111B
bit7
-
bit6
-
bit5
-
bit4
ICR4
R
bit3
ICR3
R/W
bit2
ICR2
R/W
bit1
ICR1
R/W
bit0
ICR0
R/W
Initial value
---11111B
bit7
-
bit6
-
bit5
-
bit4
ICR4
R
bit3
ICR3
R/W
bit2
ICR2
R/W
bit1
ICR1
R/W
bit0
ICR0
R/W
Initial value
---11111B
bit7
-
bit6
-
bit5
-
bit4
ICR4
R
bit3
ICR3
R/W
bit2
ICR2
R/W
bit1
ICR1
R/W
bit0
ICR0
R/W
Initial value
---11111B
bit7
-
bit6
-
bit5
-
bit4
ICR4
R
bit3
ICR3
R/W
bit2
ICR2
R/W
bit1
ICR1
R/W
bit0
ICR0
R/W
Initial value
---11111B
bit7
-
bit6
-
bit5
-
bit4
ICR4
R
bit3
ICR3
R/W
bit2
ICR2
R/W
bit1
ICR1
R/W
bit0
ICR0
R/W
Initial value
---11111B
bit7
-
bit6
-
bit5
-
bit4
ICR4
R
bit3
ICR3
R/W
bit2
ICR2
R/W
bit1
ICR1
R/W
bit0
ICR0
R/W
Initial value
---11111B
bit7
-
bit6
-
bit5
-
bit4
ICR4
R
bit3
ICR3
R/W
bit2
ICR2
R/W
bit1
ICR1
R/W
bit0
ICR0
R/W
Initial value
---11111B
ICR12
Address:
0000044CH
ICR13
Address:
0000044DH
ICR14
Address:
0000044EH
ICR15
Address:
0000044FH
ICR16
Address:
00000450H
ICR17
Address:
00000451H
ICR18
Address:
00000452H
ICR19
Address:
00000453H
ICR24
Address:
00000458H
ICR25
Address:
00000459H
ICR26
Address:
0000045AH
ICR27
Address:
0000045BH
(Continued)
132
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CM71-10155-2E
CHAPTER 5 INTERRUPT CONTROLLER
5.2 Interrupt Controller Registers
MB91490 Series
(Continued)
ICR28
Address:
0000045CH
bit7
-
bit6
-
bit5
-
bit4
ICR4
R
bit3
ICR3
R/W
bit2
ICR2
R/W
bit1
ICR1
R/W
bit0
ICR0
R/W
Initial value
---11111B
bit7
-
bit6
-
bit5
-
bit4
ICR4
R
bit3
ICR3
R/W
bit2
ICR2
R/W
bit1
ICR1
R/W
bit0
ICR0
R/W
Initial value
---11111B
bit7
-
bit6
-
bit5
-
bit4
ICR4
R
bit3
ICR3
R/W
bit2
ICR2
R/W
bit1
ICR1
R/W
bit0
ICR0
R/W
Initial value
---11111B
bit7
-
bit6
-
bit5
-
bit4
ICR4
R
bit3
ICR3
R/W
bit2
ICR2
R/W
bit1
ICR1
R/W
bit0
ICR0
R/W
Initial value
---11111B
bit7
-
bit6
-
bit5
-
bit4
ICR4
R
bit3
ICR3
R/W
bit2
ICR2
R/W
bit1
ICR1
R/W
bit0
ICR0
R/W
Initial value
---11111B
bit7
-
bit6
-
bit5
-
bit4
ICR4
R
bit3
ICR3
R/W
bit2
ICR2
R/W
bit1
ICR1
R/W
bit0
ICR0
R/W
Initial value
---11111B
bit7
-
bit6
-
bit5
-
bit4
ICR4
R
bit3
ICR3
R/W
bit2
ICR2
R/W
bit1
ICR1
R/W
bit0
ICR0
R/W
Initial value
---11111B
bit7
-
bit6
-
bit5
-
bit4
ICR4
R
bit3
ICR3
R/W
bit2
ICR2
R/W
bit1
ICR1
R/W
bit0
ICR0
R/W
Initial value
---11111B
bit7
-
bit6
-
bit5
-
bit4
ICR4
R
bit3
ICR3
R/W
bit2
ICR2
R/W
bit1
ICR1
R/W
bit0
ICR0
R/W
Initial value
---11111B
bit7
-
bit6
-
bit5
-
bit4
ICR4
R
bit3
ICR3
R/W
bit2
ICR2
R/W
bit1
ICR1
R/W
bit0
ICR0
R/W
Initial value
---11111B
bit7
-
bit6
-
bit5
-
bit4
ICR4
R
bit3
ICR3
R/W
bit2
ICR2
R/W
bit1
ICR1
R/W
bit0
ICR0
R/W
Initial value
---11111B
bit7
-
bit6
-
bit5
-
bit4
ICR4
R
bit3
ICR3
R/W
bit2
ICR2
R/W
bit1
ICR1
R/W
bit0
ICR0
R/W
Initial value
---11111B
bit7
-
bit6
-
bit5
-
bit4
ICR4
R
bit3
ICR3
R/W
bit2
ICR2
R/W
bit1
ICR1
R/W
bit0
ICR0
R/W
Initial value
---11111B
ICR29
Address:
0000045DH
ICR30
Address:
0000045EH
ICR31
Address:
0000045FH
ICR33
Address:
00000461H
ICR34
Address:
00000462H
ICR35
Address:
00000463H
ICR36
Address:
00000464H
ICR37
Address:
00000465H
ICR38
Address:
00000466H
ICR39
Address:
00000467H
ICR41
Address:
00000469H
ICR42
Address:
0000046AH
(Continued)
CM71-10155-2E
FUJITSU SEMICONDUCTOR LIMITED
133
CHAPTER 5 INTERRUPT CONTROLLER
5.2 Interrupt Controller Registers
MB91490 Series
(Continued)
ICR43
Address:
0000046BH
bit7
-
bit6
-
bit5
-
bit4
ICR4
R
bit3
ICR3
R/W
bit2
ICR2
R/W
bit1
ICR1
R/W
bit0
ICR0
R/W
Initial value
---11111B
bit7
-
bit6
-
bit5
-
bit4
ICR4
R
bit3
ICR3
R/W
bit2
ICR2
R/W
bit1
ICR1
R/W
bit0
ICR0
R/W
Initial value
---11111B
bit7
-
bit6
-
bit5
-
bit4
ICR4
R
bit3
ICR3
R/W
bit2
ICR2
R/W
bit1
ICR1
R/W
bit0
ICR0
R/W
Initial value
---11111B
bit7
-
bit6
-
bit5
-
bit4
ICR4
R
bit3
ICR3
R/W
bit2
ICR2
R/W
bit1
ICR1
R/W
bit0
ICR0
R/W
Initial value
---11111B
bit7
-
bit6
-
bit5
-
bit4
ICR4
R
bit3
ICR3
R/W
bit2
ICR2
R/W
bit1
ICR1
R/W
bit0
ICR0
R/W
Initial value
---11111B
bit7
bit6
-
bit5
-
bit4
LVL4
R
bit3
LVL3
R/W
bit2
LVL2
R/W
bit1
LVL1
R/W
bit0
LVL0
R/W
Initial value
0--11111B
ICR44
Address:
0000046CH
ICR45
Address:
0000046DH
ICR46
Address:
0000046EH
ICR47
Address:
0000046FH
HRCL
Address:
00000045H
MHALTI
R/W
R/W: Readable/writable
R:
Read only
-:
134
Undefined bit
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
CHAPTER 5 INTERRUPT CONTROLLER
5.3 Block Diagram of Interrupt Controller
MB91490 Series
5.3
Block Diagram of Interrupt Controller
Figure 5.3-1 shows the block diagram of the interrupt controller.
■ Block Diagram of the Interrupt Controller
Figure 5.3-1 Block Diagram of Interrupt Controller
WAKEUP (LEVEL 11111B : "1")
UNMI
Priority judgment
NMI
NMI
processing
5
LVL4 to LVL0
LEVEL,
VECTOR
generation
LEVEL judgment
HOLD request
cancel
request
MHALTI
ICR00
RI00
VECTOR
judgment
6
VCT5 to VCT0
ICR47
RI47
(DLYIRQ)
R-bus
CM71-10155-2E
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135
CHAPTER 5 INTERRUPT CONTROLLER
5.4 Register Details Explanation of Interrupt Controller
5.4
MB91490 Series
Register Details Explanation of Interrupt Controller
This section explains the registers used by the interrupt controller in detail.
■ Interrupt Control Register (ICR)
ICR00 to IICR19, ICR24 to ICR31, ICR33 to ICR39, ICR41 to ICR47
Address:
ch.0 to 19 000440H to 000453H
bit7
-
bit6
-
bit5
-
ch.24 to 31 000458H to 00045FH
ch.33 to 39 000461H to 000467H
bit4
ICR4
R
bit3
ICR3
R/W
bit2
ICR2
R/W
bit1
ICR1
R/W
bit0
ICR0
R/W
Initial value
---11111B
ch.41 to 47 000469H to 00046FH
R/W: Readable/writable
R:
Read only
-:
Undefined bit
The interrupt control register. One register is provided for each interrupt input to set the interrupt level for
the corresponding interrupt request.
[bit4 to bit0] ICR4 to ICR0
The interrupt level setting bits specify the interrupt level for the corresponding interrupt request. An
interrupt request is masked in the CPU if the interrupt level set in this register is greater than or equal to
the level mask value set in the ILM register of CPU.
Initialized to "11111B" by reset.
Table 5.4-1 lists the correspondence between interrupt level and available interrupt level setting bits.
Table 5.4-1 Correspondence between Interrupt Levels and Available Interrupt Level
Setting Bit Settings
136
ICR4
ICR3
ICR2
ICR1
ICR0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Interrupt level
0
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
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System reserved
NMI
Maximum permitted level setting
(High)
(Low)
Interrupt disabled
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CHAPTER 5 INTERRUPT CONTROLLER
5.4 Register Details Explanation of Interrupt Controller
MB91490 Series
ICR4 is fixed at "1". Writing "0" is not permitted.
■ Hold Request Cancel Level Register (HRCL)
HRCL
Address
00000045H
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
MHALTI
-
-
LVL4
R
LVL3
R/W
LVL2
R/W
LVL1
R/W
LVL0
R/W
0--11111B
R/W
R/W: Readable/writable
R:
Read only
-:
Undefined bit
The level setting register used to generate requests to cancel a hold request.
[bit7] MHALTI
The MHALTI bit causes DMA transfers to be halted by an NMI request. The bit is set to "1" by an NMI
request and is cleared by writing "0". Always clear this bit at the end of the NMI routine in the same
way as for standard interrupt routines.
[bit4 to bit0] LVL4 to LVL0
These set the interrupt level for generating a request to the bus master to cancel a hold request.
If an interrupt request with a higher-priority level than the interrupt level set in this register occurs, a
request to cancel the hold request is passed to the bus master.
The LVL4 bit is fixed at "1". Writing "0" is not permitted.
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CHAPTER 5 INTERRUPT CONTROLLER
5.5 Operation of Interrupt Controller
5.5
MB91490 Series
Operation of Interrupt Controller
This section explains the operation of the interrupt controller.
■ Determining the Priority
This module selects the highest priority interrupt amongst any interrupt factors that occur simultaneously
and outputs the interrupt level and interrupt number for the interrupt factor to the CPU.
The criteria for determining the priority of interrupt factor are as follows.
(1) NMI
(2) Interrupt factor that satisfies the following conditions
• Interrupt level is other than 31. (31 is interrupt disabled)
• Interrupt factor with lowest interrupt level value.
Of these, the interrupt factor with the lowest interrupt number.
If no interrupt factor is selected by the above criteria, 31 (11111B) is output as the interrupt level. The
interrupt number in this case is undefined.
"APPENDIX B Interrupt Vector" lists the relationship among the interrupt factor, interrupt number, and
interrupt level.
■ NMI (Non Maskable Interrupt)
The NMI has the highest priority of all the interrupt factors handled by this module.
Accordingly, the NMI is always selected if it occurs at the same time as another interrupt factor.
● The following information is passed to the CPU when an NMI occurs.
Interrupt level
: 15 ("01111B")
Interrupt number : 15 ("0001111B")
● NMI detection
The external interrupts/NMI module sets and detects NMIs. In this module, an NMI request only generates
the interrupt level, interrupt number, and MHALTI.
● Halt on DMA transfer by NMI
When an NMI request occurs, the MHALTI bit in the HRCL register goes to "1" to halt DMA transfer. To
release the halt on DMA transfer, clear the MHALTI bit to "0" at the end of the NMI routine.
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CHAPTER 5 INTERRUPT CONTROLLER
5.5 Operation of Interrupt Controller
MB91490 Series
■ Hold Request Cancel Request
If you want to process high priority interrupts during a CPU hold (during DMA transfer), the module that
generated the hold request needs to cancel the request. Set the interrupt level at which a request to cancel is
to be generated in the HRCL register.
● Generation criteria
If an interrupt factor with a higher-priority level than the level set in the HRCL register occurs, a request to
cancel the hold request is passed to the DMAC.
If interrupt level in HRCL register > level of interrupt after the priority judgment, then do generate cancel
request.
If interrupt level in HRCL register  level of interrupt after the priority judgment, then do not generate
cancel request.
The cancel request remains active until the interrupt factor that generated the cancel request is cleared and
therefore no DMA transfer occurs during this time. Always clear the associated interrupt factor.
As the MHALTI bit in the HRCL register goes to "1" when an NMI is used, the cancel request is active.
● Possible levels
The values able to be set in the HRCL register are "10000B" to "11111B", the same as the ICR.
If "11111B" is set, a cancel request is generated for all interrupt levels. If "10000B" is set, a cancel request
is only generated for an NMI.
Table 5.5-1 shows the interrupt level settings for generating a request to cancel a hold request.
Table 5.5-1 Interrupt Level Settings That Generate a Hold Request Cancel Request
HRCL register
Interrupt levels that generate a cancel request
16
NMI only
17
NMI, interrupt level 16
18
NMI, interrupt levels 16 and 17
to
31
to
NMI, interrupt levels 16 to 30 [Initial value]
Once reset, DMA transfer is halted for all interrupt levels. As this means that no DMA transfer will be
performed when an interrupt occurs, set the required value in the HRCL register.
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CHAPTER 5 INTERRUPT CONTROLLER
5.5 Operation of Interrupt Controller
MB91490 Series
■ Recovery from a Standby Mode (Stop or Sleep)
The function for using an interrupt request to recover from stop mode is performed by this module.
If one or more interrupt requests from a peripheral including NMI (with interrupt level other than
"11111B") occur, a request to recover from stop mode is sent to the clock controller.
As the priority judgment unit restarts operation once the clock supply starts after recovery from stop mode,
the CPU is able to execute instructions until the priority judgment unit produces a result.
The same operation occurs when recovering from sleep mode.
Access to the registers in this module remains possible even in sleep mode.
Notes:
• The device also recovers from stop mode when an NMI request occurs. However, apply a valid
input level to the NMIX pin in stop mode.
• Set the interrupt level for interrupt factors that you do not want to cause the device to recover from
stop or sleep mode to "11111B" in the corresponding peripheral control register.
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CHAPTER 5 INTERRUPT CONTROLLER
5.5 Operation of Interrupt Controller
MB91490 Series
■ Example of Using the Function to Generate a Request to Cancel a Hold Request
(HRCR)
If you want the CPU to perform high-priority processing during DMA transfer, you need to cancel the hold
state by requesting the DMA to cancel its hold request. This uses an interrupt to cause the DMA to cancel
its hold request and to give priority to CPU operation.
● Control register
• HRCL (Hold request cancel level setting register): this module
If an interrupt with a higher-priority level than the interrupt level set in this register occurs, a request to
cancel the hold request is passed to the DMA. Sets the level to use as the criterion.
• ICR: this module
Set an interrupt level with a higher priority than the level set in the HRCL register in the ICRs of the
interrupt factors you want to use.
● Hardware configuration
The signal flow is shown below.
Figure 5.5-1 Signal Flow
This module
IRQ
Bus access request
MHALTI
I-UNIT
DHREQ
DMAC
(ICR)
Conver-
(HRCL)
ter
DHREQ
DHACK
IRQ
MHALTI
CM71-10155-2E
Bus
CPU
DHACK
: D-bus hold request
: D-bus hold acknowledge
: Interrupt request
: Hold request cancel request
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CHAPTER 5 INTERRUPT CONTROLLER
5.5 Operation of Interrupt Controller
MB91490 Series
● Sequence
Figure 5.5-2 Interrupt Level HRCL < ICR (LEVEL)
RUN
Interrupt processing
Bus hold
(1)
CPU
Bus hold (DMA transfer)
Example of
interrupt routine
(2)
Bus access
request
(1) Clearing
interrupt source
|
DHREQ
(2) RETI
DHACK
IRQ
LEVEL
MHALTI
When an interrupt request occurs and the interrupt level changes, the MHALTI signal to the DMA goes
active if the new level has a higher priority than the level set in the HRCL register. This causes the DMA to
halt access requests and the CPU to recover from the hold state and start processing the interrupt.
The diagram below shows the case when multiple interrupts occur.
Figure 5.5-3 Interrupt Level HRCL < ICR (Interrupt I) < ICR (Interrupt II)
RUN
Bus hold
Interrupt I
Interrupt processing II
(3)
CPU
(4)
Interrupt processing I Bus hold (DMA transfer)
(1)
(2)
Bus access
request
DHREQ
DHACK
IRQ1
IRQ2
LEVEL
MHALTI
Example of interrupt routine
(1), (3) Clearing interrupt source
|
(2), (4) RETI
The above example shows the case when a higher priority interrupt occurs during execution of interrupt
routine I.
DHREQ becomes low while the interrupt with an interrupt level higher than the interrupt level set in the
HRCL register is present.
Note:
Take note of the relationship between the interrupt levels set in the HRCL register and ICRs.
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CHAPTER 6
EXTERNAL INTERRUPT AND
NMI CONTROLLER
This chapter describes the overview of the external
interrupt and NMI controller, the configuration and
functions of registers, and operation of the external
interrupt and NMI controller.
6.1 Overview of External Interrupt/NMI Controller
6.2 Registers of External Interrupt/NMI Controller
6.3 Operation of External Interrupt/NMI Controller
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CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER
6.1 Overview of External Interrupt/NMI Controller
6.1
MB91490 Series
Overview of External Interrupt/NMI Controller
The external interrupt controller is a block that controls external interrupt requests
input to NMIX and INT0 to INT6.
For external interrupt input, "H level", "L level", "rising edge", or "falling edge" can be
selected as the level of a request to be detected.
■ Register List
Following figure shows the register list of the external interrupt/NMI controller.
External interrupt source register
EIRR0
Address
bit7
bit6
bit5
ER7*
ER6
ER5
00000040H
R/W
R/W
R/W
bit4
ER4
R/W
bit3
ER3
R/W
bit2
ER2
R/W
bit1
ER1
R/W
bit0
ER0
R/W
Initial value
00000000B
Interrupt enable register
ENIR0
Address
bit7
bit6
EN7*
EN6
00000041H
R/W
R/W
bit4
EN4
R/W
bit3
EN3
R/W
bit2
EN2
R/W
bit1
EN1
R/W
bit0
EN0
R/W
Initial value
00000000B
bit11
LB5
R/W
bit10
LA5
R/W
bit9
LB4
R/W
bit8
LA4
R/W
Initial value
00000000B
bit3
LB1
R/W
bit2
LA1
R/W
bit1
LB0
R/W
bit0
LA0
R/W
Initial value
00000000B
bit5
EN5
R/W
External interrupt request level setting register
ELVR0
Address
bit15
bit14
bit13
bit12
LB7*
LA7*
LB6
LA6
00000042H
R/W
R/W
R/W
R/W
ELVR0
Address
bit7
bit6
bit5
bit4
00000043H
LB3
LA3
LB2
LA2
R/W
R/W
R/W
R/W
R/W: Readable/writable
-:
Undefined bit
* : Used for low voltage detection interrupt function.
For details, refer to "CHAPTER 18 LOW VOLTAGE DETECTION INTERRUPT / RESET".
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CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER
6.1 Overview of External Interrupt/NMI Controller
MB91490 Series
■ Block Diagram of External Interrupt/NMI Controller
Figure 6.1-1 shows the block diagram of external interrupt/NMI controller.
Figure 6.1-1 Block Diagram of External Interrupt / NMI Controller
16
Interrupt request
9
16
External interrupt enable register
Gate
Source F/F
Edge detection circuit
External interrupt source register
8
INT0 to INT6
NMIX
Low voltage detection circuit *
16
External interrupt request level setting register
* : Used for low voltage detection interrupt function.
For details, refer to "CHAPTER 18 LOW VOLTAGE DETECTION INTERRUPT / RESET".
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CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER
6.2 Registers of External Interrupt/NMI Controller
6.2
MB91490 Series
Registers of External Interrupt/NMI Controller
This section explains the configuration and functions of registers used by external
interrupt/NMI controller.
■ Interrupt Enable Register (ENIR (ENIR0): ENable Interrupt Request Register)
ENIR0
Address
00000041H
bit7
EN7*
R/W
bit6
EN6
R/W
bit5
EN5
R/W
bit4
EN4
R/W
bit3
EN3
R/W
bit2
EN2
R/W
bit1
EN1
R/W
bit0
EN0
R/W
Initial value
00000000B
R/W : Readable/writable
* : Used for low voltage detection interrupt function.
For details, refer to "CHAPTER 18 LOW VOLTAGE DETECTION INTERRUPT / RESET".
ENIR register controls mask of the external interrupt (INT0 to INT6) request output. Output for an interrupt
request is enabled based on the bit in this register to which "1" has been written (INT0 enable is controlled
by EN0), and the interrupt request is output to the interrupt controller. The pin corresponding to the bit to
which "0" is written holds the interrupt source but does not generate a request to the interrupt controller.
No enable bit exists for NMI.
■ External Interrupt Source Register (EIRR (EIRR0): External Interrupt Request Register)
EIRR0
Address
00000040H
bit7
ER7*
R/W
bit6
ER6
R/W
bit5
ER5
R/W
bit4
ER4
R/W
bit3
ER3
R/W
bit2
ER2
R/W
bit1
ER1
R/W
bit0
ER0
R/W
Initial value
00000000B
R/W : Readable/writable
* : Used for low voltage detection interrupt function.
For details, refer to "CHAPTER 18 LOW VOLTAGE DETECTION INTERRUPT / RESET".
EIRR register is a register that shows a corresponding external interrupt request exists when reading, and
that clears a content of the flip-flop showing this request when writing.
If the read value of this EIRR register is "1", there is an external interrupt request at the pin corresponding
to this bit. Write "0" to this register to clear the request flip-flop of the corresponding bit.
Writing "1" to this register is invalid.
"1" is read in a read operation of the read modify write (RMW) instruction.
The flag for NMI cannot be accessed by a user.
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CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER
6.2 Registers of External Interrupt/NMI Controller
MB91490 Series
■ External Interrupt Request Level Setting Register
(ELVR (ELVR0): External LeVel setting Register)
ELVR0
Address
00000042H
ELVR0
Address
00000043H
bit15
LB7*
R/W
bit14
LA7*
R/W
bit13
LB6
R/W
bit12
LA6
R/W
bit11
LB5
R/W
bit10
LA5
R/W
bit9
LB4
R/W
bit8
LA4
R/W
Initial value
00000000B
bit7
LB3
R/W
bit6
LA3
R/W
bit5
LB2
R/W
bit4
LA2
R/W
bit3
LB1
R/W
bit2
LA1
R/W
bit1
LB0
R/W
bit0
LA0
R/W
Initial value
00000000B
R/W : Readable/writable
* : Used for low voltage detection interrupt function.
For details, refer to "CHAPTER 18 LOW VOLTAGE DETECTION INTERRUPT / RESET".
ELVR is a register to select request detections. In ELVR, two bits each are assigned to INT0 to INT6,
which results in the settings shown in table below. When each bit of the EIRR is cleared while the level is
in the request input level, an appropriate bit is set again as long as the input is at active level.
Table 6.2-1 Assignment of ELVR
LBx
LAx
Operation
0
0
"L" level indicates the existence of a request
0
1
"H" level indicates the existence of a request
1
0
A rising edge indicates the existence of a request
1
1
A falling edge indicates the existence of a request
Detection level of NMI is always a falling edge level.
Also, when using NMI to return from the stop state, detection level is "L" level.
Note:
If the external interrupt request level is changed, it may cause the internal interrupt. So, it is
necessary to clear the external interrupt cause register (EIRR) after reading the external interrupt
request level register.
Before clearing the external interrupt cause register, read out the external interrupt request register
for writing clear.
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CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER
6.3 Operation of External Interrupt/NMI Controller
MB91490 Series
Operation of External Interrupt/NMI Controller
6.3
If, after a request level and an enable register are defined, a request defined in the ELVR
register is input to the corresponding pin, this module generates an interrupt request
signal to the interrupt controller. For simultaneous interrupt requests from resources,
the interrupt controller determines the interrupt request with the highest priority and
generates an interrupt for it.
■ Operation of an External Interrupt
Figure 6.3-1 shows the external interrupt operation.
Figure 6.3-1 External Interrupt Operation
External Interrupt
CPU
Interrupt controller
Resource request
ELVR
ICR yy
EIRR
ENIR
IL
CMP
ICR xx
CMP
ILM
Source
■ Return from Standby
Be sure to disable the channel that is not used before entering to standby.
■ Operating Procedure for an External Interrupt
Set up a register located inside the external interrupt controller as follows:
1. Set that general-purpose I/O port as an input port which also serves as a pin to be used as an external
interrupt input.
2. Disable the target bit in the interrupt enable register (ENIR).
3. Set the target bit in the external interrupt request level setting register (ELVR).
4. Read the external interrupt request level setting register (ELVR).
5. Clear the target bit in the external interrupt source register (EIRR).
6. Enable the target bit in the interrupt enable register (ENIR).
(Simultaneous writing of 16-bit data is supported for steps 5. and 6.)
Before setting a register in this module, you must disable the enable register. In addition, before enabling
the enable register, you must clear the interrupt source register. This procedure is required to prevent an
interrupt source from occurring by mistake while a register is being set or an interrupt is enabled.
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CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER
6.3 Operation of External Interrupt/NMI Controller
MB91490 Series
■ External Interrupt Request Level
• If the request level is an edge request, a pulse width of at least 4 peripheral clock is required to detect an
edge.
• If the request input level is a level setting, a request input is entered from outside and is then cancelled,
the request to the interrupt controller remains active because a source holding circuit exists internally.
When the request input level is a level setting, pulse widths must be more than 3 machine cycles.
Moreover, even if the factor register is cleared, the interrupt request to the interrupt controller keeps
being generated as long as the interrupt input terminal maintains the active level.
The external interrupt source register must be cleared to cancel a request to the interrupt controller.
Figure 6.3-2 Clearing the External Interrupt Source Register when a Level is Set
Interrupt Input
Level
detection
External interrupt source register
(Source holding circuit)
Enable gate
Interrupt controller
Holds a source unless it is cleared
Figure 6.3-3 Interrupt Source and Interrupt Request to Interrupt Controller when Interrupts are Enabled
H level
Interrupt input
Interrupt request
to interrupt controller
CM71-10155-2E
Becomes inactive when the external interrupt source register is cleared
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CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER
6.3 Operation of External Interrupt/NMI Controller
MB91490 Series
■ NMI
• An NMI has the highest level among the user interrupts and cannot be masked.
However, as an exception, when NMI is activated without setting ILM, NMI source is detected but CPU
will not accept the NMI request. At this time, the NMI source will be held until ILM is set to be accepted
by NMI. For this reason, use NMI after resetting and setting ILM value to 16 or higher.
Also, since an internal source flag of NMI cannot be accessed from CPU, keep NMIX pin to "H" level
after reset.
• An NMI is accepted under the following conditions:
Normal state:Falling edge
STOP state:"L" level
• An NMI can be used to clear stop mode. Inputting the "L" level in the stop state clears the stop state and
causes the oscillation stabilization wait time to start.
The NMI request detector has an NMI flag that is set for an NMI request and is cleared only if an
interrupt for the NMI itself is accepted or reset occurs. Note that this bit is not readable or writable.
Figure 6.3-4 NMI Request Detector
(NMI flag)
0
NMI request
(Stop clearing)
Q SX
Falling edge
detection
NMIX
R
1
Peripheral clock (CLKP)
STOP
Clear (RST, interrupt acknowledge)
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CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER
6.3 Operation of External Interrupt/NMI Controller
MB91490 Series
■ Notes If Restoring from STOP Status Performed Using an External Interrupt
During STOP status, external interrupt signals that are first entered to the INT terminal are entered
asynchronously, to enable recovery from the STOP status. The period from that STOP being released to the
passage of oscillation stabilization wait time contains a period that cannot identify the other external
interrupt signal inputs (Period b+c+d for Figure 6.3-5.). To synchronize external interrupt signals after the
STOP has been released with the internal clock, while the clock is not stable, interrupt request cannot be
stored.
Consequently, if sending external interrupt inputs after the STOP has been released, input external interrupt
signals after the oscillation stabilization wait time has elapsed.
Figure 6.3-5 Recovery Operation Sequence Using External Interrupts from STOP Status
INT1
INT0
Internal
STOP
Regulator
Internal
operation (RUN)
Implement command (RUN)
X0
Internal clock
Interrupt flag clear
ER0
EN0
"1" (Set to enable before switching to STOP mode)
ER1
EN1
"1" (Set to enable before switching to STOP mode)
(a) STOP
(c) Oscillation stabilization wait time
(b) Oscillator oscillation time
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(d)RUN
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CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER
6.3 Operation of External Interrupt/NMI Controller
MB91490 Series
■ Recovery Operations from STOP Status
The STOP recovery operation using external interrupts from existing circuits is performed as described
below.
● Processing before changing to STOP status
• External Interrupt Process Configuration
It is necessary to set the external interrupt input process to release STOP status before the device transits
to STOP status. These configuration are made using the PFR register (Port Function Register) and ENIR
register (ENable Interrupt Register). Under normal conditions (i.e., any status other than STOP), the
interrupt input process is authorized, so there is no need for special recognition. In STOP status, however,
the input path is controlled by the PFR register value.
Pin name used for STOP release
Setting registers and bit
P86/INT6/PPG6
Set PFR8 bit6 to "0".
P85/INT5/PPG5
Set PFR8 bit5 to "0".
P84/INT4/PPG4
Set PFR8 bit4 to "0".
• External Interrupt Inputs
If recovering from STOP status, the external interrupt signals are asynchronous and send the input signal.
When this interrupt signal is enabled, the internal STOP signal is immediately turned OFF. At the same
time, the external interrupt circuit is switched so as to synchronize other level interrupt inputs.
● Oscillator Oscillation Time
After the regulator stabilization wait time has ended, the clock will start to oscillate. The oscillator
oscillation time depends on the used oscillator.
● Oscillation Stabilization Wait Time
After the oscillator oscillation time, an oscillation stabilization wait time is taken inside the device. The
oscillation stabilization wait time is specified by bits OS1 and OS0 on the standby control register. After
the oscillation stabilization wait time has ended, the internal clock is supplied, and in addition to the
activation of interrupt command operations from the external interrupt, it also becomes possible to
receive external interrupt requests other than the recovery from STOP request.
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CHAPTER 7
REALOS-RELATED
HARDWARE
The REALOS-related hardware is used by the real-time
OS. Accordingly, these functions cannot be used by
user programs if using REALOS.
This chapter explains the overview of the delayed
interrupt module and bit search module, the
configuration and functions of the registers, and the
operation of the delayed interrupt module and bit search
module.
7.1 Delayed Interrupt Module
7.2 Bit Search Module
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CHAPTER 7 REALOS-RELATED HARDWARE
7.1 Delayed Interrupt Module
7.1
MB91490 Series
Delayed Interrupt Module
The delayed interrupt module is used to generate the interrupt for task switching.
An interrupt request to the CPU can be generated and cleared by software using this
module.
■ Delayed Interrupt Module Registers
DICR
Address
00000044H
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-
-
-
-
-
-
-
DLYI
-------0B
R/W
R/W: Readable/writable
-:
Undefined bit
■ Block Diagram of Delayed Interrupt Module
R-bus
DLYI
Interrupt request
■ Register Details Explanation
● DICR (Delayed Interrupt Control Register)
Address
00000044H
bit7
-
bit6
-
bit5
-
bit4
-
bit3
-
bit2
-
bit1
-
bit0
DLYI
R/W
Initial value
-------0B
R/W: Readable/writable
-:
Undefined bit
This register controls the delayed interrupt.
[bit0] DLYI
DLYI
Description
0
Delayed interrupt source cleared or no request present [Initial value]
1
Delayed interrupt source occurred
This bit controls generation and clearing of the interrupt source.
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CHAPTER 7 REALOS-RELATED HARDWARE
7.1 Delayed Interrupt Module
■ Operation Explanation
The delayed interrupt is used to generate the interrupt for task switching. An interrupt request to the CPU
can be generated and cleared by software using this function.
● Interrupt number
The delayed interrupt is assigned to the interrupt source corresponding to the highest interrupt number.
On MB91490 series, the delayed interrupt has interrupt number 63 (3FH).
● DLYI Bit of DICR
Writing "1" to this bit generates a delayed interrupt source. Similarly, writing "0" to this bit clears the
delayed interrupt source.
This bit functions like a standard interrupt source flag and should be cleared in the interrupt routine at the
same time as performing task switching.
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CHAPTER 7 REALOS-RELATED HARDWARE
7.2 Bit Search Module
7.2
MB91490 Series
Bit Search Module
Searches for a zero, one, or change point in the data written to the input register and
returns the detected bit position.
■ Bit Search Module Registers
bit 31
bit0
Address: 000003F0H
BSD0
Zero-detect data register
Address: 000003F4H
BSD1
One-detect data register
Address: 000003F8H
BSDC
Change point detection data register
Address: 000003FCH
BSRR
Detection result register
■ Block Diagram of Bit Search Module
Figure 7.2-1 Block Diagram of Bit Search Module
D-bus
Input latch
Address decoder
Detection
mode
1 detection data coding
Bit search circuit
Detection result
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7.2 Bit Search Module
MB91490 Series
■ Register Details Explanation
● Zero-detect data register (BSD0)
Address
000003F0H
bit31
bit0
Attribute  Write only
Initial value  XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXXB
Detects "0" in the value written.
The initial value by reset is irregular. The read value is undefined.
Use a 32-bit data transfer instruction to transfer the data
(Do not use 8-bit or 16-bit data transfer instructions).
● One-detect data register (BSD1)
Address
000003F4H
bit31
bit0
Attribute  Readable/Writable
Initial value  XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXXB
Use a 32-bit data transfer instruction to transfer the data
(Do not use 8-bit or 16-bit data transfer instructions).
• Writing
Detects "1" in the value written.
• Reading
Reads the data to enable the internal state of the bit search module to be saved. This is used to save and
restore the original state when the bit search module is used by an interrupt handler or similar.
Saving and restoring can be performed using only the one-detect data register even if data is written to
the 0-detect or change point detection data registers.
The initial value by reset is irregular.
● Change point detection data register (BSDC)
Address
000003F8H
bit31
bit0
Attribute  Write only
Initial value  XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXXB
Detects the change point in the value written.
The initial value by reset is irregular.
The read value is undefined.
Use a 32-bit data transfer instruction to transfer the data
(Do not use 8-bit or 16-bit data transfer instructions).
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7.2 Bit Search Module
MB91490 Series
● Detection result register (BSRR)
Reads the result of the zero-detect, one-detect, or change point detect operation.
Which result is read from this register is determined by which data register was written to most recently.
Address
000003FCH
bit31
bit0
Attribute  Read only
Initial value  XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXXB
■ Operation Explanation
● 0 detection
The module scans data written to the zero-detect data register from the MSB to the LSB and returns the
position of the first "0".
The result is obtained by reading the detection result register.
Table 7.2-1 shows the relationship between the returned value and the detected position.
If no "0" exists (if the value is "FFFFFFFFH"), 32 is returned as the search result.
[Execution example]
Write data
Read data (decimal)
11111111111111111111000000000000B (FFFFF000H)
11111000010010011110000010101010B (F849E0AAH)

20

5
10000000000000101010101010101010B (8002AAAAH)

1
11111111111111111111111111111111B (FFFFFFFFH)

32
● 1 detection
The module scans data written to the one-detect data register from the MSB to the LSB and returns the
position of the first "1".
The result is obtained by reading the detection result register.
Table 7.2-1 shows the relationship between the returned value and the detected position.
If no "1" exists (if the value is "00000000H"), 32 is returned as the search result.
[Execution example]
Write data
158
Read data (decimal)
00100000000000000000000000000000B (20000000H)

2
00000001001000110100010101100111B (01234567H)
00000000000000111111111111111111B (0003FFFFH)

7

14
00000000000000000000000000000001B (00000001H)
00000000000000000000000000000000B (00000000H)

31

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7.2 Bit Search Module
MB91490 Series
● Change point detection
The data written to the change point detection data register is scanned from bit30 to the LSB and compared
with the MSB. The position of the first bit with a value different to the MSB is returned.
The result is obtained by reading the detection result register.
Table 7.2-1 shows the returned value and detected position.
If no change point exists, 32 is returned as the search result.
The change point detection function never returns a result of zero.
[Execution example]
Write data
Read data (decimal)
00100000000000000000000000000000B (20000000H)
00000001001000110100010101100111B (01234567H)

2

7
00000000000000111111111111111111B (0003FFFFH)

14
00000000000000000000000000000001B (00000001H)

31
00000000000000000000000000000000B (00000000H)
11111111111111111111000000000000B (FFFFF000H)

32

20
11111000010010011110000010101010B (F849E0AAH)
10000000000000101010101010101010B (8002AAAAH)

5

1
11111111111111111111111111111111B (FFFFFFFFH)

32
Table 7.2-1 Bit Position and Return Value (Decimal)
Detected bit
position
Return
value
Detected bit
position
Return
value
Detected bit
position
Return
value
Detected bit
position
Return
value
31
0
23
8
15
16
7
24
30
1
22
9
14
17
6
25
29
2
21
10
13
18
5
26
28
3
20
11
12
19
4
27
27
4
19
12
11
20
3
28
26
5
18
13
10
21
2
29
25
6
17
14
9
22
1
30
24
7
16
15
8
23
0
31
Not exist
32
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CHAPTER 7 REALOS-RELATED HARDWARE
7.2 Bit Search Module
MB91490 Series
■ Backup/Restore Processing
When it is necessary to backup and restore the internal state of the bit search module such as when using
the bit search module in an interrupt handler, always use the following procedure.
(1) Read the one-detect data register and save the value. (backup)
(2) Use the bit search module.
(3) Write the data saved in step (1) to the one-detect data register (restore).
This ensures that the value returned when the detection result register is next read will be based on the
value written to the bit search module prior to step (1). This procedure will correctly restore the result, even
if the data register written to previously was the zero-detect or change point detect data register.
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CHAPTER 8
16-BIT RELOAD TIMER
This chapter describes the overview of the reload timer,
the configuration and functions of registers, and the
reload timer operation.
8.1 Overview of 16-bit Reload Timer
8.2 16-bit Reload Timer Register
8.3 Operation of 16-bit Reload Timer
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CHAPTER 8 16-BIT RELOAD TIMER
8.1 Overview of 16-bit Reload Timer
8.1
MB91490 Series
Overview of 16-bit Reload Timer
The 16-bit reload timer consists of a 16-bit down-counter, 16-bit reload register, internal
count, clock generation prescaler, and control register.
■ Overview of 16-bit Reload Timer
The 16-bit reload timer consists of a 16-bit down-counter, 16-bit reload register, internal count, clock
generation prescaler, and control register.
The clock source can be selected from three internal clocks (peripheral clock (CLKP) divided by 2, 8, 32) .
■ Block Diagram of the 16-bit Reload Timer
Figure 8.1-1 shows the block diagram of the 16-bit reload timer.
Figure 8.1-1 Block Diagram of 16-bit Reload Timer
16-bit reload register
(TMRLR0, TMRLR1)
Reload
16-bit down counter (TMR0, TMR1)
R-bus
UF
RELD
INTE
OUT
CTL
Count
enable
UF
AND
Clock
selector
Prescaler
IRQ
CNTE
TRG
CSL1
CSL0
Prescaler
clear
16-bit reload timer 1
timer output
To A/D activate
compare 0
Peripheral clock (CLKP)
The only 16-bit reload timer 1 timer output can be used as the activation cause of A/D converter. The
activation target A/D converter is 10-bit A/D converter 1.
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8.2 16-bit Reload Timer Register
MB91490 Series
8.2
16-bit Reload Timer Register
This section describes the configuration and functions of the 16-bit reload timer
registers.
■ List of 16-bit Reload Timer Registers
TMCSR0, TMCSR1 high byte
Address
0000 004EH
0000 0056H
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value




CSL1
CSL0


----00--B




R/W
R/W


bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value



RELD
INTE
UF
CNTE
TRG
---00000B



R/W
R/W
R/W
R/W
R/W
TMCSR0, TMCSR1 low byte
Address
0000 004FH
0000 0057H
TMR0, TMR1
Address
bit15
bit0
0000 004AH
0000 0052H
Initial value
XXXXH
R
TMRLR0, TMRLR1
Address
bit15
bit0
0000 0048H
0000 0050H
Initial value
XXXXH
W
R/W:
R:
W:
-:
Readable/writable
Read only
Write only
Undefined bit
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CHAPTER 8 16-BIT RELOAD TIMER
8.2 16-bit Reload Timer Register
8.2.1
MB91490 Series
Control Status Register (TMCSR)
The control status register (TMCSR) controls the operation mode and interrupt of the
16-bit reload timer.
■ Bit Configuration of Control Status Register (TMCSR)
TMCSR0, TMCSR1 high byte
Address
0000 004EH
0000 0056H
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value




CSL1
CSL0


----00--B




R/W
R/W


bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value



RELD
INTE
UF
CNTE
TRG
---00000B



R/W
R/W
R/W
R/W
R/W
TMCSR0, TMCSR1 low byte
Address
0000 004FH
0000 0057H
R/W: Readable/writable
-:
Undefined bit
[bit15 to bit12] Reserved: Reserved bits
Reading of these bits always returns "0000B".
[bit11, bit10] CSL1,CSL0: Count source select bits
These are the count source selection bits. The count source can select the internal clock. The available count
sources are as follows.
164
=40MHz
=20MHz
/21 [Initial value]
50ns
100ns
Internal clock
/23
200ns
400ns
Internal clock
/25
800ns
1.6s
-
-
CSL1
CSL0
Count Source (: Peripheral clock)
0
0
Internal clock
0
1
1
0
1
1
Setting prohibited
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CHAPTER 8 16-BIT RELOAD TIMER
8.2 16-bit Reload Timer Register
MB91490 Series
[bit9 to bit7] Reserved: Reserved bits
Please set to "000B".
[bit6, bit5] Reserved: Reserved bits
Reading of these bits always returns "0".
[bit4] RELD: Reload enable bit
The reload enable bit. Setting "1" sets reload mode. In this case, the contents of the reload register are
loaded to the counter and the count continues when the counter underflows from "0000H" to "FFFFH".
Setting "0" sets one-shot mode. In this case, the count halts when the counter underflows from "0000H" to
"FFFFH".
[bit3] INTE: Interrupt enable bit
The interrupt request enable bit. If this bit is set to "1", an interrupt request is generated when the UF bit is
"1". No interrupt request is generated if this bit is set to "0".
[bit2] UF: Underflow interrupt flag
The timer interrupt request flag. This bit is set to "1" when the counter underflows from "0000H" to
"FFFFH". Writing "0" to this bit clears it.
Writing "1" to this bit has no meaning.
Read modify write (RMW) instructions always read the bit as "1".
[bit1] CNTE: Count enable bit
The count enable bit for the timer. Writing "1" to this bit sets the timer to wait for a start trigger. Writing
"0" halts the count.
[bit0] TRG: Trigger bit
The software trigger bit. Writing "1" to this bit generates a software trigger which loads the contents of the
reload register to the counter and starts the count.
Writing "0" to this bit has no meaning. Reading value is always "0".
The trigger input in this register is only meaningful when CNTE=1. The trigger has no effect if CNTE=0.
Note:
Only modify the bits other than UF, CNTE, and TRG when CNTE = 0.
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CHAPTER 8 16-BIT RELOAD TIMER
8.2 16-bit Reload Timer Register
8.2.2
MB91490 Series
16-bit Timer Register (TMR)
The 16-bit timer register (TMR) is used to read the count value of the 16-bit timer.
■ Bit Configuration of 16-bit Timer Register (TMR)
TMR0, TMR1
Address
bit15
bit0
0000 004AH
0000 0052H
Initial value
XXXXH
R
R: Read only
The count value of the 16-bit timer can be read from this register. The initial value is undefined. Always
use a 16-bit data transfer instruction to read this register.
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CHAPTER 8 16-BIT RELOAD TIMER
8.2 16-bit Reload Timer Register
MB91490 Series
8.2.3
16-bit Reload Register (TMRLR)
16-bit reload register (TMRLR) stores the initial value of the counter.
■ Bit Configuration of 16-bit Reload Register (TMRLR)
TMRLR0, TMRLR1
Address
bit15
bit0
0000 0048H
0000 0050H
Initial value
XXXXH
W
W: Write only
This register stores the initial value of the count. The initial value is irregular. Always use a 16-bit data
transfer instruction to write to this register.
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CHAPTER 8 16-BIT RELOAD TIMER
8.3 Operation of 16-bit Reload Timer
8.3
MB91490 Series
Operation of 16-bit Reload Timer
This section explains the internal clock operation and underflow operation of the reload
timer.
■ Internal Clock Operation
When the timer is driven by the divided internal clock, the count source can be selected from the peripheral
clock divided by 2, 8 or 32.
If you wish to enable and start the count at the same time, write "1" to both the CNTE bit and TRG bit in
the control status register. The TRG bit trigger input always functions regardless of the operation mode,
provided the timer is enabled (CNTE = 1).
The time between input of a counter start trigger and the data in the reload register being loaded to the
counter is T (T: cycle of peripheral clock).
Figure 8.3-1 Counter Start and Operation
Count clock
Counter
Reload data
-1
-1
-1
Load data
CNTE
TRG
T
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CHAPTER 8 16-BIT RELOAD TIMER
8.3 Operation of 16-bit Reload Timer
MB91490 Series
■ Underflow Operation
An underflow on this timer is defined as when the counter goes from "0000H" to "FFFFH". Accordingly, an
underflow occurs after (reload register setting value + 1) counts.
If the RELD bit in the control status register is "1" when the underflow occurs, the contents of the reload
register are loaded to the counter and the count continues. If the RELD bit is "0", the counter halts at
"FFFFH".
Figure 8.3-2 Underflow Operation
[RELD =1]
Count clock
Counter
0000H
Reload data
-1
-1
-1
Load data
Underflow set
[RELD =0]
Count clock
Counter
0000H
FFFFH
Underflow set
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CHAPTER 8 16-BIT RELOAD TIMER
8.3 Operation of 16-bit Reload Timer
MB91490 Series
■ Counter Operation States
The counter state is determined by the CNTE bit in the control status register and by the internal WAIT
signal. The states that can be set include the stop state, when CNTE=0 and WAIT=1 (STOP state); the
startup trigger wait state, when CNTE=1 and WAIT=1 (WAIT state); and the operation state, when
CNTE=1 and WAIT=0 (RUN state).
Figure 8.3-3 Status Transitions of Counter
Reset
State transition invoked by
hardware
State transition invoked by
register access
STOP
CNTE=0,WAIT=1
Counter: Maintains value when
stopped
Undefined just after a reset
CNTE=1
TRG=0
WAIT
CNTE=1
TRG=1
CNTE=1,WAIT=1
RUN
Counter: Maintains value when
stopped
Remains undefined just
after a reset until first load.
LDX . UFX
TRG=1
CNTE=1,WAIT=0
Counter: operation
TRG=1
RELD . UF
LOAD
CNTE=1,WAIT=0
Load contents of reload register to counter
Load completed
■ Precautions
• Operation of the internal prescaler is enabled when a trigger (software trigger or external trigger) occurs
while bit1 of the control status register (timer enable: CNTE) is set to "1".
• If the interrupt request flag is set and cleared at the same timing, the flag set operation has precedence
and the clear operation is ignored.
• If writing to the 16-bit timer reload register occurs at the same time as a reload timing, the old data is
loaded to the counter and the new data is not loaded to the counter until the next reload timing.
• If a 16-bit timer register load occurs at the same time as a count, the load (reload) operation has
precedence.
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CHAPTER 9
TIMING GENERATOR
This chapter explains the overview of the timing
generator, the configuration and functions of registers,
and operation of the timing generator.
9.1 Overview of Timing Generator
9.2 Block Diagram of Timing Generator
9.3 Registers of Timing Generator
9.4 Operation of Timing Generator
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CHAPTER 9 TIMING GENERATOR
9.1 Overview of Timing Generator
9.1
MB91490 Series
Overview of Timing Generator
The timing generator is to activate the delay synchronization for multiple PPG timers.
■ Configuration of Timing Generator
• This generator comprises an 8-bit counter, control register, compare registers, compare circuits and a
prescaler.
• It can activate the delay synchronization for 4 channels (ch.0/ch.2/ch.4/ch.6) of PPG.
• Four counter operation clocks (peripheral clock(CLKP)/2, peripheral clock(CLKP)/8, peripheral
clock(CLKP)/32 and peripheral clock(CLKP)/64) are available for selection.
• The amount of delay can be set by setting four compare registers (COMP0/COMP2/COMP4/COMP6)
corresponding to each PPG channel.
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CHAPTER 9 TIMING GENERATOR
9.2 Block Diagram of Timing Generator
MB91490 Series
9.2
Block Diagram of Timing Generator
This section shows the block diagram of the timing generator.
Figure 9.2-1 Block Diagram
Prescaler
Peripheral clock
(CLKP)
CS1/CS0
1/2
1/8
1/32
1/64
STR
MONI
8-bit counter
Counter value
COMP0
Compare circuit
Set
Clr
PPG0TG
Set
Clr
PPG2TG
Set
Clr
PPG4TG
Set
Clr
PPG6TG
COMP2
Compare circuit
COMP4
Compare circuit
COMP6
Compare circuit
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CHAPTER 9 TIMING GENERATOR
9.3 Registers of Timing Generator
9.3
MB91490 Series
Registers of Timing Generator
This section describes the registers of the timing generator.
■ Registers of Timing Generator
Control register 0: TTCR0
Address
bit31
bit30
bit29
bit28
0000 0144H TRG6O TRG4O TRG2O TRG0O
W
W
W
W
bit27
CS1
R/W
bit26
CS0
R/W
bit25
MONI
R
bit24
STR
W
Initial value
11110000B
Compare register 0: COMP0
Address
0000 0148H
bit31
D7
R/W
bit30
D6
R/W
bit29
D5
R/W
bit28
D4
R/W
bit27
D3
R/W
bit26
D2
R/W
bit25
D1
R/W
bit24
D0
R/W
Initial value
00000000B
bit21
D5
R/W
bit20
D4
R/W
bit19
D3
R/W
bit18
D2
R/W
bit17
D1
R/W
bit16
D0
R/W
Initial value
00000000B
bit13
D5
R/W
bit12
D4
R/W
bit11
D3
R/W
bit10
D2
R/W
bit9
D1
R/W
bit8
D0
R/W
Initial value
00000000B
bit5
D5
R/W
bit4
D4
R/W
bit3
D3
R/W
bit2
D2
R/W
bit1
D1
R/W
bit0
D0
R/W
Initial value
00000000B
Compare register 2: COMP2
Address
0000 0149H
bit23
D7
R/W
bit22
D6
R/W
Compare register 4: COMP4
Address
0000 014AH
bit15
D7
R/W
bit14
D6
R/W
Compare register 6: COMP6
Address
0000 014BH
bit7
D7
R/W
bit6
D6
R/W
R/W : Readable/writable
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CHAPTER 9 TIMING GENERATOR
9.3 Registers of Timing Generator
MB91490 Series
9.3.1
Timing Generator Control Register (TTCR0)
The timing generator control register (TTCR0) is used to check the status of PPG trigger
clear, timer prescaler and 8-bit counter as well as to control their operations.
■ Timing Generator Control Register (TTCR0)
Timing generator control register 0: TTCR0
Address
0000 0144H
bit15
bit14
bit13
bit12
TRG6O TRG4O TRG2O TRG0O
W
W
W
W
bit11
CS1
R/W
bit10
CS0
R/W
bit9
MONI
R
bit8
STR
W
Initial value
11110000B
R/W : Readable/writable
R : Read only
W : Write only
[bit15 to bit12] TRG6O/TRG4O/TRG2O/TRG0O: PPG Trigger clear bits
Writing "0" to these bits clears the PPG start trigger to be output. The correspondence with trigger of the
bits is shown below.
[Timing generator 0]
TRG0O: PPG0TG
TRG2O: PPG2TG
TRG4O: PPG4TG
TRG6O: PPG6TG
Read values of this register are always "1".
[bit11, bit10] CS1, CS0: Count clock selection bits
The operation clock of the 8-bit counter is selected as follows:
CM71-10155-2E
CS1
CS0
Clock source
0
0
Peripheral clock (CLKP) / 2 (50 ns @40 MHz)[Initial value]
0
1
Peripheral clock (CLKP) / 8 (200 ns @40 MHz)
1
0
Peripheral clock (CLKP) /32 (800 ns @40 MHz)
1
1
Peripheral clock (CLKP) /64 (1.6 s @40 MHz)
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CHAPTER 9 TIMING GENERATOR
9.3 Registers of Timing Generator
MB91490 Series
[bit9] MONI: 8-bit counter operating monitor bit
The operation of the 8-bit counter is selected as follows:
MONI
Status of 8-bit counter
0
Stopping counter [Initial value]
1
Operation counter
Writing value has no meaning.
[bit8] STR: 8-bit counter operation enable bit
The operation of the 8-bit counter is selected as follows:
STR
Operations of 8-bit counter
0
Has no meaning
[Initial value]
1
Start counter operation
Read value is always "0".
Writing "0" has no meaning.
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CHAPTER 9 TIMING GENERATOR
9.3 Registers of Timing Generator
MB91490 Series
9.3.2
Compare Register (COMP0/COMP2/COMP4/COMP6)
The compare registers (COMP0/COMP2/COMP4/COMP6) are used to set PPG start
signals. When the 8-bit counter matches with the value of one of the compare registers,
the corresponding PPG start signal is set.
■ Compare Register (COMP0/COMP2/COMP4/COMP6)
Compare register: COMP0/COMP2/COMP4/COMP6
Address
0000 0148H
0000 0150H
0000 014AH
0000 0152H
bit15
D7
R/W
bit14
D6
R/W
bit13
D5
R/W
bit12
D4
R/W
bit11
D3
R/W
bit10
D2
R/W
bit9
D1
R/W
bit8
D0
R/W
Initial value
00000000B
R/W : Readable/writable
[bit15 to bit8] D7 to D0: Compare value setting bits
Notes:
• When the value of the compare register is "00000000B", the PPG start signal won’t be set.
• Make sure to rewrite the register while the 8-bit counter is stopped.
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CHAPTER 9 TIMING GENERATOR
9.4 Operation of Timing Generator
9.4
MB91490 Series
Operation of Timing Generator
This section describes the operation of the timing generator.
■ Operation of Prescaler
This operation sets clock that is the count clock for the 8-bit counter divided by the peripheral clock
(CLKP).
■ 8-bit Counter
• The 8-bit counter starts counting the count clock from the prescaler by setting the STR bit.
• The 8-bit counter starts counting up and stops the counting with overflow.
• To start counter during counting is ignored.
• "1" is read to the MONI bit while the 8-bit counter is counting. When stopped, "0" is read.
• The count value of the 8-bit counter is input to comparators.
Figure 9.4-1 Operation/stop Timing of 8-bit Counter
8-bit counter
STR=1
STR=1
Counting
MONI=1
Stop counting
MONI=0
Counting
MONI=1
Stop counting
MONI=0
Stop count by overflow
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CHAPTER 9 TIMING GENERATOR
9.4 Operation of Timing Generator
MB91490 Series
Figure 9.4-2 Trigger Timing
8-bit counter
STR=1
TRG0O, TRG2O = 0
F0H
A0H
80H
TRG4O, TRG6O = 0
40H
COMP0
40H
COMP2
80H
COMP4
A0H
COMP6
F0H
PPG0TG
PPG2TG
PPG4TG
PPG6TG
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9.4 Operation of Timing Generator
180
MB91490 Series
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
CHAPTER 10
PPG
This chapter explains the overview of the PPG, the
configuration and functions of registers, and the PPG
operation.
10.1 Overview of PPG
10.2 Block Diagram of PPG
10.3 Registers of PPG
10.4 Operation Explanation of PPG
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CHAPTER 10 PPG
10.1 Overview of PPG
10.1
MB91490 Series
Overview of PPG
The PPG is an 8-bit reload timer module that can be used as a PPG output to output
pulses controlled by the timer operation.
The hardware consists of 8 8-bit down counters, 16 8-bit reload registers, control
register, 3 external pulse outputs, and 8 interrupt output. It is an 8ch 8-bit PPG or a 4ch
16-bit PPG.
■ Functions of PPG
• 4 PPG operation modes are supported.
• PPG output operation
Outputs a pulse waveform with arbitrary period and duty ratio.
Can also be used in conjunction with an external circuit to form a D/A converter.
• Output inversion function
The PPG output value can be inverted.
■ PPG Mode
• 8-bit PPG output independent operation mode
Can operate as an independent PPG output.
• 16-bit PPG output operation mode
1 channel 16-bit PPG output can be operated.
• 8 + 8-bit PPG output operation mode
With setting the ch(n + 1) output as the ch(n) clock input, the 8-bit PPG output in any cycle can be
operated (n = 0, 2, 4, 6).
• 16 + 16-bit PPG output operation mode
This mode sets the 16-bit prescaler output, ch(n + 3) + ch(n + 2) as a clock input for the 16-bit PPG, ch(n
+ 1) + ch(n). (n = 0, 4)
■ PPG Channels Corresponding to Each Mode
PPG channel
8-bit mode
PPG0
PPG0
PPG1
PPG1
PPG2
PPG2
PPG3
PPG3
PPG4
PPG4
PPG5
PPG5
PPG6
PPG6
PPG7
PPG7
8+8-bit mode
16-bit mode
PPG0+PPG1
PPG0
16+16-bit mode
PPG0+PPG2
PPG2+PPG3
PPG2
PPG4+PPG5
PPG4
PPG4+PPG6
PPG6+PPG7
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PPG6
CM71-10155-2E
CHAPTER 10 PPG
10.2 Block Diagram of PPG
MB91490 Series
10.2
Block Diagram of PPG
This section shows the block diagram of the PPG.
■ Block Diagram of the 8-bit PPG ch.0, ch.2, ch.4, ch.6
Figure 10.2-1 Block Diagram of the 8-bit PPG (ch.0, ch.2, ch.4, ch.6)
ch. (n+1) borrow
Peripheral clock (CLKP) 64-divided
Peripheral clock (CLKP) 16-divided
Peripheral clock (CLKP) 4-divided
Peripheral clock (CLKP)
To port
To multi-function timer 0 (PPG0/2/4)
PPG
output latch
Inversion
Clear
0
1
TTRGn
Count clock selection
S
R
PCNT (down counter)
"H"/"L" select
PEN(n+1)
TTRGI(n+1)
From timing
generator
Q
IRQn
Reload
"H"/"L" selector
PRLLn PRLBHn
PIEn
PRLHn
PUFn
"L"-side data bus
"H"-side data bus
PPGCn / TRG
n = 0, 2, 4, 6
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Operating mode
(control)
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10.2 Block Diagram of PPG
MB91490 Series
■ Block Diagram of the 8-bit PPG ch.1, ch.5
Figure 10.2-2 Block Diagram of the 8-bit PPG (ch.1, ch.5)
ch. (n+1) borrow
To port
Peripheral clock (CLKP) 64-divided
Peripheral clock (CLKP) 16-divided
Peripheral clock (CLKP) 4-divided
Peripheral clock (CLKP)
PPG
output latch
Inversion
Clear
0
1
TTRGn
PEN(n)
TTRGI(n)
From timing
generator
S
R Q
Count clock selection
IRQn
PCNT (down counter)
"H"/"L" select
ch (n-1)
borrow
Reload
"H"/"L" selector
PRLLn PRLBHn
PUFn
PIEn
PRLHn
"L"-side data bus
"H"-side data bus
PPGCn / TRG
n = 1, 5
184
Operating mode
(control)
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CM71-10155-2E
CHAPTER 10 PPG
10.2 Block Diagram of PPG
MB91490 Series
■ Block Diagram of the 8-bit PPG ch.3, ch.7
Figure 10.2-3 Block Diagram of the 8-bit PPG (ch.3, ch.7)
Peripheral clock (CLKP) 64-divided
Peripheral clock (CLKP) 16-divided
Peripheral clock (CLKP) 4-divided
Peripheral clock (CLKP)
PPG
output latch
Inversion
Clear
0
1
TTRGn
PEN(n)
TTRGI(n)
From timing
generator
S
R Q
Count clock selection
IRQn
PCNT (down counter)
ch (n-1)
borrow
Reload
"H"/"L" select
"H"/"L" selector
PRLLn
PRLBHn
PUFn
PIEn
PRLHn
"L"-side data bus
"H"-side data bus
PPGCn / TRG
n = 3, 7
CM71-10155-2E
Operating mode
(control)
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10.2 Block Diagram of PPG
MB91490 Series
■ Connection Diagram between PPG and Multi-function Timer
Multifunction timer 0
PPG0
PPG2
Selector
(PSEL)
R TO01
R TO23
R TO45
Waveform generator 0
PPG4
■ Block Diagram of Gate Function
Figure 10.2-4 Block Diagram of Gate Function
From TRG register
PEN(n) PEN(n+1)
Level detection
Selector
Selector
PEN(n) of
PPG ch. (n)
From
multifunction
timer GATEn
0
1
Selector
PEN(n+1) of
PPG ch. (n+1)
STGRn EDGEn
0
n = 0, 2, 4
186
1
0
X
1
X
1
X
FUJITSU SEMICONDUCTOR LIMITED
MD1 ch. (n)
MD0
MD1 ch. (n+1)
MD0
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CHAPTER 10 PPG
10.3 Registers of PPG
MB91490 Series
10.3
Registers of PPG
This section lists the registers of the PPG.
■ PPG Registers
PPG trigger register (TRG)
TRG
Address
bit7
000131H
bit6
bit5
bit4
bit3
bit2
bit1
bit0
PEN07 PEN06 PEN05 PEN04 PEN03 PEN02 PEN01 PEN00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
00000000B
Output inversion register (REVC)
REVC
Address
bit7
000135H
bit6
bit5
bit4
bit3
bit2
bit1
bit0
REV07 REV06 REV05 REV04 REV03 REV02 REV01 REV00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
GATE function control register (GATECn)
GATECn
Address
bit7
bit6
bit5
ch.0: 000133H
ch.4: 000137H
-
-
-
-
bit4
STGR(n+2) EDGE(n+2)
bit3
bit2
-
-
-
-
bit 2
bit 1
bit1
bit0
Initial value
00000000B
Initial value
STGR(n) EDGE(n) GATEC0: --00--00B
GATEC4: ------00B
R/W
R/W
R/W
R/W
n = 0, 4
PPG operation mode control register (PPGC0 to PPGC7)
PPGCn
Address
ch.0:
000108H
to
ch.7:
000117H
bit 7
bit 6
bit 5
bit 4
bit 3
Initial value
*
bit 0
00000000B
*
PIEn
PUFn
PCS1
PCS0
MD1
MD0
PEN07
PEN06 INTMn
PEN05
PEN04
PEN03
PEN02
PEN01 TTRGn
PEN00
PEN07
PEN06
PEN05
PEN04
PEN03
PEN02
PEN07
PEN06
PEN05
PEN04
PEN03
PEN01
N00
PEN07
PEN06
PEN05
PEN04
PEN03
PEN02
PEN01 PE
PEN00
PEN07
PEN06
PEN05
PEN04
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
n=0 to 7 PPG0 to 7
*: MD1 and MD0 exist only in even-numbered channel, but they do not exist in odd-numbered channel.
The initial value of odd-numbered channel is undefined. Writing to them is meaningless.
R/W: Readable/writable
-:
Undefined bit
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10.3 Registers of PPG
MB91490 Series
● Reload registers: 8-bit PPG mode
Reload register H (PRLH0 to PRLH7)
PPLHn
bit 15
Address
ch.0:
000100H to
ch.7:
000112H
n=0 to 7
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
Initial value
bit 8
PEN07
PEN06
PEN05
PEN04
PEN03
PEN02
PEN01
PEN00
PEN07
PEN06
PEN05
PEN04
PEN03
PEN02
PEN01
PEN00
PEN07
PEN06
PEN05
PEN04
PEN03
PEN02
PEN01
N00
PEN07
PEN06
PEN05
PEN04
PEN03
PEN02
PEN01 PE
PEN00
PEN07
PEN06
PEN05
PEN04
PEN03
PEN02
PEN01
PEN00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXXB
R/W
PPG0 to 7
Reload register L (PRLL0 to PRLL7)
PRLLn
bit 7
bit 6
Address
ch.0:
000101H to
ch.7:
000113H
bit 5
bit 4
bit 3
bit 2
bit 1
Initial value
bit 0
PEN07
PEN06
PEN05
PEN04
PEN03
PEN02
PEN01
PEN00
PEN07
PEN06
PEN05
PEN04
PEN03
PEN02
PEN07
PEN06
PEN05
PEN04
PEN03
PEN01
N00
PEN07
PEN06
PEN05
PEN04
PEN03
PEN02
PEN01 PE
PEN00
PEN07
PEN06
PEN05
PEN04
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXXB
R/W
n=0 to 7 ch.0 to ch.7
R/W: Readable/writable
■ Reload Registers: 16-bit PPG Mode
Reload register H (PRLH0, PRLH2, PRLH4, PRLH6)
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
XXXXXXXXB
R/W
R/W
n=0,2,4,6
R/W
R/W
R/W
R/W
R/W
R/W
PPG0/2/4/6
Reload register L (PRLL0, PRLL2, PRLL4, PRLL6)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
XXXXXXXXB
R/W
R/W
n=0,2,4,6
R/W
R/W
R/W
R/W
R/W
R/W
PPG0/2/4/6
The address of PRLLn in 16-bit PPG mode is different from 8-bit PPG mode.
R/W: Readable/writable
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CHAPTER 10 PPG
10.3 Registers of PPG
MB91490 Series
10.3.1
PPG Operation Mode Control Registers
(PPGC0 to PPGC7)
The PPG operation mode control registers can make interrupt, operation mode,
prescaler, and other settings.
■ PPG Operation Mode Control Registers (PPGC0 to PPGC7)
PPG operation mode control registers (PPGC0 to PPGC7)
Address
bit7
bit6
bit5
bit4
bit3
ch.0: 000108H to
ch.7: 000117H
bit2
bit1
bit0
PIE
PUF
INTM
PCS1
PCS0
MD1
MD0
TTRG
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
00000000B
R/W: Readable/writable
[bit7] PIE (Ppg Interrupt Enable): PPG interrupt enable bit
This bit enables or disables PPG interrupts as follows:
0
Disables PPG interrupts.
1
Enables PPG interrupts.
•An interrupt request occurs when the PUF bit is set to "1" with this bit containing "1".
•No interrupt request occurs with this bit containing "0".
•The bit is initialized to "0" by a reset.
•The bit is readable and writable.
[bit6] PUF (Ppg Underflow Flag): PPG counter underflow bit
This bit indicates the detection status of a PPG counter underflow as follows:
0
Indicates that no PPG counter underflow has been detected.
1
Indicates that the PPG counter underflow has been detected.
•This bit is set to "1" on occurrence of an underflow when the count value for each channel changes
from "00H" to "FFH" in either 8-bit PPG 2-channel mode or 8-bit prescaler + 8-bit PPG mode.
•In 16-bit PPG 1-channel mode, the bit is set to "1" on occurrence of an underflow when the count value
of ch(n+1)/ch(n) (n = 0/2/4/6) changes from "0000H" to "FFFFH".
•Writing "0" to the bit set it to "0".
•Writing "1" to this bit is meaningless.
•The bit returns "1" when read of a read modify write (RMW) instruction.
•The bit is initialized to "0" by a reset.
•The bit is readable and writable.
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10.3 Registers of PPG
MB91490 Series
[bit5] INTM (Interrupt Mode): Interrupt mode bit
This bit allows the PUFn bit to detect only the underflow from PRLBH.
0
The PUF bit is set to "1" when the underflow occurs.
1
The PUFn bit is set to "1" only when the underflow from PRLBHn occurs.
•The bit is initialized to "0" by a reset.
•The bit is readable and writable.
•Setting this bit to "1" allows an interrupt to occur when one cycle of the PPG waveform is output.
•Do not rewrite this bit with interrupts enabled.
[bit4, bit3] PCS1, PCS0 (Ppg Count Select): Count clock select bits
These bits select the operating clock for the down counter as follows:
PCS1
PCS0
Operation mode
0
0
Peripheral clock (CLKP) (25-ns peripheral clock at 40 MHz)
0
1
Peripheral clock (CLKP) /4 (100-ns peripheral clock at 40 MHz)
1
0
Peripheral clock (CLKP) /16 (400-ns peripheral clock at 40 MHz)
1
1
Peripheral clock (CLKP) /64 (1.6-s peripheral clock at 40 MHz)
•These bits are initialized to "00B" by a reset.
•The bits are readable and writable.
[bit2, bit1] MD1, MD0 (ppg count MoDe): Operation mode select bits
These bits select the operation mode of the PPG timer as follows:
MD1
MD0
Operation mode
0
0
8-bit PPG 2-channel independent mode
0
1
8-bit prescaler + 8-bit PPG mode
1
0
16-bit PPG mode
1
1
16-bit prescaler + 16-bit PPG mode
•These bits are initialized to "00B" by a reset.
•The bits are readable and writable.
•The bits exist only for even-numbered channels.
[bit0] TTRG (Timing TRGer): Timing trigger select bit
This bit allows the PPG to get started only with the trigger signal from the timing generator.
0
Starts the PPG in response to the TRG register or multi-function timer.
1
Starts the PPG only in response to the timing generator.
•The bit is initialized to "0" by a reset.
•The bit is readable and writable.
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CHAPTER 10 PPG
10.3 Registers of PPG
MB91490 Series
10.3.2
Reload Registers (PRLH0 to PRLH7, PRLL0 to PRLL7)
Reload registers can hold the reload values for the down counter.
■ Reload Registers (PRLH0 to PRLH7, PRLL0 to PRLL7)
Reload registers H (PRLH0 to PRLH7)
Address
ch.0: 000100H
to
ch.7: 000112H
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
PEN07
PEN06
PEN05
PEN04
PEN03
PEN02
PEN01
PEN00
PEN07
PEN06
PEN05
PEN04
PEN03
PEN02
PEN01
PEN00
PEN07
PEN06
PEN05
PEN04
PEN03
PEN02
PEN01
N00
PEN07
PEN06
PEN05
PEN04
PEN03
PEN02
PEN01 PE
PEN00
PEN07
PEN06
PEN05
PEN04
PEN03
PEN02
PEN01
PEN00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
XXXXXXXXB
R/W
Reload registers L (PRLL0 to PRLL7)
bit 7
Address
ch.0: 000101H
to
ch.7: 000113H
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PEN07
PEN06
PEN05
PEN04
PEN03
PEN02
PEN01
PEN00
PEN07
PEN06
PEN05
PEN04
PEN03
PEN02
PEN07
PEN06
PEN05
PEN04
PEN03
PEN01
N00
PEN07
PEN06
PEN05
PEN04
PEN03
PEN02
PEN01 PE
PEN00
PEN07
PEN06
PEN05
PEN04
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
XXXXXXXXB
R/W
R/W: Readable/writable
Register Name
Function
PRLL
Holds the "L"-side reload value.
PRLH
Holds the "H"-side reload value.
Note:
When the PPG is used either in 8-bit prescaler + 8-bit PPG mode or in 16-bit prescaler + 16-bit PPG
mode, the PPG waveform may vary from cycle to cycle if the prescaler-side PRLL and PRLH
registers are set to different values. They should therefore be set to the same value.
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CHAPTER 10 PPG
10.3 Registers of PPG
10.3.3
MB91490 Series
PPG Trigger Register (TRG)
The PPG trigger register can enable the operation of each PPG.
■ PPG Trigger Register (TRG)
PPG trigger register (TRG)
Address
000131H
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
PEN07 PEN06 PEN05 PEN04 PEN03 PEN02 PEN01 PEN00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
00000000B
R/W: Readable/writable
[bit7 to bit0] PEN07 to PEN00 (Ppg ENable): PPG operation enable bits
These bits are used to select the PPG operation start and the operation mode:
PEN07 to PEN00
Operation Status
0
Stops the PPG from operating (while holding the output at "L" level).
1
Enables the PPG to operate.
•The bits are initialized to "0" by a reset.
•The bits are readable and writable.
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CHAPTER 10 PPG
10.3 Registers of PPG
MB91490 Series
10.3.4
Output Inversion Register (REVC)
The output inversion register can enable the inverted output of each PPG output value.
■ Output Inversion Register (REVC)
Output inversion register (REVC)
bit7
bit6
Address
000135H
bit5
bit4
bit3
bit2
bit1
bit0
REV07 REV06 REV05 REV04 REV03 REV02 REV01 REV00 Initial value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000000B
R/W: Readable/writable
[bit7 to bit0] REV07 to REV00: Output inversion bits
These bits are used to invert the PPG output values including the initial level.
REV07 to REV00
Output Level
0
Normal
1
Inverted
•The bits are initialized to "0" by a reset.
•The bits are readable and writable.
•As the register simply inverts the PPG output, it inverts the initial level as well. It also exchanges the
"L" and "H" relationships between reload registers with each other.
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CHAPTER 10 PPG
10.3 Registers of PPG
10.3.5
MB91490 Series
GATE Function Control Registers (GATEC0/GATEC4)
The GATE function control registers can enable the PPG to start/stop in response to the
signal from the multi-function timer.
■ GATE Function Control Registers (GATEC0/GATEC4)
GATE function control register (GATECn)
Address
bit7
bit6
bit5
ch.0: 000133H
ch.4: 000137H
-
-
R/W
R/W
bit4
bit3
bit2
-
-
R/W
R/W
STGR(n+2) EDGE(n+2)
R/W
R/W
bit1
bit0
STGR(n) EDGE(n)
R/W
Initial value
ch.0 : --00--00B
ch.4 : ------00B
R/W
R/W: Readable/writable
n = 0, 4
[bit5, bit1] STGR: Gate function select bits
These bits are used to select whether to use the trigger signal from the multi-function timer or the TRG
register to start the PPG as follows:
STGR
Operation mode
0
Starts the PPG according to the TRG register.
1
Starts the PPG in response to the trigger signal from the multi-function timer.
•The bits are initialized to "0" by a reset.
•The bits are readable and writable.
[bit4, bit0] EDGE: Trigger edge select bits
These bits are used to select the trigger edge from the multi-function timer as follows:
EDGE
Operation Mode
0
Start at the rising edge -> Stop at the falling edge *1
1
Start at the falling edge -> Stop at the rising edge *2
•The bits are initialized to "0" by a reset.
•The bits are readable and writable.
*1: The PPG remains on with the signal at the "H" level.
*2: The PPG remains on with the signal at the "L" level.
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CHAPTER 10 PPG
10.4 Operation Explanation of PPG
MB91490 Series
10.4
Operation Explanation of PPG
MB91490 series has 8 channels for 8-bit PPG and can operate four modes in total:
independent mode, 8-bit prescaler + 8-bit PPG mode, 16-bit PPG 1 channel mode, and
16-bit prescaler + 16-bit PPG mode.
■ Operation Explanation
Each of 8-bit length PPG units has two 8-bit-length reload registers for the "L" and "H" sides (PRLL,
PRLH). The "L"-side and "H"-side values written to this register are alternately reloaded to the 8-bit downcounter (PCNT) which counts down on each cycle of the count clock. The value of the pin output (PPG) is
toggled each time a counter borrow occurs to trigger another reload. With this operation, the pin output
(PPG) becomes a pulse output, which has "L"/"H" width corresponding to the value of reload register.
The operation starts/restarts when the bit of the register is written.
The relationship between the reload operation and the pulse output is shown below.
Reload operation
Pin output change
PRLH  PCNT
PPG [0  1]
PRLL  PCNT
PPG [1  0]
When bit7 (PIEn) of the PPGCn register is "1", an interrupt request is output when the counter goes from
"00H" to "FFH" causing a borrow (or a borrow from "0000H" to "FFFFH" in 16-bit PPG mode). (n = 0 to 7)
● Operation Modes
There are four operation modes: independent mode, 8-bit prescaler + 8-bit PPG mode, 16-bit PPG 1
channel mode, and 16-bit prescaler + 16-bit PPG mode.
• In the independent mode, a channel can operate as 8-bit PPG independently. The PPG output of ch.(n) is
connected to PPG(n) pin. (n = 0 to 7)
• The 8-bit prescaler + 8-bit PPG mode makes 1 channel operate as an 8-bit prescaler, counts its borrow
output, and then allows the 8-bit PPG waveform in any cycle to be output. For example, the prescaler
output of ch.0 is connected to the PPG0 pin; the PPG output of ch.1 is connected to the PPG1 pin.
• In the 16-bit PPG 1 channel mode, two channels are combined, and the combined channel operates as
16-bit PPG. For example, if ch.0 and ch.1 are combined, 16-bit PPG outputs are connected to both
PPG0 pin and PPG1 pin.
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CHAPTER 10 PPG
10.4 Operation Explanation of PPG
MB91490 Series
● PPG Output Operation
The PPG in this block is activated and starts counting when the bit corresponding to each channel in the
TRG register (PPG trigger register) is set to "1". After operation starts, the count operation is stopped when
each channel bit of TRG register is set to 0. After having stopped, the pulse output holds "L" level.
Do not set the PPG channel as the operating state, with the prescaler channel as the stopped state, in the 8bit prescaler + 8-bit PPG mode and the 16-bit prescaler + 16-bit PPG mode.
In 16-bit PPG mode, use the PENn bits for each channel in the TRG register to simultaneously start and
stop operation. (n = 0 to 7)
PPG output operation is explained below.
In PPG operation, the pulse wave with any frequency/duty ratio (the ratio between "H" level period and "L"
level period in pulse wave) is output continuously. If the pulse wave output is started, PPG will not stop it
before operation stop is set.
PENn
Output Pin
Operation
start by PENn
(from L-side)
PPG
T x (L+1)
T x (H+1)
Start
n = 0 to 7
Peripheral
(CLKP)
PPG output operation output waveform
● Relationship between Reload Value and Pulse Width
The pulse width to be output is the value that multiplies the cycle of the count clock by the value in the
reload register plus 1. Note that the pulse width will be one cycle of the count clock when the reload
register value is set to "00H" at operating the 8-bit PPG and when the reload register value is set to "0000H"
at operating the 16-bit PPG. Note that the pulse width will be 256 cycles of the count clock when the reload
register value is set to "FFH" at operating the 8-bit PPG and the pulse width will be 65536 cycles of the
count clock when the reload register value is set to "FFFFH" at operating the 16-bit PPG.
The equations for calculating the pulse width are shown below:
Pl = T × (L + 1)
Ph = T × (H + 1)
196
{
L
H
T
Ph
Pl
: PRLL value
: PRLH value
: Period of input clock
: "H" pulse width
: "L" pulse width
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CHAPTER 10 PPG
10.4 Operation Explanation of PPG
MB91490 Series
● Count Clock Selection
The count clock to be used are the same input for the peripheral clock (CLKP), and can be selected from
one of the following four types of count clock inputs.
The count clock operates as shown below.
PPGC0 to PPGC7 registers
Count clock operation
PCS1
PCS0
0
0
Count clock is counted for peripheral clock (CLKP)
0
1
Count clock is counted for 4 cycles of peripheral clock (CLKP)
1
0
Count clock is counted for 16 cycles of peripheral clock (CLKP)
1
1
Count clock is counted for 64 cycles of peripheral clock (CLKP)
Note that, in 8-bit prescaler + 8-bit PPG mode and 16-bit prescaler + 16-bit PPG mode, the period of the
initial count may vary if the PPG is started when the prescaler is running and the PPG is halted.
● Control of Pulse Pin Output
The pulse output generated by operating this module can be output from external pins (PPG4 to PPG6).
As both PPG(m) and PPG(m + 1) output the same waveform in 16-bit PPG mode (m = 0, 2, 4, 6), the same
output can be obtained whichever of these is enabled as an external output pin.
In the 8-bit prescaler + 8-bit PPG mode and the 16-bit prescaler + 16-bit PPG mode, the 8-bit prescaler
toggle waveform is output on the prescaler side, and the 8-bit PPG waveform is output on the PPG side.
The following shows an example of the output waveform in this mode.
Figure 10.4-1 8 + 8 PPG Output Operation Output Waveform (Example ch.1/ch.0)
Ph1
PPG1
(prescaler side)
Pl1
PPG0
(PPG side)
Ph0
Pl0
L1
Pl1= T x (L1 + 1)
Ph1= T x (L1 + 1)
Pl0= T x (L1 + 1) x (L0 + 1)
Ph0= T x (L1 + 1) x (H0 + 1)
Note:
CM71-10155-2E
Setting the same value to PRLL
and PRLH for ch.1 is
recommended.
L0
H0
T
Ph0
PI0
Ph1
PI1
: ch.1 PRLL value and
ch.1 PRLH value
: ch.0 PRLL value
ch.0 PRLH value
: Period of input clock
: "H" pulse width of PPG0
: "L" pulse width of PPG0
: "H" pulse width of PPG1
: "L" pulse width of PPG1
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CHAPTER 10 PPG
10.4 Operation Explanation of PPG
MB91490 Series
● Interrupt
The interrupt on this module becomes active when a reload value is counted out and a borrow occurs.
However, the interrupt only goes to active if the INTMn bit is "1" when an underflow (borrow) occurs for
PRLBHn. The interrupt occurs when H width pulse ends.
In the 8-bit PPG mode and the 8-bit prescaler +8-bit PPG mode, an interrupt request is performed by the
relevant counter borrow. However, in 16-bit PPG mode and 16-bit prescaler +16-bit PPG mode, PUF(m)
and PUF(m+1) are concurrently set by the borrow of the 16-bit counter. For this reason, it is recommended
that either PIE (m) or PIE (m + 1) is enabled in order to unify the interrupt sources. Similarly, it is
recommended that you write to PUF(m) and PUF(m + 1) simultaneously when clearing the interrupt
source. (m = 0, 2, 4, 6)
● GATE Function
By using the multi-function timer signal, PPG can be: started-stopped.
• In the 8-bit PPG mode and the 8-bit prescaler + 8-bit PPG mode, this function can activate the PPG
ch.(n).
• In the 16-bit PPG mode and the 16-bit prescaler + 16-bit PPG mode, this function can activate the PPG
ch. (n), ch. (n+1).
The activation for each mode is determined by the MD register for each PPG.
• When PPG ch. (n): MD1, MD0 = 0, X, PPG ch. (n) is started (8-bit PPG)
• When PPG ch. (n): MD1, MD0 = 1, X, PPG ch. (n), ch. (n+1) are started (16-bit PPG)
EDGE bit and the multi-function timer signal can control the period when PPG activation is valid.
n = 0/2/4 (multi-function timer 0)
Figure 10.4-2 PPG Count Operation Based on EDGE Bit and Multi-function Timer
EDGE = 0 (Start on rising edge
stop on falling edge)
Multifunction timer
signal
PPG count
Start
Stop
EDGE = 1 (Start on falling edge
Start
stop on rising edge)
Multifunction timer
signal
PPG count
Start
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Stop
Start
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CM71-10155-2E
CHAPTER 10 PPG
10.4 Operation Explanation of PPG
MB91490 Series
● Initial values for hardware
Each hardware is initialized by a reset as shown below.
< Register >
PPGC(n)

00000000B
TRG

00000000B
REVC

00000000B
GATEC0 XX00XX00B
GATEC4  XXXXXX00B
< Pulse output >
PPG(n)

"L"
< Interruption request >
IRQ(n)

"L"
(n = 0 to 7)
Any hardware other than those above is not initialized.
● PPG combinations
ch.0: PPGC
ch.2: PPGC
MD1
MD0
MD1
MD0
0
0
0
0
0
0
ch.0
ch.1
ch.2
ch.3
0
8-bit PPG
8-bit PPG
8-bit PPG
8-bit PPG
0
1
8-bit PPG
8-bit PPG
8-bit PPG
8-bit prescaler
0
1
0
8-bit PPG
8-bit PPG
0
0
1
1
0
1
0
0
8-bit PPG
8-bit prescaler
8-bit PPG
8-bit PPG
0
1
0
1
8-bit PPG
8-bit prescaler
8-bit PPG
8-bit prescaler
0
1
1
0
8-bit PPG
8-bit prescaler
0
1
1
1
1
0
0
0
16-bit PPG
8-bit PPG
8-bit PPG
1
0
0
1
16-bit PPG
8-bit PPG
8-bit prescaler
1
0
1
0
16-bit PPG
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
16-bit PPG
Setting disabled
16-bit PPG
Setting disabled
16-bit PPG
Setting disabled
16-bit PPG
16-bit prescaler
The operations for ch.4 to ch.7 can be combined in the same way as for ch. (0, 1, 2, 3).
Replace as shown below.
ch.0 = ch.4
ch.1 = ch.5
ch.2 = ch.6
ch.3 = ch.7
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CHAPTER 10 PPG
10.4 Operation Explanation of PPG
200
MB91490 Series
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
CHAPTER 11
MULTI-FUNCTION TIMER
This chapter explains the overview of the multi-function
timer, the configuration and functions of registers, and
operation of the multi-function timer.
11.1 Overview of the Multi-function Timer
11.2 Block Diagram of the Multi-function Timer
11.3 Pins of the Multi-function Timer
11.4 Multi-function Timer Register
11.5 Multi-function Timer Interrupt
11.6 Operation of the Multi-function Timer
11.7 Notes on Using the Multi-function Timer
11.8 Example Program for Multi-function Timer
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CHAPTER 11 MULTI-FUNCTION TIMER
11.1 Overview of the Multi-function Timer
11.1
MB91490 Series
Overview of the Multi-function Timer
Multi-function timer consists of three 16-bit free-run timer, six 16-bit output compares,
four 16-bit input captures, one waveform generator, and two A/D activation compares. If
this waveform generator is used with the PPG timer, 6 different waveforms can be
output from the 16-bit free-run timer, an input pulse width and an external clock cycle
can be measured.
■ Structure of Multi-function Timer
● 16-bit free-run timer (× 3)
• The 16-bit free-run timer consists of 16-bit up/down counters, control registers, 16-bit compare clear
registers (with buffer registers), and prescalers.
• Nine different counter operating clocks are available (, /2, /4, /8, /16, /32, /64, /128, and /256).
( : Peripheral clock (CLKP))
• A compare clear interrupt is generated when a compare clear register compares and matches 16-bit freerun timer. A zero-detection interrupt is generated while the 16-bit free-run timer detects a count value
"0".
• A compare clear register has selectable buffer registers. (Data written to this buffer register is transferred
to a compare clear register.) When the 16-bit free-run timer is stopped and data is written to the buffer,
the transfer is performed immediately. When the timer value "0" is detected during the 16-bit free-run
timer operation, data is transferred from the buffer.
• When a compare match with a reset, a software clear, or a compare clear register occurs in the up count
mode, the counter value is reset to "0000H".
• This counter output value can be used as a multi-function timer output compare and an input capture
clock count.
• When a zero-detection or a compare match occurs, A/D can be activated.
• The connections between the free-run timer and the resource can be set by the free-run timer selector or
the resource input selector.
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CHAPTER 11 MULTI-FUNCTION TIMER
11.1 Overview of the Multi-function Timer
MB91490 Series
● 16-bit output compare (× 6)
• The 16-bit output compare consists of six 16-bit compare registers (with selectable buffer registers),
compare output latches, and compare control registers. An interrupt is generated and the output level is
inverted when a match occurs between the value of the selected 16-bit free-run timer and the compare
register.
• Six compare registers can be operated independently. An output pin and an interrupt flag are assigned to
each compare register.
• Two compare registers can be paired to control an output pin. The output pin can be reversed with using
two compare registers together.
• The initial value of each output pin can be set.
• An interrupt can be generated when the output compare register matches the 16-bit free-run timer.
• Any channel of free-run timer for each compare unit can be set.
● 16-bit input capture (× 4)
• The input capture consists of four independent external input pins, and capture registers and capture
control registers associated to these pins. Detection of an edge on the input signal from the external pin
causes the value of the selected 16-bit free-run timer to be stored to the capture register and an interrupt
to be generated.
• The trigger edge for the external input signal can be selected from the three types: Rising edge, falling
edge, and both edges. Also there are registers that indicate whether the trigger edge is a rising edge or a
falling edge.
• Four input capture can be used independently.
• An interrupt can be generated when a valid edge of an external input signal is detected.
• The input free-run timers of input capture unit can be configured.
● 8/16-bit PPG timer (× 8)
• The PPG ch.0/ch.2/ch.4 are used for the output waveform to the waveform generator.
• See "CHAPTER 10 PPG" for details of the PPG timer.
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CHAPTER 11 MULTI-FUNCTION TIMER
11.1 Overview of the Multi-function Timer
MB91490 Series
● Waveform generator
• The waveform generator consists of three 16-bit dead timer registers, three timer control registers, and
one 16-bit waveform control register.
• The waveform generator can generate real-time output, 16-bit PPG waveform output, non-overlap 3phase waveform output (for inverter control), and DC chopper waveform output.
• The non-overlap waveform output can be generated on the basis of the dead time of the 16-bit dead
timer (dead time timer function).
• The non-overlap waveform output can be generated when the real-time output is activated in 2 channel
mode (dead time timer function).
• When a real-time output compare match is detected, GATE signal is generated to start or stop the PPG
timer operation (GATE function).
• When a real-time output compare match is detected, the 16-bit dead timer becomes active. With
generating the GATE signal for controlling the PPG operation, the input PPG timer can be started or
stopped easily (GATE function).
• DTTI pins can be used to control stopping forcibly.
• DTTI registers can be used to control stopping forcibly.
● A/D activation compare (× 2)
• The A/D can be activated when the a match occurs between the value of the 16-bit free-run timer and
the compare register. The 16-bit free-run timer ch.0/ch.1/ch.2 is selected as the free-run timer input.
• The A/D can be activated when the free-run timer value is corresponding to the compare register at upcounting 16-bit free-run timer.
• The A/D can be activated when the free-run timer value is corresponding to the compare register at
down-counting 16-bit free-run timer.
• The A/D can be activated when the free-run timer value is corresponding to the compare register at up/
down-counting 16-bit free-run timer.
• A separate value can be set to the two compare registers respectively. The A/D can be activated when
the free-run timer value is corresponding to the compare register 0 at up-counting 16-bit free-run timer.
And the A/D can be activated when the free-run timer value is corresponding to the compare register 1
at down-counting 16-bit free-run timer.
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CHAPTER 11 MULTI-FUNCTION TIMER
11.2 Block Diagram of the Multi-function Timer
MB91490 Series
11.2
Block Diagram of the Multi-function Timer
This section shows the block diagram of the multi-function timer.
R-bu s
■ Block Diagram of the Multi-function Timer
DT TI 0(PP5 )
DTTI0 falling edge
detection interrupt
Dead timer interrupt
RT O0(PQ0)
PPG0/2/ 4
GA TE 0/2/4
Waveform
generator
0
Output compare interrupt
0-5
16-bit
free-run timer
0-2
Zero-detection
compare clear
0-2
Timer 0-2
16-bit output
compare
0-5
RT0- 5
RT O5(PQ5)
IC 0(PP0 )
Timer 0-2
16-bit reload timer 1
timer output
CM71-10155-2E
RT O4(PQ4)
Free-run
timer
selector
CK I0
(PP4 )
16-bit intput
capture
0-3
IC 1(PP1 )
IC 2(PP2 )
Zero-detection
compare clear
0-2
IC 3(PP3 )
Timer 0-2
Input capture interrupt
0-3
RT O2(PQ2)
RT O3(PQ3)
Timer 0-2
Free-run timer interrupt
0-2
RT O1(PQ1)
AD TG 0
To 10-bit A/D converter 2
AD TG 2
To 10-bit A/D converter 1
A/D activation
compare
0
TI N2
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CHAPTER 11 MULTI-FUNCTION TIMER
11.2 Block Diagram of the Multi-function Timer
MB91490 Series
R-bus
■ Block Diagram of 16-bit Free-run Timer
Compare clear buffer
register 0-2
(CPCLRB0-2)
TCCSL0-2
BFE
CKI0
(PP4)
1
Peripheral clock (CLKP)
0
Divided by 1 to 256
CLK[3 :0]
ECKE
TCCSL0-2
TCCSH0-2
Compare clear register
0-2
(CPCLR0-2)
16-bit free-run timer
0-2
STOP
TCCSH0-2 MSI[2:0]
TCCSM0-2
MODE
Timer 0-2
SCLR
TCCSL0-2
To free-run timer selector
To A/D activation compare 0
Zerodetection
circuit
Zero-detection
compare clear
0-2
Interrupt
generation
circuit
Interrupt
generation
circuit
MODE2 MSI[5:3]
TCCSH0-2 IRQZE
Compare clear 0-2
Compare
circuit
IRQZF
ICRE
ICLR
Compare clear
interrupt 0-2
Zero-detecction
interrupt 0-2
1 ADTRGC0-2
AD0E
0
SEL0
ADTRGC0-2
To A/D activation
compare 0
1 ADTRGC0-2
AD2E
0
SEL2
206
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ADTRGC0-2
CM71-10155-2E
CHAPTER 11 MULTI-FUNCTION TIMER
11.2 Block Diagram of the Multi-function Timer
MB91490 Series
R-bus
■ Block Diagram of the 16-bit Output Compare
OCSL0 BUF0
Buffer enable
Output compare buffer register 0
(OCCPB0)
OCSH1
Zero-detection
BTS0
Compare clear
Output compare register 0
(OCCP0)
Compare
circuit
Free-run timer output
OCSL0 BUF1
Buffer enable
Output compare buffer register 1
(OCCPB1)
OCSH1 CMOD
BTS1
Compare clear
Output compare register 1
(OCCP1)
Interrupt 0
OCSL2 BUF0
Buffer enable
RT1
Compare
circuit
Free-run timer output
ICE1
ICP1
OCSL0
Output compare buffer register 2
(OCCPB2)
To waveform generator 0
Interrupt 1
OCSH3
Zero-detection
BTS0
Compare clear
Output compare register 2
(OCCP2)
Compare
circuit
Free-run timer output
OCSL2 BUF1
Buffer enable
Output compare buffer register 3
(OCCPB3)
OCSH3 CMOD
RT2
ICE0
ICP0
OCSL2
To waveform generator 0
Interrupt 2
OCSH3
Zero-detection
BTS1
Compare clear
Output compare register 3
(OCCP3)
OCSL4 BUF0
Buffer enable
RT3
Compare
circuit
Free-run timer output
ICE1
ICP1
OCSL2
Output compare buffer register 4
(OCCPB4)
To waveform generator 0
Interrupt 3
OCSH5
Zero-detection
BTS0
Compare clear
Output compare register 4
(OCCP4)
Compare
circuit
Free-run timer output
OCSL4 BUF1
Buffer enable
Output compare buffer register 5
(OCCPB5)
OCSH5 CMOD
RT4
ICE0
ICP0
OCSL4
To waveform generator 0
Interrupt 4
OCSH5
Zero-detection
BTS1
Compare clear
Output compare register 5
(OCCP5)
RT5
Compare
circuit
Free-run timer output
CM71-10155-2E
ICE0
ICP0
OCSL0
To waveform generator 0
OCSH1
Zero-detection
From free-run
timer selector
(after selecting
free-run timers 0 to 2)
RT0
FUJITSU SEMICONDUCTOR LIMITED
ICE1
ICP1
OCSL4
To waveform generator 0
Interrupt 5
207
CHAPTER 11 MULTI-FUNCTION TIMER
11.2 Block Diagram of the Multi-function Timer
MB91490 Series
R-bus
■ Block Diagram of the 16-bit Input Capture
PICSH01
IEI0
Free-run timer output
Intput capture data register 0
(IPCP0)
Edge detection
EG01
EG00
ICP0
ICE0
PICSL01
Intput capture data register 1
(IPCP1)
PICSH01
Edge detection
EG11
From free-run
timer selector
(after selecting
free-run timers 0 to 2)
EG10
ICP1
ICE1
PICSL01
Intput capture data register 2
(IPCP2)
ICSH23
EG20
ICP2
ICE2
ICSL23
Intput capture data register 3
(IPCP3)
IC2(PP2)
ICSL23
Interrupt 2
ICSH23
IEI3
Edge detection
EG31
ICP3
ICE3
ICSL23
208
PICSL01
Edge detection
EG21
Free-run timer output
IC1(PP1)
Interrupt 1
IEI2
Free-run timer output
PICSL01
Interrupt 0
IEI1
Free-run timer output
IC0(PP0)
EG30
IC3(PP3)
ICSL23
Interrupt 3
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
CHAPTER 11 MULTI-FUNCTION TIMER
11.2 Block Diagram of the Multi-function Timer
MB91490 Series
R-bus
■ Block Diagram of the Waveform Generator
DMOD0
DTCR0
GTEN[1: 0]
TMD[2: 0]
RT0/RT1
(From 16-bit output
compare 0/1)
(U)
RTO0(PQ0)
SIGCR20
PSEL0[1:0 ]
Various waveform
generation circuits
Output
control
RTO1(PQ1)
GATE0
(X)
GATE1
16-bit dead timer register 0
(TMRR0)
16-bit dead timer register 0
TMIF0
TMIE0
DTCR0
PGEN[1:0]
PICSH01
Compare/
dead time
generation circuit
Interrupt 0
DMOD1
DTCR1
GTEN[3: 2]
TMD[5: 3]
RT2/RT3
(From 16-bit output
compare 2/3)
(V)
RTO2(PQ2)
SIGCR20
PPG0
PPG2
PPG4
GATE0
GATE2
GATE4
PSEL1[1:0 ]
PSEL0[1:0 ]
PSEL1[1:0 ]
PSEL2[1:0 ]
SIGCR20
DCK[2 :0]
SIGCR10
Output
control
RTO3(PQ3)
GATE2
(Y)
GATE3
16-bit dead timer register 1
(TMRR1)
Peripheral clock
(CLKP)
Various waveform
generation circuits
16-bit dead timer register 1
TMIF1
TMIE1
DTCR1
PGEN[3:2]
PICSH01
Compare/
dead time
generation circuit
Interrupt 1
DMOD2
DTCR2
GTEN[5: 4]
TMD[8: 6]
RT4/RT5
(From 16-bit output
compare 4/5)
(W)
RTO4(PQ4)
SIGCR20
PSEL2[1:0 ]
Various waveform
generation circuits
Output
control
GATE4
RTO5(PQ5)
(Z)
GATE5
16-bit dead timer register 2
(TMRR2)
16-bit dead timer register 2
Compare/
dead time
generation circuit
PGEN[5:4]
PICSH01
SIGCR10
TMIF2
TMIE2
DTCR2
CM71-10155-2E
Interrupt 2
NWS[1:0]
FUJITSU SEMICONDUCTOR LIMITED
DTTI
control
circuit
Noise
cancel
circuit
SIGCR10
NRSL
DTIF
DTIE
DTTI0 interrupt
SIGCR20
DTTI
DTTI0(PP5)
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CHAPTER 11 MULTI-FUNCTION TIMER
11.2 Block Diagram of the Multi-function Timer
MB91490 Series
Free-run timers 0 to 2
zero- detection
or compare clear
R-bus
■ Block Diagram of the A/D Activation Compare
Select
ADTGSEL0
Compare buffer register 0
(ADCOMPB0)
SEL0[1:0 ]
ADTGBUF0
BTS0 BUFX0
Compare register 0
(ADCOMP0)
Free- run timer selector
CE0[1:0]
ADTG0
(To 10-bit A/D converter 2)
Compare
circuit
Compare enable
Free-run timers 0
Free-run timers 1
Free-run timers 2
16-bit reload timer 1
timer output
Free-run timers 0 to 2
zero- detection
or compare clear
Select
ADTGSEL0
Compare buffer register 2
(ADCOMPB2)
SEL2[1:0 ]
ADTGBUF0
BTS2 BUFX2
0
Compare register 2
(ADCOMP2)
Compare
circuit
ADTG2
(To 10-bit A/D converter 1)
1
Free- run timer selector
ADTRGE2
(Free-run timer 2)
CE2[1:0]
ADTGCE0
AD2E
Compare enable
A/D trigger output enable
R-bus
■ Block Diagram of the Free-run Timer Selector
FRS0-2
Timer output (Free-run timer 0)
Timer output (Free-run timer 1)
Timer output (Free-run timer 2)
Zero-detection (Free-run timer 0)
Zero-detection (Free-run timer 1)
Zero-detection (Free-run timer 2)
Timer output/zero-detection/compare clear
Timer output/zero-detection/compare clear
Timer output/zero-detection/compare clear
FSOn
(n=Integer)
Timer output/zero-detection/compare clear
Timer output/zero-detection/compare clear
Compare clear (Free-run timer 0)
Compare clear (Free-run timer 1)
Compare clear (Free-run timer 2)
Timer output/zero-detection/compare clear
To 16-bit output compare 0
To 16-bit output compare 1
To 16-bit output compare 2
To 16-bit output compare 3
To 16-bit output compare 4
To 16-bit output compare 5
FRS3-4
Timer output
Timer output
FSln
(n=Integer)
Timer output
Timer output
210
FUJITSU SEMICONDUCTOR LIMITED
To 16-bit intput capture 0
To 16-bit intput capture 1
To 16-bit intput capture 2
To 16-bit intput capture 3
CM71-10155-2E
CHAPTER 11 MULTI-FUNCTION TIMER
11.3 Pins of the Multi-function Timer
MB91490 Series
11.3
Pins of the Multi-function Timer
This section describes the pins of the multi-function timer.
■ Pins of the Multi-function Timer
Table 11.3-1 Pins of the Multi-function Timer 0
Pin name
Pin function
I/O Type
PP5/DTTI0
Port P, I/O, DTTI
PP4/CKI0
Port P, I/O, External clock
PP0/IC0
Port P, I/O, Input capture 0
PP1/IC1
Port P, I/O, Input capture 1
PP2/IC2
Port P, I/O, Input capture 2
PP3/IC3
Port P, I/O, Input capture 3
PQ0/RTO0 (U)
Port Q, I/O, RTO0
PQ1/RTO1 (X)
Port Q, I/O, RTO1
PQ2/RTO2 (V)
Port Q, I/O, RTO2
PQ3/RTO3 (Y)
Port Q, I/O, RTO3
CMOS output,
CMOS hysteresis
input
Pull-up
option
Standby
control
Selectable
PQ4/RTO4 (W) Port Q, I/O, RTO4
PQ5/RTO5 (Z)
Port Q, I/O, RTO5
Yes
Pin setting
Set a pin as input port
(DDRP: bit5 = 0)
Set a pin as input port
(DDRP: bit4 = 0)
Set a pin as input port
(DDRP: bit0 = 0)
Set a pin as input port
(DDRP: bit1 = 0)
Set a pin as input port
(DDRP: bit2 = 0)
Set a pin as input port
(DDRP: bit3 = 0)
Set RTO0 output
(DDRQ: bit0 = 1)
Set RTO1 output
(DDRQ: bit1 = 1)
Set RTO2 output
(DDRQ: bit2 = 1)
Set RTO3 output
(DDRQ: bit3 = 1)
Set RTO4 output
(DDRQ: bit4 = 1)
Set RTO5 output
(DDRQ: bit5 = 1)
DDRx: Port direction register
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CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
11.4
MB91490 Series
Multi-function Timer Register
This section describes the multi-function timer 0 registers.
■ 16-bit Free-run Timer Register
Compare clear buffer register , Compare clear register (Upper)
CPCLRBHn/CPCLRHn
CPCLRBH Write
CPCLRH Read
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
CL15
CL14
CL13
CL12
CL11
CL10
CL09
CL08
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
bit2
bit1
bit0
Initial value
11111111 B
Address :
ch.0 : 0000B4 H
ch.1 : 0000BC H
ch.2 : 0000C4 H
Compare clear buffer register , Compare clear register (Lower)
CPCLRBLn/CPCLRLn
bit6
bit5
bit4
bit3
bit7
CL07
CL06
CL05
CL04
CL03
CL02
CL01
CL00
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
T15
T14
T13
T12
T11
T10
T09
T08
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Timer data register (Lower)
TCDTLn
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
T07
T06
T05
T04
T03
T02
T01
T00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CPCLRBL Write
CPCLRL Read
Initial value
11111111 B
Timer data register (Upper)
TCDTHn
Address :
ch.0 : 0000B6
ch.1 : 0000BE
ch.2 : 0000C6
H
H
H
Initial value
00000000 B
Initial value
00000000 B
R/W: Readable/writable
n = 0/1/2 : FRT0/1/2
(Continued)
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CM71-10155-2E
CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
(Continued)
Timer state control register (Upper)
TCCSHn
Address:
ch.0: 0000B8H
ch.1: 0000C0H
ch.2: 0000C8H
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
ECKE
IRQZF
IRQZE
MSI2
MSI1
MSI0
ICLR
ICRE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
00000000B
Timer state control register (Lower)
TCCSLn
Address:
ch.0 : 0000B9H
ch.1 : 0000C1H
ch.2 : 0000C9H
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
BFE
STOP
MODE
SCLR
CLK3
CLK2
CLK1
CLK0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
-
-
-
-
MODE2
MSI5
MSI4
MSI3
-
-
-
-
R/W
R/W
R/W
R/W
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
01000000B
Timer state control register M
TCCSMn
Address:
ch.0 : 0000BAH
ch.1 : 0000C2H
ch.2 : 0000CAH
A/D trigger control register
ADTRGCn
Address:
ch.0: 0000BBH
ch.1: 0000C3H
ch.2: 0000CBH
bit7
-
SEL2
-
SEL0
-
AD2E
-
-
R/W
-
R/W
-
R/W
-
AD0E
R/W
Initial value
----0000B
Initial value
-000-000B
R/W: Readable/writable
-:
Undefined bit
n = 0/1/2 : FRT0/1/2
CM71-10155-2E
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213
CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
■ Free-run Timer Selection Registers
Free-run timer selection register (Upper) for output compare
FRS1
Address:
FRS1: 0000CEH
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
-
-
FSO13
FSO12
-
-
FSO9
FSO8
-
-
R/W
R/W
-
-
R/W
R/W
Initial value
FRS1
--00--00 B
Free-run timer selection register (Lower) for output compare
FRS0,FRS2
Address:
FRS0: 0000CFH
FRS2: 0000CDH
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
-
-
FSO5
FSO4
-
-
FSO1
FSO0
-
-
R/W
R/W
-
-
R/W
R/W
bit9
bit8
Initial value
FRS0/2
--00--00 B
Free-run timer selection register (Upper) for input capture
FRS4
Address:
FRS4: 0000D2H
bit15
bit14
bit13
bit12
bit11
bit10
-
-
FSI13
FSI12
-
-
FSI9
FSI8
-
-
R/W
R/W
-
-
R/W
R/W
bit3
bit2
bit1
bit0
FSI1
FSI0
R/W
R/W
Initial value
FRS4
--00--00 B
Free-run timer selection register (Lower) for input capture
FRS3
Address:
FRS3: 0000D3H
bit7
bit6
-
-
bit5
bit4
FSI5
FSI4
-
-
-
-
R/W
R/W
-
-
Initial value
FRS3
--00--00 B
R/W: Readable/writable
-:
Undefined bit
214
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CM71-10155-2E
CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
■ 16-bit Output Compare Register
Output compare buffer register, Output compare register (Upper)
OCCPBH0 to OCCPBH5/
OCCPH0 to OCCPH5
OCCPBH Write
OCCPH Read
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
OP15
OP14
OP13
OP12
OP11
OP10
OP09
OP08
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
Initial value
00000000B
Address
ch.0: 0000A0H
ch.1: 0000A2H
ch.2: 0000A4H
ch.3: 0000A6H
ch.4: 0000A8H
ch.5: 0000AAH
Output compare buffer register, Output compare register (Lower)
OCCPBL0 to OCCPBL5/
OCCPL0 to OCCPL5
OCCPBL Write
OCCPL Read
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
OP07
OP06
OP05
OP04
OP03
OP02
OP01
OP00
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
Initial value
00000000B
Compare control register 1,3,5 (Upper)
OCSH1,OCSH3,OCSH5
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
-
BTS1
BTS0
CMOD
-
-
OTD1
OTD0
-
R/W
R/W
R/W
-
-
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
IOP1
IOP0
IOE1
IOE0
BUF1
BUF0
CST1
CST0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
-110--00 B
Address
ch.1: 0000ACH
ch.3: 0000AEH
ch.5: 0000B0H
Compare control register 0,2,4 (Lower)
OCSL0,OCSL2,OCSL4
Address
ch.0: 0000ADH
ch.2: 0000AFH
ch.4: 0000B1H
R/W
Compare mode control register
OCMOD0
bit15
Address
ch.0: 0000B2H
bit14
bit13
bit12
bit11
bit10
bit9
bit8
-
-
MOD15
MOD14
MOD13
MOD12
MOD11
MOD10
-
-
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
00001100B
Initial value
--000000B
R/W: Readable/writable
R:
Read only
W:
Write only
-:
Undefined bit
CM71-10155-2E
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CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
■ 16-bit Input Capture Register
Input capture data register (Upper)
IPCPH0 to IPCPH3
Address
ch.0: 0000D4H
ch.1: 0000D6H
ch.2: 0000D8H
ch.3: 0000DAH
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
CP15
CP14
CP13
CP12
CP11
CP10
CP09
CP08
R
R
R
R
R
R
R
R
Initial value
XXXXXXXXB
Input capture data register (Lower)
IPCPL0 to IPCPL3
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CP07
CP06
CP05
CP04
CP03
CP02
CP01
CP00
R
R
R
R
R
R
R
R
Initial value
XXXXXXXXB
Input capture state control register (ch. 2, ch. 3) (Upper)
ICSH23
Address
ch.0: 0000DEH
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
-
-
-
-
-
-
IEI3
IEI2
-
-
-
-
-
-
R
R
Initial value
------00B
Input capture state control register (ch. 2, ch. 3) (Lower)
ICSL23
Address
ch.0: 0000DFH
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ICP3
ICP2
ICE3
ICE2
EG31
EG30
EG21
EG20
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
00000000B
PPG output control / Input capture state control register (ch. 0, ch. 1) (Upper)
PICSH01
Address
ch.0: 0000DCH
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
PGEN5
PGEN4
PGEN3
PGEN2
PGEN1
PGEN0
IEI1
IEI0
W
W
W
W
W
W
R
R
Initial value
00000000B
Input capture state control register (ch. 0, ch. 1) (Lower)
PICSL01
Address
ch.0: 0000DDH
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ICP1
ICP0
ICE1
ICE0
EG11
EG10
EG01
EG00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
00000000B
R/W: Readable/writable
R: Read only
W: Write only
-:
Undefined bit
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CM71-10155-2E
CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
■ Waveform Generator Register
16-bit dead timer register (Upper)
TMRRH0, TMRRH1, TMRRH2
Address:
Waveform generator0:
ch.0: 0000E0H
ch.1: 0000E2H
ch.2: 0000E4H
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
TR15
TR14
TR13
TR12
TR11
TR10
TR09
TR08
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
TR07
TR06
TR05
TR04
TR03
TR02
TR01
TR00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
XXXXXXXXB
16-bit dead timer register (Lower)
TMRRL0, TMRRL1, TMRRL2
Initial value
XXXXXXXXB
16-bit dead timer control register 0
DTCR0
Address:
Waveform generator0 : 0000E8H
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
DMOD0
GTEN1
GTEN0
TMIF0
TMIE0
TMD2
TMD1
TMD0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
00000000B
16-bit dead timer control register 1
DTCR1
Address:
Waveform generator0 : 0000E9H
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
DMOD1
GTEN3
GTEN2
TMIF1
TMIE1
TMD5
TMD4
TMD3
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
00000000B
16-bit dead timer control register 2
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
DMOD2
GTEN5
GTEN4
TMIF2
TMIE2
TMD8
TMD7
TMD6
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Waveform control register 10
bit7
SIGCR10
bit6
bit5
bit4
bit3
bit2
bit1
bit0
DTIE
DTIF
NRSL
DCK2
DCK1
DCK0
NWS1
NWS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
-
DTTI
-
R/W
DTCR2
Address:
Waveform generator0 : 0000EAH
Address:
Waveform generator0
: 0000EDH
Initial value
00000000B
Initial value
00000000B
Waveform control register 20
SIGCR20
PSEL2[1] PSEL2[0] PSEL1[1] PSEL1[0] PSEL0[1] PSEL0[0]
Address:
Waveform generator0 : 0000EFH
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
000000-1B
R/W: Readable/writable
-:
Undefined bit
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CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
■ A/D Activation Compare Register
Compare register 0, 2 (Upper)
ADCOMPB0/ADCOMP0
ADCOMPB2/ADCOMP2
ADCOMPB0 / ADCOMPB2
Read/write
ADCOMP0 / ADCOMP2
Read/write
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
CMP15
CMP14
CMP13
CMP12
CMP11
CMP10
CMP09
CMP08
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
Address
Initial value
00000000B
Address ADCOMPD0/ADCOMPDB0
ADCOMPD2/ADCOMPDB2
ch.0: 0000F0H
ch.0: 0000F2H
ch.2: 0000F8H
ch.2: 0000FAH
Compare register 0, 2 (Lower)
ADCOMPB0 / ADCOMPB2
Read/write
ADCOMP0 / ADCOMP2
Read/write
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CMP07
CMP06
CMP05
CMP04
CMP03
CMP02
CMP01
CMP00
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
bit7
bit6
bit5
bit4
-
-
CE2[1]
-
R/W
Initial value
00000000B
Compare enable register
ADTGCE0
Address
A/D activation compare 0: 0000FFH
bit3
bit2
bit1
bit0
CE2[0]
-
-
CE0[1]
CE0[0]
R/W
-
-
R/W
R/W
bit13
bit12
bit11
bit10
bit9
bit8
-
SEL2[1]
SEL2[0]
-
-
-
R/W
R/W
-
-
Initial value
--00--00 B
Count direction selection for comparison register
ADTGSEL0
bit15
bit14
Address
A/D activation compare 0: 0000FEH
SEL0[1] SEL0[0]
R/W
Initial value
--00--00 B
R/W
Buffer control register
ADTGBUF0
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
-
BTS2
-
BTS0
-
BUFX2
-
BUFX0
R/W
-
R/W
-
R/W
-
R/W
Address
A/D activation compare 0: 0000FDH
Initial value
-0-0-1-1 B
R/W: Readable/writable
R: Read only
W: Write only
-:
Undefined bit
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CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
11.4.1
Compare Clear Buffer Register (CPCLRBH0 to
CPCLRBH2, CPCLRBL0 to CPCLRBL2) /Compare Clear
Register (CPCLRH0 to CPCLRH2, CPCLRL0 to CPCLRL2)
The compare clear buffer register (CPCLRBH, CPCLRBL) is a 16-bit buffer register
which exists in the compare clear register (CPCLRH, CPCLRL). Both the register
(CPCLRBH, CPCLRBL) and the register (CPCLRH, CPCLRL) exist in the same address.
■ Compare Clear Buffer Register (CPCLRBH0 to CPCLRBH2, CPCLRBL0 to CPCLRBL2)
Compare clear buffer register (Upper)
CPCLRBH0 to
CPCLRBH2
Address (ch.n) :
ch.0: 0000B4H
ch.1: 0000BCH
ch.2: 0000C4H
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
CL15
CL14
CL13
CL12
CL11
CL10
CL09
CL08
W
W
W
W
W
W
W
W
Initial value
11111111 B
Compare clear buffer register (Lower)
CPCLRBL0 to
CPCLRBL2
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CL07
CL06
CL05
CL04
CL03
CL02
CL01
CL00
W
W
W
W
W
W
W
W
Initial value
11111111 B
W: Write only
The compare clear buffer register is a buffer register which exists in the same address of the compare clear
register (CPCLRH, CPCLRL). When the buffer function is disabled (the timer state control register lower
(TCCSL), BFE: bit7 = 0), or the free-run timer is stopped, the value of the compare clear buffer register is
transferred to the compare clear register immediately. If the buffer function is enabled, the value is
transferred to the compare clear register when the count value 0 of the 16-bit free-run timer is detected.
To access this register, use a half-word or word access instruction. Do not access this register with the read
modify write (RMW) instructions.
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CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
■ Compare Clear Register (CPCLRH0 to CPCLRH2, CPCLRL0 to CPCLRL2)
Compare clear register (Upper)
CPCLRH0 to CPCLRH2
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
CL15
CL14
CL13
CL12
CL11
CL10
CL09
CL08
R
R
R
R
R
R
R
R
Initial value
11111111 B
Address (F R T n):
ch.0: 0000B4H
ch.1: 0000BCH
ch.2: 0000C4H
Compare clear register (Lower)
CPCLRL0 to CPCLRL2
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CL07
CL06
CL05
CL04
CL03
CL02
CL01
CL00
R
R
R
R
R
R
R
R
Initial value
11111111 B
R : Read only
The compare clear register is used to compare with the count value of the 16-bit free-run timer. In up-count
mode, the 16-bit free-run timer is reset to "0000H" when the 16-bit free-run timer count value matches the
value in this register. In up/down count mode, the 16-bit free-run timer changes its mode from the up
counting to the down counting when this register matches the count value of the 16-bit free-run timer; or
changes from the down counting to up counting when a zero-detection occurs.
To access this register, use a half-word or word access instruction. Do not access this register with the read
modify write (RMW) instructions.
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CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
11.4.2
Timer Data Register (TCDTH0 to TCDTH2, TCDTL0 to
TCDTL2)
The timer data register (TCDTH, TCDTL) is used to read the count value of the 16-bit
free-run timer. Also the count value of the 16-bit free-run timer can be set to this
register.
■ Timer Data Register (TCDTH0 to TCDTH2, TCDTL0 to TCDTL2)
Timer data register (Upper)
TCDTH0 to TCDTH2
Address (F R T n):
ch.0: 0000B6H
ch.1: 0000BEH
ch.2: 0000C6H
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
T15
T14
T13
T12
T11
T10
T09
T08
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
00000000 B
R/W
Timer data register (Lower)
TCDTL0 to TCDTL2
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
T07
T06
T05
T04
T03
T02
T01
T00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
00000000 B
R/W
R/W: Readable/writable
The timer data register is used to read the count value of the 16-bit free-run timer. The count value is
cleared to "0000H" immediately when a reset occurs. Writing the value to this register can be set the timer
value. Please write a value while the timer is stopped (the timer state control register lower (TCCSL),
STOP: bit6 = 1). To access the timer data register, use a half-word or word access instruction.
16-bit free-run timer is initialized immediately when the following factors occur.
• Reset
• The clear bit (SCLR: bit 4) in the timer state control register lower (TCCSL)=1 while the 16-bit freerun timer is operating (STOP: bit 6 in the timer state control register lower (TCCSL)=0)
(Note) The 16-bit free-run timer is not initialized as the clear bit (SCLR: bit 4) in the timer state control
register lower (TCCSL)=1 while the 16-bit free-run timer is stopped (STOP: bit6 in the timer state
control register lower (TCCSL)=1)
• Match of the compare clear register and the timer count value in the up count mode (the timer state
control register lower (TCCSL), MODE: bit5 = 0)
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CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
11.4.3
MB91490 Series
Timer State Control Register (TCCSH0 to TCCSH2,
TCCSL0 to TCCSL2, TCCSM0 to TCCSM2)
The timer state control register (TCCSH, TCCSL and TCCSM) is a 16-bit and 8-bit
registers which are used to control the operation of the 16-bit free-run timer.
■ Timer State Control Register Upper (TCCSH0 to TCCSH2)
Timer state control register (Upper)
Address:
ch.0: 0000B8H
ch.1: 0000C0H
ch.2: 0000C8H
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
ECKE
IRQZF
IRQZE
MSI2
MSI1
MSI0
ICLR
ICRE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TCCSH0 to TCCSH2
Initial value : 00000000
R/W
ICRE
Compare clear inter rupt request enable bit
0
Disable inter rupt request
1
Enable inter rupt request
B
Compare clear inter rupt flag bit
ICLR
Read
Write
0
No compare clear match
Clear this bit
1
Compare clear matches
No ef fect on this bit
MSI2
MSI1
MSI0
0
0
0
Generate interrupt at 1st match occurred
0
0
1
Generate interrupt at 2nd match occurred
0
1
0
Generate interrupt at 3rd match occurred
0
1
1
Generate interrupt at 4th match occurred
1
0
0
Generate interrupt at 5th match occurred
1
0
1
Generate interrupt at 6th match occurred
1
1
0
Generate interrupt at 7th match occurred
1
1
1
Generate interrupt at 8th match occurred
IRQZE
Interrupt mask selection bits
Zero detection interrupt request enable bit
0
Disable interrupt request
1
Enable interrupt request
IRQZF
0
1
Zero detection interrupt flag bit
Read
Write
Zero is not detected
Zero is detected
ECKE
Clear this bit
No ef fect on this bit
Clo ck select bit
0
Peripheral clock (CLKP)
1
External clock (CKI0)
R/W : Readable/Writable
: Initial value
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CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
Table 11.4-1 Timer State Control Register Upper (TCCSH) (1 / 2)
Bit name
Function
• This bit is used to select the peripheral clock (CLKP) or the external clock
(CKI0) as a count clock of the 16-bit free-run timer.
bit15
ECKE:
Clock select bit
• Setting this bit to "0" selects the peripheral clock (CLKP). To select a count
clock frequency, you also need to select a clock frequency select bits of the
TCCSL register (CLK3 to CLK0: bit3 to bit0).
• Setting this bit to "1" selects the external clock (CKI0). The external clock
(CKI0) is input from CKI pins. Therefore, write "0" to the bit4 of the port
direction register (DDRP, DDRR) to enable the external clock input.
Note:
The count clock is changed immediately when this bit is set. Therefore, this bit
must be changed when the output compare and the input capture are stopped.
• When the count value of the 16-bit free-run timer is 0000H, this bit is set to "1".
• When this bit is set to "0": Clears the bit.
• Setting this bit to "1" has no effect on this bit.
• When this bit is read to a read modify write (RMW) instruction, "1" is always
read.
Note:
This bit is not set by a software clear (writing "1" to bit4 (SCLR) of the timer state
control register lower (TCCSL)) when the 16-bit free-run timer is operating (bit6
(STOP) of the timer state control register lower (TCCSL)=0).
In up/down count mode (bit5 (MODE) in the timer state control register lower
(TCCSL) = 1), this bit is set to "1" when an interrupt set in the interrupt mask
selection bits (bit12 to bit10 (MSI2 to MSI0) in the timer state control register
upper (TCCSH)  000B) occurs. When no interrupt occurs, this bit is not set to
"1".
In the up count mode (MODE: bit5 = 0), this bit is set every time the zero-detection occurs regardless of the value of the MSI2 to MSI0: bit12 to bit10.
IRQZE:
When this bit and the interrupt flag bit (IRQZF: bit14) are set to "1", an interrupt
bit13 Zero detection interrupt request request to the CPU can be generated.
enable bit
IRQZF:
bit14
Zero-detection interrupt flag bit
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CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
Table 11.4-1 Timer State Control Register Upper (TCCSH) (2 / 2)
Bit name
Function
When MODE2:bit11 of timer state control register M=0
• These bits are used to set the mask counting of the compare clear interrupt at
up-count mode (MODE:bit5 of the timer state control register lower (TCCSL)=0).
These bits are used to set the mask counting of 0 detection interrupt at up/downcount mode (MODE:bit5 of the timer state control register lower (TCCSL)=1).
• When 0 is set to this bit, the interrupt factor is not masked.
When MODE2:bit11 of the timer state control register M=1
bit12
MSI2 to MSI0:
to
Interrupt mask selection bits
bit10
• These bits are used to set the mask counting of "0" detection interrupt at up/downcount mode (MODE:bit5 of the timer state control register lower (TCCSL)=1).
• The setting of up-count mode (MODE:bit5 of the timer state control register
lower (TCCSL)=0) is prohibited.
Note:
Reading returns the value of the mask counter.
For read-modify-write instruction, reading returns the value of the mask register.
Write data at writing to the mask register.
When free-run timer is running (STOP:bit6 of the timer state control register
lower (TCCSL)=0), writing value to the mask register will be reloaded to the
counter after the mask counter reached to zero.
When free-run timer is stopped (STOP:bit6 of the timer control register lower
(TCCSL)=1), writing value to the mask register will reload to the counter immediately.
• This bit is set to "1" when the value of the compare clear matches the value of
the 16-bit free-run timer.
• When this bit is set to "0": Clears the bit.
• Setting this bit to "1" has no effect on this bit.
• When this bit is read to a read modify write (RMW) instruction, "1" is always
read.
bit9
bit8
224
ICLR:
Compare clear interrupt flag bit Note:
In up-count mode (bit5 (MODE) in the timer state control register lower (TCCSL) =
0), this bit is set to "1" when an interrupt set in the interrupt mask selection bits
occurs.
When no interrupt occurs, this bit is not set to "1".
In the up/down count mode (MODE:bit5 of the timer state control register lower
(TCCSL)=1), this bit is set every time a compare clear occurs regardless of the
value of the MSI 2 to MSI 0.
ICRE:
An interrupt request to the CPU can be generated when this bit and the compare
Compare clear interrupt request clear interrupt flag bit (ICLR: bit9) are set to "1".
enable bit
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
■ Timer State Control Register Lower (TCCSL0 to TCCSL2)
Timer state control register (Lower)
Address:
ch.0: 0000B9H
ch.1: 0000C1H
ch.2: 0000C9H
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
BFE
STOP
MODE
SCLR
CLK3
CLK2
CLK1
CLK0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TCCSL0 to TCCSL2
Initial value: 01000000 B
Clock frequency select bits
CLK3 CLK2 CLK1 CLK0 Count
clock
φ=40MHz φ=20MHz
φ=10MHz
φ=5MHz
φ=2.5MHz
100ns
200ns
400ns
0
0
0
φ
0
0
0
1
φ/2
50ns
100ns
200ns
400ns
800ns
0
0
1
0
φ/4
100ns
200ns
400ns
800ns
1.6μs
0
0
1
1
φ/8
200ns
400ns
800ns
1.6μs
3.2μs
0
1
0
0
φ/16
400ns
800ns
1.6μs
3.2μs
6.4μs
0
1
0
1
φ/32
800ns
1.6μs
3.2μs
6.4μs
12.8μs
0
1
1
0
φ/64
1.6μs
3.2μs
6.4μs
12.8μs
25.6μs
0
1
1
1
φ/128
3.2μs
6.4μs
12.8μs
25.6μs
51.2μs
1
0
0
0
φ/256
6.4μs
12.8μs
25.6μs
51.2μs
102.4μs
-
-
-
-
-
-
0
Disable other setting
25ns
50ns
Peripheral clock (CLKP)
SCLR
0
1
MODE
Timer clear bit
Read
Write
Always read "0"
Do not initialize counter
Initialized counter to "0000H
Timer count mode bit
0
Up count mode
1
Up/down count mode
Timer enable bit
STOP
0
Enable count (start count)
1
Disable count (stop count)
BFE
Compare clear buffer enabled bit
0
Disable compare clear buffer
1
Enable compare clear buffer
R/W: Readable/Writable
: Initial value
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CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
Table 11.4-2 Timer State Control Register Lower (TCCSL)
Bit name
Function
• This bit is used to enable a compare clear buffer register (CPCLRBH, CPCLRBL).
BFE:
bit7 Compare clear
buffer enable bit
• Setting this bit to "0" disables the compare clear buffer register (CPCLRBH, CPCLRBL).
Accordingly, you can write directly to the compare clear registers (CPCLRH and CPCLRL).
• Setting this bit to "1" enables the compare clear buffer register (CPCLRBH, CPCLRBL). The
data written to and stored in the compare clear buffer register (CPCLRBH, CPCLRBL) is
transferred to the compare clear register when a count value of "0" is detected in the 16-bit
free-run timer.
• This bit is used to start/stop the 16-bit free-run timer counting.
• Setting this bit to "0" starts the 16-bit free-run timer counting.
STOP:
bit6
Timer enable bit
• Setting this bit to "1" stops the 16-bit free-run timer counting.
• Even if SCLR: bit4 of timer state control register lower is 1 when the free-run timer is
stopping (this bit=1), the free-run timer is not initialized.
• This bit is used to select a count mode of the 16-bit free-run timer.
• Selecting this bit to "0" selects the up-count mode. The timer continues to perform
incremental counting until the count value matches a compare clear register and is reset
"0000H". Then, the timer restarts to perform incremental counting.
• Setting this bit to "1" selects the up/down count mode. The timer continues to perform
MODE:
bit5 Timer count mode
incremental counting until the count value matches a compare clear register. Then, the mode
bit
changes to the down count. After that, the mode changes to the up count again when the count
value reaches to "0000H".
• This bit can be written even if the timer is operating or stopped. When the timer is running,
the value written to this bit is stored in a buffer and the count mode changes based on the
buffer value the next time the timer value goes to "0000H".
• This bit is used to initialize the 16-bit free-run timer to "0000H".
• Initialize the 16-bit free-run timer:
When this bit is set to "1" while the 16-bit free-run timer is running (STOP: bit6 of the timer
state control register lower (TCCSL)=0), the timer is initialized to "0000H" at the next count
bit4
SCLR:
Timer clear bit
clock. When the bit is set to "1" while the timer is stopped (STOP: bit6 of the timer state
control register lower (TCCSL)=1), the timer is not initialized.
• The read value is always "0".
bit3 CLK3 to CLK0:
to Clock frequency
bit0 select bits
226
Note:
Writing "1" to this bit does not generate a zero-detection interrupt.
No timer clear is performed if you set "1" and then write "0" before the next count clock.
• These bits are used to select a count clock frequency of the 16-bit free-run timer.
• The count clock is changed immediately after the bits are set.
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
■ Timer State Control Register M (TCCSM0 to TCCSM2)
Timer state control register M
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
TCCSM0 to TCCSM2
-
-
-
-
MODE2
MSI5
MSI4
MSI3
-
-
-
-
R/W
R/W
R/W
R/W
Address:
ch.0: 0000BAH
ch.1: 0000C2H
ch.2: 0000CAH
Initial value : ----0000
MSI5
MSI4
MSI3
0
0
0
Generate interrupt at 1st match occurred
0
0
1
Generate interrupt at 2nd match occurred
0
1
0
Generate interrupt at 3rd match occurred
0
1
1
Generate interrupt at 4th match occurred
1
0
0
Generate interrupt at 5th match occurred
1
0
1
Generate interrupt at 6th match occurred
1
1
0
Generate interrupt at 7th match occurred
1
1
1
Generate interrupt at 8th match occurred
MODE2 MODE*
R/W
-
: Reada ble/Writable
: Initial value
: Undefined bit
B
1
Compare clear interrupt mask selection bits
Interrupt mask mode bit 2
0
0
Setting value of MSI5 to MSI3 are invalid
0
1
Setting value of MSI5 to MSI3 are invalid
1
0
Prohibited Setting (Operation does not guarantee)
1
1
Setting value of MSI5 to MSI3 are valid
*1: bit5 in the timer state control register lower (TCCSL)
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CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
Table 11.4-3 Timer State Control Register M (TCCSM)
Bit name
bit15
to Undefined bits
bit12
Function
• The read value of these bits are undefined.
• Write to these bits takes no effect.
• This bit is used to mask the zero-detection interrupt and compare clear interrupt separately
when the 16-bit free-run timer is in up/down count mode (MODE: bit5 of the timer state
control register lower (TCCSL)=1).
MODE2:
bit11 Interrupt mask
mode bit 2
• If the bit is set to "1" when MODE: bit5 of the timer state control register lower (TCCSL) is
1, the value set is MSI5 to MSI3: bit10 to bit8 of this register is valid and the number of the
specified compare clear interrupt is masked. The number of masking of zero-detection
interrupt is the value set in MSI2 to MSI0: bit12 to bit10 of the timer state control register
upper (TCCSH).
Note:
If the bit is set to "0" when MODE: bit5 of the timer state control register lower (TCCSL) is 1,
the operation is not guaranteed.
• This bit is only valid when MODE2: bit11 of this register and MODE: bit5 of the timer state
control register lower (TCCSL) are 1. It is used to set the number of masking of the compare
clear interrupt.
The number of masking of the zero-detection interrupt is set by MSI2 to MSI0: bit12 to bit10
of the timer state control register upper (TCCSH).
MSI5 to MSI3:
bit10
Compare clear
to
interrupt mask
bit8
selection bits
228
• Setting the bits to "000B" do not mask the compare clear interrupt cause.
Note:
Reading returns the value of the mask counter.
For read-modify-write instruction, reading returns the value of the mask register. Write data at
writing to the mask register.
When free-run timer is running (STOP:bit6 of the timer state control register lower
(TCCSL)=0), writing value to the mask register will be reloaded to the counter after the mask
counter reached to "0".
When free-run timer is stopped (STOP:bit6 of the timer state control register lower
(TCCSL)=1), writing value to the mask register will reload to the counter immediately.
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
11.4.4
A/D Trigger Control Register (ADTRGC0 to ADTRGC2)
Controls A/D trigger signal output when a free-run timer compare match or zerodetection occurs.
■ A/D Trigger Control Register (ADTRGC0 to ADTRGC2)
A/D trigger control register
Address:
A/D trigger 0: 0000BBH
A/D trigger 1: 0000C3H
A/D trigger 2: 0000CBH
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
-
SEL2
-
SEL0
-
AD2E
-
AD0E
-
R/W
-
R/W
-
R/W
-
R/W
AD0E
Disable
1
Enable
AD2E
10-bit A/D converter 1trigger output enable bit
0
Disable
1
Enable
-
CM71-10155-2E
10-bit A/D converter 2 trigger source select bit
0
At zero detection
1
At compare match
SEL2
: Readable/Writable
: Initial value
: Undefined bit
10-bit A/D converter 2 trigger output enable bit
0
SEL0
R/W
ADTRGC0 to ADTRGC2
Initial value: -0-0-0-0 B
10-bit A/D converter 1 trigger source select bit
0
At zero detection
1
At compare match
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CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
Table 11.4-4 A/D Trigger Control Register (ADTRGC)
Bit name
bit7
Undefined bit
bit6
SEL2:
10-bit A/D converter 1
trigger source select bit
bit5
Undefined bit
bit4
SEL0:
10-bit A/D converter 2
trigger source select bit
bit3
Undefined bit
bit2
AD2E:
10-bit A/D converter 1
trigger output enable bit
bit1
Undefined bit
bit0
AD0E:
10-bit A/D converter 2
trigger output enable bit
230
Function
• The read value is undefined.
• Writing to this bit has no effect on operation.
This bit is the bit that selects whether the 10-bit A/D converter 1 trigger is
output at a zero detection of the free-run timer or a compare match.
• The read value is undefined.
• Writing to this bit has no effect on operation.
This bit is the bit that selects whether the 10-bit A/D converter 2 trigger is
output at a zero detection of the free-run timer or a compare match.
• The read value is undefined.
• Writing to this bit has no effect on operation.
• When this bit is set to "0", the 10-bit A/D converter 1 trigger signal is not
output.
• When this bit is set to "1", the 10-bit A/D converter 1 trigger signal can be
output.
• The read value is undefined.
• Writing to this bit has no effect on operation.
• When this bit is set to "0", the 10-bit A/D converter 2 trigger signal is not
output.
• When this bit is set to "1", the 10-bit A/D converter 2 trigger signal can be
output.
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
11.4.5
Free-run Timer Selection Register (FRS0 to FRS4)
The free-run timer selection register is used to select one of the free-run timers with 3
channels for each input capture and output compare.
■ Free-run Timer Selection Register (Upper) for Output Compare (FRS1)
Free-run timer selection register (Upper) for output compare
bit15
-
bit14
-
bit13
bit12
FSO13
FSO12
R/W
bit11
bit10
-
-
R/W
-
-
bit9
bit8
FSO9
FSO8
R/W
R/W
FRS1
Address :
FRS1: 0000CEH
Initial value:
FRS1 : --00--00B
FSO9
FSO8
0
0
F R T0
OC2
0
1
F R T1
OC2
1
0
Other settings
FSO13
FSO12
-
CM71-10155-2E
F R T2
OC2
Prohibited (Operation not guarantee)
Free-run timer selection bits for output compare
0
0
F R T0
OC3
0
1
F R T1
OC3
1
0
Other settings
R/W
Free-run timer selection bits for output compare
F R T2
OC3
Prohibited (Operation not guarantee)
: Readable/Writable
: Initial value
: Undefined bit
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CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
Table 11.4-5 Free-run Timer Selection Register (Upper) for Output Compare (FRS1)
Bit name
bit15,
bit14
Undefined bit
bit13,
bit12
FSO13, FSO12:
free-run timer selection bits
for output compare
bit11,
bit10
Undefined bit
bit9,
bit8
FSO9, FSO8:
free-run timer selection bits
for output compare
232
Function
• The read value is undefined.
• Writing to this bit has no effect on operation.
These bits are used to select one of the free-run timers for output compare 3.
Note:
Be sure to check that the free-run timer is stopped before using these bits.
• The read value is undefined.
• Writing to this bit has no effect on operation.
These bits are used to select one of the free-run timers for output compare 2.
Note:
Be sure to check that the free-run timer is stopped before using these bits.
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CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
■ Free-run Timer Selection Register (Lower) for Output Compare(FRS0, FRS2)
Free-run timer selection register (Lower) for output compare
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
-
-
FSO5
FSO4
-
-
FSO1
FSO0
-
-
R/W
R/W
-
-
R/W
R/W
Initial value
FRS0, FRS2: --00--00B
FSO0
0
0
F R T0
OC0 / OC4
0
1
F R T1
OC0 / OC4
F R T2
OC0 / OC4
Free-run timer selection bits for output compare
Prohibited (Operation not guarantee)
FSO5
FSO4
0
0
F R T0
OC1 / OC5
0
1
F R T1
OC1 / OC5
1
0
F R T2
OC1 / OC5
Other settings
-
Address :
FRS0 : 0000CF H
FRS2 : 0000CD H
FSO1
1
0
Other settings
R/W
FRS0/FRS2
Free-run timer selection bits for output compare
Prohibited (Operation not guarantee)
: Readable/Writable
: Initial value
: Undefined bit
Table 11.4-6 Free-run Timer Selection Register (Lower) for Output Compare (FRS0, FRS2)
Bit name
bit7,
bit6
Undefined bits
bit5,
bit4
FSO5, FSO4:
free-run timer selection bits
for output compare
bit3,
bit2
Undefined bits
bit1,
bit0
FSO1, FSO0:
free-run timer selection bits
for output compare
CM71-10155-2E
Function
• The read value is undefined.
• Writing to this bit has no effect on operation.
These bits are used to select one of the free-run timers for output compare 1/5.
Note:
Be sure to check that the free-run timer is stopped before using these bits.
• The read value is undefined.
• Writing to this bit has have no effect on operation.
These bits are used to select one of the free-run timers for output compare 0/4.
Note:
Be sure to check that the free-run timer is stopped before using these bits.
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CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
■ Free-run Timer Selection Register (Upper) for Input Capture (FRS4)
Free-run timer selection register (Upper) for input capture
bit15
bit14
bit13
bit12
bit11
FRS4
bit8
-
FSI13
FSI12
-
-
FSI9
FSI8
-
-
R/W
R/W
-
-
R/W
R/W
Address :
FRS4 : 0000D2
H
Initial value
FRS4: --00--00B
FSI9
FSI8
0
0
F R T0
IC2
0
1
F R T1
IC2
F R T2
IC2
Free-run timer selection bits for input capture
Prohibited (Operation not guarantee)
FSI13
FSI12
0
0
F R T0
IC3
0
1
F R T1
IC3
1
0
F R T2
IC3
Other settings
-
bit9
-
1
0
Other settings
R/W
bit10
Free-run timer selection bits for input capture
Prohibited (Operation not guarantee)
: Readable/Writable
: Initial value
: Undefined bit
Table 11.4-7 Free-run Timer Selection Register (Upper) for Input Capture (FRS4)
Bit name
bit15,
bit14
Undefined bits
bit13,
bit12
FSI13, FSI12:
free-run timer selection bits
for input capture
bit11,
bit10
Undefined bits
bit9,
bit8
FSI9, FSI8:
free-run timer selection bits
for input capture
234
Function
• The read value is undefined.
• Writing to these bits has no effect on operation.
These bits are used to select one of the free-run timers for input capture3.
Note:
Be sure to check that the free-run timer is stopped before using these bits.
• The read value is undefined.
• Writing to these bits has no effect on operation.
These bits are used to select one of the free-run timers for input capture2.
Note:
Be sure to check that the free-run timer is stopped before using these bits.
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CM71-10155-2E
CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
■ Free-run Timer Selection Register (Lower) for Input Capture(FRS3)
Free-run timer selection register (Lower) for input capture
bit7
bit6
-
-
-
-
bit5
bit4
FSI5
FSI4
R/W
R/W
bit3
bit2
bit1
-
-
FSI1
FSI0
-
-
R/W
R/W
Address :
FRS3 : 0000D3
H
Initial value
FRS3: --00--00B
FSI0
0
0
F R T0
IC0
0
1
F R T1
IC0
F R T2
IC0
Free-run timer selection bits for input capture
Prohibited (Operation not guarantee)
FSI5
FSI4
0
0
F R T0
IC1
0
1
F R T1
IC1
1
0
F R T2
IC1
Other settings
-
FRS3
FSI1
1
0
Other settings
R/W
bit0
Free-run timer selection bits for input capture
Prohibited (Operation not guarantee)
: Readable/Writable
: Initial value
: Undefined bit
Table 11.4-8 Free-run Timer Selection Register (Lower) for Input Capture (FRS3)
Bit name
bit7,
bit6
Undefined bits
bit5,
bit4
FSI5, FSI4:
free-run timer selection bits
for input capture
bit3,
bit2
Undefined bits
bit1,
bit0
FSI1, FSI0:
free-run timer selection bits
for input capture
CM71-10155-2E
Function
• The read value is undefined.
• Writing to these bits has no effect on operation.
These bits are used to select one of the free-run timers for input capture1.
Note:
Be sure to check that the free-run timer is stopped before using these bits.
• The read value is undefined.
• Writing to these bits has no effect on operation.
These bits are used to select one of the free-run timers for input capture0.
Note:
Be sure to check that the free-run timer is stopped before using these bits.
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CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
11.4.6
MB91490 Series
Output Compare Buffer Register (OCCPBH0 to
OCCPBH5, OCCPBL0 to OCCPBL5) /Output Compare
Register (OCCPH0 to OCCPH5, OCCPL0 to OCCPL5)
The output compare buffer register (OCCPBH, OCCPBL) is a 16-bit buffer register for
the output compare register (OCCPH, OCCPL).
Both the register (OCCPBH, OCCPBL) and the register (OCCPH, OCCPL) exist in the
same address.
■ Output Compare Buffer Register (OCCPBH0 to OCCPBH5, OCCPBL0 to OCCPBL5)
Output compare buffer register (Upper)
OCCPBH0 to OCCPBH5
Address
ch.0 : 0000A0 H
ch.1 : 0000A2 H
ch.2 : 0000A4 H
ch.3 : 0000A6 H
ch.4 : 0000A8 H
ch.5 : 0000AA H
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
OP15
OP14
OP13
OP12
OP11
OP10
OP09
OP08
W
W
W
W
W
W
W
W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
OP07
OP06
OP05
OP04
OP03
OP02
OP01
OP00
W
W
W
W
W
W
W
W
Initial value
00000000 B
Output compare buffer register (Lower)
OCCPBL0 to OCCPBL5
Initial value
00000000 B
W: W rite only
The output compare buffer register is a buffer register for the output compare register (OCCPH, OCCPL).
When the buffer function is disabled (the lower of the compare control register (OCSL0, OCSL2, OCSL4),
BUF1, BUF0: bit3, bit2 = 11B), or the free-run timer is stopped, the value of the output compare buffer
register is transferred to the output compare register immediately. When the buffer function is enabled (the
lower of the compare control register (OCSL0, OCSL2, OCSL4), BUF1, BUF0: bit3, bit2=00B), the value
is transferred when the compare clear match or zero-detection occurs according to the transfer selection bits
(BTS1, BTS0: bit14, bit13) in the upper of the compare control register (OCSH1, OCSH3, OCSH5).
To access this register, use a half-word or word access instruction.
The free-run timer in the above explanation refers to the operation of the free-run timer selected for output
compare. Do not access this register with the read modify write (RMW) instructions.
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CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
■ Output Compare Register (OCCPH0 to OCCPH5, OCCPL0 to OCCPL5)
Output compare register (Upper)
OCCPH0 to OCCPH5
Address
ch.0 : 0000A0 H
ch.1 : 0000A2 H
ch.2 : 0000A4 H
ch.3 : 0000A6 H
ch.4 : 0000A8 H
ch.5 : 0000AA H
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
OP15
OP14
OP13
OP12
OP11
OP10
OP09
OP08
R
R
R
R
R
R
R
R
Initial value
00000000 B
Output compare register (L ower)
OCCPL0 to OCCPL5
R:
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
OP07
OP06
OP05
OP04
OP03
OP02
OP01
OP00
R
R
R
R
R
R
R
R
Initial value
00000000 B
Read only
The output compare register is a 16-bit register used to compare with the count value of the 16-bit free-run
timer. Set the value of the output compare buffer register (OCCPBH, OCCPBL) before the timer operation
is enabled.
When the value of the output compare register matches the count value of the 16-bit free-run timer, a
compare signal is generated and the output compare interrupt flag bit (the lower of the compare control
register (OCSL0, OCSL28, OCSL4), IOP1, IOP0: bit7, bit6) is set. When the output level is set (the upper
of the compare control register (OCSH1, OCSH3, OCSH5), OTD1, OTD0: bit9, bit8), an output level
waveform generator (RTO0 to RTO5) corresponding to the output compare register (OCCPH0 to
OCCPH5, OCCPL0 to OCCPL5) can be reversed.
The compare signal is not generated when the value of this register matches the peak value when the 16-bit
free-run timer is in up/down mode.
● Up/down mode
• In CMOD = 0
When this register is set to "FFFFH", the RT output goes to "0" regardless of the 16-bit free-run timer
value and inversion mode.The output goes to "1" when "0000H" is set.
• In CMOD = 1
When this register is set to "FFFFH", the RT output goes to "1" regardless of the 16-bit free-run timer
value and inversion mode. The output goes to "0" when "0000H" is set.
To access this register, use a half-word or word access instruction. Do not access this register with the
read modify write (RMW) instructions.
The free-run timer in the above explanation refers to the operation of the free-run timer selected for
output compare.
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CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
Compare Control Register (OCSH0 to OCSH5,
OCSL0 to OCSL5)
11.4.7
The compare control register is used to control the output level, output enable, output
level reverse mode, compare operation enable, compare match interrupt enable, and
compare match interrupt flag of RT0 to RT5.
■ Compare Control Register, Upper Byte (OCSH1, OCSH3, OCSH5)
Compare control register (Upper)
OCSH1, OCSH3, OCSH5
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
-
BTS1
BTS0
CMOD
-
-
OTD1
OTD0
Initial value: -110--00
-
R/W
R/W
R/W
-
-
R/W
R/W
Address
ch.1: 0000ACH
ch.3: 0000AEH
ch.5: 0000B0H
Output level bit
OTD0
0
Read
0
MOD1x=1
0
RT0, RT2, RT4:
This level is reversed immediately at the match
with compare register0, 2, 4
RT1, RT3, RT5:
This level is reversed immediately at the match
with compare register1, 3, 5
1
RT0, RT2, RT4:
This level is reversed immediately at the match
with compare register0, 2, 4
RT1, RT3, RT5:
This level is reversed immediately at the match
with compare register (0 or 1),(2 or 3),
(4 or 5) occurs
Set "1" at match in up count mode.
Reset "0" at match in down count mode.
Set "0" at match in up count mode.
Reset "1" at match in down count mode.
Buffer transfer selection bit
0
Transfer starts when zero detection occurs (ch.0,ch.2,ch.4)
1
Transfer starts when compare clear match occurs (ch.0,ch.2,ch.4)
BTS1
238
RT1,RT3, or RT5 output ”1”
MOD1x=0
BTS0
-
Write
RT1,RT3, or RT5 output ”0”
Output level reverse mode bit
CMOD
: Readable/Writable
: Initial value
: Undefined bit
RT0,RT2, or RT4 output ”1”
Read
Current output value of RT1,
RT3, or RT5
1
RT0,RT2, or RT4 output ”0”
Output level bit
OTD1
R/W
Write
Current output value of RT0,
RT2, or RT4
1
B
Buffer transfer selection bit
0
Transfer starts when zero detection occurs (ch.1,ch.3,ch.5)
1
Transfer starts when compare clear match occurs (ch.1,ch.3,ch.5)
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
Table 11.4-9 Compare Control Register, Upper Byte (OCSH1, OCSH3, OCSH5) (1 / 2)
Bit name
bit15 Undefined bit
Function
• The read value is undefined.
• Writing to this bit has no effect on operation.
• This bit is used to select the time when the data is transferred from the output compare buffer
registers (OCCPBH1, OCCPBH3, OCCPBH5, OCCPBL1, OCCPBL3, OCCPBL5) to the
output compare registers (OCCPH1, OCCPH3, OCCPH5, OCCPL1, OCCPL3, OCCPL5).
BTS1:
bit14 Buffer transfer • Setting this bit to "0" starts the data transfer when the count value "0" of the 16-bit free-run
selection bit
timer is detected.
• Setting this bit to "1" starts the data transfer when a compare clear match of the 16-bit free-run
timer occurs.
• This bit is used to select the time when the data is transferred from the output compare buffer
registers (OCCPBH0, OCCPBH2, OCCPBH4, OCCPBL0, OCCPBL2, OCCPBL4) to the output
compare registers (OCCPH0, OCCPH2, OCCPH4, OCCPL0, OCCPL2, OCCPL4).
BTS0:
bit13 Buffer transfer • Setting this bit to "0" starts the data transfer when the count value "0" of the 16-bit free-run
selection bit
timer is detected.
• Setting this bit to "1" starts the data transfer when a compare clear match of the 16-bit free-run
timer occurs.
• This bit is used to change the pin output level inversion mode immediately after a match occurs.
• When this bit is set to "0":
The compare mode control register (OCMOD): MOD1x = 0
- RT0, RT2, RT4: The level is reversed immediately when the compare registers 0, 2, 4 match
the 16-bit free-run timer.
- RT1, RT3, RT5: The level is reversed immediately when the compare registers 1, 3, 5 match
the 16-bit free-run timer.
The compare mode control register (OCMOD): MOD1x = 1
- Set to "1" when the match occurs in the up-count mode.
CMOD:
Output level
bit12
reverse mode
bit
- Reset to "0" when the match occurs in the down-count mode.
• When this bit is set to "1":
The compare mode control register (OCMOD): MOD1x = 0
- RT0, RT2, RT4: The level is reversed immediately when the compare registers 0, 2, 4 match
the 16-bit free-run timer.
- RT1, RT3, RT5: The level is reversed immediately when the compare registers (0 or 1) (2 or
3) (4 or 5) match the 16-bit free-run timer.
- When the value of the compare register 0, 2, 4 and 1, 3, 5 is the same, the operation is the
same operation as one compare register is used.
The compare mode control register (OCMOD): MOD1x = 1
- Reset to "0" when the match occurs in the up-count mode.
- Set to "1" when the match occurs in the down-count mode.
• The read value is undefined.
bit11,
Undefined bits
bit10
• Writing to these bits has no effect on operation.
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CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
Table 11.4-9 Compare Control Register, Upper Byte (OCSH1, OCSH3, OCSH5) (2 / 2)
Bit name
Function
• This bit is used to change a pin output level of the output compare 1, 3, 5 (RT1, RT3, RT5).
bit9
OTD1:
Output level
bit
• The initial value of the compare pin output is "0".
• Always halt compare operation before writing to the value of this bit. The read value of this bit
indicates the output compare value of RT1, RT3, RT5.
• This bit can be written when CST1: bit1 of the compare control register lower (OCSL) is 0.
• This bit is used to change a pin output level of the output compare 0, 2, 4 (RT0, RT2, RT4).
bit8
OTD0:
Output level
bit
• The initial value of the compare pin output is "0".
• Always halt compare operation before writing to the value of this bit. The read value of this bit
indicates the output compare value of RT0, RT2, RT4.
• This bit can be written when CST0: bit0 of the compare control register lower (OCSL) is 0.
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CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
■ Compare Control Register, Lower Byte (OCSL0, OCSL2, OCSL4)
Compare control register (Lower)
OCSL0, OCSL2, OCSL4
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
IOP1
IOP0
IOE1
IOE0
BUF1
BUF0
CST1
CST0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CST0
Compare operation enable bit
Disable compare operation of compare register 0,2,4
1
Enable compare operation of compare register 0,2,4
Compare operation enable bit
0
Disable compare operation of compare register 1,3,5
1
Enable compare operation of compare register 1,3,5
BUF0
Compare buffer invalid bit
0
Valid compare buffer of compare register 0,2,4
1
Invalid compare buffer of compare register 0,2,4
BUF1
Compare buffer invalid bit
0
Valid compare buffer of compare register 1,3,5
1
Invalid compare buffer of compare register 1,3,5
IOE0
Compare match interrupt enable bit
0
Disable compare match interrupt of compare register 0,2,4
1
Enable compare match interrupt of compare register 0,2,4
IOE1
Compare match interrupt enable bit
0
Disable compare match interrupt of compare register 1,3,5
1
Enable compare match interrupt of compare register 1,3,5
IOP0
Compare match interrupt flag bit
Read
Write
0
Compare match interrupt of compare
register 0,2,4 does not occur.
Clear this bit
1
Compare match interrupt of compare
register 0,2,4 occur.
No effect on this bit
IOP1
CM71-10155-2E
Address
ch.0: 0000ADH
ch.2: 0000AFH
ch.4: 0000B1H
0
CST1
R/W
Initial value: 00001100B
Compare match interrupt flag bit
Read
Write
0
Compare match interrupt of compare
register 1,3,5 does not occur.
Clear this bit
1
Compare match interrupt of compare
register 1,3,5 occur.
No effect on this bit
: Readable/Writable
: Initial value
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CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
Table 11.4-10 Compare Control Register, Lower Byte (OCSL0, OCSL2, OCSL4)
Bit name
Function
• This bit is an interrupt flag which indicates that the compare register 1, 3, 5 matches the
value of the 16-bit free-run timer.
bit7
IOP1:
Compare match
interrupt flag bit
• This bit is set to "1" when the value of the compare register matches the value of the 16-bit
free-run timer.
• When this bit is set while the compare match interrupt enable bit (IOE1: bit5) is enabled, the
output compare interrupt occurs.
• When this bit is set to "0": Clears the bit.
• Setting this bit to "1" has no effect on this bit.
• When this bit is read to a read modify write (RMW) instruction, "1" is always read.
• This bit is an interrupt flag which indicates that the compare register 0, 2, 4 matches the
value of the 16-bit free-run timer.
bit6
IOP0:
Compare match
interrupt flag
bit
• This bit is set to "1" when the value of the compare register matches the value of the 16-bit
free-run timer.
• When this bit is set while the compare match interrupt enable bit (IOE0: bit4) is enabled, the
output compare interrupt occurs.
• When this bit is set to "0": Clears the bit.
• Setting this bit to "1" has no effect on this bit.
• When this bit is read to a read modify write (RMW) instruction, "1" is always read.
bit5
• This bit is used to enable the output compare interrupt of the compare register 1, 3, 5.
IOE1:
Compare match
• An output compare interrupt is generated if this bit is "1" when the compare match interrupt
interrupt enable bit
flag bit (IOP1:bit7) is set.
bit4
• This bit is used to enable the output compare interrupt of the compare register 0, 2, 4.
IOE0:
Compare match
• An output compare interrupt is generated if this bit is "1" when the compare match interrupt
interrupt enable bit
flag bit (IOP0:bit6) is set.
bit3
BUF1:
Compare buffer
disable bit
bit2
BUF0:
Compare buffer
disable bit
• This bit is used to disable the buffer function of the output compare register 1, 3, 5.
• Setting this bit to "0" enables the buffer function.
• Setting this bit to "1" disables the buffer function.
• This bit is used to disable the buffer function of the output compare register 0, 2, 4.
• Setting this bit to "0" enables the buffer function.
• Setting this bit to "1" disables the buffer function.
bit1
CST1:
Compare
operation enable
bit
• This bit is used to enable the compare operation between the 16-bit free-run timer and
compare register 1, 3, 5.
bit0
CST0:
Compare
operation enable
bit
• This bit is used to enable the compare operation between the 16-bit free-run timer and
compare register 0, 2, 4.
242
• Before enabling compare operation, always write values to compare registers 1, 3, and 5,
and to the timer data registers (TCDTH and TCDTL).
• Before enabling compare operation, always write values to compare registers 0, 2, and 4,
and to the timer data registers (TCDTH and TCDTL).
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
11.4.8
Compare Mode Control Register (OCMOD0)
The compare mode control register controls the mode for inverting the output level
when a compare match occurs and whether to set or reset.
■ Compare Mode Control Register (OCMOD0)
Compare mode control register
Address
ch.0: 0000B2H
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
-
-
MOD15
MOD14
MOD13
MOD12
MOD11
MOD10
-
-
R/W
R/W
R/W
R/W
R/W
R/W
MOD10
0
1
MOD11
0
1
MOD12
0
1
MOD13
0
1
MOD14
0
1
MOD15
0
R/W
-
CM71-10155-2E
: Readable/Writable
: Initial value
: Undefined bit
1
OCMOD0
Initial value : --000000
B
ch.0 compare match output setting bit
Reverse previous output value
Set to "1" or reset to "0"
by CMOD
ch.1 compare match output setting bit
Reverse previous output value
Set to "1" or reset to "0"
by CMOD
ch.2 compare match output setting bit
Reverse previous output value
Set to "1" or reset to "0"
by CMOD
ch.3 compare match output setting bit
Reverse previous output value
Set to "1" or reset to "0"
by CMOD
ch.4 compare match output setting bit
Reverse previous output value
Set to "1" or reset to "0"
by CMOD
ch.5 compare match output setting bit
Reverse previous output value
Set to "1" or reset to "0"
FUJITSU SEMICONDUCTOR LIMITED
by CMOD
243
CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
Table 11.4-11 Compare Mode Control Register (OCMOD0)
Bit name
bit15,
Undefined bits
bit14
bit13
MOD15:
ch.5 compare match mode
setting bit
bit12
MOD14:
ch.4 compare match mode
setting bit
bit11
MOD13:
ch.3 compare match mode
setting bit
bit10
MOD12:
ch.2 compare match mode
setting bit
Function
• The read value is undefined.
• Writing to these bits has no effect the operation.
• These bits specify the operation when the compare match of the output compare
output occurs.
• The initial value is "0".
• When the bits are set to "0", reverse the output value temporarily when the match
occurs.
• When the bits are set to "1", set the output value to "1" or reset the output value to
"0" when the match occurs. CMOD bit of the compare control register (OCSH)
sets the set/reset switch.
• Before data is written, be sure to stop the compare operation.
• CMOD is set for ch.0 and ch.1, ch.2 and ch.3, ch.4 and ch.5.
MOD11:
ch.1 compare match mode
setting bit
- Reset/set is not available to ch.0 and ch.1 separately.
bit9
MOD10:
ch.0 compare match mode
setting bit
- Reset/set is not available to ch.4 and ch.5 separately.
bit8
244
- Reset/set is not available to ch.2 and ch.3 separately.
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
11.4.9
Input Capture Data Register (IPCPH0 to IPCPH3,
IPCPL0 to IPCPL3)
The input capture data register is used to store the count value of the free-run timer on
detection of a valid edge of the input waveform.
■ Input Capture Data Register (IPCPH0 to IPCPH3, IPCPL0 to IPCPL3)
Input capture data register (Upper)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
CP15
CP14
CP13
CP12
CP11
CP10
CP09
CP08
R
R
R
R
R
R
R
R
Input capture data register (Lower)
bit7
IPCPL0 to IPCPL3
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CP07
CP06
CP05
CP04
CP03
CP02
CP01
CP00
R
R
R
R
R
R
R
R
IPCPH0 to IPCPH3
Address
ch.0: 0000D4H
ch.1: 0000D6H
ch.2: 0000D8H
ch.3: 0000DAH
R:
Initial value
XXXXXXXX B
Initial value
XXXXXXXX B
Read only
This register is used to store the value of the free-run timer each time the specified edge is detected on the
waveform input to the corresponding external pin. (Always use half-word or word access instructions to
access this register. Writing data to this register is not permitted.)
The free-run timer in the above explanation refers to the operation of the free-run timer selected for input
capture.
CM71-10155-2E
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CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
Input Capture State Control/PPG Output Control Register
(ICSH23, ICSL23, PICSH01, PICSL01)
11.4.10
The input capture state control/PPG output control register (ICSH23, ICSL23, PICSH01,
PICSL01) is used to control the edge selection, the interrupt request enable, the
interrupt request flag, and the PPG output. This register is also used to indicate a valid
edge which was detected on the input capture 2 and 3.
■ Input Capture State Control Register (ch.2, ch.3), Upper Byte (ICSH23)
Input capture state control register (Upper)
Address
ch.0: 0000DEH
bit15
bit9
bit8
-
bit14
-
bit13
-
bit12
-
bit11
-
-
IEI3
IEI2
-
-
-
-
-
-
R
R
IEI2
-
246
: Read only
: Initial value
: Undefined bit
ICSH23
Initial value : ------00
B
Valid edge indication bit (input capture 2)
0
Falling edge is detected .
1
Rising edge is detected .
IEI3
R
bit10
Valid edge indication bit (input capture 3)
0
Falling edge is detected .
1
Rising edge is detected .
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
Table 11.4-12 Input Capture State Control Register (ch.2, ch.3), Upper Byte (ICSH23)
Bit name
Function
• The read value is undefined.
bit15
to
Undefined bits
bit10
• Writing to these bits has no effect on operation.
• This bit specifies the valid edge indication bit for capture register 3 and indicates whether a
rising edge or falling edge was detected.
bit9
IEI3:
Valid edge
indication bit
(Input capture
3)
• "0" is written to this bit when a falling edge is detected.
• "1" is written to this bit when a rising edge is detected.
• This bit is a read only bit.
Note:
When the lower of the input capture state control register (ICSL23), EG31, EG30: bit3, bit2 =
00B, the read value has no meaning.
• This bit specifies the valid edge indication bit for capture register 2 and indicates whether a
rising edge or falling edge was detected.
bit8
IEI2:
Valid edge
indication bit
(Input capture
2)
CM71-10155-2E
• "0" is written to this bit when a falling edge is detected.
• "1" is written to this bit when a rising edge is detected.
• This bit is a read only bit.
Note:
When the lower of the input capture state control register (ICSL23), EG21, EG20: bit1, bit0 =
00B, the read value has no meaning.
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CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
■ Input Capture State Control Register (ch.2, ch.3), Lower Byte (ICSL23)
Input capture state control register (Lower)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ICP3
ICP2
ICE3
ICE2
EG31
EG30
EG21
EG20
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EG20
Edge selection bits (input capture 2)
0
0
Edge is not detected (stop)
0
1
Rising edge is detected .
1
0
Falling edge is detected .
1
1
Both edges are detected .
0
Edge is not detected (stop)
0
1
Rising edge is detected .
1
0
Falling edge is detected .
1
1
Both edges are detected .
Interrupt request enable bit (input capture 2)
0
Disable interrupt request
1
Enable interrupt request
ICE3
Interrupt request enable bit (input capture 3)
0
Disable interrupt request
1
Enable interrupt request
ICP2
Interrupt request flag bit (input capture 2)
Read
Write
0
Valid edge is not detected
This bit is cleared .
1
Valid edge is detected
No ef fect on this bit
ICP3
248
Edge selection bits (input capture 3)
0
ICE2
B
Address
ch.0: 0000DFH
EG21
EG31 EG30
R/W
ICSL23
Initial value : 00000000
Interrupt request flag bit (input capture 3)
Read
Write
0
Valid edge is not detected
This bit is cleared .
1
Valid edge is detected
No ef fect on this bit
: Readable/Writable
: Initial value
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
MB91490 Series
CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
Table 11.4-13 Input Capture State Control Register (ch.2, ch.3), Lower Byte (ICSL23)
Bit name
Function
• This bit is used as an interrupt request flag of the input capture 3.
bit7
ICP3:
Interrupt request
flag bit
(Input capture 3)
• This bit is set to "1" immediately when a valid edge of an external input pin is
detected.
• When a valid edge is detected while the interrupt request enable bit (ICE3: bit5) is
set, the interrupt can be generated immediately.
• When this bit is set to "0": Clears the bit.
• Setting this bit to "1" has no effect on this bit.
• When this bit is read to a read modify write (RMW) instruction, "1" is always read.
• This bit is used as an interrupt request flag of the input capture 2.
bit6
ICP2:
Interrupt request
flag bit
(Input capture 2)
• This bit is set to "1" immediately when a valid edge of an external input pin is
detected.
• When a valid edge is detected while the interrupt request enable bit (ICE2: bit4) is
set, the interrupt can be generated immediately.
• When this bit is set to "0": Clears the bit.
• Setting this bit to "1" has no effect on this bit.
• When this bit is read to a read modify write (RMW) instruction, "1" is always read.
• This bit is used to enable an input capture interrupt request of the input capture 3.
bit5
ICE3:
Interrupt request
enable bit
(Input capture 3)
bit4
ICE2:
Interrupt request
enable bit
(Input capture 2)
bit3,
bit2
EG31, EG30:
Edge selection bits
(Input capture 3)
• These bits are used to specify the active edge polarity for the external input to input
capture 3.
EG21, EG20:
Edge selection bits
(Input capture 2)
• These bits are used to specify the active edge polarity for the external input to input
capture 2.
bit1,
bit0
CM71-10155-2E
• When the interrupt request flag bit (ICP3: bit7) is set while this bit is set to "1", the
input capture 3 interrupt is generated.
• This bit is used to enable an input capture interrupt request of the input capture 2.
• When the interrupt request flag bit (ICP2: bit6) is set while this bit is set to "1", the
input capture 2 interrupt is generated.
• These bits are used also to enable an operation of the input capture 3.
• These bits are used also to enable an operation of the input capture 2.
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CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
■ PPG Output Control Register Upper Byte (PICSH01)
PPG output control register (Upper)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
PGEN5
PGEN4
PGEN3
PGEN2
PGEN1
PGEN0
IEI1
IEI0
W
W
W
W
W
R
R
W
Valid edge indication bit (input capture 0)
0
Falling edge is detected .
1
Rising edge is detected .
IEI1
Valid edge indication bit (input capture 1)
0
Falling edge is detected .
1
Rising edge is detected .
PPG output enable bit
0
Disa ble configured PPG output to RTO0.
1
Ena ble configured PPG output to RTO0.
PGEN1
PPG output enable bit
0
Disa ble configured PPG output to RTO1.
1
Ena ble configured PPG output to RTO1.
PGEN2
PPG output enable bit
0
Disa ble configured PPG output to RTO2.
1
Ena ble configured PPG output to RTO2.
PGEN3
PPG output enable bit
0
Disa ble configured PPG output to RTO3.
1
Ena ble configured PPG output to RTO3.
PGEN4
PPG output enable bit
0
Disa ble configured PPG output to RTO4.
1
Ena ble configured PPG output to RTO4.
PGEN5
B
Address
ch.0: 0000DCH
IEI0
PGEN0
R
W
PICSH01
Initial value : 00000000
PPG output enable bit
0
Disa ble configured PPG output to RTO5.
1
Ena ble configured PPG output to RTO5.
: Read only
: W rite only
: Initial value
250
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
Table 11.4-14 PPG Output Control Register Upper Byte (PICSH01)
Bit name
bit15
to
bit10
PGEN5 to
PGEN0:
PPG output
enable bits
Function
• These bits are used to select the PPG output to RTO0 to RTO5.
• These bits are write-only.
• This bit specifies the valid edge indication bit for capture register 1 and indicates
whether a rising edge or falling edge was detected.
bit9
IEI1:
Valid edge
indication bit
(Input capture
1)
• "0" is written to this bit when a falling edge is detected.
• "1" is written to this bit when a rising edge is detected.
• This bit is a read only bit.
Note:
When the lower of the input capture state control register (PICSL01), EG11, EG10: bit3,
bit2 = 00B, the read value has no meaning.
• This bit specifies the valid edge indication bit for capture register 0 and indicates
whether a rising edge or falling edge was detected.
bit8
IEI0:
Valid edge
indication bit
(Input capture
0)
CM71-10155-2E
• "0" is written to this bit when a falling edge is detected.
• "1" is written to this bit when a rising edge is detected.
• This bit is a read only bit.
Note:
When the lower of the input capture state control register (PICSL01), EG01, EG00: bit1,
bit0 = 00B, the read value has no meaning.
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CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
■ Input Capture State Control Register (ch.01) Lower Byte (PICSL01)
Input capture state control register (lower)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ICP1
ICP0
ICE1
ICE0
EG11
EG10
EG01
EG00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PICSL01
Initial value : 00000000
B
Address
ch.0: 0000DDH
EG01
EG00
0
0
Edge is not detected (stop)
0
1
Rising edge is detected .
1
0
Falling edge is detected.
1
1
EG11
EG10
0
0
Edge is not detected (stop)
0
1
Rising edge is detected .
1
0
Falling edge is detected.
1
1
ICE0
Both edge are detected .
Interrupt request enable bit (input capture 0)
Disable inter rupt request
Enable inter rupt request
Interrupt request enable bit (input capture 1)
0
Disable inter rupt request
1
Enable inter rupt request
Interrupt request flag bit (input capture 0)
Read
0
Valid edge is not detected.
1
Valid edge is detected .
ICP1
252
Edge selection bits (input capture 1)
1
ICP0
: Readable/Writable
: Initial value
Both edge are detected .
0
ICE1
R/W
Edge selection bits (input capture 0)
Write
This bit is cleared .
No effect on this bit .
Interrupt request flag bit (input capture 1)
Read
0
Valid edge is not detected .
1
Valid edge is detected .
FUJITSU SEMICONDUCTOR LIMITED
Write
This bit is cleared .
No effect on this bit .
CM71-10155-2E
CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
Table 11.4-15 Input Capture State Control Register (ch.01) Lower Byte (PICSL01)
Bit name
Function
• This bit is used as an interrupt request flag of the input capture 1.
• This bit is set to "1" immediately when a valid edge of an external input pin is detected.
ICP1:
Interrupt request
bit7
flag bit
(Input capture 1)
• When a valid edge is detected while the interrupt request enable bit (ICE1: bit5) is set, the
interrupt is generated immediately.
• When this bit is set to "0": Clears the bit.
• Setting this bit to "1" has no effect on this bit.
• When this bit is read to a read modify write (RMW) instruction, "1" is always read.
• This bit is used as an interrupt request flag of the input capture 0.
• This bit is set to "1" immediately when a valid edge of an external input pin is detected.
ICP0:
Interrupt request
bit6
flag bit
(Input capture 0)
• When a valid edge is detected while the interrupt request enable bit (ICE0: bit4) is set, the
interrupt is generated immediately.
• When this bit is set to "0": Clears the bit.
• Setting this bit to "1" has no effect on this bit.
• When this bit is read to a read modify write (RMW) instruction, "1" is always read.
ICE1:
Interrupt request
bit5
enable bit
(Input capture 1)
ICE0:
Interrupt request
bit4
enable bit
(Input capture 0)
• This bit is used to enable an input capture interrupt request of the input capture 1.
• When the interrupt request flag bit (ICP1: bit7) is set while this bit is set to "1", the input
capture 1 interrupt is generated.
• This bit is used to enable an input capture interrupt request of the input capture 0.
• When the interrupt request flag bit (ICP0: bit6) is set while this bit is set to "1", the input
capture 0 interrupt is generated.
• These bits are used to specify the active edge polarity for the external input to input capture
EG11,EG10:
bit3,
1.
Edge selection bits
bit2
(Input capture 1)
• These bits are used also to enable an operation of the input capture 1.
• These bits are used to specify the active edge polarity for the external input to input capture
EG01,EG00:
bit1,
0.
Edge selection bits
bit0
(Input capture 0)
• These bits are used also to enable an operation of the input capture 0.
CM71-10155-2E
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CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
11.4.11
MB91490 Series
16-bit Dead Timer Register (TMRRH0 to TMRRH2,
TMRRL0 to TMRRL2)
The 16-bit dead timer register stores the compare value of the 16-bit dead timer.
■ 16-bit Dead Timer Register (TMRRH0 to TMRRH2, TMRRL0 to TMRRL2)
16-bit dead timer register (Upper)
TMRRH0 to TMRRH2
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
TR15
TR14
TR13
TR12
TR11
TR10
TR09
TR08
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
16-bit dead timer register (Lower)
TMRRL0 to TMRRL2
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
TR07
TR06
TR05
TR04
TR03
TR02
TR01
TR00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
Wave Generator 0
ch.0: 0000E0H
ch.1: 0000E2H
ch.2: 0000E4H
Initial value
XXXXXXXXB
Initial value
XXXXXXXXB
R/W: Readable/Writable
These registers are used to store the compare value for the 16-bit dead timer.
These register values are reloaded when the 16-bit dead timer starts the operation.
If the values are rewritten to these registers during the timer operation, these new values are enabled in the
next timer start/operation.
To access these registers, use a half-word or word access instruction.
In the dead time timer mode, these registers are used to set the non-overlap time.
Non-overlap time = (Setting value) × Selected clock
Note:
"0000H" cannot be set.
In the timer mode, these registers are used to set the GATE time of the PPG timer operation.
GATE time = (Setting value) × Selected clock
Note:
"0000H" cannot be set.
254
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
11.4.12
16-bit Dead Timer Control Register (DTCR0 to DTCR2)
The 16-bit dead timer control register (DTCR0 to DTCR2) is used to control the operation
mode of the waveform generator, the interrupt request enable, the interrupt request flag, the
GATE signal enable, and the output level polarity.
■ 16-bit Dead Timer Control Register, Upper Byte (DTCR0)
16-bit dead timer control register
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
DMOD0
GTEN1
GTEN0
TMIF0
TMIE0
TMD2
TMD1
TMD0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DTCR0
Initial value : 00000000
TMD2
TMD1
TMD0
0
0
0
Ope ration mode bits
0
0
1
PPG timer outputs pulse while R T signal is at "H" .
0
1
0
Rising edge of each RT signal becomes trigger, and
16-bit dead timer starts. The PPG timer outputs
pulse until the 16-bit dead timer stops. (timer mode)
1
0
0
Non-overlap signal is generated by the RT signal.
(dead time timer mode)
1
1
1
Disable
Waveform gene rator stops.
Other
TMIE0
0
1
TMIF0
0
1
GTEN0
Interrupt request enable bit, software trigger bit
Interrupt is not gene rated even though underfl ow is generated
in 16-bit dead timer.
Interrupt is generated when underflow is generated in 16-bit
dead timer.
Interrupt request flag bit
Read
Write
Underflow of counter is not
detected.
Underflow of counter is
detected.
This bit is cleared .
No effect on this bit .
G ATE signal control bit 0
The GATE signal is not controlled by RT0. (asynchronous mode)
1
The GATE signal is controlled by RT0. (synchronous mode)
G ATE signal control bit 1
0
The GATE signal is not controlled by RT1. (asynchronous mode)
1
The GATE signal is controlled by RT1. (synchronous mode)
DMOD0
CM71-10155-2E
Disable
0
GTEN1
R/W
B
Address
Waveform generator0
ch.0: 0000E8H
Output polarity control bit
0
Normal polarity output
1
Reverse polarity output
: Reada ble/Writable
: Initial value
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255
CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
Table 11.4-16 16-bit Dead Timer Control Register, Upper Byte (DTCR0)
Bit name
Function
• This bit is used to set the U/V/W output in the dead time timer mode.
DMOD0:
bit15 Output polarity
control bit
• Setting this bit reverses the U/V/W output polarity.
GTEN1:
bit14 GATE signal
control bit1
This bit is used to control the GATE signal of the PPG timer with RT1.
GTEN0:
bit13 GATE signal
control bit0
This bit is used to control the GATE signal of the PPG timer with RT0.
Note:
When the dead time timer mode is not selected, (TMD2: bit10 = 0), this bit has no meaning.
• This bit is used as an interrupt request flag of the 16-bit dead timer.
• This bit is set to "1" when an underflow occurs on the 16-bit dead timer.
• Writing "0" to this bit clears the bit. Writing "1" to this bit has no effect on this bit.
TMIF0:
bit12 Interrupt request
flag bit
• When this bit is read to a read modify write (RMW) instruction, "1" is always read.
Note:
This bit works only when the register values (TMD2 to TMD0: bit10 to bit8) are 000B or 001B,
and becomes always "0" when they are other values.
If a software clear (writing "0") and hardware set (underflow on 16-bit dead timer 0) occur
simultaneously, the software operation has precedence and the bit is cleared.
• This bit is used as a software trigger bit and an interrupt enable bit of the 16-bit dead timer.
• TMD2 to TMD0: bit10 to bit8 = 000B or 001B:
TMIE0:
Interrupt request
bit11 enable bit,
software trigger
bit
This bit is used as a software trigger of the 16-bit dead timer. When this bit changes from "0" to
"1", it becomes a trigger of the 16-bit dead timer, reloads the value, and starts the down count.
• When this bit is "1" and the interrupt request flag bit (TMIF0: bit12) is "1", an interrupt
request is sent to the CPU.
Note:
To trigger the 16-bit dead timer again, you must write "0" to this bit before writing "1".
• These bits are used to select the operation mode of the waveform generator.
• TMD2 to TMD0: bit10 to bit8 = 000B:
The RT0 and RT1 signals of the output compare are respectively output from the RTO0 and
RTO1. The 16-bit dead timer is also used as a reload timer.
bit10 TMD2 to TMD0:
to Operation mode
bit8 bits
• TMD2 to TMD0: bit10 to bit8 = 001B:
The RT0 and RT1 signals of the output compare are respectively output from RTO0 and
RTO1 when the PPG output is disabled (the upper of the PPG output control/input capture
state control register (PICSH01), PGEN0: bit10 = 0, PGEN1: bit11 = 0). The 16-bit dead
timer is also used as a reload timer.
Note:
Always select two-channel mode for RT1 (set bit12 (CMOD) in the upper compare control register (OSCH1)=1) to use the waveform generator in dead time timer mode.
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CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
■ 16-bit Dead Timer Control Register, Lower Byte (DTCR1)
16-bit dead timer control register
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
DMOD1
GTEN3
GTEN2
TMIF1
TMIE1
TMD5
TMD4
TMD3
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TMD5 TMD4
Address
Waveform generator0
ch.1: 0000E9H
Waveform generator stops.
0
0
0
0
0
1
PPG timer outputs pulse while
0
1
0
Rising edge of each R T signal becomes trigger,
and 16-bit dead timer start s . The PPG timer outputs
pulse until the 16-bit dead timer stop s. (timer mode)
1
0
0
Non-overlap signal is generated by the R T
signal . (dead time timer mode)
1
1
1
TMIE1
0
1
TMIF1
0
1
GTEN2
R T signal is at "H" .
Disable
Disable
Interrupt request enable bit, soft ware trigger bit
Interrupt is not generated even though underflow is generated
in 16-bit dead timer.
Interrupt is gene rated when underfl ow is generated in 16-bit
dead timer.
Interrupt request flag bit
Read
Write
Underflow of counter is not
detected.
Underflow of counter is
detected.
This bit is cleared .
No effect on this bit .
G ATE signal control bit 2
0
The GATE signal is not controlled by RT2. (asynchronous mode)
1
The GATE signal is controlled by RT2. (synchronous mode)
GTEN3
G ATE signal control bit 3
0
The GATE signal is not controlled by RT3. (asynchronous mode)
1
The GATE signal is controlled by RT3. (synchronous mode)
DMOD1
CM71-10155-2E
B
Operation mode bits
TMD3
Other
R/W
DTCR1
Initial value : 00000000
Output polarity control bit
0
Normal polarity output
1
Reverse polarity output
: Readable/Writable
: Initial value
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CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
Table 11.4-17 16-bit Dead Timer Control Register, Lower Byte (DTCR1)
Bit name
Function
• This bit is used to set the U/V/W output in the dead time timer mode.
DMOD1:
bit7 Output polarity
control bit
• Setting this bit reverses the U/V/W output polarity.
Note:
When the dead time timer mode is not selected, (TMD5: bit2 = 0), this bit has no meaning.
GTEN3:
bit6 GATE signal
control bit3
This bit is used to control the GATE signal of the PPG timer with RT3.
GTEN2:
bit5 GATE signal
control bit2
This bit is used to control the GATE signal of the PPG timer with RT2.
• This bit is used as an interrupt request flag of the 16-bit dead timer.
• This bit is set to "1" when an underflow occurs on the 16-bit dead timer.
• Writing "0" to this bit clears the bit. Writing "1" to this bit has no effect on this bit.
TMIF1:
• When this bit is read to a read modify write (RMW) instruction, "1" is always read.
bit4 Interrupt request
Note:
flag bit
This bit works only when the register values (TMD5 to TMD3: bit2 to bit0) are "000B" or
"001B", and becomes always 0 when they are other values.
If a software clear (writing "0") and hardware set (underflow on 16-bit dead timer 1) occur simultaneously, the software operation has precedence and the bit is cleared.
• This bit is used as a software trigger bit and an interrupt enable bit of the 16-bit dead timer.
• TMD5 to TMD3: bit2 to bit0 = 000B or 001B:
TMIE1:
This bit is used as a software trigger of the 16-bit dead timer. When this bit changes from "0" to
Interrupt request
"1", it becomes a trigger of the 16-bit dead timer, reloads the value, and starts the down count.
bit3 enable bit,
software trigger • When this bit is "1" and the interrupt request flag bit (TMIF1: bit4) is "1", an interrupt request
bit
is sent to the CPU.
Note:
To trigger the 16-bit dead timer again, you must write "0" to this bit before writing "1".
• These bits are used to select the operation mode of the waveform generator.
• TMD5 to TMD3: bit2 to bit0 = 000B:
The RT2 and RT3 signals of the output compare are respectively output from the RTO2 and
RTO3. The 16-bit dead timer is also used as a reload timer.
bit2 TMD5 to TMD3:
to Operation mode
bit0 bits
• TMD5 to TMD3: bit2 to bit0 = 001B:
The RT2 and RT3 signals of the output compare are respectively output from the RTO2 and
RTO3 when the PPG0 output is disabled (the upper of the PPG output control/input capture
state control register (PICSH01), PGEN2: bit12=0, PGEN3: bit13=0). The 16-bit dead timer is
also used as a reload timer.
Note:
Always select two-channel mode for RT3 (set bit12 (CMOD) in the upper compare control register (OCSH3)=1) to use the waveform generator in dead time timer mode.
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CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
■ 16-bit Dead Timer Control Register, Upper Byte (DTCR2)
16-bit dead timer control register
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
DMOD2
GTEN5
GTEN4
TMIF2
TMIE2
TMD8
TMD7
TMD6
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
Waveform generator0
ch.2: 0000EAH
TMD7
TMD6
0
0
0
0
0
1
PPG timer outputs pulse while R T signal is at "H" .
0
1
0
Rising edge of each R T signal becomes t rigger,
and 16-bit dead timer star ts. The PPG timer outputs
pulse until the 16-bit dead timer stop s. (timer mode)
1
0
0
Non-overlap signal is generated by the R T
signal . (dead time timer mode)
1
1
1
TMIE2
0
1
TMIF2
0
1
GTEN4
Ope ration mode bits
Waveform gene rator stop s.
Disable
Disable
Interrupt request ena ble bit, soft ware t rigger bit
Interrupt is not generated even though underfl ow is generated
in 16-bit dead timer.
Interrupt is generated when underfl ow is generated in 16-bit
dead time r.
Interrupt request flag bit
Read
Write
Underflow of counter is not
detected.
Underflow of counter is
detected.
This bit is cleared .
No ef fect on this bit .
G ATE signal control bit 4
0
The GATE signal is not controlled by RT4. (asynchronous mode)
1
The GATE signal is controlled by RT4. (synchronous mode)
GTEN5
G ATE signal control bit 5
0
The GATE signal is not controlled by RT5. (asynchronous mode)
1
The GATE signal is controlled by RT5. (synchronous mode)
DMOD2
CM71-10155-2E
B
TMD8
Other
R/W
DTCR2
Initial value : 00000000
Output polarity control bit
0
Normal polarity output
1
R everse polarity output
: Readable/Writable
: Initial value
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CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
Table 11.4-18 16-bit Dead Timer Control Register, Upper Byte (DTCR2)
Bit name
Function
• This bit is used to set the U/V/W output in the dead time timer mode.
DMOD2:
bit15 Output polarity
control bit
• Setting this bit reverses the U/V/W output polarity.
Note:
When the dead time timer mode is not selected, (TMD8: bit10 = 0), this bit has no meaning.
GTEN5:
bit14 GATE signal
control bit5
This bit is used to control the GATE signal of the PPG timer with RT5.
GTEN4:
bit13 GATE signal
control bit4
This bit is used to control the GATE signal of the PPG timer with RT4.
• This bit is used as an interrupt request flag of the 16-bit dead timer.
• This bit is set to "1" when an underflow occurs on the 16-bit dead timer.
• Writing "0" to this bit clears the bit. Writing "1" to this bit has no effect on this bit.
TMIF2:
bit12 Interrupt request
flag bit
• When this bit is read to a read modify write (RMW) instruction, "1" is always read.
Note:
This bit works only when the register values (TMD8 to TMD6: bit10 to bit8) are "000B" or
"001B", and becomes always "0" when they are other values.
If a software clear (writing "0") and hardware set (underflow on 16-bit dead timer 2) occur
simultaneously, the software operation has precedence and the bit is cleared.
• This bit is used as a software trigger bit and an interrupt enable bit of the 16-bit dead timer.
• TMD8 to TMD6: bit10 to bit8 = 000B or 001B:
TMIE2:
Interrupt request
bit11 enable bit,
software trigger
bit
This bit is used as a software trigger of the 16-bit dead timer. When this bit changes from "0" to
"1", it becomes a trigger of the 16-bit dead timer, reloads the value, and starts the down count.
• When this bit is "1" and the interrupt request flag bit (TMIF2: bit12) is "1", an interrupt
request is sent to the CPU.
Note:
To trigger the 16-bit dead timer again, you must write "0" to this bit before writing "1".
• These bits are used to select the operation mode of the waveform generator.
• TMD8 to TMD6: bit10 to bit8 = 000B:
The RT4 and RT5 signals of the output compare are respectively output from the RTO4 and
RTO5. The 16-bit dead timer is also used as a reload timer.
bit10 TMD8 to TMD6:
to Operation mode
bit8 bits
• TMD8 to TMD6: bit10 to bit8 = 001B
The RT4 and RT5 signals of the output compare are respectively output from the RTO4 and
RTO5 when the PPG output is disabled (the upper of the PPG output control/input capture
state control register (PICSH01), PGEN4: bit14 = 0, PGEN5: bit15 = 0). The 16-bit dead
timer is also used as a reload timer.
Note:
Always select two-channel mode for RT5 (set bit12 (CMOD) in the upper compare control
register (OCSH5)=1) to use the waveform generator in dead time timer mode.
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CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
11.4.13
Waveform Control Register (SIGCR1/SIGCR2)
The waveform control register is used to control the operating clock frequency, enable the noise
cancellation feature, enable DTTI input, and control DTTI interrupts.
■ Waveform Control Register 1 (SIGCR1)
Waveform control register 10
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
DTIE
DTIF
NRSL
DCK2
DCK1
DCK0
NWS1
NWS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
NWS1 NWS0
SIGCR1
Initial value: 00000000B
Address
Waveform generator0
ch.10: 0000EDH
DTTI0 noise width selection bits
0
0
0
1
Cancel noise of 8 peripheral clock (CLKP) cycles
1
0
Cancel noise of 16 peripheral clock (CLKP) cycles
1
1
Cancel noise of 32 peripheral clock (CLKP) cycles
DCK2 DCK1
Cancel noise of 4 peripheral clock (CLKP) cycles
DCK0
Operation clock selection bits
0
0
0
φ (50 ns, φ=20 MHz)
0
0
1
φ/2 (100 ns, φ=20 MHz)
0
1
0
φ/4 (200 ns, φ=20 MHz)
0
1
1
φ/8 (400 ns, φ=20 MHz)
1
0
0
φ /16 (800 ns, φ=20 MHz)
1
0
1
φ /32 (1.6 μs, φ=20 MHz)
1
1
0
φ /64 (3.2 μs, φ=20 MHz)
1
1
1
φ: Peripheral clock (CLKP)
NRSL
Noise cancel circuit of DTTI0 input is invalid.
1
Noise cancel circuit of DTTI0 input is valid.
CM71-10155-2E
DTTI0 interrupt flag bit
Read
Write
0
No interrupt request
1
Interrupt request
DTIE
: Readable/Writable
: Initial value
Noise cancel function valid bit
0
DTIF
R/W
Disable
This bit is cleared.
No effect on this bit.
DTTI0 input valid bit
0
Invalid DTTI0 input
1
Valid DTTI0 input
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11.4 Multi-function Timer Register
MB91490 Series
Table 11.4-19 Waveform Control Register1 (SIGCR1)
Bit name
bit7
DTIE:
DTTI0 input
enabled bit
Function
This bit is used to enable the output level control DTTI signal of RTO0 to RTO5 pins.
• This bit is the DTTI0 interrupt flag.
• When DTTI0 input is enabled (DTIE: bit7 = 1) and DTTI0 "L" level is detected, this bit is
set, and an interrupt request is generated.
• When this bit is set to "0": Clears the bit.
bit6
DTIF:
DTTI0 interrupt
flag bit
• Setting this bit to "1" has no effect on this bit.
• "1" is always read during read modify write (RMW) instruction.
Note:
When the noise cancellation feature is enabled (NRSL: bit5 = 1), this bit is set to "1" when a
noise pulse is generated.
If a software clear (write 0) and hardware set (DTTI0 "L" level detected) occur simultaneously, the software clear is given precedence over the hardware set, and this bit is cleared.
• This bit is used to enable the noise cancellation feature.
bit5
bit4
to
bit2
NRSL:
Noise cancellation
feature enabled bit
DCK2 to DCK0:
Operation clock
selection bits
NWS1, NWS0:
bit1,
DTTI0 noise width
bit0
selection bits
262
• The noise canceling circuit accepts the DTTI0 input signal if it remains at the "L" level
until an overflow occurs on the counter. The counter is an n-bit counter operated by Low
level input. n is set by NWS1 bit and NWS0 bit; Based on the settings of bit1 and bit0, the
value of n is 2, 3, 4, or 5.
Note:
Approximately 2n peripheral clock (CLKP) are required to cancel the noise pulse width.
When a noise cancellation circuit is selected, input is disabled when in a mode that stops the
peripheral clock (CLKP) (e.g. stop mode).
These bits are used to select the operating clock for the 16-bit dead timer.
These bits are used to select the width of noise pulses to reject on the DTTI0 pin.
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
■ Waveform Control Register 2 (SIGCR2)
Waveform control register 2
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
PSEL21
PSEL20
PSEL11
PSEL10
PSEL01
PSEL00
-
DTTI
R/W
R/W
R/W
R/W
R/W
R/W
-
R/W
SIGCR2
Initial value: 000000-1B
Address
Waveform generator0
ch.20: 0000EFH
DTTI
Software DTTI set bit
1
Clear DTTI
0
Set DTTI
PSEL0[1:0]
0
0
PPG0
0
1
PPG2
1
0
1
1
PSEL1[1:0]
-
PPG4
Prohibited setting (Operation does not guarantee)
PPG Input channel setting bits (RTO23)
0
0
PPG0
0
1
PPG2
1
0
1
1
PSEL2[1:0]
R/W
PPG Input channel setting bits (RTO01)
PPG4
Prohibited setting (Operation does not guarantee)
PPG Input channel setting bits (RTO45)
0
0
PPG0
0
1
PPG2
1
0
1
1
PPG4
Prohibited setting (Operation does not guarantee)
: Reada ble/Writable
: Initial value
: Undefined bit
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CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
Table 11.4-20 Waveform Control Register 2 (SIGCR2)
Bit name
Function
bit7,
bit6
PSEL2[1:0]:
• These register bits are to set the input PPG for output RTO45.
PPG input channel
• PSEL2[1:0]=11B is prohibited setting.
setting bits (RTO45)
bit5,
bit4
PSEL1[1:0]:
• These register bits are to set the input PPG for output RTO23.
PPG input channel
• PSEL1[1:0]=11B is prohibited setting.
setting bits (RTO23)
bit3,
bit2
PSEL0[1:0]:
• These register bits are to set the input PPG for output ROT01.
PPG input channel
• PSEL0[1:0]=11B is prohibited setting.
setting bits (RTO01)
bit1
Undefined bit
• The read value is undefined.
• Writing to this bit has no effect on operation.
• Write "0" to set DTTI0.
bit0
264
DTTI:
Software DTTI bit
• Write "1" to this bit to clear it.
Note: As this uses the external input DTTI0 and OR, however, DTTI0 depends on
the external input level.
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
11.4.14
A/D Activation Compare Register (ADCOMPB0,
ADCOMPB2, ADCOMP0, ADCOMP2, ADTGCE0,
ADTGSEL0, ADTGBUF0)
Compare registers 0, 2 activate A/D converters when their values match that of the freerun timer. The compare register buffer is used to write compare values.
The control register can select whether the A/D activation request is generated when
the compare match occurs.
■ Compare Buffer Register 0, 2 (ADCOMPB0, ADCOMPB2)
Compare buffer register 0,2 (Upper)
ADCOMPB0, ADCOMPB2
Address
ch.0: 0000F0H
ch.2: 0000F8H
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
CMP15
CMP14
CMP13
CMP12
CMP11
CMP10
CMP09
CMP08
W
W
W
W
W
W
W
W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CMP07
CMP06
CMP05
CMP04
CMP03
CMP02
CMP01
CMP00
W
W
W
W
W
W
Address (ADCOMPBD)
ch.0: 0000F2H
ch.2: 0000FAH
Compare buffer register 0,2 (Lower)
W
W
W: Write only
The compare buffer register is a buffer register for A/D activation compare register (ADCOMP).
When the buffer function is disabled (buffer control register (ADTGBUF), BUFX2, BUFX0:bit2, bit0 =
11B), or the free-run timer is stopped, the value of the compare buffer register is transferred to the compare
register immediately. When the buffer function is enabled (buffer control register (ADTGBUF), BUFX2,
BUFX0:bit2, bit0 = 00B), the value is transferred to the compare register when a compare match or a zero
detection occurs.
When count direction selection register (ADTGSEL), SEL1, SEL0 = 11B, ADCOMPDB0, ADCOMPDB2
are operating as a buffer registers for ADCOMPD0, ADCOMPD2.
To write this register, use a halfword or word access instruction.
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CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
■ Compare Register 0, 2 (ADCOMP0, ADCOMP2)
Compare register 0, 2 (Upper)
ADCOMP0, ADCOMP2
Address
ch.0: 0000F0H
ch.2: 0000F8H
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
CMP15
CMP14
CMP13
CMP12
CMP11
CMP10
CMP09
CMP08
R
R
R
R
R
R
R
R
Initial value
00000000B
Address ADCOMPD0/ADCOMPD2
ch.0: 0000F2H
ch.2: 0000FAH
Compare register 0, 2 (Lower)
R:
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CMP07
CMP06
CMP05
CMP04
CMP03
CMP02
CMP01
CMP00
R
R
R
R
R
R
R
R
Initial value
00000000B
Read only
The compare register is used to write data for comparison with the 16-bit free-run timer count value. It is
possible to activate A/D when the free-run timer and compare values match.
The value written to the compare register is used for a comparison immediately.
When count direction selection register (ADTGSEL), SEL1, SEL0 = 11B, ADCOMP0, ADCOMP2 and
ADCOMPD0, ADCOMPD2 are doing compare match operation. The former is only during up counting,
the later only during down counting of the free-run timer.
Always use word or half-word access to read the compare register. Do not access this register with the read
modify write (RMW) instructions.
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CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
■ Compare Enable Register (ADTGCE0)
Compare enable register
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CE01
CE00
R/W
R/W
-
-
CE21
CE20
-
-
-
-
R/W
R/W
-
-
CE0[1:0]
-
CM71-10155-2E
Address
ch.0 : 0000FF
B
H
10-bit A/D converter 2 compare activation enable bits
0
0
0
1
Enable compare (free-run timer0 selected)
1
0
Enable compare (free-run timer1 selected)
1
1
Enable compare (free-run timer2 selected)
CE2[1:0]
R/W
ADTGCE0
Initial value : --00--00
Disable compare
10-bit A/D converter 1 compare activation enable bits
0
0
Disable compare
0
1
Enable compare (free-run timer0 selected)
1
0
Enable compare (free-run timer1 selected)
1
1
Enable compare (free-run timer2 selected)
: Readable/Writable
: Initial value
: Undefined bit
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CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
Table 11.4-21 Compare Enable Register (ADTGCE0)
Bit name
Function
• The read value is undefined.
bit7,
bit6
Undefined bits.
bit5,
bit4
CE21, CE20:
• Write "00B" to these bits to disable compare operation.
10-bit A/D converter 1
• Write other than "00B" to these bits to output a activation request for 10-bit A/D
compare activation
converter 1 when there is a free-run timer and a compare value match.
enable bits
bit3,
bit2
Undefined bits
bit1,
bit0
CE01, CE00:
• Write "00B" to these bits to disable compare operation.
10-bit A/D converter 2
• Write other than "00B" to these bits to output a activation request for 10-bit A/D
compare activation
converter 2 when there is a free-run timer and a compare value match.
enable bits
• Writing to these bits has no effect on operation.
• The read value is undefined.
• Writing to these bits has no effect on operation.
Note:
If these registers are set, be sure to check that the free-run timer is stopped.
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CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
■ Count Direction Selection (for Comparison) Register (ADTGSEL0)
Count direction selection register (for Comparison)
bit15
bit13
bit12
bit11
bit10
bit9
bit8
-
bit14
-
SEL21
SEL20
-
-
SEL01
SEL00
-
-
R/W
R/W
-
-
R/W
R/W
SEL0[1:0]
-
CM71-10155-2E
Address
ch.0 : 0000FE
B
H
Count direction selection bits
0
0
Both up / down count
0
1
Up count only
1
0
Down count only
1
1
Up count (ADCOMP0) / Down count (ADCOMPD0)
SEL2[1:0]
R/W
ADTGSEL0
Initial value : --00--00
Count direction selection bits
0
0
0
1
Up count only
1
0
Down count only
1
1
Up count (ADCOMP2) / Down count (ADCOMPD2)
Both up / down count
: Readable/Writable
: Initial value
: Undefined bit
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CHAPTER 11 MULTI-FUNCTION TIMER
11.4 Multi-function Timer Register
MB91490 Series
Table 11.4-22 Count Direction Selection (for Comparison) Register (ADTGSEL0)
Bit name
bit15,
Undefined bits
bit14
Function
• The read value is undefined.
• Writing to these bits has no effect on operation.
• Write "00B" to activate the comparison in up/down count mode of free-run timer.
• Write "01B" to activate the comparison in up count mode of free-run timer.
SEL2:
bit13,
Count
bit12
direction selection bits
• Write "10B" to activate the comparison in down count mode of free-run timer.
• When setting "11B", ADCOMP2 execute compare match only while free-run timer is
up count, and ADCOMPD2 execute compare match only while free-run timer is down
count.
bit11,
Undefined bits
bit10
• The read value is undefined.
• Writing to these bits has no effect on operation.
• Write "00B" to activate the comparison in up/down count mode of free-run timer.
• Write "01B" to activate the comparison in up count mode of free-run timer.
SEL0:
bit9,
Count
bit8
direction selection bits
270
• Write "10B" to activate the comparison in down count mode of free-run timer.
• When setting "11B", ADCOMP0 execute compare match only while free-run timer is
up count, and ADCOMPD0 execute compare match only while free-run timer is down
count.
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11.4 Multi-function Timer Register
MB91490 Series
■ Buffer Control Register (ADTGBUF0)
Buffer control register
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
-
BTS2
-
BTS0
-
BUFX2
-
BUFX0
-
R/W
-
-
R/W
-
R/W
R/W
BUFX0
Valid
1
Invalid
Valid
1
Invalid
Compare register 0 buffer transfer control bit
0
At zero detection
1
At compare clear
BTS2
W
Compare register 2 buffer function control bit
0
BTS0
Address
ch.0: 0000FDH
Compare register 0 buffer function control bit
0
BUFX2
ADTGBUF0
Initial value : -0-0-1-1 B
Compare register 2 buffer transfer control bit
0
At zero detection
1
At compare clear
: Readable/Writable
: Initial value
-
: Undefined bit
Note:
Be sure to stop the free-run timer before rewriting the BTS bit.
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11.4 Multi-function Timer Register
MB91490 Series
Table 11.4-23 Buffer Control Register (ADTGBUF0)
Bit name
Function
• The read value is undefined.
bit7,
bit 5
Undefined bits
bit6,
bit4
• Write "0" to this bit to transfer the compare value to the buffer, at zero
BTS0, BTS2:
detection of free-run timer.
compare register buffer trans• Write "1" to this bit to transfer the compare value to the buffer at compare
fer control bits
match of free-run timer.
bit3,
bit1
Undefined bits
bit2,
bit0
BUFX0, BUFX2:
compare register buffer function control bits
272
• Writing to these bits has no effect on operation.
• The read value is indetermine.
• Writing to these bits has no effect on operation.
• Write "1" to this bit to disable compare buffering.
• Write "0" to this bit to enable compare buffering.
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11.5 Multi-function Timer Interrupt
MB91490 Series
11.5
Multi-function Timer Interrupt
The multi-function timer can generate 16-bit free-run timer interrupts, 16-bit output
compare interrupts, 16-bit input capture interrupts, and waveform generator interrupts.
■ 16-bit Free-run Timer Interrupt
See Table 11.5-1 for 16-bit free-run timer interrupt control bits and interrupt causes.
Table 11.5-1 16-bit Free-run Timer Interrupt Control Bits and Interrupt Causes
16-bit free-run timer
Compare clear
Zero-detect
Interrupt request flag bit
Timer state control register upper (TCCSH) ICLR:
bit9
Timer state control register upper
(TCCSH) IRQZF: bit14
Interrupt request enable bit
Timer state control register upper (TCCSH) ICRE:
bit8
Timer state control register upper
(TCCSH) IRQZE: bit13
Interrupt cause
The 16-bit free-run timer value and compare-clear
register (CPCLRH/CPCLRL) match.
16-bit free-run timer goes to "0"
When the 16-bit free-run timer value and compare-clear register (CPCLRH/CPCLRL) match, the timer
state control register upper (TCCSH) ICLR: bit9 is set to 1. When interrupt requests are enabled in this
state (TCCSH: ICRE bit8=1), the interrupt request is output to the interrupt controller.
When the timer value is" 0000H", the timer state control register upper (TCCSH) IRQZF: bit14 is set to "1".
When interrupt requests are enabled in this state (TCCSH IRQZE:bit13=1), the interrupt request is output
to the interrupt controller.
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11.5 Multi-function Timer Interrupt
MB91490 Series
■ 16-bit Output Compare Interrupt
See Table 11.5-2 for 16-bit output compare interrupt control bits and interrupt causes.
Table 11.5-2 16-bit Output Compare 0 to 5 Interrupt Control Bits and Interrupt Causes
16-bit output compare 0, 1
16-bit output compare 2, 3
16-bit output compare 4, 5
Interrupt request Compare control register Low
Compare control register Low
Compare control register Low
flag bit
(OCSL0) IOP1, IOP0 (bit7, bit6) (OCSL2) IOP1, IOP0 (bit7, bit6) (OCSL4) IOP1, IOP0 (bit7, bit6)
Interrupt request Compare control register Low
Compare control register Low
Compare control register Low
enable bit
(OCSL0) IOE1, IOE0 (bit5, bit4) (OCSL2) IOE1, IOE0 (bit5, bit4) (OCSL4) IOE1, IOE0 (bit5, bit4)
Interrupt cause
The 16-bit free-run timer value
and output compare register
(OCCPH0, OCCPH1, OCCPL0,
OCCPL1) match.
The 16-bit free-run timer value
and output compare register
(OCCPH2, OCCPH3, OCCPL2,
OCCPL3) match.
The 16-bit free-run timer value and
output compare register (OCCPH4,
OCCPH5, OCCPL4, OCCPL5)
match.
When the 16-bit free-run timer value and output compare register (OCCPH0 to OCCPH5, OCCPL0 to
OCCPL5) match, the compare control register low-order (OCSL0, OCSL2, and OCSL4) IOP 1 and IOP 0:
bit7 and bit6 are set to 1. When interrupt requests are enabled in this state (OCSL0, OCSL2, and OCSL4
registers IOE1 and IOE0: bit5/bit4 = 11B), the interrupt request is output to the interrupt controller.
■ 16-bit Input Capture Interrupt
See Table 11.5-3 for 16-bit input capture interrupt control bits and interrupt causes.
Table 11.5-3 16-bit Input Capture 0 to 3 Interrupt Control Bits and Interrupt Causes
16-bit input capture 0, 1
16-bit input capture 2, 3
Interrupt request flag bit
Input capture status control register Low
(PICSL01) ICP1, ICP0 (bit7, bit6)
Input capture status control register Low
(ICSL23) ICP3, ICP2 (bit7, bit6)
Interrupt request enable bit
Input capture status control register Low
(PICSL01) ICE1, ICE0 (bit5, bit4)
Input capture status control register Low
(ICSL23) ICP3, ICP2 (bit5, bit4)
Interrupt cause
Valid edges are detected by IC0 and IC1 pins. Valid edges are detected by IC2 and IC3 pins.
With 16-bit input capture, when a valid edge is detected by IC0 to IC3 pins, the input capture-status control
registers (PICSL01 and ICSL23) ICP3, ICP2, ICP1, and ICP0: bit7 and bit6 are both set to 11B. When
interrupt requests are enabled in this state (PICSL01 and ICSL23 registers ICE3, ICE2, ICE1, ICE0: bit5
and bit4 are both 11B), interrupt requests are output to the interrupt controller.
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11.5 Multi-function Timer Interrupt
MB91490 Series
■ Waveform Generator Interrupts
See Table 11.5-4 for waveform generator interrupt control bits and interrupt causes.
Table 11.5-4 Waveform Generator Interrupt Control Bits and Interrupt Causes
Waveform generator
16-bit dead timer 0 to 2
DTTI0
Interrupt request flag bit
16-bit dead timer control register High, Low (DTCR0 Waveform control register1/2
to DTCR2) TMIF0 to TMIF2 (High is bit12, Low is (SIGCR1/SIGCR2)
bit4)
DTIF (bit6)
Interrupt request enable bit
16-bit dead timer control register High, Low (DTCR0
to DTCR2) TMIE0 to TMIE2 (High is bit11, Low is
bit3)
Interrupt cause
Underflow in 16-bit dead timer 0 to 2
Low level detected in DTTI.
The waveform generator sets TMIF0 to TMIF2 (upper bit12 and lower bit4) in the 16-bit dead timer control
register (DTCR0 to DTCR2) to "1" when an underflow occurs on the 16-bit dead timer and the TMD8 to
TMD0 bits in the DTCR0 to DTCR2 registers (upper bit10 to bit8, lower bit2 to bit0) are set to "000B" or
"001B". When interrupt requests are enabled in this state (DTCR0 to DTCR2 registers TMIE0 to TMIE2
(upper bit is 11, lower bit is 3) = 1), the interrupt request is output to the interrupt controller.
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11.6 Operation of the Multi-function Timer
11.6
MB91490 Series
Operation of the Multi-function Timer
The operation of the multi-function timer is described below.
■ Operation of the Multi-function Timer
● 16-bit free-run timer
When the 16-bit free-run timer enables count operation, the counter begins counting up from the value set in the
timer data register (TCDTH/TCDTL). The count value is used as the standard time of the 16-bit output compare
and 16-bit input capture.
● Free-run timer selector
The free-run timer input can be selected for the 16-bit output compare, 16-bit input capture, A/D activation
compare. The output compare/input capture can be selected by the free-run timer selector and the A/D activation
compare by the compare enable register (ADTGCE).
● 16-bit output compare
16-bit output compare is used to compare the value set in the output compare register with the 16-bit free-run timer
value. If a match is detected, the interrupt flag is set, and the output level is reversed.
● 16-bit input capture
16-bit input capture is used to detect specified valid edges.
When a valid edge is detected, the interrupt flag is set, and the value of the 16-bit free-run timer is retrieved, and
stored in the input capture data register.
● Waveform generator
The waveform generator generates a variety of waveforms (including dead times) using real-time output (RTO0 to
RTO5), the input 16-bit PPG timer, and 16-bit dead timer.
● A/D activation compare
An A/D activation is generated when the selected 16-bit free-run timer reaches the specified value.
The channel of the free-run timer can be selected by the register setting.
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11.6 Operation of the Multi-function Timer
MB91490 Series
11.6.1
Operation of 16-bit Free-run Timer
Three 16-bit free-run timer units are provided and these start up-counting from the
value set in the timer data register (TCDTH/TCDTL) after a reset completes. The count
value is used as the standard time of the 16-bit output compare and 16-bit input
capture.
■ Timer Clear
The count value of the 16-bit free-run timer is cleared when one of the following holds:
• A match with the compare-clear register is detected via up-count mode (TCCSL registers MODE: bit5 =
0)
• "1" is written to bit4 (SCLR) of the TCCSL register during operation
• "0000H" is written to the TCDTH/TCDTL register when operation is halted
• A reset occurs
After a reset, the counter is immediately cleared. The counter is cleared, synchronized with the count
timing, when cleared by software or when a match with the compare clear register occurs
Figure 11.6-1 Clear Timing of 16-bit Free-run Timer

Compare clear
register value
N
Compare match
Count value
N
0000H
Note:
The count value of the 16-bit free-run timer is not cleared even if "1" is written to bit4 (SCLR) of the
TCCSL register while the timer is stopped.
■ Timer Mode
The following modes can be selected for the 16-bit free-run timer.
• Up-count mode (TCCSL registers MODE: bit5 = 0)
• Up/down count mode (TCCSL registers MODE: bit5=1)
In the up-count mode, the counter starts counting from the preset timer data register (TCDTH/TCDTL) and
continues counting up until the count value matches the value in the compare clear register (CPCLRH/
CPCLRL). Then, the counter is cleared to "0000H" and the counter restarts counting up.
In the up/down count mode, the counter starts counting from the preset timer data register (TCDTH/
TCDTL) and continues counting up until the count value matches the value in the compare clear register
(CPCLRH/CPCLRL). Then, counting changes from the up-count mode to the down-count mode, the
counter value performs counting down until it reaches to "0000H", and the counter restarts counting up.
You can write to the mode bit (bit5 (MODE) in the TCCSL register) at any time regardless of whether the
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11.6 Operation of the Multi-function Timer
MB91490 Series
timer is running or halted. The value written to the bit when the timer is running is stored in a buffer and
the actual count mode does not change until the timer value reaches "0000H".
Figure 11.6-2 Change Timer Mode during Timer Operation
Count value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Start timer operation
Change to up-count mode
Change to up/down count mode
Reset
Compare clear
buffer register
BFFFH
TCCSL: MODE
■ Compare Clear Buffer
The compare-clear register (CPCLRH/CPCLRL) has a buffer feature that can be enabled or disabled. When
the buffer function is enabled (bit7 (BFE) = 1 in the TCCSL register), data written to the compare clear
buffer register (CPCLRBH/CPCLRBL) is transferred to the CPCLRH/CPCLRL register when zero is
detected on the 16-bit free-run timer. When the buffer function is disabled (bit7 (BFE) in the TCCSL
register = 0) and data is written directly to the CPCLRH/CPCLRL register.
Figure 11.6-3 Operation in Up-count Mode when Compare Clear Buffer is Disabled
(TCCSL Register’s BFE:bit7 = 0)
Count value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Reset
278
Time
Start timer operation
Compare clear match
Zero detection
Compare clear
buffer register
BFFFH
7FFFH
FFFFH
Compare clear
register
BFFFH
7FFFH
FFFFH
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11.6 Operation of the Multi-function Timer
MB91490 Series
Figure 11.6-4 Operation in Up-count Mode when Compare Clear Buffer is Enabled
(TCCSL Register’s BFE:bit7=1)
Count value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Reset
Compare clear
buffer register
Time
Start timer operation
Compare clear match
Zero detection
7FFFH
BFFFH
Compare clear
register
FFFFH
7FFFH
BFFFH
FFFFH
Figure 11.6-5 Operation in Up/Down Count Mode when Compare Clear Buffer is Enabled
(TCCSL Register’s BFE:bit7 = 1)
Count value
Compare clear match
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Zero detection
Start timer operation
Reset
Compare clear
buffer register
Compare clear
register
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7FFFH
BFFFH
BFFFH
FFFFH
7FFFH
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FFFFH
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11.6 Operation of the Multi-function Timer
MB91490 Series
■ Timer Interrupt
The 16-bit free-run timer can generate the following two interrupts.
• Compare clear interrupt
• Zero-detect interrupt
Compare-clear interrupts are generated when the timer value matches the value of the compare-clear
register.
Zero-detect interrupts are generated when the timer value reaches "0000H".
Note:
A software clear (setting bit4 (SCLR) in the TCCSL register = 1) does not generate a zero-detect
interrupt.
Figure 11.6-6 Interrupt Generated in Up-count Mode (TCCSL Register MODE:bit5 = 0)
N-1
Count value
N
0
1
Compare clear interrupt
Zero-detection interrupt
Figure 11.6-7 Interrupt Generated in Up/Down-count Mode (TCCSL Register MODE:bit5 = 1)
Count value
N-1
N
N-1
0
Compare clear interrupt
Zero-detection interrupt
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11.6 Operation of the Multi-function Timer
MB91490 Series
■ Interrupt Mask Function
It is possible to mask either one of zero detection interrupt or compare match interrupt or both.
The following describes how to mask either one of interrupt.
- It is possible to mask interrupt requests by setting the TCCSH registers MSI2 - MSI0 : bit12-bit10.
MSI2 bit - MSI0 bit are a 3-bit reload down register that reload when the count value reaches "000B".
The count value can also be loaded by writing directly to the MSI2 to MSI0 bits. The mask count is
the value set in MSI2 bit - MSI0 bit. When MSI2 bit - MSI0 bit are "000B", interrupt request are not
masked.
- The interrupt request depends on the count mode (TCCSL registers MODE : bit5). In up-count mode,
it is only possible to mask compare-clear interrupts, and zero-detect interrupts are generated each
time "0" is detected. In up/down count mode, it is only possible to mask zero-detect interrupts.
The following explains how to mask both interrupt requests.
- Both interrupt can be masked when the free-run timer is only in up/down count mode and in MODE2
in the TCCSM register =1 and MODE in the TCCSL register = 1.
- MSI2 to MSI0 bits in the TCCSH register is used for zero detect interrupt mask and MSI5 to MSI3
bits in the TCCSM register is used for compare clear interrupt mask.
Note:
A software clear (setting bit4 (SCLR) in the TCCSL register = 1) does not generate a 0-detect
interrupt.
Figure 11.6-8 Compare Clear Interrupt Masked in Up-count Mode
Count value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
MODE2=0,
MODE=0
Reset
Time
Start timer operation 1st
Zero-detection
interrupt
2nd
3rd
4th
Software clear
TCCSH : MSI2 to MSI0=000B
Compare clear TCCSH : MSI2 to MSI0=001B
interrupt
TCCSH : MSI2 to MSI0=010B
Note: Both zero
Note
ero detection interrupt
inter upt and compare clear interrupt
inter upt are cleared by
y the softwar
soft are.
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11.6 Operation of the Multi-function Timer
MB91490 Series
Figure 11.6-9 Zero Detection Interrupt Masked in Up/Down Count Mode
Count value
FFFFH
1st
2nd
3rd
4th
5th
6th
BFFFH
7FFFH
3FFFH
0000H
MODE2=0,
MODE=1
Reset
Time
Start timer operation 1st
Compare clear
interrupt
3rd
2nd
4th
5th
6th
Software clear
TCCSH : MSI2 to MSI0=000B
Zero-detection TCCSH : MSI2 to MSI0=001B
interrupt
TCCSH : MSI2 to MSI0=010B
Note: Both zero
Note
ero detection interrupt
inter upt and compare clear interrupt
inter upt are cleared by
y the softwar
soft are.
Figure 11.6-10 Both Zero Detection interrupt and Compare Clear Interrupt Masked in Up/Down Count Mode
Count value
FFFFH
1st
2nd
3rd
4th
5th
6th
BFFFH
7FFFH
3FFFH
0000H
MODE2=1,
MODE=1
Reset
Time
Start timer operation 1st
Compare clear
interrupt
2nd
3rd
4th
5th
6th
Software clear
TCCSM : MSI5 to MSI3=000B
TCCSM : MSI5 to MSI3=001B
TCCSM : MSI5 to MSI3=010B
Zero-detection
interrupt
TCCSH : MSI2 to MSI0=000B
TCCSH : MSI2 to MSI0=001B
TCCSH : MSI2 to MSI0=010B
Note: Both zero
Note
ero detection interrupt
inter upt and compare clear interrupt
inter upt are cleared by
y the softwar
soft are.
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11.6 Operation of the Multi-function Timer
MB91490 Series
■ Selected External Count Clock
The 16-bit free-run timer is incremented based on the input clock (peripheral clock (CLKP) or external
clock). When the external clock is selected in external clock mode (bit15 (ECKE) in the TCCSH register =
1), the 16-bit free-run timer starts counting up on rising edges if the initial value of the external input is "1".
Subsequently, it counts up on both edges. If the initial value of external input is "0", it starts counting up on
a falling edge. Subsequently, it counts up on both edges.
Figure 11.6-11 Count Timing of 16-bit Free-run Timer
External clock input
TCCSH: ECKE bit
Count clock
Count value
N
N+1
N+2
Note:
The external clock input is counted on both edges.
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11.6 Operation of the Multi-function Timer
MB91490 Series
■ A/D Activation by Free-run Timer
It is possible to activate A/D upon a compare match or zero detection of the 16-bit free-run timer. The
activation trigger can be selected by means of the A/D trigger cause selection bits (SEL0, SEL2: bit4, bit6)
of the A/D trigger control register (ADTRGC).
It is possible to halt A/D activation signals, even upon compare match or zero-detection, via the A/D trigger
output enable/disable bits (AD0E, AD2E: bit0, bit2) of the A/D trigger control register (ADTRGC).
Note:
If A/D activation signal output is enabled from disabled state, and in the meantime, an activation
trigger compare match or 0-detection is arrived, the A/D activation signal will be asserted
immediately after the A/D activation signal output was enabled.
● Activate A/D when zero is detected (ADTRGC: SELn = 0 (n=0, 2))
Free-run timer
Count value
Compare
clear value
Free-run timer
Count value
Compare
clear value
Up-count mode
Up/down-count mode
Time
A/D startup A/D startup
Time
A/D startup
A/D startup
A/D startup
● Activate A/D when a compare clear match occurs (ADTRGC: SELn = 1 (n=0, 2))
Free-run timer
Count value
Compare
clear value
Free-run timer
Count value
Compare
clear value
Up-count mode
Up/down-count mode
Time
A/D startup A/D startup
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A/D startup
Time
A/D startup
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11.6 Operation of the Multi-function Timer
MB91490 Series
11.6.2
Operation of Free-run Timer Selector
Free-run timer selector is used to select the input free-run timers to output compare and
input capture unit.
Multi-function timer contains 3 free-run timers, 6 output compare, 4 input capture.
The mapping information is shown in Table 12.6-1 and Table 12.6-2.
Table 11.6-1 Registers for Mapping Free-run Timers
Resource
Register
OCU0
FRS0[2:0]
OCU1
FRS0[6:4]
OCU2
FRS1[10:8]
OCU3
FRS1[14:12]
OCU4
FRS2[2:0]
OCU5
FRS2[6:4]
ICU0
FRS3[2:0]
ICU1
FRS3[6:4]
ICU2
FRS4[10:8]
ICU3
FRS4[14:12]
Table 11.6-2 Set Value List
Set value
Free-run timer
000B
free-run timer0 (Default status of multifunction timer0)
001B
free-run timer1
010B
free-run timer2
Others
Prohibited (Operation not guarantee)
Note:
Before setting the free-run timer selection register, be sure to stop the 16-bit free-run timer.
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11.6 Operation of the Multi-function Timer
11.6.3
MB91490 Series
Operation of 16-bit Output Compare
Output compare is used to compare the value set in the compare clear register with the
16-bit free-run timer value. If a match is detected, the interrupt flag is set, and the output
level is reversed.
If the free-run timer is in up/down count mode, match signals are ignored when the
count peak and compare register value match.
■ 16-bit Output Compare Operation (Inversion Mode, MOD1x = 0)
● Compare operation can be performed on each channel (compare control register higher-orders
(OCSH1, OCSH3, and OCSH5) CMOD: bit12 = 0)
Figure 11.6-12 Example of Output Waveform when the Initial Output is "0" and Compare Register 0 and
Compare Register 1 are Used Separately (Free-run Timer in Up-count Mode)
Count value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Reset
Compare register 0
BFFFH
Compare register 1
7FFFH
RT0
RT1
Compare 0 interrupt
Compare 1 interrupt
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11.6 Operation of the Multi-function Timer
MB91490 Series
Figure 11.6-13 Example of Output Waveform when the Initial Output is "0" and Compare Register 0 and
Compare Register 1 are Used Separately (Free-run Timer in Up/Down Count Mode)
Count value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Reset
Compare register 0
BFFFH
Compare register 1
7FFFH
RT0
RT1
Compare 0 interrupt
Compare 1 interrupt
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11.6 Operation of the Multi-function Timer
MB91490 Series
● The output level can be changed using a single compare register (compare control register higherorders (OCSH1, OCSH3 and OCSH5) CMOD: bit12 = 1)
Figure 11.6-14 Example of Output Waveform when the Initial Output is "0" and Compare Register 0 and
Compare Register 1 are Used Together (Free-run Timer in Up-count Mode)
Count value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Reset
Compare register 0
BFFFH
Compare register 1
7FFFH
Correspond to compare 0
RT0
Correspond to compare 0 and 1
RT1
Compare 0 interrupt
Compare 1 interrupt
Figure 11.6-15 Example of Output Waveform when the Initial Output is "0" and Compare Register 0 and
Compare Register 1 are Used Together (Free-run Timer in Up/Down Count Mode)
Count value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Reset
Compare register 0
BFFFH
Compare register 1
7FFFH
RT0
Correspond to compare 0
RT1
Correspond to compare 0 and 1
Compare 0 interrupt
Compare 1 interrupt
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11.6 Operation of the Multi-function Timer
MB91490 Series
● Output level when compare buffer is disabled
Figure 11.6-16 Example of Output Waveform when the Compare Buffer is Disabled
(Free-run Timer in Up-count Mode)
Count value
FFFFH
BFFFH
7FFFH
3FFFH
Time
0000H
Start timer operation
Compare clear match
Reset
Compare clear
match
Compare clear
buffer register 0
BFFFH
3FFFH
BFFFH
Compare clear
register 0
BFFFH
3FFFH
BFFFH
RT0
Interrupt
● Output level when compare buffer is selected, and a compare clear match occurs:
Figure 11.6-17 Example of Output Waveform when the Compare Buffer is Valid
(Free-run Timer in Up/Down Count Mode)
Count value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Start timer operation
Compare clear match
Zero-detection
Reset
Compare buffer
register 0
Compare
register 0
BFFFH
3FFFH
BFFFH
BFFFH
3FFFH
BFFFH
RT0
Interrupt
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11.6 Operation of the Multi-function Timer
MB91490 Series
■ 16-bit Output Compare Operation (Set/Reset Mode, MOD1x = 1)
Count value
FFFFH
BFFFH
7FFFH
3FFFH
Time
0000H
Reset
Compare register 0
BFFFH
Compare register 2
7FFFH
RT0
RT2
Compare 0 interrupt
Compare 2 interrupt
Up count of ch.0 is set, down count of ch.0 is reset
Up count of ch.2 is reset, down count of ch.2 is set
Note: Keeps "1" if ch.0 compare clear match occurs. ch.2 is always "0".
Count value
FFFFH
BFFFH
7FFFH
3FFFH
Time
0000H
Reset
Compare register 0
BFFFH
Compare register 2
7FFFH
RT0
RT2
Compare 0 interrupt
Compare 2 interrupt
Up count of ch.0 is set, down count of ch.0 is reset
Up count of ch.2 is reset, down count of ch.2 is set
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11.6 Operation of the Multi-function Timer
MB91490 Series
■ 16-bit Output Compare Timing
When a match occurs between the free-run timer and compare register, the output compare generates the
compare match signal to reverse the output and generates an interrupt. When a compare match occurs,
output is reversed in synchronization with the count timing of the counter.
Figure 11.6-18 Compare Register Interrupt Timing
Peripheral clock (CLKP)
N+1
N
Count value
N
Compare register
Compare match
Interrupt
Figure 11.6-19 Pin Output Change Timing
Peripheral clock (CLKP)
Count value
Compare register
N
N
N+1
N+1
N
Compare match
Pin output
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11.6 Operation of the Multi-function Timer
MB91490 Series
■ Operation of 16-bit Output Compare and Free-run Timer
● When the free-run timer up-counts
The data transfer timing for the compare buffer of the output compare is when a compare clear match occurs
with the free-run timer.
Free-run timer
count value
CFFFH
BFFFH
0000H
Time
Compare buffer
register
Compare register
BFFFH
BFFFH
CFFFH
BFFFH
CFFFH
0000H
BFFFH
BFFFH
0000H
0000H
BFFFH
CFFFH
0000H
0000H
CFFFH
0000H
RT
● When the free-run timer up-counts
The data transfer timing for the compare buffer of the output compare is when zero is detected in the free-run
timer.
Free-run timer
count value
CFFFH
BFFFH
0000H
Time
Compare buffer
register
Compare register
BFFFH
BFFFH
CFFFH
BFFFH
CFFFH
0000H
BFFFH
BFFFH
0000H
0000H
BFFFH
CFFFH
0000H
0000H
CFFFH
0000H
RT
1peripheral clock (CLKP) "0" output
The data transfer timing for the compare buffer of the output compare is
when zero is detected in the free-run timer.
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11.6 Operation of the Multi-function Timer
MB91490 Series
● When the free-run timer up/down counts
• The data transfer timing for the compare buffer of the output compare is when a compare clear match
occurs with the free-run timer.
• When the output compare output mode is set to reverse the output when a match occurs
Notes:
• RT is set to "1" when the compare register is set to "0000H" regardless of the free-run timer count
value (reset to "0" when CMOD = 1).
• RT is reset to "0" when the compare register is set to "FFFFH", regardless of the free-run timer
count value (set to "1" when CMOD = 1).
• No comparison is performed when the value of the compare clear register in the free-run timer is
the same as the compare register in the output compare. In this case, RT is reset to "0" when
both the compare clear register and compare register are set to "FFFFH", regardless of the freerun timer count value.
For CMOD=0
Free-run timer
count value
CFFFH
BFFFH
0000H
Time
Compare buffer
register
BFFFH
Compare register
BFFFH
CFFFH
BFFFH
BFFFH
0000H
CFFFH
BFFFH
FFFFH
0000H
0000H
FFFFH
RT initial value [0]
RT initial value [1]
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11.6 Operation of the Multi-function Timer
MB91490 Series
● When the free-run timer up/down counts
• The data transfer timing for the compare buffer of the output compare is when zero is detected in the
free-run timer.
• When the output compare output mode is set to reverse the output when a match occurs
Notes:
• RT is set to "1" when the compare register is set to "0000H" regardless of the free-run timer count
value (reset to "0" when CMOD = 1).
• RT is reset to "0" when the compare register is set to "FFFFH", regardless of the free-run timer
count value (set to "1" when CMOD = 1).
• No comparison is performed when the value of the compare clear register in the free-run timer is
the same as the compare register in the output compare. In this case, RT is reset to "0" when
both the compare clear register and compare register are set to "FFFFH", regardless of the freerun timer count value.
Free-run timer
count value
For CMOD=0
CFFFH
BFFFH
0000H
Time
Compare buffer
register
BFFFH
Compare register
BFFFH
CFFFH
BFFFH
CFFFH
0000H
BFFFH
FFFFH
0000H
0000H
FFFFH
0000H
RT initial value [0]
RT initial value [1]
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11.6 Operation of the Multi-function Timer
MB91490 Series
● When the free-run timer up/down counts
• The data transfer timing for the compare buffer of the output compare is when a compare clear match
occurs with the free-run timer.
• The output compare output is set to "1" for a match due to an up-count and reset to "0" for a match due
to a down-count (CMOD=0).
Notes:
• RT is set to "1" when the compare register is set to "0000H" regardless of the free-run timer count
value. When the compare register is changed from "0000H" to any value between "0001H" and
"FFFEH", RT maintains the value "1".
• RT is reset to "0" when the compare register is set to "FFFFH", regardless of the free-run timer
count value. When the compare register is changed from "FFFFH" to any value between "0001H"
and "FFFEH", RT is set to "1".
• No comparison is performed when the value of the compare clear register in the free-run timer is
the same as the compare register in the output compare. In this case, RT is reset to "0" when
both the compare clear register and compare register are set to "FFFFH", regardless of the freerun timer count value.
Free-run timer
count value
CFFFH
BFFFH
0000H
Time
Compare buffer
register
BFFFH
Compare register
BFFFH
CFFFH
BFFFH
BFFFH
CFFFH
0000H
BFFFH
FFFFH
0000H
0000H
FFFFH
RT initial value [0]
RT initial value [1]
Free-run timer
count value
CFFFH
BFFFH
0000H
Time
Compare buffer
register
BFFFH
Compare register
BFFFH
0000H
BFFFH
FFFFH
BFFFH
0000H
BFFFH
FFFFH
BFFFH
RT initial value [0]
RT initial value [1]
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11.6 Operation of the Multi-function Timer
MB91490 Series
● When the free-run timer up/down counts
• The data transfer timing for the compare buffer of the output compare is when zero is detected in the
free-run timer.
• The output compare output is set to "1" for a match due to an up-count and reset to "0" for a match due
to a down-count (CMOD=0).
Notes:
• RT is set to "1" when the compare register is set to "0000H" regardless of the free-run timer count
value. When the compare register is changed from "0000H" to any value between "0001H" and
"FFFEH", RT is set to "0".
• RT is reset to "0" when the compare register is set to "FFFFH", regardless of the free-run timer
count value. When the compare register is changed from "FFFFH" to any value between "0001H"
and "FFFEH", RT maintains the value "0".
• No comparison is performed when the value of the compare clear register in the free-run timer is
the same as the compare register in the output compare. In this case, RT is reset to "0" when
both the compare clear register and compare register are set to "FFFFH", regardless of the freerun timer count value.
Free-run timer
count value
CFFFH
BFFFH
0000H
Time
Compare buffer
register
Compare register
BFFFH
CFFFH
BFFFH
BFFFH
CFFFH
0000H
BFFFH
FFFFH
0000H
FFFFH
0000H
0000H
RT initial value [0]
RT initial value [1]
Free-run timer
count value
CFFFH
BFFFH
0000H
Time
Compare buffer
register
BFFFH
Compare register
BFFFH
0000H
BFFFH
0000H
FFFFH
BFFFH
BFFFH
FFFFH
BFFFH
RT initial value [0]
RT initial value [1]
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11.6 Operation of the Multi-function Timer
MB91490 Series
● When the free-run timer up/down counts
• The data transfer timing for the compare buffer of the output compare is when a compare clear match
occurs with the free-run timer.
• Output compare output when up-count match is reset to 0, and down-count match is set to "1"
(CMOD=1):
Notes:
• RT is reset to "0" when the compare register is set to "0000H", regardless of the free-run timer
count value. When the compare register is changed from "0000H" to any value between "0001H"
and "FFFEH", RT maintains the value "0".
• RT is set to "1" when the compare register is set to "FFFFH" regardless of the free-run timer count
value. When the compare register is changed from "FFFFH" to any value between "0001H" and
"FFFEH", RT is set to "0".
• No comparison is performed when the value of the compare clear register in the free-run timer is
the same as the compare register in the output compare. In this case, RT is reset to "0" when
both the compare clear register and compare register are set to "FFFFH", regardless of the freerun timer count value.
Free-run timer
count value
CFFFH
BFFFH
0000H
Time
Compare buffer
register
Compare register
BFFFH
BFFFH
CFFFH
BFFFH
BFFFH
CFFFH
0000H
BFFFH
FFFFH
0000H
0000H
FFFFH
RT initial value [0]
RT initial value [1]
Free-run timer
count value
CFFFH
BFFFH
0000H
Time
Compare buffer
register
BFFFH
Compare register
BFFFH
0000H
BFFFH
FFFFH
BFFFH
0000H
BFFFH
FFFFH
BFFFH
RT initial value [0]
RT initial value [1]
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11.6 Operation of the Multi-function Timer
MB91490 Series
● When the free-run timer up/down counts
• The data transfer timing for the compare buffer of the output compare is when zero is detected in the
free-run timer.
• Output compare output when up-count match is reset to "0", and down-count match is set to "1"
(CMOD=1):
Notes:
• RT is reset to "0" when the compare register is set to "0000H", regardless of the free-run timer
count value. When the compare register is changed from "0000H" to any value between "0001H"
and "FFFEH", RT is set to "1".
• RT is set to "1" when the compare register is set to "FFFFH" regardless of the free-run timer count
value. When the compare register is changed from "FFFFH" to any value between "0001H" and
"FFFEH", RT maintains the value "1".
• No comparison is performed when the value of the compare clear register in the free-run timer is
the same as the compare register in the output compare. In this case, RT is reset to "0" when
both the compare clear register and compare register are set to "FFFFH", regardless of the freerun timer count value.
Free-run timer
count value
CFFFH
BFFFH
0000H
Time
Compare buffer
register
BFFFH
Compare register
CFFFH
BFFFH
BFFFH
CFFFH
0000H
BFFFH
FFFFH
0000H
0000H
FFFFH
0000H
RT initial value [0]
RT initial value [1]
Free-run timer
count value
CFFFH
BFFFH
0000H
Time
Compare buffer
register
BFFFH
Compare register
BFFFH
0000H
BFFFH
0000H
FFFFH
BFFFH
BFFFH
FFFFH
BFFFH
RT initial value [0]
RT initial value [1]
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11.6 Operation of the Multi-function Timer
MB91490 Series
11.6.4
16-bit Input Capture Operation
Input capture is used to detect specified valid edges. When a valid edge is detected, the
interrupt flag is set, and the value of the 16-bit free-run timer is loaded into the capture
register.
■ 16-bit Input Capture Operation
Figure 11.6-20 Example of Input Capture Timing
Count value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Reset
IC0
IC1
IC2
Capture
register0
Capture
register1
Capture
register2
3FFFH
Undefined
7FFFH
Undefined
BFFFH
Undefined
3FFFH
Capture 0
interrupt
Capture 1
interrupt
Capture 2
interrupt
Generate interrupt by valid edge again
Clear interrupt by software
Capture 0 : Rising edge
Capture 1 : Falling edge
Capture 2 : both edges
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11.6 Operation of the Multi-function Timer
MB91490 Series
■ Input Timing for 16-bit Input Capture
Figure 11.6-21 Example for Timing of 16-bit Input Capture for Input Signal
Peripheral clock
(CLKP) φ
Count value
Input capture input
N
N+1
Valid edge
Capture signal
Capture register
N+1
Interrupt
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11.6 Operation of the Multi-function Timer
MB91490 Series
11.6.5
Waveform Generator Operation
The waveform generator can generate a variety of waveforms (including dead times)
using real-time output (RTO0 to RTO5), the 16-bit PPG timer 0/2/4, and 16-bit dead
timers 0, 1, and 2.
■ Output Status of RTO0 to RTO5 and GATE
Table 11.6-3 RTO0 to RTO5/GATE Output Status and Bit Settings (1 / 2)
TMD2 TMD1 TMD0 GTENx PGENx
0
0
0
X
X
0
0
1
X
0
0
0
1
0
0
0
1
1
0
1
1
0
0
X
Always "0"
Real-time output RTx (16-bit output compare output)
(RTx and
GTENx) *3
1
RTx outputs a PPG0/PPG2/PPG4 pulse for duration H. *1
Always "0"
1
RTx outputs the PPG0/PPG2/PPG4 pulse activated by the GATE
signal for duration H.
(RT0|RT1|
RT2|RT3|
RT4|RT5)
16-bit dead timer 0 starts on a rising edge on RT0 or RT1 and "H"
is output until the 16-bit dead timer 0 underflows.
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0
"H" is output
16-bit dead timer 1 starts on a rising edge on RT2 or RT3 and "H" during timer
is output until the 16-bit dead timer 1 underflows.
operation
X
16-bit dead timer 2 starts on a rising edge on RT4 or RT5 and "H"
is output until the 16-bit dead timer 2 underflows.
0
16-bit dead timer 0 starts on a rising edge on RT0 or RT1 and the
PPG0/PPG2/PPG4 pulse is output until the 16-bit dead timer 0
underflows.*1
0
16-bit dead timer 1 starts on a rising edge on RT2 or RT3 and the
PPG0/PPG2/PPG4 pulse is output until the 16-bit dead timer 1
underflows. *1
0
GATE
Real-time output RTx (16-bit output compare output)
X
0
RTOx
1
*4
Always "0"
16-bit dead timer 2 starts on a rising edge on RT4 or RT5 and the
PPG0/PPG2/PPG4 pulse is output until the 16-bit dead timer 2
underflows. *1
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MB91490 Series
Table 11.6-3 RTO0 to RTO5/GATE Output Status and Bit Settings (2 / 2)
TMD2 TMD1 TMD0 GTENx PGENx
1
1
0
0
0
1
GATE
16-bit dead timer 0 starts on a rising edge on RT0 or RT1 and the
PPG0/PPG2/PPG4 pulse activated by the GATE signal is output
until the 16-bit dead timer 0 underflows.
1
0
RTOx
1
16-bit dead timer 1 starts on a rising edge on RT2 or RT3 and the
PPG0/PPG2/PPG4 pulse activated by the GATE signal is output
until the 16-bit dead timer 1 underflows.
1
16-bit dead timer 2 starts on a rising edge on RT4 or RT5 and the
PPG0/PPG2/PPG4 pulse activated by the GATE signal is output
until the 16-bit dead timer 2 underflows.
X
RT1 generates a non-overlapping signal. *2
X
X
RT3 generates a non-overlapping signal. *2
"H" is output
during timer
operation*4
Always "0"
RT5 generates a non-overlapping signal. *2
X
1
1
1
0
X
Setting disabled
-
1
1
1
1
X
Setting disabled
-
The others
Always "0"
Always "0"
*1: PPG needs to select the channel used from PPG0/PPG2/PPG4, and to be started beforehand.
*2: In order to generate a non-overlapping signal, first select 2-channel mode (compare control registers higher-order
(OCSH1, OCSH3, and OCSH5) CMOD: bit12 = 1 for RT1, RT3, and RT5.
*3: The GATE signal is generated from the RTx whose GTENx bit is set to "1".
*4: The GATE signal is generated while the timer activated by the RTx whose GTENx bit is set to "1" is operating. If more
than one GATEx bit is set to "1", the GATE signal is the OR of the signals of each of the operating timers.
Note:
RTO0 and RTO1 are controlled by the 16-bit dead timer control register higher-order (DTCR0) TMD2
to TMD0: bit10 to bit8, RTO2 and RTO3 are controlled by the lower-order of the DTCR1 register
TMD5 to TMD3: bit2 to bit0, and RTO4 and RT5 are controlled by the higher-order of the DTCR2
register TMD8 to TMD6: bit10 to bit8.
■ PPG Output Control
PPG output to RTO0 pin to RTO5 pin can be enabled by means of the PPG output control/input capturestatus control registers higher-order (PICSH01) PGEN5 to PGEN0: bit15 to bit10.
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11.6 Operation of the Multi-function Timer
MB91490 Series
■ PPG Output by Gate Trigger
The waveform generator can generate a GATE signal via real-time output RTO0 to RTO5, and the 16-bit
dead timer 0, 1, and 2 can operate the PPG count as a trigger. Two real-time outputs (RTO0/RTO2/RTO4
and RTO1/RTO3/RTO5) are controlled by one 16-bit dead timer 0, 1, and 2, generating six separate gate
signals. Six gate signals are used logical sum and the GATE signal is generated, causing trigger of the PPG
count. Also, if PGEN 0 to PGEN 5 signals are used, it is possible to output 6 different waveforms to RTO0
pin to RTO5 pin using PPG alone.
[Waveform generator 0]
PPG0
PPG2
RTO0/RTO1
Selector
PPG4
RTO2/RTO3
RTO4/RTO5
● GATE signal generation when GATEx is active and each RTx is at the "H" level (TMD8 to TMD0 (upper
bit10 to bit8, lower bit2 to bit0) in the 16-bit dead timer control registers (DTCR0, DTCR1, DTCR2) are
"001B" or "111B")
Figure 11.6-22 GATE Signal Generation when RTx is "H"
16-bit free-run timer
Count value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Compare
register 0
BFFFH
Compare
register 1
7FFFH
RT0
RT1
GATE0
GATE1
GATE
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11.6 Operation of the Multi-function Timer
MB91490 Series
● GATE signal generation from rising edge on RTx until underflow on 16-bit dead timer 0, 1, 2 when
GTENx is active (TMD8 to TMD0 in the DTCR0, DTCR1, DTCR2 registers = 010B)
Figure 11.6-23 GATE Signal Generation from Rising Edge on RTx until Underflow Occurs
on 16-bit Dead Timer
16-bit free-run timer
Count value
FFFFH
BFFFH
7FFFH
3FFFH
Time
0000H
Compare
register 0
BFFFH
Compare
register 1
7FFFH
RT0
RT1
GATE0
GATE1
Time of 16-bit dead timer 0
Time of 16-bit dead timer 0
GATE
Note:
Each 16-bit dead timer is used for two RTs. In other words, 16-bit dead timer 0 is used for RT0 and
RT1; 16-bit dead timer 1 is used for RT2 and RT3; and 16-bit dead timer 2 is used for RT4 and RT5.
Consequently, you must not try to use a RT to activate a timer that is already operating. Attempting
to do this will extend the GATE signal and therefore result in misoperation.
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11.6 Operation of the Multi-function Timer
MB91490 Series
11.6.5.1
Operation of Timer Mode
When an RT0 to RT5 pins rising edge is detected, the value is reloaded into the 16-bit
dead timer, and the 16-bit dead timer starts counting down. PPG timer continues to
output to the RTO0 to RTO5 pins until an underflow occurs on the 16-bit dead timer.
■ Operation of Timer Mode
● Generation of PPG output pulse from a rising edge on RT until an underflow on the 16-bit dead timer
(TMD8 to TMD0 (upper bit10 to bit8, lower bit2 to bit0) in the DTCR0, DTCR1, DTCR2 registers are
"010B")
Figure 11.6-24 Waveform Generated when TMD2 to TMD0 (Upper bit10 to bit8, Lower bit2 to bit0) = 010B
<Register setting>
TCDTH, TCDTL
:
TCCSH, TCCSL
:
CPCLRH, CPCLRL
:
OCCPH0 to OCCPH5, OCCPL0 to OCCPL5 :
OCSH0 to OCSH5, OCSL0 to OCSL5
:
DTCR0 to DTCR2
:
TMRRH0 to TMRRH2, TMRRL0 to TMRRL2 :
SIGCR1
:
Note: Be sure to set according to "X" operation.
PCSR : XXXXH
XXXXH
XXXXXXXX X0X0XXXXB
PDUT : XXXXH
XXXXH (Setting of cycle)
PCNT : XXXXH
XXXXH (Compare value)
PICS01 : XXH (PPG0 output selection)
-XX0XXXX XXXXXX11B
011XX010B
XXXXH (Setting of non-overlap timing)
XXXXXX00B (Setting of DTTI input and 16-bit dead timer count clock)
16-bit free-run timer
Count value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
PPG
Compare
register 0
BFFFH
Compare
register 1
7FFFH
RT0
RT1
GATE
RTO0
RTO1
Time of 16-bit dead timer 0
Time of 16-bit dead timer 0
Note:
Each 16-bit dead timer is used for two RTs. In other words, 16-bit dead timer 0 is used for RT 0 and
RT1; 16-bit dead timer 1 is used for RT2 and RT3; and 16-bit dead timer 2 is used for RT4 and RT5.
Consequently, you must not try to use a RT to activate a PPG that is already operating. Attempting
to do this will extend the GATE signal and therefore result in misoperation.
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11.6 Operation of the Multi-function Timer
11.6.5.2
MB91490 Series
Operation during Dead Time Timer Mode
The dead-time generator inputs real-time output (RT1, RT3, and RT5) and outputs a nonoverlapping signal (reverse signal) to the external pins (RTO0 to RTO5).
■ Operation During Dead Time Timer Mode
● This non-overlapping signal is generated via normal-polarity RT 1, RT 3, and RT 5 (16-bit dead timer
control registers (DTCR0, DTCR1, and DTCR2)TMD8 to TMD0 (higher-order bits are 10 to 8; lowerorder bits are 2 to 0) =100B)
When the DTCR 0, DTCR 1, and DTCR 2 registers DMOD2 to DMOD0 select the non-overlapping signal
with a value of 0 (normal polarity), a delay equivalent to the non-overlap time set in the 16-bit dead timer
registers (TMRRH0 to TMRRH2, TMRRL0 to TMRRL2) is applied. This delay is generated on the rising
edge and falling edge of the RT1, RT3, RT5 pins.
Figure 11.6-25 Non-overlapping Signal Generation Using Normal Polarity RT1, RT3, and RT5
<Register setting>
TCDTH, TCDTL
: XXXXH
OCCPH, OCCPL0 to 5 : XXXXH (Compare value)
TCCSH, TCCSL
: XXXXXXXX X0X0XXXXB
OCSH, OCSL0 to 5
: -XX1XXXX XXXXXX11B
CPCLRH, CPCLRL
: XXXXH (Setting of cycle)
DTCR0 to DTCR2
: 0XXXX100B
TMRRH0 to TMRRH2, TMRRL0 to TMRRL2 : XXXXH (Setting of non-overlap timing)
SIGCR1
: XXXXXXXXB (Setting of DTTI input and 16-bit dead timer count clock)
Note: Be sure to set according to "X" operation.
16-bit dead timer 0
Count value
TMRRH0/
TMRRL0
set value
Time
RT1
RTO0(U)
2 peripheral clock
(CLKP) cycles
RTO1(X)
2 peripheral clock
(CLKP) cycles
2 peripheral clock
(CLKP) cycles
2 peripheral clock (CLKP) cycles
Pin name
RTO0 (U)
RTO2 (V)
Delayed signal is applied at rising edge of RT3.
RTO4 (W)
Delayed signal is applied at rising edge of RT5.
RTO1 (X)
306
Output signal
Delayed signal is applied at rising edge of RT1.
Delayed inverted signal is applied at falling edge of RT1.
RTO3 (Y)
Delayed inverted signal is applied at falling edge of RT3.
RTO5 (Z)
Delayed inverted signal is applied at falling edge of RT5.
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11.6 Operation of the Multi-function Timer
MB91490 Series
● This non-overlapping signal is generated via reverse-polarity RT1, RT3, and RT5 (16-bit dead timer
control registers (DTCR0, DTCR1, and DTCR2) TMD8 to TMD0 (higher-order bits are 10 to 8; lowerorder bits are 2 to 0) = 100B)
When the DTCR0, DTCR1, and DTCR2 registers DMOD2 to DMOD0 (higher-order bit is 15, lower-order
bit is 7) select the non-overlapping signal with a value of 1 (reverse polarity), a delay equivalent to the nonoverlap time set in the 16-bit dead timer registers (TMRRH0 to TMRRH2, TMRRL0 to TMRRL2) is
applied. This delay is generated on the rising edge and falling edge of the RT1, RT3, RT5 pins.
Figure 11.6-26 Non-overlapping Signal Generation Using Inverted Polarity RT1, RT3, and RT5
<Register setting>
OCCPH0 to OCCPH5, OCCPL0 to OCCPL5 : XXXXH (Compare value)
TCDTH, TCDTL
: XXXXH
TCCSH, TCCSL
: XXXXXXXX X0X0XXXXB
OCSH0 to OCSH5, OCSL0 to OCSL5
: -XX1XXXX XXXXXX11B
CPCLRH, CPCLRL
: XXXXH (Setting of cycle)
DTCR0 to DTCR2
: 1XXXX100B
TMRRH0 to TMRRH2, TMRRL0 to TMRRL2 : XXXXH (Setting of non-overlap timing)
SIGCR1
: XXXXXXXXB (Setting of DTTI input and 16-bit dead timer count clock)
Note: Be sure to set according to "X" operation.
16-bit dead timer 0
Count value
TMRRH0/
TMRRL0
set value
Time
RT1
2 peripheral clock
(CLKP) cycles
RTO0(U)
2 peripheral clock
(CLKP) cycles
RTO1(X)
2 peripheral clock (CLKP) cycles
Pin name
2 peripheral clock
(CLKP) cycles
Output signal
RTO0 (U)
Delayed inverted signal is applied at rising edge of RT1.
RTO2 (V)
Delayed inverted signal is applied at rising edge of RT3.
RTO4 (W)
Delayed inverted signal is applied at rising edge of RT5.
RTO1 (X)
Delayed signal is applied at falling edge of RT1.
RTO3 (Y)
Delayed signal is applied at falling edge of RT3.
RTO5 (Z)
Delayed signal is applied at falling edge of RT5.
■ Notes on using the dead time timer mode
When the pulse width of RT1, RT3 or RT5 is smaller than the current setting of the non-overlap time, 16bit dead timer reloads the value of TMRRH0 to TMRRH2 and TMRRL0 to TMRRL2 at the next RT edge,
then restarts counting down.
If the compare output transition time is small and reloading is repeated before the dead timer underflow
occurs, X and U are fixed to "L" in Normal mode, and X and U are fixed to "H" in Reverse mode.
Therefore, set the 16-bit dead timer registers (TMRRH0 to TMRRH2, TMRRL0 to TMRRL2) not to be
reloaded repeatedly.
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11.6 Operation of the Multi-function Timer
MB91490 Series
Figure 11.6-27 When reloaded before the dead timer underflow occurs
<Register setting>
TCDTH, TCDTL
: XXXXH
OCCPH0 to 5, OCCPL0 to 5 : XXXXH (Compare value)
TCCSH, TCCSL
: XXXXXXXX X0X0XXXXB
OCSH0 to 5, OCSL0 to 5
: -XX1XXXX XXXXXX11B
CPCLRH, CPCLRL
: XXXXH (Setting of cycle)
DTCR0 to 2
: XXXXX100B
TMRRH0 to TMRRH2, TMRRL0 to TMRRL2 : XXXXH (Setting of non-overlap timing)
SIGCR1
: XXXXXXXXB (Setting of DTTI input and 16-bit dead timer count clock)
Note: Be sure to set according to "X" operation.
16-bit dead timer 0
Count value
TMRRH0/
TMRRL0
set value
Time
RT 1
Normal mode
RTO0(U)
"L"
RTO1(X)
2 per ipheral cloc k
(CLKP) cycles
2 per ipheral cloc k
(CLKP) cycles
2 per ipheral cloc k (CLKP) cycles
Reverse mode
"H"
RTO0(U)
RTO1(X)
2 per ipheral cloc k
(CLKP) cycles
308
2 per ipheral cloc k
(CLKP) cycles
2 per ipheral cloc k (CLKP) cycles
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11.6 Operation of the Multi-function Timer
MB91490 Series
11.6.5.3
DTTI Pin Control Operation
You can control RTO0 to RTO5 output by means of the DTTI pins by setting "1" in the
waveform control register 1 (SIGCR1) DTIE: bit7. When a DTTI pin "L" level is detected,
RTO0 to RTO5 output is fixed at non-operating level until the interrupt flag (SIGCR
register DTIF: bit6) is cleared. When RTO0 to RTO5 is at non-operating level, these pins
can be set via software using the port data registers (PDR), which share them.
Additionally, if they are used as input ports using the data direction register (DDR), Hi-Z
is output.
■ DTTI Pin Input Operation
Even when "L" is detected in DTTI pin input, although the timer continues to operate while the waveform
generator is operational, waveforms are not output to the external RTO0 to RTO5 pins.
Figure 11.6-28 Operation for Valid DTTI Input
<Register setting>
TCDTH, TCDTL
:
TCCSH, TCCSL
:
OCSH0 to OCSH5, OCSL0 to OCSL5
:
PDRx
:
TMRRH0 to TMRRH2, TMRRL0 to TMRRL2 :
SIGCR1
:
Note: Be sure to set according to "X" operation.
CPCLRH, CPCLRL
: XXXXH (Setting of cycle)
XXXXH
XXXXXXXX X0X0XXXXB OCCPH0 to OCCPH5, OCCPL0 to OCCPL5 : XXXXH (Compare value)
DTCR0 to DTCR2
: 0XXXX100B
-XX1XXXX XXXXXX11B
XXXXXX00B (Setting of non-operating level)
XXXXH (Setting of non-overlap timing)
1XXXXXXXB (Setting of DTTI input and 16-bit dead timer count clock)
16-bit free-run timer
Count value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Compare
register 0
BFFFH
Compare
register 1
3FFFH
RT1
RTO0
RTO1
DTTI0
DTIF
Output non-operating
Software reset
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11.6 Operation of the Multi-function Timer
MB91490 Series
■ DTTI Operation of Waveform Control Register 2 (SIGCR2)
The output of waveform control register 2’s DTTI: bit0 with the DTTI pin input and OR is the DTTI input.
Consequently, when "0" is set in this register, control is permanently in DTTI input status, and the input
from the DTTI pins has no meaning.
When this register is cleared by writing "1", the DTTI pin input value is used.
■ DTTI Pin Noise Cancellation Feature
The DTTI pin input noise cancellation feature is enabled when "1" is set in the waveform control register 1
(SIGCR1) NRSL: bit5. When the noise cancellation feature is enabled, there is a delay of 4, 8, 16, or 32
peripheral clock (CLKP) cycles (selected via the SIGCR1 register NWS1 and NWS0: bit1 and bit0), for the
a mount of time necessary to lock the output pins (RTO0 - RTO5) to non-operating level. Since the noise
cancellation circuit uses resources, in modes where oscillation is stopped (e.g. stopped mode), input is
disabled, even when DTTI input is enabled.
■ DTTI Interrupt
When DTTI "L" level is detected, after the noise cancellation time has elapsed, the DTTI interrupt flag
(SIGCR1 register DTIF: bit6) is set to "1", and an interrupt request is sent to the interrupt controller.
Figure 11.6-29 DTTI Interrupt Timing
DTTI
SIGCR1 register
DTIF bit
Noise cancel time that is controlled
by NWS1 and NWS0 bits of SIGCR1
register
"0" is written to DTIF bit of
SIGCR1 register via software
Notes:
• The setting in PFRQ is invalid when DTIF: bit6 of the waveform control register 1 (SIGCR1) is 1,
and the respective ports are always used as general-purpose ports. See Section "4.2.4 MultiFunction Timer I/O Port" for details.
• If the SIGCR1 registers NWS1 and NWS0 bits' values change within the noise cancellation time,
a larger (NWS1 and NWS0) noise cycle value is enabled.
• The SIGCR1 register DTIF: bit6 can only be cleared via software.
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11.6 Operation of the Multi-function Timer
MB91490 Series
11.6.6
A/D Activation Compare Operation
An A/D activation can be performed when the value of 16-bit free-run timer reaches the
specified value.
■ A/D Activation
Three A/D converter units can be activated.
■ A/D Compare Activation Enabled
If the compare register value is set, and other than "00B" is set into the compare enable register (ADTGCE)
CE00, CE01, CE20, CE21: bit0, bit1, bit4, bit5, when the free run timer and compare register value are
matched, an A/D activation signal is generated.
When "00B" is set into CE00, CE01, CE20, CE21, even if the free run timer and compare register value are
matched, an A/D activation signal is not generated.
■ Setting of Free-run Timer Input Selection
The free-run timer input can be selected independently for the A/D activation compare by the compare
enable register (ADTGCE) as well as the A/D activation compare enable control.
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11.6 Operation of the Multi-function Timer
MB91490 Series
■ A/D Compare Activation Mode
The A/D activation mode is set in the SEL bits of the ADTGSEL register.
● SELn1, SELn0 = 0, 0: Generate activation when a compare match occurs
Free-run timer
Count value
Compare value
Time
A/D activation
A/D activation
A/D activation
A/D activation
● SELn1, SELn0 = 0, 1: Only generate activation when a compare match occurs for an up-count
Free-run timer
Count value
Compare value
Time
A/D activation
A/D activation
● SELn1, SELn0 = 1, 0: Only generate activation when a compare match occurs for a down-count
Free-run timer
Count value
Compare value
Time
A/D activation
A/D activation
● SELn1,SELn0=1, 1: Activating compare match at up-counting and down-counting
Free-run timer
ADCOMP
ADCOMPD
Time
A/D activation
A/D activation
A/D activation
A/D activation
■ Setting of Free-run Timer Count Direction Selection
The A/D activation compare register is compared with the free-run timer by the count direction selection
register (ADTGSEL) in either of up-counting, down-counting or up/down-counting.
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11.6 Operation of the Multi-function Timer
MB91490 Series
■ Compare Register Buffering
Writing "0" to the BUFX bits (bit2, bit0) of the buffer control register (ADTGBUF) enables the compare
register buffering. If buffering is selected (by setting buffer control register (ADTGBUF), BTS bits (bit6,
bit4), the buffer is transferred the value of the compare register to the compare buffer register at the
compare clear interruption (by setting ADTGBUF, BTS:bit6, bit4=1) or zero detection interruption (by
setting ADTGBUF, BTS:bit6, bit4=0).
■ A/D Activation by Zero Detection of Free-run Timer or Compare Clear
If "1" is written to the AD2E, AD0E bits (bit2, bit0) of the A/D trigger control register (ADTRGC),
A/D can be activated when a zero detection of the free-run timer or a compare match interrupt occurs.
When "0" is set to the SEL bit (bit6, bit4) of the A/D trigger control register (ADTRGC), zero detection
occurs. When "1" is set to it, compare match interrupt occurs.
■ Reload Timer (ch.1)
When A/D compare activation is disabled and the A/D activation by a zero detection of the free- run timer
or a compare clear is disabled, the A/D activation by the 16-bit reload timer ch.1 is enabled. The activation
by the 10-bit A/D converter 1 is enabled.
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11.6 Operation of the Multi-function Timer
MB91490 Series
Figure 11.6-30 Compare Register 0: Valid Buffer Function, and Compare Register 2: Invalid Buffer Function
Count value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Reset
Compare buffer
register 0
BFFFH
Compare
register 0
7FFFH
BFFFH
BTS0
BUFX0
Zero detection
Compare buffer
register 2
Compare
register 2
3FFFH
3FFFH
4FFFH
2F24H
4FFFH
2F24H
BTS2
BUFX2
Compare clear
Figure 11.6-31 A/D Trigger 0 is Activating at Up/Down Counting, A/D Trigger 2 is Activating at Up Counting
Count value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Reset
Compare
register 0
7FFFH
Compare
register 2
3FFFH
ADTGSEL:SEL0
00B
ADTGSEL:SEL2
01B
BFFFH
A/D trigger 0
A/D trigger 2
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11.6 Operation of the Multi-function Timer
MB91490 Series
Figure 11.6-32 A/D Activation Compare Compare Clear Interrupt of Free-run Timer
Count value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Reset
Compare
register 0
7FFFH
ADTGSEL:SEL0
00B
Zero detection
Compare clear
ADTRGCE0
01B
00B
ADTRGC:
SEL0
ADTRGC:
AD0E
A/D trigger 0
Figure 11.6-33 The Data Transfer Timing at Compare Match at Free-run timer Up-count Mode
Count value
FFFF H
CFFFH
BFFFH
0000H
Time
Compare buffer
register
Compare register
BFFFH
BFFFH
CFFFH
BFFFH
CFFFH
0000H
BFFFH
BFFFH
0000H
0000H
BFFFH
CFFFH
0000H
FFFFH
CFFFH
0000H
FFFFH
0000H
A/D Trigger
Figure 11.6-34 The Data Transfer Timing at Zero Detection at Free-run timer Up-count Mode
Count value
FFFF H
CFFFH
BFFFH
0000H
Time
Compare buffer
register
Compare register
BFFFH
BFFFH
CFFFH
BFFFH
CFFFH
0000H
BFFFH
BFFFH
0000H
0000H
BFFFH
CFFFH
0000H
FFFFH
CFFFH
0000H
FFFFH
0000H
A/D Trigger
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11.6 Operation of the Multi-function Timer
MB91490 Series
Figure 11.6-35 The Data Transfer Timing at Compare Match at Free-run timer Up/Down Count Mode
Count value
CFFFH
BFFFH
0000H
Time
Compare buffer
register
BFFFH
Compare register
BFFFH
CFFFH
BFFFH
BFFFH
0000H
CFFFH
BFFFH
FFFFH
0000H
0000H
FFFFH
A/D Trigger
Figure 11.6-36 The Data Transfer Timing at Zero Detection at Free-run timer Up/Down Count Mode
Count value
CFFFH
BFFFH
0000H
Time
Compare buffer
register
BFFFH
Compare register
BFFFH
CFFFH
BFFFH
CFFFH
0000H
BFFF H
FFFFH
0000 H
0000H
FFFF H
0000 H
A/D Trigger
Note:
See Section "11.7 Notes on Using the Multi-function Timer" for connection between the A/D
activation compare and A/D converter.
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11.7 Notes on Using the Multi-function Timer
MB91490 Series
11.7
Notes on Using the Multi-function Timer
Heed the following cautions when using the multi-function timer.
■ Notes at Accessing the Buffer Registers
CPCLRL/Hn register in free-run timer, OCCPL/Hn register in output compare, and ADCOMPn/
ADCOMPBn register in A/D activating compare have the buffer function. Do not access to these registers
by the read-modify-write instruction.
■ Notes on Using the 16-bit Free-run Timers
● Cautions for setting via the program
• When a reset is executed, although the timer value becomes "0000H", the zero-detect interrupt flag is
not set.
• Since the timer-mode bit (TCCSL registers MODE: bit5) has a buffer, and so timer modes changed after
zero-detect are enabled.
• A software clear (setting bit4 (SCLR) in the TCCSL register = 1) initializes the timer but does not
generate a zero-detect interrupt.
• When the compare value and count value match, if the count starts, the compare-clear flag is not set.
● Cautions for interrupt
• If "1" is set in the timer state control register upper (TCCSH) IRQZF: bit14, then interrupt requests are
enabled (TCCSH register's IRQZE: bit13 = 1), control cannot return from the interrupt processing. Be
sure to clear the IRQZF: bit14.
• If "1" is set in the timer state control register upper (TCCSH) ICLR: bit9, then interrupt requests are
enabled (TCCSH register's ICRE: bit8 =1), control cannot return from the interrupt processing. Be sure
to clear the ICLR: bit9.
● Cautions at accessing the TCCSH/TCCSM registers
• A set value is read from MSI2 to MSI0/MSI5 to MSI3 at the read-modify-write instruction.
• The counter value is read from MSI2 to MSI0/MSI5 to MSI3 at the normal reading.
■ Cautions for Use of Free-run Timer Selector
Be sure to select the setting while the free-run timer is stopped.
■ Notes on Using the 16-bit Output Compare
● Cautions for interrupt
If "11B" is set in the compare control registers lower-order(OCSL0, OCSL2, and OCSL4) IOP1, IOP0 :
bit7 and bit6, then interrupt requests are enabled (OCSL register's IOE1, IOE0 : bit6 and bit5=11B), control
cannot return from the interrupt processing. Be sure to clear the IOP0, IOP1 bits.
■ Cautions for Use of 16-bit Input Capture
● Cautions for interrupt
• If "1" is set in the input capture state control registers lower-order (PICSL01 and ICSL23) ICP3, ICP2,
ICP1, and ICP0 (both bit7 and bit6), then interrupt requests are enabled (PCICSL01 and ICSL23
register’s ICE3, ICE2, ICE1, and ICE0 (both bit5 and bit4) =11B), control cannot return from the
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11.7 Notes on Using the Multi-function Timer
MB91490 Series
interrupt processing. Be sure to clear ICP 3, ICP 2, ICP 1, and ICP 0 (both bit7 and bit6).
• When the input capture pin (IC) level changes the time between setting the bit for ICP3, ICP2, ICP1,
and ICP0 and processing of the interrupt routine, the valid edge indication bits of the ICP3, ICP2, ICP1,
and ICP0 (ICSH23 register’s IEI3 and IEI2: bit9 and bit8 and PICSH01 register’s IEI1 and IEI0: bit9,
bit8) indicates the newly detected edge.
■ Notes on Using the Waveform Generator
● Cautions for setting via the program
• Confirm that the trigger source and 16-bit dead timer are not counting when the bit values of TMD8,
TMD5, TMD2 (higher-order bit is 10; lower-order bit is 2), TMD7, TMD4, TMD1 (higher-order bit is
9; lower-order bit is 1), and TMD6, TMD3, TMD0 (higher-order bit is 8; lower-order bit is 0) in the 16bit dead timer control registers (DTCR0, DTCR1, and DTCR2) are changed while the waveform
generator is operating (DTCR0, DTCR1, and DTCR2 register’s TMD2 to TMD0, TMD5 to TMD3,
TMD8 to TMD6 are "001B", "010B", or "100B"). If this operation is not performed, an unintended
waveform will be output from the RTO pin due to the output scheduled by the previous trigger.
However, the RTO output returns to normal operation when a timer underflow occurs or when triggered
again by the new trigger source.
• The trigger source is at "H" level for RT when TMD8 to TMD0 (higher-order bits are 10 to 8; lowerorder bits are 2 to 0) in the DTCR0, DTCR1, and DTCR2 registers are "001B"; it is rising edge of RT
when these bits are "010B"; it is rising or falling edge of RT when these bits are "100B".
For example, if TMD bit8 to bit0 change from "100B" to "010B", the following steps can be executed.
1. Set the 16-bit dead timer register (TMRRH0 to TMRRH2, TMRRL0 to TMRRL2) to an extremely
small value like 0001H.
2. Set the RTO1, RTO3, or RTO5 output to "L" or "H" and wait for an underflow on timer 0, 1, or 2.
3. Change the mode bits (TMD 8 to TMD 0) and corresponding settings.
4. A corrected output waveform appears at the RTO pins after 1 machine cycle.
• If the value of the 16-bit dead timer register (TMRRH0 to TMRRH2, TMRRL0 to TMRRL2) is
modified while the timer is counting, the new value is not used until the next timer trigger. When
accessing the timer registers, be sure to use half-word or word data transfer commands.
• Only change the waveform control register 1’s (SIGCR1) DCK2 to DCK0: bit4 to bit2 when the timers
are not counting.
• Only change the waveform control register 1’s (SIGCR1) NWS1 and NWS0: bit1 and bit0 when the
noise cancellation feature is disabled.
● Cautions for interrupt
• If "1" is set in the 16-bit dead timer control register (DTCR0, DTCR1, and DTCR2) TMIF2 to TMIF0
(higher-order bit is 12; lower-order bit is 4), then interrupt requests are enabled (DTCR0, DTCR1, and
DTCR2 register’s TMIE2 to TMIE0 (higher-order bit is 11; lower-order bit is 3) =1), control cannot
return from the interrupt processing. Be sure to clear the TMIF bit.
• Control cannot return from interrupt processing after setting 1 in the waveform control register 1
(SIGCR1)DTIF:bit6. Be sure to clear the DTIF bit.
■ Notes on Using the A/D Activation Compare
Be sure to select the setting while the free-run timer is stopped.
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11.8 Example Program for Multi-function Timer
MB91490 Series
11.8
Example Program for Multi-function Timer
Below is a sample multi-function timer program.
■ Example Program for the 16-bit Free-run Timer
● Processing
• When the 16-bit free-run timer is 4 ms, generate a compare-clear interrupt.
• This timer is used to re-generate a compare-clear timer during up-count mode.
• 16 MHz is for the peripheral clock (CLKP), and 62.5 ns is for the count clock.
● Coding example
ICR33
.EQU
000461H
; Compare clear interrupt control register for the 16-bit free-run
; timer 0
TCCSH
.EQU
0000B8H
; Timer control status register
CPCLRBH .EQU
0000B4H
; Compare-clear buffer register
; --------------- Main Program -----------------------------------------------------------------------------ORG
C0000H
START:
;
:
; Assumes that the stack pointer (SP) has already been
; initialized.
ANDCCR
#0EFH
LDI
#ICR32,r0
; Disables the interrupt.
LDI
#00H,r1
STB
r1,@r0
; Interrupt levels 16 (the highest priority)
LDI
#CPCLRBH,r0
; Set value to the compare clear buffer register so that
LDI
#0FA00H,r1
; compare clear interrupts will be generated at 4ms
STH
r1,@r0
; intervals in 16-bit free-run timer up-count mode
LDI
#TCCSH,r3 ; Set up-down count mode,
LDI
#0110H,r1
; set 62.5ns count clock,
STH
r1,@r3
; enable compare clear interrupt,
; clear compare clear interrupt flag bit,
; disable interrupt mask,
; clear timer, and enable operation
LOOP
STILM
#14H
; Set the ILM in PS to level 20
ORCCR
#10H
; Interruption permission
LDI
#00H,r0
; Infinite loop
LDI
#01H,r1
BRA
LOOP
;
; --------------- Interrupt Program -------------------------------------------------------------------------CM71-10155-2E
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11.8 Example Program for Multi-function Timer
WARI
LDI
#0100H,r1
ANDH
r1,@r3
;
:
;
User processing
;
:
RETI
MB91490 Series
; Clear interrupt request flag.
: Returns from interrupt.
; --------------- Vector Settings ----------------------------------------------------------------------------VECT
.ORG FFFF8H
.DATA.W
WARI
; Set interrupt routine.
.ORG
FFFF8H
.DATA.W
0x07000000 ; Set single-chip mode.
.DATA.W
START
; Set reset vectors
.END
■ Example Program for the 16-bit Output Compare
● Processing
• When the 16-bit free-run timers count value matches the output compare value, an output compare
match is generated.
• Use when the 16-bit free-run timer is in up/down count mode.
● Coding example
ICR44
.EQU
00046CH
; Output compare 0/1 interrupt register
TCCSH
.EQU
0000B8H
; Timer control status register
CPCLRBH .EQU
0000B4H
; Compare-clear buffer register
OCCPBH0 .EQU
0000A0H
; Output compare buffer register 0
OCCPBH1 .EQU
0000A2H
; Output compare buffer register 1
OCSH1
0000ACH
; Compare control register
.EQU
; --------------- Main Program -----------------------------------------------------------------------------START:
;
320
:
; Assumes that the stack pointer (SP) has already been
; initialized.
ANDCCR
#0EFH
; Disables the interrupt.
LDI
#ICR44,r0
LDI
#00H,r1
STB
r1,@r0
LDI
#CPCLRBH,r0 ; Set compare clear buffer register
LDI
#0FFFFH,r1
STH
r1,@r0
; Interrupt levels 16 (the highest priority)
; for 16-bit free-run timer
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CHAPTER 11 MULTI-FUNCTION TIMER
11.8 Example Program for Multi-function Timer
MB91490 Series
LOOP
LDI
#OCCPBH0,r0 ; Set the output compare register 0.
LDI
#0BFFFH,r1
STH
r1,@r0
LDI
#OCCPBH1,r0 ; Set the output compare register 1.
LDI
#07FFFH,r1
STH
r1,@r0
LDI
#OCSH1,r3
; Enable output compare output.
LDI
#6C33H,r2
; Enable compare match interrupts 0/1.
STH
r2,@r3
; Clear the interrupt flag bit.
LDI
#TCCSH,r0
; Set up-down count mode,
LDI
#0010H,r1
; clear timer, and enable operation
STH
r1,@r0
STILM
#14H
; Set the ILM in PS to level 20
ORCCR
#10H
; Interruption permission
LDI
#00H,r0
; Infinite loop
LDI
#01H,r1
BRA
LOOP
;
; --------------- Interrupt Program -----------------------------------------------------------------------WARI :
ANDH
r2,@r3
;
:
;
User processing
;
:
RETI
; Clear interrupt register flag.
: Returns from interrupt.
; --------------- Vector Settings ----------------------------------------------------------------------------VECT
.ORG FFFF8H
.DATA.W WARI
.ORG
; Set interrupt routine.
FFFF8H
.DATA.W 0x07000000
; Set single-chip mode.
.DATA.W START
; Set reset vectors.
.END
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CHAPTER 11 MULTI-FUNCTION TIMER
11.8 Example Program for Multi-function Timer
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MB91490 Series
CM71-10155-2E
CHAPTER 12
BASE TIMER
This chapter provides an overview of the base timer,
summarizes its register configuration and functions, and
describes its operations.
12.1 Overview of the Base Timer
12.2 Block Diagrams of the Base Timer
12.3 Base Timer's Registers
12.4 Operations of the Base Timer
12.5 32-bit Mode Operations
12.6 Notes of Using the Base Timer
12.7 Base Timer Interrupts
12.8 Base Timer Description by Function Mode
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CHAPTER 12 BASE TIMER
12.1 Overview of the Base Timer
12.1
MB91490 Series
Overview of the Base Timer
The base timer can assign itself, according to the settings of the FMD2, FMD1, and
FMD0 bits in its timer control register, to serve as only one of the 16-bit PWM timer, 16bit PPG timer, 16/32-bit reload timer, and 16/32-bit PWC timer. This section outlines the
base timer in each function mode available.
■ Function Mode Bit Settings and Timer Function Modes Assigned
FMD2/FMD1/FMD0 bit Settings
Timer Function Mode
000B
Reset mode
001B
16-bit PWM timer
010B
16-bit PPG timer
011B
16/32-bit reload timer
100B
16/32-bit PWC timer
■ Reset Mode
Placing the base timer in this mode resets its macro (with each register reset to the initial value). Place the
base timer in this mode once before changing its function mode or T32 bit setting. After a reset, however,
the base timer can set its function mode and the T32 bit without entering the reset mode in advance.
■ 16-bit PWM Timer
The 16-bit PWM timer mainly consists of a 16-bit down counter, a 16-bit data register buffered for period
setting, a 16-bit compare register buffered for duty cycle setting, and a pin controller.
Period data and duty cycle data can be updated during timer operation as they are held in their buffered
respective registers.
The count clock for the 16-bit down counter can be selected from among five different internal clocks
(available by frequency-dividing the peripheral clock (CLKP) by 1, 4, 16, 128, and 256).
The PWM timer can select one-shot mode in which stops counting on an underflow or continuous mode in
which repeats counting by reloading.
For activation, the PWM timer can select a software trigger or one of three different external events (risingedge detection, falling-edge detection, and both-edge detection).
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CHAPTER 12 BASE TIMER
12.1 Overview of the Base Timer
MB91490 Series
■ 16-bit PPG Timer
The 16-bit PPG timer mainly consists of a 16-bit down counter, a 16-bit data register for "H"-width setting,
a 16-bit data register for "L"-width setting, and a pin controller.
The count clock for the 16-bit down counter can be selected from among five different internal clocks
(available by frequency-dividing the peripheral clock (CLKP) by 1, 4, 16, 128, and 256).
The PPG timer can select one-shot mode in which stops counting on an underflow or continuous mode in
which repeats counting by reloading.
For activation, the PPG timer can select a software trigger or one of three different external events (risingedge detection, falling-edge detection, and both-edge detection).
■ 16/32-bit Reload Timer
The 16/32-bit reload timer mainly consists of a 16-bit down counter, a 16-bit reload register, and a pin
controller.
The count clock for the 16-bit down counter can be selected from among five different internal clocks
(available by frequency-dividing the peripheral clock (CLKP) by 1, 4, 16, 128, and 256).
The reload timer can select one-shot mode in which stops counting on an underflow or continuous mode in
which repeats counting by reloading.
For activation, the reload timer can select a software trigger or one of three different external events (risingedge detection, falling-edge detection, and both-edge detection).
■ 16/32-bit PWC Timer
The 16/32-bit PWC timer mainly consists of a 16-bit up counter, a measurement input pin, and control
registers.
The PWC timer measures the time between arbitrary events based on the pulse input from an external
source.
The reference count clock can be selected from among five different internal clocks (available by
frequency-dividing the peripheral clock (CLKP) by 1, 4, 16, 128, and 256).
Measurement modes
"H" pulse width ( to ) / "L" pulse width ( to )
Rising period ( to ) / Falling period ( to )
Inter-edge measurement ( or  to  or )
The PWC timer can generate an interrupt request upon completion of measurement.
The PWC timer can select one-shot measurement or continuous measurement.
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CHAPTER 12 BASE TIMER
12.2 Block Diagrams of the Base Timer
12.2
MB91490 Series
Block Diagrams of the Base Timer
This section provides a block diagram of the base timer in each function mode.
■ Block Diagram of 16-bit PWM Timer
Figure 12.2-1 Block Diagram of 16-bit PWM Timer
BTnPCSR
n = 0,1
BTnPDUT
Write to
BTnPDUT
Load
CKS
Buffer
Buffer
/ 16
/ 16
OSEL
/3
Peripheral clock
(CLKP)
20
Frequency
divider
circuit
Count
clock
27
28
16
/
Down counter
BTnTMR
Count
Under
enable
flow
EGS
/
2
Inversion
control
Match
detection
Load
PMSK
Toggle
generation
TOUT
UDIE
STRG CTEN
TIN
Edge
detection
Count
enable
IRQ0
Interrupt
source
generation
MDSE
Trigger
DTIE
IRQ1
CTEN
Timer enable
TGIE
■ Block Diagram of 16-bit PPG Timer
Figure 12.2-2 Block Diagram of 16-bit PPG Timer
Set reload
data
n = 0,1
CKS
BTnPRLL
16
/
BTnPRLHB
/3
Peripheral clock
(CLKP)
Frequency
divider
circuit
Count
clock
27
28
/
2
Load
Down counter
BTnTMR
Count
Underenable
flow
EGS
STRG CTEN
OSEL inversion
control
326
Edge
detection
PPG output
TOUT
Toggle
generation
PMSK
UDIE
Count
enable
MDSE
CTEN
TIN
BTnPRLH
20
IRQ0
Interrupt
source
generation
IRQ1
Trigger
Timer enable
FUJITSU SEMICONDUCTOR LIMITED
TGIE
CM71-10155-2E
CHAPTER 12 BASE TIMER
12.2 Block Diagrams of the Base Timer
MB91490 Series
■ Block Diagram of 16/32-bit Reload Timer (ch.1, ch.0)
Figure 12.2-3 Block Diagram of 16/32-bit Reload Timer (ch.1, ch.0)
ch.1
BTnPCSR
/ 16
Count
clock
Load
Down counter
BTnTMR
UnderCount
flow
enable
32-bit mode
T32 = 1
16-bit mode
T32 = 0
ch.0
OSEL
BTnPCSR
Inversion
control
Toggle
generation
CKS
/3
Peripheral
clock
(CLKP)
/ 16
20
Frequency
divider
circuit
Count
clock
27
28
/
2
TOUT
Load
Down counter
BTnTMR
UnderCount
flow
enable
EGS
Output waveform
T32
MDSE
Count
enable
UDIE
IRQ0
STRG
TIN
Trigger
Edge
detection
CTEN
CTEN
Interrupt
source
generation
IRQ1
Timer enable
TGIE
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CHAPTER 12 BASE TIMER
12.2 Block Diagrams of the Base Timer
MB91490 Series
■ Block Diagram of 16/32-bit PWC Timer (ch.1, ch.0)
Figure 12.2-4 Block Diagram of 16/32-bit PWC (ch.1, ch.0)
ch.1
BTnDTBF
/ 16
Count
clock
Clear
Up counter
BTnTMR
Count
ena ble
Overflow
32-bit mode
T32 = 1
16-bit mode
T32 = 0
BTnDTBF
ch.0
CKS
/3
/ 16
0
Peripheral
clock
(CLKP)
2
Frequency
divider
circuit
Count
clock
27
28
Clear
Up counter
BTnTMR
Count
ena ble
Overflow
MDSE
MDSE
/
3
EGS
Edge
detection
Edge
detection
328
OVIE
Count
ena ble
STRG
TIN
T32
CTEN
IRQ0
Interrupt
source
generation
IRQ1
Sta rt detection
CTEN
Stop detection
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CM71-10155-2E
CHAPTER 12 BASE TIMER
12.3 Base Timer's Registers
MB91490 Series
12.3
Base Timer's Registers
This section lists the registers used for the base timer and their bit configurations in
each timer function mode.
■ List of Base Timer's Registers
Table 12.3-1 List of Base Timer's Registers
Function mode settings
(FMD2, FMD1, FMD0)
Addresses
bit15
bit8 bit7
All modes
000162H
000582H
000163H
000583H
BTnTMCR (timer control register)
All modes
-
000165H
000585H
-
001B/010B/011B
000160H
000580H
000161H
000581H
100B
001B/011B
010B
BTnSTC
(status control register)
BTnTMR (timer register)
-
BTnPCSR (period setting register)
000168H
000588H
000169H
000589H
BTnPRLL ("L"-width setting reload register)
100B
-
001B
BTnPDUT (duty setting register)
010B
011B
100B
bit0
00016AH
00058AH
00016BH
00058BH
BTnPRLH ("H"-width setting reload register)
BTnDTBF (data buffer register)
n = 0,1
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CHAPTER 12 BASE TIMER
12.3 Base Timer's Registers
MB91490 Series
■ Bit Configurations in Each Timer Function Mode
Figure 12.3-1 Registers for 16-bit PWM Timer
Function mode setting
bit15
bit7
-
bit14
bit13
FMD=001B
bit12
bit11
bit10
bit9
bit8
CKS2 CKS1 CKS0 RTGEN PMSK EGS1 EGS0
bit6
bit5
bit4
bit3
bit2
bit1
BTnTMCR
(timer control register)
bit0
FMD2 FMD1 FMD0 OSEL MDSE CTEN STRG
bit7
bit6
bit5
bit4
bit3
-
TGIE
DTIE
UDIE
-
bit15
bit14
bit13
bit12
bit11
bit2
bit1
bit0
BTnSTC
TGIR DTIR UDIR
(status control register)
bit10
BTnTMR
bit9
bit8
(timer register)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
BTnPCSR
(period setting register)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
BTnPDUT
(duty setting register)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
n = 0,1
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CHAPTER 12 BASE TIMER
12.3 Base Timer's Registers
MB91490 Series
Figure 12.3-2 Registers for 16-bit PPG Timer
Function mode setting
bit15
bit7
-
bit14
bit13
FMD=010B
bit12
bit11
bit10
bit9
bit8
CKS2 CKS1 CKS0 RTGEN PMSK EGS1 EGS0
bit6
bit5
bit4
bit3
bit2
bit1
BTnTMCR
(timer control register)
bit0
FMD2 FMD1 FMD0 OSEL MDSE CTEN STRG
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
-
TGIE
-
UDIE
-
TGIR
-
UDIR
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
BTnSTC
(status control register)
BTnTMR
(timer register)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
BTnPRLL
("L"-width setting reload
register)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
BTnPRLH
("H"-width setting reload
register)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
n = 0,1
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CHAPTER 12 BASE TIMER
12.3 Base Timer's Registers
MB91490 Series
Figure 12.3-3 Registers for Reload Timer
Function mode setting
bit15
bit7
T32
bit14
bit13
FMD=011B
bit12
CKS2 CKS1 CKS0
bit6
bit5
bit4
bit11
bit10
-
-
bit3
bit2
bit9
bit8
EGS1 EGS0
bit1
BTnTMCR
(timer control register)
bit0
FMD2 FMD1 FMD0 OSEL MDSE CTEN STRG
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
-
TGIE
-
UDIE
-
TGIR
-
UDIR
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
BTnSTC
(status control register)
BTnTMR
(timer register)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
BTnPCSR
(period setting register)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
n = 0,1
Figure 12.3-4 Registers for PWC Timer
Function mode setting
bit15
bit7
T32
bit14
bit13
FMD=100B
bit12
CKS2 CKS1 CKS0
bit6
bit5
bit4
FMD2 FMD1 FMD0
bit11
bit3
-
bit10
bit9
bit8
EGS2 EGS1 EGS0
bit2
bit1
MDSE CTEN
BTnTMCR
(timer control register)
bit0
-
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ERR
EDIE
-
OVIE
-
EDIR
-
OVIR
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
BTnSTC
(status control register)
BTnDTBF
(data buffer register)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
n = 0,1
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CHAPTER 12 BASE TIMER
12.4 Operations of the Base Timer
MB91490 Series
12.4
Operations of the Base Timer
This section introduces how the base timer operates in each timer function mode.
■ Operations of the Base Timer
● Reset mode
Placing the base timer in this mode resets its macro (with each register reset to the initial value). Place the
base timer in this mode once before changing its function mode or T32 bit setting. After a reset, however,
the base timer can set its function mode and the T32 bit without entering the reset mode in advance. If you
set this mode for even-numbered channels in 32-bit mode, odd-numbered channels are reset as well at the
same time. Thus you do not have to set the reset mode for odd-numbered channels.
● 16-bit PWM timer
The 16-bit PWM timer starts decrementing its counter by the value set as a period when triggered to start.
The PWM timer then sets the output to the "L" level first and, if the 16-bit down counter value matches the
value set in the duty setting register, inverts the output to the "H" level. Then it inverts the output back to
the "L" level when the counter causes an underflow subsequently. This generates a waveform with an
arbitrary period and duty cycle.
● 16-bit PPG timer
The 16-bit PPG timer starts decrementing its counter by the value set in the "L"-width setting reload
register when triggered to start. The PPG timer then sets the output to the "L" level first and inverts the
output back to the "H" level when the counter causes an underflow. The PPG timer continuously
decrements the counter by the value set in the "H"-width setting reload register and inverts the output level
to "L" when the counter causes an underflow. This generates a waveform with arbitrary "L" and "H"
widths.
● 16-bit reload timer
The 16-bit reload timer starts decrementing its 16-bit down counter by the value set as a period when
triggered to start. When the down counter causes an underflow, the interrupt flag is set. Depending on the
MDSE bit setting, the output level either toggles, or is inverted, between "H" and "L" each time the counter
causes an underflow or becomes "H" when the counter starts counting and "L" when it causes an
underflow.
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CHAPTER 12 BASE TIMER
12.4 Operations of the Base Timer
MB91490 Series
● 32-bit reload timer
The 32-bit reload timer is the same in basic operation as the 16-bit reload timer, except that it works as a
32-bit version using a pair of even-numbered and odd-numbered channels. Although the even-numbered
and odd-numbered channels then operate as the lower 16-bit and upper 16-bit timers, respectively, interrupt
control and output wave control follow their respective settings for the even-numbered channel. To set the
period, write the value to the upper register (odd-numbered channel) first and then to the lower register
(even-numbered channel).
To obtain the timer value, read the lower register (even-numbered channel) first and then the upper register
(odd-numbered channel).
● 16-bit PWC timer
The 16-bit PWC timer starts the 16-bit up counter upon input of a pre-set measurement start edge and stops
the counter upon detection of a measurement stop edge. The count value between the two edges is written
to the data buffer register as a pulse width.
● 32-bit PWC timer
The 32-bit PWC timer is the same in basic operation as the 16-bit PWC timer, except that it works as a 32bit version using a pair of even-numbered and odd-numbered channels. Although the even-numbered and
odd-numbered channels then operate as the lower 16-bit and upper 16-bit counters, respectively, interrupt
control follows the setting for the even-numbered channel. To obtain the measured value or count value,
read the lower register (even-numbered channel) first and then the upper register (odd-numbered channel).
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CHAPTER 12 BASE TIMER
12.5 32-bit Mode Operations
MB91490 Series
12.5
32-bit Mode Operations
The reload timer and PWC timer can operate in 32-bit mode using a pair of channels.
This section describes the basic functions and operations of 32-bit mode.
■ Functions of 32-bit Mode
The 32-bit mode combines two channels of base timer into a 32-bit data reload timer or PWC timer. Either
32-bit timer allows the timer/counter value to be read even during operation as it takes the upper 16-bit
timer/counter value of the odd-numbered channel also when reading the lower 16-bit timer/counter value of
the even-numbered channel.
■ Setting the 32-bit Mode
First, set the FMD2, FMD1, and FMD0 bits in the BTnTMCR register for the even-numbered channel to
"000B" to reset in reset mode. Then, select the reload timer or PWC timer and set its operations in the same
way as in 16-bit mode. At this time, write "1" to the T32 bit in the BTnTMCR register to enter the 32-bit
operation mode. The T32 bit for the odd-numbered channel must be left containing "0". Neither the reset
mode setting is required for the odd-numbered channel. To use the base timer as the reload timer, set the
period setting register for the odd-numbered channel to the upper 16-bit reload value among 32 bits and set
the period setting register for the even-numbered channel to the lower 16-bit reload value.
As the transition to 32-bit operation mode takes place the moment is written to the T32 bit, the setting must
be changed with counting halted on both of the channels.
To switch from 32-bit mode to 16-bit mode, set the FMD2, FMD1, and FMD0 bits in the BTnTMCR
register for the even-numbered channel to "000B" to reset the states of both of the even-numbered and oddnumbered channels in reset mode. Then set each channel for operation in 16-bit mode.
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CHAPTER 12 BASE TIMER
12.5 32-bit Mode Operations
MB91490 Series
■ Operations in 32-bit Mode
When the reload timer or PWC timer is started in 32-bit mode under control of the even-numbered channel,
the timer/counter of the even-numbered channel operates as the lower 16-bit timer/counter and the timer/
counter of the odd-numbered channel operates as the upper 16-bit one.
In 32-bit mode, the base timer follows the settings for the even-numbered channel while ignoring those for
the odd-numbered channel (except the period setting register when serving as the reload timer). Even for
the timer start, waveform output, and interrupt signal settings, the even-numbered channel overrides the
odd-numbered channel (odd-numbered channel is always masked at "L").
The following example shows a PWC configuration using ch.0 and ch.1.
ch. 1
Underflow
Overflow
ch.0
Interrupt
Upper 16-bit
timer/counter
Upper 16-bit
reload value
T32=0
336
Underflow
Overflow
Lower 16-bit
timer/counter
Waveform output
Read/write signals
Lower 16-bit
reload value
PWC measured waveform/
external trigger
T32=1
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
CHAPTER 12 BASE TIMER
12.6 Notes of Using the Base Timer
MB91490 Series
12.6
Notes of Using the Base Timer
This section summarizes the notes on using the base timer.
■ Common Notes on Using Each Type of Timer
● Notes on setting through programming
• The following bits in the BTnTMCR register must not be updated during operation. Be sure to update
them before starting the base timer or after stopping it.
[bit14, bit13, bit12] CKS2, CKS1, CKS0 : Clock select bits
[bit10, bit9, bit8]
EGS2, EGS1, EGS0
: Measurement edge select bits
[bit7]
T32
: 32-bit timer select bit
(Used with the reload timer or PWC timer selected)
[bit6, bit5,bit4]
FMD2, FMD1, FMD0 : Timer function mode select bits
[bit2]
MDSE
: Measurement mode (one-shot/continuous) select bit
• If you set the FMD2, FMD1, and FMD0 bits in the BTnTMCR register to "000B" to enter the reset
mode, all the registers of the base timer are initialized and thus they must be set all over again.
• If you set the FMD2, FMD1, and FMD0 bits in the BTnTMCR register to "000B" to enter the reset
mode, the other bits in the BTnTMCR register are initialized with their settings ignored.
■ Notes on Using the 16-bit PWM/PPG/Reload Timer
● Notes on setting through programming
• When the interrupt request flag is attempted to be set and cleared at the same timing, the flag set action
overrides the flag clear action.
• When the down counter is attempted to load and count at the same timing, the load action overrides the
count action.
• Set the FMD2, FMD1, and FMD0 bits in the BTnTMCR register to select the timer function mode
before setting the period, duty cycle, "H" width, and "L" width.
• If a restart is detected when counting is completed in one-shot mode, the counter is restarted with the
count value reloaded.
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CHAPTER 12 BASE TIMER
12.6 Notes of Using the Base Timer
MB91490 Series
■ Notes on Using the PWC Timer
● Notes on setting through programming
• Writing "1" to the counting enable bit (CTEN) clears the counter, nullifying the data existing in the
counter before counting is enabled.
• If you set the PWC mode (FMD = 100B) after a system reset or in reset mode and enables measurement
(CTEN = 1) at the same time, the timer may operate according to the immediately preceding
measurement signal.
• If a measurement start edge is detected the moment a restart is set in continuous measurement mode, the
timer immediately starts counting from "0001H".
• An attempt to restart the timer after starting counting can result as follows, depending on that timing:
- If the attempt is made at a measurement end edge in one-shot pulse width measurement mode:
Although the timer is restarted and waits for an measurement start edge, the measurement end flag
(EDIR) is set.
- If the attempt is made at a measurement end edge in continuous pulse width measurement mode:
Although the timer is restarted and waits for a measurement start edge, the measurement end flag
(EDIR) is set and the current measurement result is transferred to the BTnDTBF register.
When restarting the timer during operation, control interrupts while paying attention to the behaviors of
flags.
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CHAPTER 12 BASE TIMER
12.7 Base Timer Interrupts
MB91490 Series
12.7
Base Timer Interrupts
This section lists the interrupt request flags, interrupt enable bits, and interrupt factors
for the base timer in each timer function mode.
■ Interrupt Control Bits and Interrupt Factors by Timer Function Mode
Table 12.7-1 lists the interrupt control bits and interrupt factors for the base timer in each timer function
mode.
Table 12.7-1 Interrupt Control Bits and Interrupt Factors in Each Timer Function Mode
Status control register (BTnSTC)
Interrupt request flag bits
Interrupt request enable
bits
Interrupt factors
UDIR: bit0
UDIE: bit4
Underflow detection
DTIR: bit1
DTIE: bit5
Duty match detection
TGIR: bit2
TGIE: bit6
Timer start trigger detection
IRQ1
PPG timer
function
UDIR: bit0
UDIE: bit4
Underflow detection
IRQ0
TGIR: bit2
TGIE: bit6
Timer start trigger detection
IRQ1
Reload timer
function
UDIR: bit0
UDIE: bit4
Underflow detection
IRQ0
TGIR: bit2
TGIE: bit6
Timer start trigger detection
IRQ1
PWC timer
function
OVIR: bit0
OVIE: bit4
Overflow detection
IRQ0
EDIR: bit2
EDIE: bit6
Measurement end detection
IRQ1
PWM timer
function
CM71-10155-2E
IRQ
IRQ0
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CHAPTER 12 BASE TIMER
12.8 Base Timer Description by Function Mode
12.8
MB91490 Series
Base Timer Description by Function Mode
This section describes each function of the base timer.
■ Base Timer Function
• PWM function
• PPG function
• Reload timer function
• PWC function
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12.8 Base Timer Description by Function Mode
MB91490 Series
12.8.1
PWM Function
The base timer can assign itself, according to the settings of the FMD2, FMD1, and
FMD0 bits in its timer control register, to serve as only one of the 16-bit PWM timer, 16bit PPG timer, 16/32-bit reload timer, and 16/32-bit PWC timer. This section describes
the functions of the base timer assigned as the PWM timer.
• Timer Control Register (BTnTMCR) for PWM Timer
• PWM Period Setting Register (BTnPCSR)
• PWM Duty Setting Register (BTnPDUT)
• Timer Register (BTnTMR)
• 16-bit PWM Timer Operation
• One-shot Operation
• Interrupt Factors and Timing Chart
• Output Waveforms
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12.8 Base Timer Description by Function Mode
MB91490 Series
Timer Control Register (BTnTMCR) for PWM Timer
12.8.1.1
The timer control register (BTnTMCR) controls the PWM timer. Keep in mind that the
register contains bits which cannot be updated with the PWM timer operating.
■ Timer Control Register (BTnTMCR Upper Byte)
Figure 12.8-1 Timer Control Register (BTnTMCR Upper Byte)
Address
ch.0: 000162H
ch.1: 000582H
bit15
bit14
bit13
bit12
bit11
bit10
-
CKS2
R/W
CKS1
R/W
CKS0 RTGEN PMSK
R/W
R/W
R/W
EGS1 EGS0
: Readable/writable
: Undefined bit
: Initial value
342
bit8
EGS1
R/W
EGS0
R/W
Initial value:
-0000000B (At reset)
Trigger input edge select bits
0
0
Disable trigger input
0
1
Rising edge
1
0
Falling edge
1
1
Both edges
PMSK
Pulse output mask bit
0
Normal output
1
Fixed to "L"-level output
RTGEN
Restart enable bit
0
Disables restarting
1
Enable restarting
CKS2 CKS1 CKS0
R/W
-
bit9
Count clock select bits
0
0
0

0
0
1
/4
0
1
0
/16
0
1
1
/128
1
0
0
/256
1
0
1
1
1
0
1
1
1
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CHAPTER 12 BASE TIMER
12.8 Base Timer Description by Function Mode
MB91490 Series
Table 12.8-1 Timer Control Register (BTnTMCR Upper Byte)
Bit name
Function
• The read value of this bit is undefined.
bit15
Undefined bit
bit14
to
bit12
CKS2, CKS1, CKS0:
Count clock select
bits
• The count clock promptly reflects any changes made to its setting. CKS2 to
CKS0 must therefore be updated while counting is stopped (CTEN = 0). Note,
however, that you can change their setting at the same time as writing "1" to the
CTEN bit.
bit11
RTGEN:
Restart enable bit
Enables restarting with a software trigger or trigger input.
• Write to this bit takes no effect.
• Select the count clock for the 16-bit down counter.
• Controls the PWM output waveform level.
• When this bit is "0", the PWM waveform is output as it is.
bit10
PMSK:
Pulse output mask bit
• When the bit is "1", the PWM output is masked to the "L" level irrespective of
the period and duty cycle.
Note:
Setting the PMSK bit to "1" with the OSEL bit (bit3) set for inverted output
masks the PWM output to the "H" level.
• Select the effective edge of the input waveform as an external trigger to set the
trigger condition.
bit9,
bit8
EGS1, EGS0:
Trigger input edge
select bits
• When these bits are set to the initial value or "00B", no effective edge of the
input waveform is selected, preventing the timer from being triggered by the
external waveform.
Note:
Writing "1" to the STRG bit enables the software trigger irrespective of the
settings of EGS1 and EGS0.
• EGS1 and EGS0 must be updated while counting is stopped (CTEN = 0). Note,
however, that you can change their setting at the same time as writing "1" to the
CTEN bit.
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CHAPTER 12 BASE TIMER
12.8 Base Timer Description by Function Mode
MB91490 Series
■ Timer Control Register (BTnTMCR Lower Byte)
Figure 12.8-2 Timer Control Register (BTnTMCR Lower Byte)
Address
bit7
ch.0: 000163H
ch.1: 000583H
R/W
bit6
bit5
FMD2 FMD1
R/W
R/W
bit4
bit3
bit2
FMD0
OSEL
MDSE
R/W
R/W
R/W
: Readable/writable
: Undefined bit
: Initial value
344
bit0
CTEN STRG
R/W
R/W
Initial value:
00000000B (At reset)
STRG
Software trigger bit
0
Disable software trigger
1
Start with software trigger
CTEN
Counting enable bit
0
Disables counting
1
Enables counting
MDSE
Mode select bit
0
Continuous operation
1
One-shot operation
OSEL
Output polarity select bit
0
Normal polarity
1
Inverted polarity
FMD2 FMD1 FMD0
R/W
-
bit1
Timer function select bits
0
0
0
Reset mode
0
0
1
Selects PWM function mode
0
1
0
Selects PPG function mode
0
1
1
Selects reload timer function mode
1
0
0
Selects PWC function mode
1
0
1
1
1
0
1
1
1
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CHAPTER 12 BASE TIMER
12.8 Base Timer Description by Function Mode
MB91490 Series
Table 12.8-2 Timer Control Register (BTnTMCR Lower Byte)
Bit name
bit7
Undefined bit
bit6
to
bit4
FMD2, FMD1,
FMD0:
Timer function select
bits
Function
• The value read is "0"
• When writing to this bit, write "0".
• These bits select the timer function mode.
• Setting the FMD2, FMD1, and FMD0 bits to "001B" selects the PWM function
mode.
• The setting must be changed with the timer stopped (CTEN = 0). Note, however,
that you can change the setting at the same time as writing "1" to the CTEN bit.
Selects the polarity of PWM output.
bit3
OSEL:
Output polarity select
bit
bit2
MDSE:
Mode select bit
bit1
CTEN:
Counting enable bit
Polarity
After reset
Normal
"L" output
Inverted
"H" output
Duty match
Underflow
• Selects continuous pulse output or one-shot pulse output.
• The setting must be changed with the timer stopped (CTEN = 0). Note, however,
that you can change the setting at the same time as writing "1" to the CTEN bit.
• This bit enables the down counter.
• Writing "0" to the CTEN bit with the counter enabled (CTEN = 1) stops the
counter.
• Writing "1" to the STRG bit with the CTEN bit containing "1" generates a
software trigger.
bit0
STRG:
Software trigger bit
Note:
Writing "1" to the CTEN and STRG bits at the same time also generates a
software trigger.
• The value read from the STRG bit is always "0".
Note:
Writing "1" to the STRG bit enables the software trigger irrespective of the
settings of the EGS1 and EGS0 bits.
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CHAPTER 12 BASE TIMER
12.8 Base Timer Description by Function Mode
MB91490 Series
■ Status Control Register (BTnSTC)
Figure 12.8-3 Status Control Register (BTnSTC)
Address
ch.0: 000165H
ch.1: 000585H
R/W
-
346
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
-
TGIE
DTIE
UDIE
-
TGIR
DTIR
UDIR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
: Readable/writable
: Undefined bit
: Initial value
Initial value:
00000000B (At reset)
UDIR
Underflow interrupt request bit
0
Clears interrupt factor
1
Indicates that interrupt factor has been detected
DTIR
Duty match interrupt request bit
0
Clears interrupt factor
1
Indicates that interrupt factor has been detected
TGIR
Trigger interrupt request bit
0
Clears interrupt factor
1
Indicates that interrupt factor has been detected
UDIE
Underflow interrupt request enable bit
0
Disables interrupt requests
1
Enables interrupt requests
DTIE
Duty match interrupt request enable bit
0
Disables interrupt requests
1
Enables interrupt requests
TGIE
Trigger interrupt request enable bit
0
Disables interrupt requests
1
Enables interrupt requests
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CHAPTER 12 BASE TIMER
12.8 Base Timer Description by Function Mode
MB91490 Series
Table 12.8-3 Status Control Register (BTnSTC)
Bit name
Function
• The value read is "0"
bit7
Undefined bit
TGIE:
Trigger interrupt
request enable bit
• Controls bit2: TGIR interrupt requests.
bit6
• Controls bit1: DTIR interrupt requests.
bit5
DTIE:
Duty match interrupt
request enable bit
• Controls bit0: UDIR interrupt requests.
bit4
UDIE:
Underflow interrupt
request enable bit
bit3
Undefined bit
• When writing to this bit, write "0".
• Setting the TGIR bit (bit2) with the TGIE bit enabling trigger interrupt requests
generates an interrupt request to the CPU.
• Setting the DTIR bit (bit1) with the DTIE bit enabling duty match interrupt
requests generates an interrupt request to the CPU.
• Setting the UDIR bit (bit0) with the UDIE bit enabling underflow interrupt
requests generates an interrupt request to the CPU.
• The value read is "0"
• When writing to this bit, write "0".
• The TGIR bit is set to "1" upon detection of a software trigger or trigger input.
bit2
TGIR:
Trigger interrupt
request bit
• Writing "0" to the TGIR bit clears it.
• Writing "1" to the TGIR bit has no effect on the bit value.
• When read by a read modify write (RMW) instruction, the bit always returns "1"
irrespective of the current bit value.
• The DTIR bit is set to "1" when the count value matches the duty cycle setting.
bit1
bit0
DTIR:
Duty match interrupt
request bit
UDIR:
Underflow interrupt
request bit
• Writing "0" to the DTIR bit clears it.
• Writing "1" to the DTIR bit has no effect on the bit value.
• When read by a read modify write (RMW) instruction, the bit always returns "1"
irrespective of the current bit value.
• The UDIR bit is set to "1" when a count value underflow occurs from 0000H to
FFFFH.
• Writing "0" to the UDIR bit clears it.
• Writing "1" to the UDIR bit has no effect on the bit value.
• When read by a read modify write (RMW) instruction, the bit always returns "1"
irrespective of the current bit value.
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CHAPTER 12 BASE TIMER
12.8 Base Timer Description by Function Mode
MB91490 Series
PWM Period Setting Register (BTnPCSR)
12.8.1.2
The PWM period setting register (BTnPCSR) is a buffered register for setting the PWM
period. Transfer to the timer register takes place when the counter is started and when
it causes an underflow.
■ Bit Configuration of the PWM Period Setting Register (BTnPCSR)
Figure 12.8-4 shows the bit configuration of the PWM period setting register (BTnPCSR).
Figure 12.8-4 Bit Configuration of the PWM Period Setting Register (BTnPCSR)
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
ch.0: 000168H
ch.1: 000588H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value:
XXXXXXXXB (At reset)
Initial value:
XXXXXXXXB (At reset)
R/W : Readable/writable
X
: Undefined value
The BTnPCSR register is a buffered register for setting the PWM period. Transfer to the timer register
takes place when the counter is started and when it causes an underflow.
After writing to the period setting register to initially set or update it, be sure to write to the duty setting
register.
• Access the BTnPCSR register using 16-bit data.
• Set the PWM period using the BTnPCSR register after selecting the PWM function mode using the
FMD2, FMD1, and FMD0 bits in the BTnTMCR register.
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CHAPTER 12 BASE TIMER
12.8 Base Timer Description by Function Mode
MB91490 Series
12.8.1.3
PWM Duty Setting Register (BTnPDUT)
The PWM duty setting register (BTnPDUT) is a buffered register for setting the PWM
duty cycle. Transfer from the buffer takes place when an underflow occurs.
■ Bit Configuration of the PWM Duty Setting Register (BTnPDUT)
Figure 12.8-5 shows the bit configuration of the PWM duty setting register (BTnPDUT).
Figure 12.8-5 Bit Configuration of the PWM Duty Setting Register (BTnPDUT)
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
ch.0: 00016AH
ch.1: 00058AH
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value:
XXXXXXXXB (At reset)
Initial value:
XXXXXXXXB (At reset)
R/W : Readable/writable
X
: Undefined value
The BTnPDUT register is a buffered register for setting the PWM duty cycle. Transfer from the buffer
takes place when an underflow occurs.
If you set the period setting and duty setting registers to the same value, the output level is all "H" in
normal polarity or all "L" in inverted polarity.
Do not set the BTnPDUT register to a value greater than the value of the BTnPCSR register, or PWM
output will be undefined.
• Access the BTnPDUT register using 16-bit data.
• Set the PWM duty cycle using the BTnPDUT register after selecting the PWM function mode using the
FMD2, FMD1, and FMD0 bits in the BTnTMCR register.
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CHAPTER 12 BASE TIMER
12.8 Base Timer Description by Function Mode
12.8.1.4
MB91490 Series
Timer Register (BTnTMR)
The timer register (BTnTMR) allows the value of the 16-bit down counter to be read from.
■ Bit Configuration of the Timer Register (BTnTMR)
Figure 12.8-6 shows the bit configuration of the PWM timer register (BTnTMR).
Figure 12.8-6 Bit Configuration of the Timer Register (BTnTMR)
Address
ch.0: 000160H
ch.1: 000580H
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
R
R
R
R
R
R
R
R
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
R
R
R
R
R
R
R
R
R
Initial value:
00000000B (At reset)
Initial value:
00000000B (At reset)
: Read only
The BTnTMR register allows the value of the 16-bit down counter to be read from.
Note:
Access the BTnTMR register using 16-bit data.
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CHAPTER 12 BASE TIMER
12.8 Base Timer Description by Function Mode
MB91490 Series
12.8.1.5
16-bit PWM Timer Operation
In PWM timer mode, a waveform having a specified period can be output either in single
shots or continuously after detection of a trigger.
The period of output pulses can be controlled by changing the BTnPCSR value.
The duty ratio can be controlled by changing the BTnPDUT value. After writing data to
the BTnPCSR register, be sure to write to the BTnPDUT register as well.
■ Continuous Operation
● When restarting is disabled (RTGEN = 0)
Figure 12.8-7 PWM Operation Timing Chart (Restarting Disabled)
Rising edge detected
Trigger is ignored.
Trigger
m
n
0
PWM
output
waveform
(1)
(2)
(1) = T(n+1) ms
(2) = T(m+1) ms
T : Count clock cycle
m : BTnPCSR value
n : BTnPDUT value
● When restarting is enabled (RTGEN = 1)
Figure 12.8-8 PWM Operation Timing Chart (Restarting Enabled)
Rising edge detected
Restarted by trigger
Trigger
m
n
0
PWM output
waveform
(1)
(2)
(1) = T(n+1) ms
(2) = T(m+1) ms
CM71-10155-2E
T : Count clock cycle
m : BTnPCSR value
n : BTnPDUT value
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CHAPTER 12 BASE TIMER
12.8 Base Timer Description by Function Mode
12.8.1.6
MB91490 Series
One-shot Operation
In one-shot operation mode, single pulses with an arbitrary width can be output by
trigger. When restarting is enabled, the counter is reloaded upon detection of a trigger
edge during operation.
■ One-shot Operation
● When restarting is disabled (RTGEN = 0)
Figure 12.8-9 One-shot Operation Timing Chart (Trigger Restarting Disabled)
Rising edge detected
Trigger is ignored.
Trigger
m
n
0
PWM output
waveform
(1)
(2)
(1) = T(n+1) ms
(2) = T(m+1) ms
T : Count clock cycle
m : BTnPCSR value
n : BTnPDUT value
● When restarting is enabled (RTGEN = 1)
Figure 12.8-10 One-shot Operation Timing Chart (Trigger Restarting Enabled)
Rising edge detected
Restarted by trigger
Trigger
m
n
0
PWM output
waveform
(1)
(2)
(1) = T(n+1) ms
(2) = T(m+1) ms
352
T : Count clock cycle
m : BTnPCSR value
n : BTnPDUT value
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CHAPTER 12 BASE TIMER
12.8 Base Timer Description by Function Mode
MB91490 Series
12.8.1.7
Interrupt Factors and Timing Chart
This section provides the interrupt factors and timing chart.
■ Interrupt Factors and Timing Chart (PWM Output: Normal Polarity)
A software trigger requires T and an external trigger requires 2T to 3T (T: peripheral clock (CLKP) cycle)
until the counter value is loaded after the input of the trigger.
Figure 12.8-11 shows the interrupt factors and timing chart, assuming "period setting" = 3 and "duty value"
= 1.
Figure 12.8-11 PWM Timer Interrupt Factors and Timing Chart
Trigger
2T to 3T (external trigger)
Load
Count clock
Count value
XXXXH
0003H
0002H
0001H
0000H
0003H
0002H
PWM output waveform
Interrupt
Start edge
TGIR
CM71-10155-2E
Duty match
DTIR
FUJITSU SEMICONDUCTOR LIMITED
Underflow
UDIR
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CHAPTER 12 BASE TIMER
12.8 Base Timer Description by Function Mode
12.8.1.8
MB91490 Series
Output Waveforms
This section illustrates PWM output.
■ PWM Output at All "L" or All "H" Level
Figure 12.8-12 and Figure 12.8-13 illustrate how to provide PWM output at all "L" and all "H" levels,
respectively.
Figure 12.8-12 Example of PWM Output at All "L" Level
Underflow interrupt
Duty value
0002H
0001H
0000H
XXXXH
PWM output waveform
Decrease the
duty value.
Use the underflow interrupt to set PMSK to "1".
The output waveform has all "L" level from the
current period.
Figure 12.8-13 Example of PWM Output at All "H" Level
Duty match interrupt
PWM output
waveform
Increase the
duty value.
Use the duty match interrupt to set the duty value
to the same as the period setting, and the output
waveform has all "H" level in the next period.
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CHAPTER 12 BASE TIMER
12.8 Base Timer Description by Function Mode
MB91490 Series
12.8.2
PPG Function
The base timer can assign itself, according to the settings of the FMD2, FMD1, and
FMD0 bits in its timer control register, to serve as only one of the 16-bit PWM timer, 16bit PPG timer, 16/32-bit reload timer, and 16/32-bit PWC timer. This section describes
the functions of the base timer assigned as the PPG timer.
• Timer Control Register (BTnTMCR) for PPG Timer
• "L"-width Setting Reload Register (BTnPRLL)
• "H"-width Setting Reload Register (BTnPRLH)
• Timer Register (BTnTMR)
• 16-bit PPG Timer Operation
• Continuous Operation
• One-shot Operation
• Interrupt Factors and Timing Chart
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12.8 Base Timer Description by Function Mode
MB91490 Series
Timer Control Register (BTnTMCR) for PPG Timer
12.8.2.1
The timer control register (BTnTMCR) controls the PPG timer. Keep in mind that the
register contains bits which cannot be updated with the PPG timer operating.
■ Timer Control Register (BTnTMCR Upper Byte)
Figure 12.8-14 Timer Control Register (BTnTMCR Upper Byte)
Address
ch.0: 000162H
ch.1: 000582H
bit15
bit14
bit13
bit12
bit11
bit10
-
CKS2
R/W
CKS1
R/W
CKS0 RTGEN PMSK
R/W
R/W
R/W
EGS1 EGS0
0
bit9
bit8
EGS1
R/W
EGS0
R/W
Trigger input edge select bits
0
Disable trigger input
0
1
Rising edge
1
0
Falling edge
1
1
Both edges
PMSK
Pulse output mask bit
0
Normal output
1
Fixed to "L"-level output
RTGEN
Restart enable bit
0
Disables restarting
1
Enable restarting
CKS2 CKS1 CKS0
R/W
-
356
Initial value:
-0000000B (At reset)
Count clock select bits

0
0
0
0
0
1
/4
0
1
0
/16
0
1
1
/128
1
0
0
/256
: Readable/writable
: Undefined bit
1
0
1
1
1
0
: Initial value
1
1
1
FUJITSU SEMICONDUCTOR LIMITED
Setting not allowed
CM71-10155-2E
CHAPTER 12 BASE TIMER
12.8 Base Timer Description by Function Mode
MB91490 Series
Table 12.8-4 Timer Control Register (BTnTMCR Upper Byte)
Bit name
bit15
Undefined bit
bit14
to
bit12
CKS2, CKS1,
CKS0:
Count clock select
bits
bit11
RTGEN:
Restart enable bit
Function
• The read value of this bit is undefined.
• Write to this bit takes no effect.
• Select the count clock for the 16-bit down counter.
• The count clock promptly reflects any changes made to its setting.
CKS2 to CKS0 must therefore be updated while counting is stopped (CTEN =
0). Note, however, that you can change their setting at the same time as writing
"1" to the CTEN bit.
This bit enables restarting with a software trigger or trigger input.
• Controls the PPG output waveform level.
• When this bit is "0", the PPG waveform is output as it is.
bit10
PMSK:
Pulse output mask bit
• When the bit is "1", the PPG output is masked to the "L" level irrespective of the
"H" and "L" width settings.
Note:
Setting the PMSK bit to "1" with the OSEL bit (bit3) set for inverted output
masks the PPG output to the "H" level.
• Select the effective edge of the input waveform as an external trigger to set the
trigger condition.
bit9,
bit8
EGS1, EGS0:
Trigger input edge
select bits
• When these bits are set to the initial value or "00B", no effective edge of the
input waveform is selected, preventing the timer from being triggered by the
external waveform.
Note:
Writing "1" to the STRG bit enables the software trigger irrespective of the
settings of EGS1 and EGS0.
• EGS1 and EGS0 must be updated while counting is stopped (CTEN = 0). Note,
however, that you can change their setting at the same time as writing "1" to the
CTEN bit.
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CHAPTER 12 BASE TIMER
12.8 Base Timer Description by Function Mode
MB91490 Series
■ Timer Control Register (BTnTMCR Lower Byte)
Figure 12.8-15 Timer Control Register (BTnTMCR Lower Byte)
Address
ch.0: 000163H
ch.1: 000583H
bit7
bit6
bit5
bit4
bit3
bit2
-
FMD2
FMD1
FMD0
OSEL
MDSE
R/W
R/W
R/W
R/W
R/W
R/W
: Readable/writable
: Undefined bit
bit0
CTEN STRG
R/W
R/W
Initial value:
00000000B (At reset)
STRG
Software trigger bit
0
Disable software trigger
1
Start with software trigger
CTEN
Counting enable bit
0
Disables counting
1
Enables counting
MDSE
Mode select bit
0
Continuous operation
1
One-shot operation
OSEL
Output polarity select bit
0
Normal polarity
1
Inverted polarity
FMD2 FMD1 FMD0
R/W
-
bit1
Timer function select bits
0
0
0
Reset mode
0
0
1
Select PWM function mode
0
1
0
Select PPG function mode
0
1
1
Select reload timer function mode
1
0
0
Select PWC function mode
1
0
1
1
1
0
1
1
1
Setting not allowed
: Initial value
358
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CHAPTER 12 BASE TIMER
12.8 Base Timer Description by Function Mode
MB91490 Series
Table 12.8-5 Timer Control Register (BTnTMCR Lower Byte)
Bit name
bit7
Undefined bit
bit6
to
bit4
FMD2, FMD1,
FMD0:
Timer function select
bits
Function
• The value read is "0"
• When writing to this bit, write "0".
• These bits select the timer function mode.
• Setting the FMD2, FMD1, and FMD0 bits to "010B" selects the PPG function
mode.
• The setting must be changed with the timer stopped (CTEN = 0). Note, however,
that you can change the setting at the same time as writing "1" to the CTEN bit.
• Selects the polarity of PPG output.
bit3
OSEL:
Output polarity select
bit
bit2
MDSE:
Mode select bit
bit1
CTEN:
Counting enable bit
Polarity
After reset
Normal
"L" output
Inverted
"H" output
End of "L"-width
counting
End of "H"-width
counting
• Selects continuous pulse output or one-shot pulse output.
• The setting must be changed with the timer stopped (CTEN = 0). Note, however,
that you can change the setting at the same time as writing "1" to the CTEN bit.
• This bit enables the down counter.
• Writing "0" to the CTEN bit with the counter enabled (CTEN = 1) stops the
counter.
• Writing "1" to the STRG bit with the CTEN bit containing "1" generates a
software trigger.
bit0
STRG:
Software trigger bit
Note:
Writing "1" to the CTEN and STRG bits at the same time also generates a
software trigger.
• The value read from the STRG bit is always "0".
Note:
Writing "1" to the STRG bit enables the software trigger irrespective of the
settings of the EGS1 and EGS0 bits.
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CHAPTER 12 BASE TIMER
12.8 Base Timer Description by Function Mode
MB91490 Series
■ Status Control Register (BTnSTC)
Figure 12.8-16 Status Control Register (BTnSTC)
Address:
ch.0 000165H
ch.1 000585H
R/W
-
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
-
TGIE
-
UDIE
-
TGIR
-
UDIR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
: Readable/writable
: Undefined bit
: Initial value
360
Initial value:
00000000B (At reset)
UDIR
Underflow interrupt request bit
0
Clears interrupt factor
1
Indicates that interrupt factor has been detected
TGIR
Trigger interrupt request bit
0
Clears interrupt factor
1
Indicates that interrupt factor has been detected
UDIE
Underflow interrupt request enable bit
0
Disables interrupt requests
1
Enables interrupt requests
TGIE
Trigger interrupt request enable bit
0
Disables interrupt requests
1
Enables interrupt requests
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
CHAPTER 12 BASE TIMER
12.8 Base Timer Description by Function Mode
MB91490 Series
Table 12.8-6 Status Control Register (BTnSTC)
Bit name
bit7
Undefined bit
bit6
TGIE:
Trigger interrupt
request enable bit
bit5
Undefined bit
bit4
UDIE:
Underflow interrupt
request enable bit
bit3
Undefined bit
Function
• The value read is "0"
• When writing to this bit, write "0".
• Controls bit2: TGIR interrupt requests.
• Setting the TGIR bit (bit2) with the TGIE bit enabling trigger interrupt requests
generates an interrupt request to the CPU.
• The value read is "0"
• When writing to this bit, write "0".
• Controls bit0: UDIR interrupt requests.
• Setting the UDIR bit (bit0) with the UDIE bit enabling underflow interrupt
requests generates an interrupt request to the CPU.
• The value read is "0"
• When writing to this bit, write "0".
• The TGIR bit is set to "1" upon detection of a software trigger or trigger input.
bit2
bit1
bit0
TGIR:
Trigger interrupt
request bit
Undefined bit
UDIR:
Underflow interrupt
request bit
• Writing "0" to the TGIR bit clears it.
• Writing "1" to the TGIR bit has no effect on the bit value.
• When read by a read modify write (RMW) instruction, the bit always returns "1"
irrespective of the current bit value.
• The value read is "0"
• When writing to this bit, write "0".
• The UDIR bit is set to "1" when a count value underflow occurs from 0000H to
FFFFH during counting from the value set as the "H" width.
• Writing "0" to the UDIR bit clears it.
• Writing "1" to the UDIR bit has no effect on the bit value.
• When read by a read modify write (RMW) instruction, the bit always returns "1"
irrespective of the current bit value.
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CHAPTER 12 BASE TIMER
12.8 Base Timer Description by Function Mode
12.8.2.2
MB91490 Series
"L"-width Setting Reload Register (BTnPRLL)
The "L"-width setting reload register (BTnPRLL) is used to set the "L" width of PPG
output waveforms. Transfer to the timer register takes place upon detection of a start
trigger or when an underflow occurs at the end of "H"-width counting.
■ Bit Configuration of the "L"-width Setting Reload Register (BTnPRLL)
Figure 12.8-17 shows the bit configuration of the "L"-width setting reload register (BTnPRLL).
Figure 12.8-17 Bit Configuration of the "L"-width Setting Reload Register (BTnPRLL)
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
ch.0: 000168H
ch.1: 000588H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value:
XXXXXXXXB (At reset)
Initial value:
XXXXXXXXB (At reset)
R/W : Readable/writable
X
: Undefined value
The BTnPRLL register is used to set the "L" width of PPG output waveforms. Transfer to the timer register
takes place upon detection of a start trigger or when an underflow occurs at the end of "H"-width counting.
• Access the BTnPRLL register using 16-bit data.
• Set the "L" width using the BTnPRLL register after selecting the PPG function mode using the FMD2,
FMD1, and FMD0 bits in the BTnTMCR register.
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CHAPTER 12 BASE TIMER
12.8 Base Timer Description by Function Mode
MB91490 Series
12.8.2.3
"H"-width Setting Reload Register (BTnPRLH)
The "H"-width setting reload register (BTnPRLH) is a buffered register for setting the
"H" width of PPG output waveforms. Transfer from the BTnPRLH register to the buffer
register takes place upon detection of a start trigger or when an underflow occurs at the
end of "H"-width counting. Transfer from the buffer register to the timer register takes
place when an underflow occurs at the end of "L" width counting.
■ Bit Configuration of the "H"-width Setting Reload Register (BTnPRLH)
Figure 12.8-18 shows the bit configuration of the "H"-width setting reload register (BTnPRLH).
Figure 12.8-18 Bit Configuration of the "H"-width Setting Reload Register (BTnPRLH)
Address
bit15
ch.0: 00016AH
ch.1: 00058AH
bit14
bit13
bit12
bit11
bit10
bit9
bit8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value:
XXXXXXXXB (At reset)
Initial value:
XXXXXXXXB (At reset)
R/W : Readable/writable
X
: Undefined value
The BTnPRLH register is used to set the "H" width of PPG output waveforms. Transfer from the
BTnPRLH register to the buffer register takes place upon detection of a start trigger or when an underflow
occurs at the end of "H"-width counting. Transfer from the buffer register to the timer register takes place
when an underflow occurs at the end of "L" width counting.
• Access the BTnPRLH register using 16-bit data.
• Set the "H" width using the BTnPRLH register after selecting the PPG function mode using the FMD2,
FMD1, and FMD0 bits in the BTnTMCR register.
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CHAPTER 12 BASE TIMER
12.8 Base Timer Description by Function Mode
12.8.2.4
MB91490 Series
Timer Register (BTnTMR)
The timer register (BTnTMR) allows the value of the 16-bit down counter to be read from.
■ Bit Configuration of the Timer Register (BTnTMR)
Figure 12.8-19 shows the bit configuration of the PPG timer register (BTnTMR).
Figure 12.8-19 Bit Configuration of the Timer Register (BTnTMR)
Address
ch.0: 000160H
ch.1: 000580H
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
R
R
R
R
R
R
R
R
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
R
R
R
R
R
R
R
R
R
Initial value:
00000000B (At reset)
Initial value:
00000000B (At reset)
: Read only
The BTnTMR register allows the value of the 16-bit down counter to be read from.
Note:
Access the BTnTMR register using 16-bit data.
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CHAPTER 12 BASE TIMER
12.8 Base Timer Description by Function Mode
MB91490 Series
12.8.2.5
16-bit PPG Timer Operation
In PPG timer mode, an arbitrary output pulse can be controlled by setting its "L" and
"H" widths in their respective reload registers.
■ Principles of Operation
The PPG timer has two 16-bit reload registers for setting the "L" and "H" widths respectively and one "H"
width setting buffer (BTnPRLL, BTnPRLH, PRLHB).
In response to the start trigger, the 16-bit down counter loads the BTnPRLL value and the BTnPRLH value
is transferred to the BTnPRLHB buffer at the same time. The counter is decremented every count clock
with the PPG output at the "L" level. When an underflow is detected, the counter reloads the BTnPRLHB
value and is decremented with the PPG output waveform inverted. When an underflow is detected again,
the PPG output waveform is inverted, the counter reloads the BTnPRLL set value, and the BTnPRLH set
value is transferred to the BTnPRLHB buffer.
Through these steps, the output waveform becomes the pulse output with the "L" and "H" widths
corresponding to their respective reload register values.
■ Reload Register Write Timing
Data is written to the BTnPRLL and BTnPRLH reload registers upon detection of a start trigger and
between when the underflow interrupt request bit (UDIR) is set and when the next period begins. The data
set then becomes the setting for the next period. The BTnPRLL and BTnPRLH settings are automatically
transferred to the BTnTMR and BTnPRLHB, respectively, upon detection of a start trigger and when an
underflow occurs at the end of "H" width counting. The data transferred to the BTnPRLHB is automatically
reloaded to the BTnTMR when an underflow occurs at the end of "L" width counting.
Rising edge detected
Trigger
IRQ1 (TGIR source)
IRQ0 (UDIR source)
Set the L width and H width of the next cycle to registers.
BTnPRLL
L0
L1
L2
L3
BTnPRLH
H0
H1
H2
H3
BTnPRLHB
xxxx
BTnTMR
xxxx
H1
H0
L0 to 0000
H2
H0 to
0000
L1 to 0000
H1 to
0000
H0
L1
H1
L2 to 0000
H2 to
0000
PPG output waveforms
L0
CM71-10155-2E
FUJITSU SEMICONDUCTOR LIMITED
L2
H2
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CHAPTER 12 BASE TIMER
12.8 Base Timer Description by Function Mode
12.8.2.6
MB91490 Series
Continuous Operation
In continuous operation mode, an arbitrary pulse can be output continuously by
updating the "L" and "H" widths at the set timing of each interrupt. When restarting is
enabled, the counter is reloaded upon detection of a trigger edge during operation.
■ Continuous Operation
● When restarting is disabled (RTGEN = 0)
Figure 12.8-20 PPG Operation Timing Chart (Restarting Disabled)
Rising edge detected
Trigger is ignored.
Trigger
m
n
0
PPG output waveform
(1)
(2)
Interrupt
Start edge
TGIR
Underflow
UDIR
Underflow
UDIR
(1) = T(m+1) ms
(2) = T(n+1) ms
T : Count clock cycle
m : BTnPRLL value
n : BTnPRLH value
● When restarting is enabled (RTGEN = 1)
Figure 12.8-21 PPG Operation Timing Chart (Restarting Enabled)
Rising edge detected
Restarted by trigger
Trigger
m
n
0
PPG output waveform
(2)
(1) = T(m+1) ms
(2) = T(n+1) ms
366
(1)
T : Count clock cycle
m : BTnPRLL value
n : BTnPRLH value
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CHAPTER 12 BASE TIMER
12.8 Base Timer Description by Function Mode
MB91490 Series
12.8.2.7
One-shot Operation
In one-shot operation mode, single pulses with an arbitrary width can be output by
trigger. When restarting is enabled, the counter is reloaded upon detection of a trigger
edge during operation.
■ One-shot Operation
● When restarting is disabled (RTGEN = 0)
Figure 12.8-22 One-shot Operation Timing Chart (Trigger Restarting Disabled)
Rising edge detected
Trigger is ignored.
Trigger
m
n
0
PPG output waveform
(1)
(2)
(1) = T(m+1) ms
(2) = T(n+1) ms
T : Count clock cycle
m : BTnPRLL value
n : BTnPRLH value
● When restarting is enabled (RTGEN = 1)
Figure 12.8-23 One-shot Operation Timing Chart (Trigger Restarting Enabled)
Rising edge detected
Restarted by trigger
Trigger
m
n
0
PPG output waveform
(1)
(2)
(1) = T(m+1) ms
(2) = T(n+1) ms
CM71-10155-2E
T : Count clock cycle
m : BTnPRLL value
n : BTnPRLH value
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CHAPTER 12 BASE TIMER
12.8 Base Timer Description by Function Mode
MB91490 Series
■ Relationship between Reload Value and Pulse Width
The output pulse width is obtained by adding 1 to the value written in the 16-bit reload register and
multiplying the result by the count clock cycle. When the reload register value is 0000H, therefore, the
output has a pulse width of one count clock cycle. When the reload register value is FFFFH, the output has
a pulse width of 65536 count clock cycles. The pulse width is calculated from the following equation.
PL = T  (L+1)
PH = T  (H+1)
PL : "L" pulse width
PH : "H" pulse width
T
: Count clock cycle
L
: BTnPRLL value
H : BTnPRLH value
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CHAPTER 12 BASE TIMER
12.8 Base Timer Description by Function Mode
MB91490 Series
12.8.2.8
Interrupt Factors and Timing Chart
This section provides the interrupt factors and timing chart.
■ Interrupt Factors and Timing Chart (PPG Output: Normal Polarity)
A software trigger requires T and an external trigger requires 2T to 3T (T: peripheral clock (CLKP) cycle)
until the counter value is loaded after the trigger is generated.
Interrupt factors are set when the PPG start trigger is detected and when an underflow is detected during
"H" level output.
Figure 12.8-24 shows the interrupt factors and timing chart, assuming "L" width setting = 1 and "H" width
setting = 1.
Figure 12.8-24 PPG Timer Interrupt Factors and Timing Chart
Trigger
2T to 3T (external trigger)
Load
Count clock
Count value
XXXXH
0001H
0000H
0001H
0000H
0001H
0000H
PPG output waveform
Interrupt
Start edge
TGIR
CM71-10155-2E
Underflow
UDIR
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CHAPTER 12 BASE TIMER
12.8 Base Timer Description by Function Mode
12.8.3
MB91490 Series
Reload Timer Function
The base timer can assign itself, according to the settings of the FMD2, FMD1, and
FMD0 bits in its timer control register, to serve as only one of the 16-bit PWM timer, 16bit PPG timer, 16/32-bit reload timer, and 16/32-bit PWC timer. This section describes
the functions of the base timer assigned as the reload timer.
• Timer Control Register (BTnTMCR) for Reload Timer
• Period Setting Register (BTnPCSR)
• Timer Register (BTnTMR)
• 16-bit Reload Timer Operation
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CHAPTER 12 BASE TIMER
12.8 Base Timer Description by Function Mode
MB91490 Series
12.8.3.1
Timer Control Register (BTnTMCR) for Reload Timer
The timer control register (BTnTMCR) controls the reload timer.
■ Timer Control Register (BTnTMCR Upper Byte)
Figure 12.8-25 Timer Control Register (BTnTMCR Upper Byte)
Address
ch.0: 000162H
ch.1: 000582H
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
-
CKS2
R/W
CKS1
R/W
CKS0
R/W
-
-
EGS1
R/W
EGS0
R/W
EGS1 EGS0
0
Trigger edge select bits
0
Disable trigger input
0
1
External trigger (rising edge)
1
0
External trigger (falling edge)
1
1
External trigger (both edges)
CKS2 CKS1 CKS0
R/W
-
Initial value:
-0000000B (At reset)
Count clock select bits

0
0
0
0
0
1
/4
0
1
0
/16
0
1
1
/128
1
0
0
/256
: Readable/writable
: Undefined bit
1
0
1
1
1
0
: Initial value
1
1
1
CM71-10155-2E
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Setting not allowed
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CHAPTER 12 BASE TIMER
12.8 Base Timer Description by Function Mode
MB91490 Series
Table 12.8-7 Timer Control Register (BTnTMCR Upper Byte)
Bit name
bit15
Undefined bit
bit14
to
bit12
CKS2, CKS1,
CKS0:
Count clock select
bits
bit11,
bit10
Undefined bits
Function
• The read value of this bit is undefined.
• Write to this bit takes no effect.
• Select the count clock for the 16-bit down counter.
• The count clock promptly reflects any changes made to its setting. CKS2 to
CKS0 must therefore be updated while counting is stopped (CTEN = 0). Note,
however, that you can change their setting at the same time as writing "1" to the
CTEN bit.
• The value read is "0"
• When writing to these bits, write "0".
• Select the effective edge of the input waveform as an external trigger to set the
trigger condition.
bit9,
bit8
EGS1, EGS0:
Trigger edge select
bits
• When these bits are set to the initial value or "00B", no effective edge of the
input waveform is selected, preventing the timer from being triggered by the
external waveform.
Note:
Writing "1" to the STRG bit enables the software trigger irrespective of the
settings of EGS1 and EGS0.
• EGS1 and EGS0 must be updated while counting is stopped (CTEN = 0). Note,
however, that you can change their setting at the same time as writing "1" to the
CTEN bit.
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CHAPTER 12 BASE TIMER
12.8 Base Timer Description by Function Mode
MB91490 Series
■ Timer Control Register (BTnTMCR Lower Byte)
Figure 12.8-26 Timer Control Register (BTnTMCR Lower Byte)
Address
bit7
ch.0: 000163H
ch.1: 000583H
T32
R/W
bit6
bit5
bit4
FMD2 FMD1 FMD0
R/W
R/W
R/W
bit3
bit2
OSEL
R/W
MDSE
R/W
bit1
bit0
CTEN STRG
R/W
R/W
STRG
Software trigger bit
0
Disable software trigger
1
Start with software trigger
CTEN
Counting enable bit
0
Disables counting
1
Enables counting
MDSE
Mode select bit
0
Reload mode
1
One-shot mode
OSEL
Output polarity select bit
0
Normal polarity
1
Inverted polarity
FMD2 FMD1 FMD0
R/W
: Readable/writable
: Initial value
CM71-10155-2E
Initial value:
00000000B (At reset)
Timer function select bits
0
0
0
Reset mode
0
0
1
Select PWM function mode
0
1
0
Select PPG function mode
0
1
1
Select reload timer function mode
1
0
0
Select PWC function mode
1
0
1
1
1
0
1
1
1
Setting not allowed
T32
32-bit timer select bit
0
16-bit timer mode
1
32-bit timer mode
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CHAPTER 12 BASE TIMER
12.8 Base Timer Description by Function Mode
MB91490 Series
Table 12.8-8 Timer Control Register (BTnTMCR Lower Byte)
Bit name
Function
• This bit selects the 32-bit timer mode.
bit7
T32:
32-bit timer select bit
bit6
to
bit4
FMD2, FMD1,
FMD0:
Timer function select
bits
• When the FMD2, FMD1, and FMD0 bits contain "011B" to select the reload
timer, setting the T32 bit to "1" places the timer in 32-bit timer mode.
• The setting must be changed with the timer stopped (CTEN = 0). Note, however,
that you can change the setting at the same time as writing "1" to the CTEN bit.
 See Section "12.5 32-bit Mode Operations".
• These bits select the timer function mode.
• Setting the FMD2, FMD1, and FMD0 bits to "011B" selects the reload timer
function mode.
• The setting must be changed with the timer stopped (CTEN = 0). Note, however,
that you can change the setting at the same time as writing "1" to the CTEN bit.
• Selects the timer output at normal level or inverted level.
• The output waveform is generated as follows depending on the combination with
the MDSE bit (bit2):
bit3
bit2
OSEL:
Output polarity select
bit
MDSE:
Mode select bit
MDSE
OSEL
Output Waveforms
0
0
Toggle output of "L" at the count start
0
1
Toggle output of "H" at the count start
1
0
Rectangular wave of "H" during count
1
1
Rectangular wave of "L" during count
• Setting the MDSE bit to "0" selects reload mode, in which the counter loads the
reload register value to continue counting the moment a count value underflow
occurs from 0000H to FFFFH.
• Setting the MDSE bit to "1" selects one-shot mode, in which the counter stops
operation the moment a count value underflow occurs from 0000H to FFFFH.
• The setting must be changed with the timer stopped (CTEN = 0). Note, however,
that you can change the setting at the same time as writing "1" to the CTEN bit.
bit1
CTEN:
Counting enable bit
• This bit enables the down counter.
• Writing "0" to the CTEN bit with the counter enabled (CTEN = 1) stops the
counter.
• Writing "1" to the STRG bit with the CTEN bit containing "1" generates a
software trigger.
bit0
STRG:
Software trigger bit
Note:
Writing "1" to the CTEN and STRG bits at the same time also generates a
software trigger.
• The value read from the STRG bit is always "0".
Note:
Writing "1" to the STRG bit enables the software trigger irrespective of the
settings of the EGS1 and EGS0 bits.
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CHAPTER 12 BASE TIMER
12.8 Base Timer Description by Function Mode
MB91490 Series
■ Status Control Register (BTnSTC)
Figure 12.8-27 Status Control Register (BTnSTC)
Address:
ch.0 000165H
ch.1 000585H
R/W
-
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
-
TGIE
-
UDIE
-
TGIR
-
UDIR
-
R/W
-
R/W
-
R/W
-
R/W
: Readable/writable
: Undefined bit
: Initial value
CM71-10155-2E
Initial value:
00000000B (At reset)
UDIR
Underflow interrupt request bit
0
Clears interrupt factor
1
Indicates that interrupt factor has been detected
TGIR
Trigger interrupt request bit
0
Clears interrupt factor
1
Indicates that interrupt factor has been detected
UDIE
Underflow interrupt request enable bit
0
Disables interrupt requests
1
Enables interrupt requests
TGIE
Trigger interrupt request enable bit
0
Disables interrupt requests
1
Enables interrupt requests
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12.8 Base Timer Description by Function Mode
MB91490 Series
Table 12.8-9 Status Control Register (BTnSTC)
Bit name
bit7
Undefined bit
bit6
TGIE:
Trigger interrupt
request enable bit
bit5
Undefined bit
bit4
UDIE:
Underflow interrupt
request enable bit
bit3
Undefined bit
Function
• The value read is "0"
• When writing to this bit, write "0".
• Controls bit2:TGIR interrupt requests.
• Setting the TGIR bit (bit2) with the TGIE bit enabling trigger interrupt requests
generates an interrupt request to the CPU.
• The value read is "0"
• When writing to this bit, write "0".
• Controls bit0:UDIR interrupt requests.
• Setting the UDIR bit (bit0) with the UDIE bit enabling underflow interrupt
requests generates an interrupt request to the CPU.
• The value read is "0"
• When writing to this bit, write "0".
• The TGIR bit is set to "1" upon detection of a software trigger or trigger input.
bit2
bit1
bit0
TGIR:
Trigger interrupt
request bit
Undefined bit
UDIR:
Underflow interrupt
request bit
• Writing "0" to the TGIR bit clears it.
• Writing "1" to the TGIR bit has no effect on the bit value.
• When read by a read modify write (RMW) instruction, the bit always returns "1"
irrespective of the current bit value.
• The value read is "0"
• When writing to this bit, write "0".
• The UDIR bit is set to "1" when a count value underflow occurs from 0000H to
FFFFH.
• Writing "0" to the UDIR bit clears it.
• Writing "1" to the UDIR bit has no effect on the bit value.
• When read by a read modify write (RMW) instruction, the bit always returns "1"
irrespective of the current bit value.
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CHAPTER 12 BASE TIMER
12.8 Base Timer Description by Function Mode
MB91490 Series
12.8.3.2
Period Setting Register (BTnPCSR)
The period setting register (BTnPCSR) holds the initial count value. In 32-bit mode, the
register holds the initial count value of the lower 16 bits for the even-numbered channel
or the initial count value of the upper 16 bits for the odd-numbered channel. The initial
value immediately after a reset is undefined. To access this register, be sure to use a
16-bit data transfer instruction.
■ Bit Configuration of the Period Setting Register (BTnPCSR)
Figure 12.8-28 shows the bit configuration of the period setting register (BTnPCSR).
Figure 12.8-28 Bit Configuration of the Period Setting Register (BTnPCSR)
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
ch.0: 000168H
ch.1: 000588H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value:
XXXXXXXXB (At reset)
Initial value:
XXXXXXXXB (At reset)
R/W : Readable/writable
X
: Undefined value
The BTnPCSR register is used to set the period. Transfer to the timer register takes place when an
underflow occurs.
• Access the BTnPCSR register using 16-bit data.
• Set the period using the BTnPCSR register after selecting the reload timer function mode using the
FMD2, FMD1, and FMD0 bits in the BTnTMCR register.
• To write data to the BTnPCSR register in 32-bit mode, access its upper 16-bit data (data for the oddnumbered channel) first and then the lower 16-bit data (data for the even-numbered channel).
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CHAPTER 12 BASE TIMER
12.8 Base Timer Description by Function Mode
12.8.3.3
MB91490 Series
Timer Register (BTnTMR)
The timer register (BTnTMR) allows the count value of the timer to be read from. In 32-bit
mode, the register holds the count value of the lower 16 bits for the even-numbered channel
or the count value for the upper 16 bits for the odd-numbered channel. The initial value is
undefined.
To read this register, be sure to use a 16-bit data transfer instruction.
■ Bit Configuration of the Timer Register (BTnTMR)
Figure 12.8-29 shows the bit configuration of the timer register (BTnTMR).
Figure 12.8-29 Bit Configuration of the Timer Register (BTnTMR)
Address
ch.0: 000160H
ch.1: 000580H
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
R
R
R
R
R
R
R
R
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
R
R
R
R
R
R
R
R
Initial value:
00000000B (At reset)
Initial value:
00000000B (At reset)
R : Read only
The BTnTMR register allows the value of the 16-bit down counter to be read from.
Notes:
• Access the BTnTMR register using 16-bit data.
• To read data from the BTnTMR register in 32-bit mode, access its lower 16-bit data (data for the
even-numbered channel) first and then the upper 16-bit data (data for the odd-numbered
channel).
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CHAPTER 12 BASE TIMER
12.8 Base Timer Description by Function Mode
MB91490 Series
12.8.3.4
16-bit Reload Timer Operation
In reload timer mode, the timer decrements the counter from the value set in the period
setting register in synchronization with the count clock, and finishes counting when the
count value reaches "0" or continues operation with the period setting loaded
automatically until the counter stops being decremented.
■ Counting with the Internal Clock Selected
To start counting the moment counting is enabled, write "1" to both of the CTEN and STRG bits in the
timer control register. The STRG bit maintains the trigger input always enabled irrespective of the
operation mode as long as the timer is active (CNTE = 1).
Enable counting and start the timer using a software trigger or external trigger, and the timer loads the
period setting register value to the counter to start decrementing the counter.
It takes 1T (T: peripheral clock (CLKP) cycle) for data in the period setting register to be loaded into the
counter after the counter start trigger is set.
Figure 12.8-30 illustrates how the counter is started by the software trigger and operates.
Figure 12.8-30 Counting with the Internal Clock Selected
Load
Count clock
Count value
XXXXH
Reload value
-1
-1
CTEN
1T
STRG
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12.8 Base Timer Description by Function Mode
MB91490 Series
■ Underflow Operation
When the counter value changes from "0000H" to "FFFFH", the transition is detected as an underflow.
When the counter counts [period setting register value + 1], therefore, an underflow occurs.
When an underflow occurs, the content of the period setting register (BTnPCSR) is loaded into the counter,
and the counter continues counting if the MDSE bit in the timer control register (BTnTMCR) is "0". If the
MDSE bit is "1", the counter stops operation with the loaded counter value left unchanged.
When an underflow occurs, the UDIR bit in the status control register (BTnSTC) is set and an interrupt
request occurs if the UDIE bit is "1".
Figure 12.8-31 is a timing chart of underflow operation.
Figure 12.8-31 Underflow Operation Timing Chart
[MDSE=0]
Load
Count clock
Count value
0000H
Reload value
-1
-1
Underflow set
UDIR
[MDSE=1]
Load
Count clock
Count value
0000H
Reload value
Underflow set
UDIR
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CHAPTER 12 BASE TIMER
12.8 Base Timer Description by Function Mode
MB91490 Series
■ Input Pin Operation
The TIN pin can be used as a trigger input. When the effective edge is input to the TIN pin, the counter
loads the content of the period setting register and starts counting. It takes 2T or 3T (T: peripheral clock
(CLKP) cycle) for the counter value to be loaded after the trigger is applied.
Figure 12.8-32 illustrates the trigger input operation with the rising edge selected as the effective edge.
Figure 12.8-32 Trigger Input Operation
TIN
2T to 3T (External trigger)
Load
Count clock
Count value
0000H
-1
Reload value
-1
■ Output Pin Operation
The TOUT pin functions as a toggle output to be inverted at each underflow in reload mode and as a pulse
output to indicate that counting is in process in one-shot mode. The output polarity can be set by the OSEL
bit in the timer control register (BTnTMCR). When the OSEL bit is "0", the initial value of the toggle
output is "0" and that of the one-shot pulse output is "1" (indicating that counting is in process). Setting the
OSEL bit to "1" inverts the output waveform.
Figure 12.8-33 is a timing chart of output pin operation.
Figure 12.8-33 Output Pin Operation Timing Chart
[MDSE=0, OSEL=0]
CTEN
Inverted with OSEL = 1
TOUT
Trigger
Underflow
[MDSE=1, OSEL=0]
CTEN
Inverted with OSEL = 1
TOUT
Trigger
Underflow
Waiting fro trigger start
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CHAPTER 12 BASE TIMER
12.8 Base Timer Description by Function Mode
12.8.4
MB91490 Series
PWC Function
The base timer can assign itself, according to the settings of the FMD2, FMD1, and
FMD0 bits in its timer control register, to serve as only one of the 16-bit PWM timer, 16bit PPG timer, 16/32-bit reload timer, and 16/32-bit PWC timer. This section describes
the functions of the base timer assigned as the PWC timer.
• Timer Control Register (BTnTMCR) for PWC Timer
• Data Buffer Register (BTnDTBF)
• PWC Operation
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12.8 Base Timer Description by Function Mode
MB91490 Series
12.8.4.1
Timer Control Register (BTnTMCR) for PWC Timer
The timer control register (BTnTMCR) controls the PWC timer.
■ Timer Control Register (BTnTMCR Upper Byte)
Figure 12.8-34 Timer Control Register (BTnTMCR Upper Byte)
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
ch.0: 000162H
ch.1: 000582H
R/W
CKS2
R/W
CKS1
R/W
CKS0
R/W
R/W
EGS2
R/W
EGS1
R/W
EGS0
R/W
EGS2 EGS1 EGS0
0
0
Measurement edge select bits
0
Measure "H" pulse width ( to )
0
0
1
Measure period between rising edges
( to )
0
1
0
Measure period between falling edges
( to )
0
1
1
Measure pulse widths between all edges
( or  to  or )
1
0
0
Measure "L" pulse width ( to )
1
0
1
1
1
0
1
1
1
CKS2 CKS1 CKS0
R/W
-
: Readable/writable
: Undefined bit
: Initial value
CM71-10155-2E
Initial value:
00000000B (At reset)
Setting not allowed
Count clock select bits
0
0
0

0
0
1
/4
0
1
0
/16
0
1
1
/128
1
0
0
/256
1
0
1
1
1
0
1
1
1
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Setting not allowed
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CHAPTER 12 BASE TIMER
12.8 Base Timer Description by Function Mode
MB91490 Series
Table 12.8-10 Timer Control Register (BTnTMCR Upper Byte)
Bit name
bit15
Undefined bit
bit14
to
bit12
CKS2, CKS1,
CKS0:
Count clock select
bits
bit11
Undefined bit
bit10
to
bit8
EGS2, EGS1, EGS0:
Measurement edge
select bits
384
Function
• The value read is "0"
• When writing to this bit, write "0".
• Select the count clock for the 16-bit up counter.
• The count clock promptly reflects any changes made to its setting. CKS2 to
CKS0 must therefore be updated while counting is stopped (CTEN = 0). Note,
however, that you can change their setting at the same time as writing "1" to the
CTEN bit.
• The value read is "0"
• When writing to this bit, write "0".
• Set the measurement edge condition.
• EGS2, EGS1, and EGS0 must be updated while counting is stopped (CTEN = 0).
Note, however, that you can change their setting at the same time as writing "1"
to the CTEN bit.
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CHAPTER 12 BASE TIMER
12.8 Base Timer Description by Function Mode
MB91490 Series
■ Timer Control Register (BTnTMCR Lower Byte)
Figure 12.8-35 Timer Control Register (BTnTMCR Lower Byte)
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ch.0: 000163H
ch.1: 000583H
T32
R/W
FMD2
R/W
FMD1
R/W
FMD0
R/W
R/W
MDSE
CTEN
R/W
R/W
R/W
CTEN
Counting enable bit
0
Halt
1
Enables operation
MDSE
Mode select bit
0
Continuous measurement mode
1
One-shot measurement mode
FMD2 FMD1 FMD0
0
R/W
-
: Readable/writable
: Undefined bit
: Initial value
CM71-10155-2E
Initial value:
00000000B (At reset)
0
Timer function mode select bits
0
Reset mode
0
0
1
PWM function mode
0
1
0
PPG function mode
0
1
1
Reload timer function mode
1
0
0
PWC function mode
1
0
1
1
1
0
1
1
1
Setting not allowed
T32
32-bit timer select bit
0
16-bit timer mode
1
32-bit timer mode
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12.8 Base Timer Description by Function Mode
MB91490 Series
Table 12.8-11 Timer Control Register (BTnTMCR Lower Byte)
Bit name
Function
• This bit selects the 32-bit timer mode.
bit7
T32:
32-bit timer select bit
bit6
to
bit4
FMD2, FMD1,
FMD0:
Timer function mode
select bits
bit3
Undefined bit
• When the FMD2, FMD1, and FMD0 bits contain "100B" to select the PWC
timer, setting the T32 bit to "1" places the timer in 32-bit PWC mode.
• The setting must be changed with the timer stopped (CTEN = 0). Note, however,
that you can change the setting at the same time as writing "1" to the CTEN bit.
 See Section "12.5 32-bit Mode Operations".
• These bits select the timer function mode.
• Setting the FMD2, FMD1, and FMD0 bits to "100B" selects the PWC timer
function mode.
• The setting must be changed with the timer stopped (CTEN = 0). Note, however,
that you can change the setting at the same time as writing "1" to the CTEN bit.
• The value read is "0"
• When writing to this bit, write "0".
• Selects measurement mode as follows.
MDSE
bit2
MDSE:
Mode select bit
0
1
Mode
Continuous measurement
One-shot measurement
Operation
Continuous measurement: buffer
register enabled
Halts after each measurement
• The setting must be changed with the timer stopped (CTEN = 0). Note, however,
that you can change the setting at the same time as writing "1" to the CTEN bit.
• This bit enables the starting or restarting of the up counter.
bit1
CTEN:
Counting enable bit
• Writing "1" to this bit with the counter enabled for operation (CTEN bit = 1)
causes a restart, resulting in the counter cleared and waiting for the measurement
start edge.
• Writing "0" to the bit with the counter enabled for operation (CTEN bit = 1 stops
the counter.
bit0
386
Undefined bit
• The value read is "0"
• When writing to this bit, write "0".
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CHAPTER 12 BASE TIMER
12.8 Base Timer Description by Function Mode
MB91490 Series
■ Status Control Register (BTnSTC)
Figure 12.8-36 Status Control Register (BTnSTC)
Address:
ch.0 000165H
ch.1 000585H
R/W
-
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ERR
EDIE
-
OVIE
-
EDIR
-
OVIR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
: Readable/writable
: Undefined bit
Initial value:
00000000B (At reset)
OVIR
Overflow interrupt request bit
0
Clears interrupt request
1
Indicates that interrupt factor has been detected
EDIR
Measurement end interrupt request bit
0
Reads measurement result (PWCR)
1
Indicates that interrupt factor has been detected
OVIE
Overflow interrupt request enable bit
0
Disables interrupt requests
1
Enables interrupt requests
EDIE
Measurement end interrupt request enable bit
0
Disables interrupt requests
1
Enables interrupt requests
ERR
Error flag bit
0
Normal state
1
Unread measurement result has been overwritten with
next measurement result
: Initial value
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12.8 Base Timer Description by Function Mode
MB91490 Series
Table 12.8-12 Status Control Register (BTnSTC)
Bit name
bit7
ERR:
Error flag bit
Function
• This flag indicates that the next measurement has been completed before reading
the current measurement result from the BTnDTBF register in continuous
measurement mode. In this case, the BTnDTBF register is updated with the new
measurement result, discarding the preceding measurement result.
• Measurement continues irrespective of the ERR bit value.
• The ERR bit can only be read; an attempt to write to it has no effect on the bit
value.
• The ERR bit is cleared by reading the measurement result (BTnDTBF).
bit6
EDIE:
Measurement end
interrupt request
enable bit
bit5
Undefined bit
bit4
OVIE:
Overflow interrupt
request enable bit
bit3
Undefined bit
bit2
bit1
EDIR:
Measurement end
interrupt request bit
Undefined bit
• Controls bit2: EDIR interrupt requests.
• Setting the EDIR bit (bit2) with the EDIE bit enabling measurement end
interrupt requests generates an interrupt request to the CPU.
• The value read is "0"
• When writing to this bit, write "0".
• Controls bit0: OVIR interrupt requests.
• Setting the OVIR bit (bit0) with the OVIE bit enabling overflow interrupt
requests generates an interrupt request to the CPU.
• The value read is "0"
• When writing to this bit, write "0".
• Indicates that measurement has been completed. The flag is set to "1" upon
completion.
• The EDIR bit is cleared by reading the measurement result (BTnDTBF).
• The EDIR bit can only be read; an attempt to write to it has no effect on the bit
value.
• The value read is "0"
• When writing to this bit, write "0".
• The flag is set to "1" when a count value overflow occurs from FFFFH to 0000H.
bit0
388
OVIR:
Overflow interrupt
request bit
• Writing "0" to the OVIR bit clears it.
• Writing "1" to the OVIR bit has no effect on the bit value.
• When read by a read modify write (RMW) instruction, the bit always returns "1"
irrespective of the current bit value.
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CHAPTER 12 BASE TIMER
12.8 Base Timer Description by Function Mode
MB91490 Series
12.8.4.2
Data Buffer Register (BTnDTBF)
The data buffer register (BTnDTBF) allows the measured value or count value of the
PWC timer to be read from. In 32-bit mode, the register holds the value of the lower 16
bits for the even-numbered channel or the value of the upper 16 bits for the oddnumbered channel.
To read this register, be sure to use a 16-bit data transfer instruction.
■ Bit Configuration of the Data Buffer Register (BTnDTBF)
Figure 12.8-37 shows the bit configuration of the data buffer register (BTnDTBF).
Figure 12.8-37 Bit Configuration of the Data Buffer Register (BTnDTBF)
Address
ch.0: 00016AH
ch.1: 00058AH
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
R
R
R
R
R
R
R
R
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
R
R
R
R
R
R
R
R
Initial value:
XXXXXXXXB (At reset)
Initial value:
XXXXXXXXB (At reset)
R : Read only
• The BTnDTBF register can only be read in both of the continuous and one-shot measurement modes.
An attempt to write to the register makes no change to the register value.
• In continuous measurement mode (BTnTMCR: bit3 MDSE = 1), the BTnDTBF register serves as a
buffer register holding the preceding measurement result.
• In one-shot measurement mode (BTnTMCR: bit3 MDSE = 0), the BTnDTBF register directly accesses
the up counter. Even during counting, the count value can be read from this register. When the
measurement is completed, the register preserved the measurement result as it is.
• Access the BTnDTBF register using 16-bit data.
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CHAPTER 12 BASE TIMER
12.8 Base Timer Description by Function Mode
12.8.4.3
MB91490 Series
PWC Operation
The PWC timer has a pulse width measurement feature, capable of selecting the count
clock from among five types and measuring the time between arbitrary events of the
input pulse and their cycle. The following outlines the basic functions and operations of
the pulse width measurement feature.
■ Pulse Width Measurement Feature
When started, the timer clears the counter to "0000H" but does not perform counting until the pre-set
measurement start edge is input. Upon detection of the measurement start edge, the timer increments the
counter from "0001H". Upon detection of the measurement end edge, the timer stops the counter. The timer
saves the count value between the two events as the pulse width to the register.
An interrupt request can be generated upon completion of measurement or when an overflow occurs.
After measurement, the timer acts as follows depending on the measurement mode:
• In one-shot measurement mode:
The timer stops operation.
• In continuous measurement mode: The timer transfers the counter value to the buffer register and stops
counting until the measurement start edge is input again.
Figure 12.8-38 Pulse Width Measurement Operation
(One-shot Measurement Mode/"H" Width Measurement)
PWC input measured pulse
CTEN
Count value
FFFFH
Count
cleared
0000H
Start
triggered
Counting
stopped
(Solid line indicates count values.)
Counting 0001H
started
Time
EDIR flag set (Measurement completed)
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CHAPTER 12 BASE TIMER
12.8 Base Timer Description by Function Mode
MB91490 Series
Figure 12.8-39 Pulse Width Measurement Operation
(Continuous Measurement Mode/"H" Width Measurement)
PWC input measured pulse
CTEN
(Solid line indicates
count values.)
Count value
FFFFH
Overflow
Data transfer to BTnDTBF
Data transfer to BTnDTBF
Count
cleared
0000H
Start
triggered
Counting
stopped
Counting
stopped
Counting 0001H
started
Counting 0001H
restarted
Counting
continued
Time
EDIR flag set (Measurement completed)
OVIR flag set
EDIR flag set
■ Selecting the Count Clock
The count clock for the counter can be selected from among five types, depending on the settings of the
CKS2 (bit6), CKS1 (bit5), and CKS0 (bit4) in the BTnTMCR registers.
The following count clocks can be selected:
BTnTMCR Register
Internal count clock selected
CKS2, CKS1, CKS0 bits
000B
Peripheral clock (CLKP) [Initial value]
001B
Peripheral clock (CLKP) divided by 4
010B
Peripheral clock (CLKP) divided by 16
011B
Peripheral clock (CLKP) divided by 128
100B
Peripheral clock (CLKP) divided by 256
101B
110B
Setting not allowed
111B
The initial value immediately after a reset selects the peripheral clock (CLKP).
Note: Be sure to select the count clock before starting the counter.
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12.8 Base Timer Description by Function Mode
MB91490 Series
■ Selecting the Operation Mode
Operation and measurement modes are selected depending on their settings in the BTnTMCR register.
Operation mode setting . . . . . . BTnTMCR bit10 to bit8: EGS2, EGS1. EGS0
(Selecting the measurement edge)
Measurement mode setting . . . BTnTMCR bit2: MDSE
(Selecting one-shot/continuous measurement)
Listed below are the selectable operation modes and their respective bit settings.
Operation mode
 to  "H" pulse width
measurement
 to  measurement of period
between rising edges
 to  measurement of period
between falling edges
 or  to  or  measurement
between all edges
 to  "L" pulse width
measurement
MDSE
EGS2
EGS1
EGS0
Continuous measurement:
Buffer enabled
0
0
0
0
One-shot measurement:
Buffer disabled
1
0
0
0
Continuous measurement:
Buffer enabled
0
0
0
1
One-shot measurement:
Buffer disabled
1
0
0
1
Continuous measurement:
Buffer enabled
0
0
1
0
One-shot measurement:
Buffer disabled
1
0
1
0
Continuous measurement:
Buffer enabled
0
1
1
1
One-shot measurement:
Buffer disabled
1
1
1
1
Continuous measurement:
Buffer enabled
0
1
0
0
One-shot measurement:
Buffer disabled
1
1
0
0
0
1
0
1
1
1
0
1
0
1
1
0
1
1
1
0
0
1
1
1
1
1
1
1
Setting not allowed
The initial value immediately after a reset selects "H" pulse width/one-shot measurement mode.
Be sure to select the operation mode before starting the counter.
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12.8 Base Timer Description by Function Mode
MB91490 Series
■ Starting and Stopping Pulse Width Measurement
Each type of measurement can be started, restarted, and aborted by the CTEN bit (bit1) in the BTnTMCR
register.
You can start/restart pulse width measurement by writing "1" to the CTEN bit. You can abort it by writing
"0" to the CTEN bit.
CTEN
Function
1
Starts/restarts pulse width measurement
0
Aborts pulse width measurement
■ Operation after being Started
The timer operation after the pulse width measurement mode has been started does not start counting until
the measurement start edge is input. Upon detection of the measurement start edge, the 16-bit up counter
starts counting from "0001H".
■ Restarting
Restarting the timer means starting the timer during operation again while it has already been started (by
writing "1" again to the CTEN bit already containing "1"). When restarted, the timer behaves as follows:
• If restarted the timer waiting for the measurement start edge: No effect on its operation.
• If restarted during measurement: The timer clears the counter to "0000H" and waits for the measurement
start edge again. If the restart and measurement end edge detection
occur at the same time, the measurement end flag (EDIR) is set. In
continuous measurement mode, the measurement result is transferred
to the BTnDTBF register.
■ Stopping
In one-shot measurement mode, the timer stops counting automatically when the counter causes an
overflow or when measurement is completed, requiring no special attention. To stop the timer either in
continuous measurement mode or before it stops automatically, you have to abort it.
■ Clearing the Counters and Their Initial Values
The 16-bit up counter is cleared to "0000H" when:
• a reset occurs
• "1" is written to the CTEN bit (bit1) in the BTnTMCR register (including the case of restarting).
The 16-bit up counter is initialized to "0001H" when:
• measurement start edge is detected.
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12.8 Base Timer Description by Function Mode
MB91490 Series
■ Details of Pulse Width Measurement Operation
● One-shot measurement and continuous measurement
There are two modes of pulse width measurement: one is to perform measurement only once and the other
is to perform measurement continuously. Each mode is selected by using the MDSE bit in the BTnTMCR
register (see "■ Selecting the Operation Mode" in "12.8.4.3 PWC Operation"). The two modes have the
following differences:
One-shot measurement mode:
When the measurement end edge is input once, the counter stops counting and the measurement end
flag (EDIR) in the BTnSTC register is set, finishing the current measurement session. If the counter is
restarted at the same time, however, it waits for the measurement start edge.
Continuous measurement mode:
When the measurement end edge is input, the counter stops counting, the measurement end flag (EDIR)
in the BTnSTC register is set, and the counter remains idle until the measurement start edge is input
again. Next time the measurement start edge is input, the counter is initialized to "0001H" to start
measurement. Upon completion of measurement, the measurement result in the counter is transferred to
the BTnDTBF register.
Be sure to select or change the measurement mode with the counter stopped.
● Measurement result data
The one-shot measurement and continuous measurement modes are different in the handling of
measurement results and counter values and the BTnDTBF function. The differences in measurement
results between the two modes are as follows:
One-shot measurement mode:
When the BTnDTBF register is read during operation, the count value being measured can be obtained.
When the BTnDTBF register is read after measurement is completed, measurement result data is
obtained.
Continuous measurement mode:
When measurement is completed, the measurement result in the counter is transferred to the BTnDTBF
register.
When the BTnDTBF register is read, the last measurement result is obtained. During measurement
operation, the BTnDTBF register holds the result of preceding measurement. The count value being
measured cannot be read.
If the current measurement is completed before the preceding measurement result is read in continuous
measurement mode, the preceding measurement result is overwritten by the new measurement result. In
this case, the error flag (ERR) in the BTnSTC register is set. The error flag (ERR) is cleared
automatically when the BTnDTBF register is read.
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12.8 Base Timer Description by Function Mode
MB91490 Series
■ Measurement Mode and Counting
Measurement mode can be selected from among five types, depending on what part of the input pulse is
measured. The following table summarizes each measurement mode and its target.
Measurement mode
EGS2, EGS1, EGS0
Measurement target (W: Pulse width to be measured)
W
"H" pulse width
measurement
000B
↑ Start
counting
001B
↑ Start
counting
W
W
Measure the period between rising edges.
Start counting (measurement) : upon detection of rising edge
Stop counting (measurement) : upon detection of rising edge
010B
↓ Start
counting
W
W
↓ Stop counting
↓ Start
↓ Stop
↓ Start
Measure the period between falling edges.
Start counting (measurement) : upon detection of falling edge
Stop counting (measurement) : upon detection of falling edge
W
Measurement of pulse
widths between all
edges
011B
↑ Start
counting
W
W
↓ Stop counting
↓ Start
↑ Stop
↑ Start
Measure the width between continuously input edges.
Start counting (measurement) : upon detection of edge
Stop counting (measurement) : upon detection of edge
W
W
Measurement of "L"
pulse width
↓
Stop
↑
Start
↑ Stop counting
↑ Start
W
Measurement of period
between falling edges
↓ Stop
counting
Measure the width of "H" period.
Start counting (measurement) : upon detection of rising edge
Stop counting (measurement) : upon detection of falling edge
W
Measurement of period
between rising edges
W
100B
↓ Start
counting
↑ Stop
counting
↓
Start
↑
Stop
Measure the width of the "L" period.
Start counting (measurement) : upon detection of falling edge
Stop counting (measurement) : upon detection of rising edge
In any measurement mode, the counter started for measurement is cleared to "0000H" and remains idle
without counting until the measurement start edge is input. When the measurement start edge is input, the
counter is incremented every count clock until the measurement end edge is input.
When measurement of pulse widths between all edges or period measurement is performed in continuous
measurement mode, the end edge becomes the next measurement start edge.
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CHAPTER 12 BASE TIMER
12.8 Base Timer Description by Function Mode
MB91490 Series
● Pulse width/period calculation method
The following equation can be used to calculate the measured pulse width/period from measurement result
data obtained from the BTnDTBF register after measurement is completed:
TW : Measured pulse width/period [ms]
TW = n  t [ms]
n
: Measurement result data in BTnDTBF
t
: Count clock cycle [ms]
● Generating interrupt requests
Interrupt requests can be generated in two ways.
• Interrupt request in response to counter overflow
When the counter is incremented to cause an overflow during measurement, the overflow flag (OVIR)
is set and generates an interrupt request if overflow interrupt requests have been enabled.
• Interrupt request upon completion of measurement
When the measurement end edge is detected, the measurement end flag (EDIR) in the BTnSTC register
is set and generates an interrupt request if measurement end interrupt requests have been enabled.
The measurement end flag (EDIR) is cleared automatically when the measurement result is read from
the BTnDTBF register.
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CHAPTER 12 BASE TIMER
12.8 Base Timer Description by Function Mode
MB91490 Series
■ Pulse Width Measurement Operation Flow
Various settings
Figure 12.8-40 Pulse Width Measurement Operation Flow
Select PWC mode
Select count clock
Select operation/
measurement modes
Clear interrupt flag
Enable interrupts
Start with CTEN bit
Restart
Clear counter
Continuous measurement
mode
One-shot measurement
mode
Measurement start edge
detected
Measurement start edge
detected
Start counting
Start counting
Increment
Increment
Overflow caused
 Set OVIR flag
Measurement end edge
detected
 Set EDIR flag
CM71-10155-2E
Overflow caused
 Set OVIR flag
Measurement end edge
detected
 Set EDIR flag
Stop counting
Stop counting
Transfer count value to
BTnDTBF
Stop operation
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12.8 Base Timer Description by Function Mode
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CHAPTER 13
UP/DOWN COUNTER
This chapter describes the function and operation of
8/16-bit up/down counter.
13.1 Overview of Up/Down Counter
13.2 Block Diagram of Up/Down Counter
13.3 Register of Up/Down Counter
13.4 Operation of Up/Down Counters
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13.1 Overview of Up/Down Counter
13.1
MB91490 Series
Overview of Up/Down Counter
The 8/16-bit up/down counter is the up/down counter/timer which consists of three
event input pins, 16-bit up/down counters, 16-bit reload/compare registers, and their
control circuits.
The operating mode can switch one channel of 8-bit counter or one channel of 16-bit by
setting.
■ Features of Up/Down Counter
• With the 16-bit count register, counting can be performed in a range between 0D to 65535D.
• The following four count modes can be selected for the count clock:
- Timer mode
- Up/down counter mode
- Phase difference count mode (multiply-by-2)
- Phase difference count mode (multiply-by-4)
• In timer mode, the count clock can be selected from two internal clocks and input from an internal
circuit.
Count clocks available for selection (for operation at 40MHz)
- 50ns (20MHz: divide-by-2)
- 200ns (5MHz: divide-by-8)
• The detection edge of the external pin input signal can be selected in up and in down counting mode.
- Detection of falling edge
- Detection of rising edge
- Detection of both rising and falling edges
- Edge detection disabled
• The phase difference counting mode is suitable for counting for an encoder, such as for a motor. Using
one of A phase output, B phase output, and Z phase output for the encoder as input allows to count
rotation angle and number of rotations easily and with high precision.
• Two different functions can be selected for the ZIN pin (this applies for all modes).
- Counter clear function
- Gate function
• The compare function and reload function are available. These functions can be used separately or
combined. By combining these functions, counting up or down can be performed with an arbitrary
width.
- Compare function (compare interrupt request output)
- Compare function (compare interrupt request output and counter clearing)
- Reload function (underflow interrupt request output and reloading)
- Compare and reload function (compare interrupt request output, counter clearing, underflow interrupt
request output, and reloading)
- Compare and reload disabled
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CHAPTER 13 UP/DOWN COUNTER
13.1 Overview of Up/Down Counter
• With the count direction flag, the counting direction immediately before the current count can be
identified.
• The generation of interrupts when a compare match occurs, at reload (underflow), at overflow, or when
the counting direction changes, can be controlled individually.
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13.2 Block Diagram of Up/Down Counter
13.2
MB91490 Series
Block Diagram of Up/Down Counter
This section explains the block diagram of up/down counter.
■ Block Diagram of Up/Down Counter
Figure 13.2-1 Block Diagram of Up/Down Counter
8/16-bit up/down counter/timer (ch.0)
Data bus
CGE1 CGE0 CGSC
ZIN0
8-bit
RCR00
(reload/compare register 0)
CTUT
Reload
control
UCRE
RLDE
Edge level detection
To ch.1
M16E
Carry
Counter
clear
UDCC
CES1 CES0
8-bit
UDCR00
(up/down count register 0)
CMS1 CMS0
CMPF
UDFF
AIN0
BIN0
Up/down
count clock
selection
Count
clock
CSTR
UDF1
OVFF
UDIE
UDF0 CDCF
Prescaler
CITE
CLKS
CFIE
Interrupt output
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CHAPTER 13 UP/DOWN COUNTER
13.3 Register of Up/Down Counter
MB91490 Series
13.3
Register of Up/Down Counter
The up/down counter has up/down count register (UDCR), reload compare register
(RCR), counter status register (CSR), and counter control register (CCR).
This section explains these registers.
■ List of Registers of Up/Down Counter
Figure 13.3-1 List of Registers of Up/Down Counter
UDCR10
Address
000542H
UDCR00
Address
000543H
RCR10
Address
000540H
RCR00
Address
000541H
CSR0
Address
000547H
CCRH0
Address
000544H
CCRL0
Address
000545H
bit15
D15
R
bit14
D14
R
bit13
D13
R
bit12
D12
R
bit11
D11
R
bit10
D10
R
bit9
D09
R
bit8
D08
R
Initial value
00000000B
bit7
D07
R
bit6
D06
R
bit5
D05
R
bit4
D04
R
bit3
D03
R
bit2
D02
R
bit1
D01
R
bit0
D00
R
Initial value
00000000B
bit15
D15
W
bit14
D14
W
bit13
D13
W
bit12
D12
W
bit11
D11
W
bit10
D10
W
bit9
D09
W
bit8
D08
W
Initial value
00000000B
bit7
D07
W
bit6
D06
W
bit5
D05
W
bit4
D04
W
bit3
D03
W
bit2
D02
W
bit1
D01
W
bit0
D00
W
Initial value
00000000B
bit7
bit6
CSTR CITE
R/W R/W
bit5
bit4
bit3
bit2
bit1
bit0
UDIE CMPF OVFF UDFF UDF1 UDF0
R/W R/W R/W R/W
R
R
Initial value
00000000B
bit15 bit14 bit13 bit12 bit11 bit10 bit9
bit8
M16E CDCF CFIE CLKS CMS1 CMS0 CES1 CES0
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
00000000B
bit7
R/W
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CTUT UCRE RLDE UDCC CGSC CGE1 CGE0
R/W R/W R/W R/W R/W
R
R
Initial value
-0000000B
R/W: Readable/writable
R:
Read only
W: Write only
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13.3 Register of Up/Down Counter
13.3.1
MB91490 Series
Up/Down Count Register (UDCR)
Up/down count register (UDCR) is 8-bit count register. Up/down counting is performed
by an input from the internal circuit, an internal prescaler, or an input of AIN pin and BIN
pin. Also, in 16-bit count mode, this register operates as 16-bit count register.
■ Up/Down Count Register (UDCR)
Figure 13.3-2 Up/Down Count Register (UDCR)
UDCR10
Address
000542H
UDCR00
Address
000543H
R:
bit15
D15
R
bit14
D14
R
bit13
D13
R
bit12
D12
R
bit11
D11
R
bit10
D10
R
bit9
D09
R
bit8
D08
R
Initial value
00000000B
bit7
D07
R
bit6
D06
R
bit5
D05
R
bit4
D04
R
bit3
D03
R
bit2
D02
R
bit1
D01
R
bit0
D00
R
Initial value
00000000B
Read only
Values cannot be written to this register directly. To write a value to this register, the RCR must be used.
First write the value to write to this register to the RCR, then set the CTUT bit of the CCRL register to "1".
The value will then be transferred from the RCR to this register (in a reload-operation by software).
Note:
In 16-bit mode, perform a 16-bit read operation for this register once.
In 8-bit mode, only UDCR00 value is effective.
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13.3 Register of Up/Down Counter
MB91490 Series
13.3.2
Reload Compare Register (RCR)
Reload compare register (RCR) is 8-bit reload/compare register. The reload value and
the compare value are set by this register. The reload value and the compare value are
the same and up/down count is enabled in 00H to the value of this register (16-bit
operation mode: 0000H to the value of this register) by activating the function of reload
and compare.
■ Reload Compare Register (RCR)
Figure 13.3-3 Reload Compare Register (RCR)
RCR10
Address
000540H
RCR00
Address
000541H
W:
bit15
D15
W
bit14
D14
W
bit13
D13
W
bit12
D12
W
bit11
D11
W
bit10
D10
W
bit9
D09
W
bit8
D08
W
Initial value
00000000B
bit7
D07
W
bit6
D06
W
bit5
D05
W
bit4
D04
W
bit3
D03
W
bit2
D02
W
bit1
D01
W
bit0
D00
W
Initial value
00000000B
Write only
This register is enabled to write only and disabled to read. By setting the CTUT bit of the CCR register to
"1" while counting is stopped, the value of this register can be transferred to the UDCR (reloaded by
software).
Note:
In 16-bit mode (when M16E = 1), write a 16-bit value to this register once.
In 8-bit mode (when M16E = 0), write a 8-bit value to RCR00.
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13.3 Register of Up/Down Counter
13.3.3
MB91490 Series
Counter Status Register (CSR)
Counter status register (CSR) can check the state of up/down counter and control the
interrupt.
■ Bit Configuration of Counter Status Register (CSR)
Figure 13.3-4 Bit Configuration of Counter Status Register (CSR)
CSR0
Address
bit7
bit6
00000547H CSTR CITE
R/W R/W
bit5
bit4
bit3
bit2
bit1
bit0
UDIE CMPF OVFF UDFF UDF1 UDF0
R/W R/W R/W R/W
R
R
Initial value
00000000B
R/W: Readable/writable
R:
Read only
[bit7] CSTR: Count start bit
This bit controls start and stop of UDCR counting operation.
CSTR
Count operation
0
Stops the counting operation [initial value].
1
Starts the counting operation.
[bit6] CITE: Compare interrupt enable bit
This bit controls whether to enable or disable interrupt output to the CPU when a compare detection flag
(CMPF) is set (during a compare operation).
CITE
Compare interrupt enable
0
Disables compare interrupt [initial value].
1
Enables compare interrupt.
[bit5] UDIE: Overflow/underflow interrupt enable bit
This bit controls whether to enable or disable interrupt output to the CPU when OVFF/UDFF is set (when
overflow or underflow occurs).
UDIE
406
Overflow/underflow interrupt enable
0
Disables overflow/underflow interrupt [initial value].
1
Enables overflow/underflow interrupt.
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13.3 Register of Up/Down Counter
MB91490 Series
[bit4] CMPF: Compare detection flag
This flag indicates that the comparison result of the UDCR value and RCR value are equal.
In write operations, the flag can only be set to "0", not to "1".
CMPF
Meaning of compare detection flag
0
Comparison result does not match [initial value].
1
Comparison result matches.
[bit3] OVFF: Overflow detection flag
This flag indicates the occurrence of an overflow.
In write operations, this flag can only be set to "0", not to "1".
OVFF
Meaning of overflow detection flag
0
No overflow [initial value]
1
Overflow
[bit2] UDFF: Underflow detection flag
This flag indicates the occurrence of an underflow.
In write operations, this flag can only be set to "0", not to "1".
UDFF
Meaning of underflow detection flag
0
No underflow [initial value]
1
Underflow
[bit1, bit0] UDF1, UDF0: Up/down flags
These bits indicate the type of a counting operation (up or down) immediately preceding the current
operation.
Only reading is allowed. No writing is allowed.
CM71-10155-2E
UDF1
UDF0
Detection edge
0
0
No input [initial value]
0
1
Down count
1
0
Up count
1
1
Both up and down counting were performed simultaneously.
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13.3 Register of Up/Down Counter
13.3.4
MB91490 Series
Counter Control Register (CCR)
Counter control register (CCR) is the register which controls the operation mode of up/
down counter. The function of bit15 (M16E) is different in odd channel and even
channel.
■ Bit Configuration of Counter Control Register (CCR)
Figure 13.3-5 Bit Configuration of Counter Control Register (CCR)
CCRH0
Address
000544H
bit15 bit14
M16E CDCF
R/W R/W
CCRL0
Address
000545H
bit7
R/W
bit13 bit12 bit11 bit10 bit9
bit8
CFIE CLKS CMS1 CMS0 CES1 CES0
R/W R/W R/W R/W R/W R/W
Initial value
00000000B
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CTUT UCRE RLDE UDCC CGSC CGE1 CGE0
R/W R/W R/W R/W R/W
R
R
Initial value
-0001000B
R/W: Readable/writable
R:
Read only
-:
Undefined bit
[bit15] M16E: 16-bit mode permission setting bit
8-bit/16-bit operation mode selection (switching) bit
M16E
16-bit mode enable setting
0
8-bit operation mode [initial value]
1
16-bit operation mode
[bit14] CDCF: Count direction change flag
This flag sets when the count direction is changed. When the count direction is changed up to down or
down to up during counting, "1" is set to this bit.
Writing "0" clears the setting.
Writing "1" is ignored. The value of this bit is not changed.
CDCF
Direction change detection
0
Direction has not been changed [initial value].
1
Direction has been changed once or more.
The count direction is set to down immediately after a reset. Therefore, CDCF is set to "1" when up
counting is performed immediately after a reset.
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13.3 Register of Up/Down Counter
MB91490 Series
[bit13] CFIE: Count direction change interrupt enable bit
This bit controls the interrupt output for the CPU when CDCF is set. An interrupt occurs if the count
direction is changed at least once during counting.
CFIE
Direction change interrupt enable
0
Disables direction change interrupt [initial value].
1
Enables direction change interrupt.
[bit12] CLKS: Internal prescaler selection bit
When timer mode is selected, this bit selects the frequency of the internal prescaler.
This bit is effective only in timer mode and only for down counting.
CLKS
Selected internal clock
0
Two peripheral clock (CLKP) cycles [initial value]
1
Eight peripheral clock (CLKP) cycles
[bit11, bit10] CMS1, CMS0: Counting mode selection bits
These bits select counting mode.
CMS1
CMS0
Counting mode
0
0
Timer mode (down count) [initial value]
0
1
Up or down counting mode
1
0
Phase difference counting mode, 2 multiplication
1
1
Phase difference counting mode, 4 multiplication
[bit9, bit8] CES1, CES0: Count clock edge selection bits
In up/down counting mode, these bits select the input of internal circuit or the detection edge of external
pins AIN and BIN.
This setting is invalid in modes other than up or down counting mode.
CES1
CES0
Selection edge
0
0
Disables edge detection [initial value].
0
1
Detects falling edge.
1
0
Detects rising edge.
1
1
Detects rising and falling edges.
[bit7] Reserved: Reserved bit
This bit is reserved. Be sure to set this bit to "0".
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13.3 Register of Up/Down Counter
MB91490 Series
[bit6] CTUT: Counter write bit
This bit transfers data from RCR to UDCR.
When this bit is set to "1", data is transferred from RCR to UDCR.
Writing "0" to this bit has no effect. The read value is always "0".
Do not set this bit to "1" during counting (when the CSTR bit of the CSR is "1").
[bit5] UCRE: UDCR clear enable bit
This bit controls the compare operation that clears UDCR.
UDCR clear functions other than clearing due to comparing (such as due to the ZIN pin), are not
affected.
UCRE
Counter clear by compare
0
Disables counter clear [initial value].
1
Enables counter clear.
[bit4] RLDE: Reload enable bit
This bit controls the start of the reload function. When the reload function is started, if UDCR leads the
underflow, this bit transfers the value of RCR to UDCR.
RLDE
Reload function
0
Disables the reload function [initial value].
1
Enables the reload function.
[bit3] UDCC: UDCR clear bit
This bit clears the UDCR. When this bit is set to "0", the UDCR is cleared to "0000H".
Writing "1" to this bit has no effect. The read value is always "1".
[bit2] CGSC: Counter clear/gate selection bit
This bit selects the function of the external pin ZIN.
CGSC
ZIN pin function
0
Counter clear function [initial value]
1
Gate function
[bit1, bit0] CGE1, CGE0: Counter clear/gate edge selection bits
These bits select the detection edge/level of the external pin ZIN.
410
CGE1
CGE0
When counter clear function is selected
When gate function is selected
0
0
Disables edge detection [initial value].
Disables level detection [initial value] (count disable)
0
1
Falling edge
"L" level
1
0
Rising edge
"H" level
1
1
Setting disabled
Setting disabled
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CHAPTER 13 UP/DOWN COUNTER
13.4 Operation of Up/Down Counters
MB91490 Series
13.4
Operation of Up/Down Counters
This section describes the up/down counter operation.
■ Selecting Counting Mode
These counters/timers have four counting modes. The CMS1 and CMS0 bits of the CCR register are used
to select the counting modes.
CMS1
CMS0
Counting mode
0
0
Timer mode (down count) [initial value]
0
1
Up/down counting mode
1
0
Phase difference counting mode, 2 multiplication
1
1
Phase difference counting mode, 4 multiplication
● Timer mode [down count]
In timer mode, the output of the internal prescaler is used for counting down. For the internal prescaler,
either two peripheral clock (CLKP) cycles or eight peripheral clock (CLKP) cycles can be selected with the
CLKS bit of the CCRH0 register.
● Up/down counting mode
In up/down counting mode, counting up/down is performed by counting the input through external pins
AIN and BIN. The input through the AIN pin controls counting up and the input through the BIN pin
controls counting down.
The inputs through the AIN pin and BIN pin are subject to edge-detected. The edge detection can be
selected by the CES1 and CES0 bits of the CCRH register.
CES1
CES0
Selection edge
0
0
Disables the edge detection. [initial value]
0
1
Detects falling edge.
1
0
Detects rising edge.
1
1
Detects both falling and rising edges.
● Phase difference counting mode (two multiplication/four multiplication)
In phase difference counting mode, to count the phase difference between phase A and phase B of the
output signal for the encoder, detect the input level of the BIN pin at input edge detection of the AIN pin.
For the phase difference between AIN pin input and BIN pin input in two multiplication or four
multiplication mode, count up if the AIN is faster, and count down if the BIN is faster.
In two multiplication mode, counting is performed by detecting the value of the AIN pin in the period
between the rising and falling edges of the BIN pin. In this case, counting is performed as follows:
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13.4 Operation of Up/Down Counters
MB91490 Series
Edge of the BIN pin
Level of the AIN pin
Count
Rising 
"H" level
Count up
Rising 
"L" level
Count down
Falling 
"H" level
Count down
Falling 
"L" level
Count up
Figure 13.4-1 Overview of the Phase Difference Counting Mode (Two Multiplication) Operation
AIN pin
↑
BIN pin
+1
1
Count value 0
↑
↑
+1
2
+1
3
↑
↑
↑
+1 +1
4
5
↑
-1 +1
4 5
↑
↑
-1
4
-1
3
↑
-1
2
↑
-1
1
↑
-1
0
In four-multiplication mode, counting is performed by detecting the value of the AIN pin at the timing
between the rising and falling edges of the BIN pin and detecting the value of the BIN pin at the timing
between the rising and falling edges of the AIN pin. In this case, counting is performed as follows:
Edge input
Edge
Level input
Level
Count
"H" level
Count up
"L" level
Count down
"H" level
Count down
Falling 
"L" level
Count up
Rising 
"H" level
Count down
"L" level
Count up
"H" level
Count up
"L" level
Count down
Rising 
Rising 
BIN
Falling 
AIN
Rising 
AIN
Falling 
BIN
Falling 
Figure 13.4-2 Overview of the Phase Difference Counting Mode (Four Multiplication) Operation
AIN pin
BIN pin
Count value 0
+1 +1 +1 +1 +1+1 + 1+1 +1+1
1 2 3 4 5 6 7 8 9 10
-1
9
+1
10
-1
9
-1 -1 -1 -1 -1 -1 -1 -1
8 7 6 5 4 3 2 1
For counting the encoder output, by inputting the A phase to the AIN pin, the B phase to the BIN pin, and
the Z phase to the ZIN pin, a highly precise count of the rotation angle and number of rotations can be
obtained and the rotation direction can be detected as well.
When this counting mode is selected, the detection edge selection with the CES1 and CES0 bits is invalid.
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CHAPTER 13 UP/DOWN COUNTER
13.4 Operation of Up/Down Counters
MB91490 Series
■ Reload/Compare Function
This counters have reload and compare clear functions, which can be combined for processing.
The examples of setting are shown in following.
RLDE
UCRE
Reload/Compare function
0
0
Disables clearing by reload/compare [initial value].
0
1
Enables clearing by compare.
1
0
Reload is enabled.
1
1
Enables clearing by reload/compare.
● Reload function
When the reload function is started, the value of the RCR is transferred to the UDCR with the timing of the
down count clock after an underflow. In this case, when UDFF bit is set, an interrupt request is generated.
In a mode in which down counting is not performed, starting this function is invalid.
Figure 13.4-3 Overview of the Operation of the Reload Function
(0FFFFH)
FFH
RCR
Reload interrupt
generated
Reload interrupt
generated
00H
Underflow
Underflow
● Compare clear function
When the compare clear function is enabled, the compare function can be used in all modes other than
timer mode. When the compare function is started, if the value of RCR and the value of UDCR match,
CMPF bit is set and an interrupt request is generated. When the compare clear function is started, the
UDCR is cleared with the timing of the next up count clock. (The UDCR is not cleared when counting
down is performed.)
In a mode in which up counting is not performed, starting this function is invalid.
Figure 13.4-4 Overview of the Compare Function Operation
(0FFFFH)
FFH
RCR
Compare match
Compare match
00H
Counter clear,
interrupt generated
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Counter clear,
interrupt generated
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13.4 Operation of Up/Down Counters
MB91490 Series
■ Synchronous Start of Reload/Compare Function
When the reload/compare function is started, counting up or down can be performed with an arbitrary
width.
The reload function is started at an underflow and transfers the value of the RCR to the UDCR. When the
values of RCR and UDCR match, the compare function clears the UDCR. By using these functions,
counting up or down is performed for values between "0000H" and the value of the RCR.
Figure 13.4-5 Overview of the Operation when the Reload and Compare Functions are Started at the Same Time
FFH
RCR
Compare match Compare match Reload
Reload
Reload
Compare match
00H
Counter clear
Counter clear
Underflow
Underflow
Counter clear
Underflow
An interrupt to the CPU can be generated at a compare match or at reload (underflow). These interrupt
outputs can be enabled separately.
The timing for clearing the UDCR is different during counting and when counting is stopped.
Reloading (writing "1" to the CTUT bit) by software is not allowed during counting.
• During counting, if an event for clearing occurs, all the events are synchronized with the count clock.
UDCR
Clear event
0065H
0066H
0000H
0001H
Synchronized to this clock
Count clock
Reference:
During counting, reloading due to an underflow is performed in synchronization with all count clocks.
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CHAPTER 13 UP/DOWN COUNTER
13.4 Operation of Up/Down Counters
MB91490 Series
• When an event for clearing occurs during counting, if counting is stopped in count clock
synchronization wait state (state of waiting for the count input for synchronization), the clear operations
are performed when counting is stopped.
UDCR
0065H
0066H
0000H
Clear event
Count clock
Disable (count disabled)
Count enable
Enable (count enabled)
• If the events for reloading and clearing occur during counting, reload and clear are performed when the
event occurs.
UDCR
0065H
0080H
Reload/
clear event
Clear by compare is performed when the values of the UDCR and the RCR match and while counting up. If
down counting is performed or counting is stopped, the clear operation is not performed even when the
values of the UDCR and the RCR match.
As for the timing of clearing and reloading, the clear operation follows the above timing for all events other
than reset input, and reloading also uses the above timing for all events.
When the events for clearing and reloading occur at the same time, the clear event takes priority.
■ Writing Data to UDCR
Data cannot be written to the UDCR directly from the data bus. To write arbitrary value to the UDCR,
follow the procedure below.
1. Write the data that is to be written to the UDCR first to the RCR (Note that this means that the original
data in the RCR will be lost).
2. By setting the CTUT bit of the CCR to 1, data is transferred from the RCR to the UDCR.
Perform the above operation while counting is stopped (when the CSTR bit of the CSR is 0).
Reference:
If 1 is written to the CTUT bit by mistake during counting, the value of the RCR is transferred to the
UDCR at the timing for a write.
Besides the above procedure, the following procedure can also be applied to clear the counter.
• Clearing by reset input.
• Clearing by edge input through the ZIN pin.
• Clearing by writing 0 to UDCC bit of the CCR.
• Clearing by compare function.
The above can be performed regardless of whether counting is performed or stopped.
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13.4 Operation of Up/Down Counters
MB91490 Series
■ Count Clear/Gate Function
The ZIN pin can be used after selecting the count clear function or gate function based on the CGSC bit of
the CCR register.
When the count clear function is started, the ZIN pin clears the counter. The CGE1 and CGE0 bits of the
CCRL register can control which edge input of the ZIN pin to use for counting.
When the gate function is started, the ZIN pin enables or disables counting. The CGE1 and CGE0 bits of
the CCR register can control which level input of the ZIN pin enables counting.
This function is effective for all modes.
Table 13.4-1 ZIN Pin Function
CGSC
ZIN pin function
0
Counter clear function [initial value]
1
Gate function
Table 13.4-2 Count Clear/Gate Function
CGE1
CGE0
When counter clear function is used
When gate function is used
0
0
Disables edge detection.
[initial value]
Disables level detection.
[initial value] (count disable)
0
1
Falling edge
"L" level
1
0
Rising edge
"H" level
1
1
Setting disabled
Setting disabled
■ Count Direction Flag
The count direction flag (UDF1 and UDF0) indicates at the time of up/down counting whether the counting
operation preceding the current operation was counting up or down. Based on the count clock signal from
the input of the AIN and BIN pins, the value of this flag changes for each count. Current rotation direction,
such as control of motor, can be determined by referring to this flag.
Table 13.4-3 Count Direction Flag
416
UDF1
UDF0
Count direction
0
0
Without input [initial value]
0
1
Down count
1
0
Up count
1
1
Up/down occurs simultaneously (no counting operation is performed).
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CHAPTER 13 UP/DOWN COUNTER
13.4 Operation of Up/Down Counters
MB91490 Series
■ Count Direction Change Flag
The CDCF is set when the counting direction changes between up and down. Simultaneously to setting this
flag, an interrupt request to the CPU can be generated. By referring to the interrupt and count direction flag,
the direction to which counting is changed can be determined. However, note that when the period of
direction change is short and multiple direction changes are performed in succession, the direction that the
flag indicates after the direction change may return to the original direction so that it appears as if the
counting direction has not changed at all in between.
Table 13.4-4 Count Direction Change Flag
CDCF
Direction change detection
0
No direction change [initial value]
1
Direction has changed (at least once).
■ Compare Detection Flag
The CMPF is set when the values of UDCR and RCR match during counting. This flag is set for a match
during counting up or down, match by occurrence of a reloading event, as well as when the values already
match when counting started.
■ Operations for 8-bits and 16-bit
This module can be used as an 8-bit up/down counter or a 16-bit up/down counter. Setting the M16E bit of
the CCR register to 0 sets 8-bit mode. Setting the bit to "1" sets 16-bit mode.
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13.4 Operation of Up/Down Counters
MB91490 Series
■ Interrupt Generation Timing
Interrupt flag
Flag setting interrupt
Reload
Clear
CDCF
(Count direction
change flag)
An interrupt is
generated
simultaneously with
setting of the flag when
counting starts
immediately after the
counting direction is
changed.
CMPF
(Compare
detection flag)
An interrupt is
generated
simultaneously with
setting of the flag when
the values of RCR and
UDCR match when up
or down counting, or
reload counting is
initiated.
UDCR is cleared at
the timing of the
first up count after
RCR and UDCR
match. (UDCR is
not cleared for
down counting).
OVFF
(Overflow
detection flag)
An interrupt is
generated
simultaneously with
setting of the flag at the
timing of the first up
count after the count
reaches "FFFFH".
UDCR is cleared at
the timing of the
first count after the
count reaches
"FFFFH".
UDFF
(Underflow
detection flag)
An interrupt is
generated
simultaneously with
setting of the flag at the
timing of the first down
count after the count
reaches "0000H".
The value of RCR
is transferred to
UDCR at the timing
of the first count
after the count
reaches "0000H".
• Because the value of RCR is used for both the reload and compare values, the compare flag is set
always when reloading is performed.
• If the clear function is enabled, clearing occurs when up counting is performed after the compare match
during down counting.
■ Note
The count direction is set to down when the count is reset. Therefore, at the first up count after resetting,
CDCF bit is set to 1 to indicate that the counting direction has been changed.
After the up count register (UDCR) reaches the maximum count that the register can hold, counting
continues without a carry-over. It therefore appears that counting is continuing with the up/down count
register cleared.
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CHAPTER 14
MULTI-FUNCTION SERIAL
INTERFACE
This chapter describes the functions and operations of
the multi-function serial interface.
14.1 Characteristics of Multi-function Serial Interface
14.2 UART (Asynchronous Serial Interface)
14.3 Overview of UART (Asynchronous Serial Interface)
14.4 Registers of UART (Asynchronous Serial Interface)
14.5 Interrupts of UART
14.6 Operation of UART
14.7 Dedicated Baud Rate Generator
14.8 Setup Procedure and Program Flow for Operation Mode 0
(Asynchronous Normal Mode)
14.9 Setup Procedure and Program Flow for Operation Mode 1
(Asynchronous Multi-processor Mode)
14.10 Notes on UART Mode
14.11 CSIO (Clock Synchronous Serial Interface)
14.12 Overview of CSIO (Clock Synchronous Serial Interface)
14.13 Registers of CSIO (Clock Synchronous Serial Interface)
14.14 Interrupts of CSIO (Clock Synchronous Serial Interface)
14.15 Operation of CSIO (Clock Synchronous Serial Interface)
14.16 Dedicated Baud Rate Generator
14.17 Setup Procedure and Program Flow for CSIO
(Clock Synchronous Serial Interface)
14.18 Notes on CSIO Mode
14.19 I2C Interface
14.20 Overview of I2C Interface
14.21 Registers of I2C Interface
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MB91490 Series
14.22 Interrupts of I2C Interface
14.23 Dedicated Baud Rate Generator
14.24 Notes on I2C Mode
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14.1 Characteristics of Multi-function Serial Interface
MB91490 Series
14.1
Characteristics of Multi-function Serial Interface
This multi-function serial interface has the following characteristics.
■ Interface Mode
The following interface modes are selectable for the multi-function serial interface depending on the
operation mode settings.
• UART0 (Asynchronous normal serial interface)
• UART1 (Asynchronous multi-processor serial interface)
• CSIO (Clock synchronous serial interface) (SPI can be supported)
• I2C (I2C bus interface)
■ Switching the Interface Mode
To communicate through each serial interface, the registers shown in Table 14.1-1 should be used to set the
operation mode before starting the communication.
Figure 14.1-1 Bit Structure of SMR Register
SMR
Address:
ch.0 000063H
ch.1 000073H
ch.2 000083H
bit7
bit6
bit5
bit4
bit3
bit2
MD2
MD1
MD0
-
SBL
BDS SCKE SOE
Read/Write (R/W) (R/W) (R/W)
(-)
Initial value
(-)
(0)
(0)
(0)
bit1
bit0
(R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
Table 14.1-1 Switching Interface Mode
MD2
MD1
MD0
Interface mode
0
0
0
UART0 (Asynchronous normal serial interface)
0
0
1
UART1 (Asynchronous multi-processor serial interface)
0
1
0
CSIO (Clock synchronization serial interface) (SPI can be supported)
1
0
0
I2C (I2C bus interface)
Note: Settings other than above are prohibited.
Notes:
• Transmission and reception cannot be guaranteed when the operation mode is switched while
one of the serial interfaces is still in use for transmission or reception operation.
• The operation mode must be set first. Otherwise, the other registers will be initialized when the
operation mode is changed. Note, however, that when SCR and SMR are written simultaneously
with 16-bit write access, SCR reflects the written content.
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.2 UART (Asynchronous Serial Interface)
14.2
MB91490 Series
UART (Asynchronous Serial Interface)
Among all the functions of the multi-function serial interface, this section describes
those supported in operation modes 0 and 1.
• UART (Asynchronous Serial Interface)
• Overview of UART (Asynchronous Serial Interface)
• Registers of UART (Asynchronous Serial Interface)
- Serial Control Register (SCR)
- Serial Mode Register (SMR)
- Serial Status Register (SSR)
- Extended Communication Control Register (ESCR)
- Reception Data Register/Transmission Data Register (RDR/TDR)
- Baud Rate Generator Registers 1, 0 (BGR1, BGR0)
• Interrupts of UART
- Occurrence of Reception Interrupts and Flag Set Timing
- Occurrence of Transmission Interrupts and Flag Set Timing
• Operation of UART
• Dedicated Baud Rate Generator
- Setting Baud Rate
• Setup Procedure and Program Flow for Operation Mode 0 (Asynchronous Normal Mode)
• Setup Procedure and Program Flow for Operation Mode 1 (Asynchronous Multi-processor Mode)
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14.3 Overview of UART (Asynchronous Serial Interface)
MB91490 Series
14.3
Overview of UART (Asynchronous Serial Interface)
UART (asynchronous serial interface) is a general-purpose serial data communication
interface to perform asynchronous communication (start-stop synchronization) with an
external unit. The UART supports a two-way communication function (normal mode)
and a master/slave communication function (multi-processor mode: the master and
slaves both supported).
■ Functions of UART (Asynchronous Serial Interface)
Function
1
Data
2
Serial input
3
Transfer system
4
Baud rate
5
Data length
6
Signaling system
NRZ (Non Return to Zero), inverted NRZ
7
Start bit detection
• Synchronized with the falling edge of a start bit (NRZ)
• Synchronized with the rising edge of a start bit (inverted NRZ)
8
9
10
Reception error detection
Interrupt request
Full-duplex double buffer
Oversampling is performed for three times to determine the reception value by the
majority of the sampling values achieved.
Asynchronous
• Dedicated baud rate generator (15-bit reload counter configuration)
• The reload counter can be used to adjust the external clock input.
5 to 9 bits (in normal mode), 7 or 8 bits (in multi-processor mode)
• Framing error
• Overrun error
• Parity error*
• Reception interrupt
(completion of reception, framing error, overrun error, parity error*)
• Transmission interrupt (transmission data empty, transmission bus idle)
• The extended intelligent I/O service (EI2OS) and DMA function are available for
both transmission and reception.
Master/slave communication
Communication between 1 (master) and n (slaves) is enabled.
function (multi-processor
(The master and slave systems are both supported.)
mode)
*: The detection of a parity error is enabled only in normal mode.
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14.4 Registers of UART (Asynchronous Serial Interface)
14.4
MB91490 Series
Registers of UART (Asynchronous Serial Interface)
This section lists the registers of UART (asynchronous serial interface).
■ List of Registers of UART (Asynchronous Serial Interface)
Figure 14.4-1 List of Registers of UART (Asynchronous Serial Interface)
Address
bit15
bit8 bit7
bit0
000062H 000063H
000072H 000073H
000082H 000083H
SCR
(serial control register)
SMR
(serial mode register)
000060H 000061H
000070H 000071H
000080H 000081H
SSR
(serial status register)
ESCR
(extended communication
control register)
000066H 000067H
UART 000076H 000077H
000086H 000087H
RDR/TDR
(transmission/reception
data register)
000064H 000065H
000074H 000075H
000084H 000085H
BGR1
(baud rate generator
register 1)
BGR0
(baud rate generator
register 0)
000068H 000069H
000078H 000079H
000088H 000089H
-
-
Table 14.4-1 Bit Assignment of UART (Asynchronous Serial Interface)
bit15
SCR/SMR UPCL
SSR/
ESCR
REC
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
-
-
RIE
TIE
TBIE
RXE
TXE
MD2
MD1
MD0
-
SBL
BDS
SCKE
SOE
-
PE
FRE
ORE
RDRF
TDRE
TBI
-
-
INV
PEN
P
L2
L1
L0
D8
(AD)
D7
D6
D5
D4
D3
D2
D1
D0
B8
B7
B6
B5
B4
B3
B2
B1
B0
TDR /
RDR
BGR1/
BGR0
424
-
EXT
B14
B13
B12
B11
B10
B9
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.4 Registers of UART (Asynchronous Serial Interface)
MB91490 Series
■ Operation Mode
The UART (asynchronous serial interface) operates in two different modes. The mode selection is
determined by MD2, MD1 and MD0 in the serial mode register (SMR).
Table 14.4-2 Operation Modes of UART (Asynchronous Serial Interface)
Operation mode
MD2
MD1
MD0
Type
0
0
0
0
UART0 (asynchronous normal mode)
1
0
0
1
UART1 (asynchronous multi-processor mode)
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14.4 Registers of UART (Asynchronous Serial Interface)
14.4.1
MB91490 Series
Serial Control Register (SCR)
The serial control register (SCR) enables or disables transmission/reception,
transmission/reception interrupts, and transmission bus idle interrupts. SCR can also
reset the UART.
■ Serial Control Register (SCR)
Figure 14.4-2 shows the bit structure of the serial control register (SCR), and Table 14.4-3 describes the
function of each bit.
Figure 14.4-2 Bit Structure of Serial Control Register (SCR)
SCR
Address:
ch.0 000062H
ch.1 000072H
ch.2 000082H
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
UPCL
-
-
RIE
TIE
TBIE
RXE
TXE
R/W
-
-
R/W
R/W
R/W
R/W
R/W
.........................................
bit7
bit0
(SMR)
Initial value
0--00000
TXE
0
1
Transmission enable bit
Disables t ransmission
Enables t ransmission
RXE
0
1
Reception enable bit
Disables reception
Enables reception
TBIE
Transmission bus idle interrupt enable bit
Disables transmission bus idle interrupt
0
1
B
Enables transmission bus idle interrupt
TIE
0
1
Transmission interrupt enable bit
Disables transmission interrupt
Enables transmission interrupt
RIE
0
1
Reception interrupt enable bit
Disables reception inter rupt
Enables reception inter rupt
Undefined bits
Read : undefined value. Write: no ef fect.
UPCL
R/W
: Readable/Writable
: Initial value
-
426
0
1
Pro grammable clear bit
Write
Read
No ef fect
"0" is al ways read .
Pro grammable clear operation
: Undefined
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
MB91490 Series
CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.4 Registers of UART (Asynchronous Serial Interface)
Table 14.4-3 Functional Description of Each Bit of Serial Control Register (SCR)
Bit name
Function
This bit is used to initialize the internal state of the UART.
Setting the bit to "1":
• The UART will be reset directly (software reset). The register setting, however,
will be retained. In this case, communication of the data which is being
transmitted or received will be cut off immediately.
bit15
UPCL:
Programmable clear
bit
• The baud rate generator will reload the value set in BGR1/BGR0 registers, and
then restart the operation.
• All the transmission/reception interrupt sources (PE, FRE, ORE, RDRF, TDRE
and TBI) will be initialized (000011B).
Setting the bit to "0": No effect on the operation
Reading this bit always returns "0".
Note:
Execute the programmable clear operation after disabling interrupts.
bit14,
bit13
Undefined bits
bit12
RIE:
Reception interrupt
enable bit
bit11
TIE:
Transmission
interrupt enable bit
bit10
TBIE:
Transmission bus idle
interrupt enable bit
Read: undefined value
Write: no effect
• This bit is used to enable/disable the output of reception interrupt requests to the
CPU.
• A reception interrupt request is output when the RIE bit and the reception data
flag bit (RDRF) are set to "1", or when any of the error flag bits (PE, ORE or
FRE) is set to "1".
• This bit is used to enable/disable the output of transmission interrupt requests to
the CPU.
• A transmission interrupt request is output when the TIE and TDRE bits are set to
"1".
• This bit is used to enable/disable the output of transmission bus idle interrupt
requests to the CPU.
• A transmission bus idle interrupt request is output when the TBIE and TBI bits
are set to "1".
This bit is used to enable/disable UART reception operation.
• Setting the bit to "0" disables the reception operation.
• Setting the bit to "1" enables the reception operation.
bit9
RXE:
Reception enable bit
Note:
Even when the reception operation is enabled (RXE = 1), such operation does not
start until the falling edge of a start bit (in NRZ format: INV = 0) is input. (When
the inverted NRZ format is selected (INV = 1), the reception operation does not
start until the rising edge is input.)
If the reception operation is disabled (RXE = 0) during the reception, the
operation will be terminated immediately.
This bit is used to enable/disable UART transmission operation.
bit8
TXE:
Transmission enable
bit
CM71-10155-2E
• Setting the bit to "0" disables the transmission operation.
• Setting the bit to "1" enables the transmission operation.
Note:
If the transmission operation is disabled (TXE = 0) during the transmission, the
operation will be terminated immediately.
FUJITSU SEMICONDUCTOR LIMITED
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.4 Registers of UART (Asynchronous Serial Interface)
14.4.2
MB91490 Series
Serial Mode Register (SMR)
The serial mode register (SMR) sets the operation mode, selects the transfer direction,
data length and stop bit length, and enables or disables the output to the serial data and
serial clock pins.
■ Serial Mode Register (SMR)
Figure 14.4-3 shows the bit structure of the serial mode register (SMR), and Table 14.4-4 describes the
function of each bit.
Figure 14.4-3 Bit Structure of Serial Mode Register (SMR)
bit15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bit8
SMR
bit7
bit6
bit5
MD2 MD1 MD0
(SCR)
Address:
ch.0 000063H
ch.1 000073H
ch.2 000083H
bit4
bit3
bit2
bit1
bit0
-
SBL
BDS SCKE SOE 000-0000B
Initial value
R/W R/W R/W R/W R/W R/W R/W R/W
SOE
0
1
Serial data output enable bit
Disables the output of SOT
Enables the output of SOT
SCKE
1
Serial clock output enable bit
Disables the output of SCK
or
Enables the input of SCK
Enables the output of SCK
BDS
0
1
Transfer direction selection bit
LSB first (Transfer starting from the least significant bit)
MSB first (Transfer starting from the most significant bit)
SBL
0
1
Stop bit length selection bit
1 bit
2 bits
0
Undefined bit
Read: undefined value. Write: no effect.
R/W
: Readable/Writable
-
: Undefined bit
: Initial value
428
MD2 MD1 MD0
Operation mode setting bits
0
0
0
Operation mode 0 (asynchronous normal mode)
0
0
1
Operation mode 1 (asynchronous multi-processor mode)
0
1
0
Operation mode 2 (clock synchronization mode)
1
0
0
Operation mode 4 (I2C mode)
Note: This section describes the registers and operations of operation
modes 0 and 1.
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
MB91490 Series
CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.4 Registers of UART (Asynchronous Serial Interface)
Table 14.4-4 Functional Description of Each Bit of Serial Mode Register (SMR)
Bit name
Function
bit7
to
bit5
MD2, MD1, MD0:
Operation mode
setting bits
These bits set the operation mode for the asynchronous serial interface.
"000B": Selects operation mode 0 (asynchronous normal mode)
"001B": Selects operation mode 1 (asynchronous multi-processor mode)
"010B": Selects operation mode 2 (clock synchronization mode)
"100B": Selects operation mode 4 (I2C mode)
This section describes the registers and operations of operation mode 0
(asynchronous normal mode) and operation mode 1 (asynchronous multi-processor
mode).
Note:
Settings other than above are prohibited.
To switch the operation mode, execute the programmable clear operation first
(SCR:UPCL = 1). And then, after setting the operation mode, set each register.
bit4
Undefined bit
Read: undefined value
Write: no effect
bit3
SBL:
Stop bit length
selection bit
This bit is used to select a bit length for a stop bit (frame end mark of transmission
data).
Setting the bit to "0" sets the stop bit to 1 bit in length.
Setting the bit to "1" sets the stop bit to 2 bits in length.
Note:
In reception, only the first bit of each stop bit is always detected.
Set this bit when transmission is disabled (TXE = 0).
bit2
BDS:
Transfer direction
selection bit
This bit is used to determine the transfer priority for transfer serial data: whether the
least significant bit should be transferred first (LSB first, BDS = 0) or the most
significant bit should be transferred first (MSB first, BDS = 1).
Note:
Set this bit when transmission and reception are disabled (TXE = RXE = 0).
bit1
SCKE:
Serial clock output
enable bit
This bit is used to control the I/O port of the serial clock.
Setting the bit to "0":
The output of SCK "H" or the input of SCK will be enabled. To use it as a SCK
input, set a general-purpose I/O port as the input port. Also select the external
clock (BGR:EXT = 1) using the external clock selection bit.
Setting the bit to "1" enables the output of SCK.
bit0
SOE:
Serial data output
enable bit
This bit is used to enable/disable the output of serial data.
Setting the bit to "0" disables the output.
Setting the bit to "1" enables the output of SOT.
Note:
The operation mode must be set first. Otherwise, the other registers will be initialized when the
operation mode is changed. Note, however, that when SCR and SMR are written simultaneously
with 16-bit write access, SCR reflects the written content.
CM71-10155-2E
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.4 Registers of UART (Asynchronous Serial Interface)
14.4.3
MB91490 Series
Serial Status Register (SSR)
The serial status register (SSR) checks the transmission/reception status, and also
checks and clears the reception error flag.
■ Serial Status Register (SSR)
Figure 14.4-4 shows the bit structure of the serial status register (SSR) and Table 14.4-5 describes the
function of each bit.
Figure 14.4-4 Bit Structure of Serial Status Register (SSR)
SSR
Address:
ch.0 000060H
ch.1 000070H
ch.2 000080H
bit15
bit14
bit13
bit12
REC
-
PE
FRE
R/W
-
R
R
bit11
bit10
bit9
bit8
bit7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bit0
ORE RDRF TDRE TBI
R
R
R
(ESCR)
Initial value
0-000011B
R
TBI
0
1
Transmission bus idle flag bit
Transmission in progress
No transmission operation
TDRE
0
1
Transmission data empty flag bit
The transmission data register (TDR) contains data.
The transmission data register (TDR) is empty.
RDRF
Reception data full flag bit
The reception data register (RDR) is empty.
The reception data register (RDR) contains data.
0
1
ORE
0
1
Overrun error flag bit
No overrun error
Overrun error
FRE
0
1
Framing error flag bit
No framing error
Framing error
PE
0
1
Parity error flag bit
No parity error
Parity error
Undefined bit
Read: undefined value. Write: no effect.
REC
R/W
: Readable/Writable
0
R
: Read only
1
-
: Undefined
Reception error flag clear bit
Write
Read
No effect
"0" is always read.
Clears the reception error flag
(PE, FRE, ORE)
: Initial value
430
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
MB91490 Series
CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.4 Registers of UART (Asynchronous Serial Interface)
Table 14.4-5 Functional Description of Each Bit of Serial Status Register (SSR)
Bit name
Function
This bit is used to clear the PE, FRE or ORE flag in the serial status register (SSR).
bit15
REC:
Reception error flag
clear bit
bit14
Undefined bit
bit13
PE:
Parity error flag bit
(only available in
operation mode 0)
bit12
bit11
FRE:
Framing error flag bit
ORE:
Overrun error flag bit
• Writing "1" clears the error flag.
• Writing "0" has no effect.
Reading this bit always returns "0".
Read: undefined value
Write: no effect
• The bit is set to "1" when a parity error occurs during reception (ESCR:PEN =
1). The bit is cleared by writing "1" to the REC bit in the serial status register
(SSR).
• A reception interrupt request is output when the PE bit and the SCR:RIE bit are
set to "1".
• When this flag is set, the data in the reception data register (RDR) is invalid.
• This bit is set to "1" when a framing error occurs during reception. The bit is
cleared by writing "1" to the REC bit in the serial status register (SSR).
• A reception interrupt request is output when the FRE and RIE bits are set to "1".
• When this flag is set, the data in the reception data register (RDR) is invalid.
• This bit is set to "1" when an overrun occurs during reception. The bit is cleared
by writing "1" to the REC bit in the serial status register (SSR).
• A reception interrupt request is output when the ORE and RIE bits are set to "1".
• When this flag is set, the data in the reception data register (RDR) is invalid.
• This flag indicates the status of the reception data register (RDR).
bit10
bit9
RDRF:
Reception data full
flag bit
TDRE:
Transmission data
empty flag bit
• The bit is set to "1" when reception data is loaded to RDR. The bit is cleared to
"0" when the reception data register (RDR) is read.
• A reception interrupt request is output when the RDRF and RIE bits are set to
"1".
• This flag indicates the status of the transmission data register (TDR).
• When transmission data is written to TDR, the bit becomes "0", indicating that
TDR contains valid data. When the data is loaded to the transmission shift
register and transmission starts, the bit becomes "1", indicating that TDR no
longer contains any valid data.
• A transmission interrupt request is output when the TDRE and TIE bits are set to
"1".
• The TDRE bit becomes "1" when the UPCL bit in the serial control register
(SCR) is set to "1".
• This bit indicates that the UART is not performing transmission operation.
• The bit is set to "0" when transmission data is written to the transmission data
register (TDR).
bit8
TBI:
Transmission bus idle
flag bit
• The bit is set to "1" when the transmission data register is empty (TDRE =1) and
no transmission operation is in progress.
• The TBI bit becomes "1" when the UPCL bit in the serial control register (SCR)
is set to "1".
• A transmission interrupt request is output when this bit is "1" and a transmission
bus idle interrupt is enabled (SCR:TBIE = 1).
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.4 Registers of UART (Asynchronous Serial Interface)
14.4.4
MB91490 Series
Extended Communication Control Register (ESCR)
The extended communication control register (ESCR) can be used to set the transmission/
reception data length, enable/disable the parity bit, select the parity bit, and invert the serial
data format.
■ Bit Structure of the Extended Communication Control Register (ESCR)
Figure 14.4-5 shows the bit structure of the extended communication control register (ESCR) and Table
14.4-6 describes the function of each bit.
Figure 14.4-5 Bit Structure of Extended Communication Control Register (ESCR)
ESCR
bit15
.........................................
(SSR)
Address:
ch.0 000061H
ch.1 000071H
ch.2 000081H
R/W
: Readable/Writable
-
: Undefined
: Initial value
432
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
-
-
INV
PEN
P
L2
L1
L0
-
-
R/W
R/W
R/W
R/W
R/W
R/W
L2
0
0
0
0
1
L1
0
0
1
1
0
L0
0
1
0
1
0
Initial value
--000000
B
Data length selection bits
8-bit length
5-bit length
6-bit length
7-bit length
9-bit length
P
0
1
Parity selection bit
Even pa rity
Odd pa rity
PEN
0
1
Parity enable bit
Disables parity
Enables parity
INV
0
1
Inverted serial data format bit
NRZ format
Inverted NRZ format
Undefined bits
Read: undefined value. Write: no effect.
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
MB91490 Series
CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.4 Registers of UART (Asynchronous Serial Interface)
Table 14.4-6 Functional Description of Each Bit of Extended Communication Control Register (ESCR)
Bit name
Function
bit7,
bit6
Undefined bits
Read: undefined value
Write: no effect
bit5
INV:
Inverted serial data
format bit
This bit is used to select the NRZ format or the inverted NRZ format as the serial
data format.
bit4
bit3
PEN:
Parity enable bit
(only available in
operation mode 0)
P:
Parity selection bit
(only available in
operation mode 0)
This bit is used to determine whether the parity bit should be added (in transmission)
or detected (in reception).
• When this bit is set to "0", the parity bit is not added.
• When this bit is set to "1", the parity bit is added.
Note:
This bit is fixed to "0" internally in operation mode 1.
This bit is used to select odd parity "1" or even parity "0" when parity is enabled
(ESCR:PEN = 1).
• Setting the bit to "0" selects even parity.
• Setting the bit to "1" selects odd parity.
These bits are used to specify a data length for transmission/reception data.
• Selecting "000B" sets the data length to 8 bits.
• Selecting "001B" sets the data length to 5 bits.
bit2
to
bit0
L2, L1, L0:
Data length selection
bits
• Selecting "010B" sets the data length to 6 bits.
• Selecting "011B" sets the data length to 7 bits.
• Selecting "100B" sets the data length to 9 bits.
Note:
Settings other than above are prohibited.
For operation mode 1, set the data length to 7 or 8 bits. Any other setting is
prohibited.
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.4 Registers of UART (Asynchronous Serial Interface)
14.4.5
MB91490 Series
Reception Data Register / Transmission Data Register
(RDR0 to RDR2/TDR0 to TDR2)
The reception and transmission data registers are located at the same address. It
serves as the reception data register in read access, while it functions as the
transmission data register in write access.
■ Reception Data Register (RDR)
Figure 14.4-6 illustrates the bit structure of the serial reception register (RDR).
Figure 14.4-6 Bit Structure of Reception Data Register (RDR)
RDR
Address:
bit15...................... bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value
ch.0 000066H
ch.1 000076H
ch.2 000086H
D8
D7
D6
D5
D4
D3
D2
D1
D0
R
R
R
R
R
R
R
R
R
00000000B
R: Read only
The reception data register (RDR) is a 9-bit data buffer register for serial data reception.
• A serial data signal sent to a serial input pin (SIN pin) is converted through the shift register and then
stored in the reception data register (RDR).
• "0" is placed in one of the upper bits, depending on the data length, as shown below.
Data length
D8
D7
D6
D5
D4
D3
D2
D1
D0
9 bits
X
X
X
X
X
X
X
X
X
8 bits
0
X
X
X
X
X
X
X
X
7 bits
0
0
X
X
X
X
X
X
X
6 bits
0
0
0
X
X
X
X
X
X
5 bits
0
0
0
0
X
X
X
X
X
• The reception data full flag bit (SSR:RDRF) is set to "1" once reception data is stored in the reception
data register (RDR). A reception interrupt request will be generated if reception interrupts have been
enabled (SSR: RIE = 1).
• Read the reception data register (RDR) when the reception data full flag bit (SSR:RDRF) is "1". The
reception data full flag bit (SSR:RDRF) is cleared to "0" automatically, when the reception data register
(RDR) is read.
• If a reception error occurs (one of SSR:PE, ORE, or FRE is "1"), the data in the reception data register
(RDR) becomes invalid.
• In operation mode 1 (multi-processor mode), 7-bit or 8-bit operation is performed and the received AD
bit is stored in bit D8.
• 16-bit access is used to read RDR for a 9-bit transfer in operation mode 1.
434
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CM71-10155-2E
CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.4 Registers of UART (Asynchronous Serial Interface)
MB91490 Series
■ Transmission Data Register (TDR)
Figure 14.4-7 illustrates the bit structure of the transmission data register.
Figure 14.4-7 Bit Structure of Transmission Data Register (TDR)
TDR
Address:
bit15...................... bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value
ch.0 000066H
ch.1 000076H
ch.2 000086H
D8
D7
D6
D5
D4
D3
D2
D1
D0
W
W
W
W
W
W
W
W
W
11111111B
W: Write only
The transmission data register (TDR) is a 9-bit data buffer register for serial data transmission.
• If transmission data is written to the transmission data register (TDR) when transmission operation is
enabled (SCR:TXE = 1), the transmission data will be transferred to the transmission shift register,
converted into serial data and then sent from a serial data output pin (SOT pin).
• As shown below, data becomes invalid from the upper bit in accordance with the data length.
Data length
D8
D7
D6
D5
D4
D3
D2
D1
D0
9 bits
X
X
X
X
X
X
X
X
X
8 bits
Invalid
X
X
X
X
X
X
X
X
7 bits
Invalid
Invalid
X
X
X
X
X
X
X
6 bits
Invalid
Invalid
Invalid
X
X
X
X
X
X
5 bits
Invalid
Invalid
Invalid
Invalid
X
X
X
X
X
• The transmission data empty flag (SSR:TDRE) is cleared to "0" when transmission data is written to
the transmission data register (TDR).
• The transmission data empty flag (SSR:TDRE) will be set to "1" when transmission data is transferred
to the transmission shift register and the transmission starts.
• Transmission data can be written when the transmission data empty flag (SSR:TDRE) is set to "1". A
transmission interrupt will occur if transmission interrupts have been enabled. Write transmission data
by generating a transmission interrupt or when the transmission data empty flag (SSR:TDRE) is set to
"1".
• Transmission data cannot be written when the transmission data empty flag (SSR:TDRE) is set to "0".
• In operation mode 1 (multi-processor mode), 7-bit or 8-bit operation is performed and the AD bit is sent
by writing to bit D8.
• 16-bit access is used to write to TDR for a 9-bit transfer in operation mode 1.
Note:
The transmission data register is used exclusively for writing, while the reception data register is
used exclusively for reading. These registers have different write and read values as they are
located at the same address. Therefore, instructions such as INC/DEC instructions, which are used
for read modify write (RMW) instruction, cannot be used.
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.4 Registers of UART (Asynchronous Serial Interface)
MB91490 Series
Baud Rate Generator Registers 1, 0 (BGR1, BGR0)
14.4.6
The baud rate generator registers 1, 0 (BGR1, BGR0) are used to set a division ratio for
the serial clock. They also allow an external clock to be selected as the clock source for
the reload counter.
■ Bit Structure of the Baud Rate Generator Registers 1, 0 (BGR1, BGR0)
Figure 14.4-8 shows the bit structure of the baud rate generator registers 1, 0 (BGR1, BGR0).
Figure 14.4-8 Bit Structure of Baud Rate Generator Registers 1, 0 (BGR1, BGR0)
BGR
bit15
Address:
bit14
bit13
bit12
EXT
BGR0
ch.0 000065H R/W
ch.1 000075H
ch.2 000085H
bit11
bit10
bit9
bit8
bit7
bit6
bit5
(BGR1)
R/W
R/W
R/W
R/W
bit4
bit3
bit2
bit1
bit0
Initial value
00000000B
(BGR0)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000000B
R/W
BGR1
ch.0 000064H
ch.1 000074H
ch.2 000084H
R/W: Readable/Writable
BGR0
Write
Read
Baud rate generator register 0
Write to reload counter bits 0-7
Read BGR0 setting value
BGR1
Write
Read
Baud rate generator register 1
Write to reload counter bits 8-14
Read BGR1 setting value
EXT
0
1
External clock selection bit
Uses internal clock
Uses external clock
• The baud rate generator registers are used to set a division ratio for the serial clock.
• BGR1 and BGR0 correspond to the upper bits and lower bits respectively and they can write a reload
value to be counted as well as read BGR1/BGR0 setting values.
• The reload counter starts counting when a reload value is written to the baud rate generator registers
(BGR1/BGR0).
• The EXT bit (bit15) is used to determine whether the internal clock or external clock should be used as
the clock source for the reload counter. Setting EXT to "0" selects the internal clock, while setting EXT
to "1" selects the external clock.
436
FUJITSU SEMICONDUCTOR LIMITED
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MB91490 Series
CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.4 Registers of UART (Asynchronous Serial Interface)
Notes:
• Use 16-bit access to write to the baud rate generator registers 1, 0 (BGR1, BGR0).
• When a setting value of the baud rate generator registers 1, 0 (BGR1, BGR0) is changed, the
new setting value is not reloaded until the counter value becomes "0000H". To make the new
setting value valid immediately, therefore, execute a programmable clear (UPCL) operation after
changing the BGR1/BGR0 setting value.
• When the reload value is even-numbered, the "L" width of the reception serial clock is one
peripheral clock (CLKP) cycle longer than the "H" width of the same serial clock. When the reload
value is odd-numbered, the "L" width is the same as the "H" width.
• Select 4 or a larger value for BGR1/BGR0. However, data may not be able to be received
properly, due to a baud rate error or reload settings.
• To change the setting to the external clock (EXT = 1) during the operation of the baud rate
generator, write "0" to baud rate generator registers 1, 0 (BGR1, BGR0), execute a programmable
clear (UPCL) operation, and then set to the external clock (EXT = 1).
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.5 Interrupts of UART
14.5
MB91490 Series
Interrupts of UART
The UART has the transmission/reception interrupt functionality. The following sources
can be used to generate interrupt requests.
• When reception data is set in the reception data register (RDR) or a reception error
occurs
• When transmission data is transferred from the transmission data register (TDR) to
the transmission shift register and then transmission starts
• Transmission bus idle state (no transmission operation)
■ Interrupts of UART
Table 14.5-1 shows the interrupt control bits and interrupt sources of the UART.
Table 14.5-1 Interrupt Control Bits and Interrupt Sources of UART
Interrupt
type
Reception
Interrupt
Flag
request
register
flag bit
Operation
mode
0
1
Interrupt source
RDRF
SSR
❍
❍
Reception of 1 byte
ORE
SSR
❍
❍
Overrun error
FRE
SSR
❍
❍
Framing error
PE
SSR
❍
×
Parity error
TDRE
SSR
❍
❍
Transmission register
being empty
TBI
SSR
❍
❍
No transmission operation
Transmission
Interrupt
source
enable bit
Clearing of interrupt request
flag
Reading reception data (RDR)
SCR:RIE
Writing "1" to the reception error
flag clear bit (SSR:REC)
SCR:TIE
Writing to transmission data
(TDR)
(Transmission again)*
Writing to transmission data
SCR:TBIE (TDR)
(Transmission again)*
*: Wait until the TDRE bit becomes "0" before setting the TIE bit to "1".
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.5 Interrupts of UART
MB91490 Series
14.5.1
Occurrence of Reception Interrupts and Flag Set Timing
Reception interrupts are generated by the completion of reception (SSR:RDRF) and the
occurrence of a reception error (SSR:PE, ORE, FRE).
■ Occurrence of Reception Interrupts and Flag Set Timing
Reception data is stored to the reception data register (RDR) when the first stop bit is detected. Each flag is
set when the reception has been completed (SSR:RDRF = 1) or a reception error has occurred (SSR:PE,
ORE, FRE = 1). If reception interrupts have been enabled (SSR:RIE = 1), a reception interrupt will occur.
Note:
If a reception error occurs, the data in the reception data register (RDR) will become invalid.
Figure 14.5-1 Timing for Setting RDRF (Reception Data Full) Flag Bit
ST
Reception data
D0
D1
D5
D2
D6
D7
SP
ST
RDRF
Occurrence of reception interrupt
Figure 14.5-2 Timing for Setting FRE (Framing Error) Flag Bit
Reception data
ST
D0
D1
D5
D2
D6
D7
SP
ST
RDRF
FRE
Occurrence of reception interrupt
Notes: • A framing error occurs when the level of the first stop bit is "L".
• Although RDRF is set to "1" and data is received when a framing error occurs, the received data will be invalid.
Figure 14.5-3 Timing for Setting ORE (Overrun Error) Flag Bit
Reception data
ST D0
D1
D2 D3
D4
D5
D6 D7
SP
ST
D0
D1 D2
D3
D4
D5
D6 D7
SP
RDRF
ORE
Note: An overrun error occurs when the next data is transferred before reception data is read (RDRF = 1).
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.5 Interrupts of UART
MB91490 Series
Occurrence of Transmission Interrupts and Flag Set
Timing
14.5.2
A transmission interrupt occurs when transmission data is transferred from the
transmission data register (TDR) to the transmission shift register (SSR:TDRE = 1) and
then the transmission starts, or when no transmission operation is in progress
(SSR:TBI = 1).
■ Occurrence of Transmission Interrupts and Flag Set Timing
● Timing for setting the transmission data empty flag (TDRE)
It is enabled to write the next data (SSR:TDRE = 1), when the data written to the transmission data register
(TDR) is transferred to the transmission shift register. At this point, a transmission interrupt will occur, if
transmission interrupts have been enabled (SCR:TIE = 1). As the TDRE bit is a read only bit, it is cleared
by writing "0" to the transmission data register (TDR).
Figure 14.5-4 Timing for Setting Transmission Data Empty Flag (TDRE)
Occurrence of transmission interrupt
Transmission data
(modes 0 and 1)
ST
D0
D1 D2
D3
Occurrence of transmission interrupt
D4 D5 D6
D7
SP ST
D0 D1
D2
TDRE
Writing to TDR
ST:
Start bit
D0 to D7: Data bits
SP:
Stop bit
● Timing for setting the transmission bus idle flag (TBI)
The SSR:TBI bit is set to "1", when the transmission data register is empty (TDRE = 1) and no
transmission operation is in progress. At this point, a transmission interrupt occurs if transmission bus idle
interrupts have been enabled (SCR:TBIE = 1). The TBI bit and transmission interrupt request are cleared
when transmission data is set to the transmission data register (TDR).
Figure 14.5-5 Timing for Setting Transmission Bus Idle Flag (TBI)
Transmission data
ST D0 D1 D2 D3 D4 D5 D6 D7 SP
ST D0 D1 D2 D3 D4 D5 D6 D7 SP
TBI
Transmission interrupt
generated by TBI bit
TDRE
Writing to
TDR
ST:
Start bit
D0 to D7: Data bits
SP:
Stop bit
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.6 Operation of UART
MB91490 Series
14.6
Operation of UART
The UART operates in two-way serial asynchronous communications for mode 0 and in
master/slave multi-processor communications for mode 1.
■ Operation of UART
● Transmission/reception data format
• Transmission and reception data is transmitted or received for a specified data bit length, always starting
from the start bit and finishing with the stop bit (at least 1 bit).
• The data transfer direction (LSB or MSB first) is determined by the BDS bit in the serial mode register
(SMR). When the addition of parity is selected, the parity bit is always placed between the last data bit
and the first stop bit.
• The addition or omission of parity can be selected in operation mode 0 (normal mode).
• In operation mode 1 (multi-processor mode), the AD bit is added rather than parity.
Figure 14.6-1 shows transmission/reception data formats for operation modes 0 and 1.
Figure 14.6-1 Examples of Transmission/Reception Data Formats (Operation Modes 0 and 1)
[Operation mode 0]
ST
D0
D1
D2
D3
D4
D5
D6
D7
SP1 SP2
ST
D0
D1
D2
D3
D4
D5
D6
D7
SP1
No parity
8-bit data
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP1 SP2
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP1
ST
D0
D1
D2
D3
D4
D5
D6
SP1 SP2
ST
D0
D1
D2
D3
D4
D5
D6
SP1
ST
D0
D1
D2
D3
D4
D5
D6
P
SP1 SP2
ST
D0
D1
D2
D3
D4
D5
D6
P
SP1
ST
D0
D1
D2
D3
D4
D5
D6
D7
AD
SP1 SP2
ST
D0
D1
D2
D3
D4
D5
D6
D7
AD
SP1
ST
D0
D1
D2
D3
D4
D5
D6
AD
SP1 SP2
ST
D0
D1
D2
D3
D4
D5
D6
AD
SP1
Parity
No parity
7-bit data
Parity
[Operation mode 1]
8-bit data
ST:
SP:
P:
AD:
D:
Start bit
Stop bit
Parity bit
Address bit
Data bit
CM71-10155-2E
7-bit data
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.6 Operation of UART
MB91490 Series
Notes:
• Figure 14.6-1 shows cases where the data length is set to 7 or 8 bits. (The data length can be set
to 5-9 bits for operation mode 0.)
• When the BDS bit in the serial mode register (SMR) is set to "1" (MSB first), the bits are
processed in the following order: D7, D6, D5...D1, D0 (P).
• When the data length is set to X bits, the lower X bits of the transmission/reception data register
(RDR/TDR) become valid.
● Transmission operation
• Transmission data can be written to the transmission data register (TDR) when the transmission data
empty flag bit (TDRE) in the serial status register (SSR) is set to "1".
• Writing transmission data to the transmission data register (TDR) sets the transmission data empty flag
bit (TDRE) to "0".
• When the transmission operation enable bit in the serial control register (SCR:TXE) is set to "1",
transmission data is loaded to the transmission shift register and the transmission starts from the start bit.
• Once transmission starts, the transmission data empty flag bit (TDRE) is set back to "1". At this point, a
transmission interrupt will occur if transmission interrupts have been enabled (SCR:TIE = 1). The next
transmission data can be written to the transmission data register through interrupt processing.
Note:
The initial value of the transmission data empty flag bit (SSR:TDRE) is "1". Therefore, a transmission
interrupt occurs immediately after transmission interrupts are enabled (SCR:TIE).
● Reception operation
• Reception operation starts when such operation is enabled (SCR:RXE = 1).
• When a start bit is detected, one frame of data is received according to the data format set in the
extended communication control register (ESCR:PEN, P, L2, L1, L0) and the serial mode register
(SMR:BDS).
• Once one frame of data has been received, the reception data full flag bit (SSR:RDRF) is set to "1". At
this point, a reception interrupt will occur if reception interrupts have been enabled (SCR:RIE = 1).
• Read reception data after one frame of data has been received, and then check the error flag status of the
serial status register (SSR). If a reception error is occurring, the error must be treated.
• Reading reception data clears the reception data full flag bit (SSR:RDRF) to "0".
Note:
The data in the reception data register (RDR) will become valid, if no reception error occurs
(SSR:PE, ORE, FRE = 0) when the reception data register full flag bit (SSR:RDRF) is set to "1".
● Clock selection
• The internal clock or external clock can be used.
• To use the external clock, set BGR:EXT to "1". In this case, the external clock is divided by the baud
rate generator.
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.6 Operation of UART
MB91490 Series
● Detection of the start bit
• In asynchronous mode, a start bit is identified by the falling edge of a SIN signal. Therefore, even when
reception operation has been enabled (SCR:RXE = 1), such operation will not start unless the falling
edge of a SIN signal is input.
• When the falling edge of a start bit is detected, the reception reload counter of the baud rate generator is
reset and reloaded to start counting down. This allows sampling to be always performed using the
central part of data.
Start bit
Data bit
SIN
SIN
(already sampled)
SEDGE
(internal signal)
Reload counter
reset
Data sampling
Reception
sampling clock
1 bit time
● Stop bit
• 1 bit or 2 bits can be selected for the bit length.
• The reception data full flag bit (SSR:RDRF) is set to "1" when the first stop bit is detected.
● Detection of errors
• In operation mode 0, parity errors, overrun errors and frame errors can be detected.
• In operation mode 1, overrun errors and frame errors can be detected. Parity errors, on the other hand,
cannot be detected.
● Parity bit
• Addition of the parity bit can be selected only in operation mode 0. The parity enable bit (ESCR:PEN)
can be used to determine the addition or omission of parity, while the parity selection bit (ESCR:P) can
be used to select even parity or odd parity.
• Parity cannot be used in operation mode 1.
Figure 14.6-2 shows transmission/reception data when parity is valid.
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.6 Operation of UART
MB91490 Series
Figure 14.6-2 Operation when Parity is Valid
ST
D0
D1
D2
D4
D3
D5
D6
D7
P
SP
Parity error occurring at
even parity in reception
(ESCR: P=0)
Reception data
(mode 0)
SSR: PE
Transmission data
(mode 0)
Transmission of even parity
(ESCR: P=0)
Transmission data
(mode 0)
Transmission of odd parity
(ESCR: P=1)
ST: Start bit
SP: Stop bit
With parity (ESCR: PEN = 1) when the bit length is 8 bits.
Note: Parity cannot be used in operation mode 1.
● Data signaling system
The NRZ (Non Return to Zero) signaling system (ESCR:INV = 0) or the inverted NRZ signaling system
(ESCR:INV = 1) can be selected by setting the INV bit in the extended communication control register.
Figure 14.6-3 shows the NRZ and inverted NRZ signaling systems.
Figure 14.6-3 NRZ (Non Return to Zero) and Inverted NRZ Signaling Systems
SIN (NRZ)
INV = 0
ST
D0
D1
D2
D3
D4
D5
D6
D7
SP
SIN (inverted NRZ)
INV = 1
ST
D0
D1
D2
D3
D4
D5
D6
D7
SP
SOT (NRZ)
INV = 0
ST
D0
D1
D2
D3
D4
D5
D6
D7
SP
SON (inverted NRZ)
INV = 1
ST
D0
D1
D2
D3
D4
D5
D6
D7
SP
● Data transfer system
LSB-first or MSB-first data bit transfer system can be selected.
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.7 Dedicated Baud Rate Generator
MB91490 Series
14.7
Dedicated Baud Rate Generator
One of the following options can be selected for the transmission/reception clock
source of the UART.
• Dedicated baud rate generator (reload counter)
• External clock input to the baud rate generator (reload counter)
■ UART Baud Rate Selection
One of the following two options can be selected for the baud rate.
● Baud rate achieved by dividing the internal clock using the dedicated baud rate generator (reload
counter)
There are two internal reload counters, and both support the transmission/reception serial clock. The baud
rate can be selected via the 15-bit reload value determined by the baud rate generator registers 1, 0 (BGR1,
BGR0).
The reload counter divides the internal clock, according to the set value.
To set the clock source, select the internal clock (SMR:EXT = 0).
● Baud rate achieved by dividing the external clock using the dedicated baud rate generator (reload
counter)
The external clock is used as the clock source for the reload counter.
The baud rate can be selected via the 15-bit reload value determined by the baud rate generator registers 1,
0 (BGR1, BGR0).
The reload counter divides the external clock, according to the set value.
To set the clock source, select the external clock and the baud rate generator clock (SMR:EXT = 1).
This mode is made available on the assumption that an oscillator with a special frequency is divided for
use.
Notes:
• Set the external clock (EXT = 1) while the reload counter is stopped (BGR1/BGR0 = 15’h00).
• When the external clock has been selected (EXT = 1), the "H" and "L" widths of the external clock
must be two or more peripheral clocks (CLKP).
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.7 Dedicated Baud Rate Generator
14.7.1
MB91490 Series
Setting Baud Rate
This section describes how the baud rates are set and the resulting serial clock
frequency is calculated.
■ Calculating the Baud Rate
The two 15-bit reload counters are set by the baud rate generator registers 1, 0 (BGR1, BGR0).
The following formula should be used to calculate a baud rate.
(1) Reload value:
V =  / b -1
V: Reload value
b: Baud rate
: Peripheral clock (CLKP), external clock frequency
(2)Example of calculation
If the peripheral clock (CLKP) is 16MHz, the internal clock is used, and the baud rate is
19200bps, the reload value will be:
Reload value:
V = (16  1000000)/19200 - 1 = 832
As a result, the baud rate is:
b = (16  1000000)/(832+1) = 19208 bps
(3) Baud rate error
The following formula is used to calculate a baud rate error.
Error(%) = (calculated value - target value) / target value  100
Example: peripheral clock (CLKP) = 20MHz, target baud rate = 153600bps
Reload value = (20  1000000)/153600 - 1 = 129
Baud rate (calculated value) = (20  1000000)/(129+1) = 153846 (bps)
Error (%) = (153846 - 153600)/153600  100 = 0.16 (%)
Notes:
• The reload counter halts when the reload value is set to "0".
• When the reload value is even-numbered, the "L" width of the reception serial clock is one
peripheral clock (CLKP) cycle longer than the "H" width of the same serial clock. When the reload
value is odd-numbered, the "L" width is the same as the "H" width.
• Select 4 or a larger value for the reload value. However, data may not be able to be received
properly, due to a baud rate error or reload settings.
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.7 Dedicated Baud Rate Generator
MB91490 Series
■ Reload Values and Baud Rates for Different Peripheral Clock (CLKP) Frequencies
Table 14.7-1 Reload Values and Baud Rates
8 MHz
10 MHz
16 MHz
20 MHz
24 MHz
32MHz
Baud rate
(bps)
Value
ERR
Value
ERR
Value
ERR
Value
ERR
Value
ERR
Value
ERR
4M
-
-
-
-
-
0
4
0
5
0
7
0
2.5M
-
-
-
0
-
-
-
-
-
-
-
-
2M
-
0
4
0
7
0
9
0
11
0
15
0
1M
7
0
9
0
15
0
19
0
23
0
31
0
500000
15
0
19
0
31
0
39
0
47
0
63
0
460800
-
-
-
-
-
-
-
-
51
-0.16
-
-
250000
31
0
39
0
63
0
79
0
95
0
127
0
230400
-
-
-
-
-
-
-
-
103
-0.16
-
-
153600
51
-0.16
64
-0.16
103
-0.16
129
-0.16
155
-0.16
207
-0.16
125000
63
0
79
0
127
0
159
0
191
0
255
0
115200
68
-0.64
86
0.22
138
0.08
173
0.22
207
-0.16
277
0.08
76800
103
-0.16
129
-0.16
207
-0.16
259
-0.16
311
-0.16
416
0.08
57600
138
0.08
173
0.22
277
0.08
346
-0.16
416
0.08
555
0.08
38400
207
-0.16
259
-0.16
416
0.08
520
0.03
624
0
832
-0.04
28800
277
0.08
346
<0.01
554
-0.01
693
-0.06
832
-0.03
1110
-0.01
19200
416
0.08
520
0.03
832
-0.03
1041
0.03
1249
0
1666
0.02
10417
767
<0.01
959
<0.01
1535
<0.01
1919
<0.01
2303
<0.01
3071
<0.01
9600
832
0.04
1041
0.03
1666
0.02
2083
0.03
2499
0
3332
-0.01
7200
1110
<0.01
1388
<0.01
2221
<0.01
2777
<0.01
3332
<0.01
4443
-0.01
4800
1666
0.02
2082
-0.02
3332
<0.01
4166
<0.01
4999
0
6666
<0.01
2400
3332
<0.01
4166
<0.01
6666
<0.01
8332
<0.01
9999
0
13332
<-0.01
1200
6666
<0.01
8334
0.02
13332
<0.01
16666
<0.01
19999
0
26666
<0.01
600
13332
<0.01
16666
<0.01
26666
<0.01
-
-
-
-
-
-
300
26666
26666
<0.01
-
-
-
-
-
-
-
-
-
• Value: the value set in BGR1/BGR0 registers (decimal)
• ERR: baud rate error (%)
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.7 Dedicated Baud Rate Generator
MB91490 Series
■ Acceptable Baud Rate Range for Reception
The following figure shows the range of acceptable baud rate differences at the transmission destination
during reception.
The following calculation formula must be used to set a baud rate error for reception within the acceptable
error range.
Figure 14.7-1 Acceptable Baud Rate Range for Reception
Sampling
UART transfer rate
Start
Bit 0
Bit 1
Bit 7
Parity
Stop
FL
1 data frame (11 x FL)
Minimum acceptable
transfer rate
Start
Bit 0
Bit 1
Bit 7
Stop
Parity
FLmin
Maximum acceptable
transfer rate
Start
Bit 0
Bit 1
Bit 7
Parity
Stop
FLmax
As shown in the figure, the sampling timing for reception data is determined by the counter selected by the
BGR1/BGR0 registers after a start bit is detected. If all data including the last data (stop bit) can fit in this
sampling timing, reception can be performed successfully.
In theory, the following is expected when this is applied to 11-bit reception.
When the sampling timing margin is equivalent of two clocks of the peripheral clock (CLKP) (), the
minimum acceptable transfer rate (FLmin) is as follows:
FLmin = (11 bits  (V + 1) - (V + 1)/2 + 2)/ = (21V + 25)/2 (s)
V: reload value
: peripheral clock (CLKP)
Consequently, the maximum receivable baud rate at the transmission destination (BGmax) is as follows:
BGmax = 11/FLmin = 22/(21V+25) (bps)
V: reload value
: peripheral clock (CLKP)
Likewise, the maximum acceptable transfer rate (Flmax) can be calculated as shown below:
FLmax = (11 bits  (V + 1) + (V + 1)/2 - 2)/ = (23V + 19)/2 (s)
V: reload value
: peripheral clock (CLKP)
Consequently, the minimum receivable baud rate at the transmission destination (BGmin) is as follows:
BGmin = 11/FLmax = 22/(23V+19) (bps)
V: reload value
: peripheral clock (CLKP)
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.7 Dedicated Baud Rate Generator
MB91490 Series
Based on the aforementioned calculation formulas for the minimum/maximum baud rates, the acceptable
baud rate error between the UART and transmission destination can be calculated as shown below.
Table 14.7-2 Acceptable Baud Rate Error
Reload value (V)
Maximum acceptable
baud rate error
Minimum acceptable
baud rate error
3
0%
0
10
+2.98%
-2.81%
50
+4.37%
-4.02%
100
+4.56%
-4.18%
200
+4.66%
-4.26%
32767
+4.76%
-4.35%
Note:
The accuracy of reception depends on the number of bits per frame, the peripheral clock (CLKP) and
the reload value. The accuracy becomes higher as the peripheral clock (CLKP) and the division ratio
become higher.
■ External Clock
The baud rate generator divides the external clock, when "1" is written to the EXT bit in the baud rate
generator register 1, 0 (BGR1, BGR0).
Note:
The UART synchronizes external clock signals with the internal clock. Therefore, the operation
becomes unstable when an external clock which cannot be synchronized is used.
■ Functions of Reload Counters
There are two reload counters, a transmission reload counter and a reception reload counter, which function
as a dedicated baud rate generator. Structured in a 15-bit register configuration based on a reload value,
these counters generate a transmission/reception clock from the external or internal clock.
■ Starting a Count
The reload counter starts a count when a reload value is written to the baud rate generator registers 1, 0
(BGR1, BGR0).
■ Restart
The reload counter restarts under the following conditions.
• For both transmission and reception reload counters
- Programmable reset (SCR:UPCL bit)
• For reception reload counter
- Detecting the falling edge of a start bit in asynchronous mode
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.8 Setup Procedure and Program Flow for Operation Mode 0
(Asynchronous Normal Mode)
14.8
MB91490 Series
Setup Procedure and Program Flow for Operation Mode 0
(Asynchronous Normal Mode)
Asynchronous serial two-way communication is enabled in operation mode 0.
■ Connection between CPUs
Two-way communication should be selected for operation mode 0 (normal mode). Two CPUs are
connected to each other, as shown in Figure 14.8-1.
Figure 14.8-1 Example of Two-way Communication Connection for UART Operation Mode 0
SOT
SOT
SIN
SIN
SCK
SCK
CPU –1 (Master)
CPU –2 (Slave)
■ Flowchart
Figure 14.8-2 Example Flowchart for Two-way Communication
(Transmission)
(Reception)
Start
Start
Setting operation mode
(set to mode 0)
Setting operation mode
(conform to
transmission)
Communicating by
setting 1-byte data
to TDR
Transmitting data
NO
RDRF=1
YES
NO
RDRF=1
YES
Reading and
processing
reception data
450
Transmitting data
(ANS)
Reading and
processing
reception data
Transmitting
1-byte data
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.9 Setup Procedure and Program Flow for Operation Mode 1
(Asynchronous Multi-processor Mode)
MB91490 Series
14.9
Setup Procedure and Program Flow for Operation Mode 1
(Asynchronous Multi-processor Mode)
In operation mode 1 (multi-processor mode), communication among multiple CPUs is
enabled through master/slave connection. The connected CPUs can be used as a
master/slave.
■ Connection among CPUs
In this master/slave communication, one master CPU and more than one slave CPU are connected to two
common communication lines, as shown in Figure 14.9-1, to configure a communication system. The
UART can be used by both the master and slaves.
Figure 14.9-1 Example Connection for UART Master/Slave Communication
SOT
SIN
Master CPU
SOT
SIN
SOT
Slave CPU #0
SIN
Slave CPU #1
■ Function Selection
For master/slave communication, select the operation mode and data transfer system shown in Table 14.91.
Table 14.9-1 Selection of Master/Slave Communication Function
Operation mode
Data
Master CPU
Address
transmission/
reception
Data transmission/
reception
Mode 1
(AD bit
transmission)
Parity
Stop bit
Bit direction
None
1 bit or 2
bits
LSB first or
MSB first
Slave CPU
Mode 1
(AD bit
reception)
AD = 1
+
7-bit or 8-bit address
AD = 0
+
7-bit or 8-bit data
Note:
Use half word access for transmission/reception data (TDR/RDR) in operation mode 1.
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.9 Setup Procedure and Program Flow for Operation Mode 1
(Asynchronous Multi-processor Mode)
● Communication procedure
MB91490 Series
Communication is started when the master CPU transmits address data, where bit D8 is treated as "1". This
data is used to select a slave CPU which will be the communication destination. Each slave CPU judges the
address data on a program, and communicates (normal data) with the master CPU when the data matches
its assigned address.
Figure 14.9-2 shows flowcharts for the master/slave communication (multi-processor mode).
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.9 Setup Procedure and Program Flow for Operation Mode 1
(Asynchronous Multi-processor Mode)
MB91490 Series
■ Flowchart
Figure 14.9-2 Example Flowchart for Master/Slave Communication
(Slave CPU)
(Master CPU)
Start
Start
Setting operation mode
(set to mode 1)
Setting operation mode
(set to mode 1)
Setting SIN pin to serial
data input
Setting SOT pin to serial
data output
Setting SIN pin to serial
data input
Setting SOT pin to serial
data output
Selecting 7 or 8 data bits
Selecting 1 or 2 stop bits
Selecting 7 or 8 data bits
Selecting 1 or 2 stop bits
Setting bit D8 to "1"
Enabling transmission/
reception operation
Enabling transmission/
reception operation
Reception byte
Transmitting slave address
Bit D8 = 1
NO
YES
NO
Setting bit D8 to "0"
Slave address
matched
YES
Communicating with
slave CPU
Communicating with
master CPU
NO
Communication
completed?
Communication
completed?
YES
NO
YES
NO
Communicating
with another slave
CPU
YES
Disabling transmission/
reception operation
End of communication
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.10 Notes on UART Mode
14.10
MB91490 Series
Notes on UART Mode
The notes for when you use the UART mode are shown below.
• To request a DMA transfer request, set the block size of DMA to one time.
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.11 CSIO (Clock Synchronous Serial Interface)
MB91490 Series
14.11
CSIO (Clock Synchronous Serial Interface)
Among all the functions of the multi-function serial interface, this section describes the
CSIO functions that are supported in operation mode 2.
• CSIO (Clock Synchronous Serial Interface)
• Overview of CSIO (Clock Synchronous Serial Interface)
• Registers of CSIO (Clock Synchronous Serial Interface)
- Serial Control Register (SCR)
- Serial Mode Register (SMR)
- Serial Status Register (SSR)
- Extended Communication Control Register (ESCR)
- Reception Data Register / Transmission Data Register (RDR/TDR)
- Baud Rate Generator Registers 1, 0 (BGR1, BGR0)
• Interrupts of CSIO (Clock Synchronous Serial Interface)
- Occurrence of Reception Interrupts and Flag Set Timing
- Occurrence of Transmission Interrupts and Flag Set Timing
• Operation of CSIO (Clock Synchronous Serial Interface)
• Dedicated Baud Rate Generator
- Setting Baud Rate
• Setup Procedure and Program Flow for CSIO (Clock Synchronous Serial Interface)
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.12 Overview of CSIO (Clock Synchronous Serial Interface)
14.12
MB91490 Series
Overview of CSIO (Clock Synchronous Serial Interface)
CSIO (Clock Synchronous Serial Interface) is a general-purpose interface for serial data
communication, which allows synchronous communications with external units (SPI
supported).
■ Functions of CSIO (Clock Synchronous Serial Interface)
Function
1
Data buffer
2
Transfer system
3
Baud rate
4
Data length
5
Reception error detection
6
Interrupt request
7
Synchronous mode
8
Pin access
456
Full-duplex double buffer
• Clock synchronization (no start bit / no stop bit)
• Master/slave function
• SPI supported (both master & slaves supported)
• Dedicated baud rate generator available (15-bit reload counter configuration, in
master operation)
• External clock can be input (in slave operation)
Variable from 5 bits to 9 bits
Overrun error
• Reception interrupt (completion of reception, overrun error)
• Transmission interrupt (transmission data empty, transmission bus idle)
• Extended intelligent I/O service (EI2OS) and DMA transfer support function are
available for both transmission and reception.
Master or slave function
Serial data output pin can be set to "1".
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.13 Registers of CSIO (Clock Synchronous Serial Interface)
MB91490 Series
14.13
Registers of CSIO (Clock Synchronous Serial Interface)
This section lists the registers of CSIO (clock synchronous serial interface).
■ List of Registers of CSIO (Clock Synchronous Serial Interface)
Figure 14.13-1 List of Registers of CSIO (Clock Synchronous Serial Interface)
Address
bit15
bit8 bit7
bit0
000062H 000063H
000072H 000073H
000082H 000083H
SCR
(serial control register)
SMR
(serial mode register)
000060H 000061H
000070H 000071H
000080H 000081H
SSR
(serial status register)
ESCR
(extended communication
control register)
000066H 000067H
CSIO 000076H 000077H
000086H 000087H
RDR/TDR
(transmission/reception
data register)
000064H 000065H
000074H 000075H
000084H 000085H
BGR1
(baud rate generator
register 1)
BGR0
(baud rate generator
register 0)
000068H 000069H
000078H 000079H
000088H 000089H
-
-
Table 14.13-1 Bit Assignment of CSIO (Clock Synchronous Serial Interface)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SCR/
SMR
UPCL
MS
SPI
RIE
TIE
TBIE
RXE
TXE
MD2
MD1
MD0
-
SCINV
BDS
SCKE
SOE
SSR/
ESCR
REC
-
-
-
ORE
RDRF
TDRE
TBI
SOP
-
-
-
-
L2
L1
L0
D8
D7
D6
D5
D4
D3
D2
D1
D0
B8
B7
B6
B5
B4
B3
B2
B1
B0
TDR/
RDR
BGR1/
BGR0
-
-
B14
CM71-10155-2E
B13
B12
B11
B10
B9
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.13 Registers of CSIO (Clock Synchronous Serial Interface)
14.13.1
MB91490 Series
Serial Control Register (SCR)
The serial control register (SCR) enables/disables transmission/reception interrupts,
transmission idle interrupts and transmission/reception operations. This register can
also set SPI connection and reset CSIO.
■ Serial Control Register (SCR)
Figure 14.13-2 shows the bit structure of the serial control register (SCR), and Table 14.13-2 describes the
function of each bit.
Figure 14.13-2 Bit Structure of Serial Control Register (SCR)
SCR
Address:
ch.0 000062H
ch.1 000072H
ch.2 000082H
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
UPCL
MS
SPI
RIE
TIE
TBIE
RXE
TXE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.........................................
bit7
(SMR)
00000000
Transmission enable bit
Disables transmission
Enables transmission
RXE
0
1
Reception enable bit
Disables reception
Enables reception
TBIE
Transmission bus idle interrupt enable bit
Disables transmission bus idle interrupt
Transmission interrupt enable bit
Disables transmission interrupt
Enables transmission interrupt
RIE
0
1
Reception interrupt enable bit
Disables reception interrupt
Enables reception interrupt
SPI
0
1
SPI support bit
Normal synchronous transfer
SPI supported
MS
0
1
Master/slave function selection bit
Master mode
Slave mode
0
1
B
Enables transmission bus idle interrupt
TIE
0
1
UPCL
: Readable/Writable
Initial value
TXE
0
1
0
1
R/W
bit0
Programmable clear bit
Write
Read
No effect
"0" is always read.
Programmable clear operation
: Initial value
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MB91490 Series
CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.13 Registers of CSIO (Clock Synchronous Serial Interface)
Table 14.13-2 Functional Description of Each Bit of Serial Control Register (SCR)
Bit name
Function
This bit is used to initialize the internal state of the CSIO.
Setting the bit to "1":
• The CSIO will be reset directly (software reset). The register setting, however,
will be retained. In this case, communication of the data which is being
transmitted or received will be cut off immediately.
bit15
UPCL:
Programmable clear
bit
• The baud rate generator will reload the value set in BGR1/BGR0 registers, and
then restart the operation.
• All the transmission/reception interrupt sources (TDRE, TBI, RDRF and ORE)
will be initialized.
• Setting the bit to "0": No effect on the operation
• Reading this bit always returns "0".
Note:
Execute the programmable clear operation after disabling interrupts.
bit14
MS:
Master/slave function
selection bit
This bit is used to select master or slave mode.
Setting the bit to "0" selects master mode.
Setting the bit to "1" selects slave mode.
Note:
The external clock will be input directly, if SMR:SCKE is set to "0" when slave
mode is selected.
bit13
SPI:
SPI support bit
This bit is used to enable communication supporting SPI.
Setting the bit to "0" enables normal synchronous communication.
Setting the bit to "1" enables SPI support.
bit12
RIE:
Reception interrupt
enable bit
bit11
TIE:
Transmission
interrupt enable bit
bit10
TBIE:
Transmission bus idle
interrupt enable bit
bit9
bit8
• This bit is used to enable/disable the output of reception interrupt requests to the
CPU.
• A reception interrupt request is output when the RIE bit and the reception data
flag bit (RDRF) are set to "1", or when any of the error flag bits (ORE) is set to
"1".
• This bit is used to enable/disable the output of transmission interrupt requests to
the CPU.
• A transmission interrupt request is output when the TIE and TDRE bits are set to
"1".
• This bit is used to enable/disable the output of transmission bus idle interrupt
requests to the CPU.
• A transmission bus idle interrupt request is output when the TBIE and TBI bits
are set to "1".
RXE:
Reception enable bit
This bit is used to enable/disable CSIO reception operation.
Setting the bit to "0" disables data frame reception operation.
Setting the bit to "1" enables data frame reception operation.
Note:
If the reception operation is disabled (RXE = 0) during the reception, the
operation will be terminated immediately.
TXE:
Transmission enable
bit
This bit is used to enable/disable CSIO transmission operation.
Setting the bit to "0" disables data frame transmission operation.
Setting the bit to "1" enables data frame transmission operation.
Note:
If the transmission operation is disabled (TXE = 0) during the transmission, the
operation will be terminated immediately.
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.13 Registers of CSIO (Clock Synchronous Serial Interface)
14.13.2
MB91490 Series
Serial Mode Register (SMR)
The serial mode register (SMR) sets the operation mode, selects the transfer direction,
data length and serial clock inversion, and enables or disables the output to the serial
data and serial clock pins.
■ Serial Mode Register (SMR)
Figure 14.13-3 shows the bit structure of the serial mode register (SMR), and Table 14.13-3 describes the
function of each bit.
Figure 14.13-3 Bit Structure of Serial Mode Register (SMR)
SMR
bit15
.....................................
bit8
bit7
bit6
bit5
bit4
MD2 MD1 MD0
(SCR)
Address:
ch.0 000063H
ch.1 000073H
ch.2 000083H
R/W
SOE
0
1
R/W
-
R/W
R/W
bit3
SCINV
R/W
bit1
bit0
BDS SCKE
bit2
SOE
R/W
R/W
Initial value
000-0000 B
R/W
Serial data output enable bit
Disables the output of SOT
Enables the output of SOT
SCKE
Serial clock output enable bit
1
Disables the output of SCK
or
Enables the input of SCK
Enables the output of SCK
BDS
0
1
Transfer direction selection bit
LSB first ( Transfer starting from the least significant bit)
MSB first ( Transfer starting from the most significant bit)
0
SCINV
0
1
Serial clo ck inversion bit
Mark level "H" format
Mark level "L" format
Undefined bit
Read : undefined value. Write: no effect .
R/W
: Readable/Writable
-
: Undefined
: Initial value
MD2 MD1 MD0
Operation mode setting bits
0
0
0
Operation mode 0 (asynchronous normal mode)
0
0
1
Operation mode 1 ( asynchronous multi-processor mode )
0
1
0
Operation mode 2 (clock synchronization mode)
1
0
0
Operation mode 4 (I 2C mode)
Note: This section describes the registers and operations of operation mode 2.
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.13 Registers of CSIO (Clock Synchronous Serial Interface)
Table 14.13-3 Functional Description of Each Bit of Serial Mode Register (SMR)
Bit name
bit7
to
bit5
MD2 to MD0:
Operation mode
setting bits
bit4
Undefined bit
Function
These bits are used to select the operation mode.
"000B": Selects operation mode 0 (asynchronous normal mode)
"001B": Selects operation mode 1 (asynchronous multi-processor mode)
"010B": Selects operation mode 2 (clock synchronization mode)
"100B": Selects operation mode 4 (I2C mode)
This section describes the registers and operations of operation mode 2 (clock
synchronization mode).
Note:
Settings other than above are prohibited.
To switch the operation mode, execute the programmable clear operation first
(SCR:UPCL = 1).
And then, after setting the operation mode, set each register.
Read: undefined value
Write: no effect
This bit is used to invert the serial clock format.
Setting the bit to "0":
• Changes the mark level of the serial clock output to "H".
• Transmission data is output, being synchronized with the falling edge (normal
transfer) or the rising edge (SPI transfer) of the serial clock.
bit3
SCINV:
Serial clock inversion
bit
• Reception data is sampled at the rising edge (normal transfer) or the falling edge
(SPI transfer) of the serial clock.
Setting the bit to "1":
• Changes the mark level of the serial clock output to "L".
• Transmission data is output, being synchronized with the rising edge (normal
transfer) or the falling edge (SPI transfer) of the serial clock.
• Reception data is sampled at the falling edge (normal transfer) or the rising edge
(SPI transfer) of the serial clock.
bit2
BDS:
Transfer direction
selection bit
bit1
SCKE:
Serial clock output
enable bit
bit0
SOE:
Serial data output
enable bit
Note:
Set this bit when transmission and reception are disabled (TXE = RXE = 0).
This bit is used to determine the transfer priority for transfer serial data: whether the
least significant bit should be transferred first (LSB first, BDS = 0) or the most
significant bit should be transferred first (MSB first, BDS = 1).
Note:
Set this bit when transmission and reception are disabled (TXE = RXE = 0).
This bit is used to control the I/O port of the serial clock.
Setting the bit to "0":
The output of SCK "H" or the input of SCK will be enabled. To use it as a
SCK input, set a general-purpose I/O port as the input port.
Setting the bit to "1" enables the output of SCK.
This bit is used to enable/disable the output of serial data.
Setting the bit to "0" enables the output of the "H" level of SOT.
Setting the bit to "1" enables the output of SOT.
Note:
The operation mode must be set first. Otherwise, the other registers will be initialized when the
operation mode is changed. Note, however, that when SCR and SMR are written simultaneously
with 16-bit write access, SCR reflects the written content.
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.13 Registers of CSIO (Clock Synchronous Serial Interface)
14.13.3
MB91490 Series
Serial Status Register (SSR)
The serial status register (SSR) checks the transmission/reception status, and also
checks and clears the reception error flag.
■ Serial Status Register (SSR)
Figure 14.13-4 shows the bit structure of the serial status register (SSR) and Table 14.13-4 describes the
function of each bit.
Figure 14.13-4 Bit Structure of Serial Status Register (SSR)
SSR
Address:
ch.0 000060H
ch.1 000070H
ch.2 000080H
bit15
bit14
bit13
bit12
REC
-
-
-
R/W
-
-
-
bit11
bit9
bit8
ORE RDRF TDRE
TBI
R
bit10
R
R
...................................
bit7
bit0
(ESCR)
Initial value
0---0011 B
R
TBI
0
1
TDRE
0
Transmission bus idle flag bit
Transmission in progress
No transmission operation
1
Transmission data empty flag bit
The transmission data register (TDR) contains data.
The transmission data register is empty.
RDRF
0
1
Reception data full flag bit
The reception data register (RDR) is empty.
The reception data register (RDR) contains data.
ORE
0
1
Overrun error flag bit
No overrun error
Overrun error
Undefined bits
Read : undefined value. Write: no effect .
REC
R/W
R
-
462
: Readable/Writable
: Read only
: Undefined
: Initial value
0
1
Reception error flag clear bit
Write
Read
No effect
"0" is always read .
Clears the reception
error flag (FRE, ORE)
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MB91490 Series
CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.13 Registers of CSIO (Clock Synchronous Serial Interface)
Table 14.13-4 Functional Description of Each Bit of Serial Status Register (SSR)
Bit name
Function
This bit is used to clear the ORE flag in the serial status register (SSR).
bit15
REC:
Reception error flag
clear bit
• Writing "1" clears the error flag.
• Writing "0" has no effect.
Reading this bit always returns "0".
bit14
to
bit12
bit11
Undefined bits
ORE:
Overrun error flag bit
Read: undefined value
Write: no effect
• This bit is set to "1" when an overrun occurs during reception. The bit is cleared
by writing "1" to the REC bit in the serial status register (SSR).
• A reception interrupt request is output when the ORE and RIE bits are set to "1".
• When this flag is set, the data in the reception data register (RDR) is invalid.
• This flag indicates the status of the reception data register (RDR).
bit10
RDRF:
Reception data full
flag bit
• The bit is set to "1" when reception data is loaded to RDR. The bit is cleared to
"0" when the reception data register (RDR) is read.
• A reception interrupt request is output when the RDRF and RIE bits are set to
"1".
• This flag indicates the status of the transmission data register (TDR).
bit9
TDRE:
Transmission data
empty flag bit
• When transmission data is written to TDR, the bit becomes "0", indicating that
TDR contains valid data. When the data is loaded to the transmission shift
register and transmission starts, the bit becomes "1", indicating that TDR no
longer contains any valid data.
• A transmission interrupt request is output when the TDRE and TIE bits are set to
"1".
• The TDRE bit becomes "1" when the UPCL bit in the serial control register
(SCR) is set to "1".
• This bit indicates that the CSIO is not performing transmission operation.
• The bit is set to "0" when data is written to the transmission data register (TDR).
bit8
TBI:
Transmission bus idle
flag bit
• The bit is set to "1" when the transmission data register (TDR) is empty (TDRE
= 1) and no transmission operation is in progress.
• The TDRE bit becomes "1" when the UPCL bit in the serial control register
(SCR) is set to "1".
• A transmission interrupt request is output when this bit is "1" and a transmission
bus idle interrupt is enabled (SCR:TBIE = 1).
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.13 Registers of CSIO (Clock Synchronous Serial Interface)
MB91490 Series
Extended Communication Control Register (ESCR)
14.13.4
The extended communication control register (ESCR) can be used to set the
transmission/reception data length and fix the serial output to "H".
■ Bit Structure of the Extended Communication Control Register (ESCR)
Figure 14.13-5 shows the bit structure of the extended communication control register (ESCR) and Table
14.13-5 describes the function of each bit.
Figure 14.13-5 Bit Structure of Extended Communication Control Register (ESCR)
ESCR
bit15
.........................................
Address :
ch.0 000061
ch.1 000071
ch.2 000081
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SOP
-
-
-
-
L2
L1
L0
R/W
-
-
-
-
R/W
R/W
Initial value
0----000 B
R/W
H
H
H
L2
0
0
0
0
1
L1
0
0
1
1
0
L0
0
1
0
1
0
Data length selection bits
8-bit length
5-bit length
6-bit length
7-bit length
9-bit length
Undefined bits
Read : undefined value. Write: no effect .
R/W
-
: Readable/Writable
: Undefined
: Initial value
464
SOP
0
1
Se rial output pin setting bit
Read
Write
No ef fect
"0" is always read.
Sets SOT pin to "H"
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MB91490 Series
CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.13 Registers of CSIO (Clock Synchronous Serial Interface)
Table 14.13-5 Functional Description of Each Bit of Extended Communication Control Register (ESCR)
Bit name
bit7
bit6
to
bit3
SOP:
Serial output pin
setting bit
Undefined bits
Function
• This bit is used to set the serial output pin to "H". The SOT pin is set to "H"
when "1" is written to this bit. It is not necessary to write "0" to this bit after that.
• Reading this bit always returns "0".
Note:
Do not set this bit during serial data transmission.
Read: undefined value
Write: no effect
These bits are used to specify a data length for transmission/reception data.
Selecting "000B" sets the data length to 8 bits.
Selecting "001B" sets the data length to 5 bits.
bit2
to
bit0
L2 to L0:
Data length selection
bits
Selecting "010B" sets the data length to 6 bits.
Selecting "011B" sets the data length to 7 bits.
Selecting "100B" sets the data length to 9 bits.
Note:
Settings other than above are prohibited.
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.13 Registers of CSIO (Clock Synchronous Serial Interface)
14.13.5
MB91490 Series
Reception Data Register / Transmission Data Register
(RDR/TDR)
The reception and transmission data registers are located at the same address. It
serves as the reception data register in read access, while it functions as the
transmission data register in write access.
■ Reception Data Register (RDR)
Figure 14.13-6 illustrates the bit structure of the serial reception register (RDR).
Figure 14.13-6 Bit Structure of Reception Data Register (RDR)
RDR
bit15...................... bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value
ch.0000066H
ch.1000076H
ch.2000086H
D8
D7
D6
D5
D4
D3
D2
D1
D0
R
R
R
R
R
R
R
R
R
00000000B
R: Read only
The reception data register (RDR) is a 9-bit data buffer register for serial data reception.
• A serial data signal sent to a serial input pin (SIN pin) is converted through the shift register and then
stored in the reception data register (RDR).
• "0" is placed in upper bits, as shown below, in accordance with the data length.
Data length
D8
D7
D6
D5
D4
D3
D2
D1
D0
9 bits
X
X
X
X
X
X
X
X
X
8 bits
0
X
X
X
X
X
X
X
X
7 bits
0
0
X
X
X
X
X
X
X
6 bits
0
0
0
X
X
X
X
X
X
5 bits
0
0
0
0
X
X
X
X
X
• The reception data full flag bit (SSR:RDRF) is set to "1" once reception data is stored in the reception
data register (RDR). A reception interrupt request will be generated if reception interrupts have been
enabled (SSR: RIE = 1).
• Read the reception data register (RDR) when the reception data full flag bit (SSR:RDRF) is "1". The
reception data full flag bit (SSR:RDRF) is cleared to "0" automatically, when the serial reception data
register (RDR) is read.
• If a reception error occurs (SSR:ORE), the data in the reception data register (RDR) becomes invalid.
• 16-bit access is used to read RDR for a 9-bit transfer.
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.13 Registers of CSIO (Clock Synchronous Serial Interface)
MB91490 Series
■ Transmission Data Register (TDR)
Figure 14.13-7 illustrates the bit structure of the transmission data register.
Figure 14.13-7 Bit Structure of Transmission Data Register (TDR)
TDR
bit15...................... bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value
ch.0 000066H
ch.1 000076H
ch.2 000086H
D8
D7
D6
D5
D4
D3
D2
D1
D0
W
W
W
W
W
W
W
W
W
11111111B
W: Write only
The transmission data register (TDR) is a 9-bit data buffer register for serial data transmission.
• If transmission data is written to the transmission data register (TDR) when transmission operation is
enabled (SCR:TXE = 1), the transmission data will be transferred to the transmission shift register,
converted into serial data and then sent from a serial data output pin (SOT pin).
• As shown below, data becomes invalid from the upper bit in accordance with the data length.
Table 14.13-6 Invalid Data of Transmission Data Register (TDR)
Data length
D8
D7
D6
D5
D4
D3
D2
D1
D0
9 bits
X
X
X
X
X
X
X
X
X
8 bits
Invalid
X
X
X
X
X
X
X
X
7 bits
Invalid
Invalid
X
X
X
X
X
X
X
6 bits
Invalid
Invalid
Invalid
X
X
X
X
X
X
5 bits
Invalid
Invalid
Invalid
Invalid
X
X
X
X
X
• The transmission data empty flag (SSR:TDRE) is cleared to "0" when transmission data is written to
the transmission data register (TDR).
• The transmission data empty flag (SSR:TDRE) will be set to "1" when transmission data is transferred
to the transmission shift register and the transmission starts.
• The next transmission data can be written when the transmission data empty flag (SSR:TDRE) is set to
"1". A transmission interrupt will occur if transmission interrupts have been enabled. Write the next
transmission data by generating a transmission interrupt or when the transmission data empty flag
(SSR:TDRE) is set to "1".
• Transmission data cannot be written to the transmission data register (TDR) when the transmission data
empty flag (SSR:TDRE) is set to "0".
• 16-bit access is used to write to TDR for a 9-bit transfer.
Note:
The transmission data register is used exclusively for writing, while the reception data register is
used exclusively for reading. The two registers have different write and read values as they are
located at the same address. Therefore, instructions such as INC/DEC instructions, which are used
for read modify write (RMW) instruction, cannot be used.
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.13 Registers of CSIO (Clock Synchronous Serial Interface)
MB91490 Series
Baud Rate Generator Registers 1, 0 (BGR1, BGR0)
14.13.6
The baud rate generator registers 1, 0 (BGR1, BGR0) are used to set a division ratio for
the serial clock.
■ Bit Structure of the Baud Rate Generator Registers 1, 0 (BGR1, BGR0)
Figure 14.13-8 shows the bit structure of the baud rate generator registers 1, 0 (BGR1, BGR0).
Figure 14.13-8 Bit Structure of Baud Rate Generator Registers 1, 0 (BGR1, BGR0)
bit15
BGR
Address:
-
BGR0
-
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
R/W
R/W
R/W
bit3
bit2
bit1
bit0
Initial value
-0000000 B
00000000 B
(BGR0)
(BGR1)
R/W
bit4
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ch.0 000065H
ch.1 000075H
ch.2 000085H
BGR1
ch.0 000064H
ch.1 000074H
ch.2 000084H
R/W : Readable/Writable
BGR0
Write
Read
Baud rate generator register 0
Write to reload counter bits 0-7
Read BGR0 setting value
BGR1
Write
Read
Baud rate generator register 1
Write to reload counter bits 8-14
Read BGR1 setting value
Undefined bit
Read : undefined value
Write: no ef fect
• A value is set to the baud rate generator registers 1, 0 (BGR1, BGR0).
• BGR0 and BGR1 correspond to the lower bits and upper bits respectively and they can write a reload
value to be counted as well as read BGR0/BGR1 setting values.
• The reload counter starts counting when a reload value is written to the baud rate generator registers 1, 0
(BGR1, BGR0).
Notes:
• Use 16-bit access to write to the baud rate generator registers 1, 0 (BGR1, BGR0).
• When the reload value is even-numbered, the "H" and "L" widths of the serial clock are as shown
below, depending on the setting of the SCINV bit. When the reload value is odd-numbered, the
"L" width is the same as the "H" width.
- SCINV = 0: The "H" width of the serial clock is 1 peripheral clock (CLKP) cycle longer.
- SCINV = 1: The "L" width of the serial clock is 1 peripheral clock (CLKP) cycle longer.
• Select 1 or a larger number for the reload value. However, select 3 or a larger value for the reload
value of the CSIO which will become the master, when using these CSIO's as the master and
slave.
• When a setting value of the baud rate generator registers 1, 0 (BGR1, BGR0) is changed, the
new setting value is not reloaded until the counter value becomes "0000H". To make the new
setting value valid immediately, therefore, execute a CSIO reset (UPCL) after changing the
BGR0/BGR1 setting value.
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.14 Interrupts of CSIO (Clock Synchronous Serial Interface)
MB91490 Series
14.14
Interrupts of CSIO (Clock Synchronous Serial Interface)
CSIO (clock synchronous serial interface) has the transmission/reception interrupt
functionality. The following sources can be used to generate interrupt requests.
• When reception data is set in the reception data register (RDR) or a reception error
occurs
• When transmission data is transferred from the transmission data register (TDR) to
the transmission shift register and then transmission starts
• Transmission bus idle state (no transmission operation)
■ Interrupts of CSIO
Table 14.14-1 lists the interrupt control bits and interrupt sources of the CSIO.
Table 14.14-1 Interrupt Control Bits and Interrupt Sources of CSIO
Interrupt
type
Interrupt
request
flag bit
Flag
register
RDRF
SSR
Interrupt source
Reception of 1 byte
Reception
Transmission
Interrupt
source
enable bit
Clearing of interrupt request flag
Reading reception data (RDR)
SCR:RIE
ORE
SSR
Overrun error
TDRE
SSR
Transmission register being empty
TBI
SSR
No transmission operation
Writing "1" to the reception error flag
clear bit (SSR:REC)
SCR:TIE
SCR:TBIE
Writing to transmission data (TDR)
(transmission again)*
Writing to transmission data (TDR)
(transmission again)*
*: Wait until the TDRE bit becomes "0" before setting the TIE bit to "1".
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.14 Interrupts of CSIO (Clock Synchronous Serial Interface)
MB91490 Series
Occurrence of Reception Interrupts and Flag Set Timing
14.14.1
Reception interrupts are generated by the completion of reception (SSR:RDRF) and the
occurrence of a reception error (SSR:ORE).
■ Occurrence of Reception Interrupts and Flag Set Timing
Reception data is stored to the reception data register (RDR) when the last data bit is detected. Each flag is
set when the reception has been completed (SSR:RDRF = 1) or a reception error has occurred (SSR:ORE =
1). If reception interrupts have been enabled (SSR:RIE = 1), a reception interrupt will occur.
Note:
If a reception error occurs, the data in the reception data register (RDR) will become invalid.
Figure 14.14-1 Reception Operation and Flag Set Timing
SCK
D0
SIN
D1
D2
D3
D4
D5
D6
D7
Sampling of
reception data
RDRF
Occurrence of
reception interrupt
Note:
The figure shows the timing based on the following conditions.
SCR: MS=1, SPI=0
ESCR: L2-L0=000 B
SMR: SCINV=0, BDS=0, SCKE=0, SOE=0
Figure 14.14-2 Timing for Setting ORE (Overrun Error) Flag
SCK
SIN
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2 D3
D4 D5 D6 D7
Sampling of
reception data
RDRF
ORE
Notes:
Occurrence of overrun error
• The figure shows the timing based on the following conditions.
SCR: MS=1, SPI=0
ESCR: L2-L0=000B
SMR: SCINV=0, BDS=0, SCKE=0, SOE=0
• An overrun error occurs when the next data is transferred before reception data is read (RDRF = 1).
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.14 Interrupts of CSIO (Clock Synchronous Serial Interface)
MB91490 Series
14.14.2
Occurrence of Transmission Interrupts and Flag Set
Timing
A transmission interrupt occurs when transmission data is transferred from the
transmission data register (TDR) to the transmission shift register (SSR:TDRE = 1) and
then the transmission starts, or when no transmission operation is in progress
(SSR:TBI = 1).
■ Occurrence of Transmission Interrupts and Flag Set Timing
● Timing for setting the transmission data empty flag (TDRE)
It is enabled to write the next data (SSR:TDRE = 1), when the data written to the transmission data register
(TDR) is transferred to the transmission shift register. At this point, a transmission interrupt will occur, if
transmission interrupts have been enabled (SCR:TIE = 1). As the TDRE bit is a read only bit, it is cleared
by writing "0" to the transmission data register (TDR).
Figure 14.14-3 Timing for Setting Transmission Data Empty Flag (TDRE)
SCK
Transmission data
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
TDRE
Writing to TDR
Occurrence of transmission interrupt
● Timing for setting the transmission bus idle flag (TBI)
The SSR:TBI bit is set to "1", when the transmission data register is empty (TDRE = 1) and no
transmission operation is in progress. At this point, a transmission interrupt occurs if transmission bus idle
interrupts have been enabled (SCR:TBIE = 1). The TBI bit and transmission interrupt request are cleared
when transmission data is set to the transmission data register (TDR).
Figure 14.14-4 Timing for Setting Transmission Bus Idle Flag (TBI)
SCK
Transmission data
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
TBI
TDRE
Writing to TDR
CM71-10155-2E
Transmission interrupt generated
by the bus idle state
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.15 Operation of CSIO (Clock Synchronous Serial Interface)
MB91490 Series
Operation of CSIO (Clock Synchronous Serial Interface)
14.15
CSIO uses clock synchronization for its transfer system.
■ Operation of CSIO (Clock Synchronous Serial Interface)
■ Normal Transfer (I)
● Features
Table 14.15-1 Features of Normal Transfer (I)
Item
Description
1
Mark level of serial clock (SCK)
"H"
2
Timing for transmission data output
Falling edge of SCK
3
Sampling of reception data
Rising edge of SCK
4
Data length
5 bits to 9 bits
● Register settings
The setting values of registers required for the normal transfer (I) are shown below.
Table 14.15-2 Register Settings for Normal Transfer (I)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
MS
SPI
RIE
TIE
TBIE
RXE
TXE
MD2
MD1
MD0
-
SCINV
BDS
SCKE
SOE
1/0
0
*
*
*
*
*
0
1
0
0
0
*
1/0
1/0
REC
-
-
-
TBI
SOP
-
-
-
-
L2
L1
L0
0
-
-
-
-
0
-
-
-
-
*
*
*
-
D8
D7
D6
D5
D4
D3
D2
D1
D0
-
*
*
*
*
*
*
*
*
*
SCR/ UPCL
SMR
0
SSR/
ESCR
TDR/
RDR
BGR1/
BGR0
ORE RDRF TDRE
-
-
-
-
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1: Set to "1"
0: Set to "0"
*: User-defined setting
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.15 Operation of CSIO (Clock Synchronous Serial Interface)
MB91490 Series
Note:
The setting values for the above bits (1/0) are different between master and slave operations. They
must be set as shown below.
Master transmission : SCR:MS = 0, SMR:SCKE = 1, SOE = 1
Master reception
: SCR:MS = 0, SMR:SCKE = 1, SOE = 0
Slave transmission : SCR:MS = 1, SMR:SCKE = 0, SOE = 1
Slave reception
: SCR:MS = 1, SMR:SCKE = 0, SOE = 0
● Normal transfer (I) timing chart
Figure 14.15-1 Normal Transfer (I) Timing Chart
●Transmission
operation
1st byte
2nd byte
SCK
SOT
D0 D1 D2
D3
D4 D5 D6 D7 D0
D1 D2 D3 D4
D4 D5 D6 D7
D1
D5
D6
D7
D2 D3 D4 D5
D6
D7
TDRE
TDR RW
TXE
●Reception
operation
SIN
D0 D1
D2 D3
D0
Sampling
RDRF
RDR RD
RXE
● Operational description
1. Master operation (SCR:MS = 0, SMR:SCKE = 1)
• Transmission operation
(1) If transmission data is written to TDR when the output of serial data is enabled (SMR:SOE = 1) and
transmission operation is enabled (SCR:TXE = 1) but reception operation is disabled (SCR:RXE =
0), SSR:TDRE will be set to "0" and transmission data will be output, being synchronized with the
falling edge of the serial clock (SCK) output.
(2) SSR:TDRE is set to "1" when the transmission data for the first bit is output. A transmission
interrupt request is output when transmission interrupts have been enabled (SCR:TIE = 1). At this
point, the transmission data for the second byte can be written.
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.15 Operation of CSIO (Clock Synchronous Serial Interface)
MB91490 Series
• Reception operation
(1) If dummy data is written to TDR when the output of serial data is disabled (SMR:SOE = 0) and
both transmission and reception operations are enabled (SCR:TXE = 1, SCR:RXE = 1), reception
data will be sampled at the rising edge of the serial clock output (SCK).
(2) SSR:RDRF is set to "1" when the last bit is received. A reception interrupt request is output when
reception interrupts have been enabled (SCR:RIE = 1). At this point, reception data (RDR) can be
read.
(3) SSR:RDRF is cleared to "0" once the reception data (RDR) is read.
Note:
To only perform reception operation, write dummy data to TDR to output the serial clock (SCK).
2. Slave operation (SCR:MS = 1, SMR:SCKE = 0)
• Transmission operation
(1) If transmission data is written to TDR when the output of serial data is enabled (SMR:SOE = 1) and
transmission operation is enabled (SCR:TXE = 1), SSR:TDRE will be set to "0" and transmission
data will be output, being synchronized with the falling edge of the serial clock (SCK) input.
(2) SSR:TDRE is set to "1" when the transmission data for the first bit is output. A transmission
interrupt request is output when transmission interrupts have been enabled (SCR:TIE = 1). At this
point, the transmission data for the second byte can be written.
• Reception operation
(1) If the output of serial data is disabled (SMR:SOE = 0) and reception operation is enabled
(SCR:RXE=1), reception data will be sampled at the rising edge of the serial clock input (SCK).
(2) SSR:RDRF is set to "1" when the last bit is received. A reception interrupt request is output when
reception interrupts have been enabled (SCR:RIE = 1). At this point, reception data (RDR) can be
read.
(3) SSR:RDRF is cleared to "0" once the reception data (RDR) is read.
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.15 Operation of CSIO (Clock Synchronous Serial Interface)
MB91490 Series
■ Normal Transfer (II)
● Features
Table 14.15-3 Features of Normal Transfer (II)
Item
Description
1
Mark level of serial clock (SCK)
"L"
2
Output timing for transmission data
Rising edge of SCK
3
Sampling of reception data
Falling edge of SCK
4
Data length
5 bits to 9 bits
● Register settings
The table below shows the register setting values required for the normal transfer (II).
Table 14.15-4 Register Settings for Normal Transfer (II)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
MS
SPI
RIE
TIE
TBIE
RXE
TXE
MD2
MD1
MD0
-
SCINV
BDS
SCKE
SOE
1/0
0
*
*
*
*
*
0
1
0
0
1
*
1/0
1/0
REC
-
-
-
TBI
SOP
-
-
-
-
L2
L1
L0
0
-
-
-
-
0
-
-
-
-
*
*
*
-
D8
D7
D6
D5
D4
D3
D2
D1
D0
-
*
*
*
*
*
*
*
*
v
SCR/ UPCL
SMR
0
SSR/
ESCR
TDR/
RDR
BGR1/
BGR0
ORE RDRF TDRE
-
-
-
-
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1: Set to "1"
0: Set to "0"
*: User-defined setting
Note:
The setting values for the above bits (1/0) are different between master and slave operations. They
must be set as shown below.
Master transmission : SCR:MS = 0, SMR:SCKE = 1, SOE = 1
Master reception
: SCR:MS = 0, SMR:SCKE = 1, SOE = 0
Slave transmission : SCR:MS = 1, SMR:SCKE = 0, SOE = 1
Slave reception
CM71-10155-2E
: SCR:MS = 1, SMR:SCKE = 0, SOE = 0
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.15 Operation of CSIO (Clock Synchronous Serial Interface)
MB91490 Series
■ Normal Transfer (II) Timing Chart
Figure 14.15-2 Normal Transfer (II) Timing Chart
●Transmission
operation
1st byte
Mark level
2nd byte
SCK
SOT
D0 D1 D2
D3 D4 D5 D6
D7 D0 D1
D2 D3 D4
D5 D6
D2 D3 D4
D5
D7
TDRE
TDR RW
TXE
●Reception
operation
SIN
D0 D1
D2 D3 D4
D5 D6 D7
D0 D1
D6
D7
Sampling
RDRF
RDR RD
RXE
● Operational description
1. Master operation (SCR:MS = 0, SMR:SCKE = 1)
• Transmission operation
(1) If transmission data is written to TDR when the output of serial data is enabled (SMR:SOE = 1) and
transmission operation is enabled (SCR:TXE = 1) but reception operation is disabled (SCR:RXE =
0), SSR:TDRE will be set to "0" and transmission data will be output, being synchronized with the
rising edge of the serial clock (SCK) output.
(2) SSR:TDRE is set to "1" when the transmission data for the first bit is output. A transmission
interrupt request is output when transmission interrupts have been enabled (SCR:TIE = 1). At this
point, the transmission data for the second byte can be written.
• Reception operation
(1) If dummy data is written to TDR when the output of serial data is disabled (SMR:SOE = 0) and
both transmission and reception operations are enabled (SCR:TXE = 1, SCR:RXE = 1), reception
data will be sampled at the falling edge of the serial clock output (SCK).
(2) SSR:RDRF is set to "1" when the last bit is received. A reception interrupt request is output when
reception interrupts have been enabled (SCR:RIE = 1). At this point, reception data (RDR) can be
read.
(3) SSR:RDRF is cleared to "0" once the reception data (RDR) is read.
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.15 Operation of CSIO (Clock Synchronous Serial Interface)
MB91490 Series
Note:
To only perform reception operation, write dummy data to TDR to output the serial clock (SCK).
2. Slave operation (SCR:MS = 1, SMR:SCKE = 0)
• Transmission operation
(1) If transmission data is written to TDR when the output of serial data is enabled (SMR:SOE = 1) and
transmission operation is enabled (SCR:TXE = 1), SSR:TDRE will be set to "0" and transmission
data will be output, being synchronized with the rising edge of the serial clock (SCK) input.
(2) SSR:TDRE is set to "1" when the transmission data for the first bit is output. A transmission
interrupt request is output when transmission interrupts have been enabled (SCR:TIE = 1). At this
point, the transmission data for the second byte can be written.
• Reception operation
(1) If the output of serial data is disabled (SMR:SOE = 0) and reception operations is enabled
(SCR:RXE = 1), reception data will be sampled at the falling edge of the serial clock input (SCK).
(2) SSR:RDRF is set to "1" when the last bit is received. A reception interrupt request is output when
reception interrupts have been enabled (SCR:RIE = 1). At this point, reception data (RDR) can be
read.
(3) SSR:RDRF is cleared to "0" once the reception data (RDR) is read.
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.15 Operation of CSIO (Clock Synchronous Serial Interface)
MB91490 Series
■ SPI Transfer (I)
● Features
Table 14.15-5 Features of SPI Transfer (I)
Item
Description
1
Mark level of serial clock (SCK)
"H"
2
Output timing for transmission data
Rising edge of SCK
3
Sampling of reception data
Falling edge of SCK
4
Data length
5 bits to 9 bits
● Register settings
The table below shows the register setting values required for the SPI transfer (I).
Table 14.15-6 SPI Transfer (I) Register Settings
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SCR/
SMR
UPCL
MS
SPI
RIE
TIE
TBIE
RXE
TXE
MD2
MD1
MD0
-
SCINV
BDS
SCKE
SOE
0
1/0
1
*
*
*
*
*
0
1
0
0
0
*
1/0
1/0
SSR/
ESCR
REC
-
-
-
TBI
SOP
-
-
-
-
L2
L1
L0
0
-
-
-
-
0
-
-
-
-
*
*
v
-
D8
D7
D6
D5
D4
D3
D2
D1
D0
-
*
*
*
*
*
*
*
*
*
TDR/
RDR
BGR1/
BGR0
ORE RDRF TDRE
-
-
-
-
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1: Set to "1"
0: Set to "0"
*: User-defined setting
Note:
The setting values for the above bits (1/0) are different between master and slave operations. They
must be set as shown below.
Master transmission : SCR:MS = 0, SMR:SCKE = 1, SOE = 1
Master reception
: SCR:MS = 0, SMR:SCKE = 1, SOE = 0
Slave transmission : SCR:MS = 1, SMR:SCKE = 0, SOE = 1
Slave reception
478
: SCR:MS = 1, SMR:SCKE = 0, SOE = 0
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.15 Operation of CSIO (Clock Synchronous Serial Interface)
MB91490 Series
● SPI transfer (I) timing chart
Figure 14.15-3 SPI Transfer (I) Timing Chart
●Transmission
operation
1st byte
2nd byte
*
SCK
SOT
D0 D1 D2
D3 D4 D5 D6
D7 D0 D1
D2 D3 D4
D0 D1 D2
D3 D4 D5 D6
D7 D0
D2
D5 D6
D7
TDRE
TDR RW
TXE
●Reception
operation
SIN
D1
D3 D4 D5
D6
D7
Sampling
RDRF
RDR RD
RXE
* : During slave transmission (MS=1, SCKE=0, SCE=1), a duration of 4 or more machine cycles is required
after data is written to TDR.
● Operational description
1. Master operation (SCR:MS = 0, SMR:SCKE = 1)
• Transmission operation
(1) If transmission data is written to TDR when the output of serial data is enabled (SMR:SOE = 1) and
transmission operation is enabled (SCR:TXE = 1) but reception operation is disabled (SCR:RXE =
0), SSR:TDRE will be set to "0" and the first bit will be output. After that, the transmission data
will be output, being synchronized with the rising edge of the serial clock (SCK) output.
(2) SSR:TDRE is set to "1", half a cycle before the falling edge of the first serial clock. A transmission
interrupt request is output when transmission interrupts have been enabled (SCR:TIE = 1). At this
point, the transmission data for the second byte can be written.
• Reception operation
(1) If dummy data is written to TDR when the output of serial data is disabled (SMR:SOE = 0) and
both transmission and reception operations are enabled (SCR:TXE = 1, SCR:RXE = 1), reception
data will be sampled at the falling edge of the serial clock output (SCK).
(2) SSR:RDRF is set to "1" when the last bit is received. A reception interrupt request is output when
reception interrupts have been enabled (SCR:RIE = 1).
At this point, reception data (RDR) can be read.
(3) SSR:RDRF is cleared to "0" once the reception data (RDR) is read.
CM71-10155-2E
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.15 Operation of CSIO (Clock Synchronous Serial Interface)
MB91490 Series
Note:
To only perform reception operation, write dummy data to TDR to output the serial clock (SCK).
2. Slave operation (SCR:MS = 1, SMR:SCKE = 0)
• Transmission operation
(1) If transmission data is written to TDR when the output of serial data is enabled (SMR:SOE = 1) and
transmission operation is enabled (SCR:TXE = 1), SSR:TDRE will be set to "0" and the first bit
will be output. After that, the transmission data will be output, being synchronized with the rising
edge of the serial clock (SCK) output.
(2) SSR:TDRE is set to "1", half a cycle before the falling edge of the first serial clock. A transmission
interrupt request is output when transmission interrupts have been enabled (SCR:TIE = 1). At this
point, the transmission data for the second byte can be written.
• Reception operation
(1) If the output of serial data is disabled (SMR:SOE = 0) and reception operation is enabled
(SCR:RXE = 1), reception data will be sampled at the falling edge of the serial clock input (SCK).
(2) SSR:RDRF is set to "1" when the last bit is received. A reception interrupt request is output when
reception interrupts have been enabled (SCR:RIE = 1). At this point, reception data (RDR) can be
read.
(3) SSR:RDRF is cleared to "0" once the reception data (RDR) is read.
480
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.15 Operation of CSIO (Clock Synchronous Serial Interface)
MB91490 Series
■ SPI Transfer (II)
● Features
Table 14.15-7 Features of SPI Transfer (II)
Item
Description
1
Mark level of serial clock (SCK)
"L"
2
Output timing for transmission data
Falling edge of SCK
3
Sampling of reception data
Rising edge of SCK
4
Data length
5 to 9 bits
● Register settings
The table below shows the register setting values required for the SPI transfer (II).
Table 14.15-8 SPI Transfer (II) Register Settings
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SCR/
SMR
UPCL
MS
SPI
RIE
TIE
TBIE
RXE
TXE
MD2
MD1
MD0
-
SCINV
BDS
SCKE
SOE
0
1/0
1
*
*
*
*
*
0
1
0
0
1
*
1/0
1/0
SSR/
ESCR
REC
-
-
-
TBI
SOP
-
-
-
-
L2
L1
L0
0
-
-
-
-
0
-
-
-
-
*
*
*
-
D8
D7
D6
D5
D4
D3
D2
D1
D0
-
*
*
*
*
*
*
*
*
*
TDR/
RDR
BGR1/
BGR0
ORE RDRF TDRE
-
-
-
-
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1: Set to "1"
0: Set to "0"
*: User-defined setting
Note:
The setting values for the above bits (1/0) are different between master and slave operations. They
must be set as shown below.
Master transmission : SCR:MS = 0, SMR:SCKE = 1, SOE = 1
Master reception
: SCR:MS = 0, SMR:SCKE = 1, SOE = 0
Slave transmission : SCR:MS = 1, SMR:SCKE = 0, SOE = 1
Slave reception
CM71-10155-2E
: SCR:MS = 1, SMR:SCKE = 0, SOE = 0
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.15 Operation of CSIO (Clock Synchronous Serial Interface)
MB91490 Series
● SPI transfer (II) timing chart
Figure 14.15-4 SPI Transfer (II) Timing Chart
●Transmission
operation
1st byte
2nd byte
*
SCK
SOT
D0 D1 D2
D3 D4 D5 D6
D7 D0 D1
D2 D3 D4
D5 D6
D7
D2
D5 D6
D7
TDRE
TDR RW
TXE
●Reception
operation
SIN
D0
D1 D2 D3 D4 D5 D6 D7 D0
D1
D3 D4
Sampling
RDRF
RDR RD
RXE
*: During slave transmission (MS=1, SCKE=0, SCE=1), a duration of 4 or more machine cycles is required
after data is written to TDR.
● Operational description
1. Master operation (SCR:MS = 0, SMR:SCKE = 1)
• Transmission operation
(1) If transmission data is written to TDR when the output of serial data is enabled (SMR:SOE = 1) and
transmission operation is enabled (SCR:TXE = 1) but reception operation is disabled (SCR:RXE =
0), SSR:TDRE will be set to "0" and transmission data will be output, being synchronized with the
falling edge of the serial clock (SCK) output.
(2) SSR:TDRE is set to "1" when the transmission data for the first bit is output. A transmission
interrupt request is output when transmission interrupts have been enabled (SCR:TIE = 1). At this
point, the transmission data for the second byte can be written.
• Reception operation
(1) If dummy data is written to TDR when the output of serial data is disabled (SMR:SOE = 0) and
both transmission and reception operations are enabled (SCR:TXE = 1, SCR:RXE = 1), reception
data will be sampled at the rising edge of the serial clock output (SCK).
(2) SSR:RDRF is set to "1" when the last bit is received. A reception interrupt request is output when
reception interrupts have been enabled (SCR:RIE = 1). At this point, reception data (RDR) can be
read.
(3) SSR:RDRF is cleared to "0" once the reception data (RDR) is read.
482
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CM71-10155-2E
CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.15 Operation of CSIO (Clock Synchronous Serial Interface)
MB91490 Series
Note:
To only perform reception operation, write dummy data to TDR to output the serial clock (SCK).
2. Slave operation (SCR:MS = 1, SMR:SCKE = 0)
• Transmission operation
(1) If transmission data is written to TDR when the output of serial data is enabled (SMR:SOE = 1) and
transmission operation is enabled (SCR:TXE = 1), SSR:TDRE will be set to "0" and transmission
data will be output, being synchronized with the falling edge of the serial clock (SCK) output.
(2) SSR:TDRE is set to "1" when the transmission data for the first bit is output. A transmission
interrupt request is output when transmission interrupts have been enabled (SCR:TIE = 1). At this
point, the transmission data for the second byte can be written.
• Reception operation
(1) If the output of serial data is disabled (SMR:SOE = 0) and reception operation is enabled
(SCR:RXE = 1), reception data will be sampled at the rising edge of the serial clock input (SCK).
(2) SSR:RDRF is set to "1" when the last bit is received. A reception interrupt request is output when
reception interrupts have been enabled (SCR:RIE = 1). At this point, reception data (RDR) can be
read.
(3) SSR:RDRF is cleared to "0" once the reception data (RDR) is read.
CM71-10155-2E
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.16 Dedicated Baud Rate Generator
14.16
MB91490 Series
Dedicated Baud Rate Generator
The dedicated baud rate generator only functions in master operation.
■ Baud Rate Selection for CSIO (Clock Synchronous Serial Interface)
The dedicated baud rage generator settings are different between master and slave operations.
● Master operation
The baud rate is selected by dividing the internal clock using the dedicated baud rate generator.
• There are two internal reload counters, and both support the transmission/reception serial clock. The
baud rate can be selected via the 15-bit reload value determined by the baud rate generator registers 1, 0
(BGR1, BGR0).
• The reload counter divides the internal clock, according to the set value.
● Slave operation
In slave operation (SCR:MS = 1), the dedicated baud rate generator does not function.
(The slave operation directly uses the external clock which is input from the clock input pin SCK.)
484
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.16 Dedicated Baud Rate Generator
MB91490 Series
14.16.1
Setting Baud Rate
This section describes how the baud rates are set and the resulting serial clock
frequency is calculated.
■ Calculating the Baud Rate
The two 15-bit reload counters are set by the baud rate generator registers 1, 0 (BGR1, BGR0).
The following formula should be used to calculate a baud rate.
(1) Reload value:
V =  / b -1
V: Reload value
b: Baud rate
: Peripheral clock (CLKP) frequency
(2) Example of calculation
If the peripheral clock (CLKP) is 16MHz, the internal clock is used, and the baud rate is
19200bps, the reload value will be:
Reload value:
V = (16  1000000)/19200 -1 = 832
So baud rate is:
b = (16  1000000)/(832+1) = 19208 bps
(3) Baud rate error
The following formula is used to calculate a baud rate error.
Error (%) = (calculated value - target value) / target value  100
Example: peripheral clock (CLKP) = 20MHz, target baud rate = 153600bps
Reload value = (20  1000000)/153600 -1 = 129
Baud rate (calculated value) = (20  1000000)/(129+1) = 153846 (bps)
Error (%) = (153846 -153600)/153600  100 = 0.16 (%)
Notes:
• The reload counter halts when the reload value is set to "0".
• When the reload value is even-numbered, the "H" and "L" widths of the serial clock are as shown
below, depending on the SCINV bit settings. When the reload value is odd-numbered, the "L"
width is the same as the "H" width.
- When SCINV is set to "0", the "H" width of the serial clock is one peripheral clock (CLKP) cycle
longer.
- When SCINV is set to "1", the "L" width of the serial clock is one peripheral clock (CLKP) cycle
longer.
• Select 3 or a larger value for the reload value.
CM71-10155-2E
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.16 Dedicated Baud Rate Generator
MB91490 Series
■ Reload Values and Baud Rates for Different Peripheral Clock (CLKP) Frequencies
Table 14.16-1 Reload Values and Baud Rates
8 MHz
10 MHz
16 MHz
20 MHz
24 MHz
32MHz
Baud rate
(bps)
Value
ERR
Value
ERR
Value
ERR
Value
ERR
Value
ERR
Value
ERR
8M
6M
5M
4M
2.5M
2M
1M
500000
460800
250000
230400
153600
125000
115200
76800
57600
38400
28800
19200
10417
9600
7200
4800
2400
1200
600
300
3
7
15
31
51
63
68
103
138
207
277
416
767
832
1110
1666
3332
6666
13332
26666
0
0
0
0
-0.16
0
-0.64
-0.16
0.08
-0.16
0.08
0.08
<0.01
0.04
<0.01
0.02
<0.01
<0.01
<0.01
26666
3
4
9
19
39
64
79
86
129
173
259
346
520
959
1041
1388
2082
4166
8334
16666
<0.01
0
0
0
0
0
-0.16
0
0.22
-0.16
0.22
-0.16
<0.01
0.03
<0.01
0.03
<0.01
-0.02
<0.01
0.02
<0.01
-
3
7
15
31
63
103
127
138
207
277
416
554
832
1535
1666
2221
3332
6666
13332
26666
-
0
0
0
0
0
-0.16
0
0.08
-0.16
0.08
0.08
-0.01
-0.03
<0.01
0.02
<0.01
<0.01
<0.01
<0.01
<0.01
-
3
4
9
19
39
79
129
159
173
259
346
520
693
1041
1919
2083
2777
4166
8332
16666
-
0
0
0
0
0
0
-0.16
0
0.22
-0.16
-0.16
0.03
-0.06
0.03
<0.01
0.03
<0.01
<0.01
<0.01
<0.01
-
3
5
11
23
47
51
95
103
155
191
207
311
416
624
832
1249
2303
2499
3332
4999
9999
19999
-
0
0
0
0
0
-0.16
0
-0.16
-0.16
0
-0.16
-0.16
0.08
0
-0.03
0
<0.01
0
<0.01
0
0
0
-
3
7
15
31
63
127
207
255
277
416
555
832
1110
1666
3071
3332
4443
6666
13332
26666
-
0
0
0
0
0
0
-0.16
0
0.08
0.08
0.08
-0.04
-0.01
0.02
<0.01
-0.01
-0.01
<0.01
<-0.01
<0.01
-
• Value: the value set in BGR1/BGR0 registers
• ERR: baud rate error (%)
■ Functions of Reload Counters
There are two reload counters, a transmission reload counter and a reception reload counter, which function
as a dedicated baud rate generator. Structured in a 15-bit register configuration based on a reload value,
these counters generate a transmission/reception clock from the internal clock.
■ Starting a Count
The reload counter starts a count when a reload value is written to the baud rate generator registers 1, 0
(BGR1, BGR0).
■ Restart
The reload counter restarts under the following conditions.
● For both transmission and reception reload counters
Programmable reset (SCR:UPCL bit)
486
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.17 Setup Procedure and Program Flow for CSIO (Clock Synchronous
Serial Interface)
MB91490 Series
14.17
Setup Procedure and Program Flow for CSIO
(Clock Synchronous Serial Interface)
Two-way serial synchronous communication is enabled in CSIO (clock synchronous
serial interface).
■ Connection between CPUs
Two-way communication should be selected for CSIO (clock synchronous serial interface). Two CPUs are
connected to each other, as shown in Figure 14.17-1.
Figure 14.17-1 Example of Two-way Communication Connection for CSIO
(Clock Synchronous Serial Interface)
SOT
SOT
SIN
SIN
SCK
SCK
CPU –1 (Master)
CPU –2 (Slave)
■ Flowchart
Figure 14.17-2 Example Flowchart for Two-way Communication
(Master)
(Slave)
Start
Start
Setting operation format
Setting operation format
(conform to master)
Transmitting data
Communicating by setting
1-byte data to TDR
NO
RDRF=1
YES
NO
RDRF=1
YES
Reading and processing reception data
CM71-10155-2E
Transmitting data
(ANS)
Reading and processing reception data
Transmitting 1-byte data
FUJITSU SEMICONDUCTOR LIMITED
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.18 Notes on CSIO Mode
14.18
MB91490 Series
Notes on CSIO Mode
The notes for when you use the CSIO mode are shown below.
• To request a DMA transfer request, set the block size of DMA to one time.
• When master reception and slave reception are selected, it is required to use two channels for DMA;
one is used for DMA transfer to receive data and the other one is used for DMA transfer to send dummy
data.
488
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.19 I2C Interface
MB91490 Series
14.19
I2C Interface
Of all the functions of the multi-function serial interface, this section describes the I2C
interface that is supported in operation mode 4.
• I2C Interface
• Overview of I2C Interface
• Registers of I2C Interface
- I2C Bus Control Register (IBCR)
- Serial Mode Register (SMR)
- I2C Bus Status Register (IBSR)
- Serial Status Register (SSR)
- Reception Data Register / Transmission Data Register (RDR/TDR)
- 7-bit Slave Address Mask Register (ISMK)
- 7-bit Slave Address Register (ISBA)
- Baud Rate Generator Registers 1, 0 (BGR1, BGR0)
• Interrupts of I2C Interface
- Operation of I2C Interface Communication
- Master Mode
- Slave Mode
- Bus Error
• Dedicated Baud Rate Generator
- Example Flowchart for I2C Interface
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.20 Overview of I2C Interface
14.20
MB91490 Series
Overview of I2C Interface
The I2C interface supports a bus between ICs and operates as a master/slave device on
the I2C bus.
■ Functions of I2C Interface
The I2C interface has the following functions.
• Master/slave transmission & reception functionality
• Arbitration function
• Clock synchronization
• Transmission direction detection
• Generation and detection of repeated start condition
• Bus error detection
• General call addressing
• 7-bit addressing as master/slave
• Interrupts can be generated during transmission and bus errors.
• 10-bit addressing can be supported by a program.
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.21 Registers of I2C Interface
MB91490 Series
Registers of I2C Interface
14.21
This section lists the registers of the I2C interface.
■ List of Registers of I2C Interface
Figure 14.21-1 List of Registers of I2C Interface
Address
I2C
bit15
bit8 bit7
bit0
000062H 000063H
000072H 000073H
000082H 000083H
IBCR
(I2C bus control register)
SMR
(serial mode register)
000060H 000061H
000070H 000071H
000080H 000081H
SSR
(serial status register)
IBSR
(I2C bus status register)
000066H 000067H
000076H 000077H
000086H 000087H
-
RDR/TDR
(transmission/reception
data register)
000064H 000065H
000074H 000075H
000084H 000085H
BGR1
(baud rate generator
register 1)
BGR0
(baud rate generator
register 0)
00006AH 00006BH
00007AH 00007BH
00008AH 00008BH
ISMK
(7-bit slave address mask
register)
ISBA
(7-bit slave address register)
Table 14.21-1 Bit Assignment of I2C Interface
bit15
bit14
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
IBCR/
SMR
MSS
ACT/
ACKE WSEL CNDE INTE
SCC
BER
INT
MD2
MD1
MD0
-
RIE
TIE
SSR/
IBSR
REC
TSET
-
-
TRX
AL
RSC
SPC
BB
RDR/
TDR
-
-
-
-
-
-
-
-
D7
D6
D5
D4
D3
D2
D1
D0
BGR1/
BGR0
-
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
ISMK/
ISBA
EN
SM6
SM5
SM4
SM3
SM2
SM1
SA6
SA5
SA4
SA3
SA2
SA1
SA0
CM71-10155-2E
bit13
bit12
bit11
ORE RDRF TDRE
-
FBT RACK RSA
SM0 SAEN
FUJITSU SEMICONDUCTOR LIMITED
bit1
bit0
ITST1 ITST0
491
CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.21 Registers of I2C Interface
14.21.1
MB91490 Series
I2C Bus Control Register (IBCR)
The I2C bus control register (IBCR) selects master/slave mode, generates a repeated
start condition, enables the acknowledge function, enables interrupts and displays an
interrupt flag.
■ I2C Bus Control Register (IBCR)
Figure 14.21-2 shows the bit structure of the I2C bus control register (IBCR), and Table 14.21-2 describes
the function of each bit.
Figure 14.21-2 Bit Structure of I2C Bus Control Register (IBCR)
IBCR
Address:
ch.0 000062H
ch.1 000072H
ch.2 000082H
bit14
bit13
bit12
bit11
bit10
bit9
bit8
MSS
ACT/SCC
ACKE
WSEL
CNDE
INTE
BER
INT
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
INT
0
1
R
(SMR)
00000000
B
Interrupt flag bit
Write
Read
Clears INT bit
No interrupt request
No effect
Interrupt request
Bus error detection bit
No error
Error detected
INTE
0
1
Interrupt enable bit
Disables interrupt
Enables interrupt
CNDE
0
1
Condition detection interrupt enable bit
Disables repeated start or stop condition interrupt
Enables repeated start or stop condition interrupt
WSEL
0
1
Wait selection bit
Wait after acknowledge (9-bit)
Wait after completion of data transmission/reception (8-bit)
ACKE
0
1
Acknowledge enable bit
Disables acknowledge
Enables acknowledge
0
1
: Readable/Writable
bit0 Initial value
BER
0
1
ACT/SCC
R/W
bit7 . . . . . . . . . . . . . . . . . . . . .
bit15
Operation flag/repeated start condition generation bit
Write
No effect
Read
No operation
Generates repeated start condition
I2C operation in progress
MSS
0
1
Master/slave selection bit
Selects slave mode
Selects master mode
: Read only
: Initial value
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.21 Registers of I2C Interface
MB91490 Series
Table 14.21-2 Functional Description of Each Bit of I2C Bus Control Register (IBCR) (1 / 4)
Bit name
Function
• Master mode will be selected if this bit is set to "1" when the I2C bus is in the idle state
(EN = 1, BB = 0).
• If this bit is set to "1" when the BB bit in the IBSR register is set to "1", the register will
wait to generate a start condition until the BB bit becomes "0". If a slave address match
occurs during that wait and the device operates as a slave, this bit will be set to "0" and the
AL bit in the IBSR register will be set to "1".
• A stop condition will be generated if "0" is written to this bit when the device is operating
as the master (MSS = 1, ACT = 1) and the interrupt flag (INT) is set to "1".
MSS:
bit15 Master/slave
selection bit
The MSS bit is cleared under the following conditions.
• The I2C interface is disabled (EN bit = 0).
• An arbitration lost condition occurs.
• A bus error is detected (BER bit = 1).
• "0" is written to the MSS bit when INT is "1".
The relationship between the MSS and ACT bits is shown below.
MSS bit
ACT bit
Status
0
0
Idle
0
1
Slave operation in progress (slave mode) due to slave
address match or ACK response* to reserved address
1
0
Master operation on standby
1
1
Master operation in progress (master mode)
*:ACK response: indicates that SDA of the I2C bus is at "L" during acknowledge.
Note:
Change the MSS bit from "1" to "0" when the INT bit and MSS bit are set to "1". If "0" is
written to the MSS bit when the ACT bit is set to "1", the INT bit will also be cleared to "0".
Writing "0" to the MSS bit returns "1" during master operation, as long as the ACT bit is set
to "1".
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.21 Registers of I2C Interface
MB91490 Series
Table 14.21-2 Functional Description of Each Bit of I2C Bus Control Register (IBCR) (2 / 4)
Bit name
Function
This bit has different meanings between read and write.
Read
Write
ACT bit
SCC bit
The ACT bit indicates that the device is operating in master or slave mode.
Setting conditions for the ACT bit:
• A start condition is output to the I2C bus (master mode).
• A slave address matches the address transmitted from the master (slave mode).
• A reserved address is detected and then an acknowledge is returned as a response (MSS
= 0: slave mode).
Reset conditions for the ACT bit:
ACT/SCC:
Operation flag /
bit14 repeated start
condition
generation bit
<Master mode>
• A stop condition is detected.
• An arbitration lost condition is detected.
• A bus error is detected.
• The I2C interface is disabled (EN bit = 0).
<Slave mode>
• A (repeated) start condition is detected.
• A stop condition is detected.
• An acknowledge is not returned although a reserved address is detected (RSA bit = 1).
• The I2C interface is disabled (EN bit = 0).
• A bus error occurs (BER bit = 1).
A repeated start is performed when "1" is written to this bit during master mode.
Writing "0" is invalid.
Note:
Write "1" to the SCC bit while an interrupt is occurring in master mode (MSS = 1, ACT =
1, INT = 1). The INT bit will be cleared to "0" if "1" is written to the SCC bit when the
ACT bit is set to "1".
In slave mode (MSS = 0, ACT = 1), it is prohibited to write "1" to this bit.
The MSS bit has higher priority than the SCC bit, when "1" is written to the SCC bit and
"0" is written to the MSS bit.
The SCC bit is read when a read modify write (RMW) instruction is used.
• If this bit is set to "1", "L" will be output when an acknowledge is returned.
ACKE:
bit13 Acknowledge
enable bit
• When ACT is set to "1", this bit must be modified, if necessary, while the INT bit is set to
"1".
This bit is invalid under the following conditions.
• An acknowledge is returned to an address field other than the reserved address
(automatic generation).
• Data transmission (RSA = 0, TRX = 1, FBT = 0)
• This bit is used to determine whether an interrupt should occur (INT = 1) before or after an
acknowledgement to put the I2C bus in a wait state.
bit12
WSEL:
Wait selection bit
• The WSEL bit is invalid under the following conditions.
• An interrupt occurs for the first byte*1 (INT = 1).
• A reserved address is detected (FBT = 1, RSA = 1).
*1: First byte: indicates the data after a (repeated) start condition
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MB91490 Series
CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.21 Registers of I2C Interface
Table 14.21-2 Functional Description of Each Bit of I2C Bus Control Register (IBCR) (3 / 4)
Bit name
Function
CNDE:
This bit is used to enable the occurrence of interrupts when a stop condition or a repeated start
bit11 Condition detection condition is detected in master or slave mode (ACT = 1). An interrupt occurs when the RSC or
interrupt enable bit SPC bit in the IBSR register is set to "1" and this bit is set to "1".
bit10
INTE:
This bit is used to enable an interrupt (INT = 1) for data transmission/reception and a bus error
Interrupt enable bit in master or slave mode.
This bit indicates that an error is detected on the I2C bus.
Setting conditions for the BER bit:
• A start condition or stop condition is detected during the transfer of the first byte*.
• A (repeated) start condition or stop condition is detected at the 2nd bit - 9th
(acknowledge) bit of data in the second or succeeding byte.
bit9
BER:
Bus error detection Reset conditions for the BER bit:
• "0" is written to the INT bit when BER is set to "1".
bit
• The I2C interface is disabled (EN = 0).
*: First byte: indicates the data after (repeated) start condition
Note:
Data cannot be transmitted or received properly if this bit is set to "1" when the interrupt
flag (INT bit) is set to "1". In this case, take an action such as retransmitting the data.
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.21 Registers of I2C Interface
MB91490 Series
Table 14.21-2 Functional Description of Each Bit of I2C Bus Control Register (IBCR) (4 / 4)
Bit name
Function
This bit is set to "1" after the 8th or 9th bit (ACK) of data transmission/reception in master or
slave mode, or upon the occurrence of a bus error. In cases other than the occurrence of a bus
error, SCL is set to "L" when the INT bit is set to "1". When the INT bit is set to "0", SCL is
released from the "L" state.
Setting conditions for the INT bit:
<8th bit>
• A reserved address is detected in the first byte.
• WSEL is "1", and an arbitration lost condition is detected in the second or succeeding
byte.
• WSEL is "1", and the TDRE bit is set to "1" in the second or succeeding byte during
master operation.
• WSEL is set to "1", and the TDRE bit is set to "1" in the second or succeeding byte
during slave transmission.
bit8
INT:
Interrupt flag bit
<9th bit>
• An arbitration lost condition is detected in the first byte.
• A NACK is received at times other than when a stop condition output is set ("0" written
to the MSS bit during master operation).
• The TDRE bit is set to "1" in the transmission direction (TRX = 1) of master or slave
mode without the detection of a reserved address in the first byte.
• The TDRE bit is set to "1" in the reception direction (TRX = 0) of master or slave mode
without the detection of a reserved address in the first byte.
• WSEL is set to "0", and an arbitration lost condition is detected in the second or
succeeding byte.
• WSEL is set to "0", and the TDRE bit is set to "1" in the second or succeeding byte
during master mode operation.
• WSEL is set to "0", and the TDRE bit is set to "1" in the second or succeeding byte
during slave transmission.
• WSEL is set to "0" when slave reception is selected. In slave reception, however, an
interrupt does not occur in the 9th bit of the first byte in which a reserved address is
detected.
<Other condition>
A bus error is detected.
Reset conditions for the INT bit:
• "0" is written to the INT bit.
• "0" is written to the MSS bit when the INT bit is "1" and the ACT bit is "1".
• "1" is written to the SCC bit when the INT bit is "1" and the ACT bit is "1".
Writing "1" to the INT bit is invalid.
Note:
Setting the EN bit to "0" may set the RDRF and INT bits to "1", depending on the reception
timing. In this case, read the reception data to clear the INT bit.
"1" is read when a read modify write (RMW) instruction is used.
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.21 Registers of I2C Interface
MB91490 Series
14.21.2
Serial Mode Register (SMR)
The serial mode register (SMR) sets the operation mode, and enables or disables
transmission/reception interrupts.
■ Serial Mode Register (SMR)
Figure 14.21-3 shows the bit structure of the serial mode register (SMR), and Table 14.21-3 describes the
function of each bit.
Figure 14.21-3 Bit Structure of Serial Mode Register (SMR)
SMR
bit15
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bit8
(IBCR)
Address:
ch.0 000063H
ch.1 000073H
ch.2 000083H
bit7
bit6
bit5
bit4
MD2 MD1 MD0
-
bit3
bit2
bit1
RIE
TIE
-
bit0
-
Initial value
000- 00-- B
R/W R/W R/W R/W R/W R/W R/W R/W
Undefined bits
Always set these bits to “00B”.
TIE
0
1
Transmission interrupt enable bit
Disables transmission interrupt
Enables transmission interrupt
RIE
0
1
Reception interrupt enable bit
Disables reception interrupt
Enables reception interrupt
Undefined bit
Read: undefined value. Write: no effect.
R/W
: Readable/Writable
-
: Undefined bit
: Initial value
MD2 MD1 MD0
Operation mode setting bits
0
0
0
Operation mode 0 (asynchronous normal mode)
0
0
1
Operation mode 1 (asynchronous multi-processor mode)
0
1
0
Operation mode 2 (clock synchronization mode)
1
0
0
Operation mode 4 (I2C mode)
Note: This section describes the registers and operations of operation mode 4.
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.21 Registers of I2C Interface
MB91490 Series
Table 14.21-3 Functional Description of Each Bit of Serial Mode Register (SMR)
Bit name
Function
bit7
to
bit5
MD2 to MD0:
Operation mode
setting bits
These bits are used to select the operation mode.
"000B": Selects operation mode 0 (asynchronous normal mode)
"001B": Selects operation mode 1 (asynchronous multi-processor mode)
"010B": Selects operation mode 2 (clock synchronization mode)
"100B": Selects operation mode 4 (I2C mode)
This section describes the registers and operations of operation mode 4 (I2C mode).
Note:
Settings other than above are prohibited.
To switch the operation mode, disable I2C first (ISMK:EN = 0).
Set each register after selecting the operation mode.
bit4
Undefined bit
Read: undefined value
Write: no effect
• This bit is used to enable or disable the output of reception interrupt requests to
the CPU.
bit3
RIE:
Reception interrupt
enable bit
• A reception interrupt request is output when the RIE bit and the reception data
flag bit (RDRF) are set to "1", or the error flag bit (ORE) is set to "1".
Note:
Set this bit to "0" when receiving data using the INT bit in the I2C bus control
register (IBCR).
• This bit is used to enable or disable the output of transmission interrupt requests
to the CPU.
bit2
bit1,
bit0
TIE:
Transmission
interrupt enable bit
Undefined bits
• A transmission interrupt request is output when the TIE and TDRE bits are set to
"1".
Note:
Set this bit to "0" when transmitting data using the INT bit in the I2C bus control
register (IBCR).
Always set these bits to "00B".
Note:
The operation mode must be set first. Otherwise, the other registers will be initialized when the
operation mode is changed. Note, however, that when IBCR and SMR are written simultaneously
with 16-bit write access, IBCR reflects the written content.
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.21 Registers of I2C Interface
MB91490 Series
14.21.3
I2C Bus Status Register (IBSR)
The I2C bus status register (IBSR) indicates the detection of a repeated start condition,
acknowledge, data direction, arbitration lost condition, stop condition, I2C bus status
and bus error.
■ I2C Bus Status Register (IBSR)
Figure 14.21-4 shows the bit structure of the I2C bus status register (IBSR) and Table 14.21-4 describes the
function of each bit.
Figure 14.21-4 Bit Structure of I2C Bus Status Register (IBSR)
IBSR
bit15
.......................................
Address:
ch.0 000061H
ch.1 000071H
ch.2 000081H
(SSR)
bit8
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
FBT R ACK RSA
bit7
TRX
AL
RSC
SPC
BB
00000000
R
R
R
R
bit6
R
Bus state bit
Bus in idle state
Bus in transmission/reception state
Stop condition confirmation bit
Stop condition not detected
Master
Stop condition detected or arbitration lost condition
generated when stop condition is output
Slave
R
: Read only
: Initial value
CM71-10155-2E
B
R
0
1
1
: Readable/Writable
R/W
BB
SPC
0
R/W
R/W
Stop condition detected
RSC
0
1
Repeated start condition confirmation bit
Repeated start condition not detected
Repeated start condition detected
AL
0
1
Arbitration lost bit
Arbitration lost condition not generated
Arbitration lost condition generated
TRX
0
1
Data direction bit
Reception direction
Transmission direction
RSA
0
1
Reserved address detection bit
Reserved address not detected
Reserved address detected
R ACK
0
1
Acknowledge flag bit
"L" reception
"H" reception
FBT
0
1
First byte bit
Other than first byte
First byte being transmitted/received
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14.21 Registers of I2C Interface
MB91490 Series
Table 14.21-4 Functional Description of Each Bit of I2C Bus Status Register (1 / 3)
Bit name
bit7
bit6
bit5
500
Function
FBT:
First byte bit
This bit indicates the first byte.
Setting condition for the FBT bit:
A (repeated) start condition is detected.
Clearing conditions for the FBT bit:
• The second byte is transmitted or received.
• A stop condition is detected.
• The I2C interface is disabled (EN bit = 0).
• A bus error is detected (BER bit = 1).
RACK:
Acknowledge flag bit
This bit is used to indicate the acknowledge received for the first byte during master
or slave mode.
Update conditions for the RACK bit
• Acknowledge for the first byte
• Acknowledge for data in master or slave mode
Clearing conditions for the RACK bit (RACK bit = 0)
• A (repeated) start condition is detected.
• The I2C interface is disabled (EN bit = 0).
• A bus error is detected (BER bit = 1).
RSA:
Reserved address
detection bit
This bit indicates the detection of a reserved address.
Setting condition for the RSA bit (RSA = 1)
The first byte is set to "0000XXXX" or "1111XXXX". "X" can be "0" or "1".
Reset conditions for the RSA bit (RSA = 0)
• A (repeated) start condition is detected.
• A stop condition is detected.
• The I2C interface is disabled (EN bit = 0).
• A bus error is detected (BER bit = 1).
When the RSA bit is set to "1" in the first byte, the interrupt flag (INT) is set to "1" at
the falling edge of SCL in the 8th bit of the first byte to set the SCL to "L". In this
case, ACKE should be set to "1" and the interrupt flag (INT) should be cleared to "0"
in order to read reception data and allow the device to operate as a slave. If the TRX
bit is set to "0", the device will receive data as a slave. To disable data reception in
the middle of the operation, set the ACKE bit to "0". No more data will be received
afterward.
Note:
When ACKE is set to "0" during a data transfer, it is prohibited to set ACKE to
"1" until a stop condition or repeated start condition is detected.
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.21 Registers of I2C Interface
Table 14.21-4 Functional Description of Each Bit of I2C Bus Status Register (2 / 3)
Bit name
bit4
bit3
bit2
Function
TRX:
Data direction bit
This bit indicates the data direction.
Setting conditions for the TRX bit:
(1) A (repeated) start condition is transmitted in master mode.
(2) The 8th bit of the first byte is "1" in slave mode (transmission direction as a
slave).
Reset conditions for the TRX bit:
(1) An arbitration lost condition is generated (AL = 1).
(2) The 8th bit of the first byte is "0" in slave mode (reception direction as a
slave).
(3) The 8th bit of the first byte is "1" in master mode (reception direction as the
master).
(4) A stop condition is detected.
(5) A (repeated) start condition is detected in modes other than master mode.
(6) The I2C interface is disabled (EN bit = 0).
(7) A bus error is detected (BER bit = 1).
AL:
Arbitration lost bit
This bit indicates an arbitration lost condition.
Setting conditions for the AL bit:
(1) The output data is different from the received data in master mode.
(2) The device is operating as a slave although the MSS bit has been set to "1".
(3) A repeated start condition is detected in the first bit of the data contained in
the second or succeeding byte in master mode.
(4) A stop condition is detected in the first bit of the data contained in the second
or succeeding byte in master mode.
(5) A repeated start condition cannot be generated in master mode, despite
attempts to do so.
(6) A stop condition cannot be generated in master mode, despite attempts to do
so.
Reset conditions for the AL bit:
(1) "1" is written to the MSS bit.
(2) "0" is written to the INT bit.
(3) "0" is written to the SPC bit when the AL and SPC bits are set to "1".
(4) The I2C interface is disabled (EN bit = 0).
(5) A bus error is detected (BER bit = 1).
RSC:
Repeated start
condition
confirmation bit
This bit indicates that a repeated start condition has been detected in master or slave
mode.
Setting condition for the RSC bit:
A repeated start condition is detected after acknowledgement during slave or
master mode operation.
Reset conditions for the RSC bit:
(1) "0" is written to the RSC bit.
(2) "1" is written to the MSS bit.
(3) The I2C interface is disabled (EN bit = 0).
Writing "1" to this bit is invalid.
Note:
Slave mode will end unless ACK is returned when the device is operating
reception in slave mode by the detection of a reserved address. Consequently, this
bit will not be set to "1" even if a repeated start condition is detected.
"1" is read when a read modify write (RMW) instruction is used.
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.21 Registers of I2C Interface
MB91490 Series
Table 14.21-4 Functional Description of Each Bit of I2C Bus Status Register (3 / 3)
Bit name
bit1
bit0
502
Function
SPC:
Stop condition
confirmation bit
This bit indicates that a stop condition has been detected in master or slave mode.
Setting conditions for the SPC bit:
(1) A stop condition is detected during slave or master mode operation.
(2) An arbitration lost condition is generated when a stop condition is generated
in master mode.
Reset conditions for the SPC bit:
(1) "0" is written to this bit.
(2) "1" is written to the MSS bit.
(3) The I2C interface is disabled (EN bit = 0).
Writing "1" to this bit is invalid.
Note:
Slave mode will end unless ACK is returned when the device is operating
reception in slave mode by the detection of a reserved address. Consequently, this
bit will not be set to "1" even if a stop condition is detected.
"1" is read when a read modify write (RMW) instruction is used.
BB:
Bus state bit
This bit indicates the bus state.
Setting condition for the BB bit:
"L" is detected at SDA or SCL of the I2C bus.
Reset conditions for the BB bit:
(1) A stop condition is detected.
(2) The I2C interface is disabled (EN bit = 0).
(3) A bus error is detected (BER bit = 1).
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.21 Registers of I2C Interface
MB91490 Series
14.21.4
Serial Status Register (SSR)
The serial status register (SSR) checks the transmission/reception status.
■ Serial Status Register (SSR)
Figure 14.21-5 shows the bit structure of the serial status register (SSR) and Table 14.21-5 describes the
function of each bit.
Figure 14.21-5 Bit Structure of Serial Status Register (SSR)
SSR
bi t15 bit14
Address:
ch.0 000060H
ch.1 000070H
ch.2 000080H
REC
R/W
bit13
bit12
TSET
-
-
R/W
-
-
bit11
bit10
bit9
ORE RDRF TDRE
R
R
R
bit8
bit7
...................................
-
bit0
(IBSR)
Initial value
00--001- B
-
Undefined bit
Read : undefined value. Write: no effect .
TDRE
0
1
Transmission data empty flag bit
The t ransmission data register (TDR) contains data .
The t ransmission data register is empty.
RDRF
0
1
Reception data full flag bit
The reception data register (RDR) is empty.
The reception data register (RDR) contains data .
ORE
0
1
Overrun error flag bit
No overrun error
Overrun error
Undefined bits
Read : undefined value. Write: no effect .
TSET
0
1
REC
R/W
R
-
: Readable/Writable
: Read only
: Undefined
0
1
Transmission buffer empty flag setting bit
Write
Read
No effect
"0" is always read .
Sets TDRE bit
Reception error flag clear bit
Write
Read
No effect
Clears the reception
"0" is always read .
error flag (ORE)
: Initial value
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.21 Registers of I2C Interface
MB91490 Series
Table 14.21-5 Functional Description of Each Bit of Serial Status Register (SSR)
Bit name
Function
This bit is used to clear the ORE bit in the serial status register (SSR).
bit15
REC:
Reception error flag
clear bit
• Writing "1" clears the ORE bit.
• Writing "0" has no effect.
Reading this bit always returns "0".
This bit is used to set the TDRE bit in the serial status register (SSR).
bit14
TSET:
Transmission buffer
empty flag setting bit
• Writing "1" sets the TDRE bit.
• Writing "0" has no effect.
Reading this bit always returns "0".
bit13,
bit12
bit11
Undefined bits
ORE:
Overrun error flag bit
Read: undefined value
Write: no effect
• This bit is set to "1" when an overrun occurs during reception. The bit is cleared
by writing "1" to the REC bit in the serial status register (SSR).
• A reception interrupt request is output when the ORE and RIE bits are set to "1".
• When this flag is set, the data in the reception data register (RDR) is invalid.
• This flag indicates the status of the reception data register (RDR).
• A reception interrupt request is output when the RIE bits and the reception data
flag bit (RDRF) are set to "1".
bit10
RDRF:
Reception data full
flag bit
• The bit is set to "1" when reception data is loaded to RDR. The bit is cleared to
"0" when the reception data register (RDR) is read.
• This bit is set at the falling edge of SCL in the 8th bit of data.
• It is also set by a NACK response.
Note:
NACK response: indicates that SDA of the I2C bus is at "H" during acknowledge.
• This flag indicates the status of the transmission data register (TDR).
• A transmission interrupt request is output when the TIE and TDRE bits are set to
"1"
bit9
TDRE:
Transmission data
empty flag bit
• When transmission data is written to TDR, the bit becomes "0", indicating that
TDR contains valid data. When the data is loaded to the transmission shift
register and transmission starts, the bit becomes "1", indicating that TDR no
longer contains any valid data.
• This bit is set when "1" is written to the TSET bit in the serial status register
(SSR). This bit is used to set the TDRE bit to "1" when an arbitration lost
condition or bus error is detected.
bit8
504
Undefined bit
Read: undefined value
Write: no effect
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.21 Registers of I2C Interface
MB91490 Series
14.21.5
Reception Data Register / Transmission Data Register
(RDR/TDR)
The reception and transmission data registers are located at the same address. It
serves as the reception data register in read access, while it functions as the
transmission data register in write access.
■ Reception Data Register (RDR)
Figure 14.21-6 illustrates the bit structure of the serial reception register (RDR).
Figure 14.21-6 Bit Structure of Reception Data Register (RDR)
RDR
bit15 ............. bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
ch.0 000067H
ch.1 000077H
ch.2 000087H
D7
D6
D5
D4
D3
D2
D1
D0
R
R
R
R
R
R
R
R
Initial value
00000000B
R: Read only
The reception data register (RDR) is a data buffer register for serial data reception.
• A serial data signal sent to a serial data line (SDA pin) is converted through the shift register and then
stored in the reception data register (RDR).
• When the first byte* is received, the least significant bit (RDR: D0) becomes the data direction bit.
• The reception data full flag bit (SSR:RDRF) is set to "1" once reception data is stored in the reception
data register (RDR).
• The reception data full flag bit (SSR: RDRF) is cleared to "0" automatically, when the reception data
register (RDR) is read.
*: Indicates the data after a (repeated) start condition.
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14.21 Registers of I2C Interface
MB91490 Series
■ Transmission Data Register (TDR)
Figure 14.21-7 illustrates the bit structure of the transmission data register.
Figure 14.21-7 Bit Structure of Transmission Data Register (TDR)
TDR
bit15 .............. bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
ch.0 000067H
ch.1 000077H
ch.2 000087H
D7
D6
D5
D4
D3
D2
D1
D0
W
W
W
W
W
W
W
W
Initial value
11111111B
W: Write only
The transmission data register (TDR) is a data buffer register for serial data transmission.
• Data is output to the serial data line (SDA pin), based on the transmission data register (TDR) value
(MSB first).
• The least significant bit (TDR: D0) becomes the data direction bit when transmitting the first byte.
• The transmission data empty flag (SSR: TDRE) is cleared to "0" when transmission data is written to
the transmission data register (TDR).
• The transmission data empty flag (SSR: TDRE) is set to "1" when transmission data is transferred to the
transmission shift register.
• Write the next transmission data under the following conditions.
- The interrupt flag (INT bit) is set to "1".
- No bus error is occurring (BER bit = 0).
- Acknowledge is returned as ACK response ("0" is received as acknowledgement).
• Transmission data cannot be written to the transmission data register (TDR) if the data empty flag (SSR:
TDRE) is set to "0".
Note:
The transmission data register is used exclusively for writing, while the reception data register is
used exclusively for reading. The two registers have different write and read values as they are
located at the same address. Therefore, instructions such as INC/DEC instructions, which are used
for read modify write (RMW) instruction, cannot be used.
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.21 Registers of I2C Interface
MB91490 Series
14.21.6
7-bit Slave Address Mask Register (ISMK)
The 7-bit slave address mask register (ISMK) determines whether each bit of a slave
address should be compared.
■ 7-bit Slave Address Mask Register (ISMK)
Figure 14.21-8 shows the bit structure of the 7-bit slave address mask register (ISMK) and Table 14.21-6
describes the function of each bit.
Figure 14.21-8 Bit Structure of 7-bit Slave Address Mask Register (ISMK)
ISMK
bit15
Address:
ch.0 00006AH
ch.1 00007AH
ch.2 00008AH
R/W
bit14
bit13
bit12
bit11
bit10
bit9
bit8
EN
SM6
SM5
SM4
SM3
SM2
SM1
SM0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
: Readable/Writable
bit7
.....................................
bit0
(ISBA)
SM6 to SM0
0
1
Slave address mask bits
No bit comparison
Bit comparison
EN
0
1
I2C interface enable bit
Disables I2C interface
Enables I2C interface
Initial value
01111111
B
: Initial value
Table 14.21-6 Functional Description of Each Bit of 7-bit Slave Address Mask Register (ISMK)
Bit name
bit15
bit14 to
bit8
Function
EN:
I2C interface enable
bit
This bit is used to enable or disable the operation of the I2C interface.
Setting the bit to "0" disables the operation of the I2C interface.
Setting the bit to "1" enables the operation of the I2C interface.
Note:
This bit is not cleared to "0" even when the BER bit in the IBSR register is set to
"1".
Set the baud rate generator when this bit is set to "0".
Set a 7-bit slave address and the 7-bit slave mask register when this bit is set to
"0".
Setting the EN bit to "0" during transmission may generate a pulse at SDA/SCL
of the I2C bus.
SM6 to SM0:
Slave address mask
bits
These bits are used to determine whether to compare the 7-bit slave address with the
received address.
Bit set to "1": compared
Bit set to "0": handled as matched
Note:
Set this register when the EN bit is "0".
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14.21 Registers of I2C Interface
14.21.7
MB91490 Series
7-bit Slave Address Register (ISBA)
The 7-bit slave address register (ISBA) sets a slave address.
■ 7-bit Slave Address Register (ISBA)
Figure 14.21-9 shows the bit structure of the 7-bit slave address register (ISBA) and Table 14.21-7
describes the function of each bit.
Figure 14.21-9 Bit Structure of 7-bit Slave Address Register (ISBA)
ISBA
bit15
.....................................
(ISMK)
Address:
ch.0 00006BH
ch.1 00007BH
ch.2 00008BH
R/W
: Readable/Writable
: Initial value
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
SAEN
SA6
SA5
SA4
SA3
SA2
SA1
SA0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SA6 to SA0
Slave address setting bits
7-bit slave address
SAEN
0
1
Slave address enable bit
Disables slave address
Enables slave address
Table 14.21-7 Functional Description of Each Bit of 7-bit Slave Address Register (ISBA)
Bit name
bit7
bit6 to
bit0
508
Function
SAEN:
Slave address enable
bit
This bit is used to enable the detection of a slave address.
Setting the bit to "0": Slave address not detected
Setting the bit to "1": ISBA/ISMK setting compared with the first byte of received
data
SA6 to SA0:
7-bit slave address
If slave address detection has been enabled (SAEN = 1), the 7-bit data which is
received after the detection of a (repeated) start condition will be compared with the
value contained in the 7-bit slave address register (ISBA). If all the bits match, the
device will operate in slave mode and output an ACK. At this point, the received
slave address will be set to this register (An ACK will not be output if SAEN is set to
"0").
The address bits which are set to "0" in the ISMK register are not subject to this
comparison.
Note:
It is prohibited to set a reserved address.
Set this register when the EN bit in the ISMK register is "0".
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.21 Registers of I2C Interface
MB91490 Series
14.21.8
Baud Rate Generator Registers 1, 0 (BGR1, BGR0)
The baud rate generator registers 1, 0 (BGR1, BGR0) are used to set a division ratio for
the serial clock.
■ Bit Structure of the Baud Rate Generator Registers 1, 0 (BGR1, BGR0)
Figure 14.21-10 shows the bit structure of the baud rate generator registers 1, 0 (BGR1, BGR0).
Figure 14.21-10 Bit Structure of Baud Rate Generator Registers 1, 0 (BGR1, BGR0)
bit15
BGR
Address:
bit14
bit13
-
bit12
bi t11 bit10
bit9
bit8
bit7
bit6
bit5
(BGR1)
bit4
bit3
bit2
bit1
bit0
(BGR0)
BGR0
(-)
ch.0 000065H
ch.1 000075H
ch.2 000085H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
-0000000 B
00000000 B
BGR1
ch.0 000064H
ch.1 000074H
ch.2 000084H
R/W : Readable/Writable
-
BGR0
Write
Read
Baud rate generator register 0
Writes to reload counter bit0 to bit7
Reads BGR0 setting value
BGR1
Write
Read
Baud rate generator register 1
Writes to reload counter bit8 to bit14
Reads BGR1 setting value
Undefined bit
Read : undefined value. Write: no ef fect.
: Undefined
The baud rate generator registers are used to set a division ratio for the serial clock.
BGR0 and BGR1 correspond to the upper bits and lower bits respectively and they can write a reload value
to be counted as well as read BGR1/BGR0 setting values.
The reload counter starts counting when a reload value is written to the baud rate generator registers 1, 0
(BGR1, BGR0).
Notes:
• Use 16-bit access to write to the baud rate generator registers 1, 0 (BGR1, BGR0).
• Set the baud rate generator registers when the EN bit in the ISMK register is "0".
• Set a baud rate regardless of master or slave mode.
• Use the peripheral clock (CLKP) at 8 MHz or higher in operation mode 4 (I2C mode). It is
prohibited to set the baud rate generator to higher than 400kbps.
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14.22 Interrupts of I2C Interface
14.22
MB91490 Series
Interrupts of I2C Interface
The following sources can be used to generate interrupt requests for the I2C interface.
• After the transmission/reception of the first byte or data
• Stop condition
• Repeated start condition
■ Interrupts of I2C Interface
Table 14.22-1 shows the interrupt control bits and interrupt sources of the I2C interface.
Table 14.22-1 Interrupt Control Bits and Interrupt Sources of I2C Interface
Interrupt
type
Interrupt
Flag
request
register
flag bit
Interrupt source
Interrupt
source
enable bit
Clearing of interrupt request flag
After transmission/reception of
1st byte*1
INT
IBCR
After transmission/reception of
data*1
IBCR:INTE
Writing "0" to interrupt flag bit
(IBCR:INT)
Detection of bus error
Detection of arbitration lost
condition
Reception
RDRF
SSR
Detection of reserved address
After reception of data
Reading reception data (RDR)
SMR:RIE
ORE
SSR
Overrun error
Writing "1" to reception error flag bit
(SSR:REC)
SPC
IBSR
Stop condition
Writing "0" to stop condition detection
bit
IBCR:CNDE
RSC
IBSR
Repeated start condition
Writing "0" to repeated start detection
flag bit (IBSR:RSC)
Transmission register being empty
Transmission
TDRE
SSR
Writing "1" to transmission buffer
empty flag setting bit
(SSR:TSET)
SMR:TIE
Writing to transmission data (TDR)
(Transmission again)*2
*1: Normal data can be transmitted or received. An interrupt does not occur when TDRE is set to "0". This function is
designed to support DMA transfer.
The TDRE bit must be set to "1" before the INT flag is set, in order to generate the INT flag in data transmission/
reception.
*2: Wait until the TDRE bit becomes "0" before setting the TIE bit to "1".
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14.22 Interrupts of I2C Interface
MB91490 Series
14.22.1
Operation of I2C Interface Communication
The I2C interface communication uses 2 two-way bus lines, a serial data line (SDA) and
a serial clock line (SCL).
■ Start Condition for I2C Bus
The start condition for the I2C bus is shown below.
Figure 14.22-1 Start Condition
SDA
SCL
Start condition
■ Stop Condition for I2C Bus
The stop condition for the I2C bus is shown below.
Figure 14.22-2 Stop Condition
SDA
SCL
Stop condition
■ Repeated Start Condition for I2C Bus
The repeated start condition for the I2C bus is shown below.
Figure 14.22-3 Repeated Start Condition
SDA
SCL
ACK *
*: ACK: Acknowledge
CM71-10155-2E
Repeated start condition
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14.22 Interrupts of I2C Interface
14.22.2
MB91490 Series
Master Mode
Master mode generates a start condition for the I2C bus and outputs a clock to the I2C
bus. Master mode will be selected and the ACT bit in the IBCR register will be set to "1",
if the MSS bit in the IBCR register is set to "1" when the I2C bus is in an idle state
(SCL = "H", SDA = "H").
■ Generating a Start Condition
A start condition is output under the following conditions.
"1" is written to the MSS bit when SDA = "H", SCL = "H", EN = 1, and BB = 0.
Outputting a start condition to the I2C bus sets the ACT bit to "1". After that, the BB bit is set to "1",
indicating that the I2C bus is in the middle of communication, once the start condition is received (see
Figure 14.22-4).
Figure 14.22-4 Correlation between Output of Start Condition and Each Bit
Start condition
A6 *1
SDA
SCL
1
A5 *2
2
BB bit
MSS bit
Writing "1"
ACT bit
TRX bit
FBT bit
TDRE bit
*1 : A6: Address bit 6
*2 : A5: Address bit 5
Note:
Use the peripheral clock (CLKP) at 8 MHz or higher in operation mode 4 (I2C mode). It is prohibited
to set the baud rate generator to higher than 400kbps.
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14.22 Interrupts of I2C Interface
MB91490 Series
■ Outputting a Slave Address
When a start condition is output, the data set in the TDR register is output from bit7 as an address. Set an
address to the TDR register before writing "1" to MSS or SCC.
Figure 14.22-5 and Figure 14.22-6 show the address and data direction output timings.
Figure 14.22-5 Address and Data Direction
1
2
3
4
5
6
7
8
SCL
SDA
A6(D7) A5(D6) A4(D5) A3(D4) A2(D3) A1(D2) A0(D1) R/W(D0)
ACK
BB bit
MSS bit*
TDRE
INT bit
<Detecting reserved address>
RSA bit
RDRF bit
INT bit
SCL remains set to "L" while INT is "1".
A6 to A0 : Address
D7 to D0 : TDR register bit
R/W
: Data direction ("L", write direction)
ACK
: Acknowledge ("L", acknowledge, output from slave)
*: Set the address to the TDR register before writing "1" to the MSS bit.
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14.22 Interrupts of I2C Interface
MB91490 Series
■ Receiving Acknowledge after Transmitting 1st Byte
The I2C interface receives an acknowledge from the slave when the data direction bit (R/W) is output. The
following operation is performed.
Table 14.22-2 Operations after Reception of Acknowledge (RSA Bit = 0)
Data
direction bit
(R/W)
0
1
Operation immediately after reception of acknowledge
Acknowledge = ACK
Acknowledge = NACK
When the TDRE bit is set to "1", the INT bit is set
to "1", causing a wait. When the TDRE bit is set to The INT bit is set to "1", causing a wait
"0", the INT bit remains "0", causing no wait
• The interrupt flag (INT) will be set to "1", causing a wait while maintaining SCL at "L", if the TDRE bit
is set to "1" after the reception of an acknowledge when the RSA bit is set to "0". The wait is cancelled
when "0" is written to the interrupt flag to set it to "0". If the TDRE bit has been set to "0", a clock will
be generated to SCL without setting the interrupt flag to "1" when an ACK is received.
• When the RSA bit is set to "1", the interrupt flag (INT) is set to "1", causing a wait while maintaining
SCL at "L", after a reserved address is received (before acknowledge). The interrupt flag will be set to
"0" to cancel the wait, if the ACKE bit and transmission data are set and "0" is written to the interrupt
flag after the RDR register has been read.
• The received acknowledge is set to the RACK bit. If NACK is identified when the RACK bit is checked
during the wait, a stop condition or repeated start condition will be generated by writing "0" to the MSS
bit or writing "1" to the SCC bit. In this case, the INT bit will be cleared to "0" automatically.
Figure 14.22-6 Acknowledge (RSA = 0, ACK Response)
Data
"L" by INT bit
SCL
SDA
R/W
ACK
Writing "0"
INT bit
RACK bit
FBT bit
Writing to TDR register
TDRE bit
Address wait timings:
• RSA = 0: after receiving acknowledge
• RSA = 1: before receiving acknowledge
The above timings are not dependent on the WSEL setting.
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14.22 Interrupts of I2C Interface
MB91490 Series
Figure 14.22-7 Acknowledge (RSA = 0, NACK Response)
"L" by INT bit
SCL
SDA
R/W
NACK
Writing "0"
Stop condition
INT bit
MSS bit
RACK bit
FBT bit
Figure 14.22-8 Acknowledge (RSA = 1, ACK Response)
"L" by INT bit
Data
SCL
SDA
R/W
ACK
Writing "0"
INT bit
RACK bit
FBT bit
RSA bit
Reading RDR register
RDRF bit
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14.22 Interrupts of I2C Interface
MB91490 Series
Figure 14.22-9 Acknowledge (RSA = 1, NACK Response)
"L" by INT bit
SCL
SDA
R/W
NACK
Writing "0"
Stop condition
INT bit
MSS bit
RACK bit
FBT bit
RSA bit
Reading RDR register
RDRF bit
■ Master Data Transmission
Data is transmitted from the master when the data direction bit (R/W) is set to "0". The slave returns an
ACK or NACK response for each byte transmitted.
The location in which a wait occurs is as follows, depending on the WSEL bit setting.
Table 14.22-3 WSEL Bit During Master Data Transmission
WSEL bit
Operation
0
A wait is generated in the second or succeeding byte, when the interrupt flag (INT) is set to "1" and SCL
is set to "L" after an acknowledge by setting the TDRE bit to "1" or detecting an arbitration lost
condition.
1
A wait is generated in the second or succeeding byte, when the interrupt flag (INT) is set to "1" and SCL
is set to "L" after the master transmits 1-byte data by setting the TDRE bit to "1" or detecting an
arbitration lost condition.
However, if a NACK is received at times other than when a stop condition is set (MSS = 0, MAS = 1), the
interrupt flag (INT) is set after an acknowledge, regardless of the WSEL setting.
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14.22 Interrupts of I2C Interface
MB91490 Series
An example procedure for transmitting data to the slave is shown below.
● Transmitting data to any address other than reserved address
(1)
Set the slave address (including the data direction bit) to the TDR register and write "1" to the
MSS bit.
(2)
An ACK will be received after the slave address is transmitted, and then the interrupt flag (INT)
will be set to "1".
(3)
Write the data to be transmitted to the TDR register.
(4)
Update the WSEL bit and write "0" to the interrupt flag (INT) to cancel a wait for the I2C bus.
(5)
Put the I2C bus in a wait by setting the interrupt flag to "1", after receiving an acknowledge upon
the transmission of one byte when WSEL is set to "0", or immediately after one byte has been
transmitted when WSEL is set to "1". Repeat (2) to (4) until a specified number of data elements
are transmitted. However, another interrupt occurs upon the reception of an acknowledge, causing
the bus to wait, when a NACK is received after the wait is cancelled with WSEL set to "1".
(6)
Set the MSS bit to "0" or the SCC bit to "1" to generate a stop condition or a repeated start
condition.
● Transmitting data to reserved address
(1)
Set the reserved address to the TDR register as the slave address and write "1" to the MSS bit.
(2)
The interrupt flag (INT) will be set to "1" once the slave address has been transmitted.
(3)
Read from the RDR register to check the reserved address.*
(4)
Write the data to be transmitted to the TDR register.
(5)
Update the WSEL bit and write "0" to the interrupt flag (INT) to cancel the wait for the I2C bus.
(6)
Put the I2C bus in a wait by setting the interrupt flag to "1", after receiving an acknowledge upon
the transmission of one byte when WSEL is set to "0", or immediately after one byte has been
transmitted when WSEL is set to "1". Repeat (4) to (6) until a specified number of data elements
are transmitted. However, another interrupt occurs upon the reception of an acknowledge, causing
the bus to wait, when a NACK is received after the wait is cancelled with WSEL set to "1".
(7)
Set the MSS bit to "0" or the SCC bit to "1" to generate a stop condition or a repeated start
condition.
*: When the reserved address is a general call address in multi-master operation, it is necessary to
confirm whether the device will operate as the master or slave for the next data by setting the
ACKE and WSEL bits to "1", if the device may operate as the slave due to the generation of an
arbitration lost condition.
Notes:
• To modify the IBCR register during transmission or reception, modify it when the interrupt flag
(INT) is set to "1".
• When the WSEL bit has been modified, this will be used as a condition for generating the interrupt
flag (INT) for the next data.
• If transmission data is written to the TDR register and an ACK response is detected when the
TDRE is set to "1" during data transmission, the written data will be transmitted without setting the
interrupt flag (INT) to "1".
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14.22 Interrupts of I2C Interface
MB91490 Series
Figure 14.22-10 Master Interrupt (1) - (WSEL = 0, RSA = 0)
S
Slave Address
W ACK
Data
ACK
▲
(1)
Data
ACK Data
ACK P or Sr
▲
(2)
▲▲
(3)
▲
(2)
S : Start condition
W: Data direction bit (write direction)
P : Stop condition
Sr: Repeated start condition
▲: Interrupt by INTE=1
▲: Interrupt by CNDE=1
(1) Interrupt generated by transmission of slave address + transmission of direction bit
+ reception of acknowledge
Writing "0" to INT after writing transmission data to TDR register
(2) Interrupt generated by transmission of 1 byte + reception of acknowledge
Writing "0" to INT after writing transmission data to TDR register
(3) Interrupt generated by transmission of 1 byte + reception of acknowledge
Setting MSS=0 or MSS=1, and SCC=1
Note: The TDRE bit is set to "1" when the interrupt flag (INT) is generated.
Figure 14.22-11 Master Transmission Interrupt (2) (WSEL = 1, RSA = 0, ACK Response)
S
Slave Address
W ACK
▲
(1)
Data
ACK
▲
(2)
Data
ACK Data
▲
(2)
ACK P or Sr
▲ ▲
(3)
S : Start condition
W: Data direction bit (write direction)
P : Stop condition
Sr: Repeated start condition
▲: Interrupt by INTE=1
▲: Interrupt by CNDE=1
(1) Interrupt generated by transmission of slave address + transmission of direction bit
+ reception of acknowledge
Writing "0" to INT after writing transmission data to TDR register
(2) Interrupt generated by transmission of 1 byte
Writing "0" to INT after writing transmission data to TDR register
(3) Interrupt generated by transmission of 1 byte
Setting MSS=0 or MSS=1, and SCC=1
Note: The TDRE bit is set to "1" when the interrupt flag (INT) is generated.
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14.22 Interrupts of I2C Interface
MB91490 Series
Figure 14.22-12 Master Transmission Interrupt (3) (WSEL = 1, RSA = 0, NACK Response)
S
Slave Address
W ACK
Data
▲
(1)
ACK
Data
▲
(2)
ACK Data
▲
(2)
NACK
P or Sr
▲ ▲
(3)
S : Start condition
W: Data direction bit (write direction)
P : Stop condition
Sr: Repeated start condition
▲: Interrupt by INTE=1
▲: Interrupt by CNDE=1
(1) Interrupt generated by transmission of slave address + transmission of direction bit
+ reception of acknowledge
Writing "0" to INT after writing transmission data to TDR register
(2) Interrupt generated by transmission of 1 byte
Writing "0" to INT after writing transmission data to TDR register
(3) Interrupt generated by transmission of 1 byte
Setting MSS=0 or MSS=1, and SCC=1
Note: The TDRE bit is set to "1" when the interrupt flag (INT) is generated.
Figure 14.22-13 Master Transmission Interrupt (4) (WSEL = 1, RSA = 0, NACK Response in the Middle of Operation)
S
Slave Address
W ACK
▲
(1)
Data
ACK
▲
(2)
Data
ACK Data
▲
(2)
NACK
P or Sr
▲ ▲▲
(2) (3)
S : Start condition
W: Data direction bit (write direction)
P : Stop condition
Sr: Repeated start condition
▲: Interrupt by INTE=1
▲: Interrupt by CNDE=1
(1) Interrupt generated by transmission of slave address + transmission of direction bit
+ reception of acknowledge
Writing "0" to INT after writing transmission data to TDR register
(2) Interrupt generated by transmission of 1 byte
Writing "0" to INT after writing transmission data to TDR register
(3) Interrupt generated by NACK response
Setting MSS=0 or MSS=1, and SCC=1
Note: The TDRE bit is set to "1" when the interrupt flag (INT) is generated.
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14.22 Interrupts of I2C Interface
MB91490 Series
Figure 14.22-14 Master Transmission Interrupt (5) (WSEL = 1 -> 0, RSA = 0, ACK Response)
S
Slave Address
W ACK
Data
▲
(1)
ACK
Data
▲
(2)
ACK Data
ACK P or Sr
▲
(2)
▲▲
(3)
S : Start condition
W: Data direction bit (write direction)
P : Stop condition
Sr: Repeated start condition
▲: Interrupt by INTE=1
▲: Interrupt by CNDE=1
(1) Interrupt generated by transmission of slave address + transmission of direction bit
+ reception of acknowledge
Writing "0" to INT after writing transmission data to the transmission buffer
(2) Interrupt generated by transmission of 1 byte
Writing "0" to WSEL and INT after writing transmission data to the transmission buffer
(3) Interrupt generated by transmission of 1 byte
Setting MSS=0 or MSS=1, and SCC=1
Note: The TDRE bit is set to "1" when the interrupt flag (INT) is generated.
Figure 14.22-15 Master Interrupt (6) - (WSEL = 0, RSA = 1)
S
Slave Address
W ACK
▲
(1)
Data
ACK
▲
(2)
Data
ACK Data
▲
(2)
ACK P or Sr
▲▲
(3)
S : Start condition
W: Data direction bit (write direction)
P : Stop condition
Sr: Repeated start condition
▲: Interrupt by INTE=1
▲: Interrupt by CNDE=1
(1) Interrupt generated by transmission of slave address (reserved address) + transmission
of direction bit + reception of acknowledge
Writing "0" to INT after writing transmission data to TDR register
(2) Interrupt generated by transmission of 1 byte + reception of acknowledge
Writing "0" to INT after writing transmission data to TDR register
(3) Interrupt generated by transmission of 1 byte + reception of acknowledge
Setting MSS=0 or MSS=1, and SCC=1
Note: The TDRE bit is set to "1" when the interrupt flag (INT) is generated.
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.22 Interrupts of I2C Interface
■ Master Data Reception
The data transmitted from the slave is received when the data direction bit (R/W) is set to "1".
The master will generate a wait for reception of each byte if the TDRE bit is set to "1" (INT = 1, RDRF =
1), and an ACK or NACK will be returned by the setting of the ACKE bit in the IBCR register, according
to the WSEL bit. When the TDRE bit is set to "0", a wait will not be generated (INT = 0) and the next data
will be received if ACK has been selected by the ACKE bit in the IBCR register, or a wait will be
generated (INT = 1) if NACK has been selected.
For interrupt-triggered waits, refer to the following section.
Table 14.22-4 WSEL Bit During Master Data Reception
WSEL bit
Operation
0
A wait is generated in the second or succeeding byte, when the interrupt flag (INT) is set to "1" and SCL
is set to "L" after an acknowledge by setting the TDRE bit to "1".
1
A wait is generated in the second or succeeding byte, when the interrupt flag (INT) is set to "1" and SCL
is set to "L" after the master transmits 1-byte data by setting the TDRE bit to "1".
An example procedure for receiving data from the slave is shown below.
(1) Set the slave address (including the data direction bit) to the TDR register and write "1" to the
MSS bit.
(2) An ACK will be received after the slave address is transmitted, and then the interrupt flag (INT)
will be set to "1".
(3) Update the WSEL bit and write "0" to the interrupt flag (INT) to cancel a wait for the I2C bus.
(4) Put the I2C bus in a wait by setting the interrupt flag to "1", after transmitting an acknowledge
upon the reception of one byte when WSEL is set to "0", or immediately after one byte has been
received when WSEL is set to "1". Repeat (2) to (4) until a specified number of data elements are
received.
(5) Output a NACK after the reception of the last data, and set the MSS bit to "0" or the SCC bit to "1"
to generate a stop condition or a repeated start condition.
Notes:
• An acknowledge will be output to handle the next data according to the setting of the ACKE bit,
even if an overrun error occurs when TDRE is set to "0".
• Modify the IBCR register during transmission/reception, if necessary, when the interrupt flag (INT)
is set to "1".
• In master reception, the next data will be received with the interrupt flag (INT) still set to "0", if the
TDRE bit is set to "0" when dummy data is written to the TDR register and the interrupt flag (INT)
is set to "1".
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14.22 Interrupts of I2C Interface
MB91490 Series
Figure 14.22-16 Master Reception Interrupt (1) - (WSEL = 0, RSA = 0)
S
Slave Address
R ACK
Data
ACK
▲
Data
ACK
▲
(1)
Data
NACK
▲
(2)
P or Sr
▲▲
(3)
▲: Interrupt by INTE=1
▲: Interrupt by CNDE=1
(1) Interrupt generated by transmission of slave address + transmission of direction bit
+ reception of acknowledge
- Interrupt cleared to "0" by writing "0" to INT
(2) Interrupt generated by reception of 1 byte + transmission of acknowledge
- Setting ACKE to "0" and writing "0" to INT after reading reception data
(3) Interrupt generated by reception of 1 byte + transmission of acknowledge
- Setting MSS=0 or MSS=1, and SCC=1
Note: The TDRE bit is set to "1" when the interrupt flag (INT) is generated.
Figure 14.22-17 Master Reception Interrupt (2) - (WSEL = 1, RSA = 0)
S
Slave Address
R ACK
▲
(1)
Data
ACK
▲
(2)
Data
ACK
Data
▲
(2)
NACK
▲
(3)
P or Sr
▲
▲: Interrupt by INTE=1
▲: Interrupt by CNDE=1
(1) Interrupt generated by transmission of slave address + transmission of direction bit
+ reception of acknowledge
- Interrupt cleared to "0" by writing "0" to INT
(2) Interrupt generated by reception of 1 byte
- Writing "0" to INT after reading reception data
(3) Interrupt generated by reception of 1 byte
- Setting ACKE=0, and then setting MSS=0 or MSS=1, and SCC=1 after reading
reception data
Note: The TDRE bit is set to "1" when the interrupt flag (INT) is generated.
■ Arbitration Lost Condition
When a master receives data which is different from the transmitted data due to a data collision with the
data from another master, this is determined as an arbitration lost condition. Consequently, the MSS bit is
set to "0" and the AL bit to "1" to allow the device to operate in slave mode.
The AL bit can be cleared to "0" under the following conditions.
• "1" is written to the MSS bit.
• "0" is written to the INT bit.
• "0" is written to the SPC bit when the AL and SPC bits are set to "1".
• The I2C interface is disabled (EN bit = 0).
When an arbitration lost condition occurs, the interrupt flag (INT) is set to "1" and the SCL of the I2C bus
is set to "L", according to the setting of WSEL.
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.22 Interrupts of I2C Interface
■ Wait in Master Mode
If the device is not operating in slave mode when the MSS bit is set to "1" with the BB bit set to "1", the
master mode will be put in a wait as long as the BB bit remains set to "1". It will transmit a start condition
once the BB bit becomes "0". The MSS and ACT bits can be used to determine whether the master mode is
in a wait or not (MSS = 1, ACT = 0: wait state). To allow the device to operate in slave mode after the MSS
bit is set to "1", set AL = 1, MSS = 0, and ACT = 1.
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14.22 Interrupts of I2C Interface
14.22.3
MB91490 Series
Slave Mode
In slave mode, the device detects a (repeated) start condition and returns an ACK when
the combination of the ISBA and ISMK registers matches the received address, in order
to operate in slave mode.
■ Slave Address Match Detection
When a (repeated) start condition is detected, the next 7-bit data is received as an address. Each bit of the
ISBA register is compared with the corresponding bit of the received address for the bits which are set to
"1" in the ISMK register. An ACK will be output if there is a match.
Table 14.22-5 Operation Immediately after Output of Acknowledge for Slave Address
Data
direction bit
(R/W)
0
Operation immediately after acknowledge
Acknowledge = ACK
Acknowledge = NACK
The INT bit is set to "1", causing a wait,
when the TDRE bit is set to "1". The INT
The INT bit remains set to "0", causing no wait.
bit remains set to "0", causing no wait,
when the TDRE bit is set to "0".
1
• Reserved address detection
When the first byte matches a reserved address ("0000XXXXB" or "1111XXXXB"), the INT bit is set to
"1" to put the I2C bus in a wait upon the reception of data from the 8th bit. At this point, ACKE is set to
"1" and the INT bit is cleared when allowing the device to operate as a slave. The device will then start
slave operation. When ACKE is set to "0", the device does not operate as a slave after the output of an
acknowledge.
■ Data Direction Bit
The data direction bit, which determines data transmission or reception, is received after an address is
received. When this bit is set to"0", this indicates transmission from the master, therefore, as a slave, the
device will receive data.
■ Slave Reception
Reception is performed in slave mode when there is a slave address match and the data direction bit is set
to "0". An example procedure for reception in slave mode is shown below.
(1) Set the interrupt flag (INT) to "1" to put the I2C bus in a wait after an ACK is transmitted. When
the MSS, ACT and FBT bits determine that the interrupt is caused by a slave address match, set the
ACKE bit to "1" and write "0" to the interrupt flag (INT) to cancel the I2C bus wait. (Refer to
Table 14.22-5.)
(2) After 1-byte data is received, set the interrupt flag (INT) to "1" according to the WSEL setting to
put the I2C bus in a wait.
(3) Read the data received from the RDR register, set the ACKE bit and then write "0" to the interrupt
flag (INT) to cancel the I2C bus wait.
(4) Repeat (2) and (3) until a stop condition or a repeated start condition is detected.
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14.22 Interrupts of I2C Interface
MB91490 Series
Figure 14.22-18 Slave Reception Interrupt (1) - (WSEL = 0, RSA = 0)
S
Slave Address
W ACK
Data
ACK
▲
(1)
Data
ACK
▲
(2)
Data
NACK
▲
(2)
P or Sr
▲▲
(3)
▲: Interrupt by INTE=1
▲: Interrupt by CNDE=1
(1) Interrupt generated by ACK output due to slave address match
- Writing "1" to ACKE and "0" to INT
(2) Interrupt generated by reception of 1 byte + ACK response
- Writing "0" to INT after reception data is read from reception buffer
(3) Interrupt generated by reception of 1 byte + NACK response
- Writing "0" to INT after reception data is read from reception buffer
Figure 14.22-19 Slave Reception Interrupt (2) - (WSEL = 1, RSA = 0)
S
Slave Address
W ACK
Data
▲
(1)
ACK
Data
▲
(2)
ACK
Data
▲
(2)
ACK
▲
(3)
P or Sr
▲
▲: Interrupt by INTE=1
▲: Interrupt by CNDE=1
(1) Interrupt generated by ACK output due to slave address match
- Writing "1" to ACKE and "0" to INT
(2) Interrupt generated by reception of 1 byte
- Writing "0" to INT after reception data is read from reception buffer
(3) Interrupt generated by reception of 1 byte
- Writing "0" to INT after reception data is read from reception buffer
Figure 14.22-20 Slave Reception Interrupt (3) - (WSEL = 1, RSA = 0)
S
Slave Address
W ACK
▲
(1)
Data
ACK
▲
(2)
Data
ACK
Data
▲
(2)
NACK
▲
(2)
P or Sr
▲▲
(3)
▲: Interrupt by INTE=1
▲: Interrupt by CNDE=1
(1) Interrupt generated by ACK output due to slave address match
- Writing "1" to ACKE and "0" to INT
(2) Interrupt generated by reception of 1 byte
- Writing "0" to INT after reception data is read from reception buffer
(3) Interrupt generated by NACK response
- Writing "0" to INT
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14.22 Interrupts of I2C Interface
MB91490 Series
Figure 14.22-21 Slave Reception Interrupt (4) - (WSEL = 0, RSA = 1)
S
Slave Address
W ACK
▲
(1)
Data
ACK
▲
(2)
Data
ACK
Data
▲
(2)
ACK
P or Sr
▲▲
(3)
▲: Interrupt by INTE=1
▲: Interrupt by CNDE=1
(1) Interrupt generated by reserved address ("0000XXXXB" or "1111XXXXB") match
- Reading reception data and writing "1" to ACKE and "0" to INT
(2) Interrupt generated by reception of 1 byte + output of acknowledge
- Writing "0" to INT
(3) Interrupt generated by reception of 1 byte + output of acknowledge
- Interrupt by writing "0" to INT
■ Slave Transmission
Transmission is performed in slave mode when there is a slave address match and the data direction bit is
set to "1". A wait is generated by setting the interrupt flag (INT) to "1" after transmitting one byte or after
returning an acknowledge, depending on the WSEL setting (see Table 14.22-5).
The RACK bit can be used to confirm the acknowledge output from the master. It indicates the end of the
data reception, determining whether or not the master succeeded in the reception at a time of NACK
response. An interrupt will occur to generate a wait if a NACK is detected when WSEL is set to "1".
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14.22.4
CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.22 Interrupts of I2C Interface
Bus Error
A case where a stop condition or a (repeated) start condition is detected during data
transmission/reception on the I2C bus is handled as a bus error.
■ Conditions for the Occurrence of Bus Errors
A bus error sets the BER bit to "1" under the following conditions.
• A (repeated) start condition or a stop condition is detected during the transfer of the first byte.
• A (repeated) start condition or a stop condition is detected in the 2nd bit - 9th (acknowledge) bit of data.
■ Bus Error Operation
Check the BER bit when transmission/reception sets the interrupt flag (INT) to "1". If the BER bit is set to
"1", the error must be treated. The BER bit is cleared when "0" is written to the INT bit.
Although a bus error sets the INT bit to "1", the I2C bus does not enter a wait state with SCL set to "L".
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.23 Dedicated Baud Rate Generator
14.23
MB91490 Series
Dedicated Baud Rate Generator
The dedicated baud rate generator sets a serial clock frequency.
■ Baud Rate Selection
● Baud rate achieved by dividing the internal clock using the dedicated baud rate generator (reload
counter)
There are two internal reload counters, and both support the transmission/reception serial clock. The baud
rate can be selected via the 15-bit reload value determined by the baud rate generator registers 1, 0 (BGR1,
BGR0).
The reload counter divides the internal clock, according to the set value.
■ Calculating the Baud Rate
The two 15-bit reload counters are set by the baud rate generator registers 1, 0 (BGR1, BGR0).
The following formula should be used to calculate a baud rate.
(1) Reload value:
V = / b -1
V: Reload value
b: Baud rate
: Peripheral clock (CLKP) frequency
Note that the set baud rate may not be generated depending on the SCL rising time of the
I2C bus. In that case, the reload value must be adjusted.
(2) Example of calculation:
If the peripheral clock (CLKP) is 16MHz and the baud rate is 400kbps, the reload value will be:
Reload value:
V = (16  1000000)/400000 -1 = 39
As a result, the baud rate is:
b= (16  1000000)/(38+2)= 400 kbps
Notes:
• Use 16-bit access to write to the baud rate generator registers 1, 0 (BGR1, BGR0).
• Set the baud rate generator registers when the EN bit in the ISMK register is "0".
• Use the peripheral clock (CLKP) at 8 MHz or higher in operation mode 4 (I2C mode). It is
prohibited to set the baud rate generator to higher than 400kbps.
• The reload counter stops when the reload value is set to "0".
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.23 Dedicated Baud Rate Generator
MB91490 Series
■ Reload Values and Baud Rates for Different Peripheral Clock (CLKP) Frequencies
Table 14.23-1 Reload Values and Baud Rates
Baud rate
[bps]
8 MHz
10 MHz
16 MHz
20 MHz
24 MHz
32MHz
Reload value Reload value Reload value Reload value Reload value Reload value
400000
19
24
39
49
59
79
200000
39
49
79
99
119
159
100000
79
99
159
199
239
319
These numerical values are based on the SCL rising time of I2C bus set to "0". If the rising is slower, the
actual baud rates should also be slower than the numerical values above.
■ Functions of Reload Counters
Structured in a 15-bit register configuration based on a reload value, these counters generate a transmission/
reception clock from the internal clock. In addition, the count value of the transmission reload counter can
be read from the baud rate generator registers 1, 0 (BGR1, BGR0).
■ Starting a Count
The reload counter starts a count when a reload value is written to the baud rate generator registers 1, 0
(BGR1, BGR0).
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.23 Dedicated Baud Rate Generator
14.23.1
MB91490 Series
Example of I2C Flowcharts
Below are some example flowcharts for I2C communication.
■ Example of I2C Flowcharts
Figure 14.23-1 Example of I2C Flowchart 1
Start
<Initial setup>
Setting baud rate (BGR)
Slave address (ISBA)
Setting slave mask (ISMK)
Enabling I2C (ISMK:EN=1)
NO
Master?
YES
Writing transmission data (TDR)
Setting master (IBCR:MSS = 1)
IBCR:INT =1?
A
NO
YES
IBCR:BER = 0?
NO
YES
IBCR:ACT = 1?
Handling bus error
NO
YES
IBCR:MSS = 1?
Handling arbitration lost condition
NO
YES
IBSR:RSA = 0?
YES
IBSR:RACK = 0?
End
Slave
NO
Reserved
address A
NO
YES
IBSR:TRX = 1?
NO
YES
Transmission
completed?
B
NO
NO
IBSR:FBT=0 ?
YES
Reading reception data (RDR)
YES
Writing transmission data
(TDR)
Setting wait (IBCR:WSEL)
Setting ACK (IBCR:ACKE)
Clearing interrupt flag
(BCR:INT = 0)
YES (NACK response)
Setting wait (IBCR:WSEL)
Setting ACK (IBCR:ACKE = 0)
Repeated start?
NO
Reception completed?
NO
Setting wait (IBCR:WSEL = 1)
Setting ACK (IBCR:ACKE = 1)
Clearing interrupt flag
(IBCR:INT = 0)
YES
Writing transmission data (TDR)
Setting repeated start
(IBCR:MSS = SCC = 1)
Setting ACK (IBCR:ACKE)
Setting stop (IBCR:MSS = 0)
Setting ACK (IBCR:ACKE)
Clearing interrupt flag (IBCR:INT = 0)
End
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.23 Dedicated Baud Rate Generator
MB91490 Series
Figure 14.23-2 Example of I2C Flowchart 2
Slave
NO
IBSR:RSA = 0?
YES
IBSR:TRX = 0?
NO
YES
NO
IBSR:FBT = 0?
NO
IBSR:RACK = 0?
YES
Reading reception data (RDR)
YES
Clearing interrupt flag
(IBCR:INT = 0)
Setting wait (IBCR:WSEL)
Setting ACK (IBCR:ACKE)
Clearing interrupt flag
(IBCR:INT = 0)
Writing transmission data (TDR)
Setting wait (IBCR:WSEL)
Clearing interrupt flag
(IBCR:INT = 0)
End
A
NO
IBSR:FBT = 1?
YES
Reading reception data (RDR)
NO
Slave operation?
YES
NO
IBSR:TRX = 1?
YES
Writing transmission data (TDR)
Setting wait (IBCR:WSEL)
Setting ACK (IBCR:ACKE = 0)
Clearing interrupt flag
(IBCR:INT = 0)
IBSR:FBT = 1?
YES
NO
Reading reception data (RDR)
Setting wait (IBCR:WSEL)
Setting ACK (IBCR:ACKE=1)
Clearing interrupt flag (IBCR:INT=0)
A
CM71-10155-2E
Setting ACK (IBCR:ACKE = 0)
Clearing interrupt flag
(IBCR:INT = 0)
End
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14.23 Dedicated Baud Rate Generator
MB91490 Series
Figure 14.23-3 Example of I2C Flowchart 3
Reserved
address
NO
IBSR:FBT = 1?
YES
NO
Multi-master?
YES
Reading reception data (RDR)
Setting wait (IBCR:WSEL = 1)
Setting ACK (IBCR:ACKE = 1)
Clearing interrupt flag
(IBCR:INT = 0)
Reading reception data (RDR)
Setting wait (IBCR:WSEL)
Setting ACK (IBCR:ACKE)
Clearing interrupt flag
(IBCR:INT = 0)
A
NO
IBSR:TRX = 1?
Reading reception data (RDR)
YES
NO
SSR:RDRF = 1?
YES (NACK response)
YES
Setting wait (IBCR:WSEL = 1)
Setting ACK (IBCR:ACKE = 1)
Clearing interrupt flag
(IBCR:INT = 0)
NO
YES
Transmission completed?
NO
Setting wait (IBCR:WSEL)
Setting ACK (IBCR:ACKE=0)
Reading reception data (RDR)
IBSR:RACK = 0?
Reception completed?
YES
NO
B
A
Writing transmission data (TDR)
Setting wait (IBCR:WSEL)
Setting ACK (IBCR:ACKE = 0)
Clearing interrupt flag
(IBCR:INT = 0)
A
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.24 Notes on I2C Mode
MB91490 Series
14.24
Notes on I2C Mode
The notes for when you use the I2C mode are shown below.
• To request a DMA transfer request, set the block size of DMA to one time.
• When master reception and slave reception are selected, it is required to use two channels for DMA;
one is used for DMA transfer to receive data and the other one is used for DMA transfer to send dummy
data.
• In I2C mode, if there is no valid data in transmission register (TDR), and transmission data empty flag
bit (TDRE) is "1", the interrupt flag (INT) becomes "1" as shown in Figure 14.24-1 when the data on
I2C bus for 9 bits (WSEL=0) or for 8 bits (WSEL=1) is transmitted. When the interrupt flag (INT)
becomes "1" during DMA transfer, DMA transfer cannot be continued unless clearing the bit to "0" by
software. (Common to master transmission, slave transmission, master reception, and slave reception.)
Figure 14.24-1 INT Bit Change Timing of I2C (WSEL= 0 )
SCL
SDA
DATA
ACK
DATA
ACK
TDRE bit
DMA transfer
to TDR
INT bit
To perform DMA transfer in I2C mode, since the specification is as shown above, such operations listed
below are required for performing DMA transfer to TDR before the interrupt flag (INT) becomes "1".
Below operations are possible to perform to prioritize DMA transfer of I2C.
- Use DMA which has a higher priority (channel number is small). It is enabled to use by fixing the
priority setting bit (AT=0).
- Set the value of DMA-halt by interrupt level bit as small as possible (LVL4-LVL0 bit in DILVR
register).
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CHAPTER 14 MULTI-FUNCTION SERIAL INTERFACE
14.24 Notes on I2C Mode
MB91490 Series
• In case of writing the transmission data to transmission data register (TDR) by DMA transfer after
transmission data empty flag (SSR: TDRE) becomes "1", or writing the data by software confirming the
transmission data empty flag (SSR:TDRE), transmission data empty flag (SSR:TDRE) may not become
"0". Therefore, the transmission data should be written before SCL in ACK field falls. There are no
restrictions on writing the transmission data by software after the interrupt flag (IBCR:INT) becomes
"1".
When performing DMA transfer or sending the data by software confirming the transmission data
empty flag (SSR:TDRE), please follow below procedures if the data cannot be written before SCL in
ACK field falls.
- Setting
Set the timing of interrupt flag (IBCR:INT) becoming "1" to the 8th bit (WSEL=1).
- Procedures
To transmit or receive data by master, the following procedures are required. To transmit or receive
data by slave, it is not required to perform the following.
1. Write the first byte (slave address) to the transmission data register by software.
2. Set to 8-bit for wait selection (IBCR:WSEL="1" write) at the same time that master is started
(IBCR:MSS="1" write).
3. After sending the first byte, the interrupt flag (IBCR:INT) becomes "1". Write the second byte to
transmission data register (TDR) by software after confirming ACK response (IBSR:RACK="0").
Set the DMAC, and activate DMA transfer, then write "0" to interrupt flag (IBCR:INT).
4. After transmission and reception are completed, terminate the master (IBCR:MSS="0" write) or
reboot (IBCR:SCC="1" write).
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CHAPTER 15
8/10-BIT A/D CONVERTER
This chapter describes the overview of the 8/10-bit A/D
converter, the configuration and functions of registers,
and the operation of the 8/10-bit A/D converter.
15.1 Overview of the 8/10-bit A/D Converter
15.2 Configuration of the 8/10-bit A/D Converter
15.3 Pin of the 8/10-bit A/D Converter
15.4 Registers of the 8/10-bit A/D Converter
15.5 Interrupt of the 8/10-bit A/D Converter
15.6 Operation Explanation of the 8/10-bit A/D Converter
15.7 A/D Conversion Data Protection Function of the 8/10-bit A/D
Converter
15.8 Using Memorandum of the 8/10-bit A/D Converter
15.9 Notes on Using the 8/10-bit A/D Converter
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CHAPTER 15 8/10-BIT A/D CONVERTER
15.1 Overview of the 8/10-bit A/D Converter
15.1
MB91490 Series
Overview of the 8/10-bit A/D Converter
The 8/10-bit A/D converter has a feature to convert analog input voltage to a 8/10-bit
digital value, using the RC successive comparison/conversion method. The input signal
can be selected from different channels of analog input pin, and three types of
conversions can be activated: software, internal timer, and external pin trigger.
■ Function of 8/10-bit A/D Converter
There is an A/D conversion feature to convert analog voltage (input voltage) input to the analog input pins
into digital values.
• The conversion time is a minimum of 1.2 s (including the sampling time at 33 MHz peripheral clock
(CLKP)).
• The conversion method used is the RC successive comparison conversion with sample hold circuit.
• The resolution of the conversion result can be selected to be 8 bits or 10 bits
• The analog input pin can be selected using program.
• The A/D data register is provided for each analog input channel.
• The A/D data register has an error flag bit and a error status bit, it can know the A/D conversion data
state according to these values.
• DMAC can be started by the A/D conversion end interrupt.
• One of the following conversion activation causes can be selected: software, 16-bit reload timer 1,
multi-functional timer (rising edge), or external pin triggers (falling edge).
• There is register bit to select 1 out of 2 sets of A/D converter function:
Function 1:
- Each analog input channel has an A/D data register.
- Generate interrupt request after all selected channels finished A/D conversion
- No conversion data protection
Function 2:
- Only 1 A/D data register available. All channels use the same data register.
- Generate interrupt request after all selected channels finished A/D conversion
- Data is not missed even if the continuous conversion is done, because the conversion data protection
function is operating in the interrupt enable status.
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CM71-10155-2E
CHAPTER 15 8/10-BIT A/D CONVERTER
15.1 Overview of the 8/10-bit A/D Converter
MB91490 Series
There are three conversion modes.
Table 15.1-1 Conversion Modes of 8/10-bit A/D Converter
Conversion Mode
CM71-10155-2E
Single Conversion Operation
Scanning Conversion Operation
Single conversion
mode
The specified channel (one
channel only) is converted for one
time and terminated.
Continuous multiple channels (more than 1
channel can be specified) are converted for
one time and terminated.
Continuous
conversion mode
Repeatedly convert specified
channel (1 channel only).
Repeatedly convert multiple channels in
succession (more than 1 channel can be
specified).
Pause-conversion
mode
The specified channel (one
channel only) is converted for one
time and suspended until the next
start.
Continuous multiple channels (more than 1
channel can be specified) are converted.
However, one channel is converted and
suspended until the next start.
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CHAPTER 15 8/10-BIT A/D CONVERTER
15.2 Configuration of the 8/10-bit A/D Converter
15.2
MB91490 Series
Configuration of the 8/10-bit A/D Converter
The 8/10-bit A/D converter is made up of the following 11 blocks.
• A/D control status registers (ADCS)
• A/D channel control register (ADCH)
• A/D mode setting register (ADMD)
• A/D data register (ADCD)
• Clock selector (input clock selector for activation of A/D conversion)
• Decoder
• Analog channel selector
• Sample hold circuit
• D/A converter
• Comparator
• Control circuit
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CM71-10155-2E
CHAPTER 15 8/10-BIT A/D CONVERTER
15.2 Configuration of the 8/10-bit A/D Converter
MB91490 Series
■ Block Diagram of 8/10-bit A/D Converter
Figure 15.2-1 Block Diagram of 8/10-bit A/D Converter
R- bus
Unit 1
A/D channel control register 1
(ADCH1)
Decoder
A/D converter
D/A
converter
A/D data register 001-031
(ADCD001-031)
Successive
approximation
register
Input
circuit
(Selector)
Comparator
AN 1-0(PB4)
AN 1-1(PB5 )
AN 1-2(PB6)
AN 1-3(PB7)
Prescaler
Peripheral clock (CLKP)
Sample & hold
circuit
A/D mode setting register 1
(ADMD1)
Multi-function timer or
16-bit reload timer 1
A/D activation
selector
External pin trigger
(ADTG1)
AVCC10
AVRH2
A/D control status register 1
(ADCS1)
AVSS10
Conversion end interrupt
R-bus
Unit 2
A/D channel control register 2
(ADCH2)
Decoder
A/D converter
D/A
converter
A/D data register 002-072
(ADCD002-072)
Successive
approximation
register
Input
circuit
(Selector)
Comparator
Peripheral clock (CLKP)
AN 2-0(PC0)
AN 2-1(PC1)
AN 2-2(PC2)
AN 2-3(PC3)
AN 2-4(PC4)
AN 2-5(PC5)
AN 2-6(PC6)
AN 2-7(PC7)
Prescaler
Sample & hold
circuit
A/D mode setting register 2
(ADMD2)
Multi-function timer
A/D activation
selector
External pin trigger
(ADTG2)
A/D control status register 2
(ADCS2)
AVCC10
AVRH2
AVSS10
Conversion end interrupt
CM71-10155-2E
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CHAPTER 15 8/10-BIT A/D CONVERTER
15.2 Configuration of the 8/10-bit A/D Converter
MB91490 Series
●A/D control status registers (ADCS)
Features are available to suspend and confirm conversion, enable/disable interrupt requests, confirm the
status of interrupt requests and select the A/D conversion resolution and the conversion function (function
1/ function 2).
● A/D channel control register (ADCH)
There is a feature to select the A/D channel.
● A/D mode setting register (ADMD)
There is a feature to select a conversion mode and to set the A/D conversion compare time and sampling time.
● A/D data register (ADCD)
This register stores A/D conversion results. Flag bits to indicate the status of data in data register.
● Clock selector (Input clock selector for activation of A/D conversion)
This is an A/D conversion activation clock selector. 16-bit reload timer channel 1 output, multi-functional
timer and external pin trigger can be selected as the activation clock.
● Decoder
The A/D channel control register (ADCH) ANE0 to ANE2 and ANS0 to ANS2 bit settings are a circuit to
select the analog input pin to use.
● Analog channel selector
This circuit selects the pin to be used from different analog input pins.
● Sample hold circuit
This circuit holds the input voltage selected by the analog channel selector. The input voltage can be
converted without affected by the input voltage fluctuation in the A/D conversion (in the comparison) by
holding the sample of input voltage immediately after starting the A/D conversion.
● D/A converter
The reference voltage is generated to compare with the held sample of input voltage.
● Comparator
This compares the input voltage for which sample hold is performed, with the output voltage of the D/A
converter to determine which is the greater of the two.
● Control circuit
The signal from the comparator (higher or lower) determines the A/D conversion value. When the A/D
conversion is terminated, this result is stored in the A/D data register (ADCD) and the interrupt request is
generated.
540
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CHAPTER 15 8/10-BIT A/D CONVERTER
15.3 Pin of the 8/10-bit A/D Converter
MB91490 Series
15.3
Pin of the 8/10-bit A/D Converter
Pins of 8/10-bit A/D converter and block diagram of pin are shown.
■ Pins of 8/10-bit A/D Converter
The A/D converter pin serves dual use as a general-purpose port. Table 15.3-1 shows pin functions, I/O
type, and settings when using the 8/10-bit A/D converter.
Table 15.3-1 Pins of 8/10-bit A/D Converter
Function
Pin Name
Pin Function
I/O Type
Pull-up
Setting
Stand-by
Control
I/O Port Setting for Using Pin
PB4/AN1-0
Unit 1
ch.0 to ch.3
PB5/AN1-1
PB6/AN1-2
PB7/AN1-3
PC0/AN2-0
PC1/AN2-1
PC2/AN2-2
Unit 2
ch.0 to ch.7
PC3/AN2-3
PC4/AN2-4
Input setting of port B
(DDRB: bit0 to bit3=0)
Set to analog input
(AICR1 bit0 to bit3=1)
Port B I/O/
analog input
Port C I/O/
analog input
Yes
(the pullup
CMOS output/ function
CMOS
does not
hysteresis input
work
or analog input when
analog
input is
enabled.)
Yes
Input setting of port B
(DDRC: bit0 to bit7=0)
Set to analog input
(AICR2: bit0 to bit7=1)
PC5/AN2-5
PC6/AN2-6
PC7/AN2-7
External trigger
input ADTG1,
ADTG2
CM71-10155-2E
CMOS output/
Port A I/O/
CMOS
external trigger
PA2/ADTG2
input
hysteresis input
PA1/ADTG1
Yes
FUJITSU SEMICONDUCTOR LIMITED
Input setting of port A (DDRA:
bit1, bit2=0)
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CHAPTER 15 8/10-BIT A/D CONVERTER
15.4 Registers of the 8/10-bit A/D Converter
15.4
MB91490 Series
Registers of the 8/10-bit A/D Converter
Register list of 8/10-bit A/D converter is shown.
■ Register List of 8/10-bit A/D Converter
Figure 15.4-1 Register List of 8/10-bit A/D Converter
AICR2
Analog input control register (upper): unit 2
Address
000170H
bit15
-
bit14
-
bit13
-
bit11
-
bit10
-
bit9
-
bit8
-
Initial value
- - - - - - - -B
bit4
AN4E
R/W
bit3
AN3E
R/W
bit2
AN2E
R/W
bit1
AN1E
R/W
bit0
AN0E
R/W
Initial value
11111111B
bit4
-
bit3
AN3E
R/W
bit2
AN2E
R/W
bit1
AN1E
R/W
bit0
AN0E
R/W
Initial value
- - - - 1111B
bit12
-
Analog input control register (lower): unit 2
Address
000171H
bit7
AN7E
R/W
bit6
AN6E
R/W
bit5
AN5E
R/W
AICR1
Analog input control register: unit 1
Address
000511H
bit7
-
bit6
-
bit5
-
ADCS1/ADCS2
A/D control status register: unit 1/2
Address
000514H
000174H
bit15
BUSY
R/W
bit14
INT
R/W
bit13
INTE
R/W
bit12
PAUS
R/W
bit11
bit10
bit9
S10 FuncSet START
R/W
R/W
R/W
bit12
ANS0
R/W
bit11
-
bit10
ANE2
R/W
bit4
STS0
R/W
bit3
CT1
R/W
bit2
CT0
R/W
Initial value
bit8
-
0000000 - B
bit9
ANE1
R/W
bit8
ANE0
R/W
- 000 - 000B
bit1
ST1
R/W
bit0
ST0
R/W
ADCH1/ADCH2
A/D channel control register: unit 1/2
Address
000516H
000176H
bit15
-
bit14
ANS2
R/W
bit13
ANS1
R/W
Initial value
ADMD1/ADMD2
A/D mode setting register: unit 1/2
Address
000517H
000177H
bit7
MD1
R/W
bit6
MD0
R/W
bit5
STS1
R/W
Initial value
00001111B
(Continued)
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CM71-10155-2E
CHAPTER 15 8/10-BIT A/D CONVERTER
15.4 Registers of the 8/10-bit A/D Converter
MB91490 Series
(Continued)
ADCD001 to ADCD031/ADCD002 to ADCD072
A/D data register (upper): unit 1/2
Address
000518H to 00051EH
000178H to 000186H
bit15
ERR
R
bit14
ERRST
R
bit13
-
bit12
-
bit11
-
bit10
-
bit9
D9
R
bit8
D8
R
bit5
D5
R
bit4
D4
R
bit3
D3
R
bit2
D2
R
bit1
D1
R
bit0
D0
R
Initial value
10- - - - XXB
A/D data register (lower): unit 1/2
Address
000519H to 00051FH
000719H to 000187H
bit7
D7
R
bit6
D6
R
Initial value
XXXXXXXXB
R/W: Readable/writable
R:
Read only
-:
Undefined bit
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CHAPTER 15 8/10-BIT A/D CONVERTER
15.4 Registers of the 8/10-bit A/D Converter
15.4.1
MB91490 Series
A/D Channel Control Register (ADCH)
The A/D channel control register has a feature to select the A/D conversion channel.
■ A/D Channel Control Register (ADCH: ADCH1, ADCH2)
Address
000516H
000176H
R/W
-
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
-
ANS2
ANS1
ANS0
-
ANE2
ANE1
ANE0
-0 00 -0 00 B
-
R/W
R/W
R/W
-
R/W
R/W
R/W
ANE2
0
0
0
0
1
1
1
1
ANE1
0
0
1
1
0
0
1
1
ANE0
0
1
0
1
0
1
0
1
A/D conversion end channel selection bits
ANS2
0
0
0
0
1
1
1
1
ANS1
0
0
1
1
0
0
1
1
ANS0
0
1
0
1
0
1
0
1
A/D conversion start channel selection bits
ch.0
ch.1
ch.2
ch.3
ch.4
ch.5
ch.6
ch.7
ch.0
ch.1
ch.2
ch.3
ch.4
ch.5
ch.6
ch.7
: Readable/Writable
: Undefined bit
: Initial value
Notes:
• A/D unit 1 has ch.0 to ch.3 and does not contain ch.4 to ch.7. Therefore, be sure to set the ANS2
and ANE2 bits of the ADCH1 register to "0".
• Be sure to set become "ANS  ANE".
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CM71-10155-2E
CHAPTER 15 8/10-BIT A/D CONVERTER
15.4 Registers of the 8/10-bit A/D Converter
MB91490 Series
Table 15.4-1 Functions of Each Bit in A/D Channel Control Register (ADCH)
Bit Name
bit15
Undefined bit
Function
• The read value is always "0".
• Set this bit to "0".
• These bits set the start channel of the A/D conversion and indicate the channel numbers
under A/D conversion during conversion operation.
• When A/D conversion is activated, A/D conversion starts from the channels written to
these bits.
• Channel numbers under the conversion can be read during the A/D conversion. The
channel number converted immediately before can be read during the suspension in the
pause conversion mode.
bit14
to
bit12
ANS2 to ANS0:
Notes:
A/D conversion start
• Be sure to set the smaller number than the number of input channel to ANS bit.
channel selection bits
• Only rewrite these bits before conversion begins, with the A/D operation stopped.
• Do not set this register bit by the read-modify-write instruction after setting the start
channel to A/D conversion start channel select bits (ANS2 to ANS0).
Because the last conversion channel is read from the ANS2 to ANS0 bits until
starting the A/D conversion operation, when this register bit is set by the readmodify-write instruction after setting the start channel to the ANS2 to ANS0 bits, the
value of the ANE2 to ANE0 bits should be re-written.
bit11
Undefined bit
• The read value is always "0".
• Set this bit to "0".
• These bits set the end channel of the A/D conversion.
• A/D conversion is performed up to the specified channel written in these bits.
bit10
to
bit8
• When the same channels with ANS2 to ANS0 are set, only those channels are
converted.
If continuous conversion mode or stop conversion mode is set, when the conversion up
ANE2 to ANE0:
to the channels specified in these bits is completed, conversion returns to the start
A/D conversion end
channel
set in ANS2 to ANS0.
channel selection bits
Notes:
• Never set ANE bit larger than the max. available channel in the product series.
• Be sure to set become "ANS  ANE".
• Only rewrite these bits before conversion begins, with the A/D operation stopped.
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CHAPTER 15 8/10-BIT A/D CONVERTER
15.4 Registers of the 8/10-bit A/D Converter
15.4.2
MB91490 Series
A/D Mode Setting Register (ADMD)
The A/D mode setting register has a feature to select a conversion mode and to set the
A/D conversion compare time and sampling time.
■ A/D Mode Setting Register (ADMD: ADMD1, ADMD2)
Address
bit7
000517H
000177H
MD1
R/W
bit6
bit5
MD0
STS1
STS0
CT1
R/W
R/W
R/W
R/W
bit4
bit3
bit1
bit0
Initial value
CT0
ST1
ST0
0000 1111B
R/W
R/W
R/W
bit2
ST1 ST0
Sampling time setting bits
10 peripheral clock (CLKP) cycles (400 ns @ 25 MHz) *
0
0
13 peripheral clock (CLKP) cycles (390 ns @ 33 MHz) *
0
1
1
0
16 peripheral clock (CLKP) cycles (400 ns @ 40 MHz) *
1
1
32 peripheral clock (CLKP) cycles (800 ns @ 40 MHz) *
*: Set the peripheral clock (CLKP) cycle to at least 390 ns.
CT1 CT0
Compare time setting bits
0
0
18 peripheral clock (CLKP) cycles (720 ns @ 25 MHz) *
24 peripheral clock (CLKP) cycles (720 ns @ 33 MHz) *
0
1
30 peripheral clock (CLKP) cycles (750 ns @ 40 MHz) *
1
0
60 peripheral clock (CLKP) cycles (1500 ns @ 40 MHz)*
1
1
*: Set the peripheral clock (CLKP) cycle to at least 720 ns.
STS1 STS0
A/D start factor selection bits
0
0
Software start
External pin trigger (falling edge) or
0
1
Software start
Timer trigger (rising edge) or
1
0
Software start
External pin trigger (falling edge) or
Timer trigger (rising edge) or
Software start
Note: 16-bit reload timer 1 or multi-function timer for unit 2
1
R/W
546
: Readable/Writable
: Initial value
MD1
0
0
1
1
MD0
0
1
0
1
1
A/D conversion mode selection bits
Single conversion mode 1 (restarting is enabled during operation)
Single conversion mode 2 (restarting is disabled during operation)
Continuous conversion mode (restarting is disabled during operation)
Stop conversion mode (restarting is disabled during operation)
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
CHAPTER 15 8/10-BIT A/D CONVERTER
15.4 Registers of the 8/10-bit A/D Converter
MB91490 Series
Table 15.4-2 Functions of Each Bit in A/D Mode Setting Register (ADMD: ADMD1, ADMD2) (1 / 2)
Bit Name
Function
• These bits are used to select the conversion mode during the A/D conversion operation.
• Two bit values of MD1 and MD0 allow the selection of either the single conversion mode
1, the single conversion mode 2, the continuous conversion mode, or the stop conversion
mode.
• The meaning of each mode is as follows.
Single conversion mode 1:
bit7,
bit6
MD1, MD0:
A/D conversion
mode selection
bits
The continuous A/D conversion from the setting channels of
ANS2 to ANS0 to the setting channels of ANE2 to ANE0 is
performed only once. It is possible to reactivate while
operating.
Single conversion mode 2: The continuous A/D conversion from the setting channels of
ANS2 to ANS0 to the setting channels of ANE2 to ANE0 is
performed only once. It is not possible to reactivate while
operating.
Continuous conversion mode: Sequentially perform A/D conversion from the channel set in
ANS2 to ANS0 to the channel set in ANE2 to ANE0, and
repeat until forcibly stopped by means of the BUSY bit. It is
not possible to reactivate while operating.
Stop conversion mode:
Perform A/D conversion from the channel set in ANS2 to
ANS0 to the channel set in ANE2 to ANE0 one channel at a
time, pausing between each, and repeat until forcibly stopped
by means of the BUSY bit. It is not possible to reactivate
while operating. The suspended conversion is restarted by the
start factor occurrence selected by the STS1 and STS0 bits.
Notes:
• Single, continuous, and stop conversion modes that cannot be re-started can be used to
activate all timers, external triggers, and software.
• Only rewrite these bits before conversion begins, with the A/D operation stopped.
• When A/D conversion mode selection bits (MD1, MD0) are set to "00B", it is possible to
reactivate in the A/D conversion. Only software activating (STS1, STS0=00B) can be set
in this mode. Reactivate according to the following procedure;
(1) Clear the INT bit to "0".
(2) Write "1" to the START bit and write "0" to the INT bit at the same time.
• The start factor of A/D conversion is selected.
• When the start factor is in the common use, the first start factor generation starts the
operation.
bit5,
bit4
STS1, STS0:
A/D start factor
selection bits
Notes:
• The activation trigger changes as soon as the bits are rewritten, so if you wish to rewrite
them while A/D conversion is ongoing, switch to a state where your target activation
trigger does not exist.
• If the STS1, STS0 bits are 11B, the timer cannot start then the external trigger input is
"L". Also, the external trigger cannot be started when the timer is "H".
CM71-10155-2E
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CHAPTER 15 8/10-BIT A/D CONVERTER
15.4 Registers of the 8/10-bit A/D Converter
MB91490 Series
Table 15.4-2 Functions of Each Bit in A/D Mode Setting Register (ADMD: ADMD1, ADMD2) (2 / 2)
Bit Name
Function
These bits are used to select the comparison time at the A/D conversion.
bit3,
bit2
CT1, CT0:
Compare time
setting bits
• After analog input is loaded (after the sampling time has elapsed), then after the time
specified in these bits has passed, the conversion results are checked, and stored in the
A/D data register (ADCD).
Notes:
• Set for the compare time to become 720 ns or more. If the compare time is set to 720 ns
or less, the normal analog conversion value might not be obtained.
• Only rewrite these bits before conversion begins, with the A/D operation stopped.
These bits are used to select the sampling time at the A/D conversion.
When A/D is activated, analog input is retrieved for the time set in these bits.
bit1,
bit0
ST1, ST0:
Sampling time
setting bits
Notes:
• Set for the sampling time to become 390 ns or more. If the sampling time is set to 390 ns
or less, the normal analog conversion value might not be obtained.
• Only rewrite these bits before conversion begins, with the A/D operation stopped.
548
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
CHAPTER 15 8/10-BIT A/D CONVERTER
15.4 Registers of the 8/10-bit A/D Converter
MB91490 Series
15.4.3
A/D Control Status Register (ADCS)
The A/D control status register has features to suspend and confirm conversion,
enable/disable interrupt requests, confirm the status of interrupt requests, and select
the A/D conversion resolution and the conversion function (function 1/function 2).
■ A/D Control Status Register (ADCS: ADCS1, ADCS2)
Address
bit15
000514H
000174H
R/W
BUSY
bit14
INT
R/W
bit13
bit12
INTE
PAUS
S10
FuncSet
R/W
R/W
R/W
R/W
START
0
1
FuncSet
0
1
S10
0
1
PAUS
0
1
INTE
0
1
INT
0
1
R/W
W
-
: Readable/Writable
: Write only
: Undefined bit
: Initial value
CM71-10155-2E
BUSY
0
1
bit11
bit10
bit8
Initial value
START
-
0000 000-B
W
-
bit9
A/D conversion start bit
(Only enable at software starting)
A/D conversion function is not starting.
A/D conversion function is starting.
A/D conversion function selection bit
Set 1: Each analog input channel has 1 A/D
data register. Generate an interrupt request
after all selected channels finished A/D conversion.
No conversion data protection function operates.
Set 2: All analog input channel share 1 A/D
data register. Generate an interrupt request
after all selected channels finished A/D conversion.
Data is not missed even if the continuous conversion
is done, because the conversion data protection
function is operating in the interrupt enable status.
A/D conversion resolution selection bit
10-bit resolution (D0 to D9)
8-bit resolution (D0 to D7)
Temporary stop flag bit
Generate no halting of A/D conversion operation
Halt on A/D conversion operation
Interrupt request enable bit
Interrupt request output is disabled.
Interrupt request output is enabled.
At read
Interrupt request flag bit
At write
No A/D conversion ends
A/D conversion ends
Bit clear
No change, no impact to others.
A/D converting bit
At read
Now stop A/D conversion
Now A/D converting
FUJITSU SEMICONDUCTOR LIMITED
At write
A/D conversion forcibly stops
No change, no impact to others.
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CHAPTER 15 8/10-BIT A/D CONVERTER
15.4 Registers of the 8/10-bit A/D Converter
MB91490 Series
Table 15.4-3 Function of Each Bit in A/D Control Status Register (ADCS) (1 / 2)
Bit Name
Function
• Operational display bit of A/D converter
• When reading, if this bit is "0", it indicates that A/D conversion is stopped. If it is "1",
it indicates that A/D conversion is ongoing.
bit15
BUSY:
A/D converting bit
• When writing, writing "0" to this bit forcibly stops A/D conversion. When "1" is
written, the conversion is not changed and no others are affected.
• "1" is always read during read modify write (RMW) instruction.
Note:
Do not perform a forced stop and software activation (BUSY = 0, START = 1) at
the same time.
• This INT bit is set to 1 if data is set in A/D data register through A/D conversion.
• If this bit and the interrupt request enable bit (ADCS: INTE) are "1", an interrupt
request is generated.
bit14
INT:
Interrupt request
flag bit
• When writing, "0" clears this bit, and with "1" no change is made, and there are no
other effects.
• "1" is always read during read modify write (RMW) instruction.
Note:
Clear this bit by writing "0" while the A/D is stopping.
bit13
INTE:
Interrupt request
enable bit
• This bit is used to enable and disable the interrupt output to CPU.
• If this bit and the interrupt request flag bit (ADCS: INT) are "1", an interrupt request
is generated.
• It is set to 1 when A/D conversion is suspended.
bit12
PAUS:
Temporary stop flag
bit
• This bit is set to 1 automatically when A/D enters conversion data protection function.
During this time, A/D conversion will halt and will not store any new coming data
• Clear this flag only by writing "0" to this register.
• 1 is always read during read modify write (RMW) instruction.
• Refer to Section "15.7 A/D Conversion Data Protection Function of the 8/10-bit A/D
Converter" for detail operation.
• This bit is used to select the A/D conversion resolution.
bit11
S10:
A/D conversion
resolution selection
bit
• Write 0 to this bit to select 10-bit resolution. Write 1 to this bit select 8-bit resolution
Notes:
• The data bit used are different depending on the resolution.
• Only rewrite this bit before conversion begins, with the A/D operation stopped.
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CHAPTER 15 8/10-BIT A/D CONVERTER
15.4 Registers of the 8/10-bit A/D Converter
MB91490 Series
Table 15.4-3 Function of Each Bit in A/D Control Status Register (ADCS) (2 / 2)
Bit Name
Function
• This bit is used to select the function set for A/D conversion.
• Write 0 to this bit select function set 1:
- Each input channel has 1 data register
- Generate interrupt after all selected channel finished conversion
bit10
Func Set:
A/D conversion
function selection
bit
- No data protection
• Write 1 to this bit select function set 2.
- All input channel share 1 data register
- Generate interrupt after each channel finished conversion
- Data protection when interrupt request enabled
Note:
Only rewrite this bit before conversion begins, with A/D operation stopped
• This bit is used to start the A/D conversion operation by the software.
• Write "1" to this bit to activate A/D conversion.
bit9
START:
A/D conversion
start bit
• Restart by this bit cannot be used at the stop conversion mode.
• "0" is always read during read modify write (RMW) instruction.
Note:
Do not perform a forced stop and software activation (BUSY = 0, START = 1) at
the same time.
bit8
Undefined bit
CM71-10155-2E
• The read value is undefined.
• Writing to this bit has no effect to operation.
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CHAPTER 15 8/10-BIT A/D CONVERTER
15.4 Registers of the 8/10-bit A/D Converter
15.4.4
MB91490 Series
A/D Data Register (ADCD)
The A/D data register stores A/D conversion results.
■ A/D Data Register
(ADCD: ADCD001 to ADCD031, ADCD002 to ADCD072)
Address
000518H to 00051EH
000178H to 000186 H
bit14
bit13
bit12
-
-
bit11
-
bit10
ERRST
-
D9
D8
R
R
-
-
-
-
R
R
bit5
552
: Read only
: Undefined bit
: Initial value
bit6
bit1
bit0
D6
D5
D4
D3
D2
D1
D0
R
R
R
R
R
R
R
R
ERR
0
1
bit3
10-- --XX XXXX XXXXB
D7
ERRST
0
1
bit4
bit8
bit7
D9 to D0
R
-
bit9
Initial value
bit15
ERR
bit2
A/D data bits
Conversion data
Conversion data error status bit (at ERR=1 only)
Conversion data is not update.
Conversion data is update.
Conversion data error flag bit
The overwriting of the conversion data has not been generated.
The overwriting of the conversion data has been generated.
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
CHAPTER 15 8/10-BIT A/D CONVERTER
15.4 Registers of the 8/10-bit A/D Converter
MB91490 Series
Table 15.4-4 Function of Each Bit in A/D Data Register (ADCD)
Bit Name
Function
• When this bit is "1", the content of the error can be known by the value of the ERRST
bit in the bit that shows that there was an error in the A/D conversion data.
bit15
ERR:
Conversion data
error flag bit
• This bit is set to "1" when reading it.
• When a new conversion result is written in this register, it is cleared to "0".
Note:
• When conversion data protection function is used FuncSet = 1 and INTE = 1, this bit
is always "0".
• It is a flag that shows the content of the error of the A/D conversion data at ERR bit =
1.
• It is shown that the conversion result by CPU reading is old at ERR bit = 1 and this bit
= 0.
bit14
ERRST:
Conversion data
error status bit
• The conversion result by CPU reading shoes that the old conversion data was lost
from the overwriting of a new conversion result without completing reading the old
conversion result with CPU at ERR bit = 1 and this bit = 1.
• When the old conversion data is lost from the overwriting of a new conversion result
without completing reading the old conversion result with CPU, it is set in "1".
• This bit is cleared to "0" when reading it.
Note:
When conversion data protection function is used (FuncSet = 1 and INTE = 1), this bit
is always "0".
bit13
to
bit10
• The read value is undefined.
Undefined bits
• Writing to these bits has no effect to operation.
• The result of the A/D conversion is stored, and the register is rewritten at each
conversion end.
• The final conversion value is stored usually.
bit9
to
bit0
D9 to D0:
A/D data bits
• The initial value of this register is undefined.
Notes:
• The conversion data protection function is provided.
• Do not write data to these bits while A/D conversion is ongoing.
• When 8-bit resolution is selected, bit8 & bit9 read 0.
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CHAPTER 15 8/10-BIT A/D CONVERTER
15.4 Registers of the 8/10-bit A/D Converter
15.4.5
MB91490 Series
Analog Input Control Register (AICR)
The analog input control register controls analog input.
■ Analog Input Control Register (AICR: AICR1, AICR2)
Address
bit7
bit6
bit5
bit4
bit3
bit2
-
-
-
-
AN3E
AN2E
-
-
-
-
R/W
R/W
000511H
bit1
bit0
Initial value
AN1E
AN0E
---- 1111B
R/W
R/W
Analog input enable bits
Analog input disable
Analog input enable
AN3E to AN0E
0
1
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
000170H
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
AN7E
AN6E
AN5E
AN4E
AN3E
AN2E
AN1E
AN0E
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
AN7E to AN0E
R/W
-
0
1
: Readable/Writable
: Undefined bit
: Initial value
Initial value
---- ---- 1111 1111B
Analog input enable bits
Analog input disable
Analog input enable
Table 15.4-5 Functions of Each Bit in Analog Input Control Register (AICR)
Bit Name
(AICR1)
bit7 to bit4
(AICR2)
bit15 to bit8
(AICR1)
bit3 to bit0
(AICR2)
bit7 to bit0
554
Function
• The read value is undefined.
Undefined bits
• Writing to these bits has no effect to operation.
• When these bits are "0", analog input is disabled.
AN3E to AN0E,
AN7E to AN0E,
Analog input enable bits
• When these bits are "1", analog input is enabled.
• Set the AICR register bit corresponding to the pin to be used as the
analog input pin to "1". When this is done, the value "0" will be read
from the PDR register.
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
CHAPTER 15 8/10-BIT A/D CONVERTER
15.5 Interrupt of the 8/10-bit A/D Converter
MB91490 Series
15.5
Interrupt of the 8/10-bit A/D Converter
The 8/10-bit A/D converter can generate interrupt requests during A/D conversion by
setting data in the A/D data register.
■ Interrupt of 8/10-bit A/D Converter
See Table 15.5-1 for the interrupt control bits and interrupt cause of the 8/10-bit A/D converter.
Table 15.5-1 Interrupt Control Bits and Interrupt Cause of 8/10-bit A/D Converter
8/10-bit A/D converter
Interrupt request flag bit
ADCS: INT
A/D conversion function
selection bit
ADCS: FuncSet
Interrupt request enable bit
ADCS: INTE
Interrupt cause
Writing of A/D conversion result to A/D data register
When FuncSet = 0, interrupt could be generated after all selected channel conversion completed. The INT
bit of the A/D control status register (ADCS) is set to "1" when all the conversion end and A/D conversion
results are set in the A/D data register (ADCD). At this time, an interrupt request is generated to the
interrupt controller if interrupt request is enabled (ADCS:INTE=1).
When FuncSet = 1, interrupt could be generated after each channel conversion completed. The INT bit of
the A/D control status register (ADCS) is set to "1" when each conversion ends and A/D conversion results
are set in the A/D data register (ADCD). At this time, an interrupt request is generated to the interrupt
controller if interrupt request is enabled (ADCS:INTE=1).
CM71-10155-2E
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CHAPTER 15 8/10-BIT A/D CONVERTER
15.6 Operation Explanation of the 8/10-bit A/D Converter
MB91490 Series
Operation Explanation of the 8/10-bit A/D Converter
15.6
Three mode types, the single conversion, continuous conversion, and stop conversion
modes are available for the 8/10-bit A/D converter. The operation explanation in each
mode is done.
■ Operation of Single Conversion Mode
In single conversion mode, it sequentially converts the analog input which has been set by the ANS bit and
ANE bit, and when it reaches to the end channel set in ANE bit, it stops the A/D conversion. If the start
channel and end channel are the same (ANS=ANE), only one channel specified in the ANS bit will be
converted. The settings in Figure 15.6-1 are required in order to operate in single-conversion mode.
Figure 15.6-1 Setting for Single Conversion Mode
bit15 bit14 bit13 bit12 bit11 bit10 bit9
ADCH/
ADMD
AICR
-
-
ANS2 ANS1 ANS0
✧
✧
✧
-
-
-
-
-
bit8
bit7
ADCS
ERR
ERRST
✧
✧
0
-
-
BUSY INT INTE PAUS S10
✧
✧
◆
-
✧
✧
✧
✧
bit5
bit4
bit3
bit2
bit1
bit0
ANE2 ANE1 ANE0 MD1 MD0 STS1 STS0 CT1 CT0 ST1 ST0
✧
✧
✧
-
-
-
0
✧
✧
✧
✧
✧
✧
✧
AN7E AN6E AN5E AN4E AN3E AN2E AN1E AN0E
◆
ADCD
bit6
-
◆
◆
◆
◆
◆
◆
◆
Store the converting data
Func
START
Set
✧
✧
: Used bit
: Set "1" to the corresponding bit in using pin
: Set "0"
Reference:
The example of conversion order in single conversion mode is shown in following.
When ANS=000B, ANE=011B: AN0 
AN2 
AN3 
end
(FuncSet =0) ADCD00 
ADCD01 
ADCD02 
ADCD03 
end
(FuncSet =1) ADCD00 
ADCD00 
ADCD00 
ADCD00 
end
When ANS=011B, ANE=011B: AN3 
556
AN1 
end
(FuncSet = 0) ADCD03 
end
(FuncSet = 1) ADCD03 
end
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
CHAPTER 15 8/10-BIT A/D CONVERTER
15.6 Operation Explanation of the 8/10-bit A/D Converter
MB91490 Series
Note:
When A/D conversion mode selection bits (MD1, MD0) are set to "00B", it is possible to reactivate in
the A/D conversion. Only software activating (STS1, STS0=00B) can be set in this mode. Reactivate
according to the following procedure.
1. Clear the INT bit to "0".
2. Write "1" to the START bit and write "0" to the INT bit at the same time.
■ Operation of Continuous Conversion Mode
In the continuous conversion mode, the analog inputs set by the ANS and ANE bits are sequentially
converted, the analog input set by the ANS bit is resumed at the end of conversion of the end channel set by
the ANE bit, and the A/D conversion operation is continued. If the start channel and end channel are
identical (ANS=ANE), conversion loops on the channel specified by ANS only. The settings shown in
Figure 15.6-2 are required in order to operate in continuous conversion mode.
Figure 15.6-2 Setting at Continuous Conversion Mode
bit15 bit14 bit13 bit12 bit11 bit10 bit9
ADCH/
ADMD
AICR
-
-
ANS2 ANS1 ANS0
✧
✧
✧
-
-
-
-
-
bit8
bit7
ADCS
ERR
ERRST
✧
✧
0
1
-
-
BUSY INT INTE PAUS S10
✧
✧
◆
-
✧
✧
✧
✧
bit5
bit4
bit3
bit2
bit1
bit0
ANE2 ANE1 ANE0 MD1 MD0 STS1 STS0 CT1 CT0 ST1 ST0
✧
✧
✧
-
-
-
1
-
0
✧
✧
✧
✧
✧
✧
AN7E AN6E AN5E AN4E AN3E AN2E AN1E AN0E
◆
ADCD
bit6
◆
◆
◆
◆
◆
◆
◆
Store the converting data
Func
START
Set
✧
✧
: Used bit
: Set "1" to the corresponding bit in using pin
: Set "0"
: Set "1"
Reference:
The example of conversion order in continuous conversion mode is shown in following.
When ANS=000B, ANE=011B: AN0  AN1 
(FuncSet =0) ADCD00 
(FuncSet =1) ADCD00 
When ANS=011B, ANE=011B: AN3  AN3 
(FuncSet =0) ADCD03 
ADCD07 
(FuncSet =1) ADCD00 
CM71-10155-2E
AN2  AN3  Repeat
ADCD01  ADCD02  ADCD03  Repeat
ADCD00  ADCD00  ADCD00  Repeat
AN3  AN3  Repeat
ADCD04  ADCD05  ADCD06 
ADCD00  ADCD01  ADCD02  Repeat
ADCD00  ADCD00  ADCD00  Repeat
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CHAPTER 15 8/10-BIT A/D CONVERTER
15.6 Operation Explanation of the 8/10-bit A/D Converter
MB91490 Series
■ Operation of Pause-Conversion Mode
In the stop conversion mode, the analog input set by the ANS and ANE bits is converted by being
suspended for every channel, the analog input set by the ANS bit is resumed at the end of conversion of the
end channel set by the ANE bit, and the operation of A/D conversion and suspension is continued. If the
start channel and end channel are identical (ANS=ANE), conversion loops on the channel specified by the
ANS bits only. When the conversion is restarted during the suspension, the start factor specified by the
STS1 and STS0 bits is generated. The settings in Figure 15.6-3 are required in order to operate in stop
conversion mode.
Figure 15.6-3 Setting at Pause-conversion Mode
bit15 bit14 bit13 bit12 bit11 bit10 bit9
ADCH/
ADMD
AICR
-
-
ANS2 ANS1 ANS0
✧
✧
✧
-
-
-
-
-
bit8
bit7
ADCS
ERR
ERRST
✧
✧
1
-
-
BUSY INT INTE PAUS S10
✧
✧
◆
-
✧
✧
✧
✧
bit5
bit4
bit3
bit2
bit1
bit0
ANE2 ANE1 ANE0 MD1 MD0 STS1 STS0 CT1 CT0 ST1 ST0
✧
✧
✧
-
-
-
1
-
1
✧
✧
✧
✧
✧
✧
AN7E AN6E AN5E AN4E AN3E AN2E AN1E AN0E
◆
ADCD
bit6
◆
◆
◆
◆
◆
◆
◆
Store the converting data
Func
START
Set
✧
✧
: Used bit
: Set "1" to the corresponding bit in using pin
: Set "1"
Reference:
The example of conversion order in stop conversion mode is shown in following.
• When ANS=000B, ANE=011B:
AN0  Pause  AN1  Pause  AN2  Pause  AN3  Repeat
FuncSet =0
ADCD00  Pause  ADCD01  Pause  ADCD02  Pause 
Repeat
FuncSet =1
ADCD00  Pause  ADCD00  Pause  ADCD00  Pause 
Repeat
• When ANS=011B, ANE=011B:
AN3  Pause  AN3  Pause  AN3  Pause  AN3  Repeat
FuncSet =0
ADCD03  Pause  ADCD04  Pause  ADCD05  Pause 
Pause
ADCD07 Pause  ADCD00  Pause  ADCD01  Pause 
Repeat
FuncSet =1
ADCD00  Pause  ADCD00  Pause  ADCD00  Pause 
Repeat
558
FUJITSU SEMICONDUCTOR LIMITED
ADCD03 
ADCD00 
ADCD06 
ADCD02 
ADCD00 
CM71-10155-2E
CHAPTER 15 8/10-BIT A/D CONVERTER
15.7 A/D Conversion Data Protection Function of the 8/10-bit A/D Converter
MB91490 Series
15.7
A/D Conversion Data Protection Function of the 8/10-bit
A/D Converter
When the A/D conversion operates in the interrupt enabled state, the conversion data
protection function works.
■ A/D Conversion Data Protection Function
When selected ADCS: FuncSet = 1 (conversion function 2), there is only 1 data register for storing
conversion result. For this reason, when performing A/D conversion, the data stored in data register is
rewritten after conversion is completed. Therefore, part of previous data may be lost when the converted
data transfer to memory is delayed. To get around this, when interrupt is enabled (ADCS:INTE=1), data
protection feature works as described below.
When conversion data is stored in the A/D data register (ADCD), the ADCS:INT bit set to "1". While the
ADCS:INT bit is "1", conversion data will not be stored to ADCD after the next conversion ends. The
ADCS:PAUS bit is set and A/D conversion becomes suspended. While suspended, the value immediately
prior is retained. In order to cancel the suspend, clear ADCS:INT bit. After the suspended status is cleared,
the conversion data that had been maintained is stored in ADCD and the next operation is performed.
Figure 15.7-1 Setting to Use Data Protection Function
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7
ADCH/
ADMD
-
AICR
-
ADCD
ERR
ANS2 ANS1 ANS0
-
ERRST
-
-
-
-
-
-
-
-
-
ADCS BUSY INT INTE PAUS S10
1
ANE2 ANE1 ANE0
-
-
MD1
bit6
bit5 bit4
bit3 bit2
MD0 STS1 STS0 CT1
CT0
AN7E AN6E AN5E AN4E AN3E AN2E
bit1 bit0
ST1
ST0
AN1E AN0E
Store the converting data
Func START
Set
1
: Used bit
: Set "1" to the corresponding bit in using pin.
1 : Set "1".
Notes:
• Conversion data protection function only operates in conversion function 2 (ADCS:FuncSet=1)
and interrupt enabled (ADCS:INTE=1)
• When the conversion is restarted during suspension, the waiting data is destroyed.
CM71-10155-2E
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CHAPTER 15 8/10-BIT A/D CONVERTER
15.8 Using Memorandum of the 8/10-bit A/D Converter
15.8
MB91490 Series
Using Memorandum of the 8/10-bit A/D Converter
This section is a memorandum when 8/10-bit A/D converter is used.
■ ADMD Register Setting
The A/D converter sampling time and compare time based on three types of frequencies (25MHz, 33MHz,
40MHz) can be set by the ADMD register. The minimum conversion time corresponding to each frequency
can be set. Set ADMD by the following two methods when a set frequency is different from three abovementioned types of values.
• ST[1:0]/CT[1:0] bit (bit3, bit2/bit1, bit0) of the ADMD register is set so that neither the time of the
sample nor the compare time may become below recommended value of 8/10-bit A/D converter.
• Set P3-to-P0 bit of DIVR0 register (bit3-to-bit0) so that the frequency of the peripheral clock (CLKP)
may become one of the above-mentioned.
● Example:
• When the peripheral clock (CLKP) frequency is 16MHz: Method 1
Cycle: 62.5ns
Sample time:
ST[1:0] =00B
 10 peripheral clock (CLKP) cycles
 10  62.5ns = 625ns > 390ns (Minimum value)
Compare time:
CT[1:0] =00B
 18 peripheral clock (CLKP) cycles
 18  62.5ns = 1125ns > 720ns(Minimum value)
.
. . Total conversion time = 1750ns
• When the peripheral clock (CLKP) frequency is 16MHz: Method 2
Source oscillation frequency: 10MHz
PLL multiplication rate:  5-multiplication
DIVR0: P3 to P0 =0001B
 CLKP = 10  5 / 2 = 25MHz
ST[1:0] = 00B, CT[1:0] =00B
. .. Total conversion time = 1120ns
560
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
CHAPTER 15 8/10-BIT A/D CONVERTER
15.9 Notes on Using the 8/10-bit A/D Converter
MB91490 Series
15.9
Notes on Using the 8/10-bit A/D Converter
This section describes notes on using 8/10-bit A/D converter.
■ Notes on Using 8/10-bit A/D Converter
● Analog input pin
The A/D input pin does double duty as a port I/O pin. The port-direction register (DDR) and analog input
enable register (AICR) are switched and used. For the pins used as analog input, set the bits corresponding
to DDR to 0 and port to input, then set AICR register analog input mode (AICR x = 1). Lock the input gate
on the port side. When the intermediate level signal is inputted in the port input mode (AICRx = 0), the
input leak current flows through the gate.
● Cautions for use of internal timers
To activate the A/D converter by an internal timer, set the STS1 and STS0 bits of the A/D control status
register (ADMD). When doing so, set the internal timer input value to the inactive side (for internal timer,
this is "L"). If you set it to the active side, the timer may start to operate as soon as you write to the ADMD
register.
● Turning-on sequence of power supply to A/D converter and analog inputs
Make sure to apply to the A/D converter power source (AVCC10, AVRH2, and AVSS10) and apply analog
input (AN1-0 to AN1-3, AN2-0 to AN2-7) after or at the same time as applying digital power source
(VCC). When cutting off the power, cut off the digital power source (VCC) after or at the same time as
cutting off the A/D converter power source and analog input.
● Power voltage of A/D converter
In order to prevent latch-ups, make sure that the A/D converter power source (AVCC10) does not exceed
the voltage of the digital power source (VCC).
● Setting of ADCH register
Set to become ANS  ANE.
Rewrite the bit with the A/D operation before conversion operates without fail has stopped.
Be sure to set "0" to the ANS2, ANE2 bits of the ADCH1 register.
● Setting of ADMD register
Set ST[1:0]/CT[1:0] bit (bit3, bit2/bit1 bit0) so that neither the time of the sample nor the compare time
may become below recommended value of 8/10-bit A/D converter.
Rewrite the bit with the A/D operation before conversion operates without fail has stopped.
Refer to "15.8 Using Memorandum of the 8/10-bit A/D Converter" for a detailed explanation.
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CHAPTER 15 8/10-BIT A/D CONVERTER
15.9 Notes on Using the 8/10-bit A/D Converter
MB91490 Series
● Setting of ADCS register
Rewrite the bit with the A/D operation before conversion operates without fail has stopped.
Do neither A/D conversion starting setting (START=1) with software nor stop setting (BUSY=1) at the
same time.
Refer to Section "15.4 Registers of the 8/10-bit A/D Converter" for a detailed explanation.
● Notice in A/D conversion data protection function
Conversion data protection function is only available in conversion function 2 (ADCS:FuncSet=1) and
interrupt enabled (ADCS:INTE=1).
● Flag bit in A/D data register
Even if lower 8 bits of the A/D data register are read by byte access, neither the ERRST nor ERR bits are
changed.
Moreover, when the conversion data protection function is used, the ERRST and ERR bits are always "0".
● External trigger terminal
Return the input level of the external trigger terminal to former level by the external trigger terminal after
the activating of the A/D converter.
● Reactivation of the A/D conversion
When A/D conversion mode selection bits (MD1, MD0) are set to "00B", it is possible to reactivate in the
A/D conversion. Only software activating (STS1, STS0=00B) can be set in this mode. Reactivate according
to the following procedure.
1. Clear the INT bit to "0".
2. Write "1" to the START bit and write "0" to the INT bit at the same time.
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CHAPTER 16
DMA CONTROLLER (DMAC)
This chapter describes the DMAC, the configuration and
functions of registers, and DMAC operation.
16.1 Overview of the DMAC
16.2 Detailed Explanation of the DMAC Registers
16.3 Explanation of the DMAC Operation
16.4 Operation Flowcharts of the DMAC
16.5 Data Bus of the DMAC
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CHAPTER 16 DMA CONTROLLER (DMAC)
16.1 Overview of the DMAC
16.1
MB91490 Series
Overview of the DMAC
This module implements DMA (Direct Memory Access) transfer on FR family devices.
When this module is used to control DMA transfer, various data transfer operations can
be executed at high speed by bypassing the CPU, enhancing system performance.
■
Hardware Configuration of the DMAC
This module mainly consists of the following blocks:
■
•
Five independent DMA channels
•
5 channel independent access control circuit
•
32-bit address registers (reload specifiable, two registers for each channel)
•
16-bit transfer count register (reload specifiable, one register for each channel)
•
4-bit block count register (one for each channel)
•
2-cycle transfer
Main DMAC Functions
Data transfer using this module mainly consists of the following functions:
● Data can be transferred independently over multiple channels (5 channels)
•
Priority (ch.0ch.1ch.2ch.3 ch.4)
•
The priority can be rotated between ch.0 and ch.1.
•
DMAC start sources
- Built-in peripheral requests (shared interrupt requests, including external interrupts)
- Software request (register write)
•
Transfer mode
- Burst transfer, step transfer, and block transfer
- Addressing mode: 32-bit full addressing (increment/decrement/fixed)
(The address increment/decrement range is from -255 to + 255.)
- Data types: Byte, halfword, and word length
- Single shot/reload selectable
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16.1 Overview of the DMAC
MB91490 Series
■
Register List of the DMAC Registers
Figure 16.1-1 provides an register list of the DMAC.
Figure 16.1-1 Register List of the DMAC
bit 31
ch.0 control/status register A
DMACA0 00000200H
ch.0 control/status register B
DMACB0 00000204H
ch.1 control/status register A
DMACA1 00000208H
ch.1 control/status register B
DMACB1 0000020CH
ch.2 control/status register A
DMACA2 00000210H
ch.2 control/status register B
DMACB2 00000214H
ch.3 control/status register A
DMACA3 00000218H
ch.3 control/status register B
DMACB3 0000021CH
ch.4 control/status register A
DMACA4 00000220H
ch.4 control/status register B
DMACB4 00000224H
All-channel control register
DMACR
ch.0 transfer source address setting register
DMASA0 00001000H
ch.0 transfer destination address setting register
DMADA0 00001004H
ch.1 transfer source address setting register
DMASA1 00001008H
ch.1 transfer destination address setting register
DMADA1 0000100CH
ch.2 transfer source address setting register
DMASA2 00001010H
ch.2 transfer destination address setting register
DMADA2 00001014H
ch.3 transfer source address setting register
DMASA3 00001018H
ch.3 transfer destination address setting register
DMADA3 0000101CH
ch.4 transfer source address setting register
DMASA4 00001020H
ch.4 transfer destination address setting register
DMADA4 00001024H
CM71-10155-2E
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00000240H
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16.1 Overview of the DMAC
■
MB91490 Series
Block Diagram of DMAC
Figure 16.1-2 is a block diagram of DMAC.
Figure 16.1-2 Block Diagram of DMAC
Counter
Selector
Write back
Buffer
DMA transfer request to
the bus controller
DTC 2-stage register DTCR
DMA activation
source
selection circuit
& request
acceptance
control
Peripheral activation request/stop input
Counter
DSS[2:0]
DDNO
Bus control unit
Selector
Counter buffer
IRQ[4:0]
Peripheral interrupt clear
MCLREQ
TYPE.MOD,WS
DDNO register
DSAD 2-stage register
SADM,SASZ[7:0] SADR
Write back
Selector
address
Counter buffer
Access
566
State
transition
circuit
DMA control
Address counter
To bus
controller
BLK register
To interrupt controller
Bus control unit
Write
ERIE,EDIR
Selector
Read/write
control
Selector
Read
Priority circuit
X-bus
Buffer
DDAD 2-stage register
DADM,DASZ[7:0] DADR
Write back
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CHAPTER 16 DMA CONTROLLER (DMAC)
16.2 Detailed Explanation of the DMAC Registers
MB91490 Series
16.2
Detailed Explanation of the DMAC Registers
This section describes the DMAC registers in detail.
■
Notes on Setting Registers
When the DMA controller (DMAC) is set, some bits need to be set while DMA is stopped. If they are set
while DMA is in progress (during transfer), correct operation cannot be guaranteed.
" * " marks indicates that the bit affects operation if it is set during DMAC transfer. Rewrite this bit while
DMAC transfer is stopped (start is disabled or temporarily stopped).
The setting of this bit that is made while DMA transfer start is disabled (when the DMACR:DMAE=0 or
the DMACA:DENB=0) becomes effective when DMA transfer start is enabled.
The setting of this bit that is made while DMA transfer is temporarily stopped (when the DMAH3 to
DMAH0 bits of DMACR are not 0000B or the PAUS bit of DMACA is "1") becomes effective when
temporary stop is canceled.
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CHAPTER 16 DMA CONTROLLER (DMAC)
16.2 Detailed Explanation of the DMAC Registers
16.2.1
MB91490 Series
DMAC ch.0,ch.1,ch.2,ch.3,ch.4 Control/Status Registers A
The [DMACA0 to DMACA4] registers control the operation of the DMAC channels.
A separate register is provided for each channel.
■
Functions of the [DMACA0 to DMACA4] Bits
The functions of the [DMACA0 to DMACA4] bits are shown below:
Figure 16.2-1 DMAC Control/Status Register A
Address
bit31 bit30 bit29 bit28 bit27 bit26 bit25 bit24 bit23 bit22 bit21 bit20 bit19 bit18 bit17 bit16
ch.0: 000200H DENB PAUS STRG
IS [4 : 0]
ch.1: 000208H R/W R/W R/W
R/W
ch.2: 000210H
ch.3: 000218H
ch.4: 000220H bit15 bit14 bit13 bit12 bit11 bit10 bit9
bit8
bit7
-
BLK [3 : 0]
R/W
R/W
bit6
bit5
bit4
bit3
bit2
bit1
bit0
DTC [15 : 0]
R/W
(Initial value: 00000000----XXXXXXXXXXXXXXXXXXXXB)
R/W: Readable/writable
[bit31] DENB (Dma ENaBle): DMA operation enable bit
This bit, which corresponds to a transfer channel, is used to enable and disable DMA transfer.
The activated channel starts DMA transfer when a transfer request is generated and accepted.
All transfer requests that are generated for a deactivated channel are disabled.
When the transfer on an activated channel reaches the specified count, this bit is set to "0" and transfer
stops.
The transfer can be forced to stop by writing "0" to this bit. Be sure to stop a transfer forcibly ("0"
write) only after temporarily stopping DMA using the PAUS bit [bit30 of DMACA]. If the transfer is
forced to stop without first temporarily stopping DMA, DMA stops but the transferred data cannot be
guaranteed. Check whether DMA is stopped using the DSS[2:0] bits [bit18 to bit16 of DMACB].
DENB
Function
0
Disables operation of DMA on the corresponding channel (initial value).
1
Enables operation of DMA on the corresponding channel.
•
If a stop request is accepted during reset: Initialized to "0".
•
This bit is readable and writable.
If the operation of all channels is disabled by bit31 (DMAE bit) of the DMAC all-channel control register
(DMACR), writing "1" to this bit is disabled and the stopped state is maintained. If the operation is disabled
by the bit31 (DMAE bit) while it is enabled by this bit, "0" is written to this bit and the transfer is stopped
(forced stop).
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CHAPTER 16 DMA CONTROLLER (DMAC)
16.2 Detailed Explanation of the DMAC Registers
MB91490 Series
[bit30] PAUS (PAUSe): Temporary stop instruction
This bit temporarily stops DMA transfer on the corresponding channel. If this bit is set, DMA transfer is
not performed before this bit is cleared (While DMA is stopped, the DSS bits are 1XXB).
If this bit is set before starting, DMA transfer continues to be temporarily stopped.
New transfer requests that occur while this bit is set are accepted, but no transfer starts before this bit is
cleared (See Section "16.3.10 Transfer Request Acceptance and Transfer").
PAUS
Function
0
Enables DMA operation of the corresponding channel (initial value)
1
Temporarily stops DMA on the corresponding channel.
•
When reset: Initialized to "0".
•
This bit is readable and writable.
[bit29] STRG (Software TRiGger): Transfer request
This bit generates a DMA transfer request for the corresponding channel. If "1" is written to this bit, a
transfer request is generated when write operation to the register is completed and transfer on the
corresponding channel is started. However, if the corresponding channel is not activated, operations on
this bit are disabled.
Reference:
If starting by a write operation to the DMAE bit and a transfer request occurring due to this bit are
simultaneous, the transfer request is enabled and transfer is started. If writing of "1" to the PAUS bit
and a transfer request occurring due to this bit are simultaneous, the transfer request is enabled, but
DMA transfer is not started before "0" is written to the PAUS bit.
STRG
Function
0
Disabled
1
DMA starting request
• When reset: Initialized to "0".
• The read value is always "0".
• Only a write value of "1" is valid. If "0" is written, operation is not affected.
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16.2 Detailed Explanation of the DMAC Registers
MB91490 Series
[bit28 to bit24] IS4 to IS0 (Input Select)*: Transfer Source Selection
These bits select the source of the transfer request as listed in the table below. Note that the software
transfer request by the STRG bit function is always valid regardless of the settings of these bits.
IS
Function
00000B
Only the software transfer request
00001B

01111B
Setting disabled

Setting disabled
10000B
Multi-function serial interface0 (receiving complete)
10001B
Multi-function serial interface1 (receiving complete)
10010B
Multi-function serial interface2 (receiving complete)
10011B
Multi-function serial interface0 (sending complete)
10100B
Multi-function serial interface1 (sending complete)
10101B
Multi-function serial interface2 (sending complete)
10110B
External interrupt 0
10111B
External interrupt 1
11000B
8/10-bit AD2
11001B
Setting disabled
11010B
8/10-bit AD1
11011B
Setting disabled
11100B
PPG0
11101B
PPG4
11110B
Setting disabled
11111B
Base timer 0 (Source 0)
•
When reset: Initialized to 00000B.
•
These bits are readable and writable.
Transfer stop request
No
Yes
No
If DMA start resulting from an interrupt from a peripheral function is set (IS=1XXXXB), disable interrupts
from the selected peripheral function with the ICR register.
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CHAPTER 16 DMA CONTROLLER (DMAC)
16.2 Detailed Explanation of the DMAC Registers
MB91490 Series
[bit23 to bit20] Reserved: Reserved bits
Be sure to set "0000B".
[bit19 to bit16] BLK3 to BLK0 (BLocK size): Block size specification
These bits specify the block size for block transfer on the corresponding channel. The value specified
by these bits becomes the number of words in one transfer unit (more exactly, the repetition count of the
data width setting). If block transfer will not be performed, set "01H" (size 1). (This register value is
ignored during demand transfer. The size becomes "1".)
BLK
XXXXB
Function
Block size of the corresponding channel
•
When reset: Not initialized.
•
These bits are readable and writable.
•
If "0" is specified for all bits, the block size becomes 16 words.
During reading, the block size is always read (reload value).
[bit15 to bit0] DTC15 to DTC0 (Dma Terminal Count register)*: Transfer count register
These bits compose a register for storing the transfer count. Each register has 16-bit length.
All registers have a dedicated reload register. When the register is used for a channel that is enabled to
reload the transfer count register, the initial value is automatically written back to the register when the
transfer is completed.
DTC
XXXXH
Function
Transfer count for the corresponding channel
When DMA transfer is started, data in this register is stored in the counter buffer of the DMA-dedicated
transfer count counter and is decremented by "1" (subtraction) after each transfer unit. When DMA transfer
is completed, the contents of the counter buffer are written back to this register and then DMA ends. Thus,
the transfer count value during DMA operation cannot be read.
•
When reset: Not initialized.
•
These bits are readable and writable. Always access DTC using halfword length or word length.
•
During reading, the count value is read. The reload value cannot be read.
•
When reset: Not initialized.
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CHAPTER 16 DMA CONTROLLER (DMAC)
16.2 Detailed Explanation of the DMAC Registers
16.2.2
MB91490 Series
DMAC ch.1,ch.2,ch.3,ch.4 Control/Status Registers B
The DMACB0 to DMACB4 registers control the operation of the DMAC channels.
A separate register is provided for each channel.
■
Functions of the DMACB0 to DMACB4 Bits
The functions of the [DMACB0 to DMACB4] are shown below:
Figure 16.2-2 DMAC Control/Status Register B
Address
bit31 bit30 bit29 bit28 bit27 bit26 bit25 bit24 bit23 bit22 bit21 bit20 bit19 bit18 bit17 bit16
ch.0: 000204H TYPE [1 : 0] MOD [1 : 0]
WS [1 : 0] SADM DADM DTCR SADR DADR
ch.1: 00020CH
R/W
R/W
R/W
R/W R/W R/W R/W R/W
ch.2: 000214H
ch.3: 00021CH
ch.4: 000224H bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5
SASZ [7 : 0]
R/W
ERIE EDIE
DSS[2 : 0]
R/W R/W
R/W
bit4
bit3
bit2
bit1
bit0
DASZ [7 : 0]
R/W
(Initial value: 0000000000000000XXXXXXXXXXXXXXXXB)
R/W: Readable/writable
[bit31, bit30] TYPE1, TYPE0 (TYPE)*: Transfer type setting
These bits specify the operation type of the corresponding channel as described below.
2-cycle transfer mode:
In this mode, the transfer source address (DMASA) and transfer destination address (DMADA) are set
and transfer is performed by repeating the read operation and write operation for the number of times
specified by the transfer count. All areas can be specified as a transfer source or transfer destination (32bit address).
TYPE
572
Function
00B
2-cycle transfer (initial value)
01B
Setting disabled
10B
Setting disabled
11B
Setting disabled
•
When reset: Initialized to "00".
•
These bits are readable and writable.
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CHAPTER 16 DMA CONTROLLER (DMAC)
16.2 Detailed Explanation of the DMAC Registers
MB91490 Series
[bit29, bit28] MOD0, MOD1 (MODe)*: Transfer mode setting
These bits set the operating mode of the corresponding channel as listed in the table below:
MOD
Function
00B
Block/step transfer mode (initial value)
01B
Burst transfer mode
10B
Setting disabled
11B
Setting disabled
•
When reset: Initialized to "00".
•
These bits are readable and writable.
[bit27, bit26] WS1, WS0 (Word Size): Transfer data width selection
These bits are used to select the transfer data width of the corresponding channel. Transfer operations
are repeated in units of the data width specified in this register for as many times as the specified count.
WS
Function
00B
Byte-width transfer (initial value)
01B
Halfword-width transfer
10B
Word-width transfer
11B
Setting disabled
•
When reset: Initialized to "00".
•
These bits are readable and writable.
[bit25] SADM (Source-ADdr. Count-Mode select)*: Transfer source address count mode
specification
This bit specifies the address processing of the transfer source address of the corresponding channel for
each transfer operation.
An address increment is added or an address decrement is subtracted after each transfer operation
according to the specified transfer source address count width (SASZ). When the transfer is completed,
the next access address is written to the corresponding address register (DMASA). As a result, the
transfer source address register is not updated until DMA transfer is completed.
To make the address always the same, specify "0" or "1" for this bit and set the address count width
(SASZ and DASZ) to "0".
SADM
Function
0
Increments the transfer source address. (initial value)
1
Decrements the transfer source address.
•
When reset: Initialized to "0".
•
This bit is readable and writable.
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16.2 Detailed Explanation of the DMAC Registers
MB91490 Series
[bit24] DADM (Destination-ADdr. Count-Mode select)*:Transfer destination address count mode
specification
This bit specifies the address processing for the transfer destination address of the corresponding
channel in each transfer operation.
An address increment is added or an address decrement is subtracted after each transfer operation
according to the specified transfer destination address count width (DASZ). When the transfer is
completed, the next access address is written to the corresponding address register (DMADA). As a
result, the transfer destination address register is not updated until the DMA transfer is completed.
To make the address always the same, specify "0" or "1" for this bit and set the address count width
(SASZ and DASZ) to "0".
DADM
Function
0
Increments the transfer destination address. (initial value)
1
Decrements the transfer destination address.
•
When reset: Initialized to "0".
•
This bit is readable and writable.
[bit23] DTCR (DTC-reg. Reload)*: Transfer count register reload specification
This bit controls reloading of the transfer count register for the corresponding channel.
If reloading of the counter is enabled by this bit, the count register value is restored to its initial value
after transfer is completed, then DMAC stops and starts waiting for a new transfer request (an activation
request by STRG or IS setting). (If this bit is "1", the DENB bit is not cleared.)
DENB=0 or DMAE=0 must be set to stop the transfer. In either case, the transfer is forcibly stopped.
If reloading of the counter is disabled, a single shot operation occurs. In single shot operation, operation
stops after the transfer is completed even if reload is specified in the address register. The DENB bit is
also cleared in this case.
DTCR
574
Function
0
Disables transfer count register reloading (initial value)
1
Enables transfer count register reloading.
•
When reset: Initialized to "0".
•
This bit is readable and writable.
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CHAPTER 16 DMA CONTROLLER (DMAC)
16.2 Detailed Explanation of the DMAC Registers
MB91490 Series
[bit22] SADR (Source-ADdr.-reg. Reload)*: Transfer source address register reload specification
This bit controls reloading of the transfer source address register for the corresponding channel.
If this bit enables the reload operation, the transfer source address register value is restored to its initial
value after the transfer is completed.
If reloading of the counter is disabled, a single shot operation occurs. In single shot operation, operation
stops after the transfer is completed even if reload is specified in the address register. The address
register value also stops in this case while the initial value is being reloaded.
If this bit disables the reload operation, the address register value when the transfer is completed is the
address to be accessed next to the final address. (When address increment is specified, the next address
is an incremented address.)
SADR
Function
0
Disables transfer source address register reloading. (initial value)
1
Enables transfer source address register reloading.
•
When reset: Initialized to "0".
•
This bit is readable and writable.
[bit21] DADR (Dest.-ADdr.-reg. Reload)*: Transfer destination address register reload specification
This bit controls reloading of the transfer destination address register for the corresponding channel.
If this bit enables reloading, the transfer destination address register value is restored to its initial value
after the transfer is completed.
The details of other functions are the same as those described for bit22 (SADR).
DADR
Function
0
Disables transfer destination address register reloading. (initial value)
1
Enables transfer destination address register reloading.
•
When reset: Initialized to "0".
•
This bit is readable and writable.
[bit20] ERIE (ERror Interrupt Enable)*: Error interrupt output enable
This bit controls the occurrence of an interrupt for termination after an error occurs. The nature of the error
that occurred is indicated by DSS2 to DSS0. Note that an interrupt occurs only for specific termination
causes and not for all termination causes. (Refer to bits DSS2-DSS0.)
ERIE
Function
0
Disables error interrupt request output. (initial value)
1
Enables error interrupt request output.
•
When reset: Initialized to "0".
•
This bit is readable and writable.
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CHAPTER 16 DMA CONTROLLER (DMAC)
16.2 Detailed Explanation of the DMAC Registers
MB91490 Series
[bit19] EDIE (EnD Interrupt Enable)*: End interrupt output enable
This bit controls the occurrence of an interrupt for normal termination.
EDIE
Function
0
Disables end interrupt request output. (initial value)
1
Enables end interrupt request output.
•
When reset: Initialized to "0".
•
This bit is readable and writable.
[bit18 to bit16] DSS2 to DSS0 (DMA Stop Status)*: Transfer stop source indication
These bits indicate a code (end code) of 3 bits that indicates the source of stopping or termination of
DMA transfer on the corresponding channel. The table below lists the end codes:
DSS
Function
Interrupt
000B
Initial value
None
X01B
Address error (underflow/overflow)
Error
X10B
Transfer stop request
Error
X11B
Normal end
End
1XXB
DMA stopped temporarily (due, for example, to DMAH, PAUS bit,
and an interrupt)
None
The code indicating a transfer stop request is set only if the request is received from a peripheral circuit.
The Interrupt column indicates the type of interrupts that can occur.
•
When reset: Initialized to "000B".
•
These bits can be cleared by writing "000B" to them.
•
These bits are readable and writable. Note, however, that the only valid written value is "000B".
[bit15 to bit8] SASZ7 to SASZ0 (Source Addr count SiZe)*: Transfer source address count size
specification
These bits specify the increment or decrement width for the transfer source address (DMASA) of the
corresponding channel for each transfer operation. The value set by these bits becomes the address
increment/decrement width for each transfer unit. The address increment/decrement width conforms to
the instruction in the transfer source address count mode (SADM).
SASZ
XXH
576
Function
Specify the increment/decrement width of the transfer source address. "0" to "255"
•
When reset: Not initialized
•
These bits are readable and writable.
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16.2 Detailed Explanation of the DMAC Registers
MB91490 Series
[bit7 to bit0] DASZ7 to DASZ0 (Des Addr count SiZe)*: Transfer destination address count size
specification
These bits specify the increment or decrement width for the transfer destination address (DMADA) of
the corresponding channel for each transfer operation. The value set by these bits becomes the address
increment/decrement width for each transfer unit. The address increment/decrement width conforms to
the instruction in the transfer destination address count mode (DADM).
DASZ
Function
XXH
Specify the increment/decrement width of the transfer destination address. "0" to "255"
•
When reset: Not initialized
•
These bits are readable and writable.
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CHAPTER 16 DMA CONTROLLER (DMAC)
16.2 Detailed Explanation of the DMAC Registers
16.2.3
MB91490 Series
DMAC ch.1,ch.2,ch.3,ch.4 Transfer Source/Transfer
Destination Address Setting Registers
The DMASA0 to DMASA4 registers and DMADA0 to DMADA4 registers control the
operation of the DMAC channels. A separate register is provided for each channel.
■
Functions of the DMASA0 to DMASA4 and DMADA0 to DMADA4 Bits
The functions of the DMASA0 to DMASA4 and DMADA0 to DMADA4 bits are shown below:
Figure 16.2-3 DMAC Transfer Source/Transfer Destination Address Setting Registers
Address
bit31 bit30 bit29 bit28 bit27 bit26 bit25 bit24 bit23 bit22 bit21 bit20 bit19 bit18 bit17 bit16
ch.0: 001000H
ch.1: 001008H
ch.2: 001010H
ch.3: 001018H
ch.4: 001020H bit15 bit14 bit13 bit12 bit11 bit10
DMASA [31 : 16]
R/W
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
DMASA [15 : 0]
R/W
(Initial value: XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXXB)
Address
bit31 bit30 bit29 bit28 bit27 bit26 bit25 bit24 bit23 bit22 bit21 bit20 bit19 bit18 bit17 bit16
ch.0: 001004H
ch.1: 00100CH
ch.2: 001014H
ch.3: 00101CH
ch.4: 001024H bit15 bit14 bit13 bit12 bit11 bit10
DMADA [31 : 16]
R/W
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
DMADA [15 : 0]
R/W
(Initial value: XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXXB)
R/W: Readable/writable
DMASA0 to 4 and DMADA0 to 4 are a group of registers used to store transfer source and transfer
destination addresses. The length of each register is 32 bits.
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CHAPTER 16 DMA CONTROLLER (DMAC)
16.2 Detailed Explanation of the DMAC Registers
[bit31 to bit0] DMASA31 to DMASA0 (DMA Source Addr)*: Transfer source address setting
These bits set the transfer source address.
[bit31 to bit0] DMADA31 to DMADA0 (DMA Destination Addr)*: Transfer destination address setting
These bits set the transfer destination address.
If DMA transfer is activated, data in this register is stored in the counter buffer of the DMA-dedicated
address counter and then the address is counted according to the settings for the transfer operation.
When the DMA transfer is completed, the contents of the counter buffer are written back to this register
and then DMA ends. Thus, the address counter value during DMA operation cannot be read.
All registers have a dedicated reload register. When the register is used for a channel that is enabled for
reloading of the transfer source/transfer destination address register, the initial value is automatically
written back to the register when the transfer is completed. Other address registers are not affected.
• When reset: Not initialized.
• These bits are readable and writable. For this register, be sure to access these bits as 32-bit data.
• If these bits are read during transfer, the address before the transfer is read. If they are read after
transfer, the next access address is read. Because the reload value cannot be read, it is not possible to
read the transfer address in real time.
Note:
Do not set any of the DMAC’s registers using this register. DMA transfer is not possible for the
DMAC’s registers themselves.
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CHAPTER 16 DMA CONTROLLER (DMAC)
16.2 Detailed Explanation of the DMAC Registers
16.2.4
MB91490 Series
DMAC ch.1,ch.2,ch.3,ch.4 DMAC All-Channel Control
Register
The [DMACR] register controls the operation of all five DMAC channels. Always use
byte length to access this register.
■
Functions of the [DMACR] Bits
The functions of the [DMACR] bits are shown below:
Figure 16.2-4 Functions of DMACR Bits
Address
bit31 bit30 bit29 bit28 bit27 bit26 bit25 bit24 bit23 bit22 bit21 bit20 bit19 bit18 bit17 bit16
000204H
DMAE
-
-
PM01
DMAH [3 : 0]
R/W R/W R/W R/W
bit15 bit14 bit13 bit12 bit11 bit10
-
-
-
-
-
R/W
-
-
-
-
-
-
-
-
-
R/W R/W R/W R/W R/W R/W R/W R/W
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
-
-
-
-
-
-
-
-
-
-
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
(Initial value: 0--00 000 -------- -------- --------B)
R/W: Readable/writable
[bit31] DMAE (DMA Enable): DMA operation enable
This bit controls the operation of all DMA channels.
If DMA operation is disabled with this bit, transfer operations on all channels are disabled regardless of
the start/stop settings for each channel and the operating status. Any channel carrying out transfer
cancels the requests and stops transfer at a block boundary. All start operations on each channel in a
disabled state are disabled.
If this bit enables DMA operation, start/stop operations are enabled for all channels. Simply enabling
DMA operation with this bit does not activate each channel.
DMA operation can be forced to stop by writing "0" to this bit. However, be sure to force stopping ("0"
write) only after temporarily stopping DMA using the DMAH[3:0] bits [bit27-bit24 of DMACR]. If
forced stopping is carried out without first temporarily stopping DMA, DMA stops, but the transfer data
cannot be guaranteed. Check whether DMA is stopped using the DSS[2:0] bits [bit18 to bit16 of
DMACB].
DMAE
580
Function
0
Disables DMA transfer on all channels. (initial value)
1
Enables DMA transfer on all channels.
•
When reset: Initialized to "0".
•
This bit is readable and writable.
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CHAPTER 16 DMA CONTROLLER (DMAC)
16.2 Detailed Explanation of the DMAC Registers
MB91490 Series
[bit28] PM01 (Priority Mode ch.0, ch.1 robin): Channel priority rotation
This bit is set to alternate priority for each transfer between Channel0 and Channel1.
PM01
Function
0
Fixes the priority. (ch.0 > ch.1)(initial value)
1
Alternates priority. (ch.1 > ch.0)
•
When reset: Initialized to "0".
•
This bit is readable and writable.
[bit27 to bit24] DMAH3 to DMAH0 (DMA Halt): DMA temporary stop
These bits control temporary stopping of all DMA channels. If these bits are set, DMA transfer is not
performed on any channel before these bits are cleared again.
When DMA transfer is activated after these bits are set, all channels remain temporarily stopped.
Transfer requests that occur on channels for which DMA transfer is enabled (DENB=1) while these bits
are set are all enabled. The transfer can be started by clearing all these bits.
DMAH
0000B
Other than 0000B
Function
Enables the DMA operation on all channels. (initial value)
Temporarily stops DMA operation on all channels.
•
When reset: Initialized to "0".
•
These bits are readable and writable.
[bit30, bit29, bit23 to bit0] (Reserved): Undefined bits
•
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A read value is undefined.
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16.3 Explanation of the DMAC Operation
16.3
MB91490 Series
Explanation of the DMAC Operation
This section provides an overview of DMAC operation. It also provides details of
transfer request settings and transfer sequences and operational details.
■
Overview of DMAC
The DMAC block is a multi-functional DMA controller that controls high-speed data transfer without the
use of CPU instructions. It is built into all FR family devices.
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16.3.1
CHAPTER 16 DMA CONTROLLER (DMAC)
16.3 Explanation of the DMAC Operation
Overview of the DMAC Operation
This section provides an overview of DMAC operation.
■
Main DMAC Operations
Functions can be set for each transfer channel independently.
Once starting has been enabled, a channel starts transfer operation only after a specified transfer request has
been detected.
After a transfer request is detected, a DMA transfer request is outputted to the bus controller and the bus
right is acquired by the bus controller before the transfer is started. The transfer is carried out as a sequence
conforming to the mode settings made independently for the channel being used.
■
Transfer Mode
Each DMA channel performs transfer according to the transfer mode set by the MOD[1:0] bits of its
DMACB register.
● Block/step transfer
Only a single block transfer unit is transferred in response to one transfer request. DMA then stops
requesting the bus controller for transfer until the next transfer request is received.
The block transfer unit is the specified block size: (BLK[3:0] of DMACA).
● Burst transfer
Transfer in response to one transfer request is carried out continuously for the number of times in the
specified transfer count.
The specified transfer count is the block size × transfer count: (BLK[3:0] of DMACA  DTC[15:0] of
DMACA).
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16.3 Explanation of the DMAC Operation
■
MB91490 Series
Transfer Type
● 2-cycle transfer (normal transfer)
The DMA controller operates a read operation and a write operation as a single unit.
Data is read from an address in the transfer source register and then written to another address in the
transfer destination register.
■
Transfer Address
The following types of addressing are available and can be set independently for each channel transfer
source and transfer destination.
● Specifying the address for a 2-cycle transfer
The value read from a register (DMASA/DMADA) in which an address has been set in advance is used as
the address for access. After receiving a transfer request, DMA stores the address from the register in the
temporary storage buffer and then starts transfer.
After each transfer (access) operation, the next access address is generated (increment/decrement/fixed
selectable) by the address counter and then restored to the temporary storage buffer. Because the contents
of the temporary storage buffer are written back to the register (DMASA/DMADA) after each block
transfer unit is completed, the address register (DMASA/DMADA) value is updated after each block
transfer unit is completed, making it impossible to determine the address in real time during transfer.
■
Transfer Count and Transfer End
● Transfer count
The transfer count register is decremented (-1) after each block transfer unit is completed. When the
transfer count register becomes "0", counting for the specified transfer ends, and the transfer stops with the
end code displayed or is reactivated (1).
Like the address register, the transfer count register is updated only after each block transfer unit.
If transfer count register reloading is disabled, the transfer ends. If reloading is enabled, the register is
initialized and then waits for transfer (DTCR of DMACB)
● Transfer end
Listed below are the sources for transfer end. When transfer ends, a source is indicated as the end code
(DSS[2:0] of DMACB).
•
End of the specified transfer count (DMACA:BLK[3:0]  DMACA:DTC[15:0]) => Normal end
•
A transfer stop request from a peripheral circuit occurred => Error
•
An address error occurred => Error
•
A reset occurred => Reset
The transfer stop source is indicated (DSS) and the transfer end interrupt or error interrupt for the end
source is generated.
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16.3 Explanation of the DMAC Operation
MB91490 Series
16.3.2
Setting a Transfer Request
The following two types of transfer requests are provided to activate DMA transfer:
• Built-in peripheral request
• Software request
Software requests can always be used regardless of the settings for other requests.
■
Built-in Peripheral Request
A transfer request is generated by an interrupt from the built-in peripheral circuit.
For each channel, set the peripheral’s interrupt by which a transfer request is generated (when the IS4 to
IS0 bits of DMACA are 1XXXXB).
Note:
Because an interrupt request used in a transfer request seems like an interrupt request to the CPU,
disable interrupts from the interrupt controller (ICR register).
■
Software Request
A transfer request is generated by writing to the trigger bit of a register (STRG of DMACA).
The software request is independent of the above transfer request and can always be used.
If a software request occurs concurrently with activation (transfer enable), a DMA transfer request is
outputted to the bus controller immediately and transfer is started.
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CHAPTER 16 DMA CONTROLLER (DMAC)
16.3 Explanation of the DMAC Operation
16.3.3
MB91490 Series
Transfer Sequence
The transfer type and the transfer mode that determine, for example, the operation
sequence after DMA transfer has started can be set independently for each channel
(Settings for TYPE[1:0] and MOD[1:0] of DMACB).
■
Selection of the Transfer Sequence
The following sequence can be selected with a register setting:
■
•
Burst 2-cycle transfer
•
Block/step 2-cycle transfer
Burst 2-Cycle Transfer
In a burst 2-cycle transfer, as many transfers as specified by the transfer count are performed continuously
for one transfer source. For a 2-cycle transfer, all 32-bit areas can be specified using a transfer source/
transfer destination address.
A peripheral transfer request or software transfer request can be selected as the transfer source.
Table 16.3-1 lists the specifiable transfer addresses for burst 2-cycle transfer.
Table 16.3-1 Specifiable Transfer Addresses for Burst 2-Cycle Transfer
Transfer source addressing
Direction
Transfer destination addressing
All 32-bit areas specifiable

All 32-bit areas specifiable
[Features of a burst transfer]
•
When one transfer request is received, transfer is performed continuously until the transfer count
register reaches 0. The transfer count is the transfer count  block size (BLK[3:0] of DMACA 
DTC[15:0] of DMACA).
•
Another request occurring during transfer is ignored.
•
If the reload function of the transfer count register is enabled, the next request is accepted after transfer
ends.
•
If a transfer request for another channel with a higher priority is received during transfer, the channel is
switched at the boundary of the block transfer unit. Processing resumes only after the transfer request
for the other channel is cleared.
Figure 16.3-1 shows an example of burst transfer.
Figure 16.3-1 Example of Burst Transfer
Transfer request ( edge)
Bus operation
Transfer count
Transfer end
(Burst transfer example: Rising edge trigger, block number = 1, transferring number = 4)
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16.3 Explanation of the DMAC Operation
MB91490 Series
■
Step/Block Transfer 2-Cycle Transfer
For a step/block transfer (Transfer for each transfer request is performed as many times as the specified
block count), all 32-bit areas can be specified as the transfer source/transfer destination address.
Table 16.3-2 lists the specifiable transfer addresses for step/block transfer 2-cycle transfer.
Table 16.3-2 Specifiable Transfer Addresses for Step/Block Transfer 2-Cycle Transfer
■
Transfer source addressing
Direction
Transfer destination addressing
All 32-bit areas specifiable

All 32-bit areas specifiable
Step Transferring
If "1" is set to the size of the block, it becomes a step transferring sequence.
[Feature of step transferring]
• Transferring is stopped clearing the transferring request after it transfers it once when the
transferring request is accepted once (The DMA transferring request is withdrawn for the bus
controller).
• When the request is generated again while transferring it, the request is ignored.
• Transferring is started continuing to switch the channel after transferring stops when the transferring
request of the channel besides a high priority level is accepted by being transferring it.
Only when the transferring request is generated at the same time, the priority level in the step
transferring has the meaning.
■
Block Transfer
If any value other than "1" is specified as the block size, a block transfer sequence is generated.
[Features of a block transfer]
The block transfer has the same features as those of a step transfer except that one transfer unit consists
of multiple transfer cycle counts (number of blocks). Figure 16.3-2 shows an example of block transfer.
Figure 16.3-2 Example of Block Transfer
Transfer request (
edge)
Bus operation
Number of blocks
Transfer count
Transfer end
(Example of block transfer where block transfer is started by rising-edge trigger,
the number of blocks is "2", and the transfer count is "2".)
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16.3 Explanation of the DMAC Operation
16.3.4
MB91490 Series
General Aspects of DMA Transfer
This section describes DMA transfer.
■
Block Size
The unit and increment for transfer data is a set of (the number set in the block size specification register 
data width) data.
Since the amount of data transferred in one transfer cycle is determined by the value specified as the data
width, one transfer unit is consists of the number of transfer cycles for the specified block size.
If a transfer request with a higher priority is received during transfer or if a temporary stop request for a
transfer occurs, the transfer stops only at the transfer unit boundary, whether or not the transfer is a block
transfer. This arrangement makes it possible to protect data block for which division or temporary stopping
is not desirable. However, if the block size is large, response time reduces.
Transfer stops immediately only when a reset occurs, in which case the data being transferred cannot be
guaranteed.
■
Reload Operation
In this module, the following three types of reloading can be set for each channel:
(1) Transfer count register reloading
After transfer is performed the specified number of times, the initial value is set in the transfer count
register again and waiting for a start request starts.
Set this type of reloading when the entire transfer sequence is to be performed repeatedly.
If reload is not specified, the count register value remains "0" after the transfer is performed the
specified number of times and no further transfer is performed.
(2) Transfer source address register reloading
After transfer is performed the specified number of times, the initial value is set in the transfer source
address register again.
Set this type of reloading when transfer is to be repeated from a fixed area in the transfer source address
area.
If reload is not specified, the transfer source address register value after the transfer is performed the
specified number of times becomes the next address. Use this type when the address area is not fixed.
(3) Transfer destination address register reloading
After transfer is performed the specified number of times, the initial value is set in the transfer
destination address register again.
Set this type of reloading when transfer is to be repeated to a fixed area in the transfer destination
address area.
(The processing hereafter is the same as described in "Transfer source address register reloading"
above.)
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CHAPTER 16 DMA CONTROLLER (DMAC)
16.3 Explanation of the DMAC Operation
If only reloading of the transfer source/transfer destination register is enabled, restart after transfer is
performed the specified number of times is not implemented and only the values of each address register
are set.
[Special examples of operating mode and the reload operation]
For a transfer in burst, block, or step transfer mode, transfer stops temporarily after reload when data
transfer ends. Transfer does not start until new transfer request input is detected.
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CHAPTER 16 DMA CONTROLLER (DMAC)
16.3 Explanation of the DMAC Operation
16.3.5
MB91490 Series
Addressing Mode
Specify the transfer destination/transfer source address independently for each transfer
channel.
This section describes the specification method. Specify the addresses based on the
transfer sequence.
■
Address Register Specifications
In 2-cycle transfer mode, set the transfer source address in the transfer source address setting register
(DMASA) and the transfer destination address in the transfer destination address setting register
(DMADA).
[Features of the Address Register]
This register has the maximum 32-bit length. With 32-bit length, all space in the memory map can be
accessed.
[Function of the Address Register]
•
The address register is read in each access operation and the read value is sent to the address bus.
•
At the same time, the address for the next access is calculated by the address counter and the address
register is updated using the calculated address.
•
For address calculation, increment or decrement is selected independently for each channel, transfer
destination, and transfer source. The address increment/decrement width is specified by the address
count size register (SASZ/DASZ of DMACB).
•
If reloading is not enabled, the address resulting from the address calculation of the last address remains
in the address register when the transfer ends.
•
If reloading is enabled, the initial value of the address is reloaded.
Reference:
If an overflow or underflow occurs as a result of 32-bit length full address calculation, an address
error is detected and transfer on the relevant channel is stopped.
Notes:
• Do not set the address of the register of DMAC to the address register.
• Do not transfer DMAC to the register by DMAC.
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16.3 Explanation of the DMAC Operation
MB91490 Series
16.3.6
Data Types
Select the data length (data width) transferred in one transfer operation from the
following:
• Byte
• Halfword
• Word
■
Access Address
Since the word boundary specification is also observed in DMA transfer, different low-order bits are
ignored if an address with a different data length is specified for the transfer destination/transfer source
address.
The actual access address has a 4-byte length starting with "00B" as the lowest-order 2 bits.
•
Word:
•
Halfword: The actual access address has 2-byte length starting with "0B" as the lowest-order bit.
•
Byte:
The actual access address and the addressing match.
If the lowest-order bits in the transfer source address and transfer destination address are different, the
addresses as set are output on the internal address bus. However, each transfer target on the bus is accessed
after the addresses are corrected according to the above rules.
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16.3 Explanation of the DMAC Operation
16.3.7
MB91490 Series
Transfer Count Control
Specify the transfer count within the range of the maximum 16-bit length (1 to 65536).
Set the transfer count value in the transfer count register (DTC of DMACA).
■
Transfer Count Registers and Reload Operation
The register value is stored in the temporary storage buffer when the transfer starts and is decremented by
the transfer count counter. When the counter value becomes "0", transfer end for the specified count is
detected, and the transfer on the channel is stopped or waiting for a restart request starts (when reload is
specified).
[Features of the group of transfer count registers:]
•
Each register has 16-bit length.
•
All registers have a dedicated reload register.
•
If transfer is activated when the register value is "0", transfer is performed 65536 times.
[Reload operation]
592
•
The reload operation can be used only if reloading is enabled in a register that allows reloading.
•
When transfer is activated, the initial value of the count register is saved in the reload register.
•
If the transfer count counter counts down to "0", end of transfer is reported and the initial value is read
from the reload register and written to the count register.
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CHAPTER 16 DMA CONTROLLER (DMAC)
16.3 Explanation of the DMAC Operation
MB91490 Series
16.3.8
CPU Control
When a DMA transfer request is accepted, DMA generates a transfer request to the bus
controller.
The bus controller passes the right to use the internal bus to DMA at a break in bus
operation and DMA transfer starts.
■
DMA Transfer and Interrupts
During DMA transfer, interrupts are generally not accepted until the transfer ends.
If a DMA transfer request occurs during interrupt processing, the transfer request is accepted and interrupt
processing is stopped until the transfer is completed.
If, as an exception, an NMI request or an interrupt request with a higher level than the hold suppress level
set by the interrupt controller occurs, DMAC temporarily cancels the transfer request via the bus controller
at a transfer unit boundary (one block) to temporarily stop the transfer until the interrupt request is cleared.
In the meantime, the transfer request is retained internally. After the interrupt request is cleared, DMAC
generates a transfer request to the bus controller again to acquire the right to use the bus and then restarts
DMA transfer.
■
Suppressing DMA
When an interrupt source with a higher priority occurs during DMA transfer, an FR family device
interrupts the DMA transfer and branches to the relevant interrupt routine. This feature is valid as long as
there are any interrupt requests. When all interrupt sources are cleared, the suppression feature no longer
works and the DMA transfer is restarted by the interrupt processing routine. Thus, if you want to suppress
restart of DMA transfer after clearing interrupt sources in the interrupt source processing routine at a level
that interrupts DMA transfer, use the DMA suppress function. The DMA suppress function can be
activated by writing any value other than "0" to the DMAH[3:0] bits of the DMA all-channel control
register and can be stopped by writing "0" to these bits.
This function is mainly used in the interrupt processing routines. Before the interrupt sources in an interrupt
processing routine are cleared, the DMA suppress register is incremented by "1". If this is done, then no
DMA transfer is performed. After interrupt processing, decrement the DMAH[3:0] bits by "1" before
returning. If multiple interrupts have occurred, DMA transfer continues to be suppressed since the
DMAH[3:0] bits are not "0" yet. If a single interrupt has occurred, the DMAH[3:0] bits become "0". DMA
requests are then enabled immediately.
Notes:
• Since the register has only 4 bits, this function cannot be used for multiple interrupts exceeding 15
levels.
• Be sure to assign the priority of the DMA tasks at a level that is at least 15 levels higher than
other interrupt levels.
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16.3 Explanation of the DMAC Operation
16.3.9
MB91490 Series
Operation Start
Starting of DMA transfer is controlled independently for each channel, but before
transfer starts, the operation of all channels needs to be enabled.
■
Enabling Operation for All Channels
Before activating each DMAC channel, operation for all channels needs to be enabled in advance with the
DMA operation enable bit (DMAE of DMACR).
All start settings and transfer requests that occurred before operation is enabled are invalid.
■
Starting Transfer
The transfer operation can be started by the operation enable bit of the control register for each channel. If a
transfer request to an activated channel is accepted, the DMA transfer operation is started in the specified
mode.
■
Starting from a Temporary Stop
If a temporary stop occurs before starting with channel-by-channel or all-channel control, the temporary
stopped state is maintained even though the transfer operation is started. If transfer requests occur in the
meantime, they are accepted and retained.
When temporary stopping is released, transfer is started.
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CHAPTER 16 DMA CONTROLLER (DMAC)
16.3 Explanation of the DMAC Operation
MB91490 Series
16.3.10
Transfer Request Acceptance and Transfer
This section describes transfer request acceptance and transfer.
■
Transfer Request Acceptance and Transfer
Sampling for transfer requests set for each channel starts after starting.
Since peripheral interrupts are handled as level detection, use interrupt clear by DMA to handle the
interrupts.
Transfer requests are always accepted while other channel requests are being accepted and transfer
performed. The channel that will be used for transfer is determined for each transfer unit after priority has
been checked.
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CHAPTER 16 DMA CONTROLLER (DMAC)
16.3 Explanation of the DMAC Operation
16.3.11
MB91490 Series
Clearing Peripheral Interrupts by DMA
This DMA has a function that clears peripheral interrupts. This function works when
peripheral interrupt is selected as the DMA start source (when IS[4:0]=1XXXXB).
Peripheral interrupts are cleared only for the set start sources. That is, only the
peripheral functions set by IS[4:0] are cleared.
■
Timing for Clearing Interrupts During DMA
The timing for clearing an interrupt depends on the transfer mode. (See Section "16.4
Flowcharts of the DMAC").
Operation
[Block/step transfer]
If block transfer is selected, a clear signal is generated after one block (step) transfer.
[Burst transfer]
If burst transfer is selected, a clear signal is generated after transfer is performed the specified number
of times.
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CHAPTER 16 DMA CONTROLLER (DMAC)
16.3 Explanation of the DMAC Operation
MB91490 Series
16.3.12
Temporary Stopping
This section describes the temporary stopping of DMA transfer.
■
Setting of Temporary Stopping by Writing to the Control Register (Set Independently
for Each Channel or All Channels Simultaneously)
If temporary stopping is set using the temporary stop bit, transfer on the corresponding channel is stopped
until release of temporary stopping is set again. You can check the DSS bits for temporary stopping.
Transfer is restarted when temporary stopping is canceled.
■
NMI/Hold Suppress Level Interrupt Processing
If an NMI request or an interrupt request with a higher level than the hold suppress level occurs, all
channels on which transfer is in progress are stopped at the boundary of the transfer unit and the bus right is
released to give priority to NMI/interrupt processing. Transfer interrupts accepted during NMI/interrupt
processing are retained, initiating a wait for completion of NMI processing.
Channels for which requests are retained restart transfer after NMI/interrupt processing is completed.
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CHAPTER 16 DMA CONTROLLER (DMAC)
16.3 Explanation of the DMAC Operation
16.3.13
MB91490 Series
Operation End/Stopping
The end of DMA transfer is controlled independently for each channel. It is also
possible to disable operation for all channels at once.
■
Transfer End
If reloading is disabled, transfer is stopped, "Normal end" is displayed as the end code, and all transfer
requests are disabled after the transfer count register becomes "0" (Clear the DENB bit of DMACA).
If reloading is enabled, the initial value is reloaded, "Normal end" is displayed as the end code, and a wait
for transfer requests starts again after the transfer count register becomes "0" (Do not clear the DENB bit of
DMACA).
■
Disabling All Channels
If the operation of all channels is disabled with the DMA operation enable bit (DMAE), all DMAC
operations, including operations on active channels, are stopped. Then, even if the operation of all channels
is enabled again, no transfer is performed unless a channel is restarted. In this case, no interrupt whatever
occurs.
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CHAPTER 16 DMA CONTROLLER (DMAC)
16.3 Explanation of the DMAC Operation
MB91490 Series
16.3.14
Stopping due to an Error
In addition to normal end after transfer for the number of times specified, stopping as
the result of various types of errors and the forced stopping are provided.
■
Transfer Stop Requests from Peripheral Circuits
Depending on the peripheral circuit that outputs a transfer request, a transfer stop request is issued when an
error is detected (Example: Error when data is received at or sent from a communications system
peripheral).
The DMAC, when it receives such a transfer stop request, displays "Transfer stop request" as the end code
and stops the transfer on the corresponding channel.
■
Occurrence of an Address Error
Inappropriate addressing occurring in an addressing mode is detected as an address error. An example of
inappropriate addressing is an overflow or underflow that occurs in the address counter when a 32-bit
address is specified.
If an address error is detected, "An address error occurred" is displayed as the end code and transfer on the
corresponding channel is stopped.
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CHAPTER 16 DMA CONTROLLER (DMAC)
16.3 Explanation of the DMAC Operation
16.3.15
MB91490 Series
DMAC Interrupt Control
Independent of peripheral interrupts that become transfer requests, interrupts can also
be outputted for each DMAC channel.
■
Interrupts That Enable DMAC Interrupt Control Outputs
•
Transfer end interrupt:
Occurs only when operation ends normally.
•
Error interrupt:
Transfer stop request due to a peripheral circuit (error due to a peripheral)
Occurrence of address error (error due to software)
All of these interrupts are outputted according to the meaning of the end code.
An interrupt request can be cleared by writing "000B" to DSS2 to DSS0 (end code) of DMACB.
Be sure to clear the end code by writing "000B" before restarting.
If reloading is enabled, the transfer is automatically restarted. At this point, however, the end code is not
cleared and is retained until a new end code is written when the next transfer ends.
Since only one end source can be displayed in an end code, the result after considering the order of priority
is displayed when multiple sources occur simultaneously. The interrupt that occurs at this point conforms to
the displayed end code.
The following shows the priority for displaying end codes (in order of decreasing priority):
600
•
Reset
•
Clearing by writing "000B"
•
Peripheral stop request
•
Normal end
•
Stopping when address error detected
•
Channel selection and control
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CHAPTER 16 DMA CONTROLLER (DMAC)
16.3 Explanation of the DMAC Operation
MB91490 Series
16.3.16
DMA Transfer during Sleep
The DMAC can also operate in sleep mode.
The DMA transfer in sleep mode is described as follows.
■
Notes on DMA Transfer in Sleep Mode
If you anticipate operations during sleep mode, note the following:
• Since the CPU is stopped, DMAC registers cannot be rewritten. Make settings before sleep mode is
entered.
• The sleep mode is released by an interrupt. Thus, if a peripheral interrupt is selected as the DMAC start
source, interrupts must be disabled by the interrupt controller.
Similarly, if you do not want to release sleep mode with a DMAC end interrupt, disable DMAC end
interrupts.
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CHAPTER 16 DMA CONTROLLER (DMAC)
16.3 Explanation of the DMAC Operation
16.3.17
MB91490 Series
Channel Selection and Control
Up to five channels can be simultaneously set as transfer channels. In general, an
independent function can be set for each channel.
■
Priority among Channels
Since DMA transfer is possible only on 1 channel at a time, priority must be set for the channels.
Two modes, fixed and rotation, are provided as the priority settings and can be selected for each channel
group (refer to "■ Channel Group").
● Fixed mode
The order of priority is fixed by channel number, with priority ascending from ch.0 to ch.4:
(ch.0 > ch.1 > ch.2 > ch.3 > ch.4)
If a transfer request with a higher priority is received during a transfer, the transfer channel becomes the
channel with the higher priority when the transfer for the transfer unit (number set in the block size
specification register  data width) ends.
When higher priority transfer is completed, transfer is restarted on the previous channel.
Figure 16.3-3 shows DMA transfer in fixed mode.
Figure 16.3-3 DMA Transfer in Fixed Mode
ch.0 transfer request
ch.1 transfer request
Bus operation
Transfer channel
CPU
SA
DA
ch.1
SA
DA
ch.0
SA
DA
ch.0
SA
DA
CPU
ch.1
ch.0 transfer end
ch.1 transfer end
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CHAPTER 16 DMA CONTROLLER (DMAC)
16.3 Explanation of the DMAC Operation
MB91490 Series
● Rotation mode (between ch.0 and ch.1 only)
When operation is enabled, the initial states have the same order that they would have in fixed mode, but at
the end of each transfer operation, the priority of the channels is reversed. Thus, if more than one transfer
request is outputted at the same time, the channel is switched after each transfer unit.
This mode is effective when continuous or burst transfer is set.
Figure 16.3-4 shows DMA transfer in rotation mode.
Figure 16.3-4 DMA Transfer in Rotation Mode
ch.0 transfer request
ch.1 transfer request
Bus operation
Transfer ch
ch.1
ch.0
ch.1
ch.0
ch.0 transfer end
ch.1 transfer end
■
Channel Group
Set the selection priority as explained in the table below.
Table 16.3-3 lists the settings for DMA selection priority.
Table 16.3-3 Setting DMA Selection Priority
CM71-10155-2E
Mode
Priority
Remarks
Fixed
ch.0 > ch.1

Rotation
ch.0 > ch.1

ch.0 < ch.1
The initial state is the top row.
If transfer occurs for the top row, the priority is reversed.
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CHAPTER 16 DMA CONTROLLER (DMAC)
16.4 Operation Flowcharts of the DMAC
16.4
MB91490 Series
Operation Flowcharts of the DMAC
Figure 16.4-1 and Figure 16.4-2 show operation flowcharts for DMA transfer.
■
Operation Flowchart for Block Transfer
Figure 16.4-1 Block Transfer
DMA stop
DENB=>0
DENB=1
Reload ena ble
Activation request
wait
Activation request
Load the initial address,
trans fer count, and number
of blocks
Calculate the address for
trans fer source address access
Calculate the address for trans fer
destination address access
Number of blocks - 1
BLK=0
Trans fer count - 1
Write ba ck the address,
trans fer count, and
number of blocks
BLK =/ 0
DTC =/ 0
Only when the peripheral
interrupt activation source
is selected
Interrupt clear
Interrupt cleared
DTC=0
DMA t rans fer end
DMA inter rupt generated
Note:
Blo ck trans fer
- Can be activated by all activation sources (selection)
- Can access all areas
- The number of blocks can be set
- Inter rupt clear is issued when number of blocks is completed
- The DMA inter rupt is issued when transfer for the number of times specified is completed
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CHAPTER 16 DMA CONTROLLER (DMAC)
16.4 Operation Flowcharts of the DMAC
MB91490 Series
■
Operation Flowchart for Burst Transfer
Figure 16.4-2 Burst Transfer
DMA stop
DENB=>0
DENB=1
Reload enable
Activation request
wait
Load the initial address,
trans fer count, and
number of blocks
Calculate the address for
trans fer source address access
Calculate the address for trans fer
destination address access
Number of blocks - 1
BLK =/ 0
BLK=0
Trans fer count - 1
DTC =/ 0
DTC=0
Write ba ck the address,
trans fer count, and number
of blocks
Interrupt clear
Only when the pe ripheral inter rupt
activation source is selected
Interrupt cleared
DMA t rans fer end
DMA inter rupt generated
Note:
Burst t rans fer
- Can be activated by all acti vation sources (selection)
- Can access all areas
- The number of blocks can be set
- Inter rupt clear and the DMA interrupt are issued when transfer for the number of
times specified is completed
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CHAPTER 16 DMA CONTROLLER (DMAC)
16.5 Data Bus of the DMAC
16.5
MB91490 Series
Data Bus of the DMAC
This section shows the flow of data during different types of transfer operation.
■
Flow of Data During 2-Cycle Transfer
Figure 16.5-1 and Figure 16.5-2 show the flow of data during 2-cycle transfer.
Figure 16.5-1 Built-in I/O Area  Built-in RAM Area Transfer
Built-in I/O area => Built-in RAM area transfer
DMAC
DMAC
Write cycle
I-bus
CPU
CPU
Read cycle
I-bus
Bus controller
D-bus
Data buffer
D-bus
F-bus
F-bus
I/O
RAM
Bus controller
Data buffer
RAM
I/O
Figure 16.5-2 Internal RAM Area  Built-in I/O Area Transfer
Internal RAM area => Built-in I/O area transfer
DMAC
DMAC
Write cycle
I-bus
CPU
CPU
Read cycle
I-bus
Bus controller
D-bus
Data buffer
Bus controller
D-bus
F- bus
RAM
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Data buffer
F- bus
I/O
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I/O
CM71-10155-2E
CHAPTER 17
FLASH MEMORY
This chapter explains the overview of the flash memory,
the configuration and functions of registers, and the
flash memory operation.
17.1 Overview of Flash Memory
17.2 Flash Memory Registers
17.3 Explanation of Flash Memory Operation
17.4 Flash Memory Automatic Algorithms
17.5 Details of Programming and Erasing Flash Memory
17.6 Flash Security Feature
17.7 Notes on Flash Memory Programming
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CHAPTER 17 FLASH MEMORY
17.1 Overview of Flash Memory
17.1
MB91490 Series
Overview of Flash Memory
The MB91490 series contains 256-Kbyte flash memory which can be erased either for all
sectors collectively or sector by sector with a + 5.0 V single power supply and can be
programmed by the FR-CPU in half-words (in 16 bits).
■ Overview of Flash Memory Outline
The flash memory is built-in flash memory driven at 5.0 V. It is the same as the discrete flash memory
which can be programmed from outside the device by using a Flash programmer. In addition, the flash
memory has discrete flash memory - equivalent functions and it allows instructions and data to be read
from in words (32 bits), contributing to high-speed operation of the device when used as the built-in ROM
for FR-CPU.
The combination of the flash memory macro and the FR-CPU interface circuit provides the following
functions:
• Serving as CPUs memory for storing programs and data (hereafter, refer to as CPU mode)
- Accessible at 32-bit bus width when used as ROM
- Capable of being read/programmed/erased by the CPU instruction (using the automatic program
algorithm *)
• Functions equivalent to those of a discrete flash memory product (hereafter, refer to as Flash mode)
- Capable of being read/programmed/erased by a Flash programmer (using the automatic program
algorithm *)
This section describes the use of the flash memory from the FR-CPU.
For details on using this flash memory with a Flash programmer, refer to the instruction manual for the
Flash programmer.
*: Automatic program algorithm =Embedded Algorithm
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CHAPTER 17 FLASH MEMORY
17.1 Overview of Flash Memory
MB91490 Series
■ Flash Memory Block Diagram
Figure 17.1-1 shows the flash memory block diagram.
Figure 17.1-1 Flash Memory Block Diagram
Bus control
signal
FR I-bus (Instruction)
FA[18:0]
RESETX
BYTEX
CEX
OEX
Flash memory
Max 256Kbytes
WEX
Bus control
signal
DI[15:0]
RDY
DO[63:0]
Data buffer
Generating
control signal
ID[31:0]
Address buffer
IA[18:0]
FA[18:0]
WE
RDY
FD[31:0]
FR F-bus (Data)
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CHAPTER 17 FLASH MEMORY
17.1 Overview of Flash Memory
MB91490 Series
■ Memory Map for Flash Memory
Figure 17.1-2 shows the memory map for flash memory.
Figure 17.1-2 Memory Map for Flash Memory (CPU mode)
256 Kbytes
64bits
0010_0000H
000F_C000H
8KB
(SA7)
8KB
(SA6)
000F_8000H
8KB
(SA5)
8KB
(SA4)
000F_4000H
8KB
(SA3)
8KB
(SA2)
000F_0000H
8KB
(SA1)
8KB
(SA0)
32KB
(SA15)
32KB
(SA14)
64KB
(SA13)
64KB
(SA12)
Bit row
31 to 24, 23 to 16,
15 to 8, 7 to 0
31 to 24, 23 to 16,
15 to 8, 7 to 0
Address row
+0/+1/+2/+3
+4/+5/+6/+7
000E_0000H
000C_0000H
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CHAPTER 17 FLASH MEMORY
17.2 Flash Memory Registers
MB91490 Series
17.2
Flash Memory Registers
This section explains a configuration and a function of registers used in the flash
memory.
■ Overview of Flash Memory Registers
The flash memory has two registers:
• FLCR: Flash control/status register (CPU mode)
• FLWC: Flash wait register
FLCR
Address
007000H
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
R/W
R/W
R/W
R
RDY
R
R/W
WE
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
R
R/W
Initial value
----X-0-B
FLWC
Address
007004H
WTC5 WTC4
R/W
R/W
R/W
WTC2 WTC1 WTC0
R/W
R/W
R/W
Initial value
--11-011B
R/W: Readable/writable
R:
Read only
-:
Undefined bit
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CHAPTER 17 FLASH MEMORY
17.2 Flash Memory Registers
17.2.1
MB91490 Series
Flash Control/Status Register (FLCR)
This register shows the operation of the Flash memory. The register controls writing in
the Flash memory. The register can be accessed only in CPU mode.
Do not access this register in the read modify write (RMW) instruction.
■ Bit Structure of Flash Control/Status Register (FLCR)
Figure 17.2-1 shows the bit structure of the flash control/status register (FLCR).
Figure 17.2-1 Bit Structure of Flash Memory Control/Status Register (FLCR)
FLCR
Address
007000H
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
R/W
R/W
R/W
R
RDY
R
R/W
WE
R/W
R/W
----X-0-B
R/W: Readable/writable
R:
Read only
-:
Undefined bit
[bit7 to bit5] Reserved: Reserved bits
These bits are reserved bits. Always write "011B" to the bits.
[bit4] Reserved: Reserved bit
This bit is a reserved bit. Resetting initializes to "0".
[bit3] RDY: Ready
This bit shows the operation of the automatic algorithm (write/erase).
When this bit is "0", write or erase by an automatic algorithm is done. Therefore, a new write or erase
command is not accepted to this bit. And, the data read from the Flash memory address cannot be done.
The read data shows the status of the Flash memory.
RDY
Function
0
The read/write/erase command of data cannot be accepted while the write/erase is
operating.
1
The read/write/erase command of data can be accepted.
• This bit is not initialized at reset (depend on the state of the Flash memory at that time).
• Only read is possible. Writing doesn't effect to this bit value.
[bit2] Reserved: Reserved bit
This bit is a reserved bit. Always write "0" to the bit.
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CHAPTER 17 FLASH MEMORY
17.2 Flash Memory Registers
MB91490 Series
[bit1] WE: Write enabled.
This bit controls to program data and command into Flash memory in the CPU mode.
While this bit contains "0", any attempt to program data or a command into Flash memory is ignored.
While this bit contains "1", the programming of data and commands into Flash memory is valid, where
the automatic algorithm can be started.
Before updating this bit, be sure to check the RDY bit to make sure that the automatic algorithm (write/
erase) has been stopped. It is impossible to rewrite this bit value while the RDY bit is "0".
In the Flash mode, the write operation becomes effective regardless of the state of this bit.
WE
Function
0
Disable write access to Flash memory. [Initial value]
1
Enable write access to Flash memory.
•
Resetting initializes to "0".
•
Readable and writable.
Note:
When the RDY bit of the FLCR register is "0", this bit cannot be rewritten. Rewrite it after confirming
the RDY bit is "1". Moreover, please execute the rewriting program of this bit in F-bus RAM or an
external area. The program example is described as follows.
● Sample program (At the change to WE=0"1")
------------------------------------------------------------------------------------------------------------------LDI #_FLCR,R0
// FLCR register (0x7000)
LDI #0b01101010, R1
// Writing data of FLCR register
STB R1,@R0
// Write to FLCR (WE=0"1")
NOP
//NOP for timing adjustment  2
NOP
-------------------------------------------------------------------------------------------------------------------
● Sample program (At the change to WE=1"0")
------------------------------------------------------------------------------------------------------------------LDI #_FLCR,R0
// FLCR register (0x7000)
LDI #0b01101000, R1
// Writing data of FLCR register
STB R1,@R0
//Write to FLCR (WE=1"0")
NOP
// NOP for timing adjustment  2
NOP
-------------------------------------------------------------------------------------------------------------------
[bit0] Reserved: Reserved bit
This bit is a reserved bit. Always write "0" to the bit.
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CHAPTER 17 FLASH MEMORY
17.2 Flash Memory Registers
17.2.2
MB91490 Series
Flash Wait Register (FLWC)
The flash wait register (FLWC) controls wait states of flash memory access in CPU
mode.
■ Bit Structure of Flash Wait Register (FLWC)
Figure 17.2-2 shows the bit structure of the flash wait register (FLWC).
Figure 17.2-2 Bit Structure of Flash Wait Register (FLWC)
FLWC
Address
007004H
bit7
bit6
R
R/W
bit5
bit4
WTC5 WTC4
R/W
R/W
bit3
R/W
bit2
bit1
bit0
WTC2 WTC1 WTC0
R/W
R/W
R/W
Initial value
--11-011B
R/W: Readable/writable
R:
Read only
-:
Undefined bit
[bit7, bit6] Reserved: Reserved bits
These bits are reserved bits. Always write "00B" to the bits.
[bit3] Reserved: Reserved bit
This bit is a reserved bit. Always write "0" to the bit.
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CHAPTER 17 FLASH MEMORY
17.2 Flash Memory Registers
MB91490 Series
[bit5, bit4, bit2 to bit0] WTC5, WTC4, WTC2 to WTC0: Wait cycle bits
Read from flash memory*1 Write to flash memory*2
WTC5
WTC4
WTC2
WTC1
WTC0
Wait Cycle
0
0
0
0
0
-
Setting disabled
Setting disabled
0
0
0
0
1
1
Setting disabled
Setting disabled
0
0
0
1
0
2
Setting disabled
1
1
0
1
1
3
[Initial value]
Setting disabled
1
1
1
0
0
4
Setting disabled
Setting disabled
1
1
1
0
1
5
Setting disabled
Setting disabled
1
1
1
1
0
6
Setting disabled
Setting disabled
1
1
1
1
1
7
Setting disabled
• Resetting initializes to "11011B".
*1: Reads from the flash memory
(1) CPU clock (CLKB) < 50 MHz
{WTC5, WTC4, WTC2 to WTC0 > 00010B (2 wait cycles).
(2) CPU clock (CLKB) > 50 MHz
{WTC5, WTC4, WTC2 to WTC0 = 11011B (3 wait cycles).
*2: Writes to the flash memory
{WTC5, WTC4, WTC2 to WTC0 = 11111B (7 wait cycles).
• A combination other than the above is a set prohibition.
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CHAPTER 17 FLASH MEMORY
17.3 Explanation of Flash Memory Operation
17.3
MB91490 Series
Explanation of Flash Memory Operation
This section explains the operation of flash memory.
■ Access Mode of Flash Memory
The following two types of access modes are available to the FR-CPU to access flash memory:
• ROM mode
The CPU can read word (32 bits) of data collectively but cannot program data into flash memory.
• Programming mode
The CPU cannot access flash memory in word (32 bits) but can program data into flash memory in halfwords (16 bits).
■ FR-CPU ROM Mode (Read Only in 32 Bits)
In this mode, the flash memory serves as internal ROM for the FR-CPU. The CPU can read a word (32
bits) of data collectively but can neither program data into flash memory nor start the automatic algorithm.
● Specification method of mode
• This mode is established when the "WE" bit of the FLCR register is set to "0".
• The flash memory remains in this mode whenever a reset is cancelled during CPU operation.
• This mode cannot be selected not during CPU operation.
● Operation content
When reading a flash memory area, the CPU can read a word (32 bits) of data collectively from memory.
● Restrictions
• The address mapping of flash memory and the endian method in this mode are different from those in
Flash programmer programming mode.
• Note also that, in this mode, you cannot program command/data into flash memory.
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CHAPTER 17 FLASH MEMORY
17.3 Explanation of Flash Memory Operation
MB91490 Series
■ FR-CPU Programming Mode (Read/Write in 16 Bits)
In this mode, the CPU can erase or program data. The CPU cannot access a word (32 bits) of data
collectively so that program in flash memory cannot be executed during this mode.
● Specification method of mode
• This mode is established when the "WE" bit of the FLCR register is set to "1".
• The "WE" bit is set to "0" after a reset is cancelled during CPU operation. To specify this mode, write
"1" to the bit. It returns to ROM mode when the WE bit becomes "0" by rewriting "0" to this bit or
generating reset.
• When the RDY bit of the FLCR register is "0", the WE bit cannot be rewritten. Rewrite the WE bit after
confirming the RDY bit became "1".
● Operation content
• When reading a flash memory area, the CPU can read a half-word (16 bits) of data collectively from.
• You can start the automatic algorithm by programming a command into flash memory. You can erase
data from or program data into flash memory by starting the automatic algorithm. For details on the
automatic algorithm, see Sections "17.4 Flash Memory Automatic Algorithms".
● Restrictions
• The address mapping of flash memory and the endian method in this mode are different from those in
ROM programmer programming mode.
• The data read by word (32 bits) length is prohibited in this mode.
■ Automatic Algorithm Execution States
When CPU programming mode starts the automatic execution algorithm, the operation of the automatic
execution algorithm can be read by internal ready/busy signal (RDY/BUSYX). This ready/busy signal level
can be read as RDY bit of the FLCR register.
When the RDY bit is "0", write or erase by an automatic algorithm is done. Therefore, a new write or the
erase command cannot be accepted. And, the data read from the Flash memory address cannot be done.
The data read when the RDY bit is "0" is a hardware sequence flag that shows the status of the Flash
memory.
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CHAPTER 17 FLASH MEMORY
17.4 Flash Memory Automatic Algorithms
17.4
MB91490 Series
Flash Memory Automatic Algorithms
This section details the command sequence for flash memory automatic algorithms, the
method of checking their execution status, and programming/erasing flash memory.
■ Overview of Flash Memory Automatic Algorithms
There are four types of commands to invoke their respective flash memory automatic algorithms: Read/
Reset, Program, Chip Erase, and Sector Erase. For the Sector Erase command, it is possible to control the
suspending and resuming of its execution.
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CHAPTER 17 FLASH MEMORY
17.4 Flash Memory Automatic Algorithms
MB91490 Series
17.4.1
Command Sequence
This section explains command sequence to start the automatic algorithm.
■ Command Sequence of Automatic Algorithm
To start the automatic algorithm, program a half-word (16 bits) of data into flash memory continuously for
once to six times. That is called the commands. The flash memory is reset to the read mode if invalid
addresses and data are programmed or addresses and data are programmed in a wrong order.
Table 17.4-1 list the commands used for flash memory write/erase.
Do the writing data as half word (16 bits) data to write with FR-CPU. (The address has described the
address of CPU mode.)
Table 17.4-1 Command Sequence Table
Command
sequence
Bus
1st bus write cycle 2nd bus write cycle 3rd bus write cycle
write
access Address
Data
Address Data Address
Data
4th bus write cycle 5th bus write cycle
6th bus write
cycle
Address
Data
Address
Data
Address
Data
Read/Reset
1
FXXXXH
F0F0H
RA
RD
--
--
--
--
--
--
--
--
Read/Reset
4
F5557H
AAAAH
FAAABH
5555H
F5557H
F0F0H
RA
RD
--
--
--
--
Write
program
4
F5557H
AAAAH
FAAABH
5555H
F5557H
A0A0H
PA
PD
--
--
--
--
Chip erase
6
F5557H
AAAAH
FAAABH
5555H
F5557H
8080H
F5557H
AAAAH
FAAABH
5555H
F5557H
1010H
Sector erase
6
F5557H
AAAAH
FAAABH
5555H
F5557H
8080H
F5557H
AAAAH
FAAABH
5555H
SA
3030H
Sector erase
temporary stop
Erasing sectors is temporary stopped by specifying the address = FXXXXH, data = B0B0H.
Sector erase restart
Erasing sectors is resumed after being temporary stopped by specifying the address = FXXXXH, data = 3030H.
continuous
mode
3
F5557H
AAAAH
FAAABH
5555H
F5557H
2020H
--
--
--
--
--
--
continuous
Write
2
FXXXXH
A0A0H
PA
PD
--
--
--
--
--
--
--
--
continuous
mode reset
2
FXXXXH
9090H
FXXXXH
F0F0H
or
0000H
--
--
--
--
--
--
--
--
RA: Read address
PA: Writing address
SA: Sector address (Specify address 4n+2 or 4n+3)
RD: Read data
PD: Write data
■ Read/Reset
The flash memory is set to the read/reset mode.
The flash memory remains in the read state until another command is input.
The flash memory is set to the read/reset mode automatically when the power is turned on. In this case, no
command is required to read data.
To return to the read mode when the timing limit is exceeded, issue a read/reset command sequence. Data
is read from flash memory in the read cycle.
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■ Write Program
In CPU programming mode, programming is performed in half-words. Programming requires four bus
operations. The command sequence has two "unlock" cycles, followed by a programming setup command
and a programming data cycle. Programming into memory is started in the last programming cycle.
Once the automatic programming algorithm command sequence is executed, the flash memory does not
require further external control. The flash memory automatically generates an internally produced
appropriate programming pulse to verify the margins of programmed cells. The automatic programming
operation finishes when bit7 data matches the data written into this bit by the data polling function (See ■
Hardware Sequence Flag in section "17.4.2 Confirming Automatic Algorithm Execution States").
Afterward, the operation returns to the read mode and does not accept writing addresses any more.
Accordingly, the flash memory demands the next valid address. In this way, data polling indicates that
memory is being programmed.
During programming, any command programmed into flash memory is ignored. If a hardware reset is
activated during programming at an address, the data at that address is not guaranteed. Programming is
allowed in any order of addresses and beyond the boundaries of sectors. Data "0" cannot be returned to data
"1" by writing. If data "1" is programmed over data "0", either the data polling algorithm determines that
the element is defective or data "1" apparently looks as if it were programmed.
When the data is read in read/reset mode, however, it remains as "0". Data "0" can be updated to data "1"
only by erasing.
■ Chip Erasing
Chip erasure (erasing all of the sectors collectively) is performed by accessing flash memory six times.
Two "unlock" cycles come first, then a "setup" command is programmed soon. Another two "unlock"
cycles are inserted prior to the chip erase command.
Before chip erasing, the user need not perform programming to flash memory. During execution of the
automatic erase algorithm, the flash memory automatically verifies its cells by programming patterns of 0s
(preprogramming) before erasing all the cells. During preprogramming, the flash memory requires no
external control.
Automatic erasure is started by programming in the command sequence and terminates when bit7 is set to
"1", when the flash memory returns to the read mode. The chip erase time is "sector erase time  the
number of all sectors + chip program (preprogram) time".
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17.4 Flash Memory Automatic Algorithms
■ Sector Erasing
Sector erasure is performed by accessing flash memory six times. Two "unlock" cycles come first, then a
"setup" command is programmed soon. Another two "unlock" cycles are inserted, then the sector erase
command is input in the sixth cycle to start erasing a sector. During a time-out period of 50 s after the last
sector erase command is programmed, the next sector erase command can be accepted.
The erasing of multiple sectors can be accepted at the same time by programming six bus cycles as
described above. This sequence is executed by programming the sector erase command (3030H)
continuously at the addresses of the sectors to be erased at the same time. When the 50 s time-out after the
last sector erase command is programmed expires, the flash memory starts erasing the sectors. To erase
multiple sectors at the same time, therefore, the sector erase command for each of the sectors must be input
within a time-out period of 50 s, or the command may not be accepted if it expires. You can check
whether the successive sector erase command is valid by monitoring bit3 (See ■ Hardware Sequence Flag
in section "17.4.2 Confirming Automatic Algorithm Execution States").
If any command other than the sector erase command and erasure pause command is input in a time-out
period, the flash memory is reset to the read mode and ignores the preceding command sequence. In this
case, the relevant sector is erased completely by erasing it again. Sector addresses can be input to the sector
erase buffer for any number of sectors in any combination. For erasing sectors, the user does not have to
program into flash memory in advance. The flash memory automatically programs (preprograms) into all
the cells in the sectors to be erased. Note also that the erasing of sectors has no effect on any other sector.
During these operations, the flash memory requires no external control.
Automatic sector erasure is started after a time-out period of 50 s after the last sector erase command is
programmed and terminates when bit7 is set to "1". The flash memory returns to the read mode. Any other
command is ignored. Data polling works for any address in the sectors erased. The multiple-sector erase
time is "(sector erase time + sector program (preprogram) time)  the number of sectors erased".
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■ Sector Erasure Pause Command
The sector erasure pause command allows the user to suspend the flash memory automatic algorithm
during erasure of sectors in order to read data from or program data into other sectors. This command is
valid only during sector erasure; it is ignored during chip erasure or programming. The sector erasure pause
command (B0B0H) is valid only during the period of sector erasure, including the sector erasure time-out
period after the sector erase command (3030H). When this command is input during the time-out period,
the flash memory terminates the time-out and suspends erasure. The flash memory restarts erasure when
the erasure restart command is programmed. The erasure pause and restart commands can be input with any
address.
When the erasure pause command is input during sector erasure, it takes a maximum of 20 s for the flash
memory to pause erasure. When the flash memory enters the erasure pause mode, the ready/busy output
and bit7 output "1", and bit6 stops toggling. You can check whether erasure is suspended by inputting the
sector address being erased to monitor the values read from bit6 and bit7. An attempt to program another
erasure pause command is ignored. When erasure is paused, the flash memory enters the erasure pause read
mode. Data reading in this mode is the same as typical data reading, except that it is effective for sectors
containing data not being erasure-paused. In erasure pause read mode, bit2 toggles for continuous reading
from the sector being erasure-paused.
In erasure pause read mode, the user can program into flash memory by programming the command
sequence. This program mode is the erasure pause program mode. Programming in this mode is the same as
normal writing in bytes, except that it is effective for sectors containing data not being erasure-paused. In
erasure pause program mode, bit2 toggles for continuous reading from the sector being erasure-paused. The
erasure pause state can be detected by checking the erasure pause bit (bit6).
Note that bit7 must be read for the address being programmed while bit6 can be read for any address. To
restart sector erasure, input the restart command (3030H). Another restart command is ignored if input at
this point of time. In contrast, the erasure pause command can be input after the flash memory restarts
erasure.
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17.4.2
Confirming Automatic Algorithm Execution States
As this flash memory uses the automatic algorithm for program/erase flow, it has a
piece of hardware to inform internal operating state of the flash memory or the
completion of its operation.
This automatic algorithm enables confirmation of the operating state of the built-in flash
memory using following hardware sequences.
■ Ready/Busy Signal (RDY/BUSYX)
Besides the hardware sequence flag, the Flash memory has the ready/busy signal as a method of informing
whether an internal automatic algorithm is now executing or ended.
This ready/busy signal can be connected to the Flash memory interface circuit, and be read as RDY bit of
the Flash memory status register.
When the read value of the RDY bit is "0", the Flash memory is now writing or erasing. At this time,
neither the writing command nor the erase command are accepted. When the read value of the RDY bit is
"1", the flash memory is in the state of the read/write/erase operation waiting.
■ Hardware Sequence Flag
Figure 17.4-1 shows the structure of the hardware sequence flag.
Figure 17.4-1 Structure of Hardware Sequence Flag
For half-word read
bit15
8 7
(Undefined)
0
Hardware sequence flag
7
For byte read (only odd-numbered addresses)
0
Hardware sequence flag
(For half-word/byte access)
DPOLL
TOGGLE
TLOVER
Undefined
SETIMR
TOGGL2
Undefined
Undefined
Note:
The word reading is prohibited. Use only the FR-CPU programming mode.
A hardware sequence flag is obtained as data by reading an address (an odd-numbered address during byte
access) of flash memory during execution of the automatic algorithm. The obtained data contains five
effective bits, each of which indicates a state of the automatic algorithm.
It doesn't have the meaning about these flags at the FR-CPU ROM mode. Only in the FR-CPU
programming mode, execute the half word read or the byte read.
Table 17.4-2 lists hardware sequence flag states.
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Table 17.4-2 Hardware Sequence Flag Status List
State
DPOLL
Automatic Programming Operation
Inverted data
Toggle
0
0
1
0
Toggle
0
1
Toggle
1
1
0
0
Toggle*1
Data
Data
Data
Data
Data
Inverted data Toggle*2
0
0
1 *3
Inverted data
Toggle
1
0
1
0
Toggle
1
1
*4
0
Toggle
1
1
*4
Automatic erasing Operation
During
execution
Reading (Sector being erased)
Erasing
pause
mode
Reading (Sector unerased)
Programming (Sector unerased)
Automatic erasing Operation
Time limit is
Temporary erase stop mode
exceeded
Write operation at the temporary erase stop
TOGGLE TLOVER SETIMR TOGGL2
*1: TOGGL2 operates as a toggle at the time of the continuous read from the temporary erase stop sector.
*2: TOGGLE operates as a toggle even at continuous reading time from whatever address
*3: When the written address is read at writing the temporary erase stop, TOGGL2 becomes "1". However, TOGGL2
operates as a toggle at the time of the continuous reading from the temporary erase stop sector.
*4: When TLOVER is "1" (over the time limit), TOGGL2 operate as a toggle to a continuous reading to the sector in the
write/erase, and does not operate as a toggle to read to other sectors.
Each bit in the table is explained below.
[bit7] :DPOLL
: Data polling
[bit6] :TOGGLE : Toggle bit
[bit5] :TLOVER : Time limit excess
[bit3] :SETIMR
: Sector erase timer
[bit2] :TOGGL2
: Toggle bit 2
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The following describes the function of each bit:
[bit7] DPOLL: Data polling flag
The data polling flag uses a data polling function to indicate that the execution of the automatic
algorithm is currently in progress or completed.
• During automatic programming
When the flash memory is read during execution of the automatic program algorithm, it outputs the
inverted version of data finally written to bit7 without accessing the address located by the address
signal. When the flash memory is read-accessed upon completion of the automatic program algorithm,
it outputs bit7 of the data read from the address located by the address signal.
• During chip/sector erasure
When the flush memory is read during execution of erasure or erasure sector algorithm, it outputs "0"
from the sector currently being erased for sector erasure. For chip erasure, it output "0" regardless the
current address. In the same way, 1 is output when it ends.
• During sector erasure suspended
When the flash memory is read during suspended sector erasure, it outputs "1" if the address located by
the address signal belongs to the sector being erasured. If the address does not belong to the sector
being erased, the flash memory outputs bit7 of data read at the address located by the address signal. By
referring this bit along with bit6 described below as the toggle bit, you can check whether sector erasure
is currently being suspended and which sector is being erased.
Note:
Any read access to the specified address is ignored during the startup of the automatic algorithm. In
relation to reading data, the data polling flag must be completed before data can be output from any
other bit.
Therefore, upon completion of the automatic algorithm, data should be read after the read access
which confirms the completion of the data polling.
[bit6] TOGGLE: Toggle bit flag
Like the data polling flag, the toggle bit flag uses a toggle bit function mainly to indicate that the
execution of the automatic algorithm is currently in progress or completed.
• During programming chip sector erasure
When the flash memory is continuously read during execution of the automatic program or chip sector
erase algorithm, it outputs the result of toggling between "1" and "0" for each read operation without
accessing the address located by the address signal. When the automatic program or chip sector erase
algorithm terminates, the flash memory stops toggling bit6 for continuous read access and outputs bit6
(DATA:6) of data read at the address located by the address signal.
• During sector erasure suspended
When the flash memory is read during suspended sector erasure, it outputs "1" if the address located by
the address signal belongs to the sector being erasured. If the address does not belong to the sector
being erased, the flash memory outputs bit6 of data read at the address located by the address signal.
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Reference:
When the sector that tries to be written is a sector that the rewriting protection is done at writing, the
toggle operation is ended without rewriting data after the toggle of about 2ms operates. When the
sector that tries to be written is protected from rewriting in the erasing, it returns to the state of read/
reset without rewriting data after the toggle of about 100ms operates.
[bit5] TLOVER: Timing limit exceeded flag
• During automatic programming/chip sector erasure
Read-accessing after a write operation or the startup of the automatic algorithm for chip sector erasure
operation outputs "0" if the specified time (time required for write/erase operation) has not been
exceeded, or "1" if the time has been exceeded.
As this is not affected by whether the automatic algorithm is currently being executed or completed,
you can determine if the write/erase operation has been successful. In other words, you can determine
that the write operation has been unsuccessful, if the automatic algorithm is still being executed by the
data polling function or the toggle bit function when this flag has output "1".
For example, a failure will occur if an attempt is made to write "1" to the flash memory address which
contains "0". In this case, the flash memory will be locked; therefore, the automatic algorithm will not
be completed.
On rare occasions, it can be completed properly as if "1" had been written successfully. As a
consequence, valid data cannot be output from the data polling flag. Also, the toggle bit flag does not
suspend the toggle operation, resulting in an exceeded time limit. Then, the timing limit exceeded flag
outputs "1".
Note that this indicates that the flash memory was not used correctly rather than any defect with the
flash memory. If this event occurs, the reset command should be executed.
[bit3] SETIMR: Sector erase timer flag
The sector erasure timer flag indicates whether or not the sector erasure wait period has passed after the
execution of the sector erasure command.
• During sector erasure
When a read access is performed after the execution of the sector erasure command, the flash memory
outputs "0" within the sector erasure wait period, or "1" after that period, rather than accessing the
address specified by the address signal of the sector which has issued the command.
If this flag is "1" when the data polling function or the toggle bit function is indicating that the erase
algorithm is currently being executed, that means that an internally controlled erasure operation has
started. After that, any command other than the ones for programming the sector erasure code or
suspending the erasure is ignored until the erasure is completed.
If this flag is "0", the flash memory accepts the additional sector deletion code to be written. To confirm
this, it is advisable to check the state in this flag by software before programming succeeding sector
erase code. If 1 is shown at the 2nd status check, the additional sector deletion code may not have been
accepted.
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• During sector erasure
When reading is carried out while sector deletion is suspended, the flash memory outputs 1 if the
address indicated by the address signal belongs to the sector during deletion. If the address does not
belong to the sector being erased, the flash memory outputs bit3 of data read at the address located by
the address signal.
[bit2] TOGGL2: Toggle bit flag 2
• During sector erasure
This toggle bit is used, along with another toggle bit flag of bit6, to detect whether the flash memory is
executing automatic erasure and whether erasure is currently being suspended.
• During programing/chip sector erasure
Same toggle operation as the toggle bit (bit2) is performed.
• During sector erasure suspended
If the flash memory is under deletion suspension reading mode, bit2 operates the toggle by continuously
reading addresses from the sector in which deletion is suspended. If the flash memory is under deletion
suspension programing mode, 1 is read by bit2 by continuously reading addresses from the sector in
which deletion is not suspended. Unlike bit2, bit6 toggles only during normal programming, erasure, or
erasure pause programming.
Reference:
Bit2 and bit6 are used at the same time to detect the reading the temporary erase stop mode. (As for
bit2, the toggle operates. But as for bit6, the toggle doesn't operate.)
In addition, bit2 is used to detect the erasing sector. As for bit2, the toggle operates to read from the
erasing sector, when the Flash memory is on the erase operating.
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17.5
MB91490 Series
Details of Programming and Erasing Flash Memory
This section describes the procedures to issue the Read/Reset, Program, Chip Erase,
Sector Erase, Sector Erase Suspend, and Sector Erase Resume commands to flash
memory for invoking their respective automatic algorithms to execute their operations.
■ Overview of Programming and Erasing Flash Memory
The following operations can be performed for flash memory by executing their respective automatic
algorithms invoked by carrying out the path write cycles of the command sequences:
• Read/Reset
• Program
• Chip Erase
• Sector Erase
• Sector Erase Suspend
• Erase Resume
Each series of path write cycles must be executed continuously. The completion of each automatic
algorithm can be checked, for example, by the data polling function. When the automatic algorithm
terminates normally, the flash memory returns to the read/reset state.
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17.5.1
Read/Reset State
This section describes the procedure for issuing the Read/Reset command to place the
flash memory in the read/reset state.
■ Placing the Flash Memory in the Read/Reset State
To place the flash memory in the read/reset state, issue the Read/Reset command in the command sequence
table continuously to the target sector in flash memory.
There are two different command sequences available to the Read/Reset command: one for a single bus
operation and the other for three bus operations. The two command sequences are basically the same.
The read/reset state is the default state of the flash memory. The flash memory always enters the read/reset
state when the power is turned on and upon normal termination of a command. In the read/reset state, the
flash memory is waiting for input of another command.
In the read/reset state, data can be read by normal read access. Like masked ROM, flash memory is
program-accessible from the CPU. The Read/Reset command is therefore not required for reading data
normally. Use the command mainly to initialize an automatic algorithm, for example, when the command
has failed to terminate normally for some reason.
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17.5.2
MB91490 Series
Programming Data
This section describes the procedure for issuing the Program command to program
data into flash memory.
■ Programming Data into Flash Memory
To invoke the automatic algorithm for programming data into flash memory, issue the Program command
in the command sequence table continuously to the target sector in flash memory. Upon completion of a
data write to the target address in the fourth cycle, the automatic algorithm is activated to start automatic
programming.
■ Addressing
The write address specified in the programming data cycle must be an even-numbered address.
Programming fails if an odd-numbered address is specified. That is, programming must be performed in
halfwords to even-numbered addresses.
Although programming can be performed in any order of addresses and beyond a sector boundary, each
Program command can write only one halfword of data.
■ Notes on Programming Data
Programming cannot restore data from "0" to "1".
If you attempt to write data "1" to data "0", the data polling algorithm or toggle operation does not
terminate, the flash memory device is regarded as defective, and the specified programming time is
exceeded, resulting in an error detected by the timing limit excess flag. Otherwise, the data "1" appears to
have been written normally. If the data is then read in the read/reset state, however, the value will still be
"0". Only erasing data "0" can set it to "1".
During execution of automatic programming, all commands are ignored. Note that, if a hardware reset
occurs during programming, the data at the address currently being programmed is not guaranteed.
■ Flash Memory Programming Procedure
Figure 17.5-1 shows an example of the flash memory programming procedure.
The states of the automatic algorithm in flash memory can be checked by referencing the hardware
sequence flags. In the example, the data polling flag (DPOLL) is used to determine whether programming
has been completed.
The data to be used for checking the flag is read from the last write address.
Since the data polling flag (DPOLL) changes the setting simultaneously with the timing limit excess flag
(TLOVER), the data polling flag (DPOLL) must be checked again even when the timing limit excess flag
(TLOVER) contains "1".
Similarly, the toggle bit flag (TOGGLE) stops toggle operation the moment the timing limit excess flag
(TLOVER) is set to "1". The toggle bit flag (TOGGLE) must therefore be checked again.
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Figure 17.5-1 Example of Flash Memory Programming Procedure
Start of programming
FLCR: Enable flash programming
by WE (bit1)
Program command sequence
AAAAH
F5557H
5555H
FAAABH
A0A0H
F5557H
Write address
Data written
Read internal address
Data polling
(DPOLL)
Next address
Data
Data
0
Timing limit
(TLOVER)
1
Read internal address
Data
Data polling
(DPOLL)
Data
Write error
Last address
NO
YES
FLCR: Disable flash programming
by WE (bit1)
Check with hardware
sequence flags
End of programming
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17.5 Details of Programming and Erasing Flash Memory
17.5.3
MB91490 Series
Erasing Data (Chip Erase)
This section describes the procedure for issuing the Chip Erase command to erase all
data from flash memory.
■ Erasing Data from Flash Memory (Chip Erase)
To erase all data from flash memory, issue the Chip Erase command in the command sequence table
continuously to the target sectors in flash memory.
The Chip Erase command is executed in six bus operations.
The chip erase operation starts upon completion of the write in the sixth cycle. The user does not have to
program into flash memory before performing chip erasure. During execution of the automatic erase
algorithm, the flash memory performs verification by automatically writing "0"s to all cells before erasing
them.
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17.5 Details of Programming and Erasing Flash Memory
MB91490 Series
17.5.4
Erasing Data (Sector Erase)
This section describes the procedure for issuing the Sector Erase command to erase
one or more arbitrary sectors in flash memory. The Sector Erase command can erase
data from flash memory in sector units. It allows two or more sectors to be specified at
the same time.
To erase an arbitrary sector in flash memory, issue the Sector Erase command in the
command sequence table continuously to the target sector in flash memory.
■ Specifying One or More Sectors
The Sector Erase command is executed in six bus operations. The sector erase wait period of 50
microseconds is started by writing the sector erase code (3030H) to one even-numbered address accessible
in the target sector in the sixth cycle.
To erase more than one sector, continue the above sequence by writing further sector erase codes (3030H)
to the addresses in the sectors to be erased.
■ Notes on Specifying Multiple Sector
Erasing sectors starts at the end of the sector erase wait period of 50 microseconds after writing the last
sector erase code. That is, to erase more than one sector at a time, the address in each sector to be erased
and the sector erase code (in the sixth cycle of the command sequence) must be input within 50
microseconds after writing the sector erase code for the previous sector. Sectors specified after this time
may not be accepted.
Whether subsequent sector erase code writes are effective or not can be monitored by using the sector erase
timer (hardware sequence flag (SETIMR)). Note that the address to read the Sector Erase command must
point to the sector to be erased.
■ Sector Erasing Procedure
The state of the automatic algorithm in flash memory can be checked by referencing hardware sequence
flags. Figure 17.5-2 shows an example of the flash memory sector erasing procedure.
In the example, the toggle bit flag (TOGGLE) is used to determine whether sector erasure has been
completed.
Note that the data to be used for checking the flag is read from the sector to be erased.
Since the toggle bit flag (TOGGLE) stops toggle operation the moment the timing limit excess flag
(TLOVER) is set to "1", the toggle bit flag (TOGGLE) must be checked again even when the timing limit
excess flag (TLOVER) contains "1".
Similarly, as the data polling flag (DPOLL) changes the setting simultaneously with the timing limit excess
flag (TLOVER), the data polling flag (DPOLL) must also be checked again.
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Figure 17.5-2 Example of Sector Erasing Procedure
Start of erasure
Sector erase
timer value
0
FLCR: WE(bit1) Enable flash
memory erasure
1
Erase command sequence
AAAAH
F5557H
FAAABH
5555H
F5557H
8080H
F5557H
AAAAH
FAAABH
5555H
Write code (3030H) to sector to be erased
YES
Any other sector to be erased?
NO
Read internal address
Read internal address 1
Next sector
Read internal address 2
Toggle bit (TOGGLE)
Data 1 = Data 2?
YES
NO
Check with hardware
sequence flags
0
Timing limit
(TLOVER)
1
Read internal address 1
Read internal address 2
NO
Toggle bit (TOGGLE)
Data 1 = Data 2?
YES
End of erasure
Last sector erased?
NO
YES
FLCR: WE (bit1) Disable flash
memory erasure
End of erasure
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17.5.5
CHAPTER 17 FLASH MEMORY
17.5 Details of Programming and Erasing Flash Memory
Suspending Sector Erasure
This section describes the procedure for issuing the Sector Erase Suspend command
to suspend erasing one or more sectors in flash memory. The command allows data to
be read from sectors currently not being erased.
■ Suspending Sector Erasure in Flash Memory
To suspend erasing sectors in flash memory, issue the Sector Erase Suspend command in the table in Table
17.4-1 to flash memory.
The Sector Erase Suspend command suspends sector erasure in process, allowing data to be read from
sectors currently not being erased. When sector erasure is being suspended, such sectors can only be read
from; they cannot be written to. The command is valid only during the period of sector erasure including
the erase wait time; it is ignored during chip erasure or programming.
If the Sector Erase Suspend command is input during a sector erase wait period, the flash memory
terminates the wait period immediately to halt erasure and enters the erase suspended state. If the command
is input during sector erase operation after a sector erase wait period, the flash memory enters the erase
suspended state after a maximum of 20 s. Issue the Sector Erase Suspend command at least 20 s after
issuing the Sector Erase command or Sector Erase Resume command.
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17.5 Details of Programming and Erasing Flash Memory
17.5.6
MB91490 Series
Resuming Sector Erasure
This section describes the procedure for issuing the Sector Erase Resume command to
resume suspended erasure of one or more sectors in flash memory.
■ Resuming Sector Erasure in Flash Memory
To resume suspend sector erasure, issue the Sector Erase Resume command in Table 17.4-1 to flash
memory.
The Sector Erase Resume command resumes sector erasure suspended by the Sector Erase Suspend
command. The Sector Erase Resume command is executed by writing the erase resume code (3030H) to
any address in the flash memory area.
Note that the Sector Erase Resume command is ignored if issued during sector erasure in process.
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CHAPTER 17 FLASH MEMORY
17.6 Flash Security Feature
MB91490 Series
17.6
Flash Security Feature
The flash security feature provides possibilities to protect the content of the flash
memory.
■ Overview
If the protection code of 0001H is written in the security bit of flash memory, access to the flash memory is
restricted. Once the flash memory is protected, performing the chip erase operation only can unlock the
function otherwise read/write access to the flash memory from any external pins is not generally possible.
This function is suitable for applications requiring security of self-containing program and data stored in
the flash memory.
Address of the security bit is 000F8004H.
■ Setting Security
The security is set after the reset factors are generated (external resets (INITX), low voltage detection reset,
watchdog reset, and software reset) by writing the protection code 0001H in security bit.
■ Releasing Security
After performing the chip erase, all the reset factors are generated.
■ Operation with Security Enabled
Read: Invalid data (all "1") is read.
Write: No writing can be performed.
■ Other Information
• For setting the general-purpose parallel programmer, see the specification of the general-purpose
parallel programmer to be used.
• Writing the protection code is generally recommended to take place at the end of the flash
programming. This is to avoid unnecessary protection during the programming.
Notes:
• Security bit is allocated in the flash memory area. Writing the protection code 0001H in security bit
makes security enable. Therefore, do not write 0001H in the address when the security feature is
not used.
• Specifying sector of flash memory to set security for each sector cannot be performed. Security
feature is only for all flash memory area.
• When security enabled, the obstruction analysis of the flash memory cannot be performed.
• Acess to Flash memory using Flash security function is limited in parallel programing mode and
flash serial program mode, but not limited in single chip mode.
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CHAPTER 17 FLASH MEMORY
17.7 Notes on Flash Memory Programming
17.7
MB91490 Series
Notes on Flash Memory Programming
This section provides notes on programming into flash memory.
■ Notes on Flash Memory Programming
Take the following precautions when reprogramming flash memory using a program:
• If a reset occurs during reprogramming of flash memory, the data being written is not guaranteed.
• In flash memory reprogramming mode (WE = 1 in the FLCR register), do not run any program in flash
memory. If an interrupt vector table resides in flash memory in that mode, do not generate an interrupt.
Doing either causes the program to run out of control as it fails to fetch normal values from flash
memory.
• To check whether programming into flash memory has been completed, reference the TOGGLE flag as
well as the RDY flag.
If flash memory is defective, the RDY flag that indicates the completion of programming is not set. If
referencing only the RDY flag, therefore, the program will enter an infinite loop.
• In flash memory reprogramming mode (WE = 1 in the FLCR register), do not enter any low-power
consumption mode.
• Do not write-access the flash memory with WE = 0 in the FLCR register.
• Do not write-access the flash memory continuously with WE = 1 in the FLCR register. In that case, be
sure to insert at least two "NOP" instructions.
[Example] Write commands (a command sequence) to flash memory. => Read flash memory.
ldi
#0xAAAA,
r0
ldi
#0x5555,
r1
ldi
#0xF5557,
r6
ldi
#0xFAAAB,
r7
ldi
#0xA0A0,
r8
ldi
# PA,
r2
ldi
# PD,
r3
sth
r0,@r6
NOP
// Be sure to insert at least two NOP instructions.
NOP
// Be sure to insert at least two NOP instructions.
sth
NOP
// Be sure to insert at least two NOP instructions.
NOP
// Be sure to insert at least two NOP instructions.
sth
r8,@r6
NOP
// Be sure to insert at least two NOP instructions.
NOP
// Be sure to insert at least two NOP instructions.
sth
NOP
638
r1,@r7
r3,@r2
// Be sure to insert at least two NOP instructions.
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CHAPTER 17 FLASH MEMORY
17.7 Notes on Flash Memory Programming
MB91490 Series
NOP
// Be sure to insert at least two NOP instructions.
• In CPU mode, write access to flash memory is allowed only in halfwords.
Do not write-access the flash memory in bytes.
• The value read immediately after writing to flash memory cannot be guaranteed. Before reading data
after writing, be sure to insert a dummy read as follows:
sth
r0,@rl
// Write to flash memory.
lduh
@r2,r4
// Dummy read
lduh
@r3,r4
// Read polling data.
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CHAPTER 17 FLASH MEMORY
17.7 Notes on Flash Memory Programming
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MB91490 Series
CM71-10155-2E
CHAPTER 18
LOW VOLTAGE DETECTION
INTERRUPT / RESET
This chapter explains the function and the operation of
the low voltage detection interrupt / Reset.
18.1 Overview of the Low Voltage Detection Interrupt / Reset
18.2 Block Diagram of Low Voltage Detection Interrupt / Reset
18.3 Low Voltage Detection Interrupt Register
18.4 Detailed Explanation for Registers of Low Voltage Detection
Interrupt
18.5 Operation of Low Voltage Detector 0
18.6 Operation of Low Voltage Detection Interrupt
18.7 Operation of Low Voltage Detector 1
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CHAPTER 18 LOW VOLTAGE DETECTION INTERRUPT / RESET
18.1 Overview of the Low Voltage Detection Interrupt / Reset
18.1
MB91490 Series
Overview of the Low Voltage Detection Interrupt / Reset
Two Low Voltage Detection circuits (Low Voltage Detector 0 and Low Voltage Detector
1) are present in MB91490 series. Low Voltage Detection Interrupt circuit detects VCC
low voltage condition and generates interrupt. Low Voltage Detection Reset circuit
detects VCC low voltage condition and generates system initialization reset.
■ Low Voltage Detection Interrupt / Reset functions
Table 18.1-1 shows the Low Voltage Detection Interrupt / Reset functions .
Table 18.1-1 Low Voltage Detection Reset/Interrupt Function
Watch voltage
Low voltage
detection
interrupt
(with Low
Voltage
Detector 0)
Low voltage
detection
reset
(with Low
Voltage
Detector 1)
642
Operation
Other operation
Purpose
–
Interrupt is generated as
warning
–
Detect
VCC 3.70 ± Interrupt detection flag
0.30V
is set to "1".
Release
VCC  3.75 ±
0.30V
–
Interrupt detection flag
can be cleared by software
Detect
VCC 3.00 ±
0.24V
All pins set to "Hi-Z".
System initialization
reset is generated
–
Release
VCC 3.05 ±
0.24V
System initialization
reset is released
–
FUJITSU SEMICONDUCTOR LIMITED
Disconnect MCU electrically from external equipment. It prevents
influence to other devices.
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CHAPTER 18 LOW VOLTAGE DETECTION INTERRUPT / RESET
18.2 Block Diagram of Low Voltage Detection Interrupt / Reset
MB91490 Series
18.2
Block Diagram of Low Voltage Detection Interrupt / Reset
This section provides block diagram of Low Voltage Detection Interrupt / Reset.
■ Block Diagram of Low Voltage Detection Interrupt
Figure 18.2-1 Block Diagram of Low Voltage Detection Interrupt
Interrupt request
Internal data bus
16
9
16
16
Interrupt enable register
Gate
Source F/F
Edge detection circuit
8
INT0 to INT6
NMIX
External interrupt source register
Vcc
External interrupt request level setting register
Low Voltage Detector 0 *
* : The low voltage detection interrupt is performed by using the external interrupt function.
Figure 18.2-2 Block Diagram of Low Voltage Detection Reset
Hi-Z Pin control
FR CPU
reset control *
Vcc
Low Voltage Detector 1
INIX
Pin
* : The initial values of standby control register STCR: OS1, OS0 vary
depending on SINIT generation factors.
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CHAPTER 18 LOW VOLTAGE DETECTION INTERRUPT / RESET
18.3 Low Voltage Detection Interrupt Register
18.3
MB91490 Series
Low Voltage Detection Interrupt Register
This section describes the configuration and functions of low voltage detection
interrupt registers.
■ List of Low Voltage Detection Interrupt Registers
Figure 18.3-1 List of Registers of Low Voltage Detection Interrupt
External interrupt source register
EIRR0
Address
bit7
bit6
bit5
ER7 * ER6
ER5
00000040H
R/W
R/W
R/W
bit4
ER4
R/W
bit3
ER3
R/W
bit2
ER2
R/W
bit1
ER1
R/W
bit0
ER0
R/W
Initial value
00000000B
Interrupt enable register
ENIR0
Address
bit7
bit6
EN7 * EN6
00000041H
R/W
R/W
bit4
EN4
R/W
bit3
EN3
R/W
bit2
EN2
R/W
bit1
EN1
R/W
bit0
EN0
R/W
Initial value
00000000B
External interrupt request level setting register
ELVR0
Address
bit15
bit14
bit13
bit12
LB7 * LA7 *
LB6
LA6
00000042H
R/W
R/W
R/W
R/W
bit11
LB5
R/W
bit10
LA5
R/W
bit9
LB4
R/W
bit8
LA4
R/W
Initial value
00000000B
bit3
LB1
R/W
bit2
LA1
R/W
bit1
LB0
R/W
bit0
LA0
R/W
Initial value
00000000B
ELVR0
Address
00000043H
bit7
LB3
R/W
bit6
LA3
R/W
bit5
EN5
R/W
bit5
LB2
R/W
bit4
LA2
R/W
R/W: Readable/writable
*
: There bits are used for the low voltage detection interrupt function
Note:
644
The low voltage detection interrupt register uses the interrupt enable register (ENIR0:EN7), the external
interrupt source register (EIRR0: ER7), and the external interrupt request level setting register (ELVR0:
LB7, LA7).
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CHAPTER 18 LOW VOLTAGE DETECTION INTERRUPT / RESET
18.4 Detailed Explanation for Registers of Low Voltage Detection Interrupt
MB91490 Series
18.4
Detailed Explanation for Registers of Low Voltage
Detection Interrupt
This section explains the configuration and functions of registers used by Low Voltage
Detection Interrupt.
■ Interrupt Enable Register (ENIR (ENIR0): ENable Interrupt Request Register)
ENIR0
Address
00000041H
bit7
EN7 *
R/W
bit6
EN6
R/W
bit5
EN5
R/W
bit4
EN4
R/W
bit3
EN3
R/W
bit2
EN2
R/W
bit1
EN1
R/W
bit0
EN0
R/W
Initial value
00000000B
R/W : Readable/writable
*
: This bit is used for the low voltage detection interrupt function
The interrupt enable register (ENIR0:EN7) controls mask of the low voltage detection interrupt request
output. Output for a low voltage detection interrupt request is enabled when "1" is written to ENIR0:EN7,
and the interrupt request is output to the interrupt controller. When "0" is written to this register, the low
voltage detection interrupt source set to the external interrupt source register (EIRR0:ER7) is hold, but an
interrupt request is not output to the interrupt controller.
Note:
The interrupt enable register of the low voltage detection interrupt uses the interrupt enable register
(ENIR0:EN7).
■ External Interrupt Source Register (EIRR (EIRR0): External Interrupt Request Register)
EIRR0
Address
00000040H
bit7
ER7 *
R/W
bit6
ER6
R/W
bit5
ER5
R/W
bit4
ER4
R/W
bit3
ER3
R/W
bit2
ER2
R/W
bit1
ER1
R/W
bit0
ER0
R/W
Initial value
00000000B
R/W : Readable/writable
*
: This bit is used for the low voltage detection interrupt function
The external interrupt source register (EIRR0:ER7) shows whether a low voltage detection interrupt request
exists when reading, and it clears the content of the flip-flop showing this request when writing. If the read
value of this EIRR0:ER7 is "1", there is a low voltage detection interrupt request. Writing "0" to this
register clears the content of the flip-flop showing the low voltage detection interrupt request. Writing "1"
to this register is invalid. "1" is read in a read operation of the read modify write (RMW) instruction.
Note:
The interrupt source register of the low voltage detection interrupt uses the external interrupt source
register (EIRR0:ER7).
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CHAPTER 18 LOW VOLTAGE DETECTION INTERRUPT / RESET
18.4 Detailed Explanation for Registers of Low Voltage Detection Interrupt
MB91490 Series
■ External Interrupt Request Level Setting Register
ELVR(ELVR0):External LeVel setting Register
External interrupt request level setting register
ELVR0
Address
bit15
bit14
bit13
bit12
LB7 * LA7 *
LB6
LA6
00000042H
R/W
R/W
R/W
R/W
ELVR0
Address
00000043H
bit7
LB3
R/W
bit6
LA3
R/W
bit5
LB2
R/W
bit4
LA2
R/W
bit11
LB5
R/W
bit10
LA5
R/W
bit9
LB4
R/W
bit8
LA4
R/W
Initial value
00000000B
bit3
LB1
R/W
bit2
LA1
R/W
bit1
LB0
R/W
bit0
LA0
R/W
Initial value
00000000B
R/W: Readable/writable
*
: There bits are used for the low voltage detection interrupt function
The external interrupt request level setting register (ELVR0:LB7,LA7) is a register to select request
detections of the low voltage detection interrupt. Even when the external interrupt source register
(EIRR0:ER7) is cleared, the low voltage detection interrupt request is set again as long as the input is an
active level.
Note:
646
Always set "00B" to the bit ELVR0:LB7,LA7.
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CHAPTER 18 LOW VOLTAGE DETECTION INTERRUPT / RESET
18.5 Operation of Low Voltage Detector 0
MB91490 Series
18.5
Operation of Low Voltage Detector 0
Low Voltage Detector 0 continuously monitor VCC voltage. When VCC drops below
detect range, low voltage signal is asserted. When VCC raise above release range, low
voltage signal is released.
■ Operation of an Low Voltage Detector 0
Figure 18.5-1 shows the low voltage detector 0 operation.
Figure 18.5-1 Low Voltage Detector 0 Operation
VCC
Release range
3.75V +/- 0.30V
Detect range
3.70V +/- 0.30V
Low voltage signal asserted
(flag bit is asserted)
Low voltage signal released
(flag bit is still asserted
unless cleared by software)
Time
■ Low Voltage Detector 0 detected
When VCC drops below detect voltage, low voltage signal is asserted and is sent to external interrupt module.
■ Low Voltage Detector 0 released
When VCC raise above release voltage, low voltage signal is released and is sent to external interrupt module.
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CHAPTER 18 LOW VOLTAGE DETECTION INTERRUPT / RESET
18.6 Operation of Low Voltage Detection Interrupt
18.6
MB91490 Series
Operation of Low Voltage Detection Interrupt
If the low voltage state is detected after setting interrupt enable register, this module
generates an interrupt request signal to the interrupt controller. For simultaneous
interrupt requests from resources, the interrupt controller determines the interrupt
request with the highest priority and generates an interrupt for it.
■ Operation of an Low Voltage Detection Interrupt
Figure 18.6-1 shows the low voltage detection interrupt operation.
Figure 18.6-1 Low Voltage Detection Interrupt Operation
Low Voltage Detection Interrupt
CPU
Interrupt controller
Resource request
ELVR
ICR yy
EIRR
Low Voltage
Detecter 0
ENIR
IL
CMP
ICR xx
CMP
ILM
■ Return from Standby
If it is not intended to wake up MCU from standby, be sure to disable low voltage detection interrupt,
before entering to standby.
■ Operating Procedure for an Low Voltage Detection Interrupt
Set up the low voltage detection interrupt as follows:
1. Clear the external interrupt source register (EIRR0:ER7).
2. Enable the interrupt enable register (ENIR0:EN7).
(Simultaneous writing of 16-bit data is supported for steps 1. and 2.)
Before setting a register for low voltage detection interrupt, you must disable the interrupt enable register.
In addition, before enabling the interrupt enable register, you must clear the external interrupt source
register. This procedure is required to prevent an interrupt source from occurring by mistake while a
register is being set or an interrupt is enabled.
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CHAPTER 18 LOW VOLTAGE DETECTION INTERRUPT / RESET
18.6 Operation of Low Voltage Detection Interrupt
MB91490 Series
■ Low Voltage Detection Interrupt Request Level
• If a low voltage detection interrupt request input is entered from low voltage detector 0 and is then
cancelled, the request to the interrupt controller remains active because a source holding circuit exists
internally.
The low voltage detector generates pulse with more than 3 machine cycles. Moreover, even if the factor
register is cleared, the interrupt request to the interrupt controller keeps being generated as long as the
interrupt input pin maintains the active level.
The external interrupt source register (EIRR0:ER7) must be cleared to cancel a request to the interrupt
controller.
Figure 18.6-2 Clearing the External Interrupt Source Register when a Level is Set
Low Voltage
Detection
Interrupt Input
Level
detection
External interrupt source register
(Source holding circuit)
Enable gate
Interrupt controller
Holds a source unless it is cleared
Figure 18.6-3 Interrupt Source and Interrupt Request to Interrupt Controller when Interrupts are Enabled
H level
Interrupt input
Interrupt request
to interrupt controller
CM71-10155-2E
Becomes inactive when the external interrupt source register is cleared
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CHAPTER 18 LOW VOLTAGE DETECTION INTERRUPT / RESET
18.6 Operation of Low Voltage Detection Interrupt
MB91490 Series
■ Notes If Restoring from STOP Status Performed Using an Low Voltage Detection Interrupt
During STOP status, low voltage detection interrupt signals that are first entered are entered asynchronously,
to enable recovery from the STOP status. The period from that STOP being released to the passage of
oscillation stabilization wait time contains a period that cannot identify the other external interrupt signal
inputs (Period b+c for Figure 18.6-4.). To synchronize external interrupt signals after the STOP has been
released with the internal clock, while the clock is not stable, interrupt request cannot be stored.
Consequently, if sending external interrupt inputs after the STOP has been released, issue external interrup
signal after the oscillation stabilization wait time has elapsed.
Figure 18.6-4 Recovery Operation Sequence Using Low Voltage Detection Interrupt Interrupts
from STOP Status
INT1
Low voltage
detector 0
Internal
STOP
Regulator
Internal
operation (RUN)
Implement command (RUN)
X0
Internal clock
Interrupt flag clear
ER7
EN7
"1" (Set to enable before switching to STOP mode)
ER1
EN1
"1" (Set to enable before switching to STOP mode)
(a) STOP
(c) Oscillation stabilization wait time
(b) Oscillator oscillation time
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CHAPTER 18 LOW VOLTAGE DETECTION INTERRUPT / RESET
18.6 Operation of Low Voltage Detection Interrupt
MB91490 Series
■ Recovery Operations from STOP Status
The STOP recovery operation using low voltage detection interrupts from existing circuits is performed as
described below.
● Processing before changing to STOP status
• Low voltage detection interrupt setting
It is necessary to set the low voltage detection interrupt input to release STOP status before the device
transits to STOP status. This setting is made using the interrupt enable register (ENIR0:EN7).
• Low Voltage Detection Interrupt Inputs
If recovering from STOP status, the low voltage detection interrupt signal is asynchronous and send the
input signal. When this interrupt signal is enabled, the internal STOP signal is immediately turned OFF.
At the same time, the external interrupt circuit is switched so as to synchronize other level interrupt
inputs.
● Oscillator Oscillation Time
After STOP status has been released, the clock will start to oscillate. The oscillator oscillation time
depends on the used oscillator.
● Oscillation Stabilization Wait Time
After the oscillator oscillation time, an oscillation stabilization wait time is taken inside the device. The
oscillation stabilization wait time is specified by OS1 and OS0 bits on the standby control register. After
the oscillation stabilization wait time has ended, the internal clock is supplied, and in addition to the
activation of interrupt command operations from the low voltage detection interrupt, it also becomes
possible to receive external interrupt requests.
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CHAPTER 18 LOW VOLTAGE DETECTION INTERRUPT / RESET
18.7 Operation of Low Voltage Detector 1
18.7
MB91490 Series
Operation of Low Voltage Detector 1
Low Voltage Detector 1 continuously monitor VCC voltage. When VCC drops below
detect range, low voltage is asserted. When VCC raise above release range, low voltage
is released.
■ Operation of an Low Voltage Detector 1
Figure 18.7-1 shows the low voltage detector 1 operation.
Figure 18.7-1 Operation of an Low Voltage Detector 1
VCC
Release range
3.05V +/- 0.24V
Detect range
3.00V +/- 0.24V
Low voltage signal asserted
(System initialization issued,
pins are forced to Hi-Z state)
Time
Low voltage signal released
(System initialization released,
pins are released from Hi-Z state)
■ Low Voltage Detector 1 detected
When VCC drops below detect voltage, low voltage detection signal is asserted. System initialization is
issued. At the same time, pins are forced to Hi-Z state.
■ Low Voltage Detector 1 released
When VCC raise above release voltage, low voltage is released. System initialization is released and pins are
released from Hi-Z state.
■ System initialization generated by Low Voltage Detector 1
In order to make sure there is enough time for oscillation stabilization wait time after system initialization
generated by Low Voltage Detector 1, the system initialization generated by Low Voltage Detector 1 is
different from that generated by an external INITX pin in the initialization values of standby control
register STCR: OS1, OS0.
• The value is initialized to "00B" by a reset triggered by the INITX pin input (SINIT).
• The value is initialized to "10B" by a reset triggered by the low voltage detection reset (SINIT).
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CHAPTER 19
SERIAL PROGRAMMING
CONNECTION
MB91F49x supports serial onboard write (Fujitsu
Semiconductor standard) to flash memory.
This chapter explains the basic configuration for serial write
to flash memory by using the Fujitsu Semiconductor Serial
Programmer.
19.1 Fujitsu Semiconductor Serial Programmer
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CHAPTER 19 SERIAL PROGRAMMING CONNECTION
19.1 Fujitsu Semiconductor Serial Programmer
19.1
MB91490 Series
Fujitsu Semiconductor Serial Programmer
Fujitsu Semiconductor Serial Programmer (software) is an onboard programming tool
for all Fujitsu Semiconductor-made micro controllers with built-in flash memory.
Two types of Serial Programmer are available according to the PC interface (RS-232C or
USB) used. Choose the type according to your environment.
■ Basic Configuration of FUJITSU SEMICONDUCTOR MCU Programmer
(Clock Asynchronous Serial Write)
FUJITSU SEMICONDUCTOR MCU Programmer is used when the PC and microcontroller are connected
through an RS-232C cable. MCU Programmer writes data, through clock asynchronous serial communication,
to built-in flash memory of a microcontroller installed in the user system.
Figure 19.1-1 shows the basic configuration of FUJITSU SEMICONDUCTOR MCU Programmer, and
Table 19.1-1 lists the system configuration.
Figure 19.1-1 Basic Configuration of FUJITSU SEMICONDUCTOR MCU Programmer
User system
*
RS-232C
* RS-232C driver IC is required separately.
Table 19.1-1 System Configuration of FUJITSU SEMICONDUCTOR MCU Programmer
Name
FUJITSU SEMICONDUCTOR
MCU Programmer
Type
Specifications
-
Software (can be downloaded from Web
(registration system))*
* For registration, contact your sales representatives.
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CHAPTER 19 SERIAL PROGRAMMING CONNECTION
19.1 Fujitsu Semiconductor Serial Programmer
MB91490 Series
Figure 19.1-2 shows a connection example.
Figure 19.1-2 Connection Example using FUJITSU SEMICONDUCTOR MCU Programmer
MB91F49x
Vcc
In serial writing: 0
MD0
In serial writing: 0
MD1
10 k
In serial writing: 1
User circuit
MD2
P81
In serial writing: 0
User circuit
In serial writing: 0
P80
X0
X1
RS-232C
driver
INITX
10 k
PG1/SIN0
10 k
PG2/SOT0
RS-232C
Vss
The pull-up resistance values shown are for example.
Select the most appropriate resistance values for each system.
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CHAPTER 19 SERIAL PROGRAMMING CONNECTION
19.1 Fujitsu Semiconductor Serial Programmer
MB91490 Series
Table 19.1-2 Oscillating frequency and communication baud rate
available for clock asynchronous serial communication
Master Oscillating Frequency
Communication Baud Rate
10 MHz
4800 bps
20 MHz
9600 bps
■ Basic Configuration of FUJITSU SEMICONDUCTOR USB Programmer
(Clock Synchronous Serial Write)
FUJITSU SEMICONDUCTOR USB Programmer is used when the PC and microcontroller are connected
through an adapter (MB2146-09A-E). USB Programmer writes data, through clock synchronous serial
communication, to built-in flash memory of a microcontroller.
Figure 19.1-3 shows the basic configuration of FUJITSU SEMICONDUCTOR USB Programmer, and
Table 19.1-3 lists the system configuration.
Figure 19.1-3 Basic Configuration of FUJITSU SEMICONDUCTOR USB Programmer
CLK synchronous serial
USB
Adapter (MB2146-09A-E)
User system
Table 19.1-3 System Configuration of FUJITSU SEMICONDUCTOR USB Programmer
Name
Type
FUJITSU SEMICONDUCTOR USB
Programmer
-
Adapter
MB2146-09A-E
Specifications
Software (can be downloaded from Web
(registration system))*
F2MC family BGM adapter
(Accessory: USB cable)
* For registration, contact your sales representatives.
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CHAPTER 19 SERIAL PROGRAMMING CONNECTION
19.1 Fujitsu Semiconductor Serial Programmer
MB91490 Series
Figure 19.1-4 shows a connection example.
Figure 19.1-4 Connection example using FUJITSU SEMICONDUCTOR USB Programmer
MB91F49x
Connector of
Yamaichi Electronics
FAP-10-08#4-0BS
Vcc
MD0
In serial writing: 0
In serial writing: 0
Connector of Yamaichi Electronics
FAP-10-08#4-0BS
1, 10
10 kΩ
In serial writing: 1
Index mark
9 pin
MD1
MD2
1 pin
10 pin
2 pin
In serial writing: 1
(TOP VIEW)
BGM
BGM
Microcontroller
Connector
Connector
pin
User circuit
P81
User circuit
P80
Microcontroller pin
1
2
Vcc
6
GND
7
PG1/SIN0
3
INITX
8
4
Unconnected
9
5
PG2/SOT0
10
Unconnected
GND
(can be unconnected)
Vcc
(can be unconnected)
PG0/SCK0
In serial writing: 0
X0
X1
3
INITX
7
PG1/SIN0
5
6
10 kΩ
PG2/SOT0
PG0/SCK0
2, 9
The pull-up resistance values shown are for example.
Select the most appropriate resistance values for each system.
CM71-10155-2E
FUJITSU SEMICONDUCTOR LIMITED
657
CHAPTER 19 SERIAL PROGRAMMING CONNECTION
19.1 Fujitsu Semiconductor Serial Programmer
MB91490 Series
Table 19.1-4 Pins used
Pins
Function
MD2, MD1, MD0
Mode Pins
P80, P81
Write program startup
pins
Input "L" level to P80, and input "H" level to P81.
Reference: Asynchronous UART mode in case of P80="L" and P81="L"
INITX
Reset pin
-
PG1/SIN0
Serial data input pin
PG2/SOT0
Serial data output pin
PG0/SCK0
Serial clock input pin
VCC
Power voltage supply pin
VSS
GND pin
658
Supplement
Controlled for program mode.
Flash serial program mode:
MD2,MD1,MD0=1,0,0
Reference: Single-chip mode: MD2,MD1,MD0=0,0,0
Uses the UART ch.0 resource as clock synchronous mode.
Supply a program voltage from the user system. Do not connect to
the power supply of the user side when connecting.
GND pin is common to GND of the flash microcontroller programmer.
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
CHAPTER 20
WILD REGISTER CONTROL
BLOCK
This chapter describes the register configuration,
functions and timer operations of the wild register
control block.
20.1 Overview of Wild Register Control Block
20.2 Registers of Wild Register Control Block
20.3 Operations of Wild Register Control Block
20.4 Restrictions and Notes
CM71-10155-2E
FUJITSU SEMICONDUCTOR LIMITED
659
CHAPTER 20 WILD REGISTER CONTROL BLOCK
20.1 Overview of Wild Register Control Block
20.1
MB91490 Series
Overview of Wild Register Control Block
The wild register function replaces the data of the patch target address set in an
address register with the data set in a data register.
■ Overview of Wild Register Control Block
The wild register control block consists of a control register, 16 address setting registers and 16 data setting
registers, a total of 33 registers.
The range of replaceable target address is limited within the internal Flash area only.
■ Block Diagram of Wild Register Control Block
Figure 20.1-1 shows a block diagram of the wild register control block.
Figure 20.1-1 Block Diagram of Wild Register Control Block
I-bus address
I-bus data
F- bus address
Control block
F- bus data
Register
Access control
Flash
660
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
CHAPTER 20 WILD REGISTER CONTROL BLOCK
20.2 Registers of Wild Register Control Block
MB91490 Series
20.2
Registers of Wild Register Control Block
This section describes the configuration and functions of the registers used in the wild
register control block.
■ List of Registers in Wild Register Control Block
Figure 20.2-1 List of Registers in Wild Register Control Block
Address
0000 7020H
0000 7030H
0000 7034H
0000 7038H
0000 703CH
0000 7040H
0000 7044H
0000 7048H
0000 704CH
0000 7050H
0000 7054H
0000 7058H
0000 705CH
0000 7060H
0000 7064H
0000 7068H
0000 706CH
0000 7070H
0000 7074H
0000 7078H
0000 707CH
0000 7080H
0000 7084H
0000 7088H
0000 708CH
0000 7090H
0000 7094H
0000 7098H
0000 709CH
0000 70A0H
0000 70A4H
0000 70A8H
0000 70ACH
CM71-10155-2E
bit31
bit24 bit23
WREN
bit16 bit15
bit8 bit7
bit0
WA00
WD00
WA01
WD01
WA02
WD02
WA03
WD03
WA04
WD04
WA05
WD05
WA06
WD06
WA07
WD07
WA08
WD08
WA09
WD09
WA10
WD10
WA11
WD11
WA12
WD12
WA13
WD13
WA14
WD14
WA15
WD15
FUJITSU SEMICONDUCTOR LIMITED
661
CHAPTER 20 WILD REGISTER CONTROL BLOCK
20.2 Registers of Wild Register Control Block
20.2.1
MB91490 Series
Wild Register Enable Register (WREN)
The wild register enable register (WREN) is a register that enables the replacement
function corresponding to each channel (ch.0 to ch.15).
■ Bit Configuration of Wild Register Enable Register (WREN)
WREN (upper)
Address
bit31
bit30
bit29
bit28
bit27
bit26
bit25
bit24
Initial value
007020H
WREN15
WREN14
WREN13
WREN12
WREN11
WREN10
WREN09
WREN08
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit23
bit22
bit21
bit20
bit19
bit18
bit17
bit16
Initial value
007021H
WREN07
WREN06
WREN05
WREN04
WREN03
WREN02
WREN01
WREN00
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WREN (lower)
R/W: Readable/writable
[bit31 to bit16] WREN15 to WREN00: Replacement function enable bits
These bits enable the replacement function corresponding to each channel.
0: Wild register function is disabled. [Initial value]
1: Wild register function is enabled.
Note:
Be sure to use halfword access when accessing to this register.
662
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
CHAPTER 20 WILD REGISTER CONTROL BLOCK
20.2 Registers of Wild Register Control Block
MB91490 Series
20.2.2
Wild Register Address Register (WA)
The wild register address register (WA) is a register that sets the replacement target
address.
■ Bit Configuration of Wild Register Address Register (WA)
WA
Address
ch.0
ch.1
ch.2
ch.3
ch.4
ch.5
ch.6
ch.7
007030H
007038H
007040H
007048H
007050H
007058H
007060H
007068H
ch.8
ch.9
ch.10
ch.11
ch.12
ch.13
ch.14
ch.15
bit31 to bit21
bit20 to bit2
bit1,bit0
-
A20 to A2
-
-
R/W
-
007070H
007078H
007080H
007088H
007090H
007098H
0070A0H
0070A8H
Initial value: - - - - - - - - - - - - X X X X X X X X X X X X X X X X X X - - B
R/W: Readable/writable
[bit31 to bit21] Reserved: Reserved bits
These bits are reserved. Be sure to set them to "0".
[bit20 to bit2] A20 to A2: Replacement target address setting bits
Set a replacement target address.
[bit1, bit0] Reserved: Reserved bits
These bits are reserved. Be sure to set them to "0".
Notes:
• Be sure to use word access when accessing to this register.
• Replacement target address is limited within the internal Flash area only. Therefore, set an
address located within the internal Flash area for A20 to A2.
CM71-10155-2E
FUJITSU SEMICONDUCTOR LIMITED
663
CHAPTER 20 WILD REGISTER CONTROL BLOCK
20.2 Registers of Wild Register Control Block
20.2.3
MB91490 Series
Wild Register Data Register (WD)
The wild register data register (WD) is a register that sets the replacement data.
■ Bit Configuration of Wild Register Data Register (WD)
WD
Address
ch.00
ch.01
ch.02
ch.03
ch.04
ch.05
ch.06
ch.07
bit31
007034H
00703CH
007044H
00704CH
007054H
00705CH
007064H
00706CH
ch.08
ch.09
ch.10
ch.11
ch.12
ch.13
ch.14
ch.15
007074H
00707CH
007084H
00708CH
007094H
00709CH
0070A4H
0070ACH
bit0
D31 to D0
R/W
Initial value: X X X XX X X X X X X X XX X X XX X X XX X X X XX X X XX X B
R/W: Readable/writable
[bit31 to bit0] D31 to D0: Replacement data setting bits
Set replacement data.
Note:
Be sure to use word access when accessing to this register.
664
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
CHAPTER 20 WILD REGISTER CONTROL BLOCK
20.3 Operations of Wild Register Control Block
MB91490 Series
20.3
Operations of Wild Register Control Block
This section describes the operations of the wild register control block.
■ Operations of Wild Register Control Block
The wild register function replaces data with any data set in WDx. The replacement data/register
corresponding to each channel is shown in the table Table 20.3-1.
Table 20.3-1 Replacement Data/Register
Channel
ch.x
(x=00 to 15)
CM71-10155-2E
Replacement data/register
Address +0
Address +1
Address +2
Address +3
WDx(D31-D24)
WDx(D23-D16)
WDx(D15-D8)
WDx(D7-D0)
FUJITSU SEMICONDUCTOR LIMITED
665
CHAPTER 20 WILD REGISTER CONTROL BLOCK
20.4 Restrictions and Notes
20.4
MB91490 Series
Restrictions and Notes
This section summarizes the restrictions and notes on the wild register control block.
■ Wild Register Enable Register (WREN)
Be sure to use halfword access when accessing to this register.
■ Wild Register Address Register (WA)
• Be sure to use word access when accessing to this register.
• Replacement target address is limited within the internal Flash area only. Therefore, set an address
located within the internal Flash area for A20 to A2.
■ Wild Register Data Register (WD)
Be sure to use word access when accessing to this register.
■ Overall Restrictions and Notes
• The wild register function prioritizes the specification of register with the lower number
(Example: ch.0 > ch.1).
• Place the program that sets the wild register in an area other than the internal Flash area.
• Do not enable the wild register function while executing Flash memory automatic algorithm (or when
RDY (bit3 = 0) in flash control/status register: FLCR).
• If replacement data is set for an address at which an instruction longer than 16-bit length (a 32/48-bit
long instruction) is located, CPU may fail to interpret the instruction correctly, causing malfunctions.
Therefore, do not set replacement data in the middle of the instruction when setting it for an address at
which a 32/48-bit long instruction is located.
666
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
APPENDIX
The appendix describes pin states in each CPU state,
notes on using the little-endian areas, a list of FR family
instructions, and notes on using MB91490 series.
APPENDIX A I/O Map
APPENDIX B Interrupt Vector
APPENDIX C Pin States in Each CPU State
APPENDIX D Notes when Little Endian Area is used
APPENDIX E INSTRUCTION LISTS
APPENDIX F Precautions when Using
CM71-10155-2E
FUJITSU SEMICONDUCTOR LIMITED
667
APPENDIX
APPENDIX A I/O Map
MB91490 Series
APPENDIX A I/O Map
This section shows the correspondence between the various peripheral resource
registers and the memory space area.
■ I/O Map
Figure A-1 View in Table
Address
000000H
+0
PDR0 [R/W]B
XXXXXXXX
Register
+1
+2
PDR1 [R/W]B
PDR2 [R/W]B
XXXXXXXX
XXXXXXXX
+3
PDR3 [R/W]B
XXXXXXXX
Block
T-unit
Port Data Register
Read/write attribute, unit of access
(B:Byte,H:Half-word,W:Word)
Initial register value after a reset
Register name (registers in column 1 are located at 4n addresses,
registers in column 2 are located at 4n + 2 addresses, and so on)
The leftmost register address (When word access is used, data from
the register in the first column becomes the MSB.)
Note :
The bit value of the register shows the initial value as follows.
" 1 " : Initial value " 1 "
" 0 " : Initial value " 0 "
" X " : Initial value " X "
- : There is physically no register in the position.
The access by the data access attribute not described is disabled.
668
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
APPENDIX
APPENDIX A I/O Map
MB91490 Series
Table A-1 I/O Map (1 / 12)
Register
Address
Block
+0
+1
+3

000000H

000004H
000008H
+2
PDRA [R/W] B,H
-----XX-
PDRB [R/W] B,H
XXXX---
00000CH
000010H
PDRJ [R/W] B
----XXXX

000014H
PDRP [R/W] B,H
--XXXXXX
PDRQ [R/W] B,H
--XXXXXX
000018H
to
00003CH
(Reserved)
PDR8 [R/W] B
-XXXXXXX

PDRC [R/W] B
XXXXXXXX

PDRG [R/W] B,H
--XXXXXX
PDRH [R/W] B,H
-----XXX
PDRL [R/W] B
-----XXX



(Reserved)
000040H
EIRR0 [R/W] B,H,W
00000000
ENIR0 [R/W] B,H,W
00000000
ELVR0 [R/W] B,H,W
00000000 00000000
000044H
DICR [R/W] B,H
--------0
HRCL [R/W,R] B,H
0--11111

TMRLR0 [W] H,W
XXXXXXXX XXXXXXXX
TMR0 [R] H,W
XXXXXXXX XXXXXXXX
00004CH

TMCSR0 [R/W,R] B,H
----00-- ---00000
000050H
TMRLR1 [W] H,W
XXXXXXXX XXXXXXXX
TMR1 [R] H,W
XXXXXXXX XXXXXXXX

TMCSR1 [R/W,R] B,H
----00-- ---00000
000048H
000054H
000058H
to
00005CH
CM71-10155-2E
Port data
register

FUJITSU SEMICONDUCTOR LIMITED
External
interrupt
(INT0 to INT6,
Low voltage
detection
interrupt)
Delay
Interrupt/
Hold request
Reload
Timer 0
Reload
Timer 1
(Reserved)
669
APPENDIX
APPENDIX A I/O Map
MB91490 Series
Table A-1 I/O Map (2 / 12)
Register
Address
Block
+0
+1
+2
+3
000060H
SSR0 [R/W, R] B,H,W
00000011
ESCR0 [R/W]/
IBSR0 [R/W, R] B,H,W
00000000
SCR0 [R/W]/
IBCR0 [R/W, R]B,H,W
00000000
SMR0 [R/W] B,H,W
000-0000
000064H
BGR01 [R/W] B,H,W
00000000
BGR00 [R/W] B,H,W
00000000
ISMK0 [R/W] B,H
01111111

000068H
000070H
SSR1 [R/W, R] B,H,W
00000011
ESCR1 [R/W]/
IBSR1 [R/W, R]B,H,W
00000000
000074H
BGR11 [R/W] B,H,W
00000000
BGR10 [R/W] B,H,W
00000000
SMR1 [R/W] B,H,W
000-0000
Multi-function
serial
interface1
RDR1 [R]/
TDR1 [W]H,W
-------0 00000000
ISMK1 [R/W] B,H
01111111
ISBA1 [R/W] B,H
00000000

00007CH
000080H
SSR2 [R/W, R] B,H,W
00000011
ESCR2 [R/W]/
IBSR2 [R/W, R] B,H,W
00000000
000084H
BGR21 [R/W] B,H,W
00000000
BGR20 [R/W] B,H,W
00000000
670
(Reserved)
SCR1 [R/W]/
IBCR1 [R/W, R]B,H,W
00000000

000078H
00008CH
to
00009CH
ISBA0 [R/W] B,H
00000000

00006CH
000088H
Multi-function
serial
interface0
RDR0 [R]/
TDR0 [W]H,W
-------0 00000000
(Reserved)
SCR2 [R/W]/
IBCR2 [R/W, R]B,H,W
00000000
SMR2 [R/W, R] B,H,W
000-0000
RDR2 [R]/
TDR2 [W]H,W
-------0 00000000
ISMK2 [R/W] B,H
01111111


FUJITSU SEMICONDUCTOR LIMITED
Multi-function
serial
interface2
ISBA2 [R/W] B,H
00000000
(Reserved)
CM71-10155-2E
APPENDIX
APPENDIX A I/O Map
MB91490 Series
Table A-1 I/O Map (3 / 12)
Register
Address
Block
+0
+1
+2
+3
0000A0H
OCCPBH0, OCCPBL0 [W]/
OCCPH0, OCCPL0 [R]H,W
00000000 00000000
OCCPBH1, OCCPBL1 [W]/
OCCPH1, OCCPL1 [R]H,W
00000000 00000000
0000A4H
OCCPBH2, OCCPBL2 [W]/
OCCPH2, OCCPL2 [R]H,W
00000000 00000000
OCCPBH3, OCCPBL3 [W]/
OCCPH3, OCCPL3 [R]H,W
00000000 00000000
0000A8H
OCCPBH4, OCCPBL4 [W]/
OCCPH4, OCCPL4 [R]H,W
00000000 00000000
OCCPBH5, OCCPBL5 [W]/
OCCPH5, OCCPL5 [R]H,W
00000000 00000000
0000ACH
OCSH1 [R/W] B,H,W
-110--00
OCSL0 [R/W] B,H,W
00001100
OCSH3 [R/W] B,H,W
-110--00
OCSL2 [R/W] B,H,W
00001100
0000B0H
OCSH5 [R/W] B,H
-110--00
OCSL4 [R/W] B,H
00001100
OCMOD0 [R/W] B
--000000

CPCLRBH0, CPCLRBL0 [W]
/ CPCLRH0, CPCLRL0 [R] H,W
11111111 11111111
0000B4H
0000B8H
TCCSH0 [R/W] B,H,W
00000000
CPCLRBH1,CPCLRBL1 [W]
/ CPCLRH1, CPCLRL1 [R] H,W
11111111 11111111
0000BCH
0000C0H
TCCSL0 [R/W] B,H,W
01000000
TCCSH1 [R/W]B,H,W
00000000
TCCSL1 [R/W] B,H,W
01000000
CPCLRBH2,CPCLRBL2 [W]
/ CPCLRH2, CPCLRL2 [R] H,W
11111111 11111111
0000C4H
TCDTH0,TCDTL0 [R/W] H,W
00000000 00000000
TCCSM0 [R/W] B,H,W
----0000
ADTRGC0 [R/W]
B,H,W
-0-0-0-0
TCCSM1 [R/W] B,H,W
----0000
ADTRGC1 [R/W]
B,H,W
-0-0-0-0
TCCSL2 [R/W] B,H,W
01000000
TCCSM2 [R/W] B,H,W
----0000
ADTRGC2 [R/W]
B,H,W
-0-0-0-0
0000CCH

FRS2 [R/W] B
--00--00
FRS1 [R/W] B,H
--00--00
FRS0 [R/W] B,H
--00--00
FRS4 [R/W] B,H
--00--00
FRS3 [R/W] B,H
--00--00
0000D0H

0000D4H
IPCPH0, IPCPL0 [R] H,W
XXXXXXXX XXXXXXXX
IPCPH1, IPCPL1 [R] H,W
XXXXXXXX XXXXXXXX
0000D8H
IPCPH2, IPCPL2 [R] H,W
XXXXXXXX XXXXXXXX
IPCPH3, IPCPL3 [R] H,W
XXXXXXXX XXXXXXXX
CM71-10155-2E
PICSL01 [R/W] B,H,W
00000000
Free-run
Timer 1
TCDTH2,TCDTL2 [R/W] H,W
00000000 00000000
TCCSH2 [R/W]B,H,W
00000000
PICSH01 [W,R] B,H,W
00000000
Free-run
Timer 0
TCDTH1,TCDTL1 [R/W] H,W
00000000 00000000
0000C8H
0000DCH
OCU0
ICSH23 [R] B,H,W
------00
FUJITSU SEMICONDUCTOR LIMITED
Free-run
Timer 2
Free-run Timer
Selector 0
ICU0
ICSL23[R/W] B,H,W
00000000
671
APPENDIX
APPENDIX A I/O Map
MB91490 Series
Table A-1 I/O Map (4 / 12)
Register
Address
Block
+0
+1
+2
+3
0000E0H
TMRRH0, TMRRL0 [R/W] H,W
XXXXXXXX XXXXXXXX
TMRRH1, TMRRL1 [R/W] H,W
XXXXXXXX XXXXXXXX
0000E4H
TMRRH2, TMRRL2 [R/W] H
XXXXXXXX XXXXXXXX

0000E8H
DTCR0 [R/W] B,H
00000000
DTCR1 [R/W] B,H
00000000
DTCR2 [R/W] B
00000000

0000ECH

SIGCR10 [R/W] B
00000000

SIGCR20 [R/W] B
000000-1
ADCOMP0 [W]/
ADCOMPB0 [R] H,W
00000000 00000000
0000F0H
Waveform
Generator 0
ADCOMPD0 [W]/
ADCOMPDB0 [R] H,W
00000000 00000000

0000F4H
ADCOMP2 [W] /
ADCOMPB2 [R] H,W
00000000 00000000
0000F8H
A/D activation
compare 0
ADCOMPD2 [W]/
ADCOMPDB2 [R] H,W
00000000 00000000
0000FCH

ADTGBUF0
[R/W] B
-0-0-1-1
ADTGSEL0
[R/W] B,H
--00--00
ADTGCE0
[R/W] B,H
--00--00
000100H
PRLH0 [R/W] B,H,W
XXXXXXXX
PRLL0 [R/W] B,H,W
XXXXXXXX
PRLH1 [R/W] B,H,W
XXXXXXXX
PRLL1 [R/W] B,H,W
XXXXXXXX
000104H
PRLH2 [R/W] B,H,W
XXXXXXXX
PRLL2 [R/W] B,H,W
XXXXXXXX
PRLH3 [R/W] B,H,W
XXXXXXXX
PRLL3 [R/W] B,H,W
XXXXXXXX
000108H
PPGC0 [R/W] B,H,W
00000000
PPGC1 [R/W] B,H,W
00000000
PPGC2 [R/W] B,H,W
00000000
PPGC3 [R/W] B,H,W
00000000
00010CH
PRLH4 [R/W] B,H,W
XXXXXXXX
PRLL4 [R/W] B,H,W
XXXXXXXX
PRLH5 [R/W] B,H,W
XXXXXXXX
PRLL5 [R/W] B,H,W
XXXXXXXX
000110H
PRLH6 [R/W] B,H,W
XXXXXXXX
PRLL6 [R/W] B,H,W
XXXXXXXX
PRLH7 [R/W] B,H,W
XXXXXXXX
PRLL7 [R/W] B,H,W
XXXXXXXX
000114H
PPGC4 [R/W] B,H,W
00000000
PPGC5 [R/W] B,H,W
00000000
PPGC6 [R/W] B,H,W
00000000
PPGC7 [R/W] B,H,W
00000000
PPG
000118H
to
00012CH
000130H


TRG [R/W] B
00000000

REVC [R/W] B
00000000
(Reserved)

GATEC0 [R/W] B
--00--00

GATEC4 [R/W] B
------00
PPG
000134H
000138H
to
000140H
672

FUJITSU SEMICONDUCTOR LIMITED
(Reserved)
CM71-10155-2E
APPENDIX
APPENDIX A I/O Map
MB91490 Series
Table A-1 I/O Map (5 / 12)
Register
Address
Block
+0
000144H
000148H
+1
TTCR0 [R/W,W,R] B
11110000
COMP0 [R/W] B,H,W
00000000
+3

COMP2 [R/W] B,H,W
00000000
00014CH
to
00015CH
COMP4 [R/W] B,H,W
00000000
COMP6 [R/W] B,H,W
00000000

BT0TMR [R] B,H,W
00000000 00000000
000160H
BT0TMCR [R/W] B,H,W
-0000000 00000000

BT0PCSR/BT0PRLL [R/W] H,W
XXXXXXXX XXXXXXXX
000168H
Base Timer 0
BT0PDUT/BT0PRLH/BT0DTBF [R/W] B,H,W
XXXXXXXX XXXXXXXX

00016CH
(Reserved)
AICR2 [R/W] B, H
-------- 11111111
000170H
ADCS2 [R/W, W] B
0000000-

ADCH2 [R/W] B,H
0000000

ADMD2 [R/W] B,H
00001111
000178H
ADCD002 [R] B,H,W
10----XX XXXXXXXX
ADCD012 [R] B,H,W
10----XX XXXXXXXX
00017CH
ADCD022 [R] B,H,W
10----XX XXXXXXXX
ADCD032 [R] B,H,W
10----XX XXXXXXXX
000180H
ADCD042 [R] B,H,W
10----XX XXXXXXXX
ADCD052 [R] B,H,W
10----XX XXXXXXXX
000184H
ADCD062 [R] B,H,W
10----XX XXXXXXXX
ADCD072 [R] B,H,W
10----XX XXXXXXXX
000188H
to
0001FCH
CM71-10155-2E
Timing
Generator 0
(Reserved)
BT0STC [R/W] B
00000000

000164H
000174H
+2

FUJITSU SEMICONDUCTOR LIMITED
8/10-bit A/D
converter 2
(with 8
channels)
(Reserved)
673
APPENDIX
APPENDIX A I/O Map
MB91490 Series
Table A-1 I/O Map (6 / 12)
Register
Address
Block
+0
+1
+2
000200H
DMACA0 [R/W] B,H,W *1
00000000 ----XXXX XXXXXXXX XXXXXXXX
000204H
DMACB0 [R/W] B,H,W
00000000 00000000 XXXXXXXX XXXXXXXX
000208H
DMACA1 [R/W] B,H,W *1
00000000 ----XXXX XXXXXXXX XXXXXXXX
00020CH
DMACB1 [R/W] B,H,W
00000000 00000000 XXXXXXXX XXXXXXXX
000210H
DMACA2 [R/W] B,H,W *1
00000000 ----XXXX XXXXXXXX XXXXXXXX
000214H
DMACB2 [R/W] B,H,W
00000000 00000000 XXXXXXXX XXXXXXXX
000218H
DMACA3 [R/W] B,H,W *1
00000000 ----XXXX XXXXXXXX XXXXXXXX
00021CH
DMACB3 [R/W] B,H,W
00000000 00000000 XXXXXXXX XXXXXXXX
000220H
DMACA4 [R/W] B,H,W *1
00000000 ----XXXX XXXXXXXX XXXXXXXX
000224H
DMACB4 [R/W] B,H,W
00000000 00000000 XXXXXXXX XXXXXXXX
000228H
to
00023CH

000240H
DMACR [R/W] B,H,W
0--00000 -------- -------- --------
000244H
to
0003ECH

0003F0H
BSD0 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F4H
BSD1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F8H
BSDC [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003FCH
BSRR [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000400H

+3
DMAC
674
FUJITSU SEMICONDUCTOR LIMITED
(Reserved)
DMAC
(Reserved)
Bit search
module
(Reserved)
CM71-10155-2E
APPENDIX
APPENDIX A I/O Map
MB91490 Series
Table A-1 I/O Map (7 / 12)
Register
Address
Block
+0

000404H
000408H
+1
DDRA [R/W] B,H
-----00-
DDRB [R/W] B,H
0000---
00040CH
000410H
DDRJ [R/W] B
----0000

000414H
DDRP [R/W] B,H
--000000
DDRQ [R/W] B,H
--000000
000418H
to
000420H
+2
+3
DDR8 [R/W] B
-0000000

DDRC [R/W] B
00000000

DDRG [R/W] B,H
--000000
DDRH [R/W] B,H
-----000
DDRL [R/W] B
-----000



(Reserved)
PFR8 [R/W] B
-000----

000424H


000428H
000430H
PFRJ [R/W] B
----0-0-
000434H

PFRH [R/W] B,H
-----0-0
Port function
register

PFRQ [R/W] B
--000000
000438H
to
00043CH
Port function
register
(Reserved)
PFRG [R/W] B,H
--0-00-0

00042CH
Port direction
register


(Reserved)
000440H
ICR00 [R/W, R] B,H,W
---11111
ICR01 [R/W, R] B,H,W
---11111
ICR02 [R/W, R] B,H,W
---11111
ICR03 [R/W, R] B,H,W
---11111
000444H
ICR04 [R/W, R] B,H,W
---11111
ICR05 [R/W, R] B,H,W
---11111
ICR06 [R/W, R] B,H,W
---11111
ICR07 [R/W, R] B,H,W
---11111
000448H
ICR08 [R/W, R] B,H,W
---11111
ICR09 [R/W, R] B,H,W
---11111
ICR10 [R/W, R] B,H,W
---11111
ICR11 [R/W, R] B,H,W Interrupt
---11111
Controller
00044CH
ICR12 [R/W, R] B,H,W
---11111
ICR13 [R/W, R] B,H,W
---11111
ICR14 [R/W, R] B,H,W
---11111
ICR15 [R/W, R] B,H,W
---11111
000450H
ICR16 [R/W, R] B,H,W
---11111
ICR17 [R/W, R] B,H,W
---11111
ICR18 [R/W, R] B,H,W
---11111
ICR19 [R/W, R] B,H,W
---11111
000454H
CM71-10155-2E

FUJITSU SEMICONDUCTOR LIMITED
(Reserved)
675
APPENDIX
APPENDIX A I/O Map
MB91490 Series
Table A-1 I/O Map (8 / 12)
Register
Address
Block
+0
+1
+2
+3
000458H
ICR24 [R/W, R] B,H,W
---11111
ICR25 [R/W, R] B,H,W
---11111
ICR26 [R/W, R] B,H,W
---11111
ICR27 [R/W, R] B,H,W
---11111
00045CH
ICR28 [R/W, R] B,H,W
---11111
ICR29 [R/W, R] B,H,W
---11111
ICR30 [R/W, R] B,H,W
---11111
ICR31 [R/W, R] B,H,W
---11111
000460H

ICR33 [R/W, R] B
---11111
ICR34 [R/W, R] B,H
---11111
ICR35 [R/W, R] B,H
---11111
Interrupt
ICR39 [R/W, R] B,H,W Controller
---11111
000464H
ICR36 [R/W, R] B,H,W
---11111
ICR37 [R/W, R] B,H,W
---11111
ICR38 [R/W, R] B,H,W
---11111
000468H

ICR41 [R/W, R] B
---11111
ICR42 [R/W, R] B,H
---11111
ICR43 [R/W, R] B,H
---11111
00046CH
ICR44 [R/W, R] B,H,W
---11111
ICR45 [R/W, R] B,H,W
---11111
ICR46 [R/W, R] B,H,W
---11111
ICR47 [R/W, R] B,H,W
---11111
000470H
to
00047CH

000480H
RSRR [R/W] B,H,W
1-0-0-00
000484H
CLKR [R/W] B
-000-000
(Reserved)
STCR [R/W] B,H,W
001100-1
TBCR [R/W] B,H,W
00XXX-00
CTBR [W] B,H,W
XXXXXXXX

DIVR0 [R/W] B
00000011

000488H
to
00050CH

000510H

AICR1 [R/W] B
----1111
000514H
ADCS1 [R/W,W] B
0000000-

(Reserved)

ADCH1 [R/W] B,H
--00--00
ADMD1 [R/W] B,H
00001111
000518H
ADCD001 [R] B,H,W
10----XX XXXXXXXX
ADCD011 [R] B,H,W
10----XX XXXXXXXX
00051CH
ADCD021 [R] B,H,W
10----XX XXXXXXXX
ADCD031 [R] B,H,W
10----XX XXXXXXXX
000520H
to
00053CH
000540H
000544H
676

RCR10 [W] B,H,W
XXXXXXXX
RCR00 [W] B,H,W
XXXXXXXX
CCRH0 [R/W] B,H
00000000
CCRL0
[R/W, R] B,H
-0001000
Clock
Control unit
8/10-bit A/D
converter 1
(with 4
channels)
(Reserved)
UDCR10 [R] B,H,W
00000000

FUJITSU SEMICONDUCTOR LIMITED
UDCR00 [R] B,H,W
00000000
CSR0 [R/W, R] B
00000000
Up/down
counter 0
CM71-10155-2E
APPENDIX
APPENDIX A I/O Map
MB91490 Series
Table A-1 I/O Map (9 / 12)
Register
Address
Block
+0
+1
000548H
to
00057CH
+3

BT1TMR [R] B,H,W
00000000 00000000
000580H
BT1TMCR [R/W] B,H,W
-0000000 00000000

BT1PCSR/BT1PRLL [R/W] H,W
XXXXXXXX XXXXXXXX
000588H
(Reserved)
BT1STC [R/W] B
00000000

000584H
00058CH
to
000600H
Base Timer 1
BT1PDUT/BT1PRLH/BT1DTBF [R/W] H,W
XXXXXXXX XXXXXXXX


000604H
000608H
+2
PCRA [R/W] B,H
-----00-
PCRB [R/W] B,H
0000---
00060CH
000610H
PCRJ [R/W] B
----0000

000614H
PCRP [R/W] B,H
--000000
PCRQ [R/W] B,H
--000000
000618H
to
000FFCH
CM71-10155-2E
(Reserved)
PCR8 [R/W] B
-0000000

PCRC [R/W] B
00000000

PCRG [R/W] B,H
--000000
PCRH [R/W] B,H
-----000
PCRL [R/W] B
-----000

Pull-up resistor
control register


FUJITSU SEMICONDUCTOR LIMITED
(Reserved)
677
APPENDIX
APPENDIX A I/O Map
MB91490 Series
Table A-1 I/O Map (10 / 12)
Register
Address
Block
+0
+1
+2
+3
001000H
DMASA0 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001004H
DMADA0 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001008H
DMASA1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00100CH
DMADA1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001010H
DMASA2 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001014H
DMADA2 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001018H
DMASA3 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00101CH
DMADA3 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001020H
DMASA4 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001024H
DMADA4 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001028H
to
006FFCH

DMAC
007000H
FLCR [R/W, R] B
----X-0-
007004H
FLWC [R/W] B
--11-011
(Reserved)

Flash memory

007008H
to
00701CH
007020H
007024H
to
00702CH
678

WREN [R/W] H
00000000 00000000
(Reserved)


FUJITSU SEMICONDUCTOR LIMITED
Wild register
control block
(Reserved)
CM71-10155-2E
APPENDIX
APPENDIX A I/O Map
MB91490 Series
Table A-1 I/O Map (11 / 12)
Register
Address
Block
+0
+1
+2
007030H
WA00 [R/W] W
-------- ----XXXX XXXXXXXX XXXXXX--
007034H
WD00 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
007038H
WA01 [R/W] W
------- ----XXXX XXXXXXXX XXXXXX--
00703CH
WD01 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
007040H
WA02 [R/W] W
------- ----XXXX XXXXXXXX XXXXXX--
007044H
WD02 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
007048H
WA03 [R/W] W
------- ----XXXX XXXXXXXX XXXXXX--
00704CH
WD03 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
007050H
WA04 [R/W] W
------- ----XXXX XXXXXXXX XXXXXX--
007054H
WD04 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
007058H
WA05 [R/W] W
------- ----XXXX XXXXXXXX XXXXXX--
00705CH
WD05 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
007060H
WA06 [R/W] W
------- ----XXXX XXXXXXXX XXXXXX--
007064H
WD06 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
007068H
WA07 [R/W] W
------- ----XXXX XXXXXXXX XXXXXX--
00706CH
WD07 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
CM71-10155-2E
FUJITSU SEMICONDUCTOR LIMITED
+3
Wild register
control block
679
APPENDIX
APPENDIX A I/O Map
MB91490 Series
Table A-1 I/O Map (12 / 12)
Register
Address
Block
+0
+1
+2
007070H
WA08 [R/W] W
-------- ----XXXX XXXXXXXX XXXXXX--
007074H
WD08 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
007078H
WA09 [R/W] W
------- ----XXXX XXXXXXXX XXXXXX--
00707CH
WD09 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
007080H
WA10 [R/W] W
------- ----XXXX XXXXXXXX XXXXXX--
007084H
WD10 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
007088H
WA11 [R/W] W
------- ----XXXX XXXXXXXX XXXXXX--
00708CH
WD11 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
007090H
WA12 [R/W] W
------- ----XXXX XXXXXXXX XXXXXX--
007094H
WD12 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
007098H
WA13 [R/W] W
------- ----XXXX XXXXXXXX XXXXXX--
00709CH
WD13 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0070A0H
WA14 [R/W] W
------- ----XXXX XXXXXXXX XXXXXX--
0070A4H
WD14 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0070A8H
WA15 [R/W] W
------- ----XXXX XXXXXXXX XXXXXX--
0070ACH
WD15 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0070B0H
to
0FFFFCH

+3
Wild register
control block
(Reserved)
*1: The lower 16 bits (DTC[15:0]) of DMACA0 to DMACA4 cannot be accessed in bytes.
*2: The initial value depends on the reset level. Therefore, an initial value has been described.
680
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
APPENDIX
APPENDIX A I/O Map
MB91490 Series
Notes:
• Data is undefined in reserved or (-) area.
• Do not execute read-modify-write (RMW) instruction on registers having a write-only bit.
• Different product series may have different setting of initial values. Details please refer to the related chapters.
CM71-10155-2E
FUJITSU SEMICONDUCTOR LIMITED
681
APPENDIX
APPENDIX B Interrupt Vector
MB91490 Series
APPENDIX B Interrupt Vector
This section shows the vector table of the MB91490 series.
■ Interrupt Vector Table
Table B-1 Interrupt Vector (1 / 4)
Interrupt number
Interrupt factor
682
Interrupt level
Offset
TBR default
address
Decimal
Hexadecimal
Reset
0
00
-
3FCH
000FFFFCH
Mode vector
1
01
-
3F8H
000FFFF8H
System reserved
2
02
-
3F4H
000FFFF4H
System reserved
3
03
-
3F0H
000FFFF0H
System reserved
4
04
-
3ECH
000FFFECH
System reserved
5
05
-
3E8H
000FFFE8H
System reserved
6
06
-
3E4H
000FFFE4H
Coprocessor absent trap
7
07
-
3E0H
000FFFE0H
Coprocessor error trap
8
08
-
3DCH
000FFFDCH
INTE instruction
9
09
-
3D8H
000FFFD8H
System reserved
10
0A
-
3D4H
000FFFD4H
System reserved
11
0B
-
3D0H
000FFFD0H
Step trace trap
12
0C
-
3CCH
000FFFCCH
NMI demand (tool)
13
0D
-
3C8H
000FFFC8H
Undefined instruction exception
14
0E
-
3C4H
000FFFC4H
NMI demand
15
0F
-
3C0H
000FFFC0H
External interrupt 0
16
10
ICR00
3BCH
000FFFBCH
External interrupt 1
17
11
ICR01
3B8H
000FFFB8H
External interrupt 2
18
12
ICR02
3B4H
000FFFB4H
External interrupt 3
19
13
ICR03
3B0H
000FFFB0H
External interrupt 4
20
14
ICR04
3ACH
000FFFACH
External interrupt 5
21
15
ICR05
3A8H
000FFFA8H
FUJITSU SEMICONDUCTOR LIMITED
CM71-10155-2E
APPENDIX
APPENDIX B Interrupt Vector
MB91490 Series
Table B-1 Interrupt Vector (2 / 4)
Interrupt number
Interrupt factor
Interrupt level
Offset
TBR default
address
Decimal
Hexadecimal
External interrupt 6
22
16
ICR06
3A4H
000FFFA4H
Low voltage detection interrupt
detection
23
17
ICR07
3A0H
000FFFA0H
Reload timer 0
24
18
ICR08
39CH
000FFF9CH
Reload timer 1
25
19
ICR09
398H
000FFF98H
Base timer 0 (Factor 0/Factor 1)
26
1A
ICR10
394H
000FFF94H
Multi-function serial interface0
(UART send completed/
receive completed/I2C status)
27
1B
ICR11
390H
000FFF90H
Multi-function serial interface1
(UART send completed/
receive completed/I2C status)
28
1C
ICR12
38CH
000FFF8CH
Base timer 1 (Factor 0/Factor 1)
29
1D
ICR13
388H
000FFF88H
Up-Down Counter 0
30
1E
ICR14
384H
000FFF84H
DTTI0
31
1F
ICR15
380H
000FFF80H
DMAC0 (end, error)
32
20
ICR16
37CH
000FFF7CH
DMAC1 (end, error)
33
21
ICR17
378H
000FFF78H
DMAC2/3/4 (end, error)