A8518 Datasheet

A8518 and A8518-1
Wide Input Voltage Range, High-Efficiency,
Fault-Tolerant LED Driver
FEATURES AND BENEFITS
•
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DESCRIPTION
Automotive AEC-100 qualified
Fully integrated 42 V MOSFET for boost converter
Fully integrated LED current sinks
Withstands surge input to 40 VIN for load dump
Operates down to 3.9 VIN (max) for idle stop
Drives two strings of LEDs
Maximum output voltage 40 V
□□ Up to 11 white LEDs in series
Drive current for each string is 200 mA
Fixed 2.15 MHz boost switching frequency
Dithering of boost switching frequency to reduce EMI
(A8518 only)
Extremely high LED contrast ratio
□□ 10,000:1 using PWM dimming alone
□□ 100,000:1 when combining PWM and analog dimming
Excellent input voltage transient response at lowest
PWM duty cycle
Gate driver for optional P-channel MOSFET input
disconnect switch
LED current accuracy 0.7%
The A8518 is a multi-output LED driver for small-size LCD
backlighting. It integrates a current-mode boost converter
with internal power switch and two current sinks. The boost
converter can drive up to 22 white LEDs, 11 LEDs per string, at
200 mA. The LED sinks can be paralleled together to achieve
higher LED currents up to 400 mA. The A8518 operates from
a single power supply from 4.5 to 40 V, which allows the part
to withstand load dump conditions encountered in automotive
systems.
The A8518 can control LED brightness through a digital
(PWM) signal. An LED brightness contrast ratio of 10,000:1
can be achieved using PWM dimming at 100 Hz; a higher ratio
of 100,000:1 is possible when using a combination of PWM
and analog dimming.
Continued on the next page…
If required, the A8518 can drive an external P-channel MOSFET
to disconnect input supply from the system in the event of a
fault. The A8518 provides protection against output short,
overvoltage, open or shorted diode, open or shorted LED pin,
and overtemperature. A cycle-by-cycle current limit protects
the internal boost switch against high-current overloads.
Package: 16-Pin TSSOP with Exposed Thermal
Continued on the next page…
•
•
Pad (suffix LP)
APPLICATIONS:
• Automotive infotainment backlighting
• Automotive cluster
• Automotive center stack
Not to scale
*optional
VIN
L1
D1
VOUT > VIN
RSC
Q1
ROVP
RADJ
CIN
COUT1
GATE
VSENSE
SW
COUT2
VOUT
VIN
OVP
VDD
VC
CVDD
A8518
LED1
RPU
FAULT
PWM
LED2
APWM
COMP
ISET
AGND PGND
CP
RISET
RZ
CZ
GND
Typical Application Circuit Showing VOUT-to-Ground Short Protection Using Optional P-Channel MOSFET
A8518-DS, Rev. 2
Wide Input Voltage Range, High-Efficiency,
Fault-Tolerant LED Driver
A8518 and A8518-1
Features and Benefits (continued)
Description (continued)
• LED string current-matching accuracy 0.8%
• Protection against:
□□ Shorted boost switch, inductor or output capacitor
□□ Shorted ISET resistor
□□ Open or shorted LED pins and LED strings
□□ Open boost diode
□□ Overtemperature
The A8518 has a fixed boost switching frequencies of 2.15 MHz.
The high switching frequency allows the converter to operate above
the AM radio band.
The A8518 offers dithering of boost switching frequency, which
helps reduce EMI (electromagnetic interference). The A8518-1 is
identical to the A8518, but without the dithering feature.
Selection Guide
Part Number
Operating Ambient
Temperature Range
TA, (°C)
Frequency
Dithering
Package
Packaging
Leadframe Plating
A8518KLPTR-T
–40 to 125
Yes
16-Pin TSSOP with
exposed thermal pad
4000 pieces per reel
100% matte tin
A8518KLPTR-T-1
–40 to 125
No
16-Pin TSSOP with
exposed thermal pad
Contact Factory
100% matte tin
Contact Allegro for additional packing options.
Table of Contents
Specifications
Absolute Maximum Ratings
Thermal Characteristics
Functional Block Diagram
Pinout Diagram and Terminal List
Electrical Characteristics
Characteristic Performance
Functional Description
Enabling the IC
Powering Up: LED Pin Short-to-GND Check
Powering Up: Boost Output Undervoltage
Soft-Start Function
LED Current Setting and LED Dimming
PWM Dimming
APWM Pin
Extending LED Dimming Ratio
3
3
3
4
5
6
10
12
12
12
13
14
14
14
15
16
Analog Dimming
LED String Short Detect
Overvoltage Protection
Boost Switch Overcurrent Protection
Input Overcurrent Protection and
Disconnect Switch
Setting the Current Sense Resistor
Input UVLO
VDD
Shutdown
Dithering Feature
Fault Protection During Operation
Application Information
Design Example
Package Outline Diagram
17
18
18
19
20
21
21
21
21
22
23
25
28
29
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
Wide Input Voltage Range, High-Efficiency,
Fault-Tolerant LED Driver
A8518 and A8518-1
SPECIFICATIONS
Absolute Maximum Ratings1
Characteristic
Symbol
LEDx Pins
VLEDx
OVP Pin
VOVP
VIN, VOUT Pins
VSENSE, GATE Pins
SW Pin2
Rating
Unit
–0.3 to 40
V
–0.3 to 40
V
VIN, VOUT
–0.3 to 40
V
VSENSE, VGATE
VIN –7.4 to VIN + 0.4
V
–0.6 to 42
V
–1 to 48
V
–0.3 to 40
V
–0.3 to 5.5
V
VSW
FAULT Pin
Notes
x = 1 and 2
Continuous
t < 50 ns
VFAULT
APWM, PWM, COMP, ISET, VDD Pins
Operating Ambient Temperature
TA
–40 to 125
ºC
Maximum Junction Temperature
TJ(max)
150
ºC
Tstg
–55 to 150
ºC
Storage Temperature
K temperature range
1 Operation
at levels beyond the ratings listed in this table may cause permanent damage to the device. The absolute maximum ratings are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the electrical characteristics table is not implied. Exposure to absolute maximumrated conditions for extended periods may affect device reliability.
2 SW DMOS is self-protecting and will conduct when V
SW exceeds 48 V.
THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information
Characteristic
Package Thermal Resistance
Symbol
RθJA
Test Conditions*
On 2-layer 3 in2 PCB
On 4-layer PCB based on JEDEC standards
Value
Unit
48.5
ºC/W
34
ºC/W
*Additional thermal information available on the Allegro website.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
Wide Input Voltage Range, High-Efficiency,
Fault-Tolerant LED Driver
A8518 and A8518-1
SW
2.15 MHZ Oscillator
Frequency
Dithering
Ramp
Error
+ Amplifier
Driver
Circuit
–
Diode Open
+ Sense
+
COMP
–
Current
Sense
–
Internal Soft
Start Block
PGND
VIN
Regulator
UVLO Block
VREF
1.235 V
Reference
OCP2
TSD
VOUT Hyst.
Control
OVP2
VOUT
AGND
Internal VCC
VDD
OVP
Sense
Fault
Block
Input Current
Sense
– Amplifier
Open/Short
LED Detect
+
VSENSE
OVP
IADJ
LED1
AGND
Vin
LED
Driver
Block
Gate
Off
NMOS
Driver
GATE
LED2
APWM
Internal
VCC
Enable
Block
ISET
PWM
VREF
PWM
Block
ISET
Block
AGND
FAULT
AGND
AGND
PGND
AGND
Functional Block Diagram
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
Wide Input Voltage Range, High-Efficiency,
Fault-Tolerant LED Driver
A8518 and A8518-1
Pinout Diagram and Terminal List Table
COMP 1
16 LED2
PGND 2
15 LED1
14 AGND
OVP 3
13 ISET
VOUT 4
SW 5
PAD
GATE 6
VSENSE 7
VIN 8
12 APWM
11 PWM
10 VDD
9 FAULT
Package LP, 16-Pin TSSOP Pinout Diagram
Terminal List Table
Name
Number
Function
1
COMP
Output of the error amplifier and compensation node. Connect a series RZ-CZ-CP network from this pin to GND for control
loop compensation.
2
PGND
Power ground for internal N-channel MOSFET switching device.
3
OVP
Overvoltage protection. Connect external resistor from VOUT to this pin to adjust the overvoltage protection level.
4
VOUT
5
SW
Connect directly to boost output voltage.
6
GATE
7
VSENSE
8
VIN
9
FAULT
10
VDD
Output of internal LDO (bias regulator). Connect a 1 µF decoupling capacitor between this pin and GND.
11
PWM
Enables the IC when this pin is pulled high. Also serves to control the LED intensity by using pulse-width modulation.
Typical PWM dimming frequency is in the range of 100 to 400 Hz.
12
APWM
13
ISET
14
AGND
LED current ground. Connect to PCB ground plane.
15
LED1
LED current sink #1. Connect the cathode of LED string to associated pin. Unused LEDx pin must be terminated to GND
through a 1.54 kΩ resistor.
16
LED2
LED current sink #2. Connect the cathode of LED string to associated pin. Unused LEDx pin must be terminated to GND
through a 1.54 kΩ resistor.
–
PAD
Exposed pad of the package providing enhanced thermal dissipation. This pad must be connected to the ground plane(s)
of the PCB with at least 8 vias, directly in the pad.
The drain of the internal N-channel MOSFET switching device of the boost converter.
Output gate driver pin for external P-channel MOSFET control.
Connect this pin to the negative sense side of the current sense resistor RSC. The threshold voltage is measured as VINVSENSE. There is also fixed current sink to allow for trip threshold adjustment.
Input power to the IC, as well as the positive input used for current sense resistor.
The pin is an open-drain type configuration that will be pulled low when a fault occurs. Connect a 100 kΩ resistor between
this pin and desired logic level voltage.
Analog trimming option or dimming. Applying a digital PWM signal to this pin adjusts the internal ISET current.
Connect RISET resistor between this pin and GND to set the desired LED current setting.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
Wide Input Voltage Range, High-Efficiency,
Fault-Tolerant LED Driver
A8518 and A8518-1
ELECTRICAL CHARACTERISTICS1: Unless otherwise noted, specifications are valid at VIN = 16 V, TA = 25ºC, • indicates specifications
guaranteed over the full operating temperature range with TA = TJ = –40ºC to 125ºC, typical specifications are at TA = 25ºC
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Input Voltage
Input Voltage Range3
VIN
●
4.5
–
40
V
UVLO Start Threshold
VUVLOrise
VIN rising
●
–
–
4.35
V
UVLO Stop Threshold
VUVLOfall
VIN falling
●
UVLO Hysteresis
VUVLOHYS
–
–
3.9
V
300
450
600
mV
Input Supply Current
Input Quiescent Current
Input Sleep Supply Current
IQ
ISLEEP
VPWM = VIH, fSW = 2 MHz
●
–
8
15
mA
VIN = 16 V, VPWM = 0 V
●
–
2
10
µA
●
–
–
0.4
V
●
Input Logic Levels (PWM, APWM)
Input Logic Level Low
VIL
Input Logic Level High
VIH
1.5
–
–
V
PWM Input Pull-Down Resistor
REN
VPWM = 5 V
60
100
140
kΩ
RAPWM
VPWM = VIH
60
100
140
kΩ
40
–
1000
kHz
APWM Input Pull-Down Resistor
APWM
APWM Frequency2
fAPWM
●
Error Amplifier
Source Current
IEA(SRC)
VCOMP = 1.5 V
–
–600
–
μA
Sink Current
IEA(SINK)
VCOMP = 1.5 V
–
+600
–
μA
COMP Pin Pull-Down Resistance
RCOMP
FAULT = 0, VCOMP = 1.5V
–
1.4
–
kΩ
VOVP(th)
OVP pin connected to VOUT
●
7
8.3
9.5
V
IOVP(th)
Current into OVP pin
●
190
200
210
μA
IOVP(LKG)
VIN = 16 V, PWM = L
●
–
0.1
1
μA
Overvoltage Protection
OVP Pin Voltage Threshold
OVP Pin Sense Current Threshold
OVP Pin Leakage Current
OVP Accuracy
Undervoltage Protection Threshold
VUVP(th)
Secondary Overvoltage Protection
VOVP(sec)
Measured at VOUT pin when ROVP = 160 kΩ2
Measured at VOUT pin when ROVP = 0
–
–
5
%
–
3
–
V
–
0.55
0.7
V
Measured at SW pin
●
42
45
48
V
ISW = 0.750 A, VIN = 16 V
●
100
250
500
mΩ
VSW = 16 V, VPWM = VIL
●
–
0.1
1
μA
●
3
3.65
4.5
A
~
4.9
–
A
BOOST Switch
Switch On-Resistance
RSW
Switch Leakage Current
ISW(LKG)
Switch Current Limit
ISW(LIM)
Secondary Switch Current Limit2
ISW(LIM2)
Higher than max ISW(LIM) under all conditions
part latches when detected
Minimum Switch On-Time
tSW(on)
●
45
65
85
ns
Minimum Switch Off-Time
tSW(off)
●
–
65
85
ns
Continued on the next page…
1 For
input and output current specifications, negative current is defined as coming out of the node or pin (sourcing); positive current is defined as going into the node or pin
(sinking).
2 Ensured by design and characterization, not production tested.
3 Minimum V = 4.5 V is only required at startup. After startup is completed, IC can continue to operate down to V = 3.9 V.
IN
IN
4 LED current is trimmed to cancel variations in both Gain and ISET voltage.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
Wide Input Voltage Range, High-Efficiency,
Fault-Tolerant LED Driver
A8518 and A8518-1
ELECTRICAL CHARACTERISTICS1 (continued): Unless otherwise noted, specifications are valid at VIN = 16 V, TA = 25ºC, • indicates
specifications guaranteed over the full operating temperature range with TA = TJ = –40ºC to 125ºC, typical specifications are at TA = 25ºC
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Oscillator Frequency
Oscillator Frequency
fSW
fSW measurements were taken with dithering
function disabled
●
1.95
2.15
2.35
MHz
LED Current Sinks
LEDx Accuracy4
ErrLED
RISET = 8.33 kΩ
●
–
0.7
3
%
LEDx Matching
ΔLEDx
ISET = 120 µA
●
–
0.8
2
%
LEDx Regulation Voltage
VLED
VLED1 = VLED2, ISET = 120 µA
●
750
850
975
mV
ISET to ILEDx Current Gain
AISET
ISET = 120 µA
●
1391
1419
1453
A/A
ISET Pin Voltage
VISET
Allowable ISET Current
IISET
VLEDx Short Detect
LED Startup Ramp Time2
Maximum PWM Dimming Until OffTime2
Minimum PWM On-Time
0.987
1.017
1.047
V
●
20
–
144
µA
●
4.7
5.2
5.7
V
VLEDx(SC)
While LED sinks are in regulation; sensed from
VLEDx to AGND
tSS
Maximum time duration before all LED channels
come into regulation, or OVP is tripped
–
20
–
ms
tPWML
Measured while PWM = low, during dimming
control and internal references are powered on
(exceeding tPWML results in shutdown)
–
16
–
ms
tPWMH(min1)
First cycle when powering up IC (PWM = 0 to
3.3 V)
●
–
0.75
2
µs
Subsequent PWM pulses
●
–
0.5
1
µs
●
–
0.2
0.5
µs
●
–
0.36
0.5
µs
VGS = VIN, no input OCP fault
–
–113
–
μA
VGS = VIN – 6 V, input OCP fault tripped
–
6
–
mA
PWM High to LED On Delay
tdPWM(on)
Time between PWM going high and when LED
current reaches 90% of maximum
(VPWM = 0 to 3.3 V)
PWM Low to LED Off Delay
tdPWM(off)
Time between PWM going low and when LED
current reaches 10% of maximum
(VPWM = 3.3 to 0 V)
GATE Pin
Gate Pin Sink Current
Gate Pin Source Current
IGSINK
IGSOURCE
Gate Shutdown Delay When
Overcurrent Fault Is Tripped2
tFAULT
VIN – VSENSE = 200 mV. Monitored at FAULT pin
–
–
3
µs
Gate Voltage
VGS
Measured between GATE and VIN when gate
is on
–
–6.7
–
V
●
17.2
21.5
25.8
µA
●
95
110
125
mV
VSENSE Pin
VSENSE Pin Sink Current
VSENSE Trip Point
Iadj
VSENSE(trip)
Measured between VIN and VSENSE, RADJ = 0
Continued on the next page…
1 For
input and output current specifications, negative current is defined as coming out of the node or pin (sourcing); positive current is defined as going into the node or pin
(sinking).
2 Ensured by design and characterization, not production tested.
3 Minimum V = 4.5 V is only required at startup. After startup is completed, IC can continue to operate down to V = 3.9 V.
IN
IN
4 LED current is trimmed to cancel variations in both Gain and ISET voltage.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
Wide Input Voltage Range, High-Efficiency,
Fault-Tolerant LED Driver
A8518 and A8518-1
ELECTRICAL CHARACTERISTICS1 (continued): Unless otherwise noted, specifications are valid at VIN = 16 V, TA = 25ºC, • indicates specifications guaranteed over the full operating temperature range with TA = TJ = –40ºC to 125ºC, typical specifications are at TA = 25ºC
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Fault Pin
FAULT Pull-Down Voltage
FAULT Pin Leakage Current
VFAULT
IFAULT(lkg)
IFAULT = 1 mA
–
–
0.5
V
VFAULT = 5 V
–
–
1
µA
155
170
–
ºC
–
20
–
ºC
Thermal Protection (TSD)
Thermal Shutdown Threshold2
TSD
Thermal Shutdown Hysteresis2
TSDHYS
Temperature rising
1 For
input and output current specifications, negative current is defined as coming out of the node or pin (sourcing); positive current is defined as going into the node or pin
(sinking).
2 Ensured by design and characterization, not production tested.
3 Minimum V = 4.5 V is only required at startup. After startup is completed, IC can continue to operate down to V = 3.9 V.
IN
IN
4 LED current is trimmed to cancel variations in both Gain and ISET voltage.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
Wide Input Voltage Range, High-Efficiency,
Fault-Tolerant LED Driver
A8518 and A8518-1
*optional
VIN
L1
D1
VOUT > VIN
RSC
Q1
ROVP
RADJ
CIN
COUT1
GATE
VSENSE
SW
COUT2
VOUT
VIN
OVP
VDD
VC
CVDD
A8518
LED1
RPU
FAULT
PWM
LED2
APWM
COMP
ISET
AGND PGND
RZ
CP
RISET
CZ
GND
Typical Application Showing Boost Configuration with Input Switch to Protect Against VOUT-to-GND Short
L2
VIN
Output: 3 WLED in series
(~10 V)
D2
L1
R1*
CIN
CSW
D2*
ROVP
COUT
GATE
VSENSE
SW
VOUT
VIN
OVP
VDD
VC
CVDD
LED1
RPU
FAULT
PWM
LED2
APWM
ISET
RISET
AGND PGND
*Notes:
Input disconnect switch is not necessary in this
case to protect against VOUT-to-GND short.
COMP
CP
RZ
CZ
R1 and D2 are used to provide a leakage path
such that OVP pin is above 100 mV during startup;
otherwise, the IC would assume a VOUT-to-GND
short and not proceed with soft start.
GND
Typical Application Showing SEPIC Configuration for Flexible Input/Output Voltage Ratio
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
9
Wide Input Voltage Range, High-Efficiency,
Fault-Tolerant LED Driver
A8518 and A8518-1
CHARACTERISTIC PERFORMANCE
Startup Waveforms
Efficiency Measurement
Efficiency at 120mA/Ch for various LED configurations
Efficiency at 120 mA/Channel for various LED configurations
89.00
VOUT
88.00
87.00
Eff(%)
Eff
%
86.00
10X2 LED
85.00
9X2 LED
84.00
8X2 LED
83.00
VSW
7X2 LED
82.00
81.00
80.00
8
10
12
14
16
ILED(TOTAL)
VIN (V)
Vin
(V)
A8518 Evaluation Board Efficiency versus Input Voltage while
Disconnect Switch and Snubber Circuit are Used
Efficiency at Vin=12V for various LED configurations
Efficiency at VIN = 12 V for various LED configurations
Start up at 100% PWM Dimming, VIN = 7 V, 2 Channels,
10 LEDs/Channels, 120 mA/Channels; Time base = 10 ms/Div
90.00
88.00
Eff
Eff(%)
%
9X2 LED
86.00
VOUT
8X2 LED
84.00
7X2 LED
82.00
VSW
80.00
78.00
0.1
0.2
0.3
0.4
Total LED
Current (A)
Total
Led Current
(A)
A8518 Evaluation Board Efficiency versus Total LED Current while
Disconnect Switch and Snubber Circuit are Used
ILED(TOTAL)
Higher efficiency can be achieved by:
• Using an inductor with a low DCR.
• Using lower forward voltage drop and a smaller juction
capacitance Schottky diode.
Start up at 0.02% PWM Dimming at 200 Hz, VIN = 7 V, 2 Channels,
10 LEDs/Channel, 120 mA/Channel; Time base = 10 ms/Div
• Removal of snubber circuit; however, this might compromise
the EMI performance.
• Shorting out the disconnect switch and the input current sense
resistor; however, this will eliminate the output short-to-GND
protection feature.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
10
A8518 and A8518-1
Transient Response to Step Change in PWM Dimming
VSW
Wide Input Voltage Range, High-Efficiency,
Fault-Tolerant LED Driver
Transient Response to Step Change in VIN Voltage
VSW
VOUT
VOUT
VIN
ILED(TOTAL)
From PWM = 0.1% to PWM = 100% at 120 mA/Channel, VIN = 12 V;
Time base = 50 ms/Div
ILED(TOTAL)
From VIN = 16 V to VIN = 5.5 V, 2 Ch, 120 mA/Channel, PWM = 100%;
Time base = 20 ms/Div
VSW
VSW
VOUT
VOUT
ILED(TOTAL)
VIN
ILED(TOTAL)
From PWM = 100% to PWM = 0.01% at 120 mA/Channel, VIN = 12 V;
Time base = 50 ms/Div
From VIN = 5.5 V to VIN = 16 V, 2 Ch, 120 mA/Channel, PWM = 100%;
Time base = 20 ms/Div
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
11
Wide Input Voltage Range, High-Efficiency,
Fault-Tolerant LED Driver
A8518 and A8518-1
FUNCTIONAL DESCRIPTION
Enabling the IC
VGATE
The IC turns on when a logic high signal is applied on the PWM
pin with a minimum duration of tPWMH(min1) for the first clock
cycle, and the input voltage present on the VIN pin is greater
than 4.35 V to clear the UVLO threshold. Before the LEDs are
enabled, the A8518 driver goes through a system check to see
if there are any possible fault conditions that might prevent the
system from functioning correctly.
VLED1
GATE=Vin-3.3V
GATE voltage is pulled lower than VIN
LED current regulation begins
VISET
VPWM
VPWM
LED Detection Period
VISET
VVDD
ILED(TOTAL)
Figure 1: Power-Up Diagram Showing PWM, ISET, VDD Voltages, and LED Current
Once the IC is enabled, there are only two ways to shut down the
IC into low-power mode:
1. Pull PWM pin to low for at least 32,750 clock cycles
(approximately 16 ms at 2 MHz).
2. Cut off the supply and allow VIN to drop below UVLO falling threshold (less than 3.9 V).
Powering Up: LED Pin Check
Once VIN pin goes above UVLO and a high signal is present
on the PWM pin, the IC proceeds to power up. The A8518 then
enables the disconnect switch (GATE) and checks to see if the
LED pins are shorted to ground and/or are not used. The LED
detect phase starts when the GATE voltage of the disconnect
switch is equal to VIN – 3.3 V.
Figure 2: Power Up Diagram Showing Disconnect,
VGATE, VLED1, VISET, and VPWM During LED Pins Detect
and Regulation Period
When the voltage on the LEDx pins exceeds 120 mV, a delay
between 3000 and 4000 clock cycles (1.5 to 2 ms) is used to
determine the status of the pins.
All unused LED pins should be connected with a 1.54 kΩ resistor to GND. The unused pin, with the pull-down resistor, will be
taken out of regulation at this point and will not contribute to the
boost regulation loop.
LED String
Use LED1 Channel Only
AGND
LED Strings LED Strings
Use Both LED Channels
LED 1
LED 2
AGND
LED 1
LED 2
1.54 k
GND
GND
Figure 3: Channel Select Setup
Figure 2 shows the relation of LEDx pins with respect to the
gate voltage of the disconnect switch (if used) during LED detect
phase.
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Wide Input Voltage Range, High-Efficiency,
Fault-Tolerant LED Driver
A8518 and A8518-1
Table 1: LED Detection Voltage Thresholds
LED Pin Voltage
Level
LED Pin
Action
Less than 70 mV
Indicates a short to
PCB GND
A8518 will not proceed
with power up
150 mV
Not used
LED string connected
with the unused LED
pin is removed from
operation
325 mV
LED pin in use
None
If an LED pin is shorted to ground, the A8518 will not proceed
with soft-start until the short is removed from the LED pin. This
prevents the A8518 from powering up and putting an uncontrolled amount of current through the LEDs.
Short is
applied at
LED1
VLED1
Short is
removed
VLED2
VISET
VLED2
LED Detection
VPWM
VLED1
LED current regulation begins
VISET
Figure 6: One LED is Shorted to GND.
VPWM
The IC will not proceed with power up until LED pin is released, at
which point the LED is checked to see if it used.
Powering Up: Boost Output Undervoltage
Protection
Figure 4: LED String Detect Occurs when Both LEDs
are Selected to be Used
During startup, after the input disconnect switch has been
enabled, the output voltage is checked through the OVP pin. If
the sensed voltage does not rise above VUVP(th), the output is
assumed to be at fault and the IC will not proceed with soft-start.
Undervoltage protection may be caused by one of the following
faults:
VLED1
VLED2
• Output capacitor shorted to GND
LED2 is not used
• Boost inductor or diode open
• OVP sense resistor open
VISET
VPWM
After an undervoltage fault, the A8518 is immediately shut down
and latched off. To enable the IC again, the PWM pin must be
pulled low for at least 32,750 clock cycles (about 16 ms), then
pulled high again.
Figure 5: Detect Voltage is about 150 mV when LED
Pin 2 is Not Used
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A8518 and A8518-1
Soft-Start Function
During startup, the A8518 ramps up its boost output voltage
following a fixed ramp function. This technique limits the input
inrush current, and ensures the same startup time regardless of
PWM duty cycle.
The soft-start process is completed when any one of the following conditions is met:
1. All LED currents have reached regulation target,
2. Output voltage has reached 93% of its OVP threshold, or
3. Soft-start ramp time (tSS) has expired.
VSW
VOUT
ILED(TOTAL)
IIN
Figure 7: Startup Diagram Showing the Input Current,
Output Voltage, Total LED Current, and Switch Node
Voltage
LED Current Setting and LED Dimming
The maximum LED current can be up to 200 mA per channel,
and is set through the ISET pin. To set ILED, calculate RISET as
follows:
Wide Input Voltage Range, High-Efficiency,
Fault-Tolerant LED Driver
Table 2: LED Current Setting Resistors (Values Rounded to
the Nearest Standard Resistor Value)
Standard Closest RISET Resistor
Values
LED Current
ILED
7.15 kΩ
200 mA per LED
8.87 kΩ
160 mA per LED
11.8 kΩ
120 mA per LED
14.3 kΩ
100 mA per LED
17.8 kΩ
80 mA per LED
PWM Dimming
The LED current can be reduced from the 100% current level
by PWM dimming using the PWM pin. When the PWM pin is
pulled high, the A8518 turns on and all enabled LEDs sink 100%
current. When PWM is pulled low, the boost converter and LED
sinks are turned off. The compensation (COMP) pin is floated,
and critical internal circuits are kept active. The typical PWM
dimming frequencies fall between 200 Hz and 1 kHz.
The A8518 is designed to deliver a maximum dimming ratio of
10,000:1 at PWM frequency of 100 Hz. That means a minimum
PWM duty cycle of 0.01%, or an on-time of just 1 μs out of a
period of 10 ms.
High-PWM dimming ratio is acheived by regulating the output
voltage during PWM off-time. The VOUT pin samples the output
voltage during PWM on-time and regulates it during off-time. A
hysteresis control loop brings VOUT higher by approximately
350 mV whenever it drops below the target voltage. In a highly
noisy switching environment, it is necessary to insert an RC filter
at the VOUT pin. A typical value of R = 10 kΩ and C = 47 pF is
recommended.
VCOMP
VOUT
ILED = IISET × AISET
VISET
RISET
(VISET × AISET )
RISET =
ILED
IISET =
where ILED is in A and RISET is in Ω.
This sets the maximum current through the LEDs, referred to as
the 100% current.
VPWM
ILED(TOTAL)
Figure 8: Typical PWM Diagram Showing VOUT, ILED,
and COMP Pins, as well as the PWM Signal. (PWM dimming Frequency is 500 Hz 50% duty cyle.)
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Wide Input Voltage Range, High-Efficiency,
Fault-Tolerant LED Driver
A8518 and A8518-1
VCOMP
VPWM
VOUT
VPWM
ILED(TOTAL)
ILED(TOTAL)
Figure 9: Typical PWM Diagram Showing VOUT, ILED,
and COMP Pins, as well as the PWM Signal. (PWM dimming frequency is 500 Hz 1% duty cycle.)
Another important feature of the A8518 is the PWM signal to
LED current delay. This delay is typically less than 500 ns, which
allows for greater LED current accuracy at low-PWM dimming
duty cycles.
The error introduced by LED turn-on delay is partially offset by
LED turn-off delay. Therefore, a PWM pulse width of under
1 µs is still feasible, but the percentage error of LED current will
increase with narrower pulse width.
Figure 11: Falling Edge PWM Signal to Total LED Current ILED(TOTAL) Turn-Off Delay. Time base = 100 ns
APWM Pin
APWM
ISET
ILED(TOTAL)
APWM ISET
Current
Adjust Block
RISET
PWM
VPWM
ISET
Current
Mirror
LED Driver
Figure 12: Simplified Block Diagram of APWM ISET
Block
The APWM pin is used in conjunction with the ISET pin (see
Figure 12). This is a digital signal pin that internally adjusts
the IISET current. The typical input signal frequency is between
40 kHz and 1 MHz. The duty cycle of this signal is inversely
proportional to the percentage of current that is delivered to
the LED (see Figure 13). As an example, a system that delivers IILED(TOTAL) = 240 mA would deliver IILED(TOTAL) = 180
mA when an APWM signal with a duty cycle of 25% is applied.
When this pin is not used it should be tied to AGND.
Figure 10: Rising Edge PWM Signal to Total LED Current ILED(TOTAL) Turn-On Delay. Time base = 100 ns
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Wide Input Voltage Range, High-Efficiency,
Fault-Tolerant LED Driver
A8518 and A8518-1
ILED(TOTAL)
100
Normalized LED Current (%)
90
80
70
VAPWM
60
50
40
30
VPWM
20
10
0
0
10
20
30
40
50
60
70
80
90
100
APWM Duty Cycle (%)
Figure 13: Normalized LED Current vs. APWM Duty Cycle
VIN = 9 V, VOUT = ~22 V, RISET = 24 kΩ, APWM = 200 kHz
Figure 15: Transition of total LED current from 240 mA
to 180 mA, when a 50 kHz 25% APWM signal is applied
to the APWM pin. (Dimming PWM = 100%)
ILED(TOTAL)
LED Current Error (% of full scale)
5
4
3
VAPWM
2
1
VPWM
0
0
10
20
30
40
50
60
70
80
90
100
APWM Duty Cycle (%)
Figure 14: Error in LED Current vs. APWM Duty Cycle
VIN = 9 V, VOUT = ~22 V, RISET = 24 kΩ, APWM = 200 kHz
Figure 16: Transition of total LED current from 180 mA
to 240 mA, when a 50 kHz 25% APWM stops being applied to the APWM pin. (Dimming PWM = 100%)
To use the APWM pin as a trim function, the user should set
the maximum output current to a value higher than the desired
current by at least 5%. The LED IISET current is then trimmed
down to the appropriate desired value. Another consideration is
the limitation of the APWM signal’s duty cycle. In some cases, it
might be more desirable to set the maximum IISET current to be
25% to 50% higher, thus allowing the APWM signal to have duty
cycles that are between 25% and 50%.
Although the APWM dimming function has a wide frequency
range, if used strictly as an analog dimming function, it is recommended to use frequency ranges between 50 and 500 kHz for
best accuracy. The frequency range needs to be considered only
if the user is not using APWM as a closed-loop trim function. It
takes about 1 millisecond to change the actual LED current due to
propagation delay between the APWM signal and ILED(TOTAL).
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A8518 and A8518-1
Wide Input Voltage Range, High-Efficiency,
Fault-Tolerant LED Driver
Analog Dimming
ILED(TOTAL)
VAPWM
Besides using APWM signal, the LED current can also be
reduced by using an external DAC or another voltage source.
Connect RISET between the DAC output and the ISET pin. The
limit of this type of dimming is dependant of the range of the
ISET pin. In the case of the A8518, the limit is 20 to 144 µA.
R ISET
ISET
VDAC
VPWM
Figure 17: Transition of output current level when a
50 kHz 50% duty cycle APWM signal is applied to the
APWM pin, in conjunction with 50% duty cycle applied
to the PWM pin.
Extending LED Dimming Ratio
The dynamic range of LED brightness can be further extended by
using a combination of PWM duty cycle, APWM duty cycle, and
analog dimming method.
For example, the following approach can be used to achieve a
50,000:1 dimming ratio at 200 Hz PWM frequency:
•
Vary PWM duty cycle from 100% down to 0.02% to give
5,000:1 dimming.
•
With PWM duty cycle at 0.02%, vary APWM duty from 0%
to 90% to reduce LED current down to 10%. This gives a net
effect of 50,000:1 dimming.
DAC
or
Voltage Source
GND
A8518
Simplified Diagram of
Voltage LED Current
Control
AGND
GND
Figure 18: Typical Application Circuit Using a DAC to
Control the LED Current in the A8518
The LED current is controlled by the following formula:
IISET =
VISET – VDAC
RISET
where VISET is the ISET pin voltage and VDAC is the DAC output
voltage.
When the DAC voltage is 0 V, the LED current will be at its
maximum. To keep the internal gain amplifier stable, do not
decrease the current through the RISET resistor to less than
20 μA.
Figure 19 shows a typical application circuit using a DAC to
control the LED current using a two-resistor configuration. The
advantage of this circuit is that the DAC voltage can be higher or
lower, thus adjusting the LED current to a higher or lower value
of the preset LED current set by the RISET resistor.
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Wide Input Voltage Range, High-Efficiency,
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A8518 and A8518-1
R1
ISET
VDAC
A8518
DAC
R ISET
GND
Simplified Diagram of
Voltage LED Current
Control
Figure 19: Typical Application Circuit Using a DAC and
RISET Resistor to Control the LED Current in the A8518
The LED current can be adjusted using the following formula:
IISET =
VISET
RISET
–
VDAC – VISET
R1
where VISET is the ISET pin voltage and VDAC is the DAC output
voltage.
When VDAC is equal to 1 V, the output is strictly controlled by
the RISET resistor. When VDAC is higher than 1 V, the LED current is reduced. When VDAC is lower that 1 V, the LED current is
increased.
LED String Short Detect
All LEDx pins are capable of handling the maximum VOUT that
the converter can deliver, thus allowing for LEDx pin to VOUT
protection in case of a connector short.
In case some of the LEDs in an LED string are shorted, the voltage at the corresponding LEDx pin will increase. Any LEDx pin
that has a voltage exceeding VLEDx(SC) will be removed from
operation. This will prevent the IC from dissipating too much
power by having a large voltage present on an LEDx pin.
At least one LED must be in regulation for the LED string shortdetect protection to activate. In case all of the LED pins are above
regulation voltage (this could happen when the input voltage
rises too high for the LED strings), they will continue to operate
normally.
Figure 20: Disabling of LED1 String when the LED1 Pin
Voltage is Increased Above 4.6 V
While the IC is being PWM dimmed, the IC will recheck the disabled LED every time the PWM signal goes high to prevent false
tripping of LED short. This also allows for some self-correction if
an intermittent LED pin short-to-VOUT is present.
Overvoltage Protection
The A8518 has output overvoltage protection (OVP) and open
Schottky diode protection (secondary OVP). The OVP pin has a
threshold level of 8.3 V. A resistor can be used to set the output
overvoltage protection threshold up to approximately 40 V. This
is sufficient for driving 11 white LED in series.
The formula for calculating the OVP resistor is shown below:
ROVP =
(VOVP – VOVP(th))
IOVP(th)
where VOVP(th) = 8.3 V typical and IOVP(th) = 200 μA typical.
The OVP function is not inherently a latched fault. If the OVP
condition occurs during a load dump, the IC will stop switching
but not shut down.
There are several possibilities why an OVP condition is encountered during operation, the two most common being an open LED
string and a disconnected output condition.
Figure 21 illustrates when the output of the A8518 is disconnected from load during normal operation. The output voltage
instantly increases up to OVP voltage level, and then the boost
stops switching to prevent damage to the IC. When the output
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A8518 and A8518-1
voltage decreases to a low value, the boost converter will begin
switching. If the condition that caused the OV event still exists,
OVP will be triggered again.
Wide Input Voltage Range, High-Efficiency,
Fault-Tolerant LED Driver
VSW
The A8518 also has built-in secondary overvoltage protection to
protect the internal switch in the event of an open-diode condition. Open Schottky diode detection is implemented by detecting
overvoltage on the SW pin of the device. If voltage on the SW
pin exceeds the device’s safe operating voltage rating, the A8518
disables and remains latched. To clear this fault, the IC must be
shut down by either using the PWM signal or by going below the
UVLO threshold on the VIN pin.
VPWM
Figure 23 illustrates open Schottky diode protection while the
IC is in normal operation. As soon as the switch node voltage
(SW) exceeds 48 V, the IC will shut down. Due to small delays
in the detection circuit, as well as there being no load present, the
switch node voltage (VSW) will rise above the trip point voltage.
VOUT
Open diode detected VOUT
ILED(TOTAL)
VSW
Figure 21: Output of A8518 when Disconnetced from
Load During Normal Operation
Figure 22 illustrates a typical OVP condition caused by an open
LED string. Once the OVP is detected, the boost stops switching,
and the open LED string is removed from operation. Afterwards,
VOUT is allowed to fall, the boost will resume switching, and the
A8518 will resume normal operation.
VPWM
ILED(TOTAL)
VOUT
Figure 23: Open Schottky Diode Protection
VSW
VPWM
When enabling the A8518 into an open-diode condition, the IC
will first go through all of its initial LED detection and will then
check the boost output voltage. At that point, the open diode is
detected.
Boost Switch Overcurrent Protection
ILED(TOTAL)
The boost switch is protected with cycle-by-cycle current limiting set at a minimum of 3 A. Figure 24 illustrates the normal
operation of the switch node (VSW), inductor current, and output
voltage (VOUT) for an 11×2 LED configuration.
Figure 22: Typical OVP Condition Caused by an Open
LED String
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A8518 and A8518-1
VOUT
VSW
Wide Input Voltage Range, High-Efficiency,
Fault-Tolerant LED Driver
There is also a secondary current limit (ISW(LIM2)) that is sensed
through the boost switch. This current limit, once detected,
immediately shuts down the A8518. The level of this current limit
is set above the cycle-by-cycle current limit to protect the switch
from destructive currents when the boost inductor is shorted.
Figure 26 shows the secondary boost switch OCP. Once this limit
is reached, the A8518 will immediately shut down.
VOUT
VSW
Inductor Current
VPWM
Inductor Current
VPWM
Figure 24: Normal Operation of Switch Node
(VSW), Inductor Current and Output Voltage (VOUT)
Figure 25 illustrates the cycle-by-cycle current limit showing the
inductor current as a green trace. Note that the inductor current is
truncated and as a result the output voltage is reduced compared
to normal operation shown for the 11×2 LED configuration.
Inductor Current Current is truncated
VOUT
Figure 26: Secondary Boost Switch OCP
Input Overcurrent Protection and Disconnect
Switch
VIN
RSC
To L1
Q1
Radj
VSW
Iadj
VPWM
Figure 25: Cycle-by-Cycle Current Limit
GND
VSENSE
VIN
GATE
A8518
Figure 27: Typical Circuit Showing Implementation of
Input Disconnect Feature
The primary function of the input disconnect switch is to protect
the system and the device from catastrophic input currents during
a fault condition.
If the input current level goes above the preset current limit
threshold, the part will be shut down in less than 3 μs—this is a
latched condition. The fault flag is also set low to indicate a fault.
This protection feature prevents catastrophic failure in the system
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A8518 and A8518-1
due to a short of the inductor, inductor short to GND, or short at
the output to GND. Figure 28 illustrates the typical input overcurrent fault condition. As soon as input OCP limit is reached, the
part disables the gate of the disconnect switch Q1.
PWM
Wide Input Voltage Range, High-Efficiency,
Fault-Tolerant LED Driver
Input UVLO
When VIN and VSENSE rise above VUVLOrise threshold, the A8518
is enabled. The A8518 is disabled when VIN falls below VUVLOfall
threshold for more than 50 μs. This small delay is used to avoid
shutting down because of momentary glitches in the input power
supply.
Figure 29 illustrates a shutdown showing a falling input voltage
(VIN). When VIN falls below 3.90 V, the IC will shut down.
VGATE
VIN
VOUT
ILED(TOTAL)
Input Current
VVDD
Inductor Current
Figure 28: Startup into Output Shorted to GND Fault.
Input OCP tripped at 4 A (RSC = 0.024 Ω, Radj = 383 Ω)
Setting the Current Sense Resistor
As shown in Figure 27:
Figure 29: Shutdown with Falling Input Voltage
VIN – VSENSE = VSC + Iadj × Radj
or
ISC = ((VIN – VSENSE) – Iadj × Radj)/RSC
where VSC = the voltage drop across RSC. The typical threshold
for the current sense is VIN – VSENSE = 110 mV when Radj is 0 Ω.
The A8518 can have this voltage trimmed using the Radj resistor.
It is recommended to set the trip point to be above 3.65 A to avoid
conflicts with the cycle-by-cycle current limit typical threshold. A
sample calculation is done below for 4.25 A of input current.
The calculated max value of sense resistor RSC = 0.11 V/4.25 A =
0.0259 Ω.
The Rsc chosen is 0.024 Ω, a standard value. Therefore, the voltage drop across RSC is:
VSC = 4.25 A × 0.024 Ω = 0.102 V
Radj =
Radj =
VSENSE(trip) – VSC
VDD
The VDD pin provides regulated bias supply for internal circuits.
Connect a CVDD capacitor with a value of 1 μF or greater to this
pin. The internal LDO can deliver no more than 2 mA of current
with a typical VDD voltage of about 3.5 V, enabling this pin to
serve as the pull-up voltage for the fault pin.
Shutdown
If PWM pin is pulled low for more than tPWML (16 ms), the
device enters shutdown mode and clears all internal fault registers. When shut down, the IC will disable all current sources and
wait until the PWM goes high to re-enable the IC.
Figure 30 depicts the shutdown using the PWM, showing the
16 ms delay between PWM signal and when the VDD and GATE
of disconnect switch turn off.
Iadj
0.11 V – 0.102 V
= 372 Ω
21.5 µA
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A8518 and A8518-1
Wide Input Voltage Range, High-Efficiency,
Fault-Tolerant LED Driver
VGATE
VVDD
ILED(TOTAL)
VPWM
Figure 30: Shutdown Using the Enable
Dithering Feature (A8518 only)
To minimize the switching frequency harmonics, a dithering
feature is implemented in A8518. This feature simplifies the input
filters needed to meet the automotive CISPR 25 conducted and
radiated emission limits. The dithering sweep is internally set
at ±5%. The switching frequency will ramp from 0.95 times the
programmed frequency to 1.05 times the programmed frequency.
The rate or modulation at which the frequency sweeps is governed by an internal 12.5 kHz triangle pattern.
VSW
Figure 31: Minimum Dithering Switching Frequency =
2.02 MHz at VIN = 12 V, and PWM Ratio = 100%
VSW
Figure 32: Maximum Dithering Switching Frequency =
2.23 MHz at VIN = 12 V, and PWM Ratio = 100%
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A8518 and A8518-1
Wide Input Voltage Range, High-Efficiency,
Fault-Tolerant LED Driver
Fault Protection During Operation
VSW
VOUT
The A8518 constantly monitors the state of the system to determine if any fault conditions occur during normal operation. The
response to a triggered fault condition is summarized in Table 3.
There are several points at which the A8518 monitors for faults
during operation. The locations are input current, switch current,
output voltage, and LED pins.
Note:
Some protection features might not be active during startup
to prevent false triggering of fault conditions.
The detectable faults are:
• Open LED pin
• Shorted LED pin to GND
Figure 33: Output Voltage Ripple Frequency Due to
Dithering = 12.4 kHz at VIN = 12 V, and PWM Ratio =
100%
VSW
VOUT
• Open or shorted inductor
• Open or shorted boost diode
• VOUT pin shorted to GND
• SW pin shorted to GND
• ISET pin shorted to GND
Note:
Some faults will not be protected if the input disconnect
switch is not used. An example of this is VOUT pin shorted to
GND.
Figure 34: Output Voltage Ripple Amplitude Due to
Dithering = 100 mV at VIN = 12 V, and PWM Ratio =
100%
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A8518 and A8518-1
Wide Input Voltage Range, High-Efficiency,
Fault-Tolerant LED Driver
Table 3: Fault Mode Table
Fault Name
Type
Primary Switch
Overcurrent
Protection (cycleby-cycle current
limit)
Autorestart
Secondary Switch
Current Limit
Input Disconnect
Current Limit
Secondary OVP
LEDx Pin Short
Protection
Latched
Latched
Latched
Autorestart
Active
Always
Always
Always
Always
Startup
Normal
operation
Fault
Flag
Set
Description
Boost
Disconnect
Switch
LED
Sink
Drivers
NO
This fault condition is triggered when the SW current
exceeds the cycle-by-cycle current limit, ISW(LIM).The
present SW on-time is truncated immediately to limit the
current. Next switching cycle starts normally.
Off for
a single
cycle
ON
ON
YES
When current through boost switch exceeds secondary
SW current limit (ISW(LIM2)), the device immediately shuts
down the disconnect switch, LED drivers and boost.
The Fault flag is set. To re-enable the part, the PWM pin
needs to be pulled low for 32,750 clock cycles.
OFF
OFF
OFF
YES
The device is immediately shut off if the voltage
across the input sense resistor is above the
VSENSE(trip) threshold. To re-enable the device, the PWM
pin must be pulled low for 32,750 clock cycles.
OFF
OFF
OFF
YES
Secondary overvoltage protection is used for open-diode
detection. When diode D1 opens, the SW pin voltage
will increase until VOVP(sec) is reached. This fault latches
the IC. The input disconnect switch is disabled as well
as the LED drivers. To re-enable the part, the PWM pin
needs to be pulled low for 32,750 clock cycles.
OFF
OFF
OFF
NO
This fault prevents the part from starting up if any of
the LED pins are shorted. The part stops soft-start from
starting while any of the LED pins are determined to be
shorted. Once the short is removed, soft-start is allowed
to start.
OFF
ON
OFF
NO
When an LED pin is open, the device will determine
which LED pin is open by increasing the output voltage
until OVP is reached. Any LED string not in regulation
will be turned OFF. The device will then go back to
normal operation by reducing the output voltage to the
appropriate voltage level.
ON
ON
OFF for
open
pins,
ON
for all
others
NO
Fault occurs when the ISET current goes above 150% of
max current. The boost will stop switching and the IC will
disable the LED sinks until the fault is removed. When
the fault is removed, the IC will try to regulate to the
preset LED current.
OFF
ON
OFF
STOP
during
OVP event
ON
ON
OFF
ON
OFF
LEDx Pin Open
Autorestart
ISET Short
Protection
Autorestart
Overvoltage
Protection
Autorestart
Always
NO
Fault occurs when OVP pin exceeds VOVP(th) threshold.
The IC will immediately stop switching to try to reduce
the output voltage. If the output voltage decreases,
then the IC will restart switching to regulate the output
voltage.
Undervoltage
Protection
Autorestart
Always
YES
Device immediately shuts off boost and current sinks
if the voltage at OVP pin is below VUVP(th). It will autorestart once the fault is removed.
ON
ON
OFF for
shorted
pins, ON
for all
others
Always
LED String Short
Detection
Autorestart
Always
NO
Fault occurs when the LED pin voltage exceeds
5.2 V. Once the LED string short fault is detected, the
LED string above the threshold will be removed from
operation.
Overtemperature
Protection
Autorestart
Always
NO
Fault occurs when the die temperature exceeds the
overtemperature threshold, typically 170ºC.
OFF
OFF
OFF
VIN UVLO
Autorestart
Always
NO
Fault occurs when VIN drops below VUVLOfall, typically
3.9 V. This fault resets all latched faults.
OFF
OFF
OFF
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Wide Input Voltage Range, High-Efficiency,
Fault-Tolerant LED Driver
A8518 and A8518-1
APPLICATION INFORMATION
Design Example
sheet’s Electrical Characteristics table.
This section provides a method for selecting component values
when designing an application using the A8518.
Assumptions: For the purposes of this example, the following are
given as the application requirements:
• VIN: 10 to 14 V
• Quantity of LED channels, #CHANNELS: 2
• Quantity of series LEDs per channel, #SERIESLEDS: 10
• LED current per channel, ILED: 120 mA
• Vf at 120 mA: 3.2 V
• fSW: 2 MHz
• PWM dimming frequency 200 Hz 1% Duty cycle
ROVP =
37.85 V – 8.3 V
= 147.75 k
0.200 mA
Chose a value of resistor that is a higher value than the calculated
ROVP. In this case, a value of 158 kΩ was selected. Below is the
actual value of the minimum OVP trip level with the selected
resistor.
VOUT(ovp) = 158 kΩ × 0.200 mA + 8.3 V
VOUT(ovp) = 39.9 V
Step 3b: At this point, a quick check needs to be done to see
if the conversion ratio is adequate for the running switching
frequency. Where VD is the diode forward voltage, minimum offtime (tSW(off)) is found in the datasheet:
Step 1: Connect LED strings to pins LED1 and LED2.
DMAX(boost) = 1 – tSW(off) × fSW(max)
Step 2: Determine the LED current set resistor RISET:
DMAX(boost) = 1 – (0.085 µs × 2.2 MHz) = 0.813
RISET =
RISET =
(VISET × AISET )
ILED
(1.017 × 1419)
= 12 kΩ
0.120
RISET = 11.8 kΩ
Step 3a: Determining the OVP resistor.
The OVP resistor is connected between the OVP pin and the
output voltage of the converter. The first step is to determine the
maximum voltage based on the LED requirements. The regulation voltage for an LED pin (VLEDx) of the A8518 is 0.85 mV. A
5 V headroom is added to give margin to the design due to noise
and output voltage ripple.
VOUT(ovp) = #SERIESLEDS × Vf + VLED + 5 V
VOUT(ovp) = 10 × 3.2 V + 0.85 V + 5 V
VOUT = 37.85 V
The OVP resistor is:
ROVP =
(VOUT(ovp) – VOVP(th))
IOVP(th)
where both IOVP(th) and VOVP(th) values are taken from the data-
Theoretical Max VOUT =
VIN(min)
1 – DMAX(boost)
– VD
VD is the voltage drop of the boost diode.
Theoretical Max VOUT =
10 V
1 – .813
– 0.4 = 53.1 V
Theoretical Max VOUT value needs to greater than the value
VOUT(ovp). If this is not the case, then either the minimum input
voltage needs to be increased, or the number of series LEDs and
VOUT(ovp) need to be reduced.
Step 4: Inductor selection.
The inductor needs to be chosen such that it can handle the necessary input current. In most applications, due to stringent EMI
requirements, the system needs to operate in continuous conduction mode throughout the whole input voltage range.
Step 4a: Determine the Duty Cycle.
DMAX = 1 –
DMAX = 1 –
VIN(min)
(VOUT(ovp) + VD )
10
(39.9 + 0.4)
= 0.75
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A8518 and A8518-1
A good approximation of efficiency h can be taken from the
efficiency curves located on page 10. A value of 90% is a good
starting approximation.
Step 4b: Determine the maximum and minimum input current to
the system. The minimum input current will dictate the inductor
value. The maximum current rating will dictate the current rating
of the inductor.
IIN(max) =
VOUT(ovp) × IOUT
IOUT = 2 × 0.120 A = 0.240 A
39.9 V × 0.24 A
= 1.06 A
10 V × 0.90
IIN(min) =
Double-check to make sure that ½ current ripple is less than
IIN(min).
IIN(min) > ½ DIL
0.626 A > 0.165 A
10 µH was selected. At 10 µH:
IL
IL = 0.375 A
2
VOUT × IOUT
0.626 A > 0.19 A
A good inductor value to use would be 10 µH.
Step 4d: This step is used to verify that there is sufficient slope
compensation for the inductor chosen. The implemented slope
compensation is 6 A/µs.
Next, insert the inductor value used in the design:
ΔIL(used) =
VIN(max) × η
ΔIL(used) =
VIN(min) × DMAX
L(used) × fSW
10 V × 0.75
10 µH × 2.0 MHz
VOUT = 10 × 3.2 + 0.85 = 32.85 V
IIN(min) =
32.85 V × 240 mA
= 0.625 A
14 V × 0.90
Step 4c: Determining the inductor value.
To ensure that the inductor operates in continuous conduction
mode, the value of inductor needs to be set such that the ½ inductor ripple current is not greater than the average minimum input
current. A first pass calculation for Kripple should be 30% of the
maximum inductor current.
ΔI L = IIN(max) × Kripple
ΔI L = 1.06 A × 0.3 = 0.318 A
L=
L=
= 0.19 A
VIN(min) × η
IOUT = #Channels × ILED
IIN(max) =
Wide Input Voltage Range, High-Efficiency,
Fault-Tolerant LED Driver
(VIN(min) × DMAX)
IL × fSW )
Required Min Slope =
= 0.375 A
ΔIL(used) × ΔS × 10 -6
1
× (1 – DMAX)
fSW
where ΔS is taken from the following formula:
ΔS = 1 –
0.18
DMAX
ΔS = 0.76
0.375×(0.76 × 10 )
= 2.28 A/µs
1
× (1 – 0.75)
2.0 MHz
-6
Required Min Slope =
If the required minimum slope is larger than the calculated slope
compensation, the inductor value needs to be increased.
10 V
× 0.75 = 11.79 µH
0.318 A × 2 MHz
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A8518 and A8518-1
Step 4e: Determining the inductor current rating.
IL(min) = IIN(max) + ½ ΔI L
IL(min) = 1.06 +
0.375 A
= 1.25 A
2
Wide Input Voltage Range, High-Efficiency,
Fault-Tolerant LED Driver
The selected diode leakage current at a 150°C junction temperature and 30 V output is 100 μA, and the maximum leakage
current through OVP pin is 1 μA. The total leakage current can be
calculated as follows:
ILK = ILKG(diode) + ILKG(ovp)
= 100 μA + 1 μA
Step 5: Choosing the proper output Schottky diode.
The diode needs to be chosen for three characteristics when it is
used in LED lighting circuitry. The most obvious two are the current rating of the diode and the reverse voltage rating. The reverse
voltage rating should be larger than the maximum output voltage
VOVP. The peak current through the diode is:
IL(used)
ID(pk) = IIN(max) +
2
ID(pk) = 1.06 +
0.375 A
= 1.25 A
2
The other major factor in deciding the boost diode is the reverse
current characteristic of the diode. This characteristic is especially important when PWM dimming is implemented. During
PWM off-time, the boost converter is not switching. This results
in a slow bleeding off of the output voltage due to leakage currents. IR or reverse current can be a large contributor, especially
at high temperatures. The reverse current of the selected diode
varies between 1 and 100 µA. For higher efficiency, use a low
forward voltage drop Schottky diode. For better EMI performance, use a small junction capacitor Schottky diode.
Step 6: Choosing the output capacitors.
The output capacitors need to be chosen such that they can
provide filtering for both the boost converter and for the PWM
dimming function. The biggest factors that contribute to the size
of the output capacitor are PWM dimming frequency and the
PWM duty cycle. Another major contributor is leakage current
(ILK). This current is the combination of the OVP current sense as
well as the reverse current of the boost diode. In this design, the
PWM dimming frequency is 200 Hz and the minimum duty cycle
is 0.02%. Typically, the voltage variation on the output during
PWM dimming needs to be less than 250 mV (VCOUT) so there is
no audible hum.
COUT = ILK ×
(1 – minimum dimming duty cycles)
PWM dimming frequency × VCOUT
= 101 μA
COUT = 101 µA ×
(1 – 0.02)
= 2 µF
200 Hz × 0.250 V
A capacitor larger than 2 µF should be selected. Due to degradation of capacitance at dc voltages, a 4.7 µF / 50 V capacitor is a
good choice.
Vendor
Value
Part Number
Murata
4.7 µF / 50 V
GRM21BC81H475KE11K
It is also necessary to note that if a high dimming ratio of 5000:1
must be maintained at lower input voltages, then larger output capacitors will be needed. 4 × 4.7 µF / 50 V / X6S / 0805
capacitors are chosen; 0805 size is selected to minimize possible
audible noise.
The RMS current through the capacitor is given by:
COUT(rms) = IOUT ×
COUT(rms) = 0.240 ×
IL(used)
IIN(max) × 12
1 – DMAX
DMAX +
0.375
1.06 × 12
= 0.424 A
1 – 0.75
0.75 +
The output capacitor needs to have a current rating of at least
0.424 A. The capacitors selected in this design, 4 × 4.7 µF / 50 V,
have a combined current rating of 3 A.
Step 7: Selection of input capacitor.
The input capacitor needs to be selected such that it provides
good filtering of the input voltage waveform. A good rule of
thumb is to set the input voltage ripple ΔVIN to be 1% of the
minimum input voltage. The minimum input capacitor requirements are as follows:
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Wide Input Voltage Range, High-Efficiency,
Fault-Tolerant LED Driver
A8518 and A8518-1
CIN =
CIN =
Step 8: Choosing the input disconnect switch components.
ΔIL(used)
8 × f SW × ΔVIN
Set the input disconnect current limit to 4.25 A.
0.375 A
= 0.234 µF
8 × 2 MHz × 0.1 V
CIN(rms) =
ΔIL(used)
IOUT × I
IN(max)
RSC =
The chosen RSC is 0.024 Ω. The trip point voltage needs to be:
(1 – D MAX )× 12
= 0.1 A
VSC = 4.25 A× 0.024 Ω = 0.102 V
0.375 A
0.240 A ×
1.06 A
CIN(rms) =
= 0.1 A
(1 – 0.75) × 12
Radj =
Radj =
A good ceramic input capacitor with ratings of 50 V / 2.2 µF or
50 V / 4.7 µF will suffice for this application.
Vendor
Value
0.11 V
= 0.0259 Ω
4.25 A
Murata
4.7 µF / 50 V
GRM32ER71H475KA88L
2.2 µF / 50 V
GRM31CR71H225KA88L
Iadj
0.11 V – 0.102 V
= 372 Ω
21.5 µA
A value of 383 Ω was chosen for this design. The disconnect
switch Q1 works as on or off. Therefore, the Radj value is not
critical.
Part Number
Murata
VVSENSE(trip) – VSC
For the input disconnect switch, an AO4421 6.2 A / 60 V P-channel MOSFET is selected.
If long wires are used for the input, it is necessary to use a much
larger input capacitor. A larger input capacitor is also required to
have stable input voltage during line transients. Combinations of
aluminum electrolytic and ceramic capacitors can be used.
To achieve proper operation at low dimming ratios, connect an
RC filter to the VOUT pin. Use R = 10 kΩ and C = 47 pF.
*optional
VIN = (4.5 to 40)V
10 µH
D1
VOUT > VIN
0.024 Q1
383 4.7 µF
158 k
10 µF
GATE
VSENSE
SW
10 µF
VOUT
VIN
OVP
VDD
VC
1 µF
LED1
10 k
FAULT
EN/PWM
APWM
LED2
ISET
AGND PGND
COMP
100 pF
11.8 k
169 0.068 F
Figure 35: Schematic Showing Calculated Values from the Design Example Above
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Wide Input Voltage Range, High-Efficiency,
Fault-Tolerant LED Driver
A8518 and A8518-1
Package Outline Diagram
For Reference Only – Not for Tooling Use
(Reference MO-153 ABT)
Dimensions in millimeters. NOT TO SCALE
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
0.65
0.45
8º
0º
5.00 ±0.10
16
16
0.20
0.09
1.70
B
3 NOM 4.40 ±0.10
3.00
6.40 ±0.20
A
6.10
0.60 ±0.15
1.00 REF
1
2
3 NOM
1
0.25 BSC
2
Branded Face
3.00
SEATING PLANE
C
16X
0.10
SEATING
PLANE
C
0.30
0.19
GAUGE PLANE
C
1.20 MAX
0.65 BSC
NNNNNNN
YYWW
LLLL
0.15
0.00
A
Terminal #1 mark area
B
Exposed thermal pad (bottom surface); dimensions may vary with device
C
Reference land pattern layout (reference IPC7351 SOP65P640X110-17M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
D
PCB Layout Reference View
1
D Standard Branding Reference View
N = Device part number
= Supplier emblem
Y = Last two digits of year of manufacture
W = Week of manufacture
L = Characters 5-8 of lot number
Branding scale and appearance at supplier discretion
Package LP, 16-Pin TSSOP with Exposed Thermal Pad
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Wide Input Voltage Range, High-Efficiency,
Fault-Tolerant LED Driver
A8518 and A8518-1
Revision History
Rev. No.
Rev. Date
–
September 29, 2014
1
March 18, 2015
2
November 4, 2015
Description
Initial Release
Revised OVP Thresholds
Amended “Enabling the IC” (page 12) and “Synchronization” (page 15) of Functional Description;
inserted Figures 13 and 14; updated Selection Guide table (page 2); corrected 2nd Typical Application
Drawing (page 9)
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the information being relied upon is current.
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