8673EQxxB

GS8673EQ18/36BK-675/625/550/500
72Mb SigmaQuad-IIIe™
Burst of 2 ECCRAM™
260-Ball BGA
Commercial Temp
Industrial Temp
675 MHz–500 MHz
1.35V VDD
1.2V to 1.5V VDDQ
Features
Clocking and Addressing Schemes
• On-Chip ECC with virtually zero SER
• Configurable Read Latency (3.0 or 2.0 cycles)
• Simultaneous Read and Write SigmaQuad-IIIe™ Interface
• Separate I/O Bus
• Double Data Rate interface
• Burst of 2 Read and Write
• Pipelined read operation
• Fully coherent Read and Write pipelines
• 1.35V nominal VDD
• 1.2V JESD8-16A BIC-3 Compliant Interface
• 1.5V HSTL Interface
• ZQ pin for programmable output drive impedance
• ZT pin for programmable input termination impedance
• Configurable Input Termination
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 260-ball, 14 mm x 22 mm, 1 mm ball pitch BGA package
–K: 5/6 RoHS-compliant package
–GK: 6/6 RoHS-compliant package
The GS8673EQ18/36BK SigmaQuad-IIIe ECCRAMs are
synchronous devices. They employ dual, single-ended master
clocks, CK and CK. These clocks are single-ended clock
inputs, not differential inputs to a single differential clock input
buffer. CK and CK are used to control the address and control
input registers, as well as all output timing.
The KD and KD clocks are dual mesochronous (with respect to
CK and CK) input clocks that are used to control the data input
registers. Consequently, data input setup and hold windows
can be optimized independently of address and control input
setup and hold windows.
SigmaQuad-IIIe™ Family Overview
SigmaQuad-IIIe ECCRAMs are the Separate I/O half of the
SigmaQuad-IIIe/SigmaDDR-IIIe family of high performance
ECCRAMs. Although very similar to GSI's second generation
of networking SRAMs (the SigmaQuad-II/SigmaDDR-II
family), these third generation devices offer several new
features that help enable significantly higher performance.
Each internal read and write operation in a SigmaQuad-IIIe B2
ECCRAM is two times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore, the address
field of a SigmaQuad-IIIe B2 ECCRAM is always one address
pin less than the advertised index depth (e.g. the 4M x 18 has
2M addressable index).
On-Chip Error Correction Code
GSI's ECCRAMs implement an ECC algorithm that detects
and corrects all single-bit memory errors, including those
induced by Soft Error Rate (SER) events such as cosmic rays,
alpha particles, etc. The resulting SER of these devices is
anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude
improvement over comparable SRAMs with no On-Chip ECC,
which typically have an SER of 200 FITs/Mb or more. SER
quoted above is based on reading taken at sea level.
Parameter Synopsis
Speed Bin
Operating Frequency
Data Rate (per pin)
Read Latency
VDD
-675
675 / 450 MHz
1350 / 900 Mbps
3.0 / 2.0
1.3V to 1.4V
-625
625 / 400 MHz
1250 / 800 Mbps
3.0 / 2.0
1.3V to 1.4V
-550
550 / 375 MHz
1100 / 750 Mbps
3.0 / 2.0
1.25V to 1.4V
-500
500 / 333 MHz
1000 / 666 Mbps
3.0 / 2.0
1.25V to 1.4V
Note: Please contact GSI for availability of 714 MHz devices.
Rev: 1.06 5/2012
1/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS8673EQ18/36BK-675/625/550/500
4M x 18 (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
A
VDD
VDDQ
VDD
VDDQ
MCL
MCH
(CFG)
MCL
ZQ
PZT1
VDDQ
VDD
VDDQ
VDD
B
VSS
NUO
VSS
NUI
MVQ
MCL
(B4M)
NC
(RSVD)
MCH
(SIOM)
PZT0
D0
VSS
Q0
VSS
C
Q17
VDDQ
D17
VDDQ
VSS
SA
VDD
SA
VSS
VDDQ
NUI
VDDQ
NUO
D
VSS
NUO
VSS
NUI
SA
VDDQ
NC
(288 Mb)
VDDQ
NC
(144 Mb)
D1
VSS
Q1
VSS
E
Q16
VDDQ
D16
VDD
VSS
SA
VSS
SA
VSS
VDD
NUI
VDDQ
NUO
F
VSS
NUO
VSS
NUI
SA
VDD
VDDQ
VDD
SA
D2
VSS
Q2
VSS
G
Q15
NUO
D15
NUI
VSS
SA
MZT1
SA
VSS
D3
NUI
Q3
NUO
H
Q14
VDDQ
D14
VDDQ
SA
VDDQ
W
VDDQ
SA
VDDQ
NUI
VDDQ
NUO
J
VSS
NUO
VSS
NUI
VSS
SA
VSS
SA
VSS
D4
VSS
Q4
VSS
K
CQ1
VDDQ
VREF
VDD
KD1
VDD
CK
VDD
KD0
VDD
VREF
VDDQ
CQ0
L
CQ1
VSS
QVLD1
Vss
KD1
VDDQ
CK
VDDQ
KD0
VSS
QVLD0
VSS
CQ0
M
VSS
Q13
VSS
D13
VSS
SA
VSS
SA
VSS
NUI
VSS
NUO
VSS
N
NUO
VDDQ
NUI
VDDQ
DLL
VDDQ
R
VDDQ
MCH
VDDQ
D5
VDDQ
Q5
P
NUO
Q12
NUI
D12
VSS
SA
MZT0
SA
VSS
NUI
D6
NUO
Q6
R
VSS
Q11
VSS
D11
MCH
VDD
VDDQ
VDD
RST
NUI
VSS
NUO
VSS
T
NUO
VDDQ
NUI
VDD
VSS
SA
VSS
SA
VSS
VDD
D7
VDDQ
Q7
U
VSS
Q10
VSS
D10
NUI
VDDQ
ADZT1
VDDQ
NUI
NUI
VSS
NUO
VSS
V
NUO
VDDQ
NUI
VDDQ
VSS
SA
(x18)
VDD
SA
(B2)
VSS
VDDQ
D8
VDDQ
Q8
W
VSS
Q9
VSS
D9
TCK
RLM0
NC
(RSVD)
MCL
TMS
NUI
VSS
NUO
VSS
Y
VDD
VDDQ
VDD
VDDQ
TDO
ZT
RLM1
MCL
TDI
VDDQ
VDD
VDDQ
VDD
Notes:
1. Pins 5A and 7A are reserved for future use. They must be tied Low in this device.
2. Pins 5R and 9N are reserved for future use. They must be tied High in this device.
3. Pin 6A is defined as mode pin CFG in the pinout standard. It must be tied High in this device to select x18 configuration.
4. Pin 8B is defined as mode pin SIOM in the pinout standard. It must be tied High in this device to select Separate I/O configuration.
5. Pin 6B is defined as mode pin B4M in the pinout standard. It must be tied Low in this device to select Burst-of-2 configuration.
6. Pin 6V is defined as address pin SA for x18 devices. It is used in this device.
7. Pin 8V is defined as address pin SA for B2 devices. It is used in this device.
8. Pin 9D is reserved as address pin SA for 144 Mb devices. It is a true no connect in this device.
9. Pin 7D is reserved as address pin SA for 288 Mb devices. It is a true no connect in this device.
10. Pins 5U and 9U are unused in this device. They must be left unconnected or driven Low.
11. Pins 8W and 8Y are reserved for internal use only. They must be tied Low.
12. Pins 7B and 7W are reserved for future use. They are true no connects in this device.
Rev: 1.06 5/2012
2/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS8673EQ18/36BK-675/625/550/500
2M x 36 (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
A
VDD
VDDQ
VDD
VDDQ
MCL
MCL
(CFG)
MCL
ZQ
PZT1
VDDQ
VDD
VDDQ
VDD
B
VSS
Q35
VSS
D35
MVQ
MCL
(B4M)
NC
(RSVD)
MCH
(SIOM)
PZT0
D0
VSS
Q0
VSS
C
Q26
VDDQ
D26
VDDQ
VSS
SA
VDD
SA
VSS
VDDQ
D9
VDDQ
Q9
D
VSS
Q34
VSS
D34
SA
VDDQ
NC
(288 Mb)
VDDQ
NC
(144 Mb)
D1
VSS
Q1
VSS
E
Q25
VDDQ
D25
VDD
VSS
SA
VSS
SA
VSS
VDD
D10
VDDQ
Q10
F
VSS
Q33
VSS
D33
SA
VDD
VDDQ
VDD
SA
D2
VSS
Q2
VSS
G
Q24
Q32
D24
D32
VSS
SA
MZT1
SA
VSS
D3
D11
Q3
Q11
H
Q23
VDDQ
D23
VDDQ
SA
VDDQ
W
VDDQ
SA
VDDQ
D12
VDDQ
Q12
J
VSS
Q31
VSS
D31
VSS
SA
VSS
SA
VSS
D4
VSS
Q4
VSS
K
CQ1
VDDQ
VREF
VDD
KD1
VDD
CK
VDD
KD0
VDD
VREF
VDDQ
CQ0
L
CQ1
VSS
QVLD1
VSS
KD1
VDDQ
CK
VDDQ
KD0
VSS
QVLD0
VSS
CQ0
M
VSS
Q22
VSS
D22
VSS
SA
VSS
SA
VSS
D13
VSS
Q13
VSS
N
Q30
VDDQ
D30
VDDQ
DLL
VDDQ
R
VDDQ
MCH
VDDQ
D5
VDDQ
Q5
P
Q29
Q21
D29
D21
VSS
SA
MZT0
SA
VSS
D14
D6
Q14
Q6
R
VSS
Q20
VSS
D20
MCH
VDD
VDDQ
VDD
RST
D15
VSS
Q15
VSS
T
Q28
VDDQ
D28
VDD
VSS
SA
VSS
SA
VSS
VDD
D7
VDDQ
Q7
U
VSS
Q19
VSS
D19
NUI
VDDQ
ADZT1
VDDQ
NUI
D16
VSS
Q16
VSS
V
Q27
VDDQ
D27
VDDQ
VSS
NUI
(x18)
VDD
SA
(B2)
VSS
VDDQ
D8
VDDQ
Q8
W
VSS
Q18
VSS
D18
TCK
RLM0
NC
(RSVD)
MCL
TMS
D17
VSS
Q17
VSS
Y
VDD
VDDQ
VDD
VDDQ
TDO
ZT
RLM1
MCL
TDI
VDDQ
VDD
VDDQ
VDD
Notes:
1. Pins 5A and 7A are reserved for future use. They must be tied Low in this device.
2. Pins 5R and 9N are reserved for future use. They must be tied High in this device.
3. Pin 6A is defined as mode pin CFG in the pinout standard. It must be tied Low in this device to select x36 configuration.
4. Pin 8B is defined as mode pin SIOM in the pinout standard. It must be tied High in this device to select Separate I/O configuration.
5. Pin 6B is defined as mode pin B4M in the pinout standard. It must be tied Low in this device to select Burst-of-2 configuration.
6. Pin 6V is defined as address pin SA for x18 devices. It is unused in this device, and must be left unconnected or driven Low.
7. Pin 8V is defined as address pin SA for B2 devices. It is used in this device.
8. Pin 9D is reserved as address pin SA for 144 Mb devices. It is a true no connect in this device.
9. Pin 7D is reserved as address pin SA for 288 Mb devices. It is a true no connect in this device.
10. Pins 5U and 9U are unused in this device. They must be left unconnected or driven Low.
11. Pins 8W and 8Y are reserved for internal use only. They must be tied Low.
12. Pins 7B and 7W are reserved for future use. They are true no connects in this device.
Rev: 1.06 5/2012
3/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS8673EQ18/36BK-675/625/550/500
Pin Description
Symbol
Description
Type
Address—Read Address is registered on ↑CK and Write Address is registered on ↑CK.
Input
D[35:0]
Write Data—Registered on ↑KD and ↑KD during Write operations.
D[17:0]—x18 and x36.
D[35:18]—x36 only.
Input
Q[35:0]
Read Data—Driven by ↑CK and ↑CK, and synchronized with ↑CQ and ↑CQ during Read operations.
Q[17:0]—x18 and x36.
Q[35:18]—x36 only.
Output
Read Data Valid—Driven high one half cycle before valid Read Data.
Output
SA
QVLD[1:0]
CK, CK
Primary Input Clocks—Dual single-ended. For Address and Control input latching, internal timing control,
and Read Data and Echo Clock output timing control.
Input
KD[1:0],
KD[1:0]
Write Data Input Clocks—Dual single-ended. For Write Data input latching.
KD0, KD0—latch Write Data (D[17:0] in x36, D[8:0] in x18).
KD1, KD1—latch Write Data (D[35:18] in x36, D[17:9] in x18).
Input
CQ[1:0],
CQ[1:0]
Echo Clocks—Free running source synchronous output clocks.
Output
R
Read Enable—Registered on ↑CK. R = 0 initiates a Read operation.
Input
W
Write Enable—Registered on ↑CK. W = 0 initiates a Write operation.
Input
Address and Write Data Input Termination Pull-Up Enable—Registered on↑CK.
ADZT1 = 0: enables termination pull-up on Address (SA), Write Data (D) inputs.
ADZT1 = 1: disables termination pull-up on Address (SA), Write Data (D) inputs.
Input
DLL
DLL Enable—Weakly pulled High internally.
DLL = 0: disables internal DLL.
DLL = 1: enables internal DLL.
Input
RST
Reset—Holds the device inactive and resets the device to its initial power-on state when asserted High.
Weakly pulled Low internally.
Input
Read Latency Select 1:0—Must be tied High or Low.
RLM[1:0] = 00: reserved.
RLM[1:0] = 01: selects 2.0 cycle Read Latency.
RLM[1:0] = 10: selects 3.0 cycle Read Latency.
RLM[1:0] = 11: reserved.
Input
ZQ
Output Driver Impedance Control Resistor Input—Must be connected to VSS through an external
resistor RQ to program output driver impedance.
Input
ZT
Input Termination Impedance Control Resistor Input—Must be connected to VSS through an external
resistor RT to program input termination impedance.
Input
ADZT1
RLM[1:0]
Rev: 1.06 5/2012
4/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS8673EQ18/36BK-675/625/550/500
Pin Description (Continued)
Symbol
Description
Type
MZT[1:0]
Input Termination Mode Select—Selects the termination mode used for all terminated inputs. Must be tied
High or Low.
MZT[1:0] = 00: disabled.
MZT[1:0] = 01: RT/2 Thevenin-equivalent (pull-up = RT, pull-down = RT).
MZT[1:0] = 10: RT Thevenin-equivalent (pull-up = 2*RT, pull-down = 2*RT).
MZT[1:0] = 11: reserved.
Input
PZT[1:0]
Input Termination Configuration Select—Selects which inputs are terminated. Must be tied High or Low.
PZT[1:0] = 00: Write Data only.
PZT[1:0] = 01: Write Data, Input Clocks.
PZT[1:0] = 10: Write Data, Address, Control.
PZT[1:0] = 11: Write Data, Address, Control, Input Clocks.
Input
MVQ
I/O Voltage Select—Indicates what voltage is supplied to the VDDQ pins. Must be tied High or Low.
MVQ = 0: Configure for 1.2V to 1.35V nominal VDDQ.
MVQ = 1: Configure for 1.5V nominal VDDQ.
Input
VDD
Core Power Supply—1.35V nominal core supply voltage.
—
VDDQ
I/O Power Supply—1.2V to 1.5V nominal I/O supply voltage. Configurable via MVQ pin.
—
VREF
Input Reference Voltage—Input buffer reference voltage.
—
VSS
Ground
—
TCK
JTAG Clock
Input
TMS
JTAG Mode Select—Weakly pulled High internally.
Input
TDI
JTAG Data Input—Weakly pulled High internally.
Input
TDO
JTAG Data Output
MCH
Must Connect High—May be tied to VDDQ directly or via a 1kΩ resistor.
Input
MCL
Must Connect Low—May be tied to VSS directly or via a 1kΩ resistor.
Input
NC
No Connect—There is no internal chip connection to these pins. They may be left unconnected, or tied High
or Low.
—
NUI
Not Used, Input—There is an internal chip connection to these input pins, but they are unused by the
device. They are pulled Low internally. They may be left unconnected or tied Low. They should not be tied
High.
Input
NUO
Not Used, Output—There is an internal chip connection to these output pins, but they are unused by the
device. Unused output pins are tri-stated internally. They should be left unconnected.
Output
Rev: 1.06 5/2012
Output
5/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS8673EQ18/36BK-675/625/550/500
Power Up Requirements
For reliability purposes, power supplies must power up simultaneously, or in the following sequence:
VSS, VDD, VDDQ, VREF and inputs.
Power supplies must power down simultaneously, or in the reverse sequence.
After power supplies power up, the following start-up sequence must be followed.
Step 1 (Recommended, but not required): Assert RST High for at least 1ms.
While RST is asserted high:
• The DLL is disabled, regardless of the state of the DLL pin.
• Read and Write operations are ignored.
Note: If possible, RST should be asserted High before input clocks (CK, CK, KD, KD) begin toggling, and remain asserted High
until input clocks are stable and toggling within specification, in order to prevent unstable, out-of-spec input clocks from causing
trouble in the SRAM.
Step 2: Begin toggling input clocks.
After input clocks begin toggling, but not necessarily within specification:
• Q are placed in the non-Read state, and remain so until the first Read operation.
• QVLD are driven Low, and remain so until the first Read operation.
• CQ, CQ begin toggling, but not necessarily within specification.
Step 3: Wait until input clocks are stable and toggling within specification.
Step 4: De-assert RST Low (if asserted High).
Step 5: Wait at least 160K (163,840) cycles.
During this time:
• Output driver and input termination impedances are calibrated (i.e. set to the programmed values).
Note: The DLL pin may be asserted High or de-asserted Low during this time. If asserted High, DLL synchronization begins
immediately after output driver and input termination impedance calibration has completed. If de-asserted Low, DLL
synchronization begins after the DLL pin is asserted High (see Step 6). In either case, Step 7 must follow thereafter.
Step 6: Assert DLL pin High (if de-asserted Low).
Step 7: Wait at least 64K (65,536) cycles.
During this time:
• The DLL is enabled and synchronized properly.
After DLL synchronization has completed:
• CQ, CQ begin toggling within specification.
Step 8: Begin initiating Read and Write operations.
Rev: 1.06 5/2012
6/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS8673EQ18/36BK-675/625/550/500
Reset (RST) Requirements
Although not generally recommended, RST may be asserted High at any time after completion of the initial power-up sequence
described previously, to reset the SRAM control logic to its initial power-on state. However, whenever RST is subsequently
de-asserted Low (as in Step 4 in the power up sequence), Steps 5~7 in the power-up sequence must be followed before Read and
Write operations are initiated.
Note: Memory array content may be perturbed/corrupted when RST is asserted High.
DLL Operation
An on-chip DLL is used to align output timing with input clocks. The DLL uses the CK input clock as a source, and is enabled
when all of the following conditions are met:
1. The DLL pin is asserted High, and
2. The RST pin is de-asserted Low, and
3. The input clock tKHKH ≤ 6.0ns.
Once enabled, the DLL requires 64K (65,536) stable clock cycles in order to synchronize properly.
The DLL can tolerate changes in input clock frequency due to clock jitter (i.e. such jitter will not cause the DLL to lose lock/
synchronization), provided the cycle-to-cycle jitter does not exceed 200ps (see the tKJITcc specification in the AC Electrical
Characteristics section for more information). However, the DLL must be resynchronized (i.e. disabled and then re-enabled)
whenever the nominal input clock frequency is changed.
When the DLL is enabled, read latency is determined by the RLM mode pins, as defined in the Read Latency section. Output
timing is aligned with the input clocks.
The DLL is disabled when any of the following conditions are met:
1. The DLL pin is de-asserted Low, or
2. The RST pin is asserted High, or
3. The input clock is stopped for at least 30ns, or tKHKH ≥ 30ns.
On-Chip Error Correction
SigmaQuad-IIIe ECCRAMs implement a single-bit error detection and correction algorithm (specifically, a Hamming Code) on
each DDR data word (comprising two 9-bit data bytes) transmitted on each 9-bit data bus (i.e., transmitted on D/Q[8:0], D/Q[17:9],
D/Q[26:18], or D/Q[35:27]). To accomplish this, 5 ECC parity bits (invisible to the user) are utilized per every 18 data bits (visible
to the user).
The ECC algorithm neither corrects nor detects multi-bit errors. However, GSI ECCRAMs are architected in such a way that a
single SER event very rarely causes a multi-bit error across any given “transmitted data unit”, where a “transmitted data unit”
represents the data transmitted as the result of a single read or write operation to a particular address. The extreme rarity of
multi-bit errors results in the SER mentioned previously (i.e., <0.002 FITs/Mb (measured at sea level)).
Not only does the on-chip ECC significantly improve SER performance, but it also frees up the entire memory array for data
storage. Very often SRAM applications allocate 1/9th of the memory array (i.e., one “error bit” per eight “data bits”, in any 9-bit
“data byte”) for error detection (either simple parity error detection, or system-level ECC error detection and correction). Such
error-bit allocation is unnecessary with ECCRAMs the entire memory array can be utilized for data storage, effectively providing
12.5% greater storage capacity compared to SRAMs of the same density not equipped with on-chip ECC.
Rev: 1.06 5/2012
7/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS8673EQ18/36BK-675/625/550/500
Read Latency (RL)
Read Latency is the Read pipeline length, and directly impacts the maximum operating frequency of the device. It is userprogrammable through mode pins RLM [1:0].
GS8673EQ18/36BK-675 Read Latency
Read Latency (RL)
RLM1
RLM0
Frequency
3.0 cycles
1
0
167 MHz–675 MHz
2.0 cycles
0
1
167 MHz–450 MHz
Read Latency (RL)
RLM1
RLM0
Frequency
3.0 cycles
1
0
167 MHz–625 MHz
2.0 cycles
0
1
167 MHz–400 MHz
Read Latency (RL)
RLM1
RLM0
Frequency
3.0 cycles
1
0
167 MHz–550 MHz
2.0 cycles
0
1
167 MHz–375 MHz
Read Latency (RL)
RLM1
RLM0
Frequency
3.0 cycles
1
0
167 MHz–500 MHz
2.0 cycles
0
1
167 MHz–333 MHz
GS8673EQ18/36BK-625 Read Latency
GS8673EQ18/36BK-550 Read Latency
GS8673EQ18/36BK-500 Read Latency
Rev: 1.06 5/2012
8/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS8673EQ18/36BK-675/625/550/500
Functional Description
Separate I/O ECCRAMs, from a system architecture point of view, are attractive in applications that execute continuous
back-to-back alternating Reads and Writes. Therefore, the SigmaQuad-IIIe ECCRAM interface and truth table are optimized for
continuously alternating Reads and Writes. Separate I/O ECCRAMs are unpopular in applications where block transfers of Reads
or Writes are needed because half of the data pins will go unused during the block transfer, potentially cutting Separate I/O
ECCRAM data bandwidth in half. Applications of this sort are better served by Common I/O ECCRAMs such as the
SigmaDDR-IIIe series.
Truth Table
SA
R
W
Current Operation
D
Q
↑CK
(tn)
↑CK
(tn+½)
↑CK
(tn)
↑CK
(tn)
(tn)
↑KD
(tn)
↑KD
(tn+½)
↑CK
(tm)
↑CK
(tm+½)
X
X
1
1
NOP
X
X
Hi-Z / 0
Hi-Z / 0
X
V
1
0
Write Only
D1
D2
Hi-Z / 0
Hi-Z / 0
V
X
0
1
Read Only
X
X
Q1
Q2
V
V
0
0
Read + Write
D1
D2
Q1
Q2
Notes:
1. 1 = input High; 0 = input Low; V equals input valid; X = input don’t care.
2. tm = tn + RL, where RL = Read Latency of the device.
3.
4.
5.
6.
D1 and D2 indicate the first and second pieces of Write Data transferred during Write operations.
Q1 and Q2 indicate the first and second pieces of Read Data transferred during Read operations.
When D input termination is disabled (MZT[1:0] = 00), Q drivers are disabled (i.e. Q pins are tri-stated) for one cycle in response to NOP and
Write commands, RL cycles after the command is sampled.
When D input termination is enabled (MZT[1:0] = 01 or 10), Q drivers are enabled Low (i.e. Q pins are driven Low) for one cycle in response
to NOP and Write Only commands, RL cycles after the command is sampled. This is done so the Memory Controller can enable On-Die
Termination on its data inputs without having to cope with the termination pulling tri-stated data inputs to VDDQ/2 (i.e. to the switch point of
the data input receivers).
Rev: 1.06 5/2012
9/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS8673EQ18/36BK-675/625/550/500
Low Power NOP Mode
When input termination is enabled on the Address (SA) and Write Data (D) inputs, those inputs can be placed in Low Power NOP
(LP NOP) mode via the synchronous ADZT1 input. When NOP operations are initiated with ADZT1 High, the termination
pull-ups on the SA and D inputs are disabled, thereby reducing the DC power associated with those inputs.
LP NOP Truth Table
R
W
ADZT1
Current Operation
SA, D Pull-Up
↑CK
(tn)
↑CK
(tn)
↑CK
(tn)
(tn)
↑CK
(tn+2)
X
X
0
Any
Enabled
X
X
1
Any
Disabled
Notes:
1. 1 = input High; 0 = input Low; X = input don’t care.
2. ADZT1 should only be driven High during NOP operations; SA, D input timing is not guaranteed in LP NOP Mode.
3. SA, D should be driven Low (or tri-stated) during LP NOP Mode, to take advantage of the power-saving feature.
LP NOP Timing Specifications
Parameter
Symbol
Min
Max
Units
CK Clock High to SA Pull-up Enable / Disable
tKHAZTV
0
2.0
ns
CK Clock High to D Pull-Up Enable / Disable
tKHDZTV
–0.4
0.4
ns
Rev: 1.06 5/2012
10/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS8673EQ18/36BK-675/625/550/500
LP NOP Timing Diagram
Write1
NOP1
(Notes 1)
(Notes 2)
NOP2
NOP3
NOP4
NOP5
NOP6
Write2
(Note 3)
(Note 4)
CK, KD
CK, KD
tKHAZTV(min)
tKHAZTV(max)
A
SA
B
R
W
ADZT1
tKHDZTV(min)
D
A0
tKHDZTV(max)
A1
B0
B1
Notes:
1. The Controller initiates Write1. The ECCRAM is enabling SA and D termination.
2. The Controller initiates two NOPs (NOP1 ~ NOP2) with ADZT1 High, to cause the ECCRAM to enter LP NOP Mode for two cycles.
The ECCRAM disables SA and D termination pull ups at ↑CK in NOP3, 2 cycles after sampling ADZT1 = 1 at ↑CK in NOP1.
The Controller drives SA, D Low during NOP1 ~ NOP6.
3. The Controller initiates four more NOPs (NOP3 ~ NOP6) with ADZT1 Low, to allow time for the ECCRAM to exit LP NOP Mode.
The ECCRAM enables SA and D termination pull ups at ↑CK in NOP5, 2 cycles after sampling ADZT1 = 0 at ↑CK in NOP3.
4. The Controller initiates Write2. The ECCRAM is enabling SA and D termination.
Rev: 1.06 5/2012
11/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS8673EQ18/36BK-675/625/550/500
Input Timing
Address (SA) inputs are latched with CK & CK.
Address input timing is clock-centered; that is, CK & CK edges must be driven such that adequate setup and hold time is provided
to the address input registers, as specified by the ECCRAM.
Control (R, W, ADZT1) inputs are latched with CK.
Control input timing is clock-centered; that is, CK edges must be driven such that adequate setup and hold time is provided to the
control input registers, as specified by the ECCRAM.
Write Data (D) inputs are latched with KD[1:0] and KD[1:0].
1. KD0 and KD0 are used to latch D[17:0] in x36, and D[8:0] in x18.
2. KD1 and KD1 are used to latch D[35:18] in x36, and D[17:9] in x18.
Write Data input timing is clock-centered; that is, KD and KD edges must be driven such that adequate setup and hold time is
provided to the data input registers, as specified by the ECCRAM.
Output Timing
The SigmaQuad-IIIe ECCRAMs feature source-synchronous output clocks, also known as echo clocks. These outputs, CQ0, CQ0,
CQ1, and CQ1 are designed to be electrically identical to data output pins. They are designed to behave just like data output pins.
They are designed to track variances demonstrated by the data outputs due to influences of temperature, voltage, process, or other
factors. As a result, the specifications that describe the relationship between the CQ clock edges and the data output edges are much
tighter than those that describe the relationship between the data outputs and the incoming CK clock.
Note that the CQ clock-to-data output specifications apply to specific combinations of clocks and data, as follows:
1. CQ0 and CQ0 are associated with Q[17:0] in x36, and with Q[8:0] in x18. They are also associated with QVLD0.
2. CQ1 and CQ1 are associated with Q[35:18] in x36, and with Q[17:9] in x18. They are also associated with QVLD1.
As can be seen, the echo clock pairs are, in each case, associated with data output pins on the nearest side of the chip. The left vs.
right side groupings prevent skew across the device and pinout from degrading the data output valid window.
Output Alignment
Q1
Active
Q2
Inactive
↑CQ
↓CQ
Q1
Inactive
Generated from ↑CK
Q2
Active
QVLD
Active/Inactive
↑CQ
↓CQ
Generated from ↑CK
Notes:
1. Q1 and Q2 indicate the first and second pieces of read data transferred in any given cycle.
2. Output timing is aligned with input clocks.
3. Output timing is clock-aligned. That is, CQ, CQ edges are aligned with Q edges.
Rev: 1.06 5/2012
12/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS8673EQ18/36BK-675/625/550/500
Output Driver Impedance Control
Programmable output drivers have been implemented on Read Data (Q), Read Data Valid (QVLD), and Echo Clocks (CQ, CQ).
The output driver impedance can be programmed via the ZQ pin. When an external impedance-matching resistor (RQ) is
connected between ZQ and VSS, output driver impedance is set to RQ/5 nominally.
Output driver impedance is set to the programmed value within 160K cycles after input clocks are operating within specification,
and RST is de-asserted Low. It is updated periodically thereafter, to compensate for temperature and voltage fluctuations in the
system.
Input Termination Impedance Control
On-die input termination can be enabled on Write Data (D), Address (SA), Control (R, W, ADZT1), and Input Clocks (CK, CK,
KD, KD) via the MZT[1:0] and PZT[1:0] pins. The termination impedance can be programmed via the ZT pin. When an external
impedance-matching resistor (RT) is connected between ZT and VSS, termination impedance is set according to the table below.
Termination impedance is set to the programmed value within 160K cycles after input clocks are operating within specification,
and RST is de-asserted Low. It is updated periodically thereafter, to compensate for temperature and voltage fluctuations in the
system.
Note: When termination impedance is enabled on a particular input, that input should always be driven High or Low; it should
never be tri-stated (i.e., in a High-Z state). If the input is tri-stated, the termination will pull the signal to VDDQ / 2 (i.e., to the
switch point of the diff-amp receiver), which could cause the receiver to enter a meta-stable state and consume more power than it
normally would. This could result in the device’s operating currents being higher.
The following table specifies the pull-up and pull-down termination impedances for each terminated input:
Pull-up and Pull-Down Termination Impedance
Terminated Inputs
CK, CK, KD, KD
PZT[1:0]
MZT[1:0]
Pull-Down
Impedance
Pull-Up
Impedance
X0
XX
disabled
disabled
01
RT
RT
10
2 * RT
2 * RT
XX
disabled
disabled
01
RT
RT
10
2 * RT
2 * RT
01
RT
RT
10
2 * RT
2 * RT
X1
0X
SA, R, W, ADZT1
1X
D
XX
Notes:
1. When MZT[1:0] = 00, input termination is disabled on all inputs.
2. When MZT[1:0] = 11, input termination state is not specified; it is reserved for future use.
3. During JTAG EXTEST and SAMPLE-Z instructions, input termination is disabled on all inputs.
Rev: 1.06 5/2012
13/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS8673EQ18/36BK-675/625/550/500
Electrical Specifications
Absolute Maximum Ratings
Parameter
Symbol
Rating
Units
Core Supply Voltage
VDD
-0.3 to +1.6
V
I/O Supply Voltage when MVQ = 0
VDDQ
-0.3 to VDD
V
I/O Supply Voltage when MVQ = 1
VDDQ
-0.3 to VDD + 0.3
V
Input Voltage when MVQ = 0
VIN
-0.3 to VDDQ + 0.3 (1.7 max)
V
Input Voltage when MVQ = 1
VIN
-0.3 to VDDQ + 0.3 (2.0 max)
V
Junction Temperature
TJ
0 to 125
°C
Storage Temperature
TSTG
-55 to 125
°C
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions for an extended period of time may affect
reliability of this component.
Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Units
Core Supply Voltage: -675 and -625 speed bins
VDD
1.3
1.35
1.4
V
Core Supply Voltage: -550 and -500 speed bins
VDD
1.25
1.3 ~ 1.35
1.4
V
I/O Supply Voltage when MVQ = 0
VDDQ
1.15
1.2 ~ 1.35
VDD
V
I/O Supply Voltage when MVQ = 1
VDDQ
1.4
1.5
1.6
V
Commercial Junction Temperature
TJC
0
—
85
°C
Industrial Junction Temperature
TJI
–40
—
100
°C
Note:
For reliability purposes, power supplies must power up simultaneously, or in the following sequence:
VSS, VDD, VDDQ, VREF, and Inputs.
Power supplies must power down simultaneously, or in the reverse sequence.
Thermal Impedance
Package
θ JA (C°/W)
Airflow = 0 m/s
θ JA (C°/W)
Airflow = 1 m/s
θ JA (C°/W)
Airflow = 2 m/s
θ JB (C°/W)
θ JC (C°/W)
FBGA
15.5
13.1
12.1
4.4
0.2
Rev: 1.06 5/2012
14/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS8673EQ18/36BK-675/625/550/500
I/O Capacitance
Parameter
Symbol
Min
Max
Units
Notes
Input Capacitance
CIN
—
5.0
pF
1, 3
Output Capacitance
COUT
—
5.5
pF
2, 3
Parameter
Symbol
Min
Max
Units
Notes
DC Input Reference Voltage
VREFdc
0.48 * VDDQ
0.52 * VDDQ
V
—
DC Input High Voltage
VIH1dc
VREF + 0.08
VDDQ + 0.15
V
4
DC Input Low Voltage
VIL1dc
–0.15
VREF – 0.08
V
4
DC Input High Voltage
VIH2dc
0.75 * VDDQ
VDDQ + 0.15
V
5
DC Input Low Voltage
VIL2dc
–0.15
0.25 * VDDQ
V
5
AC Input Reference Voltage
VREFac
0.47 * VDDQ
0.53 * VDDQ
V
1
AC Input High Voltage
VIH1ac
VREF + 0.15
VDDQ + 0.25
V
2, 3, 4
AC Input Low Voltage
VIL1ac
–0.25
VREF – 0.15
V
2, 3, 4
AC Input High Voltage
VIH2ac
VDDQ – 0.2
VDDQ + 0.25
V
2, 5
AC Input Low Voltage
VIL2ac
– 0.25
0.2
V
2, 5
Notes:
1. VIN = VDDQ/2.
2. VOUT = VDDQ/2.
3. TA = 25°C, f = 1 MHz.
Input Electrical Characteristics when MVQ = 0
Notes:
1. VREFac is equal to VREFdc plus noise.
2. VIH max and VIL min apply for pulse widths less than one-quarter of the cycle time.
3. Input rise and fall times must be a minimum of 1 V/ns, and within 10% of each other.
4. Applies to: CK, CK, KD[1.0], KD[1.0], SA, D[35:0], R, W, ADZT1.
5. Applies to: DLL, RST, RLM[1:0], MZT[1:0], PZT[1:0].
Rev: 1.06 5/2012
15/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS8673EQ18/36BK-675/625/550/500
Input Electrical Characteristics when MVQ = 1
Parameter
Symbol
Min
Max
Units
Notes
DC Input Reference Voltage
VREFdc
0.47 * VDDQ
0.53 * VDDQ
V
—
DC Input High Voltage
VIH1dc
VREF + 0.1
VDDQ + 0.15
V
4
DC Input Low Voltage
VIL1dc
–0.15
VREF – 0.1
V
4
DC Input High Voltage
VIH2dc
0.75 * VDDQ
VDDQ + 0.15
V
5
DC Input Low Voltage
VIL2dc
–0.15
0.25 * VDDQ
V
5
AC Input Reference Voltage
VREFac
0.46 * VDDQ
0.54 * VDDQ
V
1
AC Input High Voltage
VIH1ac
VREF + 0.2
VDDQ + 0.25
V
2, 3, 4
AC Input Low Voltage
VIL1ac
–0.25
VREF – 0.2
V
2, 3, 4
AC Input High Voltage
VIH2ac
VDDQ – 0.2
VDDQ + 0.25
V
2, 5
AC Input Low Voltage
VIL2ac
–0.25
0.2
V
2, 5
Notes:
1. VREFac is equal to VREFdc plus noise.
2. VIH max and VIL min apply for pulse widths less than one-quarter of the cycle time.
3. Input rise and fall times must be a minimum of 1V/ns, and within 10% of each other.
4. Applies to: CK, CK, KD[1.0], KD[1.0], SA, D[35:0], R, W, ADZT1.
5. Applies to: DLL, RST, RLM[1:0], MZT[1:0], PZT[1:0].
Rev: 1.06 5/2012
16/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS8673EQ18/36BK-675/625/550/500
Input Termination Impedance
Parameter
Symbol
MZT[1:0]
Min
Max
Units
Notes
Input Termination Impedance when MVQ = 0
RIN
01
RT * 0.85
RT * 1.15
10
(2*RT) * 0.8
(2*RT) * 1.2
Ω
1, 2, 3
Input Termination Impedance when MVQ = 1
RIN
01
RT * 0.8
RT * 1.2
10
(2*RT) * 0.75
(2*RT) * 1.25
Ω
1, 2, 3
Parameter
Symbol
Min
Max
Units
Notes
DC Output High Voltage
VOHdc
—
VDDQ + 0.15
V
1
DC Output Low Voltage
VOLdc
-0.15
—
V
1
AC Output High Voltage
VOHac
—
VDDQ + 0.25
V
1
AC Output Low Voltage
VOLac
-0.25
—
V
1
Parameter
Symbol
Min
Max
Units
Notes
Output Driver Impedance when MVQ = 0
ROUT
(RQ/5) * 0.9
(RQ/5) * 1.1
Ω
1, 2
Output Driver Impedance when MVQ = 1
ROUT
(RQ/5) * 0.85
(RQ/5) * 1.15
Ω
1, 2
Notes:
1. Applies to pull-up and pull-down individually.
2. Parameter applies when 105 < RT < 135.
3. Tested at VIN = VDDQ * 0.2 and VDDQ * 0.8.
Output Electrical Characteristics
Notes:
1. Parameters apply to: CQ, CQ, Q, QVLD.
Output Driver Impedance
Notes:
1. Parameter applies when 175Ω < RQ < 225Ω
2. Tested at VOUT = VDDQ * 0.2 and VDDQ * 0.8.
Rev: 1.06 5/2012
17/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS8673EQ18/36BK-675/625/550/500
Leakage Currents
Parameter
Symbol
Min
Max
Units
Notes
ILI1
–2
2
uA
1, 2
ILI2
–20
2
uA
1, 3
ILI3
–2
20
uA
1, 4
ILO
–2
2
uA
5, 6
Input Leakage Current
Output Leakage Current
Notes:
1. VIN = VSS to VDDQ.
2. Parameters apply to CK, CK, KD, KD, SA, D, R, W, ADZT1 when input termination is disabled.
Parameters apply to RLM, MZT, PZT, MVQ, TCK.
3. Parameters apply to DLL, TMS, TDI (weakly pulled up).
4. Parameters apply to RST (weakly pulled down).
5. VOUT = VSS to VDDQ.
6. Parameters apply to Q, CQ, CQ, QVLD, TDO.
Operating Currents
P/N
GS8673EQ18/36BK-675
GS8673EQ18/36BK-625
GS8673EQ18/36BK-550
GS8673EQ18/36BK-500
RL
Operating
Frequency
IDD
IDD
IDD
IDD
(VDD = 1.25 V)
(VDD = 1.3 V)
(VDD = 1.35 V)
(VDD = 1.4 V)
x18
x36
x18
x36
x18
x36
x18
x36
n/a
n/a
2030
2870
2140
3010
2260
3170
1460
2020
1540
2130
1630
2240
n/a
n/a
1900
2680
2000
2820
2110
2970
1330
1830
1410
1930
1490
2030
3
675 MHz
2
450 MHz
3
625 MHz
2
400 MHz
3
550 MHz
1630
2290
1720
2410
1820
2540
1930
2670
2
375 MHz
1190
1640
1270
1730
1340
1830
1420
1930
3
500 MHz
1490
2090
1580
2200
1670
2320
1770
2440
2
333 MHz
1090
1490
1160
1570
1230
1670
1300
1750
Units
mA
mA
mA
mA
Notes:
1. IOUT = 0 mA; VIN = VIH or VIL.
2. Applies at 100% Reads + Writes.
Rev: 1.06 5/2012
18/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS8673EQ18/36BK-675/625/550/500
AC Test Conditions for 1.2V nominal VDDQ (MVQ = 0)
Parameter
Symbol
Conditions
Units
Core Supply Voltage: -675 and -625 speed bins
VDD
1.3 to 1.4
V
Core Supply Voltage: -550 and -500 speed bins
VDD
1.25 to 1.4
V
I/O Supply Voltage
VDDQ
1.15 to 1.25
V
Input Reference Voltage
VREF
0.6
V
Input High Level
VIH
0.9
V
Input Low Level
VIL
0.3
V
Input Rise and Fall Time
—
2.0
V/ns
Input and Output Reference Level
—
0.6
V
Parameter
Symbol
Conditions
Units
Core Supply Voltage: -675 and -625 speed bins
VDD
1.3 to 1.4
V
Core Supply Voltage: -550 and -500 speed bins
VDD
1.25 to 1.4
V
I/O Supply Voltage
VDDQ
1.4 to 1.6
V
Input Reference Voltage
VREF
0.75
V
Input High Level
VIH
1.25
V
Input Low Level
VIL
0.25
V
Input Rise and Fall Time
—
2.0
V/ns
Input and Output Reference Level
—
0.75
V
Note:
Output Load Conditions RQ = 200Ω. Refer to figure below.
AC Test Conditions for 1.5V nominal VDDQ (MVQ = 1)
Note:
Output Load Conditions RQ = 200Ω. Refer to figure below.
AC Test Output Load
50Ω
Q, CQ
50Ω
VDDQ/2
5 pF
Rev: 1.06 5/2012
19/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS8673EQ18/36BK-675/625/550/500
AC Electrical Characteristics (independent of device speed grade)
Parameter
Symbol
Min
Max
Units Notes
Input Clock Timing
Clk High Pulse Width
tKHKL
0.45
—
cycles
1
Clk Low Pulse Width
tKLKH
0.45
—
cycles
1
Clk High to Clk High
tKHKH
0.45
0.55
cycles
2
Clk High to Write Data Clk High
tKHKDH
-200
200
ps
3
DLL Lock Time
tKlock
65,536
—
cycles
4
Clk Static to DLL Reset
tKreset
30
—
ns
5,11
Output Timing
Clk High to Data Output Valid
tKHQV
—
400
ps
6
Clk High to Data Output Hold
tKHQX
-400
—
ps
6
Clk High to Data Output High-Z
tKHQHZ
—
400
ps
7
Clk High to Data Output Low-Z
tKHQLZ
-400
—
ps
7
Clk High to Echo Clock High
tKHCQH
-400
400
ps
8
Echo Clk High to Echo Clock High
tCQHCQH
tKHKH (min) - 50
tKHKH (max) + 50
ps
9,11
Echo Clk High to Echo Clock High
tCQHCQH
tKHKH (min) - 50
tKHKH (max) + 50
ps
10,11
Notes:
All parameters are measured from the mid-point of the object signal to the mid-point of the reference signal unless otherwise noted.
1. Parameters apply to CK, CK, KD, KD.
2. Parameter specifies ↑CK → ↑CK and ↑KD → ↑KD requirements.
3. Parameter specifies ↑CK → ↑KD and ↑CK → ↑KD requirements.
4. VDD slew rate must be < 0.1V DC per 50ns for DLL lock retention. DLL lock time begins once VDD and input clock are stable.
5. Parameter applies to CK.
6. Parameters apply to Q, and are referenced to ↑CK.
7. Parameters apply to Q when MZT[1:0] = 00, and are referenced to ↑CK. They are measured at ± 50 mV from steady state voltage.
8. Parameter specifies ↑CK → ↑CQ timing.
9. Parameter specifies ↑CQ → ↑CQ timing. tKHKH (min) and tKHKH (max) are the minimum and maximum input delays from ↑CK to ↑CK
applied to the device, as determined by the Absolute Jitter associated with those clock edges.
10. Parameter specifies ↑CQ → ↑CQ timing. tKHKH (min) and tKHKH (max) are the minimum and maximum input delays from ↑CK to ↑CK
applied to the device, as determined by the Absolute Jitter associated with those clock edges.
11. Parameters are not tested. They are guaranteed by design, and verified through extensive corner-lot characterization.
Rev: 1.06 5/2012
20/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS8673EQ18/36BK-675/625/550/500
AC Electrical Characteristics (variable with device speed grade)
–675
–625
–550
–500
Notes
Symbol
Units
Parameter
1.48
6.0
1.6
6.0
1.8
6.0
2.0
6.0
ns
1,2
2.2
6.0
2.5
6.0
2.66
6.0
3.0
6.0
ns
1,3
—
60
—
60
—
60
—
60
ps 1,4,5
Min
Max
Min
Max
Min
Max
Min
Max
Input Clock Timing
Clk Cycle Time
tKHKH
Clk Cycle-to-Cycle Jitter
tKJITcc
Input Setup & Hold Timing
Address Input Valid to Clk High
tAVKH
150
—
160
—
180
—
200
—
ps
6
Control Input Valid to Clk High
tIVKH
150
—
160
—
180
—
200
—
ps
7
Data Input Valid to Clk High
tDVKH
150
—
160
—
180
—
200
—
ps
8
Clk High to Address Input Hold
tKHAX
150
—
160
—
180
—
200
—
ps
6
Clk High to Control Input Hold
tKHIX
150
—
160
—
180
—
200
—
ps
7
Clk High to Data Input Hold
tKHDX
150
—
160
—
180
—
200
—
ps
8
Output Timing
Echo Clk High to Data Output Valid
tCQHQV
—
150
—
150
—
150
—
150
ps 9,10
Echo Clk High to Data Output Hold
tCQHQX
-150
—
-150
—
-150
—
-150
—
ps 9,10
Notes:
All parameters are measured from the mid-point of the object signal to the mid-point of the reference signal.
1. Parameters apply to CK, CK, KD, KD.
2. Parameter applies when RL=3.
3. Parameter applies when RL=2.
4. Parameter specifies Cycle-to-Cycle (C2C) Jitter (i.e. the maximum variation from clock rising edge to the next clock rising edge).
As such, it limits Period Jitter (i.e. the maximum variation in clock cycle time from nominal) to ± 30ps.
And as such, it limits Absolute Jitter (i.e. the maximum variation in clock rising edge from its nominal position) to ± 15ps.
5. The device can tolerated C2C Jitter greater than 60ps, up to a maximum of 200ps. However, when using a device from a particular speed
bin, tKHKH (min) of that speed bin must be derated (increased) by half the difference between the actual C2C Jitter and 60ps. For example,
if the actual C2C Jitter is 100ps, then tKHKH (min) for the -675 speed bin (RL=3) is derated to 1.5ns (1.48ns + 0.5*(100ps - 60ps)).
6.
7.
8.
9.
10.
Parameters apply to SA, and are referenced to ↑CK & ↑CK.
Parameters apply to R, W, ADZT1, and are referenced to ↑CK.
Parameters apply to D, and are referenced to ↑KD & ↑KD.
Parameters apply to Q, QVLD and are referenced to ↑CQ & ↑CQ.
Parameters are not tested. They are guaranteed by design, and verified through extensive corner-lot characterization.
Rev: 1.06 5/2012
21/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS8673EQ18/36BK-675/625/550/500
SigmaQuad-IIIe Burst of 2, RL = 3
Rd + Wr
Rd Only
Wr Only
Rd + Wr
Wr Only
Rd Only
NOP
Rd + Wr
Rd + Wr
NOP
Rd Only
KD
tKHKH
tKHKL tKLKH tKHKH
KD
tDVKH
D
D21
D22
tKHKDH
D41
D42
tDVKH
tKHDX
D61
D62
D71
D72
DA1
DA2
tKHDX
DC1
DC2
tKHKDH
CK
tKHKH
tKHKL tKLKH tKHKH
CK
tAVKH
SA
A1
A2
A3
A4
tAVKH
tKHAX
A5
A7
A6
A8
A9
AA
tKHAX
AB
AD
AC
tIVKH tKHIX
R
W
tKHQX
tKHQV
Q
Q11
Q12
Q31
Q32
Q51
Q52
Q81
Q82
QVLD
tCQHQX
tKHCQH
tCQHQV
tCQHQX
tCQHQX
tCQHQV
tCQHQV
CQ
tCQHCQH
CQ
Note: The Q state during non-Reads depicted in this diagram (Q=Low) applies when D input termination is enabled (MZT=01 or 10).
When D input termination is disabled (MZT=00), the Q state during non-Reads is High-Z.
Rev: 1.06 5/2012
22/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS8673EQ18/36BK-675/625/550/500
JTAG Test Mode Description
These devices provide a JTAG Test Access Port (TAP) and Boundary Scan interface using a limited set of IEEE std. 1149.1
functions. This test mode is intended to provide a mechanism for testing the interconnect between master (processor, controller,
etc.), ECCRAM, other components, and the printed circuit board. In conformance with a subset of IEEE std. 1149.1, these devices
contain a TAP Controller and multiple TAP Registers. The TAP Registers consist of one Instruction Register and multiple Data
Registers.
The TAP consists of the following four signals:
Pin
Pin Name
I/O
Description
TCK
Test Clock
I
Induces (clocks) TAP Controller state transitions.
TMS
Test Mode Select
I
Inputs commands to the TAP Controller.
Sampled on the rising edge of TCK.
TDI
Test Data In
I
Inputs data serially to the TAP Registers.
Sampled on the rising edge of TCK.
TDO
Test Data Out
O
Outputs data serially from the TAP Registers.
Driven from the falling edge of TCK.
Concurrent TAP and Normal ECCRAM Operation
According to IEEE std. 1149.1, most public TAP Instructions do not disrupt normal device operation. In these devices, the only
exceptions are EXTEST and SAMPLE-Z. See the Tap Registers section for more information.
Disabling the TAP
When JTAG is not used, TCK should be tied Low to prevent clocking the ECCRAM. TMS and TDI should either be tied High
through a pull-up resistor or left unconnected. TDO should be left unconnected.
JTAG DC Operating Conditions
Parameter
Symbol
Min
Max
Units
Notes
JTAG Input High Voltage
VTIH
0.75 * VDDQ
VDDQ + 0.15
V
1
JTAG Input Low Voltage
VTIL
–0.15
0.25 * VDDQ
V
1
JTAG Output High Voltage
VTOH
VDDQ – 0.2
—
V
2, 3
JTAG Output Low Voltage
VTOL
—
0.2
V
2, 4
Notes:
1. Parameters apply to TCK, TMS, and TDI during JTAG Testing.
2. Parameters apply to TDO during JTAG testing.
3. ITOH = –2.0 mA.
4.
ITOL = 2.0 mA.
Rev: 1.06 5/2012
23/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS8673EQ18/36BK-675/625/550/500
JTAG AC Timing Specifications
Parameter
Symbol
Min
Max
Unit
TCK Cycle Time
tTHTH
50
—
ns
TCK High Pulse Width
tTHTL
20
—
ns
TCK Low Pulse Width
tTLTH
20
—
ns
TMS Setup Time
tMVTH
10
—
ns
TMS Hold Time
tTHMX
10
—
ns
TDI Setup Time
tDVTH
10
—
ns
TDI Hold Time
tTHDX
10
—
ns
Capture Setup Time (Address, Control, Data, Clock)
tCS
10
—
ns
Capture Hold Time (Address, Control, Data, Clock)
tCH
10
—
ns
TCK Low to TDO Valid
tTLQV
—
10
ns
TCK Low to TDO Hold
tTLQX
0
—
ns
JTAG Timing Diagram
tTHTL
tTLTH
tTHTH
TCK
tMVTH
tTHMX
tDVTH
tTHDX
TMS
TDI
tTLQV
tTLQX
TDO
Rev: 1.06 5/2012
24/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS8673EQ18/36BK-675/625/550/500
TAP Controller
The TAP Controller is a 16-state state machine that controls access to the various TAP Registers and executes the operations
associated with each TAP Instruction. State transitions are controlled by TMS and occur on the rising edge of TCK.
The TAP Controller enters the Test-Logic Reset state in one of two ways:
1. At power up.
2. When a logic 1 is applied to TMS for at least 5 consecutive rising edges of TCK.
The TDI input receiver is sampled only when the TAP Controller is in either the Shift-IR state or the Shift-DR state.
The TDO output driver is enabled only when the TAP Controller is in either the Shift-IR state or the Shift-DR state.
TAP Controller State Diagram
1
Test-Logic Reset
0
0
Run-Test / Idle
1
Select DR-Scan
1
Select IR-Scan
0
1
0
1
Capture-DR
Capture-IR
0
0
0
Shift-DR
1
1
Exit1-DR
Exit1-IR
0
0
0
Pause-DR
1
0
Exit2-IR
1
Rev: 1.06 5/2012
0
25/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
0
1
Update-DR
1
0
Pause-IR
1
Exit2-DR
0
Shift-IR
1
1
1
Update-IR
1
0
© 2011, GSI Technology
GS8673EQ18/36BK-675/625/550/500
TAP Registers
TAP Registers are serial shift registers that capture serial input data (from TDI) on the rising edge of TCK, and drive serial output
data (to TDO) on the subsequent falling edge of TCK. They are divided into two groups: Instruction Registers (IR), which are
manipulated via the IR states in the TAP Controller, and Data Registers (DR), which are manipulated via the DR states in the TAP
Controller.
Instruction Register (IR—3 bits)
The Instruction Register stores the various TAP Instructions supported by ECCRAM. It is loaded with the IDCODE instruction
(logic 001) at power-up, and when the TAP Controller is in the Test-Logic Reset and Capture-IR states. It is inserted between TDI
and TDO when the TAP Controller is in the Shift-IR state, at which time it can be loaded with a new instruction. However, newly
loaded instructions are not executed until the TAP Controller has reached the Update-IR state.
The Instruction Register is 3 bits wide, and is encoded as follows:
Code
(2:0)
Instruction
Description
EXTEST
Loads the logic states of all signals composing the ECCRAM I/O ring into the Boundary Scan Register when the TAP Controller is in the Capture-DR state, and inserts the Boundary Scan Register
between TDI and TDO when the TAP Controller is in the Shift-DR state.
Also transfers the contents of the Boundary Scan Register associated with all output signals (Q,
QVLD, CQ, CQ) directly to their corresponding output pins. However, newly loaded Boundary Scan
Register contents do not appear at the output pins until the TAP Controller has reached the
Update-DR state.
Also disables all input termination.
See the Boundary Scan Register description for more information.
IDCODE
Loads a predefined device- and manufacturer-specific identification code into the ID Register when
the TAP Controller is in the Capture-DR state, and inserts the ID Register between TDI and TDO
when the TAP Controller is in the Shift-DR state.
See the ID Register description for more information.
010
SAMPLE-Z
Loads the logic states of all signals composing the ECCRAM I/O ring into the Boundary Scan Register when the TAP Controller is in the Capture-DR state, and inserts the Boundary Scan Register
between TDI and TDO when the TAP Controller is in the Shift-DR state.
Also disables all input termination.
See the Boundary Scan Register description for more information.
011
PRIVATE
Reserved for manufacturer use only.
100
SAMPLE
Loads the logic states of all signals composing the ECCRAM I/O ring into the Boundary Scan Register when the TAP Controller is in the Capture-DR state, and inserts the Boundary Scan Register
between TDI and TDO when the TAP Controller is in the Shift-DR state.
See the Boundary Scan Register description for more information.
101
PRIVATE
Reserved for manufacturer use only.
110
PRIVATE
Reserved for manufacturer use only.
BYPASS
Loads a logic 0 into the Bypass Register when the TAP Controller is in the Capture-DR state, and
inserts the Bypass Register between TDI and TDO when the TAP Controller is in the Shift-DR
state.
See the Bypass Register description for more information.
000
001
111
Rev: 1.06 5/2012
26/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS8673EQ18/36BK-675/625/550/500
Bypass Register (DR—1 bit)
The Bypass Register is one bit wide, and provides the minimum length serial path between TDI and TDO. It is loaded with a logic
0 when the BYPASS instruction has been loaded in the Instruction Register and the TAP Controller is in the Capture-DR state. It is
inserted between TDI and TDO when the BYPASS instruction has been loaded into the Instruction Register and the TAP
Controller is in the Shift-DR state.
ID Register (DR—32 bits)
The ID Register is loaded with a predetermined device- and manufacturer-specific identification code when the IDCODE
instruction has been loaded into the Instruction Register and the TAP Controller is in the Capture-DR state. It is inserted between
TDI and TDO when the IDCODE instruction has been loaded into the Instruction Register and the TAP Controller is in the
Shift-DR state.
The ID Register is 32 bits wide, and is encoded as follows:
See BSDL Model
(31:12)
GSI ID
(11:1)
Start Bit
(0)
XXXX XXXX XXXX XXXX XXXX
0001 1011 001
1
Bit 0 is the LSB of the ID Register, and Bit 31 is the MSB. When the ID Register is selected, TDI serially shifts data into the MSB,
and the LSB serially shifts data out through TDO.
Boundary Scan Register (DR—127 bits)
The Boundary Scan Register is equal in length to the number of active signal connections to the ECCRAM (excluding the TAP
pins) plus a number of place holder locations reserved for functional and/or density upgrades. It is loaded with the logic states of all
signals composing the ECCRAM’s I/O ring when the EXTEST, SAMPLE, or SAMPLE-Z instruction has been loaded into the
Instruction Register and the TAP Controller is in the Capture-DR state. It is inserted between TDI and TDO when the EXTEST,
SAMPLE, or SAMPLE-Z instruction has been loaded into the Instruction Register and the TAP Controller is in the Shift-DR state.
Additionally, the contents of the Boundary Scan Register associated with the ECCRAM outputs (Q, QVLD, CQ, CQ) are driven
directly to the corresponding ECCRAM output pins when the EXTEST instruction is selected. However, after the EXTEST
instruction has been selected, any new data loaded into Boundary Scan Register when the TAP Controller is in the Shift-DR state
does not appear at the output pins until the TAP Controller has reached the Update-DR state.
The value captured in the boundary scan register for NU pins is determined by the external pin state while the NC pins are 0
regardless of the external pin state. The value captured in the internal cells is 1.
Output Driver State During EXTEST
EXTEST allows the Internal Cell (Bit 127) in the Boundary Scan Register to control the state of Q drivers. That is, when Bit 127 =
1, Q drivers are enabled (i.e., driving High or Low), and when Bit 127 = 0, Q drivers are disabled (i.e., forced to High-Z state). See
the Boundary Scan Register section for more information.
Input Termination State During EXTEST and SAMPLE-Z
Input termination on all inputs is disabled during EXTEST and SAMPLE-Z.
Rev: 1.06 5/2012
27/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS8673EQ18/36BK-675/625/550/500
Boundary Scan Register Bit Order Assignment
The table below depicts the order in which the bits are arranged in the Boundary Scan Register. Bit 1 is the LSB and Bit 127 is the
MSB. When the Boundary Scan Register is selected, TDI serially shifts data into the MSB, and the LSB serially shifts data out
through TDO.
Bit
Pad
Bit
Pad
Bit
Pad
Bit
Pad
Bit
Pad
1
7L
29
11G
57
10W
85
4R
113
3C
2
7K
30
13G
58
8V
86
2R
114
2B
3
9L
31
10G
59
9U
87
3P
115
4B
4
9K
32
12G
60
8T
88
1P
116
6A
5
8J
33
11H
61
9R
89
4P
117
6B
6
7H
34
13H
62
8P
90
2P
118
6C
7
9H
35
10J
63
9N
91
3N
119
5D
8
7G
36
12J
64
8M
92
1N
120
6E
9
8G
37
13K
65
6M
93
4M
121
5F
10
9F
38
13L
66
7N
94
2M
122
6G
11
8E
39
11L
67
5N
95
3L
123
5H
12
7D
40
12M
68
7P
96
1L
124
6J
13
9D
41
10M
69
6P
97
1K
125
5K
14
8C
42
13N
70
5R
98
2J
126
5L
15
8B
43
11N
71
6T
99
4J
127
Internal
16
9B
44
12P
72
7U
100
1H
17
7A
45
10P
73
5U
101
3H
18
9A
46
13P
74
6V
102
2G
19
10B
47
11P
75
6W
103
4G
20
12B
48
12R
76
7Y
104
1G
21
11C
49
10R
77
4W
105
3G
22
13C
50
13T
78
2W
106
2F
23
10D
51
11T
79
3V
107
4F
24
12D
52
12U
80
1V
108
1E
25
11E
53
10U
81
4U
109
3E
26
13E
54
13V
82
2U
110
2D
27
10F
55
11V
83
3T
111
4D
28
12F
56
12W
84
1T
112
1C
Rev: 1.06 5/2012
28/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS8673EQ18/36BK-675/625/550/500
260-Pin BGA Package Drawing (Package K)
0.08 S C
0.08 S C A S B S
Ø
Ø
Ø
0.50~Ø0.70(260x)
13 12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
19.00
17.40 ± 0.05
22.00 ± 0.05
1.00
PIN #1 CORNER
12.60 ± 0.05
B
A
1.00
14.00 ± 0.05
12.00
Rev: 1.06 5/2012
C
0.15
0.05
SEATING PLANE
0.40~0.60
0.51 REF
C
4–R0.5 (MAX)
0.50 + 0.03
0.10
HEAT SPREADER
//
1.09 REF
C
2.10 + 0.2/–0.3
0.05(4X)
Ball Pitch:
1.00 Substrate Thickness:
Ball Diameter:
0.60 Mold Thickness:
0.51
—
29/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS8673EQ18/36BK-675/625/550/500
Ordering Information—GSI SigmaQuad-IIIe ECCRAM
Org
Part Number
Type
Package
Status
Speed
(MHz)
TA
4M x 18
GS8673EQ18BK-675
SigmaQuad-IIIe B2 ECCRAM
260-ball BGA
Qual
675
C
4M x 18
GS8673EQ18BK-625
SigmaQuad-IIIe B2 ECCRAM
260-ball BGA
Qual
625
C
4M x 18
GS8673EQ18BK-550
SigmaQuad-IIIe B2 ECCRAM
260-ball BGA
Qual
550
C
4M x 18
GS8673EQ18BK-500
SigmaQuad-IIIe B2 ECCRAM
260-ball BGA
Qual
500
C
4M x 18
GS8673EQ18BK-675I
SigmaQuad-IIIe B2 ECCRAM
260-ball BGA
Qual
675
I
4M x 18
GS8673EQ18BK-625I
SigmaQuad-IIIe B2 ECCRAM
260-ball BGA
Qual
625
I
4M x 18
GS8673EQ18BK-550I
SigmaQuad-IIIe B2 ECCRAM
260-ball BGA
Qual
550
I
4M x 18
GS8673EQ18BK-500I
SigmaQuad-IIIe B2 ECCRAM
260-ball BGA
Qual
500
I
2M x 36
GS8673EQ36BK-675
SigmaQuad-IIIe B2 ECCRAM
260-ball BGA
Qual
675
C
2M x 36
GS8673EQ36BK-625
SigmaQuad-IIIe B2 ECCRAM
260-ball BGA
Qual
625
C
2M x 36
GS8673EQ36BK-550
SigmaQuad-IIIe B2 ECCRAM
260-ball BGA
Qual
550
C
2M x 36
GS8673EQ36BK-500
SigmaQuad-IIIe B2 ECCRAM
260-ball BGA
Qual
500
C
2M x 36
GS8673EQ36BK-675I
SigmaQuad-IIIe B2 ECCRAM
260-ball BGA
Qual
675
I
2M x 36
GS8673EQ36BK-625I
SigmaQuad-IIIe B2 ECCRAM
260-ball BGA
Qual
625
I
2M x 36
GS8673EQ36BK-550I
SigmaQuad-IIIe B2 ECCRAM
260-ball BGA
Qual
550
I
2M x 36
GS8673EQ36BK-500I
SigmaQuad-IIIe B2 ECCRAM
260-ball BGA
Qual
500
I
4M x 18
GS8673EQ18BGK-675
SigmaQuad-IIIe B2 ECCRAM
RoHS-compliant 260-ball BGA
Qual
675
C
4M x 18
GS8673EQ18BGK-625
SigmaQuad-IIIe B2 ECCRAM
RoHS-compliant 260-ball BGA
Qual
625
C
4M x 18
GS8673EQ18BGK-550
SigmaQuad-IIIe B2 ECCRAM
RoHS-compliant 260-ball BGA
Qual
550
C
4M x 18
GS8673EQ18BGK-500
SigmaQuad-IIIe B2 ECCRAM
RoHS-compliant 260-ball BGA
Qual
500
C
4M x 18
GS8673EQ18BGK-675I
SigmaQuad-IIIe B2 ECCRAM
RoHS-compliant 260-ball BGA
Qual
675
I
4M x 18
GS8673EQ18BGK-625I
SigmaQuad-IIIe B2 ECCRAM
RoHS-compliant 260-ball BGA
Qual
625
I
4M x 18
GS8673EQ18BGK-550I
SigmaQuad-IIIe B2 ECCRAM
RoHS-compliant 260-ball BGA
Qual
550
I
4M x 18
GS8673EQ18BGK-500I
SigmaQuad-IIIe B2 ECCRAM
RoHS-compliant 260-ball BGA
Qual
500
I
2M x 36
GS8673EQ36BGK-675
SigmaQuad-IIIe B2 ECCRAM
RoHS-compliant 260-ball BGA
Qual
675
C
2M x 36
GS8673EQ36BGK-625
SigmaQuad-IIIe B2 ECCRAM
RoHS-compliant 260-ball BGA
Qual
625
C
2M x 36
GS8673EQ36BGK-550
SigmaQuad-IIIe B2 ECCRAM
RoHS-compliant 260-ball BGA
Qual
550
C
2M x 36
GS8673EQ36BGK-500
SigmaQuad-IIIe B2 ECCRAM
RoHS-compliant 260-ball BGA
Qual
500
C
Notes: C = Commercial Temperature Range. I = Industrial Temperature Range.
Rev: 1.06 5/2012
30/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS8673EQ18/36BK-675/625/550/500
Ordering Information—GSI SigmaQuad-IIIe ECCRAM
Org
Part Number
Type
Package
Status
Speed
(MHz)
TA
2M x 36
GS8673EQ36BGK-675I
SigmaQuad-IIIe B2 ECCRAM
RoHS-compliant 260-ball BGA
Qual
675
I
2M x 36
GS8673EQ36BGK-625I
SigmaQuad-IIIe B2 ECCRAM
RoHS-compliant 260-ball BGA
Qual
625
I
2M x 36
GS8673EQ36BGK-550I
SigmaQuad-IIIe B2 ECCRAM
RoHS-compliant 260-ball BGA
Qual
550
I
2M x 36
GS8673EQ36BGK-500I
SigmaQuad-IIIe B2 ECCRAM
RoHS-compliant 260-ball BGA
Qual
500
I
Notes: C = Commercial Temperature Range. I = Industrial Temperature Range.
Revision History
Rev. Code
Types of Changes
Format or Content
Revisions
• Creation of new datasheet
GS8673EQ1836BK_r1
GS8673EQ1836BK_r1_01
Content
• Changed speed bins to 625, 550, & 500 MHz.
• Increased VDD (min) spec from 1.25V to 1.3V for 625 MHz speed
bin.
• Improved tKHQV / tKHQX specs from +/-500ps to +/-400ps.
• Updated the Low Power NOP Mode section.
GS8673EQ1836BK_r1_02
Content
• Added 675 MHz speed bin.
• Updated to MP status.
GS8673EQ1836BK_r1_02a
Content
• Re-added tKHKH (max) specs (previously inadvertently deleted).
• Updated IDD specs.
GS8673EQ1836BK_r1_03
Content
• Added part numbers for lead-free RoHS-compliant BGA package.
GS8673EQ1836BK_r1_04
Content
• Updated Addressing Schemes section, and moved to p.1.
• Updated Absolute Maximum Ratings.
• Updated Input Electrical Characteristics.
• Corrected JTAG BScan Register bit order.
GS8673EQ1836BK_r1_05
Content
• Updated status of lead-free RoHS-compliant BGA pkg to “Qual”.
Content
• Updated Absolute Maximum Ratings.
• Updated Recommended Operating Conditions.
• Updated AC Electrical Specifications:
Updated tCQHCQH spec, and associated note.
Added tCQHCQH and tKJITcc specs, and associated notes.
Removed tKvar and tCQvar specs.
GS8673EQ1836BK_r1_06
Rev: 1.06 5/2012
31/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
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