EiceDRIVER™ 2EDL family: Technical description

Eice DR IV ER ™ Co m pac t
High voltage gate drive IC
2E DL fa mi ly
Technical description
Applic atio n N ote
AN2013-11
Rev. 2.0, 2015-04-16
EiceDRIVER(TM) Compact 2EDL family
Technical Description
Edition 2015-04-20
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2015 Infineon Technologies AG
All Rights Reserved.
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EiceDRIVER(TM) Compact 2EDL family
Technical Description
Revision History
Rev. 1, 2013-01-08
Page or Item
Subjects (major changes since previous revision)
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corrected orthography
Trademarks of Infineon Technologies AG
AURIX™, BlueMoon™, C166™, CanPAK™, CIPOS™, CIPURSE™, COMNEON™, EconoPACK™,
CoolMOS™, CoolSET™, CORECONTROL™, CROSSAVE™, DAVE™, EasyPIM™, EconoBRIDGE™,
EconoDUAL™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™,
ISOFACE™, IsoPACK™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OmniTune™, OptiMOS™, ORIGA™,
PRIMARION™, PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™, ReverSave™, SatRIC™,
SIEGET™, SINDRION™, SIPMOS™, SMARTi™, SmartLEWIS™, SOLID FLASH™, TEMPFET™, thinQ!™,
TRENCHSTOP™, TriCore™, X-GOLD™, X-PMU™, XMM™, XPOSYS™.
Other Trademarks
Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™,
PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by
AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum.
COLOSSUS™, FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™
of Epcos AG. FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium.
HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™
of Infrared Data Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR
STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc.
MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. Mifare™ of NXP. MIPI™ of MIPI Alliance, Inc.
MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA MANUFACTURING CO., MICROWAVE
OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of OmniVision Technologies, Inc.
Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of
Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™ of Spansion LLC Ltd.
Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc.
TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company
Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas Instruments
Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex
Limited.
Last Trademarks Update 2010-10-26
Final Application Note
AN2013-11
3
Rev. 2.0, 2015-04-16
EiceDRIVER(TM) Compact 2EDL family
Technical Description
Table of Contents
1
Scope and product family ................................................................................................................. 6
2
Technology Characteristics .............................................................................................................. 7
3
3.1
3.1.1
3.1.2
3.2
3.2.1
3.2.2
3.3
3.3.1
3.3.2
3.3.3
3.4
3.4.1
3.4.2
3.4.3
3.5
3.5.1
3.5.2
3.5.3
3.6
3.7
3.8
3.9
Technical description of the 2EDL family ........................................................................................ 8
Control input section ............................................................................................................................ 8
High side input pins (HIN), Low side input pins (LIN) .......................................................................... 8
Enable and fault pin (EN-/FLT, 2EDL23x06PJ only) ............................................................................ 9
IC supply section ................................................................................................................................ 10
IGBT types ......................................................................................................................................... 10
MOSFET types ................................................................................................................................... 10
Output sections .................................................................................................................................. 11
Low side gate drive ............................................................................................................................ 11
High side section ................................................................................................................................ 11
Negative transients at high side reference (pin VS) ........................................................................... 12
Bootstrapping ..................................................................................................................................... 12
Temperature stability of bootstrap diode and application range ........................................................ 12
Supply voltage range calculation ....................................................................................................... 13
Calculating the bootstrap capacitance CBS ........................................................................................ 14
Protection ........................................................................................................................................... 15
Overcurrent protection (OCP, 2EDL23x06PJ only) ........................................................................... 15
Deadtime & Shoot Through Prevention ............................................................................................. 17
Undervoltage Lockout (UVLO) ........................................................................................................... 17
Calculation of power dissipation and thermal aspects ....................................................................... 17
Creepage ............................................................................................................................................ 19
Design considerations ........................................................................................................................ 19
Layout considerations ........................................................................................................................ 19
4
4.1
List of used parameters ................................................................................................................... 21
General ............................................................................................................................................... 21
References............................................................................................................................................................ 22
Final Application Note
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Rev. 2.0, 2015-04-16
EiceDRIVER(TM) Compact 2EDL family
Technical Description
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Cross section of a FET in SOI-technology ........................................................................................... 7
Control input pin structure .................................................................................................................... 8
Short pulse suppression (left: short ON pulse; right: short OFF pulse) ............................................... 8
Schematic of the structure of the EN-/FLT pin ..................................................................................... 9
Timing diagram for ITRIP to FAULT propagation delay ....................................................................... 9
Typical areas of operation for IGBT types ......................................................................................... 10
Typical areas of operation for MOSFET types ................................................................................... 11
Structure of the low side gate drive section ....................................................................................... 11
Structure of the low side gate drive section ....................................................................................... 12
Voltage drop of bootstrap voltage in steady state vs. duty cycle of LS transistor .............................. 13
Bootstrap circuit for one half bridge ................................................................................................... 14
Size of the bootstrap capacitor as a function of the switching frequency fP for driving IKD10N60R
according to equ. (5) with a voltage ripple of 0.1 V ............................................................................ 15
Internal structure of the ITRIP and EN-/FLT sections ........................................................................ 16
Short circuit clamping ......................................................................................................................... 16
UVLO filter time .................................................................................................................................. 17
Parasitic inductances in the layout ..................................................................................................... 20
List of Tables
Table 1
Table 2
Members of 2EDL family ...................................................................................................................... 6
Used parameters ................................................................................................................................ 21
Final Application Note
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Rev. 2.0, 2015-04-16
EiceDRIVER(TM) Compact 2EDL family
Technical Description
1
Scope and product family
The 2EDL family is a high voltage half bridge gate drive IC up to a maximum blocking voltage of 600V. Typical
applications are consumer and industrial drives, fans, pumps, induction cooking equipment or switch mode
power supplies. The converters can be used for example in drives applications which are basing on induction
machines (IM) or brushless DC motors. The 2EDL family is designed in silicon-on-insulator-technology (SOI).
This technology provides an excellent ruggedness against negative voltage spikes and noise.
This application note gives an overview of the technological characteristics. It also describes the most important
sections in terms of the application and gives design recommendations for a proper operation of the device in
the application. This document covers the following products:
Table 1
Members of 2EDL family
Sales Name
EN-/FLT
deadtime & interlock
typ. UVLO-Thresholds Bootstrap diode Package
No
Yes
12.5 V / 11.6 V
Yes
No
No
12.5 V / 11.6 V
Yes
No
Yes
9.1 V / 8.3 V
Yes
2EDL23I06PJ
Yes
Yes
12.5 V / 11.6 V
Yes
DSO-14
2EDL23N06PJ
Yes
Yes
9.1 V / 8.3 V
Yes
DSO-14
2EDL05I06PF,
2EDL05I06PJ
2EDL05I06BF
2EDL05N06PF
2EDL05N06PJ
DSO-8
DSO-14
DSO-8
DSO-8
DSO-14
The 2EDL family provides positive control logic as well as different under voltage lockout levels for MOSFET
and IGBT. The pin designations, control signals, thresholds and parameters described in this application note
must be understood according to the individual part.
In this application note, the parameter values for 2EDL 0.5A version (2EDL05I06PF, 2EDL05I06PJ,
2EDL05I06BF, 2EDL05N06PF and 2EDL05N06PJ) are referred to 2EDL 0.5A datasheet, and the parameter
values for 2EDL 2.3A version (2EDL23I06PJ and 2EDL23N06PJ) are referred to 2EDL 2.3A datasheet.
Target applications are all cost sensitive applications in the consumer and low end industrial area. All devices
are therefore compatible even to microcontrollers with a supply voltage of 3.3 V. The 2EDL is compatible to the
same footprint as a number of other gate drive IC in the market. Nevertheless, many features are built in, which
provide an add-on value to the application. Please refer here also to the product specifications of 2EDL family.
Final Application Note
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Rev. 2.0, 2015-04-16
EiceDRIVER(TM) Compact 2EDL family
Technical Description
2
Technology Characteristics
SOI is the abbreviation of Silicon-On-Insulator and is an advanced technique for MOS/CMOS fabrications. It
differs from the conventional bulk process by placing the active transistor layer on the top of an insulator, as
shown in Figure 1.
Figure 1
Cross section of a FET in SOI-technology
The silicon is separated by a buried silicon oxide layer to one layer on the top and the other on the bottom. The
one on the top, which is the silicon film, is used to produce the transistor and the one on the bottom is used as
the silicon substrate. The buried silicon oxide provides an insulation barrier between the active layer and silicon
substrate and hence reduces the parasitic capacitance tremendously. Moreover, this insulation barrier disables
leakage or latch-up currents between adjacent devices.
A major technological advantage of the Thin-Film-SOI technology is the easy way of lateral insulation of
elements inside the silicon film. The thin film technology allows each device to be separated from all other
devices by a simple local oxidation (LOCOS) process. Thus, there is no need for CMOS-wells for preventing the
"latch-up" effect and reducing the chip size.
The small size of PN-junctions inside the thin silicon film leads to higher switching speed, lower leakage
currents and consequently higher temperature stability. In order to obtain a proper body contact for the thin SOIMOS transistor the channel doping is extended and connected to a common source contact (split source
contact). Hence the thin-film SOI-MOS transistor exhibits an anti-paralleled diode that safeguards the device in
case of polarity reversal.
In spite of the thin drift regions inside the silicon films, reasonable low on-resistance per area is achieved. This
allows a cost effective layout of the output driver transistors.
The SOI technology is also implemented for the 600 V level-shift transistors and high-voltage diodes. The 600VNMOSFET is based on the low-voltage SOI-NMOSFET structure in conjunction with a very long Drainextension. The buried oxide insulation barrier cuts off parasitic current paths between substrate and silicon film.
This prevents the latch-up effects in case that the voltage at any pin is either negative or exceeds the supply
voltage VDD. Even in case of high dv/dt switching or under elevated temperature the IC operates stable and
hence provides improved robustness.
Besides these improvements, the thin-film SOI-technology provides additional benefits like lower power
consumption and higher immunity to radioactive radiation or cosmic rays.
Final Application Note
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Rev. 2.0, 2015-04-16
EiceDRIVER(TM) Compact 2EDL family
Technical Description
3
Technical description of the 2EDL family
3.1
Control input section
All control input pins (HIN, LIN, PGND, EN) contain clamping diodes to the supply voltage VDD. The purpose of
these diodes is ESD protection. Therefore they are designed to manage low energy single pulse stresses only.
A continuous operation above the absolute maximum ratings is forbidden. A hard pull-up to the supply voltage
VDD with a pull-up resistance of 0  is possible, but it injects additional power dissipation into the IC. Please
note, that this causes additional losses and must be considered in the losses calculation.
3.1.1
High side input pins (HIN), Low side input pins (LIN)
2EDL-family
HINx
LINx
ILIN
IHIN
VDD V ; V
IH
IL
INPUT
NOISE
FILTER
VZ=5.25 V
Figure 2
Control input pin structure
All gate control input pins are equipped with an integrated diode clamp which is activated, when the input signal
is higher than the voltage at pin VDD according to Figure 2. It must be guaranteed by application design, that
these diodes are not overstressed by excessive voltages larger than VDD. Anyway, voltage spikes by crosstalk
or other low-energetic injections can be clamped to VDD. Please note that the integrated zener diode is
decoupled by a series resistor and is for internal protection than for protection against overvoltages. The HIGH
levels of the input Schmitt-trigger is typically VIH = 2.1 V and the LOW level is VIL = 0.9 V. This setting of levels
provides a full compliance to LSTTL- and 3.3V-CMOS-levels, so that the 2EDL family is compatible to common
microcontroller output pins. Some competitor’s components do not provide the full compliance to these voltage
levels, so that the connectivity to the microcontroller is a major concern. Electromagnetic interference (EMI) may
cause distortions of the control signals, so that a RC-filtering of the input pins can improve the signal integrity of
the system. The RC filter must not distort the control signal, so that the edges are still steep. A good design is
therefore to use a resistor of 100  and a capacitor of 1 nF. Please note here, that the impedance of the RC
filter must follow the I/O-pin specifications of the microcontroller, so that the controller can drive the RC-filter
sufficiently.
tFILIN
tFILIN
HIN/LIN
tIN
tIN
HIN/LIN
tIN < tFILIN
tIN < tFILIN
high
HO/LO
HIN/LIN
HO/LO
low
tIN
HIN/LIN
tIN
tIN > tFILIN
HO/LO
Figure 3
tIN > tFILIN
HO/LO
Short pulse suppression (left: short ON pulse; right: short OFF pulse)
Final Application Note
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Rev. 2.0, 2015-04-16
EiceDRIVER(TM) Compact 2EDL family
Technical Description
Both input sections (HIN and LIN) contain as well a pull-down resistor. However, this resistor is high-ohmic
(approx. 100 k) and is considered as a protection against PCB track cracks, so that the device keeps its
outputs off in these cases.
The input noise filter suppresses short pulses and prevents the driven power transistor from excessive switching
losses due to linear operation of the switching transistors. The input noise filter time at input LIN or HIN is about
tFILIN =190 ns for IGBT types. For MOSFET types, it is 100ns for high side input HIN and 150ns for low side input
LIN. This means, that an input signal must stay on its level for this period of time in order to process the state
change correctly according to Figure 3. Please note, that there is a slightly higher signal distortion between input
and output, when the input pulse duration is similar as the filter time. However, it is recommended for IGBT
anyway to stay above a minimal pulse duration of 0.8 μs in order to obtain the specified behavior of the IGBT.
Please note that unused input pin (LIN or HIN) must be biased to GND for safety consideration.
3.1.2
Enable and fault pin (EN-/FLT, 2EDL23x06PJ only)
This pin is available for 2EDL23x06PJ devices only. It is a bidirectional open drain output pin, which can shut
down the IC in input mode and which indicates either under voltage lockout (UVLO) or overcurrent in output
mode.
The signal applied to pin EN controls directly the output sections, when used in input mode. All outputs are set
to LOW, if this signal is lower than VEN- = 0.9 V typically and operation is enabled with signal levels higher than
typical VEN+ = 2.1 V. The internal structure of this pin is similar as b) in Figure 2. The pull-down resistor has a
value of typ. 73 k. The typical propagation delay time from EN to the output sections is tEN = 550 ns.
The IC is steadily enabled, when the EN pin is pulled up to the logic section supply voltage (i.e. +5V / +3.3V). In
this case, an external pull-up resistor (Rpu in Figure 4) in the range of a few k (e.g. 4.7 k) is necessary to bias
this open drain pin. It is recommended to use a pull-up resistor of min. 20k when pulling up this pin to VDD
(i.e. +15V). This pin can also be used as a redundant way to shut down the application in case that a (double)
failure occurs or a first shut down mechanism (e.g. PGND) fails by incident.
2EDL23x
+5V
To logic
µC
Rpu
EN
GPIO
Figure 4
EN/FLT
CFLT
Ron,FLT≈
35
From
UVLO
OR
73k
Latch
230µs
GND
From
ITRIPfilter
Schematic of the structure of the EN-/FLT pin
This pin indicates the failure status of the IC. The level of this pin is LOW in case of undervoltage lockout or
triggering of the overcurrent protection. The voltage at this pin is internally clamped to VDD, as one can see in
the internal structure according to Figure 4. The internal pull-down FET has a typical resistance of Ron,FLT =
35 . The delay time from the overcurrent trigger event to the change of status at the EN-/FLT-pin is tFLT =
2.1 µs typically according to the timing diagram shown in Figure 5.
vITRIP
VITRIP
0.1V
t
vFAULT
0.5V
tFLT
Figure 5
tFLT
t
Timing diagram for ITRIP to FAULT propagation delay
Final Application Note
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Rev. 2.0, 2015-04-16
EiceDRIVER(TM) Compact 2EDL family
Technical Description
3.2
IC supply section
The IC is supplied by the pins VDD and GND for the input side and the pins VB and VS for the high side
section.
The 2EDL family supports the operation of IGBT as well as power MOSFET. There is a considerable difference
between both types of power transistors in respect of driving their gates. IGBT usually have a gate threshold
voltage VGE(th) = 4.5 V … 5 V, where power MOSFET have a gate threshold of VGS(th) = 3 V … 4 V. As a
consequence, MOSFET are usually driven sufficiently with a gate source voltage of VGS = 10 V without losing
conduction performance, where IGBT need a recommended gate emitter voltage of VGE = 15 V. This difference
is considered in the two different undervoltage lockout (UVLO) levels of the 2EDL family. The absolute
maximum rating is in all cases VDD,max = 20 V regardless of the undervoltage lockout levels.
Please note that the decoupling capacitor for the driver IC supply should be put as close as possible to the
supply pins (VDD and VB), it should be ceramic type and µA range is expected as minimum.
3.2.1
IGBT types
The supply voltage VDD of the IC must reach initially at least a typical voltage of VDDUV+ for the low side (input
side) and VBSUV+, respectively for the high side supply, before the IC gets into an operational state. The levels
are asymmetric, which has advantages for bootstrapping when using the integrated bootstrap diode. The levels
of these parameters are VDDUV+ = 12.5 V and VBSUV+ = 11.6 V according to Figure 6. It is recommended to have
a margin of at least 1 V in respect to VDDUV+ and VBSUV+ in order to avoid unintended shut-down caused by noise.
The shutdown levels of the UVLO function are also asymmetric. The IC shuts down the individual gate sections,
when the related supply voltage is below typ. VDDUV- = 11.6 V or typ. VBSUV- = 10.7 V. This prevents the driven
transistors from critically low gate voltage levels during on-state and therefore from excessive power dissipation.
Please refer to section 3.5.3 for further information.
VDDMAX , VBSMAX
vDD
vBS
20
V
17.5
13
VDDUV+ 12.5
VBSUV+, VDDUV- 11.6
VBSUV- 10.7
t
IC STATE
OFF
Figure 6
3.2.2
HS
ON
on
ON
Recommended
Area
ON
Forbidden
Area
ON
ON
Recommended Area
ON
HS
on
OFF
Typical areas of operation for IGBT types
MOSFET types
MOSFET types do not have the asymmetric UVLO levels. The turn-on levels of the UVLO function are VDDUV+ =
VBSUV+ = 9.1V for the low side and high side supply. The IC shuts down the individual gate sections, when the
related supply voltage is below VDDUV- = VBSUV- = 8.3 V. Please refer to section 3.5.3 for further information.
Figure 7 shows the IC states and the correlated areas of operation concerning the supply voltages for both the
low side supply voltage VDD and the high side supply voltages vBS. There are different limits for IGBT and
MOSFET type driver IC. The forbidden area is for supply voltages above 20 V, because here the internal
clamping structures begin to break through and the IC is endangered to be damaged by locally excessive power
dissipation.
Final Application Note
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Rev. 2.0, 2015-04-16
EiceDRIVER(TM) Compact 2EDL family
Technical Description
20
V
17.5
vDD
vBS
13
VBSUV+, VDDUV+ 9.1
VBSUV-, VDDUV- 8.3
t
IC STATE
OFF
Figure 7
ON
ON
Recommended
Area
ON
Forbidden
Area
ON
ON
Recommended Area
ON
OFF
Typical areas of operation for MOSFET types
3.3
Output sections
3.3.1
Low side gate drive
The low side gate drive sections contain FET in push-pull configuration. The source transistor is p-channel type
and the sink transistor is n-channel type, so that rail-to-rail behavior is implemented. The typical turn-on current
is IO+ = 230 mA and a typical turn-off current of IO- = 480 mA for the 0.5A types. The versions with large output
currents have typically IO+ = 1800 mA and a typical turn-off current of IO- = 2300 mA. There is a level shift
structure included in the 2EDL family between PGND and GND levels in order to allow a proper gate drive
referenced to pin PGND (2EDL23x06PJ) or GND (others).
2EDL family
VDD
DELAY
GND / PGND
LEVELSHIFTER
PMOS
IO
+
NMOS
RG
LO
IO
-
GND
GND (2EDL05)/
PGND (2EDL23)
Figure 8
Structure of the low side gate drive section
The output pin LO is clamped to the supply voltage VDD of the IC via the body diodes of the FET. This prevents
the output pins from excessive pulse voltages, which may be coupled into the gate track. There is also an
internal zener clamp of the push-pull circuit between GND and VDD.
3.3.2
High side section
The high side gate drive section is shown in Figure 9. The control signal passes the high voltage level shift
section and is stored in the gate drive flip-flop latch. The output gate drive signal HO is clamped internally by
integrated diodes to the reference voltage (pin VS) and the bias voltage (pin VB), which is identical to the low
side sections.
Final Application Note
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Rev. 2.0, 2015-04-16
EiceDRIVER(TM) Compact 2EDL family
Technical Description
Please note, that there is a parasitic connection from high side to the low side control area. It must be
guaranteed by the design of the individual application, that there are no negative voltages lower than -50 V
referred to GND at pin VS, which last longer than 500ns according to the maximum rating of the datasheet of
2EDL family. The negative voltages can also affect the signal transmission over the level shift structure. There is
no signal transmission possible, when the voltage at pin VB is smaller than 7V with reference to GND, i.e. VBGND
< 7.0 V.
All members of the 2EDL family contain an integrated bootstrap diode. Please refer to section 3.4 for further
information about the integrated bootstrap diode.
2EDL family
Bootstrap diode
HV LEVELSHIFTER
VB
LATCH
DRIVER
HO
UVLO
VS
Figure 9
3.3.3
Structure of the low side gate drive section
Negative transients at high side reference (pin VS)
The 2EDL family is very robust against negative transient voltages thanks to the inherent oxide insulation of the
SOI-technology. Therefore, the minimum voltage at the pins VS is specified to -50 V for a period of time of
500 ns. This duration is long enough to cover the usual requirement for this stress in drives and switch mode
power supply applications. However, it must be the target of any design to avoid such negative voltages at all.
Parasitic inductances can induce voltages, so that the potential at pin VS becomes negative in respect to pin
GND. It is a well-known failure mechanism of other driver IC technologies that these negative voltages force
current through the substrate material. The substrate currents can lead to a latch of the high side gate driver or
other malfunction, which is then insensitive to any control signal. The result is, that the IGBT are operated in
short circuit, which leads to excessive power dissipation and also to system breakdown.
The negative voltage can also increase the pulse current through the internal bootstrap diode or to an
increased / excessive bootstrap voltage in general. The design target is therefore to avoid such negative
transient voltage at all or to keep at least the absolute maximum ratings.
3.4
Bootstrapping
3.4.1
Temperature stability of bootstrap diode and application range
All parts of the 2EDL family contain integrated bootstrap diodes and low ohmic current limiting resistors.
Especially the low ohmic current limiting resistors provide essential advantages over other competitor devices
with high ohmic bootstrap structures. A low ohmic resistor such as in the 2EDL family allows faster recharching
of the bootstrap capacitor during periods of small duty cycles on the low side transistor. Such points of operation
occur e.g. during low speed operation of drives at high torque, which can be excellently controlled with field
oriented control of induction, permanent magnet synchronous or BLDC motors. There is usually no complete
recharging possible any more during small duty cycles, so that the bootstrap voltage at the bootstrap capacitor
CBS sinks. The design must ensure, that the gate is always supplied properly in order to avoid excessive
conduction losses and hence IGBT damage. A low ohmic current limiting resistor such as in the 2EDL family
leads to sufficient bootstrap supply, when the LS transistor is operated at 2% duty cycle according to Figure 10.
The solid lines represent the PWM modulated ripple at room temperature. It is assumed as a rule of thumb, that
the Rds(on) of any bootstrap FET is doubled, when the temperature increases by 100°C. The resulting curves at
125°C are shown as dashed lines. It is easy to see that the situation gets even more severe at 125°C with
competitor devices, which use FET structures. A sufficient supply is here only possible with duty cycles above
approx. 10% or even higher. A diode, which is used in the 2EDL family is much more temperature robust.
Hence, the 2EDL family can be still used at high temperatures with a duty cycle of the low side transistor of 2%!
The bootstrap diode is usable for all kind power electronic converters. The bootstrap diode is a real pn-diode
and not a FET structure of a similar workaround. The bootstrap diode of the 2EDL-family is applicable for all
Final Application Note
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Rev. 2.0, 2015-04-16
EiceDRIVER(TM) Compact 2EDL family
Technical Description
control modes of modern power electronics, such as trapezoidal or sinusoidal drives control, continuous or
discontinuous PWM schemes. No restrictions do limit designs or PWM schemes, when using the integrated
bootstrap diode.
Figure 10
3.4.2
Voltage drop of bootstrap voltage in steady state vs. duty cycle of LS transistor
Supply voltage range calculation
The UVLO limits for IGBT types are designed in a way, that they support both, a proper start up as well as a
save operation in PWM. It is the initial charging of the bootstrap capacitor during startup which must ensure, that
the maximum limit of VBSUV+ is exceeded, so that the high side section is ready to operate. This means that the
bootstrap capacitor CBS according to Figure 11 is not charged, when the low side transistor T2 turns on. The
related equation for the minimum supply voltage of IGBT types at the end of the charging cycle is
DDminIGBT = BSUV+max + FBSmax + CE,LS = 12.4 V + 1.2 V + 0.5V = 14.1 V
(1)
where VBSUV+max is the maximum value for the positive going UVLO level of the high side section, VFBSmax is the
maximum bootstrap voltage and VCE,LS is the low side IGBT voltage. A shunt voltage can be neglected for initial
charging. It can easily be seen, that a supply voltage of VDD = 15 V is sufficient.
For MOSFET types there is
DDminMOSFET = BSUV+max + FBSmax = 9.9 V + 1.2 V = 11.1 V
(2)
which means, that a supply voltage of VDD ≈ 12 V is sufficient.
Another point of operation, which occurs in drive systems, is the operation at full load and low speed. It can be
assumed for the case that the PWM frequency is much larger than the motor frequency (i.e. fp » fMot), that there
are periods of time, where the low side IGBT is almost continuously on. The IC should not go into UVLO
protection there. The calculation is
BS,IGBT = VDD − 1.2 V − CE,LS (nom ) – Sh =
= 15 V − 1.2 V − 1.8 V − 10A ∙ 20mΩ = 11.8 V > BSUV−max
(3)
This equation goes with the assumption, that a shunt resistance of RSh = 20 m is used for a 10A-IGBT.
In case VBS,IGBT < VBSUV-max, the VVDD value should be chosen to have a value higher than 15V accordingly.
Final Application Note
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Rev. 2.0, 2015-04-16
EiceDRIVER(TM) Compact 2EDL family
Technical Description
3.4.3
Calculating the bootstrap capacitance CBS
Bootstrapping is a common method of pumping charges from a low potential to a higher one. With this
technique a supply voltage for the floating high side sections of the gate drive can be easily established
according to Figure 11. This circuit is shown for one of the three half bridges of a drives application.
VBus
VDD
CVDD
RLim DBS
VB
CBS
Gate HO
Drive VS
IC
LO
D1
T2
D2
GND
Figure 11
T1
Bootstrap circuit for one half bridge
The first pulse of transistor T2 will force the potential of pin VS to GND. The existing difference between the
voltage of the bootstrap capacitor VCBS and VDD results in the charging current iBS into the capacitor CBS. The
current iBS is a pulse current and therefore the ESR of the capacitor C BS must be very small in order to avoid
losses in the capacitor that result in lower lifetime of the capacitor.
This pin is on high potential again after transistor T2 is turned off and either T1 or D1 is conducting current. But
now the bootstrap diode DBS blocks a reverse current, so that the charges on the capacitor cannot flow back to
the capacitor CVDD. The bootstrap diode DBS also takes over the blocking voltage between pin VB and VDD. It is
good engineering to choose the same blocking voltage of power transistor T1 and external bootstrap diode. The
voltage of the bootstrap capacitor can now supply the high side gate drive sections.
It is a general design rule for the location of bootstrap capacitors CBS, that they must be placed as close as
possible to the IC. Otherwise, parasitic resistors and inductances may lead to voltage spikes, which may trigger
the undervoltage lockout threshold of the individual high side driver section. However, all parts of the 2EDL
family, which have the UVLO for IGBT also contain a filter at each supply section in order to actively avoid such
undesired UVLO triggers.
The voltage of bootstrap capacitor is approximately
CBS ≈ DD − FBS − CE,LS
(4)
A current limiting resistor RLim according to Figure 11 reduces the peak of the pulse current during the turn-on
of transistor T2. The pulse current will occur at each turn-on of transistor T2, so that with increasing switching
frequency the capacitor CBS is charged more frequently. Therefore a smaller capacitor is suitable at higher
switching frequencies. The bootstrap capacitor is mainly discharged by two effects: The high side quiescent
current and the gate charge of the transistor to be turned on. The calculation of the bootstrap capacitor results in
QBS ∙ P + G
BS =
∙ 1.2
(5)
∆BS
with iQBS being the quiescent current of the high side section, tP the switching period, QG the total gate charge
and vBS the voltage drop at the bootstrap capacitor within a switching period. An additional margin of 20% is
added for the case of tolerances for the bootstrap capacitor. Please note, that the value QG may vary to a
maximum value and the capacitor shows voltage dependent derating behavior of its capacitance. Equation (5) is
valid for pulse by pulse considerations. It is easy to see, that higher capacitance values are needed, when
operating continuously at small duty cycles of T2 or D2, e.g. in discontinuous conduction mode.
Figure 12 shows the curve corresponding to equ. (5) for a continuous sinusoidal modulation, if the voltage ripple
vBS = 0.1 V. The recommended bootstrap capacitance is therefore in the range up to 4.7 μF for most switching
frequencies. The performance of the integrated bootstrap diode supports the requirement for small bootstrap
capacitances. It is therefore recommended not to exceed a maximum capacitance of CBS = 47 µF.
Please note here, that equ. (5) is valid for continuous switching operation according to the switching frequency.
The use of space vector modulations can cause periods up to 60° (electrical), in which no switching of the low
side transistor of a half bridge occurs and must be considered separately. This effects the bootstrap capacitor
Final Application Note
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Rev. 2.0, 2015-04-16
EiceDRIVER(TM) Compact 2EDL family
Technical Description
size, especially for low output current (motor current) frequencies. In this case the variable tP must be set to the
longest period of no charging.
5
µF
4
3
2
1
CBS
0
0
5
10
kHz
15
20
fP
Figure 12
Size of the bootstrap capacitor as a function of the switching frequency fP for driving
IKD10N60R according to equ. (5) with a voltage ripple of 0.1 V
3.5
Protection
3.5.1
Overcurrent protection (OCP, 2EDL23x06PJ only)
The current signal of the DC-link reference is measured in order to recognize overcurrent or half bridge short
circuit events. A shunt resistor generates a voltage drop, which triggers a comparator with a threshold of
VITRIP,TH+ = 0.46 V according to Figure 13. An integrated filter with a time constant of 1.8 µs suppresses potential
voltage spikes caused by non-optimal layout or by reverse recovery events, when commutating on the diode of
a low side switch.
This triggering current is calculated with
ITRIP =
IT,TH+
SH
(6)
where RSH is the value of the shunt resistor.
It is generally recommended as good engineering to use low inductive SMD shunts (maximum allow power
should not be violated). These shunts are wide spread in the market and generate only small inductive transient
voltages. Such voltages can disturb e.g. the current sensing signal, but also a proper operation of current
sensing amplifiers or comparators. Other shunt solutions generally have more disadvantage comparing with
SMD shunts so that it is not prefered. The maximum allowed voltage level at pin PGND (as shown in Figure 13)
must be fulfilled under any circumstance. In case big overvoltage due to noise or paracistic effect can be
observed, measures need to be taken to protect the PGND pin, e.g. back to back connected zener diodes or
decoupling capacitor which are tied between PGND and GND.
The output of the comparator passes a noise filter, which inhibits an overcurrent shutdown caused by parasitic
voltage spikes. The typical filter time of the noise filter is tFILITRIP = 1.8 µs. This is a large filter, but the connection
of the shunt sense track to pin PGND, which is the return path of the gate current, does not allow any external
filtering. A set-dominant latch stores the overcurrent event for typically 230 µs until it is reset either by the
external pull up resistor or by a signal provided from the microcontroller. The reset is realized by pulling the
voltage at pin EN-/FLT higher than the input high level voltage VIH.
Final Application Note
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Rev. 2.0, 2015-04-16
EiceDRIVER(TM) Compact 2EDL family
Technical Description
CollectorHS
2EDL23x
GateDrive
LO
iSh
+5V
GND
Rpu
EN/FLT
From /
To µC
Figure 13
CFLT
PGND
VITRIP,TH+
VITRIP,TH,hys
EN
Ron,FLT≈
35
Latch
230µs
Rsh
GND
+
Filter (1.8µs)
-
All red tracks
to be short !
0.46
V
Internal structure of the ITRIP and EN-/FLT sections
The ITRIP-latch activates the discharging NMOS-FET at pin EN-/FLT. The RDS(on) of this FET (Ron,FLT) is typically
35 Ω, so that there is a characteristical discharge curve in respect of the external capacitor C FLT. The time
constant is defined by the external capacitor CFLT and the Ron,FLT. The discharge phase ends, when the
comparator is low again. This corresponds to a voltage level at the comparator of V IT,TH+ - VIT,HYS = 460 mV –
70 mV = 390 mV, where VIT,HYS = 70 mV is the hysteresis of the ITRIP-comparator.
To avoid repetitively switching on and off of driver IC and power devices during a continuously ITRIP events
(e.g. real short circuit), each ITRIP event should trigger the blanking logic which will block the input signal. To
achieve this, the voltage at pin EN-/FLT must be reduced (by discharging external CFLT) lower than the minimal
VEN,TH– (0.7V for this product) value inside the 230µs latch time, which follows the equation
−
(7)
EN = 0 ∗  on,FLTFLT < EN,TH−_min
here, the V0 is the voltage at pin EN-/FLT which is defined by the external pull-up power supply (+5V in this
example). The value of CFLT must be carefully chosen according to this equation, so that too big capacitor can
be avioded.
DC bus
Cgc
Dcl
VDD
HIN
LIN
EN/ FLT
dvCE
dt
VB
HO
VS
VS
To Load
Dcl
LO
GND
Figure 14
PGND
- DC Bus
Short circuit clamping
Another issue should be noticed that, when short circuit or over current happens (e.g. VS short to ground) as
shown in Figure 14, due to the high dv/dt across the power device there will be displacement current going
through the Miller capacitor, the gate voltage will be further lifted up. In this case the current of the power device
will be further increased which could easily damage the power device. To prevent this, an external clamping
diode (Dcl) between gate of power device and the supply pin of driver IC (VB) is recommended. The same
theory also applies to low side circuit, here the gate of power device need to be clamped to VDD.
Final Application Note
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Rev. 2.0, 2015-04-16
EiceDRIVER(TM) Compact 2EDL family
Technical Description
3.5.2
Deadtime & Shoot Through Prevention
The 2EDL family prevents shoot through and generates a fixed deadtime between the individual power devices
of each half bridge. The deadtime is typically DT = 380 ns for IGBT version and DT = 75 ns for MOSFET
version. However, it is necessary to check the transient times of the driven power devices. These times are the
turn-on delay td(on), the rise time tr, the turn-off delay time td(off) and the fall time tf. They are defining the timing
and the deadtime which is mandatory for the prevention of shoot through. A deadtime of 1 μs to 1.5 μs is
sufficient for most applications. Please note, that especially the transient behavior of power transistors can limit
the minimum dead time depending on junction temperature, collector current and gate resistance.
It is only the type 2EDL05I06BF, which does not have any dead time and interlocking implemented. This part is
the optimal driver IC for switched reluctance motors (SRM), welding systems using two-transistor-forward
topology and other applications, where it is required to turn on the high side output simultaneously to the low
side output.
3.5.3
Undervoltage Lockout (UVLO)
Both output sections are shut down in case of an undervoltage condition on the pin VDD by blocking the signals
to the low side and the high side section. There is an additional undervoltage detection for the high side only, so
that the high side section can also be shut down independently from the low side. The levels are VDDUV+ for the
control side and VBSUV+ for the high side sections. Please refer to the correct absolute level in respect to the
individual type of the 2EDL family. Please refer to section 3.2 for further information.
In case of an UVLO shut down of an output section, it is necessary to reach the start-up levels of VDDUV+ and
VBSUV+ again as described in section 3.2. The independent UVLO functions of the low and high side section
enable a restart of the affected high side section in case of a bootstrapping supply, because the switch mode
operation of the low side transistor pumps continuously charges into the according bootstrap capacitor, which
increases the bootstrap voltage VBS.
All IGBT type driver IC of the 2EDL family contain a filter (approx. 1.5µs) for the supply voltage level VDD and the
high side supply voltage level VBS. This avoids undervoltage events, which are caused by noise or crosstalk as it
is shown in Figure 15. The outputs shut down in any case, when VDD or VBS drops below 7.5 V. The type
2EDL23I06PJ and 2EDL23N06PJ indicates the UVLO by pulling the pin EN-/FLT down to ground. The types
2EDL05I06PF and 2EDL05I06PJ also filter the supply levels, but don´t indicate this by a specific pin.
No UVLO
UVLO triggered
VUVLO–
t < tFILVDD
or t < tFILVBS
vDD
vBS
7.5 V
t < tFILVDD
or t < tFILVBS
t
t > tFILVDD
or t > tFILVBS
vLO
vHO
t
Figure 15
UVLO filter time
All MOSFET types (2EDL23N06PJ and 2EDL05N06PF) have a filter time for UVLO in the range of approx.
150 ns.
3.6
Calculation of power dissipation and thermal aspects
The 2EDL family is available in two packages, the PG-DSO-8 and the PG-DSO-14. Both packages are RoHS
compliant. Please refer to section 3.7 for further information in respect to the insulation coordination. It is
essential to assure, that the component is not thermally overloaded. This can be checked by means of the
thermal resistance junction to ambient and the calculation or measurement of the dissipated power. The thermal
resistance is given in the datasheet (section 4) and refers to a specific layout. Changes of this layout may lead
to an increased thermal resistance, which will reduce the total dissipated power of the driver IC. One should
therefore do temperature measurements in order to avoid thermal overload under application relevant
conditions of ambient temperature and housing.
Final Application Note
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Rev. 2.0, 2015-04-16
EiceDRIVER(TM) Compact 2EDL family
Technical Description
The maximum chip temperature Tj can be calculated with
j = d ∙ th(ja) + amb,max
(8)
where Tamb, max is the maximum ambient temperature.
The dissipated power Pd is a combination of several sources. The following items contribute to the total power
dissipation:
- the quiescent current (high side and low side) of the IC (Pd1VDD, Pd1BS)
- the output section (Pd2on, Pd2off)
- the input sections of the IC (Pd3)
- the leakage losses between any high side section to the control section (Pd4)
The individual items can be calculated for a worst case by means of the following cooking recipe:
1. Measure the operating current IDD for maximum switching frequency of the application. Connect both control
pins and do not connect power transistors.
d1VDD = DD,ma ∙ DD,max
(9)
Each high side section generates continuous power dissipation in respect of the quiescent current. This is given
as
d1BS = QBS ∙ BS,max
(10)
2. Calculate the losses of the output section by means of the total gate charge of the power transistor QGtot , the
supply voltage VDD, the switching frequency fP ,and the ext. gate resistor. Different cases for turn-on and turn-off
must be considered, because many designs use different resistors for turn-on and turn-off. This leads to a
specific distribution of losses in respect to the external gate resistor R Gxx,ext and the internal resistance of the
output section. When we take 2EDL 0.5A version as an example
d2on =
2
22.5Ω
G,to ∙ DD ∙ P ∙
2
Gon,ext + 22.5Ω
, for turn-on
(1)
2
6.5Ω

∙ ∙ ∙
2 G,tot DD P Goff,ext + 6.5Ω
, for turn-off
(2)
d2off =
If the 2EDL 2.3A version is used
d2on =
2
7Ω

∙ ∙ ∙
2 G,to DD P Gon,ext + 7Ω
, for turn-on
(3)
d2off =
2
5Ω

∙ ∙ ∙
2 G,tot DD P Goff,ext + 5Ω
, for turn-off
(4)
Both portions Pd2on and Pd2off together are the output section losses.
3. The input sections generate losses by means of their input structures. These are pull-down resistors of
approx. 100 k
d3 =
2 in 2
∙
2 100kΩ
(5)
4. The leakage losses are given by the current, which crosses the insulation barrier. The relevant parameters
are the leakage current ILVS of any high side and the DC bus voltage VDC of the application. The high side
section is either on the positive bus potential or at the negative bus potential during operation. It is therefore in
principle half the product of these two values. However, there can be a static status of operation, where all three
high side sections are on high potential. Thus, we get
d4 = LVS ∙ DC,max
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EiceDRIVER(TM) Compact 2EDL family
Technical Description
All remaining contributions can be estimated as approximately 20% of the sum of the above mentioned portions.
The final power dissipation during operation is then the sum of both contributions
d = 1.2 (d1VDD + d1QBS + d2on + d2off + d3 + d4 )
(7)
The datasheet shows specific layouts, for which the given thermal resistance junction to ambient (Rth(j-a)) is valid.
The thermal resistance which is given in the datasheet is specified for equal operation of both power transistors.
It is important to know, that different layouts may lead to different thermal resistances. It is therefore always
good engineering praxis to examine additionally the package temperature by experiment.
3.7
Creepage
The creepage distance of the DSO-8 package (2EDL05I06PF, 2EDL05N06PF and 2EDL05I06BF) is 2.140 mm
according to the package drawing. The related parameter for 2EDL05I06PJ is 2.865 mm, for 2EDL23I06PJ and
2EDL23N06PJ it is 2.105 mm. It depends on the individual application standard, such as [3] or [4], the safety
concept of the end device as well as the application conditions, such as pollution degree, etc. to identify the
relevant requirements for the system.
The mentioned standards and similar ones describe in detail the relevant considerations for an appropriate
calculation of the creepage distance for the target system.
3.8
Design considerations
Please note, in no circumstance the driver IC can be used in parallel (it is not allowed to connect several driver
ICs in parallel).
3.9
Layout considerations
Parasitic in inductances the ground circuit or in the gate circuits exist by means of PCB track loops. They can
lead to oscillations in the according tracks. This can be the root cause of abnormal function of the IC. Figure 16
shows these inductances and track loops.
First of all, the gate tracks, which connect the pins HO and LO with the according gate terminal of the power
transistor and the tracks connecting the emitter / source terminals of the power transistor with the VS or PGND
of the IC must be as short as possible. The area of these tracks must be minimized. This ensures, that the
switching speed of the high side transistor and the low side transistor are similar or even equal. The loop, which
consists of pin PGND, the shunt resistor and pin GND should be as well minimized. Figure 16 shows the case of
a single shunt design. Some systems may use one shunt in each phase of the drive, which is located between
source / emitter of the low side transistor and the pin PGND. The driver IC is usually stabilized by means of a
low impedance capacitor, which may be a ceramic type. The loop between pin VDD, the capacitor and GND
should also be as small as possible. This helps to minimize the gate circuit inductances as well as the bootstrap
circuit inductances.
A similar consideration must be done for the high side supply circuit. The loop of pins VB, the bootstrap
capacitor CBS, and the pin VS must also be small. Otherwise, there may be inductive voltage drops during the
gate charging process of turn-on, which may result in spontaneous undervoltage lockout events at the high side
section.
Final Application Note
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Rev. 2.0, 2015-04-16
EiceDRIVER(TM) Compact 2EDL family
Technical Description
VDC
VDD
CBS
VB
HO
VS
CDC
Small and
short loops
LO
PGND
RSh
GND
Figure 16
Low
inductive
shunt
Parasitic inductances in the layout
Finally, the inductances of the DC link tracks can be partially cancelled, if one places a low impedance film
capacitor between the positive and negative rail closely to the transistor terminals as shown in Figure 16 with
CDC.
Final Application Note
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EiceDRIVER(TM) Compact 2EDL family
Technical Description
4
List of used parameters
4.1
General
big letters
small letters
italic letters
upright letters
Time constant parameters
Time varying parameters
physical parameters
components in circuits
Table 2
Used parameters
Parameter
Description
A
area
p, P
power
b, B
flux density
r, R
resistance
C
Parameter
Description
capacitance
t, T
time, time intervals
d, D
duty cycle
v, V
voltage
f
frequency
w, W
energy
i, I
current

efficiency
l, L
inductance
C
capacitor

L
inductor
D
diode
R
resistor
IC
integrated circuit
TR
transformer
AC
alternating current value
i
running variable
avg
average
in
input value
DC
direct current value
max
maximum value
BE
basis-emitter
min
minimum value
C
collector value
off
turn-off / off-state value
E
emitter value
on
turn-on / on-state value
G
gate value
out
output value
P
primary side value
p
pulsed
Pk
peak value
S
secondary side value
Final Application Note
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Rev. 2.0, 2015-04-16
EiceDRIVER(TM) Compact 2EDL family
Technical Description
References
[1]
KOA corporation: “Handling precautions for flat chip resistors”, Revision B 1.1, application note, KOA
corporation, Japan, 2007
[2]
KOA corporation: “Flat chip thick film resistors general purpose RK73B”, Revision 10.11.2006, data sheet,
KOA corporation, Japan, 2006
[3]
IEC 60335-1: "Household and similar electrical appliances – Safety – Part 1: General requirements”, Ed. 4,
2001-05; International Electrotechnical Commission; Geneva, Switzerland, 2001
[4]
IEC 664-1: "Insulation coordination for equipment within low-voltage systems – Part 1: Principles,
requirements, tests”, Ed. 1, 1992-10; International Electrotechnical Commission; Geneva, Switzerland,
1992
Final Application Note
AN2013-11
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Rev. 2.0, 2015-04-16
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
AN-EICEDRIVER-2EDL-1
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