2EDL23I06PJ Data Sheet (1,007 KB, EN)

Eice DR IV ER ™ Co m pac t
High voltage gate driver IC
2E DL fa mi ly
600 V half bridge gate drive IC
2EDL23I06PJ
2EDL23N06PJ
EiceDRIVER™ Compact
Final dat a sheet
<Revision 2.2>, 01.06.2016
Final
Indust rial Po wer C o ntrol
Edition 01.06.2016
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2016 Infineon Technologies AG
All Rights Reserved.
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EiceDRIVER™ Compact
2EDL family
Revision History
Page or Item
Subjects (major changes since previous revision)
<Revision 0.86>, 15.05.2014
all
change term VCC in VDD
<Revision 2.2>, 01.06.2016
o
o
Update maximum Ta from 95 C to 105 C in Table 5
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Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex
Limited.
Last Trademarks Update 2010-10-26
Final datasheet
3
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EiceDRIVER™ Compact
2EDL family
Table of Contents
1
Overview ............................................................................................................................................. 7
2
Blockdiagram...................................................................................................................................... 9
3
3.1
3.2
3.2.1
3.2.2
3.2.3
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
Pin configuration, description, and functionality ......................................................................... 10
Pin Configuration and Description...................................................................................................... 10
Low Side and High Side Control Pins (LIN, HIN) ............................................................................... 10
Input voltage range ............................................................................................................................ 10
Switching levels .................................................................................................................................. 10
Input filter time .................................................................................................................................... 11
VDD, GND and PGND (Low Side Supply) ......................................................................................... 11
VB and VS (High Side Supplies) ........................................................................................................ 11
LO and HO (Low and High Side Outputs) .......................................................................................... 11
Undervoltage lockout (UVLO) ............................................................................................................ 12
Bootstrap diode .................................................................................................................................. 12
Deadtime and interlock function ......................................................................................................... 12
EN-/FLT (fault indication and enable function) ................................................................................... 12
Power ground / over current protection .............................................................................................. 13
4
4.1
4.2
4.3
4.4
4.5
4.6
Electrical Parameters ....................................................................................................................... 14
Absolute Maximum Ratings ............................................................................................................... 14
Required operation conditions ........................................................................................................... 15
Operating Range ................................................................................................................................ 15
Static logic function table ................................................................................................................... 16
Static parameters ............................................................................................................................... 16
Dynamic parameters .......................................................................................................................... 18
5
Timing diagrams............................................................................................................................... 19
6
6.1
Package ............................................................................................................................................. 22
PG-DSO-14 ........................................................................................................................................ 22
Final datasheet
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2EDL family
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Typical Application ............................................................................................................................... 8
Block diagram for 2EDL23x06PJ ......................................................................................................... 9
Pin Configuration of 2EDL family ....................................................................................................... 10
Input pin structure............................................................................................................................... 11
Input filter timing diagram ................................................................................................................... 11
EN-/FLT pin structures and interface to microcontroller (µC) ............................................................ 12
Timing of short pulse suppression ..................................................................................................... 19
Timing of of internal deadtime ............................................................................................................ 19
Enable delay time definition ............................................................................................................... 19
Input to output propagation delay times and switching times definition ............................................. 20
Operating areas (IGBT UVLO levels)................................................................................................. 20
Operating areas (MOSFET UVLO levels) .......................................................................................... 20
ITRIP-Timing ...................................................................................................................................... 21
Output pulse width timing and matching delay timing diagram for positive logic ............................... 21
Package drawing ................................................................................................................................ 22
PCB reference layout (according to JEDEC 1s0P) left: Reference layout right: detail of footprint .... 22
Final datasheet
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2EDL family
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Members of 2EDL family ...................................................................................................................... 7
Pin Description ................................................................................................................................... 10
Abs. maximum ratings ........................................................................................................................ 14
Required Operation Conditions .......................................................................................................... 15
Operating range ................................................................................................................................. 15
Static parameters ............................................................................................................................... 16
Dynamic parameters .......................................................................................................................... 18
Data of reference layout ..................................................................................................................... 22
Final datasheet
6
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EiceDRIVER™ Compact
2EDL family
EiceDRIVER™ Compact
600 V half bridge gate drive IC
Overview
1
Main features
PG-DSO-14

Thin-film-SOI-technology

Maximum blocking voltage +600V

Individual control circuits for both outputs

Filtered detection of under voltage supply

All inputs clamped by diodes

Active shut down function

Asymmetric undervoltage lockout thresholds for high side and low side

Qualified according to JEDEC (high temperature stress tests for 1000h) for target applications
1
Product highlights

Insensitivity of the bridge output to negative transient voltages up to -50V given by SOI-technology

Ultra fast bootstrap diode

Overcurrent comparator

Enable function, Fault indicator
Typical applications

Home appliances

Consumer electronics

Fans, pumps

General purpose drives
Product family
Table 1
Members of 2EDL family
Sales Name
2EDL23I06PJ
Special function
output
current
Target
transistor
typ. LS UVLOthresholds
Bootstrap Package
diode
deadtime, interlock,
2.3 A
IGBT
12.5 V / 11.6 V
Yes
DSO-14
2.3 A
MOSFET
9.1 V / 8.3 V
Yes
DSO-14
Enable, Fault, OCP
2EDL23N06PJ
deadtime, interlock,
Enable, Fault, OCP
1
J-STD-020 and JESD-022
Final datasheet
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2EDL family
Description
The 2EDL family contains devices, which control power devices like MOS-transistors or IGBTs with a maximum
blocking voltage of +600V in half bridge configurations. Based on the used SOI-technology there is an excellent
ruggedness on transient voltages. No parasitic thyristor structures are present in the device. Hence, no parasitic
latch up may occur at all temperature and voltage conditions.
The two independent drivers outputs are controlled at the low-side using two different CMOS resp. LSTTL
compatible signals, down up to 3.3V logic. The device includes an under-voltage detection unit with hysteresis
characteristic which are optimised either for IGBT or MOSFET.
Those parts, which are designed for IGBT have asymmetric undervoltage lockout levels, which support strongly
the integrated ultrafast bootstrap diode. Additionally, the offline gate clamping function provides an inherent
protection of the transistors for parasitic turn-on by floating gate conditions, when the IC is not supplied via VDD.
+ DC-Bus
+5V
VDD
PWM_H
HIN
VB
HO
PWM_L
LIN
VS
EN/FLT
EN
/CTRAP
2EDL23x06PJ
LO
GND
GND
Figure 1
To
Load
To Opamp /
Comparator
GND
PGND
- DC-Bus
Typical Application
Final datasheet
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2EDL family
2
Figure 2
Blockdiagram
Block diagram for 2EDL23x06PJ
Final datasheet
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2EDL family
3
Pin configuration, description, and functionality
3.1
Pin Configuration and Description
2EDL (SO8)
2EDL (0.5A, SO14)
2EDL (2.3A, SO14)
1
VDD
VB
8
1
nc
nc 14
1
VDD
nc
14
2
HIN
HO
7
2
VDD
nc 13
2
HIN
nc
13
3
LIN
VS
6
3
HIN
VB 12
3
LIN
VB
12
4
GND
LO
5
4
LIN
HO 11
4
EN-/FLT
HO
11
5
GND
VS 10
5
GND
VS
10
6
LO
nc
9
6
PGND
nc
9
7
nc
nc
8
7
nc
8
Figure 3
Table 2
LO
Pin Configuration of 2EDL family
Pin Description
Symbol
Description
VDD
Low side power supply
GND
Logic ground
HIN
High side logic input
LIN
Low side logic input
EN-/FLT
Enable input and Fault indication output
PGND
Low side gate driver reference
VB
High side positive power supply
HO
High side gate driver output
VS
High side negative power supply
LO
Low side gate driver output
nc
Not Connected
3.2
Low Side and High Side Control Pins (LIN, HIN)
3.2.1
Input voltage range
All input pins have the capability to process input voltages up to the supply voltage of the IC. The inputs are
therefore internally clamped to VDD and GND by diodes. An internal pull-down resistor is high ohmic, so that it
can keep the IC in a safe state in case of PCB crack.
3.2.2
Switching levels
The Schmitt trigger input threshold is such to guarantee LSTTL and CMOS compatibility down to 3.3 V
controller outputs. The input Schmitt trigger and noise filter provide beneficial noise rejection to short input
pulses according to Figure 4 and Figure 5. Please note, that the switching levels of the input structures remain
constant even though they can accept amplitudes up to the IC supply level.
Final datasheet
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EiceDRIVER™ Compact
2EDL family
2EDL-family
ILIN
IHIN
HINx
LINx
Vcc V ; V
IH
IL
INPUT
NOISE
FILTER
VZ=5.25 V
Figure 4
3.2.3
Input pin structure
Input filter time
a)
b)
tFILIN
tFILIN
HIN
LIN
LIN
high
LO
Figure 5
HO
LO
low
Input filter timing diagram
Short pulses are suppressed by means of an input filter. The MOSFET version (2EDL23N06PJ) has an input
filter time of tFILIN = 100 ns typ. for high side and 150ns typ. for low side. The IGBT version (2EDL23I06PJ) has
filter times of 190ns typ.
3.3
VDD, GND and PGND (Low Side Supply)
VDD is the low side supply and it provides power to both the input logic and the low side output power stage.
The input logic is referenced to GND ground as well as the under-voltage detection circuit. Output power stage
is referenced to PGND ground. PGND ground is floating respect to GND ground with an absolute maximum
range of operation of +/-5.7 V. A back-to-back zener structure protects grounds from noise spikes.
The undervoltage lockout circuit enables the device to operate at power on when a typical supply voltage higher
than VDDUV+ is present. Please see section 3.6 “Undervoltage lockout”” for further information.
1
A filter time of typ. 1.5 µs helps to suppress noise from the UVLO circuit, so that negative going voltage spikes
at the supply pins will avoid parasitic UVLO events.
3.4
VB and VS (High Side Supplies)
VB to VS is the high side supply voltage. The high side circuit can float with respect to GND following the
external high side power device emitter/source voltage. Due to the low power consumption, the floating driver
stage can be supplied by bootstrap topology connected to VDD. A filter time of typ. 1.3 µs helps to suppress
noise from the UVLO circuit, so that negative going voltage spikes at the supply pins will avoid parasitic UVLO
events.
The under-voltage circuit enables the device to operate at power on when a typical supply voltage higher than
VDDUV+ is present. Please see section 3.6 “Undervoltage lockout” for further information. Details on bootstrap
supply section and transient immunity can be found in application note EiceDRIVER™ 2EDL family: Technical
description.
3.5
LO and HO (Low and High Side Outputs)
Low side and high side power outputs are specifically designed for pulse operation such as gate drive for IGBT
and MOSFET devices. Low side output is state triggered by the respective inputs, while high side output is edge
triggered by the respective inputs. In particular, after an undervoltage condition of the VBS supply, a new turnon signal (edge) is necessary to activate the high side output. In contrast, the low side outputs switch to the
state of their respective inputs after an undervoltage condition of the VDD supply.
The output current specification IO+ and IO- is defined in a way, which considers the power transistors miller
voltage.This helps to design the gate drive better in terms of the application needs. Nevertheless, the devices
are also characterised for the value of the pulse short circuit value IOpk+ and IOpk–.
Final datasheet
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2EDL family
3.6
Undervoltage lockout (UVLO)
Two different UVLO options are required for IGBT and MOSFET. The types 2EDL23I06PJ are designed to drive
IGBT. There are higher levels of undervoltage lockout for the low side UVLO than for the high side. This
supports an improved start up of the IC, when bootstrapping is used. The thresholds for the low side are
typically VDDUV+ = 12.5 V (positive going) and VDDUV– = 11.6 V (negative going). The thresholds for the high side
are typically VBSUV+ = 11.6 V (positive going) and VBSUV– = 10.7 V (negative going).
The types 2EDL23N06PJ are designed to drive power MOSFET. A similar distinction for the high side and low
side UVLO threshold as for IGBT is not realised here. The IC shuts down all the gate drivers power outputs,
when the supply voltage is below typ. VDDUV- = 8.3 V (min. / max. = 7.5 V / 9 V). The turn-on threshold is typ.
VDDUV+ = 9.1 V (min. / max. = 8.3 V / 9.9 V)
3.7
Bootstrap diode
An ultra fast bootstrap diode is monolithically integrated for establishing the high side supply. The differential
resistor of the diode helps to avoid extremely high inrush currents when charging the bootstrap capacitor
initially.
3.8
Deadtime and interlock function
The IC provides a hardware fixed deadtime. The deadtime is different for the MOSFET type (2EDL23N06PJ)
and for the IGBT type (2EDL23I06PJ). The deadtimes are particularly typ. 380 ns for IGBT and typ. 75 ns for
MOSFET. An additional interlock function prevents the two outputs from being activated simultaneously.
3.9
EN-/FLT (fault indication and enable function)
The types 2EDL23x06PJ provide a pin, which can either be used to shut down the IC or to read out a failure
status of the IC. The signal applied to pin EN controls directly the output stages. All outputs are set to LOW, if
EN is at LOW logic level. An integrated pull down resistor shuts down the IC in case of a floating input. The
internal structure of the pin is given in Figure 6. The switching levels of the Schmitt-Trigger are here VEN,TH+ =
2.1 V and VEN,TH- = 0.9 V. The typical propagation delay time is tEN = 550 ns. The input is clamped by diodes to
VDD and GND. The input voltage range is the same as the input control pins with a max. of 20 V.
The /FAULT function is an active low open-drain output indicating the status of the gate driver (see Figure 6).
The pin is active (i.e. forces LOW voltage level) when one of the following conditions occur:

Under-voltage condition of VDD supply: In this case the fault condition is released as soon as the
supply voltage condition returns in the normal operation range (please refer to VDD pin description for
more details). The fault signal is activate as long as UVLO is given during power up.

Overcurrent detection (ITRIP): The fault condition is latched until the overcurrent trigger condition is
finished and additional typ. 230 µs are elapsed.
The interface to the microcontroller can be realised by using an open collector / drain configured output pin for
enabling the driver IC and a GPIO pin for monitoring the /FAULT. The external pull-up resistor will pull-up the
voltage to +5V, when the IC is set for operation.
2EDL23x
+5V
To logic
µC
Rpu
EN
GPIO
Figure 6
EN/FLT
CFLT
Ron,FLT≈
35W
From
UVLO
OR
73kW
Latch
230µs
GND
From
ITRIPfilter
EN-/FLT pin structures and interface to microcontroller (µC)
Final datasheet
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2EDL family
3.10
Power ground / over current protection
A power ground (PGND) connects directly the emitter or source of the low side transistor with the gate drive IC.
No other components, such as shunts, etc., are between this connection and the emitter or source. This enables
the routing of smallest gate circuit loops and therefore smallest gate inductances.
A potential shunt resistor is between the power ground (PGND) connection and the gound connection (GND),
which leads to a voltage drop between these two pins.
The voltage drop between PGND and GND can be seen sensed by means of a comparator with a threshold of
Vth,ITRIP = 0.46 V. If the voltage drop is larger than Vth,ITRIP , then the output of the comparator is triggered and the
/FLT output is activated. Simultaneously, the IC shuts down both gate outputs for the period of the fault
indication, which is 230 µs.
Several influences, such as reverse recovery currents, parasitic inductances and other noise sources, make the
need of a signal filter necessary. The filter has a time constant of typically 1.8 µs to ensure good noise quality.
_________________________________
1
Not subject of production test, verified by characterisation
Final datasheet
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2EDL family
4
Electrical Parameters
4.1
Absolute Maximum Ratings
All voltages are absolute voltages referenced to VGND -potential unless otherwise specified. (Ta=25°C)
Table 3
Abs. maximum ratings
Parameter
Symbol
VS
High side offset voltage(Note 1)
Min.
Max.
Unit
VDD-VBS-6
600
V
VDD -VBS – 50 –
High side offset voltage (tp<500ns, Note 1)
High side offset voltage(Note 1)
VB
High side offset voltage (tp<500ns, Note 1)
VDD – 6
620
VDD – 50
–
High side floating supply voltage (VB vs. VS) (internally clamped)
VBS
-1
High side output voltage (VHO vs. VS)
VHO
-0.5
20
VB + 0.5
Low side supply voltage (internally clamped)
Low side supply voltage (VDD vs. VPGND)
VDD
-1
20
VDDPGND
-0.5
25
Gate driver ground
Low side output voltage (VLO vs. VPGND)
VPGND
-5.7
VLO
-0.5
5.7
VDDPGND + 0.5
Input voltage LIN,HIN,EN
VIN
-0.5
VDD + 0.5
FAULT output voltage
VFLT
VDD + 0.5
Power dissipation (to package) (Note 2)
PD
-0.5
–
0.9
W
Thermal resistance
(junction to ambient, see section 6)
Rth(j-a)
–
134
K/W
Junction temperature (Note 3)
TJ
–
150
°C
Storage temperature
TS
- 40
150
offset voltage slew rate (Note 4)
dVS/dt
–
50
V/ns
Note :The minimum value for ESD immunity is 1.0kV (Human Body Model). ESD immunity inside pins connected to the low side (VDD, HIN,
LIN, FAULT, EN, GND, PGND, LO) and pins connected inside each high side itself (VB, HO, VS) is guaranteed up to 1.5kV (Human Body
Model) respectively.
Note 1 : In case VDD > VB there is an additional power dissipation in the internal bootstrap diode between pins VDD and VB in case of
activated bootstrap diode. Insensitivity of bridge output to negative transient voltage up to –50V is not subject to production test – verified by
design / characterization.
Note 2: Consistent power dissipation of all outputs. All parameters are inside operating range.
Note 3: Qualification stress tests cover a max. junction temperature of 150°C for 1000 h.
Note 4: Not subject of production test, verified by characterisation.
Final datasheet
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2EDL family
4.2
Required operation conditions
All voltages are absolute voltages referenced to VGND -potential unless otherwise specified. (Ta = 25°C)
Table 4
Required Operation Conditions
Parameter
Min.
Max.
Unit
High side offset voltage (Note 1)
Symbol
VB
7
620
V
Low side supply voltage (VDD vs. VPGND)
VDDPGND
10
25
4.3
Operating Range
All voltages are absolute voltages referenced to VGND -potential unless otherwise specified. (Ta = 25°C)
Table 5
Operating range
Parameter
Symbol
VS
Min.
Max.
High side floating supply offset voltage (VB vs. VDD, statically)
VBDD
VDD VBS -1 500
-1.0
500
High side floating supply voltage (VB vs. VS, Note 1)
VBS
13
17.5
10
High side floating supply offset voltage
IGBT-Types
MOSFET-Types
High side output voltage (VHO vs. VS)
Low side output voltage (VLO vs. VPGND)
Low side supply voltage
IGBT-Types
VHO
10
17.5
VBS
VLO
0
VDD
VDD
13
17.5
10
17.5
MOSFET-Types
Unit
V
Low side ground voltage
VPGND
-2.5
2.5
Logic input voltages LIN,HIN,EN (Note 2)
VIN
0
FAULT output voltage
VFLT
0
17.5
VDD
tIN
0.8
–
0.3
–
-40
–
–
105
°C
4.8
3.3
K/W
Pulse width for ON or OFF (Note 3)
IGBT-Types
MOSFET-Types
Ambient temperature
Ta
Thermal resistance
(junction to ambient, see section 6)
DSO8
DSO14
th(j-top)
µs
Note 1 : Logic operational for VB (VB vs. VGND) > 7.0V
Note 2 : All input pins (HIN, LIN) and EN pin are internally clamped (see abs. maximum ratings)
Note 3 : The input pulse may not be transmitted properly in case of input pulse width at LIN and HIN below 0.8µs (IGBT types) or 0.3 µs
(MOSFET) respectively
Final datasheet
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2EDL family
4.4
Static logic function table
VDD
VBS
ENABLE
FAULT
PGND
LO
HO
<VDDUV–
X
X
0
X
0
0
15V
<VBSUV–
3.3 V
High imp.
< Vth,ITRIP
LIN
0
15V
15V
3.3 V
0
> Vth,ITRIP
0
0
15V
15V
0V
High imp.
X
0
0
15V
15V
3.3 V
High imp.
< Vth,ITRIP
LIN
HIN
All voltages with reference to GND
4.5
Static parameters
VDD = VBS = 15V unless otherwise specified. (Ta = 25°C) and VGND = VPGND unless otherwise specified
Table 6
Static parameters
Parameter
Symbol
Values
Unit Test condition
Min.
Typ.
Max.
High level input voltage
VIH
1.7
2.1
2.4
Low level input voltage
VIL
0.7
0.9
1.1
EN positive going threshold
VEN,TH+
1.7
2.1
2.4
EN negative going threshold
VEN,TH–
0.7
0.9
1.1
VDD -0.32 VDD -0.7
VB -0.32 VB -0.7
High level output voltage
High level output voltage
LO VOH
HO
LO VOL
–
–
HO
–
–
VPGND
+0.18
VS +0.18
VPGND 0.4
VS +0.4
11.8
12.5
13.2
8.3
9.1
9.9
10.9
11.6
12.4
8.3
9.1
9.9
10.9
11.6
12.4
7.5
8.3
9
10
10.7
11.7
VDD supply undervoltage
positive going threshold
IGBT-types
VBS supply undervoltage
positive going threshold
IGBT-types
VDD supply undervoltage
negative going threshold
IGBT-types
VBS supply undervoltage
negative going threshold
IGBT-types
MOSFET types
7.5
8.3
9
VDD and VBS supply UVLO
hysteresis
IGBT-types
VDDUVH
MOSFET types VBSUVH
Vth,ITRIP
ITRIP comparator threshold
0.5
0.9
–
0.5
0.9
–
0.4
0.46
0.53
ITRIP comparator hysteresis
0.045
0.07
–
–
1
12.5
–
10
–
VDDUV+
MOSFET types
VBSUV+
MOSFET types
VDDUV–
MOSFET types
VBSUV–
Vth,ITRIP
V
IO = - 100 mA
IO = 100 mA
VITRIP = VPGND - VGND
hys
High side leakage current betw. VS and
GND
High side leakage current betw. VS and
GND
1
ILVS+
ILVS+
1
µA
VS = 600V
TJ = 125 °C,
VS = 600 V
Not subject of production test, verified by characterisation
Final datasheet
16
<Revision 2.2>, 01.06.2016
EiceDRIVER™ Compact
2EDL family
Table 6
Static parameters
Parameter
Symbol
Values
Unit Test condition
Min.
Typ.
Max.
Quiescent current VBS supply (VB only)
IQBS1
–
180
300
HO = low
depending on
current types
Quiescent current VBS supply (VB only)
IQBS2
–
180
300
Quiescent current VDD supply (VDD only)
IQDD1
–
0.34
0.8
HO = high
depending on
current types
VLIN = float
Quiescent current VDD supply (VDD only)
IQDD2
–
0.32
0.8
VLIN = 3.3 V, VHIN=0
Quiescent current VDD supply (VDD only)
IQDD3
–
0.32
0.8
VLIN=0 , VHIN=3.3 V
Input bias current
ILIN+
15
35
60
Input bias current
ILIN–
–
0
–
VLIN = 0
Input bias current
IHIN+
15
35
60
VHIN = 3.3 V
Input bias current
IHIN–
–
0
–
VHIN = 0
Input bias current (EN=high)
IEN+
–
45
100
VENABLE = 3.3 V
Mean output current for load capacity
charging in range from 4.5 (30%) to 7.5V
(50%)
Peak output current turn on (single pulse)
IO+
1.3
1.8
–
A
CL = 61 nF
IOpk+1
–
2.3
–
A
RL = 0 W, tp <10 µs
Mean output current for load capacity
discharging in range from 7.5V (50%) to
4.5V (30%)
Peak output current turn off (single pulse)
IO–
1.65
2.5
–
A
CL = 61 nF
IOpk–1
–
2.8
–
A
RL = 0 W, tp <10 µs
Bootstrap diode forward voltage between
VDD and VB
Bootstrap diode forward current between
VDD and VB
VF,BSD
–
0.9
1.2
V
IF = 0.3 mA
IF,BSD
45
82
120
mA
VDD – VB = 4 V
Bootstrap diode resistance
RBSD
15
27
40
W
VF1 = 4 V, VF2 = 5 V
EN-/FLT low on resistance of the pull down
transistor
Ron,FLT
–
35
70
1
mA
µA
VLIN = 3.3 V
VEN-/FLT = 0.5 V
Not subject of production test, verified by characterisation
Final datasheet
17
<Revision 2.2>, 01.06.2016
EiceDRIVER™ Compact
2EDL family
4.6
Dynamic parameters
VDD = VBS = 15 V, VS = VGND = VPGND, CL = 180 pF unless otherwise specified. (TA=25°C)
Table 7
Dynamic parameters
Parameter
Symbol
ton
Turn-on propagation delay IGBT types
MOSFET types
toff
Turn-off propagation delay IGBT types
MOSFET types
Values
Min.
Typ.
Max.
280
210
420
310
610
460
260
400
590
200
300
440
Unit
Test condition
ns
VLIN/HIN = 0 or 3.3 V
Turn-on rise time
tr
–
48
80
Turn-off fall time
tf
–
37
60
Shutdown propagation delay ENABLE
tEN
–
550
850
VEN=0.5 V,
VLO / VHO = 20%
120
190
320
VLIN/HIN = 0 & 3.3 V
100
150
170
250
tFILIN
Input filter time at LIN/HIN IGBT types
for turn on and off
MOSFET types
HIN
LIN
VLIN/HIN = 0 or 3.3 V
CL = 4.9 nF
Input filter time EN
tFILEN
50
100
200
400
–
ITRIP filter time
tFILITRIP
1.0
1.8
2.7
1.1
2.2
3.0
VPGND = 1 V
VLO / VHO = 3V
VPGND = 1 V,
/FLT=0.5 V
VPGND = 0.1 V,
/FLT=2.1 V
VLIN/HIN = 0 & 3.3 V
Shut down propoagation delay PGND to any tITRIP
output
µs
VPGND = 1 V, /FLT=0
Propagation delay ITRIP to FAULT
tFLT
1.0
2.1
2.9
Fault-clear time
tFLTCLR
70
230
–
DT
260
380
540
30
75
140
MDT
Dead time matching
IGBT types
abs(DT_LH – DT_HL)
MOSFET types
for single IC
MTON
Matching delay ON, abs(ton_HS - ton_LS)
–
10
80
–
10
50
–
10
60
external dead time
> 500 ns
Matching delay OFF, abs(toff_HS-toff_LS)
–
10
60
external dead time
>500 ns
–
–
20
20
80
70
PW in > 1 µs
Dead time
IGBT types
MOSFET types
Output pulse width
matching. PW in-PW out
Final datasheet
MTOFF
PM
IGBT types
MOSFET types
18
ns
ext. dead time 0ns
<Revision 2.2>, 01.06.2016
EiceDRIVER™ Compact
2EDL family
Timing diagrams
5
tFILIN
HIN/LIN
tFILIN
tIN
tIN
HIN/LIN
tIN < tFILIN
tIN < tFILIN
high
HO/LO
HO/LO
low
tIN
HIN/LIN
tIN
HIN/LIN
tIN > tFILIN
tIN > tFILIN
HO/LO
HO/LO
Figure 7
Timing of short pulse suppression
LIN1,2,3
1.65V
1.65V
HIN1,2,3
12V
HO1,2,3
3V
DT
DT
12 V
LO1,2,3
3V
Figure 8
Timing of of internal deadtime
EN
tEN
HO1,2,3
LO1,2,3
Figure 9
3V
Enable delay time definition
Final datasheet
19
<Revision 2.2>, 01.06.2016
EiceDRIVER™ Compact
2EDL family
PWIN
LIN1,2,3
1.65V
1.65V
HIN1,2,3
ton
toff
tr
12V
tf
12V
HO1,2,3
LO1,2,3
3V
PWOUT
3V
Figure 10
Input to output propagation delay times and switching times definition
Figure 11
Operating areas (IGBT UVLO levels)
Figure 12
Operating areas (MOSFET UVLO levels)
Final datasheet
20
<Revision 2.2>, 01.06.2016
EiceDRIVER™ Compact
2EDL family
PGND
1V
0.1V
FAULT
2.1V
0.5V
tFLT
tFLTCLR
Any
output
Figure 13
3V
tITRIP
ITRIP-Timing
HIN/LIN
PWIN
PM = PWIN - PWOUT
PWOUT
HO/LO
HIN/LIN
PWIN
PM = PWIN - PWOUT
MToff
PWOUT
HO/LO
Figure 14
MTon
Output pulse width timing and matching delay timing diagram for positive logic
Final datasheet
21
<Revision 2.2>, 01.06.2016
EiceDRIVER™ Compact
2EDL family
6
Package
6.1
PG-DSO-14
Max. reflow solder temperature:
Max. wave solder temperature:
Figure 15 Package drawing
Figure 16
265°C acc. JEDEC
245°C acc. JEDEC
PCB reference layout (according to JEDEC 1s0P)
left: Reference layout
right: detail of footprint
The thermal coefficient is used to calculate the junction temperature, when the IC surface temperature is
measured. The junction temperature is
j = Ψth(j-top) ∙  + top
Table 8
Data of reference layout
Dimensions
Material
Metal (Copper)
76.2  114.3  1.5 mm³
FR4 (therm = 0.3 W/mK)
70µm (therm = 388 W/mK)
Final datasheet
22
<Revision 2.2>, 01.06.2016
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
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