A4402 Datasheet

A4402
Constant On-Time Buck Converter
With Integrated Linear Regulator
Features and Benefits
Description
▪2 MHz switching frequency
▪Adjustable soft start timer
▪Watchdog input
▪Power-on reset output
▪Adjustable buck and linear regulators
▪Enable input
▪6 to 50 V supply voltage range
▪Overcurrent protection
▪Undervoltage lockout (UVLO)
▪Thermal shutdown protection
Applications:
Automotive (“K” version)
• Power steering control units
•Transmission control units
•Lighting control units
•Infotainment
•Cluster
•Centerstack
•Other body control
The A4402 is a dual-output regulator, combining in a single
package a constant on-time buck regulator and a linear regulator
(LDO)—each with adjustable output voltages. It is ideal for
applications that require two regulated voltages, such as in
microcontroller- or DSP-based applications requiring core
and I/O voltage rails.
Commercial (“E” version)
•Photo and inkjet printers
•Industrial controls
•Distributed power systems
•Networking applications
•Point-of-sale
•Security systems
Package: 16-pin TSSOP with exposed
thermal pad (suffix LP)
The buck regulator output supplies the adjustable linear
regulator to reduce power dissipation and increase overall
efficiency. The switching regulator is capable of operating
above 2 MHz, allowing the use of small low value inductors
and capacitors while avoiding sensitive EMI frequency bands
such as AM radio in automotive applications.
Protection features include undervoltage lockout and thermal
shutdown. In case of a shorted load, each regulator features
overcurrent protection.
The device has an integrated power-on reset with adjustable
delay to monitor LDO output voltage and provide a signal that
can be used to reset a DSP or microcontroller. It also includes
a watchdog circuit.
The A4402 is provided in a 16-pin TSSOP, with exposed pad
for enhanced thermal dissipation. It is lead (Pb) free, with
100% matte tin leadframe plating.
Not to scale
Typical Application
VIN1
0.1 µF
TSET
BOOT
0.15 µF
0.01 µF
LX
CPOR
POR
A 4402
0.33 µF
RSENSE
GND
GND
VO2
4.7 µF
R1
31.6 kΩ
FB1
R2
9.76 kΩ
20 kΩ
NPOR
VO2
ENB
R3
10 kΩ
4.7 kΩ
GND
5
85
3.3
80
VOUT (V)
75
70
65
VIN2
WDI
90
Switching Regulator Output
VSW
5V
L1
33 µH
ISEN
Efficiency vs. Output Current
10 µF
Efficiency %
TON
CTSET
VBAT
Rton
750 kΩ
FB2
Linear Regulator Output
VLIN
3.3 V
250 mA
1 µF
60
0
200
400
800
IOUT (mA)
R4
5.62 kΩ
Data is for reference only. Efficiency data from circuit shown in left panel.
4402-DS, Rev. 11
600
1000 1200
Constant On-Time Buck Converter
With Integrated Linear Regulator
A4402
Selection Guide
Part Number
A4402ELPTR-T
A4402KLPTR-T
Ambient Operating
Temperature, TA
–40°C to 85°C
–40°C to 150°C
Packing
4000 pieces per 13-in. reel
Package
16-pin TSSOP with exposed thermal pad
Absolute Maximum Ratings
Characteristic
Symbol
Notes
Rating
Unit
VIN1 Pin
VIN1
–0.3 to 50
V
VIN2 Pin
VIN2
–0.3 to 7
V
LX Pin
VLX
–1 to 50
V
ISEN Pin
VISEN
–0.5 to 1
V
ENB Pin
VENB
–0.3 to 7
V
VO2 Pin
VO2
–0.3 to 7
V
WDI Pin
VWDI
–0.3 to 6
V
TON Pin
VTON
–0.3 to 7
V
FB1 and FB2 Pins
VFBx
–0.3 to 7
V
NPOR
VNPOR
–0.3 to 6.5
V
TSET Pin
VTSET
–0.3 to 7
V
POR Pin
VPOR
–0.3 to 6
V
BOOT Pin
VBOOT
VLX to VIN1+ 7
V
Range E
–40 to 85
°C
Range K
–40 to 150
°C
TJ(max)
150
°C
Tstg
–40 to 150
°C
Ambient Operating Temperature
Junction Temperature
Storage Temperature Range
TA
Thermal Characteristics
Characteristic
Package Thermal Resistance
Symbol
RθJA
Test Conditions*
On 4-layer PCB based on JEDEC standard
Value
Unit
34
ºC/W
*Additional thermal information available on the Allegro website.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
Constant On-Time Buck Converter
With Integrated Linear Regulator
A4402
VREF
CTSET
TSET
VIN1
Soft Start
Ramp Generator
0.15 µF
WDI
0.1 µF
Boot
Charge
10 µF
Watchdog Timer
CPOR
LX
POR
0.33 µF
4.7 µF
RSENSE
ENB
GND
R1
31.6 kΩ
GND
VO2
VFB2
FB1
Switch
Disable
20 kΩ
NPOR
VIN2
FAULT
R2
9.76 kΩ
VSW
TSD
VO2
ENB
VSW
5V
L1
33 µH
ISEN
Switch PWM
Control
VIN2
VIN1
1 µF
WDI
VREG
Internal
Regulator
4.7 kΩ
VBAT
Rton
750 kΩ
0.01 µF
BOOT
TON
Functional Block Diagram
VREF
VLIN
3.3 V
250 mA
R3
10 kΩ
VREG
VREF
FB2
R4
5.62 kΩ
Terminal List Table
Pin-out Diagram
TON 1
16 ENB
GND 2
15 VIN1
FB2 3
14 GND
VIN2 4
VO2 5
PAD
13 LX
12 BOOT
WDI 6
11 ISEN
TSET 7
10 POR
NPOR 8
9 FB1
Number
1
2
3
4
5
6
7
8
9
10
11
Name
TON
GND
FB2
VIN2
VO2
WDI
TSET
NPOR
FB1
POR
ISEN
12
13
14
15
16
–
BOOT
LX
GND
VIN1
ENB
PAD
Function
On time setting terminal
Ground
Feedback for VLIN
Input voltage 2
Regulator 2 output
Watchdog input
Soft start and watchdog timing capacitor terminal
Fault output
Feedback for VSW
POR delay
Current sense, limit setting for switching regulator, connect to GND
through series resistor
Boot node for LX
Switching regulator output
Ground
Input voltage 1
Enable input
Exposed thermal pad
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
Constant On-Time Buck Converter
With Integrated Linear Regulator
A4402
ELECTRICAL CHARACTERISTICS1 valid for Temperature Range E version at TJ = 25°C and for Temperature Range K
version at TJ = –40°C to 150°C, VIN1 = 6 to 50 V (unless otherwise noted)
Characteristics
Symbol
Supply Quiescent Current
IIN(Q)
ENB Logic Input Voltage
VENB
ENB Hysteresis
ENB Logic Input Current2
Test Conditions
Min.
Typ.
Max.
Unit
ENB = 5 V, IOUT = ISW+ILIN = 0 mA, 13.5 V < VIN1 < 50 V
1
–
6
mA
ENB = 0 V, 13.5 V< VIN1 < 18 V, IOUT = ISW+ ILIN = 0 mA
–
–
1
µA
2.0
2.28
2.56
V
VENB rising
VENBHYS
IENB
–
100
–
mV
High input level, VENB = 3 V
–
–
100
µA
Low input level, VENB < 0.4 V
–2
–
2
µA
1 mA < IO2 < 250 mA, 3.3 V < VIN2 < 5 V
1.156
1.180
1.204
V
VO2 rising based on FB voltage
0.896
0.944
0.990
V
mV
Linear Regulator
Feedback Voltage
VFB2
VO2 Undervoltage Lockout
Threshold
VO2UVLO
VO2 Undervoltage Lockout
Hysteresis
VO2UVHYS
30
50
70
Feedback Input Bias Current2
IFB2
–100
100
400
nA
Current Limit
IO2
250
–
350
mA
Switching Regulator
Feedback Voltage
VFB1
IOUT = ISW+ ILIN = 1 mA to 1.0 A, 8 V < VIN1 < 18 V
1.139
1.180
1.221
V
Feedback Input Bias Current
IFB1
VIN1 = 6 V
–400
–100
100
nA
VIN1 = 19.25 V, Rton = 750 kΩ
450
640
830
ns
Switcher On Time
ton
VIN1 = 13.5 V, Rton = 750 kΩ
165
230
300
ns
VIN1 = 8 V, Rton = 750 kΩ
1050
1480
1925
ns
V
ton Low Voltage Threshold
VPL
VIN1 rising
8.1
9
9.9
ton High Voltage Threshold
VPH
VIN1 rising
15.75
17.5
19.25
V
Changeover Hysteresis
VHYS
–
250
–
mV
Minimum On-time
tonmin
80
–
–
ns
Minimum Off-time
toffmin
130
–
–
ns
TJ = 25°C, ILOAD = 1 A
–
400
–
mΩ
TJ = 125°C, ILOAD = 1 A
–
650
–
mΩ
Buck Switch On-Resistance
ISEN Voltage
Valley Current Limit Threshold
RDS(on)
VISEN
Ilim
–150
–250
–350
mV
RSENSE = 0.27 Ω
–
740
–
mA
6 V < VIN1 < 8 V
–
–
550
mA
Protection Circuitry
NPOR Output Voltage
VNPOR
INPOR = 1 mA
–
–
400
mV
NPOR Leakage Current
INPOR
VNPOR = 5.5 V
–
–
1.5
µA
20 kΩ pullup connected to VOUT2
–
–
0.7
V
TJ rising
–
170
–
ºC
–
15
–
ºC
NPOR Reset
VNPORRESET
Thermal Shutdown Threshold
TJTSD
Thermal Shutdown Hysteresis
TJTSDHYS
Continued on the next page…
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
Constant On-Time Buck Converter
With Integrated Linear Regulator
A4402
ELECTRICAL CHARACTERISTICS1 (continued) valid for Temperature Range E version at TJ = 25°C and for Temperature
Range K version at TJ = –40°C to 150°C, VIN1 = 6 to 50 V (unless otherwise noted)
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
7
10
14
µA
Timing Circuitry
TSET Current, Watchdog Mode
ITSETWDI
NPOR = high
TSET Valley Voltage, Watchdog Mode
VTRIP
–
1.2
–
V
TSET Reset Voltage, Watchdog Mode
VRESET
–
0.48
–
V
WDI Frequency
fWDI
–
–
100
kHz
WDI Duty Cycle
DCWDI
10
–
90
%
WDI Logic Input
VWDI(0)
VIN2 ×
0.55
–
–
V
VWDI = 0 to 5 V
–20
< 1.0
20
µA
–
300
–
mV
NPOR = low
14
20
26
µA
3.92
5.60
7.28
µA
WDI Logic Input Current2
IWDI
WDI Input Hysteresis
VWDIHYS
TSET Current, Soft Start Mode
ITSETSS
POR Current
IPOR
1Temperature
Range E version tested at TJ = 25°C with performance from –40°C to 85°C guaranteed by design and characterization.
2For input and output current specifications, negative current is defined as coming out of (sourcing) the specified pin.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
Constant On-Time Buck Converter
With Integrated Linear Regulator
A4402
Power-Up and Power-Down Timing Diagrams
Using ENB
ENB
18 V
VIN1
6V
t ss
V SW
UVLO Rising
V O2
UVLO Rising
UVLO Falling
t por
NPOR
t por
Using VIN1
ENB
VIN1
t ss
t ss
V SW
V O2
NPOR
UVLO Rising
t por
UVLO Falling
UVLO Rising
t por
VPOR
VCTSET
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
Constant On-Time Buck Converter
With Integrated Linear Regulator
A4402
Watchdog Timing Diagram
ENB
t ss
V SW
VO2
NPOR
UVLO Rising
t por
t por
t wait
WDI
t wait
V trip
V TSET
V reset
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
Constant On-Time Buck Converter
With Integrated Linear Regulator
A4402
Functional Description
Under light load conditions, the switch enters pulse-skipping
mode to ensure regulation is maintained. This effectively changes
the switcher frequency. The frequency also is affected when the
switcher is operating in discontinuous mode. In order to maintain
a wide input voltage range, the switcher period is extended when
either the minimum off-time at low VIN1 , is reached or the minimum on-time at high VIN1 .
Switcher Overcurrent Protection The converter utilizes
pulse-by-pulse valley current limiting, which operates when the
current through the sense resistor rises to VISEN . During an overload condition, the switch is turned on for a period determined
by the constant on-time circuitry. The switch off-time is extended
until the current decays to the current limit value set by the
selection of the sense resistor, at which point the switch turns on
again. Because no slope compensation is required in this control
scheme, the current limit is maintained at a reasonably constant
level across the input voltage range.
Figure 1 illustrates how the current is limited during an overload
condition. The current decay (period with switch off) is proportional to the output voltage. As the overload is increased, the output voltage tends to decrease and the switching period increases.
VIN1 and VIN2 VIN1 is a high voltage input, designed to withstand 50 V. Bulk capacitance of at least 10 µF should be used to
decouple input supply VIN1. The VIN2 input is used to supply
the linear regulator and should be connected directly to the output
of the switching regulator when the target for the VSW voltage is
between 3 and 5.5 V. For voltages outside of that range, the bias
For applications where the switcher voltage is greater than 5 V, a
second supply between 3 and 5.5 V can be used to supply VIN2
bias current and the linear regulator. Note that the current into the
VIN2 supply must supply both the idd bias current and any current load on the linear regulator.
Output Voltage Selection The output voltage on each of the
two regulators is set by a voltage divider off the regulator output,
as follows:
 R1 + R2 
(1)

VSW = VFB1 
,

R2


 R3 + R4 

(2)
VLIN = VFB2 
.

R4


In order to maintain accuracy on the regulators the equivalent
impedance on the FB node (R1 parallel with R2) should be
approximately 10 kΩ.
Inductor current operating at maximum load
Current Limit level
Maximum load
Current
The device is enabled via the ENB input. When the ENB pin
is pulled high, the converter starts-up under the control of an
adjustable soft start routine whose ramp time is controlled by an
external capacitor.
supply for the IC is taken from VIN1 directly and affects overall
efficiency.
Constant On-Time
Constant period
Time
Inductor current operating in a “soft” overload
Overload
Current Limit level
Current
Basic Operation The A4402 contains a fixed on-time, adjustable voltage buck switching regulator with valley sensing current
mode control, and an adjustable linear regulator designed to run
off the buck regulator output. The constant on-time converter
maintains a constant output frequency because the on-time is
inversely proportional to the supply voltage. As the input voltage
decreases, the on-time is increased, maintaining a relatively constant period. Valley mode current control allows the converter to
achieve very short on-times because current is measured during
the off-time.
Constant On-Time
Extended period
Time
Figure 1. Current limiting during overload
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
Constant On-Time Buck Converter
With Integrated Linear Regulator
A4402
FB Both output regulators use a resistive feedback network to set
the output voltage. To prevent introducing noise into the FB network it is important to keep the total impedance of the FB nodes
low enough to prevent noise injection. For commercial applications it is recommended that the impedances on the FB nodes are
less than 50 kΩ. For automotive applications it is recommended
that the total impedance of the FB nodes is less than 25 kΩ.
up normally. Refer to timing diagrams for details.
TSET The TSET pin serves a dual function by controlling the
timing for both the soft start ramp and the WDI input. The current
sourced from the TSET pin is dependant on the state of NPOR.
TON A resistor from the TON input to VIN1 sets the on-time of
the converter for a given input voltage. The formula to calculate
the on-time, tON (ns), is:
There are two formulas for calculating the time constants. CTSET
must be selected so that both the WDI frequency and soft start
requirements are met. The formulas for calculating WDI and soft
start timing are:
(3)
tWDI = 7.2 × 9.6 × 104 × CTSET , and
(4)
tSS = 6.0 × 6.0 × 104 × CTSET ,
where CTSET is the value of the capacitor and the results,
tx, are in s.
Watchdog The WDI input is used to monitor the state of a DSP
or microcontroller. A constant current is driven into the capacitor
on TSET, causing the voltage on the TSET pin to ramp upward
until, at each rising edge on the WDI input, the ramp is pulled
down to VRESET. If no edge is seen on the WDI pin before the
ramp reaches VTRIP , the NPOR pin is pulled low.
The watchdog timer is not activated until the WDI input sees one
rising edge. If the watchdog timer is not going to be used, the
WDI pin should be pulled to ground with a 4.7 kΩ resistor.
Soft Start During soft start, an internal ramp generator and the
external capacitor on TSET are used to ramp the output voltage
in a controlled fashion. This reduces the demand on the external power supply by limiting the current that charges the output
capacitor and any DC load at startup. Either of the following
conditions are required to trigger a soft start:
• ENB pin input rising edge
• Reset of a TSD event
When a soft start event occurs, VO2 is held in the off state until
the soft start ramp timer expires. Then the regulator will power
BOOT A bootstrap capacitor is used to provide adequate charge
to the NMOS switch. The boot capacitor is referenced to LX
and supplies the gate drive with a voltage larger than the supply
voltage. The size of the capacitor must be 0.01 µF, X7R type, and
rated for at least 25 V.
R
tON = TON
VIN1
. –9
3.12 10–12 + 60 × 10
(5)
When the supply voltage is between 9 and 17.5 V, the switcher
period remains constant, at a level based on the selected value
of Rton . At voltages lower than 9 V and higher than 17.5 V, the
period is increased by a factor of 3.5.
If a constant period is desired over varying input voltages, it is
important to select an on-time that under worst case conditions
will not exceed the minimum off-time or minimum on-time of the
converter. For reasonable input voltage ranges, the period of the
converter can be held constant, resulting in a constant operating
frequency over the input supply range.
More information on how to choose Rton can be found in the
Application Information section.
ISEN The sense input is used to sense the current in the diode
during the off-time cycle. The value for RSENSE is obtained by the
formula:
RSENSE = VISEN / IVALLEY ,
(6)
where IVALLEY is the lowest current measured through the inductor during the off-time cycle.
It is recommended that the current sense resistor be sized so that,
at peak output current, the voltage on ISEN does not exceed
–0.5 V. Because the diode current is measured when the inductor
current is at the valley, the average output current is greater than
the IVALLEY value. The value for IVALLEY should be:
IVALLEY = IOUT(av) – 0.5 IRIPPLE + K ,
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
(7)
9
Constant On-Time Buck Converter
With Integrated Linear Regulator
A4402
where:
IOUT(av) is the average of both output currents,
following conditions:
IRIPPLE is the inductor ripple current, and
K is a guardband margin. The peak current in the switch is then:
IPEAK = IVALLEY + IRIPPLE .
(8)
The valley current must be calculated so that, at the worst-case
ripple, the converter can still supply the required current to the
load. Further information on how to calculate the ripple current is
included in the Application Information section.
ENB An active high input enables the device. When set low, the
device enters sleep mode; all internal circuitry is disabled, and the
part draws a maximum of 1 µA.
Thermal Shutdown When the device junction temperature, TJ ,
is sensed to be at TJTSD, a thermal shutdown circuit disables the
regulator output, protecting the A4402 from damage.
Power-on Reset Delay The POR function monitors the VFB2
voltage and provides a signal that can be used to reset a DSP or
microcontroller. A POR event is triggered by either of the
• VFB2 falls below its UVLO threshold. This occurs if the current
limit on either regulator is exceeded, or if the switcher voltage
falls due to TSD.
• After a rising edge on the WDI input, the voltage on TSET
reaches VTRIP.
An open drain output, through the NPOR pin, is provided to
signal a POR event to the DSP or microcontroller. The reset
occurs after an adjustable delay, tPOR, set by an external capacitor
connected to the POR pin. The value of tPOR is calculated using
the following formula:
tPOR = 214 × 103 × CPOR ,
(9)
where CPOR is the value of the POR capacitor in farads, and tPOR
is the POR time in seconds.
Shutdown The buck regulator will shutdown if one of the following conditions is present:
• TSD
• ENB falling edge
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
10
Constant On-Time Buck Converter
With Integrated Linear Regulator
A4402
Application Information
Switcher On-Time and Switching Frequency In order for
the switcher to maintain regulation, the energy that is transferred
to the inductor during the on-time must be transferred to the output capacitor during the off-time. This relationship must be maintained for stable operation and governs the fundamental operation
of a switching regulator. Each component along the current path
changes the voltage across the inductor and therefore the energy
that is transferred during each cycle. Summing the voltage from
VIN to VOUT during each cycle gives a relationship of the voltage
across the inductor during the on-time and during the off-time.
These terms are represented as VON and VOFF .
Given a target operating frequency, represent tON as:
tON = T × D(10)
where T equals 1 / fSW , and D is the duty cycle.
Duty cycle can be represented as the voltage across the inductor
during the off-time, divided by the total voltage of the off-time
and on-time:
D = VOFF / (VOFF + VON )
(11)
Next, determine the voltage drops during the on cycle and the
off cycle. Figure 2 shows the current path during the on‑time and
off‑time.
Creating voltage summation during each cycle will give equations to represent VON and VOFF :
VON = VIN – VOUT – (IOUT × RL ) – (RDS × IOUT )(12)
VOFF = VOUT + (IOUT × RL ) + Vf + (RS × IOUT )(13)
Now substituting VON and VOFF into equation 11 gives a complete formula for duty cycle as it relates to the voltage across the
inductor:
D=
VOUT × (IOUT× RL ) + Vf + ( RS× IOUT)
VOUT + (IOUT× RL ) + Vf + ( RS× IOUT) +
VIN – VOUT – (IOUT× RL ) – ( RDS+ IOUT)
(14)
The effects of the voltage drop across the inductor resistance and
trace resistance do have an effect on the switching frequency.
However, the frequency variation due to these factors is small
and is covered in the variation of the switcher period, TSW , which
is ±25% of the target. Removing these current-dependent terms
simplifies the equation:
D=
VOUT + Vf + ( RS× IOUT)
VOUT + Vf + ( RS× IOUT) +
VIN – VOUT – ( RDS× IOUT)
(15)
Further simplification and grouping of terms yields:
D=
VOUT + Vf + ( RS× IOUT)
VIN + Vf + ( RS× IOUT) – ( RDS× IOUT)
tON =
1
fSW
(16)
Substitute this simplified expression for duty cycle back into
equation 10. The following formula results in the on-time, given
a target switching frequency:
VOUT + Vf + ( RS× IOUT)
VIN + Vf + ( RS× IOUT) – ( RDS× IOUT)
(17)
The formulas above describe how tON changes based on input and
load conditions. Because load changes are minimal, and the output voltage is fixed, the dominant factor that effects on-time is the
input voltage. The converter is able to maintain a constant period
over a varying supply voltage because the on-time is proportional
to the input voltage. The current into the TON terminal is derived
from a resistor tied to VIN1, which sets the on-time proportional
to the supply voltage. Selecting the resistor value, based on the
tON calculated above, is done using the following formula:
RTON =
(tON – 60 × 10 –9 )× VIN
3.12 × 10 –12
(18)
After the resistor is selected and a suitable tON is found, it must
be demonstrated that tON does not, under worst-case conditions,
V RL Current path (on-cycle)
VIN1
L1
LX
Vf
A4402
V RS
V RL
Current path
(off-cycle)
RLOAD
Star Ground
Figure 2. Current limiting during overload
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11
Constant On-Time Buck Converter
With Integrated Linear Regulator
A4402
exceed the minimum on-time or minimum off-time of the converter. The minimum on-time occurs at maximum input voltage
and minimum load. The maximum off-time occurs at minimum
supply voltage and maximum load. For supply voltages below
9.5 V and above 17 V, refer to the Low and High Voltage Operation section.
Low and High Voltage Operation The converter can run at
very low input voltages. With a 5 V output, the minimum input
supply can be as low as 6 V. When operating at high frequencies,
the on-time of the converter must be very short because the available period is short. At high input voltages the converter must
maintain very short on-times, while at low input voltages the converter must maintain long off-times. Rather than limit the supply
voltage range, the converter solves this problem by automatically
increasing the period by a factor of 3.5. With the period extended,
the converter will not violate the minimum on-time or off-time.
If the input voltage is between 9.5 V and 17 V, the converter will
maintain a constant period. When calculating worst-case on-times
and off-times, make sure to use the multiplier if the supply voltage is between those values.
When operating at voltages below 8 V, additional care must be
taken when selecting the inductor and diode. At low voltages
the maximum current may be limited due to the IR drops in the
current path. When selecting external components for low voltage
operation, the IR drops must be considered when determining
on-time, so the complete formula should be used to make sure the
converter does not violate the timing specification.
Inductor Selection Choosing the right inductor is critical to
the correct operation of the switcher. The converter is capable of
running at frequencies above 2 MHz. This makes it possible to
use small inductor values, which reduces cost and board area.
The inductor value is what determines the ripple current. It is
important to size the inductor so that under worst-case conditions
IVALLEY equals IAV minus half the ripple current plus reasonable
margin. If the ripple current is too large, the converter will be
current limited. Typically peak-to-peak ripple current should be
limited to 20% to 25% of the maximum average load current.
Worst-case ripple current occurs at maximum supply voltage.
After calculating the duty cycle, DC, for this condition, the ripple
current can be calculated. First to calculate DC:
VSW+ Vf + (RSENSE× IPEAK )
DC =
VIN1(max) + Vf + (RSENSE× IPEAK )
.
(19)
Using the duty cycle, a ripple current can be calculated using the
following formula:
VIN1 – VOUT
IRIPPLE × DC ×
1
fSW(min)
(20)
,
where IRIPPLE is 25% of the maximum load current, and fSW(min)
is the minimum switching frequency (nominal frequency minus
25%). For the example used above, a 1 A converter with a supply
voltage of 13.5 V was the design objective. The supply voltage
can vary by ±10%. The output voltage is 5 V, Vf is 0.5 V, VSENSE
is 0.15, and the desired frequency is 2.0 MHz. The duty cycle
is calculated to be 36.45%. The worst-case frequency is 2 MHz
minus 20% or 1.6 MHz. Using these numbers in the above
formula shows that the minimum inductance for this converter is
9.6 µH.
L=
Output Capacitor The converter is designed to operate with
a low-value ceramic output capacitor. When choosing a ceramic
capacitor, make sure the rated voltage is at least 3 times the
maximum output voltage of the converter. This is because the
capacitance of a ceramic decreases as they operate closer to their
rated voltage. It is recommended that the output be decoupled
with a 10 µF, X7R ceramic capacitor. Larger capacitance may be
required on the outputs if load surges dramatically influence the
output voltage.
Output ripple is determined by the output capacitance and the
effects of ESR and ESL can be ignored assuming recommended
layout techniques are followed. The output voltage ripple is
approximated by:
IRIPPLE
(21)
.
4 × fSW × COUT
Input Capacitor The value of the input capacitance affects
the amount of current ripple on the input. This current ripple is
usually the source of supply side EMI. The amount of interference depends on the impedance from the input capacitor and
the bulk capacitance located on the supply bus. Adding a small
value, 0.1 µF , ceramic capacitor as close to the input supply pin
as possible can reduce EMI effects. The small capacitor will help
reduce high frequency transient currents on the supply line. If
further filtering is needed it, is recommended that two ceramic
capacitors be used in parallel to further reduce emissions.
VRIPPLE =
Rectification Diode The diode conducts the current during the
off-cycle. A Schottky diode is needed to minimize the forward
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12
Constant On-Time Buck Converter
With Integrated Linear Regulator
A4402
drop and switching losses. In order to size the diode correctly, it
is necessary to find the average diode conduction current using
the formula below:
(22)
ID(av) = ILOAD × (1 – DC(min)) ,
where DC (min) is defined as:
ance paths to each other. Figure 3 illustrates the technique.
The ground from each of the components should be very close to
each other and be connected on the same surface as the components. Internal ground planes should not be used for the star
ground connection, as vias add impedance to the current path.
(24)
PD(diode) = ILOAD(av) × DC(min) × Vf ,
The power dissipation in the sense resistor must also be considered using I2R and the minimum duty cycle.
In order to further reduce noise effects on the PCB, noise sensitive traces should not be connected to internal ground planes.
The feedback network from the switcher output should have an
independent ground trace that goes directly to the exposed pad
underneath the device. The exposed pad should be connected to
internal ground planes and to any exposed copper used for heat
dissipation. If the grounds from the device are also connected
directly to the exposed pad the ground reference from the feedback network will be less susceptible to noise injection or ground
bounce.
PCB Layout The board layout has a large impact on the performance of the device. It is important to isolate high current
ground returns, to minimize ground bounce that could produce
reference errors in the device. The method used to isolate power
ground from noise sensitive circuitry is to use a star ground. This
approach makes sure the high current components such as the
input capacitor, output capacitor, and diode have very low imped-
To reduce radiated emissions from the high frequency switching
nodes it is important to have an internal ground plane directly
under the LX node. The plane should not be broken directly
under the node as the lowest impedance path back to the star
ground would be directly under the signal trace. If another trace
does break the return path, the energy will have to find another
path, which is through radiated emissions.
VSW+Vf
VIN1+Vf
(23)
,
DC (min) =
where VIN1 is the maximum input voltage and Vf is the maximum
forward voltage of the diode.
Average power dissipation in the diode is:
Current path (on-cycle)
VIN1
L1
LX
A4402
RSENSE
Current path
(off-cycle)
RLOAD
Star Ground
Figure 3. Star Ground Connection
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13
Constant On-Time Buck Converter
With Integrated Linear Regulator
A4402
PCB Layout Diagram
VIN1
C5
GND
R5
R7
GND
GND
U1
VIN2
C1
R6
Star Ground
C8
C2
C7
C3
VLIN
R4
L1
C4
C6
VSW
R1
GND
R2
GND
D1
R3
VIN1
R5
C5
GND
R6
R7
VLIN
C6
R4
FB2
VIN2
C2
ENB
TON
A4402
PAD
C1
C8
VIN1
R1
GND
LX
VO2
BOOT
WDI
ISEN
TSET
POR
NPOR
FB1
A4402
C7
D1
R2
PCB
C4
Trace (2 oz.)
Signal (1 oz.)
L1
C3
Solder
Ground (1 oz.)
Thermal (2 oz.)
Thermal Vias
R3
VSW
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14
Constant On-Time Buck Converter
With Integrated Linear Regulator
A4402
Pin Circuit Diagrams
Power Terminals
Logic Terminals
VIN1
LX
TON
54 V
GND
GND
GND
VIN1
VIN2
FB1
FB2
WDI
TSET
NPOR
POR
ISEN
ENB
7V
GND
GND
VIN1
BOOT
54 V
10 V
10 V
GND
LX
VIN2
VO2
GND
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115 Northeast Cutoff
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15
Constant On-Time Buck Converter
With Integrated Linear Regulator
A4402
Package LP, 16-Pin TSSOP
with Exposed Thermal Pad
0.45
5.00 ±0.10
16
+0.05
0.15 –0.06
0.65
16
4° ±4
1.70
B
4.40 ±0.10
3.00
6.40 ±0.20
0.60 ±0.15
A
1
6.10
(1.00)
2
3.00
16X
0.25
SEATING
PLANE
0.10 C
+0.05
0.25 –0.06
3.00
0.65
1.20 MAX
0.15 MAX
C
1 2
SEATING PLANE
GAUGE PLANE
3.00
C
PCB Layout Reference View
All dimensions nominal, not for tooling use
(reference JEDEC MO-153 ABT)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B Exposed thermal pad (bottom surface)
C Reference land pattern layout (reference IPC7351 SOP65P640X110-17M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
16
Constant On-Time Buck Converter
With Integrated Linear Regulator
A4402
Revision History
Revision
Revision Date
Rev. 10
August TBD, 2013
Rev. 11
March 26, 2014
Description of Revision
Update TON description
Revised Functional Description and Pin Circuits
Copyright ©2008-2014, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
17
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