CCD Delay Line Series MN3883S Full Multi-PAL-Compatible CCD Video Signal Delay Element Overview The MN3883S is a CCD signal delay element for video signal processing applications. It contains such components as a shift register clock driver, charge I/O blocks, 1/2nd frequency doubler, two switchable CCD analog shift registers, a clamp bias circuit, resampling output amplifiers, a mode selection circuit and booster circuits. When the switch input is "H" level, the MN3883S samples the input using the supplied clock signal with a frequency 7.15909 MHz of twice the NTSC color signal subcarrier frequency, and after adding in the attached filter delay, produces independent delays of 1 H (the horizontal scan period for the NTSC system) each for the two lines. When the switch input is "M" level, the MN3883S samples the input using the supplied clock signal with a frequency 8.8672375 MHz of twice the PAL color signal subcarrier frequency, and after adding in the attached filter delay, produces independent delays of 1 H (the horizontal scan period for the NTSC system) each for the two lines. When the switch input is "L" level, the MN3883S samples the input using the supplied clock signal with a frequency 8.8672375 MHz of twice the PAL color signal subcarrier frequency, and after adding in the attached filter delay, produces independent delays of 1 H (the horizontal scan period for the PAL system) for the Y output and 2 H for the C output. Pin Assignment VBIASC 1 16 VINC VOC 2 15 N.C. N.C. 3 14 N.C. VDD 4 13 XI –VBB 5 12 VSS N.C. 6 11 SW VOY 7 10 N.C. VBIASY 8 9 VINY ( TOP VIEW ) SOP016-P-0225 Features Single 4.9 V power supply Single chip combining luminance signal delay element and delay element for color signal converted to low frequency Full Multi-PAL support, switchable between NTSC, 4.43 NTSC, and PAL systems Applications Full multi-PAL-compatible VCRs 1 MN3883S CCD Delay Line Series VBIASC 1 4 V DD 12 VSS Block Diagram Bias circuit VINC 16 P Charge input block 443N Charge input block N Charge input block CCD 8 stages + CCD + CCD 108 stages 451 stages Charge detection block Resampling VOC output amplifier 2 CCD 3.5 stages CCD 3 stages øS driver ø2 driver øR driver ø2 driver øR driver ø1 driver øSH driver øSH driver Timing adjustment N 443N XI P 13 Waveform amplifier adjustment block 1/2nd frequency doubler Timing adjustment øS driver ø1 driver øSH driver øSH driver Clamp circuit CCD + CCD + CCD 7.5 stages 108 stages 451 stages Charge detection block CCD 3.5 stages 8 Mode selection circuit 11 CCD 3 stages Three input levels: H: NTSC M: 4.43 NTSC L: PAL 2 7 Resampling VOY output amplifier VBIASY -VBB 5 VINY Charge input block 443N Charge 9 input block N Charge input block SW P CCD Delay Line Series MN3883S Application Circuit Example 10µF 0.1µF 1 VBIASC + 4 VDD 12 VSS – (0.01µF) Bias circuit VINC 16 (0.01µF) P Charge input block 443N Charge input block N Charge input block CCD 8 stages + CCD 108 stages 2 VOC CCD Charge detecResampling 451 stages tion block output amplifier + CCD 3.5 stages CCD 3 stages øS driver ø1 driver ø2 driver øR driver øSH driver øSH driver Timing adjustment N 443N P XI 13 Waveform amplifier 1000pF 1/2nd frequency doubler adjustment block Timing adjustment øS driver ø1 driver ø2 driver øR driver øSH driver øSH driver Clamp circuit CCD + CCD 7.5 stages 108 stages + CCD 451 stages Charge detection block 7 VOY Resampling output amplifier CCD 3.5 stages SW (0.01µF) Three input levels: H: NTSC M: 4.43 NTSC L: PAL 8 Mode selection circuit VBIASY CCD 3 stages -VBB 5 Charge input block 443N 9 VINY Charge input – + block 0.47µF N Charge input block 11 P (0.01µF) Note: When an electlytic capacitor is attached to pin 5, connect the negative pole to pin 5. 3 MN3883S CCD Delay Line Series Package Dimensions (Unit:mm) SOP016-P-0225 10.10±0.20 16 9 8 1.27 0.40±0.10 SEATING PLANE 4 0.10±0.10 (0.6) 1.60 -0.20 +0.50 +0.10 0.15 -0.05 0 to 10° 1.50±0.20 1 6.50±0.20 4.30±0.20 1.10±0.20 0.40min.