P3P623S05B D

P3P623S05A/B,
P3P623S09A/B
Timing-Safet Peak EMI
Reduction IC
Functional Description
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P3P623S05/09 is a versatile, 3.3 V Zero−delay buffer
designed to distribute Timing−Safe clocks with Peak EMI
reduction. P3P623S05 is an eight−pin version, accepts one
reference input and drives out five low−skew Timing−Safe
clocks. P3P623S09 accepts one reference input and drives
out nine low−skew Timing−Safe clocks.
All parts have on−chip PLL that locks to an input clock on
the CLKIN pin. The PLL feedback is on−chip and is
obtained from the CLKOUT pad, internal to the device.
Multiple P3P623S05 / P3P623S09 devices can accept the
same input clock and distribute it. In this case, the skew
between the outputs of the two devices is guaranteed to be
less than 700 pS.
All outputs have less than 200 pS of cycle−to−cycle jitter.
The input and output propagation delay is guaranteed to be
less than ±350 pS, and the output−to−output skew is
guaranteed to be less than 250 pS.
Refer “Spread Spectrum Control and Input−Output Skew
Table” for deviations and Input−Output Skew for
P3P623S05A/B and P3P623S09A/B devices.
P3P623S05/09 operates from a 3.3 V supply and is
available in TSSOP package, as shown in the ordering
information table.
TSSOP8 4.4x3
CASE 948AL
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
Spread Spectrum Frequency Generation
The clocks in digital systems are typically square waves
with a 50% duty cycle and as frequencies increase the edge
rates also get faster. Analysis shows that a square wave is
composed of fundamental frequency and harmonics. The
fundamental frequency and harmonics generate the energy
peaks that become the source of EMI. Regulatory agencies
test electronic equipment by measuring the amount of peak
energy radiated from the equipment. In fact, the peak level
allowed decreases as the frequency increases. The standard
methods of reducing EMI are to use shielding, filtering,
multi−layer PCBs, etc. These methods are expensive.
Spread spectrum clocking reduces the peak energy by
reducing the Q factor of the clock. This is done by slowly
modulating the clock frequency. The P3P623S05/09 uses
the center modulation spread spectrum technique in which
the modulated output frequency varies above and below the
reference frequency with a specified modulation rate. With
center modulation, the average frequency is the same as the
unmodulated frequency and there is no performance
degradation.
Application
P3P623S05/09 is targeted for use in Displays and memory
interface systems.
General Features
• Clock Distribution with Timing−Safe Peak EMI
•
•
•
•
•
•
Reduction
Input Frequency Range: 20 MHz − 50 MHz
Multiple Low Skew Timing−Safe Outputs:
♦ P3P623S05: 5 Outputs
♦ P3P623S09: 9 Outputs
Supply Voltage: 3.3 V ± 0.3 V
Packaging Information:
♦ P3P623S05: 8 Pin TSSOP
♦ P3P623S09: 16 Pin TSSOP
True Drop−in Solution for Zero Delay Buffer
These Devices are Pb−Free, Halogen Free/BFR Free
and are RoHS Compliant
© Semiconductor Components Industries, LLC, 2014
October, 2014 − Rev. 0
TSSOP16 4.4x5
CASE 948AN
Timing−Safe Technology
Timing−Safe technology is the ability to modulate a clock
source with Spread Spectrum technology and maintain
synchronization with any associated data path.
1
Publication Order Number:
P3P623S05B/D
P3P623S05A/B, P3P623S09A/B
BLOCK DIAGRAM
CLKOUT
PLL
PLL
MUX
CLKIN
CLK1
CLKOUT
CLKA1
CLKIN
CLKA2
CLK2
CLKA3
CLK3
CLKA4
P3P623S05A/B
CLK4
CLKB1
S2
Select Input
Decoding
S1
CLKB2
CLKB3
P3P623S09A/B
Figure 1. General Block Diagram
PIN CONFIGURATION
CLKIN
1
CLK1
2
8
CLKOUT
7
CLK4
P3P623S05A/B
CLK2
3
6
VDD
GND
4
5
CLK3
Figure 2. Pin Configuration for P3P623S05A/B
Table 1. PIN DESCRIPTION FOR P3P623S05A/B
Pin #
Pin Name
Type
Description
1
CLKIN (Note 1)
I
External reference Clock input, 5 V tolerant input.
2
CLK1 (Note 2)
O
Buffered clock output (Note 3)
3
CLK2 (Note 2)
O
Buffered clock output (Note 3)
4
GND
P
Ground
5
CLK3 (Note 2)
O
Buffered clock output (Note 3)
6
VDD
P
3.3 V supply
7
CLK4 (Note 2)
O
Buffered clock output (Note 3)
8
CLKOUT (Note 3)
O
Buffered clock output. Internal feedback on this pin.
1. Weak pull−down
2. Weak pull−down on all outputs
3. Buffered clock output is Timing−Safe
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2
CLKB4
P3P623S05A/B, P3P623S09A/B
CLKIN
1
16 CLKOUT
CLKA1
2
15 CLKA4
CLKA2
3
14 CLKA3
VDD
4
13 VDD
P3P623S09A/B
GND
5
12 GND
CLKB1
6
11 CLKB4
CLKB2
7
10 CLKB3
S2
8
9
S1
Figure 3. Pin Configuration for P3P623S09A/B
Table 2. PIN DESCRIPTION FOR P3P623S05A/B
1.
2.
3.
4.
Pin #
Pin Name
Type
1
CLKIN (Note 1)
I
External reference Clock input, 5 V tolerant input.
Description
2
CLKA1 (Note 2)
O
Buffered clock Bank A output (Note 4)
3
CLKA2 (Note 2)
O
Buffered clock Bank A output (Note 4)
4
VDD
P
3.3 V supply
5
GND
P
Ground
6
CLKB1 (Note 2)
O
Buffered clock Bank B output (Note 4)
7
CLKB2 (Note 2)
O
Buffered clock Bank B output (Note 4)
8
S2 (Note 3)
I
Select input, bit 2. See Select Input Decoding table for P3P623S09A/B for more details.
9
S1 (Note 3)
I
Select input, bit 1. See Select Input Decoding table for P3P623S09A/B for more details.
10
CLKB3 (Note 2)
O
Buffered clock Bank B output (Note 4)
11
CLKB4 (Note 2)
O
Buffered clock Bank B output (Note 4)
12
GND
P
Ground
13
VDD
P
3.3 V supply
14
CLKA3 (Note 2)
O
Buffered clock Bank A output (Note 4)
15
CLKA4 (Note 2)
O
Buffered clock Bank A output (Note 4)
16
CLKOUT (Note 2)
O
Buffered clock output. Internal feedback on this pin.
Weak pull−down
Weak pull−down on all outputs
Weak pull−up on these inputs
Buffered clock output is Timing−Safe
Table 3. SELECT INPUT DECODING TABLE FOR P3P623S09A/B
S2
S1
CLK A1 − A4
CLK B1 − B4
CLKOUT (Note 5)
Output Source
PLL Shut−Down
0
0
Three−state
Three−state
Driven
PLL
N
0
1
Driven
Three−state
Driven
PLL
N
1
0
Driven
Driven
Driven
Reference
Y
1
1
Driven
Driven
Driven
PLL
N
5. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the
reference and the Output.
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3
P3P623S05A/B, P3P623S09A/B
Table 4. SPREAD SPECTRUM CONTROL AND INPUT−OUTPUT SKEW TABLE
Frequency (MHz)
Device
Deviation
Input−Output Skew (+TSKEW)
32
P3P623S05A / 09A
±0.25%
0.125
P3P623S05B / 09B
±0.50%
0.25
NOTE: TSKEW is measured in units of the Clock Period
Table 5. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
VDD
Supply Voltage to Ground Potential
VIN
DC Input Voltage (CLKIN)
TSTG
Rating
Unit
−0.5 to +4.6
V
−0.5 to +7
Storage temperature
−65 to +125
°C
Ts
Max. Soldering Temperature (10 sec)
260
°C
TJ
Junction Temperature
150
°C
2
KV
TDV
Static Discharge Voltage (As per JEDEC STD22− A114−B)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Table 6. OPERATING CONDITIONS
Parameter
Min
Max
Unit
Supply Voltage
3.0
3.6
V
TA
Operating Temperature (Ambient Temperature)
−40
+85
°C
CL
Load Capacitance
30
pF
CIN
Input Capacitance
7
pF
VDD
Description
Table 7. ELECTRICAL CHARACTERISTICS
Parameter
Description
Test Conditions
Min
Typ
Max
Units
0.8
V
VIL
Input LOW Voltage (Note 1)
VIH
Input HIGH Voltage (Note 1)
IIL
Input LOW Current
VIN = 0 V
50
mA
IIH
2.0
V
Input HIGH Current
VIN = VDD
100
mA
VOL
Output LOW Voltage (Note 2)
IOL = 8 mA
0.4
V
VOH
Output HIGH Voltage (Note 2)
IOH = −8 mA
IDD
Supply Current
Unloaded outputs
ZO
Output Impedance
2.4
V
15
mA
23
W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. CLKIN input has a threshold voltage of VDD/2
2. Parameter is guaranteed by design and characterization. Not tested in production.
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4
P3P623S05A/B, P3P623S09A/B
Table 8. SWITCHING CHARACTERISTICS
Parameter
Description
Test Conditions
Min
Input Frequency
1/t1
Typ
Max
Units
20
50
MHz
50
MHz
60
%
Output Frequency
30 pF load
20
tD
Duty Cycle (Notes 3, 4) = (t2/t1) * 100
Measured at VDD/2
40
t3
Output Rise Time (Notes 3, 4)
Measured between 0.8 V and 2.0 V
2.5
nS
t4
Output Fall Time (Notes 3, 4)
Measured between 2.0 V and 0.8 V
2.5
nS
t5
Output−to−output skew (Notes 3, 4)
All outputs equally loaded
250
pS
t6
Delay, CLKIN Rising Edge to
CLKOUT Rising Edge (Note 4)
Measured at VDD/2
±350
pS
t7
Device−to−Device Skew (Note 4)
Measured at VDD/2 on the
CLKOUT pins of the device
700
pS
tJ
Cycle−to−cycle jitter (Notes 3, 4)
Loaded outputs
±200
pS
PLL Lock Time (Note 4)
Stable power supply, valid clock
presented on CLKIN pin
1.0
mS
tLOCK
3. All parameters specified with 30 pF loaded outputs.
4. Parameter is guaranteed by design and characterization. Not tested in production.
Switching Waveforms
t1
t2
VDD/2
VDD/2
VDD/2
OUTPUT
Figure 4. Duty Cycle Timing
2V
2V
0.8V
0.8V
OUTPUT
t3
t4
Figure 5. All Outputs Rise/Fall Time
VDD/2
OUTPUT
VDD/2
OUTPUT
t5
Figure 6. Output−Output Skew
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5
50
P3P623S05A/B, P3P623S09A/B
VDD/2
INPUT
VDD/2
OUTPUT
t6
Figure 7. Input−Output Propagation Delay
VDD/2
CLKOUT, Device 1
VDD/2
CLKOUT, Device 2
t7
Figure 8. Device−Device Skew
Input
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
TSKEW −
TSKEW+
Timing−Safet
Output
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
One clock cycle
N=1
+3.3 V
VDD
0.1 mF
OUTPUT
+3.3 V
CLK
LOAD
VDD
TSKEW represents input−output skew
GND
0.1 mF
when spread spectrum is ON
For example, TSKEW = ± 0.125 for an
Input clock12MHz, translates in to
(1/12MHz) * 0.125=10.41nS
Figure 9. Input−Output Skew
Figure 10. Test Circuit
Input
Input
Timing−Safet CLKOUT
CLKOUT with SSOFF
Figure 11. Typical Example of Timing−Safe Waveform
Table 9. ORDERING INFORMATION
Part Number
P3P623S05BG−08TR
Marking
ADQ
Package Type
8 pin, 4.4 mm TSSOP, Tape & Reel, Green
Temperature
0°C to +70°C
NOTE: A “microdot” placed at the end of last row of marking or just below the last row toward the center of package indicates Pb−free
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6
P3P623S05A/B, P3P623S09A/B
PACKAGE DIMENSIONS
TSSOP8, 4.4x3
CASE 948AL
ISSUE O
b
SYMBOL
MIN
NOM
A
E1
E
MAX
1.20
A1
0.05
0.15
A2
0.80
b
0.19
0.30
c
0.09
0.20
D
2.90
3.00
3.10
E
6.30
6.40
6.50
E1
4.30
4.40
4.50
0.90
e
0.65 BSC
L
1.00 REF
L1
0.50
θ
0º
0.60
1.05
0.75
8º
e
TOP VIEW
D
A2
c
q1
A
A1
L1
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
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7
L
P3P623S05A/B, P3P623S09A/B
PACKAGE DIMENSIONS
TSSOP16, 4.4x5
CASE 948AN
ISSUE O
b
SYMBOL
MIN
NOM
A
E1 E
MAX
1.10
A1
0.05
0.15
A2
0.85
0.95
b
0.19
0.30
c
0.13
0.20
D
4.90
5.10
E
6.30
6.50
E1
4.30
4.50
e
0.65 BSC
L
1.00 REF
L1
0.45
0.75
θ
0º
8º
e
PIN#1
IDENTIFICATION
TOP VIEW
D
A2
SIDE VIEW
A
c
θ1
A1
END VIEW
L1
L
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
TIMING SAFE is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
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expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
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P3P623S05B/D