Ordering number : EN8300A LC875832A LC875824A LC875816A CMOS IC ROM 32K/24K/16K byte, RAM 1024 byte on-chip 8-bit 1-chip Microcontroller Overview The SANYO LC875832A/24A/16A are 8-bit microcomputers that, centered around a CPU running at a minimum bus cycle time of 100ns, integrate on a single chip a number of hardware features such as 32K/24K/16K-byte ROM 1024-byte RAM, sophisticated 16-bit timers/counters (may be divided into 8-bit timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit PWMs), four 8-bit timers with a prescaler, a base timer serving as a time-of-day clock, a high-speed clock counter, a synchronous SIO interface (with automatic block transmission/reception capabilities), an asynchronous/synchronous SIO interface, a UART interface (full duplex), an 8-bit 11-channel AD converter, two 12-bit PWM channels, a system clock frequency divider, ROM correction function , and a 23-source 10-vector interrupt feature. Features ROM • 32768 × 8-bits (LC875832A) • 24576 × 8-bits (LC875824A) • 16384 × 8-bits (LC875816A) RAM • 1024 × 9 bits (LC875832A/24A/16A) Minimum Bus Cycle • 100ns (10MHz) VDD=3.0 to 3.6V • 125ns (8MHz) VDD=2.5 to 3.6V • 500ns (2MHz) VDD=2.2 to 3.6V Note: The bus cycle time here refers to the ROM read speed. Minimum Instruction Cycle Time • 300ns (10MHz) VDD=3.0 to 3.6V • 375ns (8MHz) VDD=2.5 to 3.6V • 1.5µs (2MHz) VDD=2.2 to 3.6V Any and all SANYO Semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO Semiconductor representative nearest you before usingany SANYO Semiconductor products described or contained herein in such applications. SANYO Semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor products described or contained herein. Ver.1.05 83006 / 42706HKIM No.8300-1/23 LC875832A/24A/16A Ports • Normal withstand voltage I/O ports Ports whose I/O direction can be designated in 1-bit units Ports whose I/O direction can be designated in 4-bit units • Normal withstand voltage input ports • Dedicated oscillator ports • Reset pins • Power pins 46 (P1n, P2n, P70 to P73, P80 to P86, PBn, PCn, PWM2, PWM3, XT2) 8 (P0n) 1 (XT1) 2 (CF1, CF2) 1 (RES) 6 (VSS1 to 3, VDD1 to 3) Timers • Timer 0 : 16-bit timer/counter with a capture register Mode 0 : 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) × 2 channels Mode 1 : 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter (with an 8-bit capture register) Mode 2 : 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register) Mode 3 : 16-bit counter (with a 16-bit capture register) • Timer 1 : 16-bit timer/counter that supports PWM/toggle outputs Mode 0 : 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/counter (with toggle outputs) Mode 1 : 8-bit PWM with an 8-bit prescaler × 2-channels Mode 2 : 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from the lower-order 8-bits) Mode 3 : 16-bit timer with an 8-bit prescaler (with toggle outputs) (the lower-order 8-bits can be used as PWM) • Timer 4 : 8-bit timer with a 6-bit prescaler • Timer 5 : 8-bit timer with a 6-bit prescaler • Timer 6 : 8-bit timer with a 6-bit prescaler (with toggle outputs) • Timer 7 : 8-bit timer with a 6-bit prescaler (with toggle outputs) • Base timer 1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler output. 2) Interrupts programmable in 5 different time schemes High-speed Clock Counter 1) Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz) 2) Can generate output real-time SIO • SIO0 : 8-bit synchronous serial interface 1) LSB first/MSB first mode selectable 2) Built-in 8-bit baudrate generator (maximum transfer clock cycle =4/3 tCYC) 3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1 bit units, suspension and resumption of data transmission possible in 1 byte units) • SIO1 : 8-bit asynchronous/synchronous serial interface Mode 0 : Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks) Mode 1 : Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates) Mode 2 : Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks) Mode 3 : Bus mode 2 (start detect, 8 data bits, stop detect) UART • Full duplex • 7/8/9 bit data bits selectable • 1 stop bit (2-bit in continuous data transmission) • Built-in baudrate generator No.8300-2/23 LC875832A/24A/16A AD Converter : 8-bits × 11-channels PWM : Multifrequency 12-bit PWM × 2-channels Remote Control Receiver Circuit (sharing pins with P73, INT3, and T0IN) • Noise rejection function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC) Watchdog Timer • External RC watchdog timer • Interrupt and reset signals selectable Clock Output Function 1) Able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock. 2) Able to output oscillation clock of sub clock. Interrupts • 23 sources, 10 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. Vector Address Level 1 00003H X or L INT0 Interrupt Source 2 0000BH X or L INT1 3 00013H H or L INT2/T0L/INT4 4 0001BH H or L INT3/INT5/base timer0/base timer1 5 00023H H or L T0H 6 0002BH H or L T1L/T1H 7 00033H H or L SIO0/UART1 receive 8 0003BH H or L SIO1/UART1 transmit 9 00043H H or L ADC/T6/T7 10 0004BH H or L Port 0/T4/T5/PWM2, PWM3 • Priority levels X > H > L • Of interrupts of the same level, the one with the smallest vector address takes precedence. Subroutine Stack Levels : 512 levels (the stack is allocated in RAM) High-speed Multiplication/Division Instructions • 16-bits × 8-bits (5 tCYC execution time) • 24-bits × 16-bits (12 tCYC execution time) • 16-bits ÷ 8-bits (8 tCYC execution time) • 24-bits ÷ 16-bits (12 tCYC execution time) Oscillation Circuits • RC oscillation circuit (internal) : • CF oscillation circuit : • Crystal oscillation circuit : For system clock For system clock, with internal Rf For low-speed system clock, with internal Rf System Clock Divider Function • Can run on low current. The minimum instruction cycle selectable from 300ns, 600ns, 1.2µs, 2.4µs, 4.8µs, 9.6µs, 19.2µs, 38.4µs, and 76.8µs (at a main clock rate of 10MHz). No.8300-3/23 LC875832A/24A/16A Standby Function • HALT mode : Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not halted automatically. 2) Canceled by a system reset or occurrence of an interrupt • HOLD mode : Suspends instruction execution and the operation of the peripheral circuits. 1) The CF, RC, and crystal oscillators automatically stop operation. 2) There are three ways of resetting the HOLD mode. (1) Setting the reset pin to the lower level (2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level (3) Having an interrupt source established at port 0 • X'tal HOLD mode : Suspends instruction execution and the operation of the peripheral circuits except the base timer. 1) The CF and RC oscillators automatically stop operation. 2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained. 3) There are four ways of resetting the X'tal HOLD mode. (1) Setting the reset pin to the low level (2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level (3) Having an interrupt source established at port 0 (4) Having an interrupt source established in the base timer circuit ROM Correction Function • Executes the correction program on detection of a match with the program counter value. • Correction program area size : 128 bytes Package Form • QIP64E (14 × 14): • TQFP64 (10 × 10): • TQFP64J (10 × 10): • TQFP64J (7 × 7): • VQFN64 (10 × 10): Development Tools • Evaluation chip : • Emulator : Lead-free type Lead-free type Lead-free type Lead-free type Lead-free type LC87EV690 EVA62S + ECB876600D + SUB875800 + POD64QFP or POD64SQFP (* Tools for VQFN64 (10 × 10), TQFP64J (7 × 7) version of PODs to be determined) No.8300-4/23 LC875832A/24A/16A Package Dimensions Package Dimensions unit : mm 3159A unit : mm 3296 12.0 33 10.0 48 33 32 64 17 10.0 17.2 14.0 64 49 12.0 32 49 17 1 1 16 0.35 0.8 16 0.2 0.5 0.15 (1.0) 0.15 (1.0) 0.1 0.1 3.0max 1.2max (2.7) (1.25) SANYO : TQFP64(10X10) SANYO : QIP64E(14X14) Package Dimensions Package Dimensions unit : mm 3310 unit : mm 3289 12.0 9.0 33 7.0 48 0.5 48 0.5 10.0 33 16 0.5 0.18 64 17 7.0 17 1 32 12.0 10.0 64 49 1 0.125 0.4 16 0.16 9.0 32 49 (1.25) 0.5 48 0.8 17.2 14.0 0.125 (1.0) 0.1 SANYO : TQFP64J(10X10) 1.2max (1.0) 0.1 1.2 MAX (0.5) SANYO : TQFP64J(7X7) No.8300-5/23 LC875832A/24A/16A Package Dimensions unit : mm 3323 TOP VIEW SIDE VIEW BOTTOM VIEW 10.2 10.0 0. 2 48 33 0.3 8.0 Typ 8.0 Typ 10.2 10.0 0.5 32 49 11 64 16 Do Not Connect 0.2 (0.8) 0.5 SIDE VIEW 0.85MAX 1 (1.25) Depth:0.03 MIN 0.5 0.3 SANYO : VQFN64(10X10) PB1 PB0 VSS3 VDD3 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 P86/AN6 P85/AN5 P84/AN4 P83/AN3 Pin Assignments 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P70/INT0/T0LCP/AN8 49 32 PB2 P71/INT1/T0HCP/AN9 50 31 PB3 P72/INT2/T0IN 51 30 PB4 P73/INT3/T0IN 52 29 PB5 RES 53 28 PB6 XT1/AN10 54 27 PB7 XT2/AN11 55 26 P27/INT5/T1IN VSS1 56 25 P26/INT5/T1IN CF1 57 24 P25/INT5/T1IN CF2 58 23 P24/INT5/T1IN VDD1 59 22 P23/INT4/T1IN P80/AN0 60 21 P22/INT4/T1IN P81/AN1 61 20 P21/URX/INT4/T1IN P82/AN2 62 19 P20/UTX/INT4/T1IN P10/SO0 63 18 P07/T7O P11/SI0/SB0 64 17 P06/T6O P16/T1PWML P17/T1PWMH/BUZ PWM2 PWM3 P04 P15/SCK1 9 10 11 12 13 14 15 16 P05/CKO 8 P03 7 P02 6 P01 5 P00 4 VSS2 3 VDD2 2 P13/SO1 P12/SCK0 1 P14/SI1/SB1 LC875832A/ LC875824A/ LC875816A Top view SANYO : QIP64E (14 × 14) “Lead-free Type” SANYO : TQFP64 (10 × 10) “Lead-free Type” SANYO : TQFP64J (10 × 10) “Lead-free Type” SANYO : TQFP64J (7 × 7) “Lead-free Type” No.8300-6/23 PB2 PB3 PB4 PB5 PB6 PB7 P27/INT5/T1IN P26/INT5/T1IN P25/INT5/T1IN P24/INT5/T1IN P23/INT4/T1IN P22/INT4/T1IN P21/URX/INT4/T1IN P20/UTX/INT4/T1IN P07/T7O P06/T6O LC875832A/24A/16A 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P05/CKO 49 32 PB1 P04 50 31 PB0 P03 51 30 VSS3 P02 52 29 VDD3 P01 53 28 PC7 P00 54 27 PC6 VSS2 55 26 PC5 25 PC4 24 PC3 VDD2 56 PWM3 57 LC875832A/ LC875824A/ LC875816A PWM2 58 23 PC2 P17/T1PWMH/BUZ 59 22 PC1 P16/T1PWML 60 21 PC0 17 P83/AN3 8 9 10 11 12 13 14 15 16 P70/INT0/T0LCP/AN8 7 P71/INT1/T0HCP/AN9 6 P72/INT2/T0IN 5 RES 4 P73/INT3/T0IN 3 XT1/AN10 2 XT2/AN11 1 VSS1 P84/AN4 CF1 18 64 CF2 63 VDD1 P13/SO1 P12/SCK0 P80/AN0 P85/AN5 P81/AN1 P86/AN6 19 P82/AN2 20 62 P10/SO0 61 P11/SI0/SB0 P15/SCK1 P14/SI1/SB1 Top view SANYO : VQFN64 (10 × 10) “Lead-free Type” No.8300-7/23 LC875832A/24A/16A System Block Diagram Interrupt control IR Standby control ROM correct CF ROM Clock generator RC PLA X’tal PC SIO0 Bus interface SIO1 Port 0 ACC Timer 0 Port 1 B register Timer 1 Port 2 C register Timer 4 Port 7 ALU Timer 5 Port 8 Timer 6 ADC PSW Timer 7 INT0 to INT5 Noise filter RAR Base timer Port B RAM PWM2/3 Port C Stack pointer UART Watchdog timer No.8300-8/23 LC875832A/24A/16A Pin Description Pin Name VSS1 I/O Description Option - -Power supply pin No - +Power supply pin No • 8-bit I/O port Yes VSS2 VSS3 VDD1 VDD2 VDD3 Port 0 I/O • I/O specifiable in 4-bit units P00 to P07 • Pull-up resistors can be turned on and off in 4-bit units. • HOLD reset input • Port 0 interrupt input • Shared pins P05 : System clock output (system clock / can selected from sub clock) P06 : Timer 6 toggle output P07 : Timer 7 toggle output Port 1 I/O • 8-bit I/O port Yes • I/O specifiable in 1-bit units P10 to P17 • Pull-up resistors can be turned on and off in 1-bit units. • Pin functions P10 : SIO0 data output P11 : SIO0 data input/bus I/O P12 : SIO0 clock I/O P13 : SIO1 data output P14 : SIO1 data input/bus I/O P15 : SIO1 clock I/O P16 : Timer 1PWML output P17 : Timer 1PWMH output/beeper output Port 2 P20 to P27 I/O • 8-bit I/O port Yes • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1-bit units. • Pin functions P20 : UART transmit P21 : UART receive P20 to P23 : INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/ timer 0H capture input P24 to P27 : INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/ timer 0H capture input Interrupt acknowledge type Rising Falling INT4 enable enable INT5 enable enable Rising & H level L level enable disable disable enable disable disable Falling Continued on next page. No.8300-9/23 LC875832A/24A/16A Continued from preceding page. Pin Name Port 7 I/O I/O Description Option • 4-bit I/O port No • I/O specifiable in 1-bit units P70 to P73 • Pull-up resistors can be turned on and off in 1-bit units. • Shared pins AD converter input port : AN8 (P70), AN9 (P71) P70 : INT0 input/HOLD reset input/timer 0L capture input/watchdog timer output P71 : INT1 input/HOLD reset input/timer 0H capture input P72 : INT2 input/HOLD reset input/timer 0 event input/timer 0L capture input/ High speed clock counter input P73 : INT3 input (with noise filter)/timer 0 event input/timer 0H capture input Interrupt acknowledge type Port 8 I/O Rising Falling INT0 enable enable INT1 enable enable INT2 enable INT3 enable Rising & H level L level disable enable enable disable enable enable enable enable disable disable enable enable disable disable Falling • 7-bit I/O port No • I/O specifiable in 1-bit units P80 to P86 • Shared pins AD converter input : port : AN0 (P80) to AN6 (P86) PWM2, I/O PWM3 Port B • PWM2 and PWM3 output ports No • General-purpose I/O available I/O • 8-bit I/O port Yes • I/O specifiable in 1-bit units PB0 to PB7 • Pull-up resistors can be turned on and off in 1-bit units. Port C I/O • 8-bit I/O port Yes • I/O specifiable in 1-bit units PC0 to PC7 • Pull-up resistors can be turned on and off in 1-bit units. RES Input Reset pin No XT1 Input • 32.768kHz crystal oscillator input pin No • Shared pins General-purpose input port AD converter input port : AN10 Must be connected to VDD1 if not to be used. XT2 I/O • 32.768kHz crystal oscillator output pin No • Shared pins General-purpose I/O port AD converter input port : AN11 Must be set for oscillation and kept open if not to be used. CF1 Input CF2 Output Ceramic resonator input pin No Ceramic resonator output pin No No.8300-10/23 LC875832A/24A/16A Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode. Port Name Option Selected in Units of P00 to P07 1-bit P10 to P17 1-bit P20 to P27 1-bit Option Type 1 Output Type Pull-up Resistor CMOS Programmable (Note 1) 2 Nch-open drain No 1 CMOS Programmable 2 Nch-open drain Programmable 1 CMOS Programmable 2 Nch-open drain Programmable P70 - No Nch-open drain Programmable P71 to P73 - No CMOS Programmable P80 to P86 - No Nch-open drain No PWM2, PWM3 - No CMOS No PB0 to PB7 1-bit 1 CMOS Programmable 2 Nch-open drain Programmable PC0 to PC7 1-bit 1 CMOS Programmable 2 Nch-open drain Programmable XT1 - No Input only No XT2 - No Output for 32.768kHz crystal oscillator No (Nch-open drain when in general-purpose output mode) Note 1 : Programmable pull-up resistors for port 0 are controlled in 4-bit units (P00 to 03, P04 to 07). *1 : Connect the IC as shown below to minimize the noise input to the VDD1 pin. Be sure to electrically short the VSS1, VSS2, and VSS3 pins. LSI VDD1 Power supply For backup *2 VDD2 VDD3 VSS1 VSS2 VSS3 *2 : The internal memory is sustained by VDD1. If none of VDD2 and VDD3 are backed up, the high level output at the ports are unstable in the HOLD backup mode, allowing through current to flow into the input buffer and thus shortening the backup time. Make sure that the port outputs are held at the low level in the HOLD backup mode. No.8300-11/23 LC875832A/24A/16A Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = VSS3 = 0V Parameter Symbol Pin/Remarks Specification Conditions VDD [V] Maximum supply VDD max VDD1, VDD2, VDD3 Input voltage VI(1) XT1, CF1 Input/output VIO(1) Ports 0, 1, 2 VDD1=VDD2=VDD3 voltage voltage min typ max unit -0.3 +4.6 -0.3 VDD+0.3 V Ports 7, 8 -0.3 Ports B, C VDD+0.3 PWM2, PWM3, XT2 High level output current Peak output Ports 0, 1, 2, 7 CMOS output select current Ports B, C Per 1 applicable pin (Note 1-1) PWM2, PWM3 Total output ΣIOAH(1) Port 7 Total of all applicable pins current ΣIOAH(2) Port 1 Total of all applicable pins PWM2, PWM3 Peak output Low level output current IOPH(1) -4 -10 -25 ΣIOAH(3) Ports 0, 2 Total of all applicable pins ΣIOAH(4) Port B Total of all applicable pins -25 ΣIOAH(5) Port C Total of all applicable pins -25 IOPL(1) P02 to P07 Per 1 applicable pin current Ports 1, 2, 7, 8 (Note 1-1) Ports B, C -25 6 mA PWM2, PWM3, XT2 Total output IOPL(2) P00, P01 Per 1 applicable pin ΣIOAL(1) Port 7 Total of all applicable pins current Power dissipation Operating ambient 10 P83 to P86, XT2 ΣIOAL(2) P80 to P82 Total of all applicable pins ΣIOAL(3) Port 1 Total of all applicable pins 10 25 PWM2, PWM3 ΣIOAL(4) Ports 0, 2 Total of all applicable pins 25 ΣIOAL(5) Port B Total of all applicable pins 25 ΣIOAL(6) Port C Total of all applicable pins 25 Pd max QIP64E (14×14) Ta= -30 to +70°C 414 TQFP64 (10×10) 236 TQFP64J (10×10) 270 TQFP64J (7×7) 188 VQFN64 (10×10) 209 Topr temperature Storage ambient 15 Tstg temperature -30 +70 -55 +125 mW °C Note 1-1 : The average current per applicable pin must not exceed 1mA. No.8300-12/23 LC875832A/24A/16A Allowable Operating Range at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter Symbol Pin/Remarks Specification Conditions VDD [V] Operating VDD(1) VDD1=VDD2=VDD3 supply voltage Memory VHD VDD1=VDD2=VDD3 sustaining min typ max unit 0.294µs ≤ tCYC ≤ 200µs 3.0 3.6 0.367µs ≤ tCYC ≤ 200µs 2.5 3.6 1.47µs ≤ tCYC ≤ 200µs 2.2 3.6 2.0 3.6 RAM and register contents sustained in HOLD mode. supply voltage High level input VIH(1) voltage Ports 1, 2 P71 to P73 2.2 to 3.6 P70 port input 0.3VDD VDD +0.7 /interrupt side VIH(2) Ports 0, 8, B, C 2.2 to 3.6 PWM2, PWM3 VIH(3) Port 70 watchdog timer side VIH(4) Low level input VIL(1) voltage XT1, XT2, CF1, RES 0.3VDD +0.7 VDD 2.2 to 3.6 0.9VDD VDD 2.2 to 3.6 0.75VDD VDD 2.2 to 3.6 VSS 0.2VDD 2.2 to 3.6 VSS 0.2VDD 2.2 to 3.6 VSS 2.2 to 3.6 VSS 0.25VDD 3.0 to 3.6 0.294 200 2.5 to 3.6 0.367 200 2.2 to 3.6 1.47 200 3.0 to 3.6 0.1 10 2.5 to 3.6 0.1 8 V Ports 1, 2 P71 to P73 P70 port input /interrupt side VIL(2) Ports 0, 8, B, C PWM2, PWM3 VIL(3) Port 70 watchdog timer side VIL(4) Instruction cycle XT1, XT2, CF1, RES tCYC time (Note 2-1) External system FEXCF(1) CF1 clock frequency • CF2 pin open 0.8VDD -1.0 µs • System clock frequency division ratio=1/1 • External system clock duty 2.2 to 3.6 0.1 2 • CF2 pin open 3.0 to 3.6 0.2 20 • System clock frequency 2.5 to 3.6 0.2 16 2.2 to 3.6 0.2 4 =50 ± 5% division ratio=1/2 Oscillation FmCF(1) CF1, CF2 frequency range (Note 2-2) 10MHz ceramic oscillation mode See Fig. 1. FmCF(2) CF1, CF2 8MHz ceramic oscillation mode See Fig. 1. FmCF(3) CF1, CF2 4MHz ceramic oscillation mode See Fig. 1. FmRC FsX’tal Internal RC oscillation XT1, XT2 3.0 to 3.6 10 2.5 to 3.6 8 2.2 to 3.6 4 2.2 to 3.6 0.3 1.0 MHz 2.0 32.768kHz crystal oscillation mode 2.2 to 3.6 32.768 kHz See Fig. 2. Note 2-1 : Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2. Note 2-2 : See Tables 1 and 2 for the oscillation constants. No.8300-13/23 LC875832A/24A/16A Electrical Characteristics at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter Symbol Pin/Remarks Specification Conditions VDD [V] High level input IIH(1) current Ports 0, 1, 2 Output disabled Ports 7, 8 Pull-up resistor off Ports B, C VIN=VDD (Including output Tr's off leakage RES IIH(2) PWM2, PWM3 current) XT1, XT2 For input port specification VIN=VDD Low level input IIH(3) CF1 VIN=VDD IIL(1) Ports 0, 1, 2 Output disabled Ports 7, 8 Pull-up resistor off Ports B, C VIN=VSS (Including output Tr's off leakage current RES IIL(2) PWM2, PWM3 current) XT1, XT2 For input port specification VIN=VSS High level output voltage 1 2.2 to 3.6 8 2.2 to 3.6 -1 2.2 to 3.6 -1 VIN=VSS 2.2 to 3.6 -8 IOH= -0.4mA 3.0 to 3.6 VDD-0.4 IOH= -0.2mA 2.2 to 3.6 VDD-0.4 IOH= -1.6mA 3.0 to 3.6 VDD-0.4 IOH= -0.8mA 2.2 to 3.6 VDD-0.4 VOH(2) VOL(1) PWM2, PWM3 PWM2, PWM3 Ports 0, 1, 2, 7, 8 IOL=1.6mA Ports B, C VOL(2) PWM2, PWM3 IOL=0.8mA XT2 VOL(3) P00, P01 VOL(4) Rpu Ports 0, 1, 2, 7 VHYS 2.2 to 3.6 0.4 3.0 to 3.6 0.4 2.2 to 3.6 0.4 VOH=0.9VDD RES All pins 0.4 IOL=2.5mA 2.2 to 3.6 2.2 to 3.6 Ports 1, 2, 7 CP 3.0 to 3.6 IOL=5mA Ports B, C Pin capacitance 2.2 to 3.6 CF1 voltage Hysteresis voltage 1 Ports 0, 1, 2, 7 Ports B, C max 2.2 to 3.6 VOH(1) VOH(3) Pull-up resistance typ IIL(3) VOH(4) Low level output min 25 50 200 0.1 unit µA V kΩ V For pins other than that under test : VIN=VSS 2.2 to 3.6 10 pF f=1MHz Ta=25°C No.8300-14/23 LC875832A/24A/16A Serial Input/Output Characteristics at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V 1. SIO0 Serial I/O Characteristics (Note 4-1-1) Parameter Symbol Pin/Remarks Specification Conditions Input clock VDD [V] Frequency tSCK(1) Low level tSCKL(1) SCK0(P12) See Fig. 6. tSCKH(1) 2.2 to 3.6 pulse width tSCKHA(1) tCYC 4 • (Note 4-1-2) Frequency tSCK(2) SCK0(P12) • CMOS output selected 4/3 • See Fig. 6. Output clock Low level tSCKL(2) 1/2 pulse width High level tSCK tSCKH(2) 2.2 to 3.6 pulse width tSCKHA(2) 1/2 • Continuous data tSCKH(2) transmission/reception mode +2tCYC • CMOS output selected • See Fig. 6. Data setup time Serial input unit 1 • Continuous data transmission/reception mode tsDI(1) SB0(P11), SI0(P11) tSCKH(2) +(10/3) tCYC tCYC • Must be specified with respect to rising edge of SIOCLK. 2.2 to 3.6 0.03 2.2 to 3.6 0.03 • See Fig. 6. Data hold time Output clock Input clock Output delay Serial output max 1 • See Fig. 6. Serial clock typ 2 pulse width High level min thDI(1) tdD0(1) time SO0(P10), SB0(P11) • Continuous data transmission/reception mode 2.2 to 3.6 • (Note 4-1-3) tdD0(2) • Synchronous 8-bit mode • (Note 4-1-3) tdD0(3) 2.2 to 3.6 (1/3)tCYC +0.05 µs 1tCYC +0.05 (Note 4-1-3) 2.2 to 3.6 (1/3)tCYC +0.15 Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: To use serial-clock-input in continuous trans / rec mode, a time from SI0RUN being set when serial clock is "H" to the first negative edge of the serial clock must be longer than tSCKHA. Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig. 6. No.8300-15/23 LC875832A/24A/16A 2. SIO1 Serial I/O Characteristics (Note 4-2-1) Parameter Symbol Pin/Remarks Specification Conditions Input clock Frequency tSCK(3) Low level tSCKL(3) SCK1(P15) See Fig. 6. 2.2 to 3.6 pulse width High level Frequency SCK1(P15) • CMOS output selected tSCKL(4) 2 1/2 tSCK tSCKH(4) 1/2 pulse width Serial input Data setup time SB1(P14), SI1(P14) • Must be specified with respect to rising edge of SIOCLK. 2.2 to 3.6 0.03 2.2 to 3.6 0.03 • See Fig. 6. Data hold time Output delay time Serial output tsDI(2) unit 1 2.2 to 3.6 pulse width High level max 1 • See Fig. 6. Low level typ tCYC tSCKH(3) tSCK(4) min 2 pulse width Output clock Serial clock VDD [V] thDI(2) tdD0(4) SO1(P13), SB1(P14) µs • Must be specified with respect to falling edge of SIOCLK. • Must be specified as the time to the beginning of 2.2 to 3.6 output state change in (1/3)tCYC +0.05 open drain output mode. • See Fig. 6. Note 4-2-1: These specifications are theoretical values. Add margin depending on its use. No.8300-16/23 LC875832A/24A/16A Pulse Input Conditions at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter Symbol Pin/Remarks Specification Conditions VDD [V] High/low level tPIH(1) INT0(P70), • Interrupt source flag can be set. pulse width tPIL(1) INT1(P71), • Event inputs for timer 0 or 1 are INT2(P72), enabled. min typ 2.2 to 3.6 1 2.2 to 3.6 2 2.2 to 3.6 64 2.2 to 3.6 256 2.2 to 3.6 200 max unit INT4(P20 to P23), INT5(P24 to P27) tPIH(2) INT3(P73) when • Interrupt source flag can be set. tPIL(2) noise filter time • Event inputs for timer 0 are constant is 1/1 tPIH(3) INT3(P73) when • Interrupt source flag can be set. tPIL(3) noise filter time • Event inputs for timer 0 are constant is 1/32 enabled. tPIH(4) INT3(P73) when • Interrupt source flag can be set. tPIL(4) noise filter time • Event inputs for timer 0 are constant is 1/128 tPIL(5) RES tCYC enabled. enabled. Resetting is enabled. µs AD Converter Characteristics at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter Symbol Pin/Remarks Specification Conditions VDD [V] Resolution N AN0(P80) to Absolute ET AN6(P86) (Note 6-1) accuracy AN8(P70) Conversion AN9(P71) AD conversion time=32 × tCYC AN10(XT1) (when ADCR2=0) (Note 6-2) TCAD time typ 3.0 to 3.6 AD conversion time=64 × tCYC (when ADCR2=1) (Note 6-2) VAIN 3.0 to 3.6 3.0 to 3.6 voltage range Analog port IAINH VAIN=VDD 3.0 to 3.6 input current IAINL VAIN=VSS 3.0 to 3.6 max unit 8 bit ±1.5 3.0 to 3.6 AN11(XT2) Analog input min 3.0 to 3.6 31.36 97.92 (tCYC= (tCYC= 0.980µs) 3.06µs) 31.36 97.92 (tCYC= (tCYC= 0.490µs) 1.53µs) VSS VDD 1 -1 LSB µs V µA Note 6-1 : The quantization error (±1/2LSB) is excluded from the absolute accuracy value. Note 6-2 : The conversion time refers to the interval from the time the instruction for starting the converter is issued till the time the complete digital value corresponding to the analog input value is loaded in the required register. No.8300-17/23 LC875832A/24A/16A Consumption Current Characteristics at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter Normal mode Symbol IDDOP(1) Pin/ VDD [V] VDD1 • FmCF=10MHz ceramic oscillation mode consumption =VDD2 • FmX’tal=32.768kHz crystal oscillation mode current =VDD3 • System clock set to 10MHz side (Note 7-1) Specification Conditions Remarks min typ max 3.0 to 3.6 3.7 8.3 3.0 to 3.6 4.0 9.2 3.0 to 3.6 2.9 6.8 unit • Internal RC oscillation stopped • 1/1 frequency division ratio IDDOP(2) • CF1=20MHz external clock • FmX’tal=32.768kHz crystal oscillation mode • System clock set to CF1 side • Internal RC oscillation stopped • 1/2 frequency division ratio IDDOP(3) • FmCF=8MHz ceramic oscillation mode • FmX’tal=32.768kHz crystal oscillation mode mA • System clock set to 8MHz side IDDOP(4) • Internal RC oscillation stopped 2.5 to 3.0 2.3 5.3 3.0 to 3.6 0.95 2.3 2.2 to 3.0 0.66 1.8 3.0 to 3.6 0.29 1.3 2.2 to 3.0 0.2 0.96 3.0 to 3.6 11 38 2.2 to 3.0 7.7 28 3.0 to 3.6 1.2 2.9 3.0 to 3.6 1.7 3.9 3.0 to 3.6 1.0 2.5 • 1/1 frequency division ratio IDDOP(5) • FmCF=4MHz ceramic oscillation mode • FmX’tal=32.768kHz crystal oscillation mode • System clock set to 4MHz side IDDOP(6) • Internal RC oscillation stopped • 1/2 frequency division ratio IDDOP(7) • FmCF=0Hz (oscillation stopped) • FmX’tal=32.768kHz crystal oscillation mode IDDOP(8) • System clock set to internal RC oscillation • 1/2 frequency division ratio IDDOP(9) • FmCF=0Hz (oscillation stopped) • FmX’tal=32.768kHz crystal oscillation mode IDDOP(10) µA • System clock set to 32.768kHz side • Internal RC oscillation stopped • 1/2 frequency division ratio HALT mode IDDHALT(1) HALT mode consumption • FmCF=10MHz ceramic oscillation mode current • FmX’tal=32.768kHz crystal oscillation mode (Note 7-1) • System clock set to 10MHz side • Internal RC oscillation stopped • 1/1 frequency division ratio IDDHALT(2) • CF1=20MHz external clock • FmX’tal=32.768kHz crystal oscillation mode • System clock set to CF1 side • Internal RC oscillation stopped • 1/2 frequency division ratio IDDHALT(3) • HALT mode • FmCF=8MHz ceramic oscillation mode • FmX’tal=32.768kHz crystal oscillation mode IDDHALT(4) mA • System clock set to 8MHz side • Internal RC oscillation stopped 2.5 to 3.0 0.77 1.9 3.0 to 3.6 0.48 1.2 2.2 to 3.0 0.3 0.88 3.0 to 3.6 0.17 0.73 2.2 to 3.0 0.12 0.56 • 1/1 frequency division ratio IDDHALT(5) • HALT mode • FmCF=4MHz ceramic oscillation mode • FmX’tal=32.768kHz crystal oscillation mode IDDHALT(6) • System clock set to 4MHz side • Internal RC oscillation stopped • 1/2 frequency division ratio IDDHALT(7) • HALT mode • FmCF=0Hz (oscillation stopped) IDDHALT(8) • FmX’tal=32.768kHz crystal oscillation mode • System clock set to internal RC oscillation • 1/2 frequency division ratio Note 7-1 : The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. Continued on next page. No.8300-18/23 LC875832A/24A/16A Continued from preceding page. Parameter Symbol Pin/remarks Specification Conditions VDD [V] HALT mode IDDHALT(9) VDD1 • HALT mode consumption =VDD2 • FmCF=0Hz (oscillation stopped) current =VDD3 • FmX’tal=32.768kHz crystal (Note 7-1) min typ max unit 3.0 to 3.6 7.6 26 2.2 to 3.0 4.7 18 3.0 to 3.6 0.04 8 2.2 to 3.0 0.03 6 3.0 to 3.6 6.3 22 2.2 to 3.0 3.8 15 oscillation mode IDDHALT(10) • System clock set to 32.768kHz side • Internal RC oscillation stopped • 1/2 frequency division ratio HOLD mode IDDHOLD(1) consumption HOLD mode VDD1 IDDHOLD(2) current Timer HOLD µA • CF1=VDD or open (external clock mode) IDDHOLD(3) Timer HOLD mode mode • CF1=VDD or open consumption (external clock mode) IDDHOLD(4) current • FmX’tal=32.768kHz crystal oscillation mode Note 7-1 : The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. UART (Full Duplex) Operating Conditions at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter Symbol Pin/remarks Specification Conditions VDD [V] Transfer rate UBR UTX (P20), 2.2 to 3.6 URX (P21) Data length : Stop bits : Parity bits : min typ max 16/3 unit 8192/3 tCYC 7, 8, and 9 bits (LSB first) 1-bit (2-bit in continuous data transmission) None Example of Continuous 8-bit Data Transmission Mode Processing (first transmit data=55H) Start bit Start of transmission Stop bit Transmit data (LSB first) End of transmission UBR Example of Continuous 8-bit Data Reception Mode Processing (first receive data=55H) Stop bit Start bit Start of reception Receive data (LSB first) End of reception UBR No.8300-19/23 LC875832A/24A/16A Characteristics of a Sample Main System Clock Oscillation Circuit Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator Vendor Name Frequency 10MHz 8MHz 4MHz Oscillator Name Oscillation Stabilization Operating Circuit Constant Nominal Time Voltage C1 C2 Rd1 Range [pF] [pF] [Ω] [V] typ Remarks max [ms] [ms] MURATA CSTCE10M0G52-R0 (10) (10) 470 3.0 to 3.6 0.05 0.25 Internal C1, C2 KYOCERA PBRC10.00HR (10) (10) 0 3.0 to 3.6 0.06 0.3 Internal C1, C2 MURATA CSTCE8M00G52-R0 (10) (10) 1k 2.5 to 3.6 0.05 0.25 Internal C1, C2 KYOCERA PBRC8.00HR (30) (30) 0 2.5 to 3.6 0.07 0.35 Internal C1, C2 MURATA CSTCR4M00G53-R0 (15) (15) 2.2k 2.2 to 3.6 0.05 0.25 Internal C1, C2 KYOCERA PBRC4.00HR (30) (30) 0 2.2 to 3.6 0.08 0.4 Internal C1, C2 The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD goes above the operating voltage lower limit (see Figure 4). Characteristics of a Sample Subsystem Clock Oscillator Circuit Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYOdesignated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator Circuit Constant Nominal Vendor Name Frequency Oscillator Name Operating Voltage C3 C4 Rf Rd2 [pF] [pF] [Ω] [Ω] 15 15 10M 510k Range [V] Oscillation Stabilization Time typ max [s] [s] 1.0 3.0 Remarks Applicable 32.768kHz SEIKO EPSON MC-306 2.2 to 3.6 CL value =12.5pF The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the oscillation to get stabilized after the HOLD mode is reset (see Figure 4). Note : The components that are involved in oscillation should be placed as close to the IC and to one another as possible because they are vulnerable to the influences of the circuit pattern. CF1 CF2 XT1 Rd1 XT2 Rf Rd2 C1 CF C2 C3 C4 X’tal Figure 1 CF Oscillator Circuit Figure 2 XT Oscillator Circuit 0.5VDD Figure 3 AC Timing Measurement Point No.8300-20/23 LC875832A/24A/16A VDD Operating VDD lower limit 0V Power supply Reset time RES Internal RC oscillation tmsCF CF1, CF2 tmsX’tal XT1, XT2 Operating mode Reset Unpredictable Instruction execution Reset Time and Oscillation Stabilization Time HOLD reset signal HOLD reset signal absent HOLD reset signal valid Internal RC oscillation tmsCF CF1, CF2 tmsX’tal XT1, XT2 State HOLD HALT HOLD Reset Signal and Oscillation Stabilization Time Figure 4 Oscillation Stabilization Times No.8300-21/23 LC875832A/24A/16A VDD RRES Note : Determine the value of CRES and RRES so that the reset signal is present for a period of 200µs after the supply voltage goes beyond the lower limit of the IC’s operating voltage. RES CRES Figure 5 Reset Circuit SIOCLK : DATAIN : DI0 DI1 DI2 DI3 DI4 DI5 DI6 DATAOUT : DO0 DO1 DO2 DO3 DO4 DO5 DO6 DI7 DI8 DO7 DO8 Data RAM transfer period (SIO0 only) tSCK tSCKH tSCKL SIOCLK : tsDI thDI DATAIN : tdDO DATAOUT : Data RAM transfer period (SIO0 only) tSCKL tSCKHA SIOCLK : tsDI thDI DATAIN : tdDO DATAOUT : Figure 6 Serial I/O Output Waveforms tPIL tPIH Figure 7 Pulse Input Timing Signal Waveform No.8300-22/23 LC875832A/24A/16A Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor products (including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. 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Specifications and information herein are subject to change without notice. PS No.8300-23/23