AP0100CS D

‡
AP0100CS HDR: Image Signal Processor (ISP)
Features
AP0100CS High-Dynamic Range (HDR) Image
Signal Processor (ISP)
AP0100CS Datasheet, Rev. 6
For the latest product datasheet, please visit www.onsemi.com
Features
Table 1:
• Up to 1.2Mp (1280x960) ON Semiconductor sensor
support
• 45 fps at 1.2Mp, 60 fps at 720p
• Optimized for operation with HDR sensors.
• Color and gamma correction
• Auto exposure, auto white balance, 50/60 Hz auto
flicker detection and avoidance
• Adaptive Local Tone Mapping (ALTM)
• Programmable Spatial Transform Engine (STE).
• Pre-rendered Graphical Overlay
• Two-wire serial programming interface (CCIS)
• Interface to low-cost Flash or EEPROM through SPI
bus (to configure and load patches, etc.)
• High-level host command interface
• Standalone operation supported
• Up to 5 GPIO
• Fail-safe IO
• Multi-Camera synchronization support
• Integrated video encoder for NTSC/PAL with overlay
capability and 10-bit I-DAC
Key Performance Parameters
Parameter
Value
Primary camera
interfaces
Parallel and HiSPi
Primary camera input
RAW12 Linear/RAW12, RAW14 (HiSPi
format only) Companded
Output interface
Analog composite, up to 16-bit
parallel digital output
Output format
YUV422 8-bit,10-bit, and 10-, 12-bit
tone-mapped Bayer
Maximum resolution
1280x960 (1.2 Mp)
NTSC output
720H x 487V
PAL output
720H x 576V
Input clock range
6-30 MHz
Supply voltage
VDDIO_S
1.8 or 2.8 V nominal
VDDIO_H
2.5 or 3.3 V nominal
VDD_REG
1.8 V nominal
VDD
1.2 V nominal
VDD_PLL
1.2 V nominal
VDD_DAC
1.2V nominal
Applications
VDDIO_OTPM
2.5 or 3.3 V nominal
• IP cam and CCTV - HD
• Enables CCTV -HD w/ MP sensor
VDDA_DAC
3.3 V nominal
VDD_PHY
2.8 V nominal
Operating temp.
–30°C to +70°C
Power consumption
185 mW
Notes: 1.
AP0100CS/D Rev. 6, 1/16 EN
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©Semiconductor Components Industries, LLC 2016,
AP0100CS HDR: Image Signal Processor (ISP)
Ordering Information
Ordering Information
Table 2:
Available Part Numbers
Part Number
Product Description
Orderable Product Attribute Description
AP0100CS2L00SUGA0-DR1
1Mp Co-Processor, 100-ball VFBGA
Drypack
AP0100CS2L00SPGAD3-GEVK
AP0100CS Demo Kit
AP0100CS2L00SPGAH-GEVB
AP0100CS Head Board
See the ON Semiconductor Device Nomenclature document (TND310/D) for a full
description of the naming convention used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com.
AP0100CS/D Rev. 6, 1/16 EN
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©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
Table of Contents
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Functional Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
System Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
On-Chip Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Multi-Camera Synchronization Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Image Flow Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Test Patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Camera Control and Auto Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Flicker Avoidance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Flicker Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Output Formatting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Bayer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Spatial Transform Engine (STE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Overlay Capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Serial Memory Partition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Overlay Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Slave Two-Wire Serial Interface (CCIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Host Command Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Start-up Host Command Lock-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Multitasking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Host Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Summary of Host Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Usage Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Two-Wire Serial Register Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Package Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
AP0100CS/D Rev. 6, Pub. 1/16 EN
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©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
General Description
General Description
The ON Semiconductor AP0100CS is a high-performance, ultra-low power in-line,
digital image processor optimized for use with HDR (High Dynamic Range) sensors. The
AP0100CS provides full auto-functions support (AWB and AE) and ALTM (Adaptive Local
Tone Mapping) to enhance HDR images and advanced noise reduction which enables
excellent low-light performance.
Functional Overview
Figure 1 shows the typical configuration of the AP0100CS in a camera system. On the
host side, a two-wire serial interface is used to control the operation of the AP0100CS,
and image data is transferred using the analog or parallel interface between the
AP0100CS and the host. The AP0100CS interface to the sensor also uses a parallel interface.
Figure 1:
AP0100CS Connectivity
1.2Mp HDR Sensor
or
12-bit parallel
Two-lane HiSPi
Analog
NTSC/PAL display
Two-wire serial I/F (CCIM)
Two-wire serial IF (CCIS)
Host
System Interfaces
Figure 2: “Typical Parallel Configuration,” on page 5 and Figure 3: “Typical HiSPi Configuration,” on page 6 show typical AP0100CS device connections.
All power supply rails must be decoupled from ground using capacitors as close as
possible to the package.
The AP0100CS signals to the sensor and host interfaces can be at different supply voltage
levels to optimize power consumption and maximize flexibility. Table 1 on page 9
provides the signal descriptions for the AP0100CS.
AP0100CS/D Rev. 6, Pub. 1/16 EN
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©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
System Interfaces
OTPM
power
Host IO
power
V DDIO _H
V DD_PHY
V DDA_DAC
V DD_DAC
M_S CLK
V DD
EXT_REG
V DD_REG
ENLDO
V DDIO _S
V DD_PLL
Sensor IO
power
DAC
analog
power
1 . 2 V ( R egulator OP)
P ower up C ore, P LL.
and DAC digital
LDO_OP
1.8V
( R egulator
IP)
V DDIO_OTPM
Typical Parallel Configuration
FB_SENSE
Figure 2:
M_S DATA
S CLK
S DATA
S ADDR
EXTCLK
EXTCLK_OUT
XTAL
RESET_BAR_OUT
SPI_CS_BAR
SPI_CLK
SPI_SDO
SPI_SDI
FV _IN
LV_IN
PIXCLK _IN
DIN [11:0]
FV_OUT
LV_OUT
PIXCLK_OUT
D OUT[15:0]
DAC_POS
DAC_NEG
DAC_REF
FRAME_SYNC
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
TRIGGER_OUT
G ND_REG
VDDIO_S6 VDD_REG4
Notes:
AP0100CS/D Rev. 6, Pub. 1/16 EN
G ND
LDO_OP4
VDDIO_OTPM
TRST_BAR5
VDDIO_H
VDDIO_DAC
1. This typical configuration shows only one scenario out of multiple possible variations for this
device.
2. ON Semiconductor recommends a 1.5kresistor value for the two-wire serial interface RPULL-UP;
however, greater values may be used for slower transmission speed.
3. RESET_BAR has an internal pull-up resistor and can be left floating if not used.
4. The decoupling capacitors for the regulator input and output should have a value of 1.0uF. The
capacitors should be ceramic and need to have X5R or X7R dielectric.
5. TRST_BAR connects to GND for normal operation.
6. ON Semiconductor recommends that 0.1F and 1F decoupling capacitors for each power supply
are mounted as close as possible to the pin. Actual values and numbers may vary depending on layout and design consideration
5
©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
System Interfaces
Typical HiSPi Configuration
V DDIO_OTPM
M_S DATA
V DD_PHY
V DDA_DAC
HiSPi
DAC
analog voltage
OTPM
power
power
V DD_DAC
V DD
EXT_REG
V DD_PLL
M_S CLK
LDO_OP
V DDIO _S
1 . 2 V ( R egulator OP)
P ower up C ore, P LL.
and DAC digital
FB_SENSE
Sensor IO
power
1.8V
( R egulator
IP)
V DD_REG
ENLDO
Figure 3:
Host IO
power
V DDIO _H
S CLK
S DATA
S ADDR
EXTCLK
EXTCLK_OUT
Sensor IO
power
XTAL
RESET_BAR_OUT
SPI_CS_BAR
SPI_CLK
SPI_SDO
SPI_SDI
FV _IN
LV_IN
PIXCLK _IN
DIN [11:0]
FV_OUT
LV_OUT
PIXCLK_OUT
D OUT[15:0]
DAC_POS
DAC_NEG
DAC_REF
FRAME_SYNC
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
TRIGGER_OUT
CLK_N CLK_P
DATA0_N DATA0_P
DATA1_N DATA1_P
G ND_REG
VDDIO_S6 VDD_REG4
LDO_OP4
G ND
VDDIO_OTPM
VDDIO_H
TRST_BAR5
VDDIO_DAC
VDDIO_PHY
HiSPi and Parallel Connection
When using the HiSPi interface, the user should connect the parallel interface to
VDDIO_S.
When using the parallel interface, the HiSPi interface and power supply (VDD_PHY) can
be left floating.
AP0100CS/D Rev. 6, Pub. 1/16 EN
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©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
System Interfaces
Crystal Usage
As an alternative to using an external oscillator, a crystal may be connected between
EXTCLK and XTAL. Two small loading capacitors and a feedback resistor should be
added, as shown in Figure 4.
Figure 4:
Using a Crystal Instead of an External Oscillator
AP0100CS
C1
EXTCLK
Rf=1MΩ
XTAL
C2
Rf represents the feedback resistor, an Rf value of 1M is sufficient for AP0100CS. C1 and
C2 are decided according to the crystal or resonator CL specification. In the steady state
of oscillation, CL is defined as (C1 x C2)/(C1+C2). In fact, the I/O ports, the bond pad,
package pin and PCB traces all contribute the parasitic capacitance to C1 and C2. Therefore, CL can be rewritten to be (C1* x C2*)/(C1*+C2*), where C1*=(C1+Cin, stray) and
C2*=(C2+Cout, stray). The stray capacitance for the IO ports, bond pad and package pin
are known which means the formulas can be rewritten as C1*=(C1+1.5pF+Cin, PCB) and
C2*=(C2+1.3pF+Cout, PCB).
Table 3:
Pin Descriptions
Name
Type
Description
EXTCLK
Input
Master input clock. This can either be a square-wave generated from an
oscillator (in which case the XTAL input must be left unconnected) or direct
connection to a crystal.
XTAL
Output
If EXTCLK is connected to one pin of a crystal, the other pin of the crystal is
connected to XTAL pin; otherwise this signal must be left unconnected.
RESET_BAR
Input/PU
SCLK
Input
Two-wire serial interface clock (host interface).
Two-wire serial interface data (host interface).
Master reset signal, active LOW. This signal has an internal pull up.
SDATA
I/O
SADDR
Input
Selects device address for the two-wire slave serial interface. When connected
to GND the device ID is 0x90. When wired to VDDIO_H, a device ID of 0xBA is
selected.
FRAME_SYNC
Input
This signal is used to synchronize to external sources or multiple cameras
together. This signal should be connected to GND if not used.
STANDBY
Input
Standby mode control, active HIGH.
EXT_REG
Input
Select external regulator if tied high
AP0100CS/D Rev. 6, Pub. 1/16 EN
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©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
System Interfaces
Table 3:
Pin Descriptions (Continued)
Name
Type
Description
ENDLO
Input
Regulator enable (VDD_REG domain)
SPI_SCLK
Output
SPI_SDI
Input/PU
Clock output for interfacing to an external SPI flash or EEPROM memory.
Data in from SPI flash or EEPROM memory. When no SPI device is fitted, this
signal is used to determine whether the AP0100CS should auto-configure: 0:
Do not auto-configure; Two-wire interface will be used to configure the
device (host-config mode) 1: Auto-configure. This signal has an internal pullup resistor.
SPI_SDO
Output
Data out to SPI flash or EEPROM memory.
SPI_CS_BAR
Output
Chip select out to SPI flash or EEPROM memory.
EXT_CLK_OUT
Output
Clock to external sensor.
RESET_BAR_OUT
Output
Reset signal to external signal.
M_SCLK
Output
Two-wire serial interface clock (Master).
M_SDATA
I/O
Two-wire serial interface clock (Master).
FV_IN
Input
Sensor frame valid input.
LV_IN
Input
Sensor line valid input.
PIXCLK_IN
Input
Sensor pixel clock input.
DIN[11:0]
Input
Sensor pixel data input DIN[11:0]
CLK_N
Input
Differential HiSPi clock (sub-LVDS, negative).
CLK_P
Input
Differential HiSPi clock (sub-LVDS, positive).
DATA0_N
Input
Differential HiSPi data, lane 0 (sub-LVDS, negative).
DATA0_P
Input
Differential HiSPi data, lane 0 (sub-LVDS, positive).
DATA1_N
Input
Differential HiSPi data, lane 1 (sub-LVDS, negative).
Differential HiSPi data, lane 1 (sub-LVDS, positive).
DATA1_P
Input
TRIGGER_OUT
Output
Trigger signal for external sensor.
FV_OUT
Output
Host frame valid output (synchronous to PIXCLK_OUT)
LV_OUT
Output
Host line valid output (synchronous to PIXCLK_OUT)
PIXCLK_OUT
Output
Host pixel clock output.
DOUT[15:0]
Output
Host pixel data output (synchronous to PIXCLK_OUT) DOUT[15:0].
DAC_POS
Output
Positive video DAC output in differential mode. Video DAC output in singleended mode. This interface is enabled by default using NTSC/PAL signaling.
For applications where composite video output is not required, the video DAC
can be placed in a power-down state under software control.
DAC_NEG
Output
Negative video DAC output in differential mode.
DAC_REF
Output
External reference resistor for Video DAC.
GPIO [5:1]
I/O
General purpose digital I/O.
TRST_BAR
Input
Must be tied to GND in normal operation.
VDDIO_S
Supply
Sensor I/O power supply.
VDDIO_H
Supply
Host I/O power supply.
VDD_PLL
Supply
PLL supply.
VDD
Supply
Core supply.
VDDIO_OTPM
Supply
OTPM power supply.
VDD_DAC
Supply
Video DAC digital power
VDDA_DAC
Supply
Video DAC analog power
VDD_PHY
Supply
PHY IO voltage for HiSPi
AP0100CS/D Rev. 6, Pub. 1/16 EN
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©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
System Interfaces
Table 3:
Pin Descriptions (Continued)
Name
Type
GND
Supply
Ground
VDD_REG
Supply
Input to on-chip 1.8V to 1.2V regulator.
LDO_OP
Output
Output from on chip 1.8V to 1.2V regulator.
FB_SENSE
Output
On-chip regulator sense signal.
AP0100CS/D Rev. 6, Pub. 1/16 EN
Description
9
©Semiconductor Components Industries, LLC,2016.
AP0100CS/D Rev. 6, Pub. 1/16 EN
Table 4:
Package Pinout
1
2
3
4
5
6
7
8
9
10
A
DOUT[11]
DOUT[13]
PIXCLK_OUT
LV_OUT
GPIO_2
TRST_BAR
SPI_SDI
SADDR
SCLK
B
DOUT[12]
DOUT[10]
DOUT[14]
FV_OUT
GPIO_3
GPIO[5]
SPI_SCLK
SDATA
TRIGGER_OUT RESET_BAR_OUT
C
DOUT[9]
DOUT[8]
DOUT[15]
GPIO[1]
GPIO_4
SPI_CS_BAR
SPI_SDO
VDDIO_H
M_SDATA
M_SCLK
D
DOUT[5]
DOUT[6]
DOUT[7]
VDDIO_H
VDDIO_HOST
VDD
FRAME_SYNC VDD
FV_IN
MCLK_OUT
E
DOUT[2]
DOUT[3]
DOUT[4]
VDDIO_H
GND
GND
GND
LV_IN
PIXCLK_IN
DIN[11]
F
DOUT[0]
DOUT[1]
EXTCLK
VDDIO_H
GND
GND
GND
VDDIO_S
DIN[9]
DIN[10]
G
GND
VDD_PLL
XTAL
VDD
VDD
VDD
GND
DIN[6]
DIN[7]
DIN[8]
H
VDD_PLL
VDD_PLL
LDO_OUTPUT VDDIO_OTPM DAC_NEG
DAC_REF
GNDA_DAC
VDD_PHY
DIN[4]
DIN[5]
J
EXT_REG
RESET_BAR
VDD_REG
VDD_DAC
DAC_POS
DATA0_P
CLK_P
DATA1_N
DIN[0]
DIN[2]
K
GND
FB_SENSE
ENLDO
GND
VDDA_DAC
DATA0_N
CLK_N
DATA1_P
DIN[1]
DIN[3]
STANDBY
10
Part Number: Image Signal Processor (ISP)
System Interfaces
©Semiconductor Components Industries, LLC,2016
AP0100CS HDR: Image Signal Processor (ISP)
On-Chip Regulator
On-Chip Regulator
The AP0100CS has an on-chip regulator, the output from the regulator is 1.2 V and
should only be used to power up the AP0100CS. It is possible to bypass the regulator and
provide power to the relevant pins that need 1.2 V. Figure 5 shows how to configure the
AP0100CS to bypass the internal regulator.
External Regulator
Host IO
power
V DDIO_OTPM
M_S DATA
V DD_PHY
V DDA_DAC
EXT_REG
M_S CLK
V DD
V DD_DAC
V DDIO _S
FB_SENSE
V DD_REG
Host IO
power
V DD_PLL
DAC
PHY
analog
External supplied
power
power
1.2V
OTPM
Host IO
power
power
LDO_OP
Sensor IO
power
ENLDO
Figure 5:
V DDIO _H
S CLK
S DATA
S ADDR
STANDBY
EXTCLK
EXTCLK_OUT
XTAL
RESET_BAR_OUT
SPI_CS_BAR
SPI_CLK
SPI_SDO
SPI_SDI
FV _IN
LV_IN
PIXCLK _IN
DIN [11:0]
FV_OUT
LV_OUT
PIXCLK_OUT
D OUT[15:0]
DAC_POS
DAC_NEG
DAC_REF
FRAME_SYNC
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
TRIGGER_OUT
CLK_N CLK_P
DATA0_N DATA0_P
DATA1_N DATA1_P
TRST_BAR
G ND
The following table summarizes the key signals when using/bypassing the regulator.
Table 5:
Key Signals When Using the Regulator
Signal Name
Internal Regulator
VDD_REG
1.8 V
ENLDO
Connect to 1.8 V (VDD_REG)
GND
FB_SENSE
1.2 V (output)
Float
LDO_OP
1.2 V (output)
Float
EXT_REG
GND
AP0100CS/D Rev. 6, Pub. 1/16 EN
11
External Regulator
Connect to VDDIO_H
Connect to VDDIO_H
©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
On-Chip Regulator
Power-Up Sequence
Powering up the ISP requires voltages to be applied in a particular order, as seen in
Figure 6. The timing requirements are shown in Table 6. The ISP includes a power-on
reset feature that initiates a reset upon power up of the ISP.
Figure 6:
Power-Up and Power-Down Sequence
dv/dt
V DDIO_H
dv/dt
t7
t1
VDDIO_S, VDDIO_OTPM, VDDA_DAC,
VDD_PHY (when using HiSPi)
t2
dv/dt
t6
V DD_REG
t3
t5
EXTCLK
SCLK
t4
SDATA
Table 6:
Power-Up and Power-Down Signal Timing
Symbol Parameter
t1
Delay from VDDIO_H to VDDIO_S, VDDIO_OTPM, VDDA_DAC, VDD_PHY
(When using HiSPi)
t2
Delay from VDDIO_H to VDD_REG
t3
EXTCLK activation
t4
First serial command1
t5
EXTCLK cutoff
t6
t7
dv/dt
Min
Typ
Max
Unit
0
–
50
ms
0
–
50
ms
t2 + 1
–
–
ms
100
–
–
EXTCLK cycles
t6
–
–
ms
Delay from VDD_REG to VDDIO_H
0
–
50
ms
Delay from VDDIO_S, VDDIO_OTPM, VDDA_DAC, VDD_PHY (When using
HiSPi) to VDDIO_H
0
–
50
ms
Power supply ramp time (slew rate)
–
–
0.1
V/s
Note:
1. When using XTAL the settling time should be taken into account.
Reset
The AP0100CS has three types of reset available:
• A hard reset is issued by toggling the RESET_BAR signal
• A soft reset is issued by writing commands through the two-wire serial interface
• An internal power-on reset
Table 7 on page 13 shows the output states when the part is in various states.
AP0100CS/D Rev. 6, Pub. 1/16 EN
12
©Semiconductor Components Industries, LLC,2016.
AP0100CS/D Rev. 6, Pub. 1/16 EN
Table 7:
Output States
Hardware States
Name
Firmware States
Reset State
Default State
Hard Standby
Soft Standby
Streaming
EXTCLK
(clock running
or stopped)
(clock running)
(clock running
or stopped)
(clock running) (clock running) (clock running) Input
XTAL
n/a
n/a
n/a
n/a
RESET_BAR
(asserted)
(negated)
(negated)
(negated)
(negated)
(negated)
Input
(clock running
or stopped)
(clock running
or stopped)
(clock running
or stopped)
Input. Must always be driven to a valid logic
level
n/a
Idle
n/a
Notes
Input
13
n/a
n/a
SDATA
Highimpedance
Highimpedance
Highimpedance
Highimpedance
SADDR
n/a
n/a
n/a
n/a
n/a
n/a
Input. Must always be driven to a valid logic
level
FRAME_SYNC
n/a
n/a
n/a
n/a
n/a
n/a
Input. Must always be driven to a valid logic
level
STANDBY
n/a
(negated)
(asserted)
(negated)
(negated)
(negated)
Input. Must always be driven to a valid logic
level
EXT_REG
n/a
n/a
n/a
n/a
n/a
n/a
Input. Must always be driven to a valid logic
level
ENLDO
n/a
n/a
n/a
n/a
n/a
n/a
Input. Must be tied to VDD_REG or GND
SPI_SCLK
Highimpedance
driven, logic 0
driven, logic 0
driven, logic 0
Output
SPI_SDI
Internal pullup enabled
Internal pullup enabled
Internal pullup enabled
internal pullup enabled
Input. Internal pull-up permanently
enabled.
SPI_SDO
Highimpedance
driven, logic 0
driven, logic 0
driven, logic 0
Output
SPI_CS_BAR
Highimpedance
driven, logic 1
driven, logic 1
driven, logic 1
Output
EXT_CLK_OUT driven, logic 0
driven, logic 0
driven, logic 0
driven, logic 0
Output
RESET_BAR_O
driven, logic 0
UT
driven, logic 0
driven, logic 1
driven, logic 1
Output. Firmware will release sensor reset
Input/Output. A valid logic level should be
established by pull-up
M_SCLK
Highimpedance
Highimpedance
Highimpedance
Highimpedance
Input/Output. A valid logic level should be
established by pull-up
M_SDATA
Highimpedance
Highimpedance
Highimpedance
Highimpedance
Input/Output. A valid logic level should be
established by pull-up
FV_IN ,LV_IN,
PIXCLK_IN,
DIN[11:0]
n/a
n/a
n/a
n/a
Dependent on
interface used
n/a
Input. Must always be driven to a valid logic
level
Part Number: Image Signal Processor (ISP)
On-Chip Regulator
©Semiconductor Components Industries, LLC,2016
SCLK
(clock running
or stopped)
AP0100CS/D Rev. 6, Pub. 1/16 EN
Table 7:
Output States
Hardware States
Name
Reset State
Default State
Firmware States
Hard Standby
Soft Standby
Streaming
Idle
Notes
CLK_N
CLK_P
DATA0_N
Disabled
Disabled
Dependent on
interface used
Dependent on
interface used
Dependent on
interface used
Dependent on
interface used
Input. Will be disabled and can be left
floating
Highimpedance
Varied
Driven if used
Driven if used
Driven if used
Driven if used
Output. Default state dependent on
configuration
Varied
Varied
Driven if used
Driven if used
Driven if used
Driven if used
Output. Default state dependent on
configuration. Tie to ground if VDAC not
used
DAC_REF
n/a
n/a
n/a
n/a
n/a
n/a
Input. Requires reference resistor. Tie to
ground if VDAC not used
GPIO[5:2]
Highimpedance
Input, then
highimpedance
Driven if used
Driven if used
Driven if used
Driven if used
Input/Output. After reset, these pins are
sampled as inputs as part of autoconfiguration.
GPIO1
Highimpedance
Highimpedance
Highimpedance
Highimpedance
Highimpedance
Highimpedance
TRIGGER_OUT
Highimpedance
Highimpedance
Driven if used
Driven if used
Driven if used
Driven if used
TRST_BAR
n/a
n/a
(negated)
(negated)
(negated)
(negated)
DATA0_P
DATA1_N
DATA1_P
FV_OUT,
LV_OUT,
PIXCLK_OUT,
DOUT[15:0]
DAC_POS
DAC_NEG
14
©Semiconductor Components Industries, LLC,2016
Part Number: Image Signal Processor (ISP)
On-Chip Regulator
Input. Must always be driven to a valid logic
level.
AP0100CS HDR: Image Signal Processor (ISP)
On-Chip Regulator
Hard Reset
The AP0100CS enters the reset state when the external RESET_BAR signal is asserted
LOW, as shown in Figure 7. All the output signals will be in High-Z state.
Figure 7:
Hard Reset Operation
t4
t1
t3
t2
EXTCLK
RESET_BAR
SDATA
All Outputs
Data Active
Data Active
Mode
Reset
Table 8:
Symbol
Enter streaming mode
Internal Initialization Time
Hard Reset
Definition
Min
Typ
Max
t1
RESET_BAR pulse width
50
–
–
t2
Active EXTCLK required after RESET_BAR asserted
10
–
–
t3
Active EXTCLK required before RESET_BAR deasserted
10
–
–
t4
First two-wire serial interface communication after
RESET is HIGH
100
–
–
Unit
EXTCLK
cycles
Soft Reset
A soft reset sequence to the AP0100 CS can be activated by writing to a register through
the two-wire serial interface.
Hard Standby Mode
The AP0100CS can enter hard standby mode by using external STANDBY signal, as
shown in Figure 8.
Entering Standby Mode
1. Assert STANDBY signal HIGH.
AP0100CS/D Rev. 6, Pub. 1/16 EN
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©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
On-Chip Regulator
Exiting Standby Mode
1. De-assert STANDBY signal LOW.
Figure 8:
Hard Standby Operation
t1
t2
t3
EXTCLK
STANDBY
Mode
Table 9:
Symbol
t1
t2
t3
STANDBY
Asserted
STANDBY
Mode
EXTCLK Disabled
EXTCLK Enabled
Hard Standby Signal Timing
Parameter
Min
Typ
Max
Unit
Standby entry complete
–
–
2 Frames
Lines
Active EXTCLK required after going into STANDBY
mode
10
–
–
EXTCLKs
Active EXTCLK required before STANDBY
de-asserted
10
–
–
EXTCLKs
AP0100CS/D Rev. 6, Pub. 1/16 EN
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©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
Multi-Camera Synchronization Support
Multi-Camera Synchronization Support
The AP0100CS supports multi-camera synchronization through the FRAME_SYNC pin.
The behavior will be different depending if the user is using interlaced or progressive
mode.
When using the interlaced modes, on the rising edge of FRAME_SYNC this will cause the
output to stop the current frame (A) and during B the image output will be indeterminate. On the falling edge of FRAME_SYNC this will cause the re-synchronization to
begin, this will continue for a period (C), during C black fields will be output. The resynchronized interlaced signal will be available at D. During C if the user toggles the
FRAME_SYNC input the AP0100CS will ignore it, the user cannot re-synchronize again
until at D.
Figure 9:
Frame Sync Behavior with Interlaced Mode
FRAME_SYNC
CVBS output
(NTSC/PAL)
A
B
C
D
When using progressive mode, the host (or controlling entity) ‘broadcasts’ a sync-pulse
to all cameras within the system that triggers capture. The AP0100AT will propagate the
signal to the TRIGGER_OUT pin, and subsequently to the attached sensor's TRIGGER
pin.
The AP0100CS supports two different trigger modes when using progressive output. The
first mode supported is ‘single-shot’; this is when the trigger pulse will cause one frame
to be output from the image sensor and AP0100CS (see Figure 10).
Figure 10:
Single-Shot Mode
FRAME_SYNC
TRIGGER_OUT
FV_OUT
Note:
This diagram is not to scale.
The second mode supported is called 'continuous', this is when a trigger pulse will cause
the part to continuously output frames, see Figure 11. This mode would be especially
useful for applications which have multiple sensors and need to have their video
streams synchronized (for example, surround view or panoramic view applications).
AP0100CS/D Rev. 6, Pub. 1/16 EN
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©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
Multi-Camera Synchronization Support
Figure 11:
Continuous Mode
FRAME_SYNC
TRIGGER_OUT
FV_OUT
Note:
This diagram is not to scale.
When two or more cameras have a signal applied to the FRAME_SYNC input at the same
time, the respective FV_OUT signals would be synchronized within 5 PIXCLK_OUT
cycles. This assumes that all cameras have the same configuration settings and that the
exposure time is the same.
AP0100CS/D Rev. 6, Pub. 1/16 EN
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©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
Image Flow Processor
Image Flow Processor
Image and color processing in the AP0100CS is implemented as an image flow processor
(IFP) coded in hardware logic. During normal operation, the embedded microcontroller
will automatically adjust the operating parameters. For normal operation of the
AP0100CS, streams of raw image data from the attached image sensor are fed into the
color pipeline. The user also has the option to select a number of test patterns to be
input instead of sensor data. The IFP is broken down into different sections, as outlined
in Figure 12.
Figure 12:
AP0100CS IFP
R A W 1 2 - o r 2 0-b it B a ye r
AE, F D and ALT M
stats
1 2 - b it A L T M B a ye r
linear or
com panded data
RX
decom panding
D efect cor r ection
,
N oise r eduction
Black level
subtr action
,
D igital gain
contr ol,
PG A
ALT M
C olor
Inter polation
C olor
C or r ection
Aper tur e
C or r ection
C r op
G am m a
R G B 2YU V
C olor Kill
YU V
filter s
P rogres s iv e
(Y C bC r or
B ay er)
Scaler
AW B stats
Progressive
T est pattern
generator
C C IR656
(Y C bC r)
ST E
R A W B a ye r
A L T M B a ye r
R GB
Inter lacer
O ver lay
PAL /N T SC
Encode D AC
N T S C /P A L
(Y C bC r)
PAL /N T SC
T est patter ns
Y C bC r
AP0100CS/D Rev. 6, Pub. 1/16 EN
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©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
Test Patterns
Test Patterns
The AP0100CS has a number of test patterns that are available when using the progressive, NTSC and PAL modes. The test patterns can be selected by programming variables.
To enter test pattern mode, set R0xC88F to 0x02 and issue a Change-Config request; to
exit this mode, set R0xC88F to 0x00, and issue a Change-Config request.
NTSC and PAL test patterns can only be selected when the device is configured for interlaced operation.
Progressive Test Patterns
Figure 13:
Progressive Test Patterns
Example
Test Pattern
FLAT FIELD
REG= 0xC88C, 0x02
// CAM_MODE_SELECT
REG= 0xC88F, 0x01
// CAM_MODE_TEST_PATTERN_SELECT
REG= 0xC890, 0x000FFFFF
// CAM_MODE_TEST_PATTERN_RED
REG= 0xC894, 0x000FFFFF
// CAM_MODE_TEST_PATTERN_GREEN
REG= 0xC898, 0x000FFFFF
// CAM_MODE_TEST_PATTERN_BLUE
Load = Change-Config
Changing the values in R0xC890-R0x898 will change the color of the
test pattern (will require a Refresh operation).
100% Color Bar
REG= 0xC88C, 0x02
REG= 0xC88F, 0x02
Load = Change-Config
// CAM_MODE_SELECT
// CAM_MODE_TEST_PATTERN_SELECT
Pseudo-Random
REG= 0xC88C, 0x02
REG= 0xC88F, 0x05
Load = Change-Config
Fade-to-Gray
REG= 0xC88C, 0x02
REG= 0xC88F, 0x08
Load = Change-Config
// CAM_MODE_SELECT
// CAM_MODE_TEST_PATTERN_SELECT
// CAM_MODE_SELECT
// CAM_MODE_TEST_PATTERN_SELECT
Linear Ramp
REG= 0xC88C, 0x02
REG= 0xC88F, 0x09
Load = Change-Config
AP0100CS/D Rev. 6, Pub. 1/16 EN
// CAM_MODE_SELECT
// CAM_MODE_TEST_PATTERN_SELECT
20
©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
Test Patterns
NTSC Test Patterns
Figure 14:
NTSC Test Patterns
Example
Test Pattern
EIA Full Field 7 Color Bars
REG= 0xC88C, 0x02
REG= 0xC88F, 0x14
Load = Change-Config
EIA Full Field 8 Color Bars
REG= 0xC88C, 0x02
REG= 0xC88F, 0x15
Load = Change-Config
// CAM_MODE_SELECT
// CAM_MODE_TEST_PATTTERN_SELECT
// CAM_MODE_SELECT
// CAM_MODE_TEST_PATTERN_SELECT
SMPTE EG 1-1990
REG= 0xC88C, 0x02
REG= 0xC88F, 0x16
Load = Change-Config
// CAM_MODE_SELECT
// CAM_MODE_TEST_PATTERN_SELECT
EIA Full Field 8 Color Bars 100 IRE
REG= 0xC88C, 0x02
// CAM_MODE_SELECT
REG= 0xC88F, 0x17
// CAM_MODE_TEST_PATTERN_SELECT
Load = Change-Config
AP0100CS/D Rev. 6, Pub. 1/16 EN
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©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
Test Patterns
PAL Test Patterns
Figure 15:
PAL Test Patterns
Example
Test Pattern
EBU Full Field 7 Color Bars
REG= 0xC88C, 0x02
REG= 0xC88F, 0x1E
Load = Change-Config
EBU Full Field 8 Color Bars
REG= 0xC88C, 0x02
REG= 0xC88F, 0x1F
Load = Change-Config
// CAM_MODE_SELECT
// CAM_MODE_TEST_PATTERN_SELECT
// CAM_MODE_SELECT
// CAM_MODE_TEST_PATTERN_SELECT
Each NTSC/PAL test pattern consists of seven or eight color bars (white, yellow, cyan,
green, magenta, red, blue and optionally black). The Y, Cb and Cr values for each bar are
detailed in Table 10.
For the NTSC SMPTE test pattern it is also required to generate -I, +Q, -4 black and +4
black.
Table 10:
NTSC/PAL Test Pattern Values
Nominal
Range
Y
Cb
Cr
16 to 235
16 to 240
16 to 240
AP0100CS/D Rev. 6, Pub. 1/16 EN
White White
100%
75% Yellow
235
128
128
180
128
128
162
44
142
Cyan
Green
Magent
a
Red
Blue
Black
-I
-Q
-4
black
+4
black
131
156
44
112
72
58
84
184
198
65
100
212
35
212
114
16
128
128
16
156
97
16
171
148
7
128
128
25
128
128
22
©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
Test Patterns
Figure 16:
Test Pattern
Defect Correction
Image stream processing commences with the defect correction function immediately
after data decompanding.
To obtain defect free images, the pixels marked defective during sensor readout and the
pixels determined defective by the defect correction algorithms are replaced with values
derived from the non-defective neighboring pixels. This image processing technique is
called defect correction.
AdaCD (Adaptive Color Difference)
Automotive applications require good performance in extremely low light, even at high
temperature conditions. In these stringent conditions the image sensor is prone to
higher noise levels, and so efficient noise reduction techniques are required to circumvent this sensor limitation and deliver a high quality image to the user.
The AdaCD Noise Reduction Filter is able to adapt its noise filtering process to local
image structure and noise level, removing most objectionable color noise while
preserving edge details.
Black Level Subtraction and Digital Gain
After noise reduction, the pixel data goes through black level subtraction and multiplication of all pixel values by a programmable digital gain. Independent color channel digital
gain can be adjusted with registers. Black level subtraction (to compensate for sensor
data pedestal) is a single value applied to all color channels. If the black level subtraction
produces a negative result for a particular pixel, the value of this pixel is set to 0.
AP0100CS/D Rev. 6, Pub. 1/16 EN
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©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
Test Patterns
Positional Gain Adjustments (PGA)
Lenses tend to produce images whose brightness is significantly attenuated near the
edges. There are also other factors causing fixed pattern signal gradients in images
captured by image sensors. The cumulative result of all these factors is known as image
shading. The AP0100CS has an embedded shading correction module that can be
programmed to counter the shading effects on each individual R, Gb, Gr, and B color
signal.
The Correction Function
The correction functions can then be applied to each pixel value to equalize the
response across the image as follows:
P corrected  row, col  = P sensor  row, col   f(row, col)
(EQ 1)
where P are the pixel values and f is the color dependent correction functions for each
color channel.
AP0100CS/D Rev. 6, Pub. 1/16 EN
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©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
Test Patterns
Adaptive Local Tone Mapping (ALTM)
Real world scenes often have very high dynamic range (HDR) that far exceeds the electrical dynamic range of the imager. Dynamic range is defined as the luminance ratio
between the brightest and the darkest object in a scene. In recent years many technologies have been developed to capture the full dynamic range of real world scenes. For
example, the multiple exposure method is widely adopted for capturing high dynamic
range images, which combines a series of low dynamic range images of the same scene
taken under different exposure times into a single HDR image.
Even though the new digital imaging technology enables the capture of the full dynamic
range, low dynamic range display devices are the limiting factor. Today’s typical LCD
monitor has contrast ratio around 1,000:1; however, it is not typical for an HDR image
(the contrast ratio for an HDR image is around 250,000:1). Therefore, in order to reproduce HDR images on a low dynamic range display device, the captured high dynamic
range must be compressed to the available range of the display device. This is commonly
called tone mapping.
Tone mapping methods can be classified into global tone mapping and local tone
mapping. Global tone mapping methods apply the same mapping function to all pixels.
While global tone mapping methods provide computationally simple and easy to use
solutions, they often cause loss of contrast and detail. A local tone mapping is thus
necessary in addition to global tone mapping for the reproduction of visually more
appealing images that also reveal scene details that are important for automotive safety
and surveillance applications. Local tone mapping methods use a spatially variable
mapping function determined by the neighborhood of a pixel, which allows it to
increase the local contrast and the visibility of some details of the image. Local methods
usually yield more pleasing results because they exploit the fact that human vision is
more sensitive to local contrast.
ON Semiconductor’s ALTM solution significantly improves the performance over global
tone mapping. ALTM is directly applied to the Bayer domain to compress the dynamic
range from 20-bit to 12-bit. This allows the regular color pipeline to be used for HDR
image rendering.
Color Interpolation
In the raw data stream fed by the external sensor to the IFP, each pixel is represented by a
20- or 12-bit integer number, which can be considered proportional to the pixel's
response to a one-color light stimulus, red, green, or blue, depending on the pixel's position under the color filter array. Initial data processing steps, up to and including ALTM,
preserve the one-color-per-pixel nature of the data stream, but after ALTM it must be
converted to a three-colors-per-pixel stream appropriate for standard color processing.
The conversion is done by an edge-sensitive color interpolation module. The module
pads the incomplete color information available for each pixel with information
extracted from an appropriate set of neighboring pixels. The algorithm used to select
this set and extract the information seeks the best compromise between preserving
edges and filtering out high frequency noise in flat field areas. The edge threshold can be
set through register settings.
AP0100CS/D Rev. 6, Pub. 1/16 EN
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©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
Test Patterns
Color Correction and Aperture Correction
To achieve good color fidelity of the IFP output, interpolated RGB values of all pixels are
subjected to color correction. The IFP multiplies each vector of three pixel colors by a 3 x
3 color correction matrix. The three components of the resulting color vector are all
sums of three 10-bit numbers. The color correction matrix can be either programmed by
the user or automatically selected by the auto white balance (AWB) algorithm implemented in the IFP. Color correction should ideally produce output colors that are
corrected for the spectral sensitivity and color crosstalk characteristics of the image
sensor. The optimal values of the color correction matrix elements depend on those
sensor characteristics and on the spectrum of light incident on the sensor. The color
correction variables can be adjusted through register settings.
Traditionally this would have been derived from two sets of CCM, one for Warm light like
Tungsten and the other for Daylight (the part would interpolate between the two
matrices). This is not an optimal solution for cameras used in a Cool White Fluorescent
(CWF) environment. A better solution is to provide three CCMs, which would include a
matrix for CWF (interpolation now between three matrices). The AP0100CS offers this
feature which will give the user improved color fidelity when under CWF type lighting.
To increase image sharpness, a programmable 2D aperture correction (sharpening filter)
is applied to color-corrected image data. The gain and threshold for 2D correction can
be defined through register settings.
Gamma Correction
The gamma correction curve is implemented as a piecewise linear function with 33 knee
points, taking 12-bit arguments and mapping them to 10-bit output. The abscissas of the
knee points are fixed at 0, 8, 16, 24, 32, 40, 48, 56, 64, 80, 96, 112, 128, 160, 192, 224, 256,
320, 384, 448, 512, 640, 768, 896, 1024, 1280, 1536, 1792, 2048, 2560, 3072, 3584, and 4096.
The 10-bit ordinates are programmable through variables.
The AP0100CS has the ability to calculate the 33-point knee points based on the tuning
of cam_ll_gamma and cam_ll_contrast_gradient_bright. The other method is for the
host to program the 33 knee point curve themselves.
Also included in this block is a Fade-to Black curve which sets all knee points to zero and
causes the image to go black in extreme low light conditions.
Color Kill
To remove high-or low-light color artifacts, a color kill circuit is included. It affects only
pixels whose luminance exceeds a certain preprogrammed threshold. The U and V
values of those pixels are attenuated proportionally to the difference between their luminance and the threshold.
YUV Color Filter
As an optional processing step, noise suppression by one-dimensional low-pass filtering
of Y and/or UV signals is possible. A 3- or 5-tap filter can be selected for each signal.
AP0100CS/D Rev. 6, Pub. 1/16 EN
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©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
Camera Control and Auto Functions
Camera Control and Auto Functions
Auto Exposure
The auto exposure algorithm optimizes scene exposure to minimize clipping and saturation in critical areas of the image. This is achieved by controlling exposure time and
analog gains of the external sensor as well as digital gains applied to the image.
Auto exposure is implemented by a firmware algorithm that is running on the
embedded microcontroller that analyzes image statistics collected by the exposure
measurement engine, makes a decision, and programs the sensor and color pipeline to
achieve the desired exposure. The measurement engine subdivides the image into 25
windows organized as a 5 x 5 grid.
Figure 17:
5 x 5 Grid
AE Track Driver
Other algorithm features include the rejection of fast fluctuations in illumination (time
averaging), control of speed of response, and control of the sensitivity to small changes.
While the default settings are adequate in most situations, the user can program target
brightness, measurement window, and other parameters described above.
The driver changes AE parameters (integration time, gains, and so on) to drive scene
brightness to the programmable target.
To avoid unwanted reaction of AE on small fluctuations of scene brightness or momentary scene changes, the AE track driver uses a temporal filter for luma and a threshold
around the AE luma target. The driver changes AE parameters only if the filtered luma is
larger than the AE target step and pushes the luma beyond the threshold.
AP0100CS/D Rev. 6, Pub. 1/16 EN
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AP0100CS HDR: Image Signal Processor (ISP)
Camera Control and Auto Functions
Auto White Balance
The AP0100CS has a built-in AWB algorithm designed to compensate for the effects of
changing spectra of the scene illumination on the quality of the color rendition. The
algorithm consists of two major parts: a measurement engine performing statistical
analysis of the image and a driver performing the selection of the optimal color correction matrix and IFP digital gain. While default settings of these algorithms are adequate
in most situations, the user can reprogram base color correction matrices, place limits
on color channel gains, and control the speed of both matrix and gain adjustments. The
AP0100 CSAWB displays the current AWB position in color temperature, the range of
which will be defined when programming the CCM matrixes.
The region of interest can be controlled through the combination of an inclusion
window and an exclusion window.
Exposure and White Balance Control
The Sensor Manager firmware component is responsible for controlling the application
of 'exposure' and 'white balance' within the system. This effectively means that all
control of integration times and gains (whether for exposure or white balance) is delegated to the Sensor Manager. The Auto Exposure (AE) and Auto White Balance (AWB)
algorithms use services provided by the Sensor Manager to apply exposure and/or white
balance changes.
Dual Band IRCF
For some applications a day/night filter would be switched in/out, this option is an
additional cost to the camera system. The AP0100CS supports the use of dual band IRCF,
which removes the need for the switching day/night filter. Tuning support is provided
for this usage case. Refer to the AP0100CS developer guide for details.
Exposure and White Balance Modes
The AP0100CS supports auto and manual exposure and white balance modes. In addition, it will operate within synchronized multi-camera systems. In this use case, one
camera within the system will be the 'master', and the others 'slaves'. The master is used
to calculate the appropriate exposure and white balance. This is then applied to all
slaves concurrently under host control.
Auto Mode
In Auto Exposure mode the AE algorithm is responsible for calculating the appropriate
exposure to keep the desired scene brightness, and for applying the exposure to the
underlying hardware. In Auto White Balance mode the AWB algorithm is responsible for
calculating the color temperature of the scene and applying the appropriate red and
blue gains to compensate.
Triggered Auto Mode
The Triggered Auto Exposure and Triggered Auto White Balance modes are intended for
the multi-camera use cases, where a host is controlling the exposure and white balance
of a number of cameras. The idea is that one camera is in triggered-auto mode (the
master), and the others in host-controlled mode (slaves). The master camera must
calculate the exposure and gains, the host then copies this to the slaves, and all changes
are then applied at the same time.
AP0100CS/D Rev. 6, Pub. 1/16 EN
28
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AP0100CS HDR: Image Signal Processor (ISP)
Flicker Avoidance
Manual Mode
Manual mode is intended to allow simple manual exposure and white balance control
by the host. The host needs to set the CAM_AET_EXPOSURE_TIME_MS, CAM_AET_EXPOSURE_GAIN and CAM_AWB_COLOR_TEMPERATURE controls, the camera will
calculate the appropriate integration times and gains.
Host Controlled
The Host Controlled mode is intended to give the host full control over exposure and
gains
Flicker Avoidance
Flicker occurs when the integration time is not an integer multiple of the period of the
light intensity. The AP0100CS can be programmed to avoid flicker for 50 or 60 Hertz. For
integration times below the light intensity period (10ms for 50Hz environment), flicker
cannot be avoided. The AP0100CS supports an indoor AE mode, that will ensure flickerfree operation.
Flicker Detection
The AP0100CS supports flicker detection, the algorithm is designed only to detect a
50Hz or 60Hz flicker source.
Output Formatting
The pixel output data in AP0100CS will be transmitted as an 8/10 bit word over one or
two clocks.
Uncompressed YCbCr Data Ordering
The AP0100CS supports swapping YCbCr mode, as illustrated in Table 11.
Table 11:
YCbCr Output Data Ordering
Mode
Data Sequence
Default (no swap)
Cbi
Swapped CrCb
Swapped YC
Swapped CrCb, YC
Yi
Cri
Yi+1
Cri
Yi
Cbi
Yi+1
Yi
Cbi
Yi+1
Cri
Yi
Cri
Yi+1
Cbi
The data ordering for the YCbCr output modes for AP0100CS are shown in Table 12:
Table 12:
YCbCr Output Modes (cam_port_parallel_msb_align=0x1)
Mode
YCbCr_422_8_8
YCbCr_422_10_10
YCbCr_422_16
AP0100CS/D Rev. 6, Pub. 1/16 EN
Byte
Pixel i
Pixel i+1
Notes
Data range of 0-255 (Y=16-235 and C=16-240)
Odd (DOUT [15:8])
Cbi
Cri
Even (DOUT [15:8])
Yi
Yi+1
Odd (DOUT [15:6])
Cbi
Cri
Even (DOUT [15:6])
Yi
Yi+1
Single (DOUT [15:0])
Cbi_Yi
Cri_Yi+1
29
Data range of 0-1023 (Y=64-940 and C=64960)
Data range of 0-255 (Y=16-235 and C=16-240)
©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
Output Formatting
Note:
Table 13:
Odd means first cycle; even means second cycle.
YCbCr Output Modes (cam_port_parallel_msb_align=0x0)
Mode
Byte
YCbCr_422_8_8
YCbCr_422_10_10
YCbCr_422_16
Figure 18:
Pixel i
Pixel i+1
""Notes"
Data range of 0-255 (Y=16-235 and C=16-240)
Odd (DOUT[7 :0])
Cbi
Cri
Even (DOUT [7:0]
Yi
Yi+1
Odd (DOUT [9:0])
Cbi
Cri
Even (DOUT [9:0])
Yi
Yi+1
Single (DOUT [15:0])
Cbi_Yi
Cri_Yi+1
Data range of 0-1023 (Y=64-940 and C=64-960)"
Data range of 0-255 (Y=16-235 and C=16-240)
8- bit YCbCr Output (YCbCr_422_8_8)
P ix el C loc k
F ram e V alid
Porch – 0-255 cycles
Line V alid
Data[15:8]
00
Cr
Data[7:0]
Y Cb Y Cr
H Blank
Y Cb Y Cr
Y Cb Y Cr
Im age
H Blank
Y Cb Y Cr
Im age
H Blank
P ix el C loc k
F ram e V alid
Porch – 0-255 cycles
Line V alid
Data[15:8]
00
Data[7:0]
Cr
H Blank
Y Cb Y C r
Y Cb Y Cr
Y Cb Y Cr
Im age
H Blank
Y Cb Y Cr
Im age
H Blank
Active Video
P ix el C loc k
F ram e V alid
Porch – 0-255 cycles
Line V alid
Data[15:8]
Data[7:0]
00
Y Cb Y Cr
Im age
Vblank
P ix el C loc k
F ram e V alid
Porch – 0-255 cycles
Line V alid
Data[15:8]
00
Data[7:0]
Cr
Vblank
Y Cb Y Cr
Im age
Vertical Blanking
Notes:
AP0100CS/D Rev. 6, Pub. 1/16 EN
1. Cb Y Cr Y by default.
2. cam_port_parallel_msb_align=0x0
30
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AP0100CS HDR: Image Signal Processor (ISP)
Output Formatting
Figure 19:
10-bit YCbCr Output (YCbCr_422_10_10)
P ix el C loc k
F ram e V alid
Porch – 0-255 cycles
Line V alid
00
Data[5:0]
Y Cb Y Cr
Cr
Data[15:6]
H Blank
Y Cb Y Cr
Y Cb Y Cr
Im age
H Blank
Y Cb Y C r
Im age
H Blank
P ix el C loc k
F ram e V alid
Porch – 0-255 cycles
Line V alid
Data[5:0]
00
Data[15:6]
Cr
Y Cb Y Cr
H Blank
Y Cb Y C r
Y Cb Y Cr
Im age
H Blank
Y Cb Y C r
Im age
H Blank
Active Video
P ix el C loc k
F ram e V alid
Porch – 0-255 cycles
Line V alid
Data[5:0]
Data[15:6]
00
Y Cb Y C r
Im age
Vblank
P ix el C loc k
F ram e V alid
Porch – 0-255 cycles
Line V alid
Data[5:0]
00
Data[15:6]
Cr
Vblank
Y Cb Y Cr
Im age
Vertical Blanking
Notes:
AP0100CS/D Rev. 6, Pub. 1/16 EN
1. Cb Y Cr Y by default.
2. cam_port_parallel_msb_align=0x1
31
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AP0100CS HDR: Image Signal Processor (ISP)
Output Formatting
Figure 20:
16-bit YCbCr Output (YCbCr_422_16)
Pixel Clock
Frame Valid
Porch – 0-255 cycles
Line Valid
Data[7:0]
Data[15:8]
Y
Y Y Y Y
Cr
Cb Cr Cb C r
H Blank
Y Y Y Y
Y Y Y Y
Cb Cr Cb C r
Y Y Y Y
Cb Cr Cb Cr
Im age
H Blank
Cb Cr Cb C r
Im age
H Blank
Pixel Clock
Frame Valid
Porch – 0-255 cycles
Line Valid
Data[7:0]
Data[15:8]
Y
Y Y Y Y
Cr
Cb Cr Cb Cr
H Blank
Y Y Y Y
Y Y Y Y
Cb Cr Cb C r
Y Y Y Y
Cb Cr Cb C r
Im age
H Blank
Cb Cr Cb C r
Im age
H Blank
Active Video
Pixel Clock
Frame Valid
Porch – 0-255 cycles
Line Valid
Data[7:0]
Data[15:8]
Y Y Y Y
Cb Cr Cb Cr
Im age
Vblank
Pixel Clock
Frame Valid
Porch – 0-255 cycles
Line Valid
Data[7:0]
Data[15:0]
Y
Y Y Y Y
Cr
Cb Cr Cb Cr
Vblank
Im age
Vertical Blanking
AP0100CS/D Rev. 6, Pub. 1/16 EN
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AP0100CS HDR: Image Signal Processor (ISP)
Output Formatting
Figure 21:
Typical CCIR656 Output
Pixel Clock
Frame Valid
Line Valid
Data[15:8]
Data[7:0]
00
80
10
80
10
80
10
80
10
FF
Blanking
00
00
80
Cb
Y
Cr
Y
SAV
Cb
Y
Cr
Y
FF
Image
00
00
9D
80
10
80
10
EAV
80
10
80
10
FF
Blanking
HBlank
00
00
80
Cb
Y
Cr
Y
SAV
Cb
Y
Cr
Y
FF
Image
00
00
9D
80
10
80
EAV
10
Blanking
HBlank
HBlank
Pixel Clock
Frame Valid
Line Valid
Data[15:8]
Data[7:0]
00
80
10
80
10
80
10
80
10
FF
Blanking
00
00
80
Cb
Y
Cr
Y
SAV
Cb
Y
Cr
Y
Image
FF
00
00
B6
80
10
80
10
EAV Blank
80
10
80
10
Blanking
HBlank
FF
00
00
AB
80
10
80
10
SAV Blank
80
10
80
10
VBlank
FF
00
00
B6
80
10
80
EAV blank
HBlank
10
Blanking
HBlank
Field 1
Pixel Clock
Frame Valid
Line Valid
Data[15:8]
Data[7:0]
00
80
10
80
10
80
10
80
10
FF
Blanking
00
00
C7
Cb
Y
Cr
Y
SAV
Cb
Y
Cr
Y
FF
Image
00
00
DA
80
10
80
10
EAV
80
10
80
10
FF
Blanking
HBlank
00
00
C7
Cb
Y
Cr
Y
SAV
Cb
Y
Cr
Y
FF
Image
00
00
DA
80
10
80
EAV
10
Blanking
HBlank
HBlank
Pixel Clock
Frame Valid
Line Valid
Data[15:8]
Data[7:0]
00
80
10
80
10
80
10
80
Blanking
10
FF
00
00
SAV
C7
Cb
Y
Cr
Y
Cb
Image
Y
Cr
Y
FF
00
00
F1
80
10
EAV Blank
80
10
80
Blanking
HBlank
HBlank
10
80
10
FF
00
00
EC
SAV Blank
80
10
80
10
80
VBlank
10
80
10
FF
00
00
F1
80
10
80
EAV blank
10
Blanking
HBlank
Field 2
AP0100CS/D Rev. 6, Pub. 1/16 EN
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AP0100CS HDR: Image Signal Processor (ISP)
Output Formatting
Figure 22:
Typical CVBS Output (NTSC/PAL)
Line Valid to First Field Latency ~= STE Latency + 1 Field
Frame Valid In
Line Valid In
1
2
3
4
5
6
7
8
9
Video
Pre-Equalisation
Pulses
Post-Equalising
Pulses
Serration Pulses
Field 1 / 3
Frame Valid In
Line Valid In
1
2
3
4
5
6
7
8
9
Video
Pre-Equalisation
Pulses
Serration Pulses
Post-Equalising
Pulses
Field 2 / 4
AP0100CS/D Rev. 6, Pub. 1/16 EN
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©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
Bayer Modes
Bayer Modes
Bayer output modes are only available in progressive output mode before STE. The data
ordering for the ALTM Bayer output modes for AP0100CS are shown in Table 14.
Table 14:
ALTM Bayer Output Modes
Mode
Byte
D1
5
D1
4
D1
3
D1
2
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
ALTM_Bayer_10
ALTM_Bayer_12
Single
Single
0
0
0
0
0
0
0
0
0
D11
0
D10
D9
D9
D98
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Table 14 and Table 15 show LSB aligned data; it is possible using register setting to obtain
MSB aligned data.
The data ordering for the Bayer output modes for AP0100CS are shown in Table 15.
Table 15:
Bayer Output Modes
Mode
Byte
Bayer_1
2
Singl
e
D15 D14 D13 D12 D11 D10
0
0
0
Note:
0
D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Notes
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
RAW Bayer
data
Bayer_12 can be selected by setting cam_mode_select = 0x1 and requesting a Change-Config
operation.
Sensor Embedded Data
The AP0100CS is capable of passing sensor embedded data in Bayer output mode only.
The AP0100CS Statistics are available through the serial interface. Refer to the developer
guide for details.
AP0100CS/D Rev. 6, Pub. 1/16 EN
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AP0100CS HDR: Image Signal Processor (ISP)
Spatial Transform Engine (STE)
Spatial Transform Engine (STE)
A spatial transform is defined as a transform in which some pixels are in different positions within the input and output pictures. Examples include zoom, lens distortion
correction, turn, and rotate. STE is a fully programmable engine which can perform
spatial transforms and eliminates the need for an expensive DSP for image correction.
Lens Distortion Correction
Automotive backup cameras typically feature a wide FOV lens so that a single camera
mounted above the center of the rear bumper can present the driver with a view of all
potential obstacles immediately behind the full width of the vehicle. Lenses with a wide
field of view typically exhibit at least a noticeable amount of barrel distortion.
Barrel distortion is caused by a reduction in object magnification the further away from
the optical axis.
For the image to appear natural to the driver, the AP0100CS corrects this barrel distortion and reprocesses the image so that the resulting distortion is much smaller. This is
called distortion correction. Distortion correction is the ability to digitally correct the
lens barrel distortion and to provide a natural view of objects. In addition, with barrel
distortion one can adjust the perspective view to enhance the visibility by virtually
elevating the point of viewing objects.
Pan, Tilt, Zoom and Rotate
Using the STE it is possible to implement image transformations like Pan, Tilt, Zoom and
Rotate.
Figure 23:
Uncorrected Image
AP0100CS/D Rev. 6, Pub. 1/16 EN
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AP0100CS HDR: Image Signal Processor (ISP)
Spatial Transform Engine (STE)
Figure 24:
Zoomed
Figure 25:
Zoom and Look Left
AP0100CS/D Rev. 6, Pub. 1/16 EN
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©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
Overlay Capability
Figure 26:
Zoom and Look Right
Overlay Capability
Figure 27 highlights the graphical overlay data flow of the AP0100CS. The images are
separated to fit into 4KB blocks of memory after compression.
• Up to seven overlays may be blended simultaneously
• Overlay size up to 720 x 576 pixels rendered
• Selectable readout: rotating order is user programmable
• Dynamic movement through predefined overlay images
• Palette of 32 colors out of 16 million with 16 colors per bitmap
• Each color has a YCbCr (8-8-8 bit) and 8 bits for the Alpha value (Transparency).
• Each layer has a built in fader which when enabled scales the Alpha value for each
pixel.
• Blend factors may be changed dynamically to achieve smooth transitions
The overlay engine is controlled through host commands that allow a bitmap to be
written piecemeal to a memory buffer through the two-wire serial interface, and
through a DMA chanel direct from SPI Flash memory. Multiple encoding passes may be
required to fit an image into a 4KB block of memory; alternatively, the image can be
divided into two or more blocks to make the image fit. Every graphic image may be positioned in an x/y direction and overlap with other graphic images.
The host may load an image at any time. Under control of DMA assist, data are transferred to the off-screen buffer in compressed form. This assures that no display data are
corrupted during the replenishment of the seven active overlay buffers.
AP0100CS/D Rev. 6, Pub. 1/16 EN
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AP0100CS HDR: Image Signal Processor (ISP)
Overlay Capability
Figure 27:
Overlay Data Flow
Overlay buffers: 4KB each
NVM
Decompress
Blend and Overlay
Bitmaps - compressed
Note:
AP0100CS/D Rev. 6, Pub. 1/16 EN
Off-screen
buffer
These images are not actually rendered, but show conceptual objects and object blending.
39
©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
Serial Memory Partition
Serial Memory Partition
The contents of the Flash/EEPROM memory partition logically into three blocks (see
Figure 28):
• Memory for overlay data and descriptors
• Memory for register settings, which may be loaded at boot-up
• Firmware extensions or software patches; in addition to the on-chip firmware, extensions reside in this block of memory
These blocks are not necessarily contiguous.
Figure 28:
Memory Partitioning
Flash
Partitioning
Flash
Partitioning
Fixed-size
Fixed Size
Overlays
– RLE
Overlays-RLE
Fixed Size
Fixed-size
Overlays
– RLE
Overlays-RLE
12-byte
12Byte Header
Header
Overlay
DataData
Overlay
RLEEncoded
Encoded
RLE
Data
Data
2KB
4Kb
2kByte
Lens Shading
Lens Correction
Correction
Parameter
Parameter
Alternate
Alternate
Reg.
Register
Setting
Setting
S/W Patch
Software
Patch
AP0100CS/D Rev. 6, Pub. 1/16 EN
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©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
Overlay Adjustment
Overlay Adjustment
To ensure a correct position of the overlay to compensate for assembly deviation, the
overlay can be adjusted with assistance from the calibration statistics engine:
• The calibration statistics engine supports a windowed 8-bin luma histogram, either
row-wise (vertical) or column-wise (horizontal).
• The example calibration statistics function of the firmware can be used to perform an
automatic successive approximation search of a cross-hair target within the scene.
• On the first frame, the firmware performs a coarse horizontal search, followed by a
coarse vertical search in the second frame.
• In subsequent frames, the firmware reduces the region-of-interest of the search to the
histogram bins containing the greatest accumulator values, thereby refining the search.
• The resultant X, Y location of the cross-hair target can be used to assign a calibration
value of offset selected overlay graphic image positions within the output image.
• The calibration statistics also supports a manual mode, which allows the host to access
the raw accumulator values directly.
Composite Video Output
The external pin GPIO[3] can be used to configure the device for default NTSC or PAL
operation. This and other video configuration settings are available as register settings
accessible through the serial interface.
Single-Ended and Differential Composite Output
The composite output can be operated in a single-ended or differential mode by simply
changing the external resistor configuration. For single-ended termination, see
Figure 29 on page 41. The differential schematic is shown in Figure 30 on page 42.
Figure 29:
Single-Ended Termination
The DAC is differential, but it may be used to produce single-ended signals provided that
the unused (DAC_NEG) output is terminated into a resistance to ground approximately
equal to the load on the DAC_POS output. Without this termination, the internal bias
AP0100CS/D Rev. 6, Pub. 1/16 EN
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AP0100CS HDR: Image Signal Processor (ISP)
Overlay Adjustment
circuits will not be kept in their proper operating regions and the dynamic performance
of the DAC will be degraded. Termination straight into ground causes all of the power
dissipation to occur on the chip, which is undesirable. If a one component saving was
absolutely critical, termination straight to ground is a possibility.
Figure 30:
Differential Connection
If the user is not using the analog output then Figure 31 shows how the signals should be
connected.
Figure 31:
No DAC
AP0100CS/D Rev. 6, Pub. 1/16 EN
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AP0100CS HDR: Image Signal Processor (ISP)
Slave Two-Wire Serial Interface (CCIS)
Slave Two-Wire Serial Interface (CCIS)
The two-wire slave serial interface bus enables read/write access to control and status
registers within the AP0100CS.
The interface protocol uses a master/slave model in which a master controls one or
more slave devices.
Protocol
Data transfers on the two-wire serial interface bus are performed by a sequence of
low-level protocol elements, as follows:
• a start or restart condition
• a slave address/data direction byte
• a 16-bit register address
• an acknowledge or a no-acknowledge bit
• data bytes
• a stop condition
The bus is idle when both SCLK and SDATA are HIGH. Control of the bus is initiated with a
start condition, and the bus is released with a stop condition. Only the master can
generate the start and stop conditions.
The SADDR pin is used to select between two different addresses in case of conflict with
another device. If SADDR is LOW, the slave address is 0x90; if SADDR is HIGH, the slave
address is 0xBA. See Table 16 below. The user can change the slave address by changing a
register value.
Table 16:
Two-Wire Interface ID Address Switching
SADDR
Two-Wire Interface Address ID
0
1
0x90
0xBA
Start Condition
A start condition is defined as a HIGH-to-LOW transition on SDATA while SCLK is HIGH.
At the end of a transfer, the master can generate a start condition without previously
generating a stop condition; this is known as a “repeated start” or “restart” condition.
Data Transfer
Data is transferred serially, 8 bits at a time, with the MSB transmitted first. Each byte of
data is followed by an acknowledge bit or a no-acknowledge bit. This data transfer
mechanism is used for the slave address/data direction byte and for message bytes. One
data bit is transferred during each SCLK clock period. SDATA can change when SCLK is low
and must be stable while SCLK is HIGH.
AP0100CS/D Rev. 6, Pub. 1/16 EN
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AP0100CS HDR: Image Signal Processor (ISP)
Protocol
Slave Address/Data Direction Byte
Bits [7:1] of this byte represent the device slave address and bit [0] indicates the data
transfer direction. A “0” in bit [0] indicates a write, and a “1” indicates a read. The default
slave addresses used by the AP0100CS are 0x90 (write address) and 0x91 (read address).
Alternate slave addresses of 0xBA (write address) and 0xBB (read address) can be
selected by asserting the SADDR input signal.
Message Byte
Message bytes are used for sending register addresses and register write data to the slave
device and for retrieving register read data. The protocol used is outside the scope of the
two-wire serial interface specification.
Acknowledge Bit
Each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the
SCLK clock period following the data transfer. The transmitter (which is the master when
writing, or the slave when reading) releases SDATA. The receiver indicates an acknowledge bit by driving SDATA LOW. As for data transfers, SDATA can change when SCLK is
LOW and must be stable while SCLK is HIGH.
No-Acknowledge Bit
The no-acknowledge bit is generated when the receiver does not drive SDATA low during
the SCLK clock period following a data transfer. A no-acknowledge bit is used to terminate a read sequence.
Stop Condition
A stop condition is defined as a LOW-to-HIGH transition on SDATA while SCLK is HIGH.
Typical Operation
A typical READ or WRITE sequence begins by the master generating a start condition on
the bus. After the start condition, the master sends the 8-bit slave address/data direction
byte. The last bit indicates whether the request is for a READ or a WRITE, where a “0”
indicates a WRITE and a “1” indicates a READ. If the address matches the address of the
slave device, the slave device acknowledges receipt of the address by generating an
acknowledge bit on the bus.
If the request was a WRITE, the master then transfers the 16-bit register address to which
a WRITE will take place. This transfer takes place as two 8-bit sequences and the slave
sends an acknowledge bit after each sequence to indicate that the byte has been
received. The master will then transfer the 16-bit data, as two 8-bit sequences and the
slave sends an acknowledge bit after each sequence to indicate that the byte has been
received. The master stops writing by generating a (re)start or stop condition. If the
request was a READ, the master sends the 8-bit write slave address/data direction byte
and 16-bit register address, just as in the write request. The master then generates a
(re)start condition and the 8-bit read slave address/data direction byte, and clocks out
the register data, 8 bits at a time. The master generates an acknowledge bit after each 8bit transfer. The data transfer is stopped when the master sends a no-acknowledge bit.
AP0100CS/D Rev. 6, Pub. 1/16 EN
44
©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
Protocol
Single READ from Random Location
Figure 32 shows the typical READ cycle of the host to the AP0100CS. The first two bytes
sent by the host are an internal 16-bit register address. The following 2-byte READ cycle
sends the contents of the registers to host.
Figure 32:
Single READ from Random Location
Previous Reg Address, N
Slave Address
S
0 A Reg Address[15:8]
S = start condition
P = stop condition
Sr = restart condition
A = acknowledge
A = no-acknowledge
A
M+1
Reg Address, M
Reg Address[7:0]
A Sr
Slave Address
1 A
Read Data
Read Data
A
A
[15:8]
[7:0]
P
slave to master
master to slave
Single READ from Current Location
Figure 33 shows the single READ cycle without writing the address. The internal address
will use the previous address value written to the register.
Figure 33:
Single Read from Current Location
Previous Reg Address, N
S
Slave Address
Reg Address, N+1
1 A
Read Data
Read Data
A
A
[7:0]
[15:8]
P
S
Slave Address
N+2
1 A
Read Data
Read Data
A P
A
[15:8]
[7:0]
Sequential READ, Start from Random Location
This sequence (Figure 34) starts in the same way as the single READ from random location (Figure 32 on page 45). Instead of generating a no-acknowledge bit after the first
byte of data has been transferred, the master generates an acknowledge bit and
continues to perform byte READs until “L” bytes have been read.
Figure 34:
Sequential READ, Start from Random Location
Previous Reg Address, N
S
Slave Address
0 A Reg Address[15:8] A
M+1
Read Data
(15:8)
A
Read Data
(7:0)
AP0100CS/D Rev. 6, Pub. 1/16 EN
M+2
A
Read Data
(15:8)
A
Read Data
(7:0)
Reg Address, M
Reg Address[7:0] A Sr
M+L-2
M+3
A
Read Data
(15:8)
45
A
1 A
Slave Address
Read Data
(7:0)
M+1
Read Data
M+L-1
A
Read Data
(15:8)
A
A
M+L
Read Data
(7:0)
A P
©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
Protocol
Sequential READ, Start from Current Location
This sequence (Figure 35) starts in the same way as the single READ from current location (Figure 33). Instead of generating a no-acknowledge bit after the first byte of data
has been transferred, the master generates an acknowledge bit and continues to
perform byte reads until “L” bytes have been read.
Figure 35:
Sequential READ, Start from Current Location
Previous Reg Address, N
S
Slave Address
1 A
N+1
Read Data
Read Data
ReadA Data
(15:8)
(7:0)
A
Read Data
Read Data
ReadA Data
(15:8)
(7:0)
N+2
A
N+L-1
Read Data
Read Data
ReadA Data
(15:8)
(7:0)
A
Read Data
Read Data
Data
A Read
(15:8)
(7:0)
N+L
A P
Single Write to Random Location
Figure 36 shows the typical WRITE cycle from the host to the AP0100CS.The first 2 bytes
indicate a 16-bit address of the internal registers with most-significant byte first. The
following 2 bytes indicate the 16-bit data.
Figure 36:
Single WRITE to Random Location
Previous Reg Address, N
S
Slave Address
AP0100CS/D Rev. 6, Pub. 1/16 EN
0 A Reg Address[15:8]
A Reg Address[7:0]
46
Reg Address, M
A
Write Data
M+1
A P
A
©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
Protocol
Sequential WRITE, Start at Random Location
This sequence (Figure 37) starts in the same way as the single WRITE to random location
(Figure 36). Instead of generating a no-acknowledge bit after the first byte of data has
been transferred, the master generates an acknowledge bit and continues to perform
byte writes until “L” bytes have been written. The WRITE is terminated by the master
generating a stop condition.
Figure 37:
Sequential WRITE, Start at Random Location
Previous Reg Address, N
S
Slave Address
0 A Reg Address[15:8]
M+1
Write Data
(15:8)
AP0100CS/D Rev. 6, Pub. 1/16 EN
A
M+2
Write Data
(7:0)
A
Write Data
Write Data
WriteAData
(15:8)
(7:0)
A
Reg Address, M
Reg Address[7:0]
A
Write Data
M+L-2
M+3
Write Data
Write Data
WriteAData
(15:8)
(7:0)
A
A
47
M+1
A
M+L-1
A
Write Data
Write Data
WriteAData
(15:8)
(7:0)
M+L
A
P
A
©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
Protocol
Device Configuration
After power is applied and the device is out of reset (either the power on reset, hard or
soft reset), it will enter a boot sequence to configure its operating mode. There are essentially three configuration modes: Flash/EEPROM Config, Auto Config, and Host Config.
The AP0100CS firmware supports a System Configuration phase at start-up. This
consists of three sub-phases of execution:
Flash detection, then one of:
a. Flash Config
b. Auto Config
c. Host Config
The System Configuration phase is entered immediately following power-up or reset.
Then the firmware performs Flash Detection.
Flash Detection attempts to detect the presence of an SPI Flash or EEPROM device:
• If no device is detected, the firmware then samples the SPI_SDI pin state to determine
the next mode:
– If SPI_SDI is low, then it enters the Host-Config mode.
– If SPI_SDI is high, then it enters the Auto-Config mode.
• If a device is detected, the firmware switches to the Flash-Config mode.
In the Flash-Config mode, the firmware interrogates the device to determine if it
contains valid configuration records:
• If no records are detected, then the firmware enters the Auto-Config mode.
• If records are detected, the firmware processes them. By default, when all Flash
records are processed the firmware switches to the Host-Config mode. However, the
records encoded into the Flash can optionally be used to instruct the firmware to
proceed to auto-config, or to start streaming (via a Change-Config).
In the Host-Config mode, the firmware performs no configuration, and remains idle
waiting for configuration and commands from the host. The System Configuration
phase is effectively complete and the AP0100CS will take no actions until the host issues
commands.
The Auto-Config mode uses the GPIO [5..2] pins to configure the operation of the device,
such as video format and pedestal (see Table 18, “GPIO Bit Descriptions in Auto-Config,”
on page 49). After Auto-Config completes the firmware switches to the Change-Config
mode.
AP0100CS/D Rev. 6, Pub. 1/16 EN
48
©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
Protocol
Supported SPI Devices
Table 17 lists supported EEPROM/Flash devices. Devices not compatible will require a
firmware patch. Contact ON Semiconductor for additional support.
Table 17:
SPI Flash Devices
Manufacturer
Device
Type
Size
Autodetected
ManuID
Atmel
Atmel
Sanyo1
ST
ST
ST
ST
ST
ST
Microchip
Microchip
AT26DF081A
AT25DF161
LE25FW806
M25P05A
M25P16
M95040
M95020
M95010
M95M01
M25AA080
M25LC080
Flash
Flash
Flash
Flash
Flash
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
1Mbyte
2Mbyte
1Mbyte
64kbyte
2Mbyte
512byte
256byte
128byte
128kbyte
1kbyte
1kbyte
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
0x1f4501
0x1f4602
0x622662
0x202010
0x202015
0x20ffff
0x20ffff
0x20ffff
0x20ffff
0x29ffff
0x29ffff
Notes:
Table 18:
Low (“0”)
High (“1”)
AP0100CS/D Rev. 6, Pub. 1/16 EN
1. Has been obsoleted.
GPIO Bit Descriptions in Auto-Config
GPIO[5]
GPIO[4]
GPIO[3]
GPIO[2]
Normal
Vertical Flip
Normal
Horizontal mirror
NTSC
PAL
No pedestal
Pedestal
49
©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
Host Command Interface
Host Command Interface
The AP0100CS has a mechanism to write higher level commands, the Host Command
Interface (HCI). Once a command has been written through the HCI, it will be executed
by on chip firmware and the results are reported back. EEPROM or Flash memory is also
available to store commands for later execution.
Figure 38:
Interface Structure
bit
15
1
0
Addr 0x40
14
0
Host Command to FW
Response from FW
command register
door bell
bit
Addr 0xFC00
15
0
Parameter 0
cmd_handler_params_pool_0
Addr 0xFC02
cmd_handler_params_pool_1
Addr 0xFC04
cmd_handler_params_pool_2
Addr 0xFC06
cmd_handler_params_pool_3
Addr 0xFC08
cmd_handler_params_pool_4
Addr 0xFC0A
cmd_handler_params_pool_5
Addr 0xFC0C
cmd_handler_params_pool_6
Addr 0xFC0E
Parameter 7
cmd_handler_params_pool_7
Command Flow
The host issues a command by writing (through the two wire interface) to the Command
Register. All commands are encoded with bit 15 set, which automatically generates the
‘host command’ (doorbell) interrupt to the microprocessor.
Assuming initial conditions, the host first writes the command parameters (if any) to the
Parameters Pool (in the Command Handler’s shared-variable page), then writes the
command to Command Register. The firmware’s interrupt handler is invoked, which
immediately copies the Command Register contents. The interrupt handler then signals
the Command Handler task to process the command.
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AP0100CS HDR: Image Signal Processor (ISP)
Host Command Interface
If the host wishes to determine the outcome of the command, it must poll the Command
Register waiting for the doorbell bit to become cleared. This indicates that the firmware
completed processing the command. The contents of the Command Register indicate
the command’s result status. If the command generated response parameters, the host
can now retrieve these from the Parameters Pool.
The host must not write to the Parameters Pool, nor issue another command, until the
previous command completes. This is true even if the host does not care about the result
of the previous command. It is strongly recommended that the host tests that the doorbell bit is clear before issuing a command.
Synchronous Command Flow
The typical ‘flow’ for synchronous commands is:
1. The host issues a ‘request’ command to perform an operation.
2. The registered command handler is invoked, validates the command parameters,
then performs the operation. The handler returns the command result status to indicate the result of the operation.
3. The host retrieves the command result value, and any associated command response
parameters.
Asynchronous Command Flow
The typical ‘flow’ for asynchronous commands is:
1. The host issues a ‘request’ command to start an operation.
2. The registered command handler is invoked, validates and copies the command
parameters, then signals a separate task to perform the operation. The handler
returns the ENOERR return value to indicate the command was acceptable and is in
progress.
3. The host retrieves the command return value – if it is not ENOERR the host knows that
the command was not accepted and is not in progress.
4. Subsequently, the host issues an appropriate ‘get status’ command to both poll
whether the command has completed, and if so, retrieve any associated response
parameters.
5. The registered command handler is invoked, determines the state of the command
(via shared variables with the processing task), and returns either ‘EBUSY’ to indicate
the command is still in progress, or it returns the result status of the command.
6. The host must re-issue the ‘get status’ command until it does not receive the EBUSY
response.
Asynchronous commands exist to allow the Host to issue multiple commands to the
various subsystems without having to wait for each command to complete. This
prevents the host command interface from being blocked by a long-running command.
Therefore, each asynchronous command has a “Get Status” (or similar) command to
allow the Host to determine when the asynchronous command completes.
AP0100CS/D Rev. 6, Pub. 1/16 EN
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©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
Start-up Host Command Lock-out
Start-up Host Command Lock-out
The AP0100CS firmware implements an internal Host Command ‘lock’. At start-up, the
firmware obtains this lock, which prevents the Host from successfully issuing a host
command. All host commands will be rejected with EBUSY until the lock is freed.
The firmware releases the Host Command lock when it completes its start-up configuration processing. The time to do this is dependent upon the configuration mechanism. It
is recommended that the Host poll the device with the System Manager Get State
command until ENOERR is returned.
Once the host can send serial commands it should perform the following sequence.
1. POLL command_register[15] until it clears (This is called the doorbell bit).
2. Continuously issue the SYSMGR_GET_STATE command (0x8101) until the result status is not EBUSY
Below is some pseudocode that a host could use to implement the above sequence:
def systemWaitReadyFollowingReset(numRetries=10):
"""API function: waits for the system to be ready following reset (or powerup)
- first wait for the doorbell bit to clear - this indicates that the device can
accept host commands.
- then wait until the system has completed its configuration phase; the system is
ready when the SYSMGR_GET_STATE command does not return EBUSY.
- note the time for the system to be ready is dependent upon the active system
configuration mode.
- numRetries is the number of retries before timing-out
- returns result status code
"""
# Wait for doorbell bit to clear (indicates device can receive host commands)
retries = numRetries
while (0 != retries):
if (reg.COMMAND_REGISTER.DOORBELL.uncached_value == 0): break
# ready to receive
commands
retries -= 1
if (0 == retries):
# device failed to respond in time
return printError(ResultStatus.EIO, 'systemWaitReadyFollowingReset failed (doorbell
failed to clear)')
# Wait for the System Manager to complete the System Configuration phase
retries = numRetries
while (0 != retries):
res, currentState = sysmgrGetState()
if (ResultStatus.ENOERR == res): break # we're done
if (ResultStatus.EBUSY != res):
return printError(res, 'systemWaitReadyFollowingReset failed (sysmgrGetState
failed)')
retries -= 1
if (0 == retries):
# device failed to respond in time
return printError(ResultStatus.EAGAIN, 'systemWaitReadyFollowingReset failed (device
busy)')
return res
AP0100CS/D Rev. 6, Pub. 1/16 EN
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©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
Multitasking
Multitasking
The AP0100CS firmware is multitasking; therefore note that it is possible for an internally requested command to be in-progress when the Host issues a command. In these
circumstances, the Host command is immediately rejected with EBUSY. The Host
should reissue the command after a short interval.
Host Commands
Overview
The AP0100CS supports a number of functional modules or processing subsystems.
Each module or subsystem exposes commands to the host to control and configure its
operation.
Command Parameters
Command parameters are written to the Parameters Pool shared-variables by the host
prior to invoking the command. Similarly, any Command Response parameters are also
written back to the Parameters Pool by the firmware.
Result Status Codes
Table 19 shows the result status codes that are written by the Command Handler to the
Host Command register, in response to a command.
Table 19:
Result Status Codes
Value
Mnemonic
Typical Interpretation – each command may re-interpret
0x00
ENOERR
No error – command was successful
0x01
ENOENT
No such entity
0x02
EINTR
0x03
EIO
Operation interrupted
I/O failure
0x04
E2BIG
Too big
0x05
EBADF
Bad file/handle
0x06
EAGAIN
Would-block, try again
0x07
ENOMEM
Not enough memory/resource
0x08
EACCES
Permission denied
0x09
EBUSY
Entity busy, cannot support operation
0x0A
EEXIST
Entity exists
0x0B
ENODEV
Device not found
0x0C
EINVAL
Invalid argument
0x0D
ENOSPC
no space/resource to complete
0x0E
ERANGE
parameter out-of-range
0x0F
ENOSYS
operation not supported
0x10
EALREADY
already requested/exists
Note:
AP0100CS/D Rev. 6, Pub. 1/16 EN
Any unrecognized host commands will be immediately rejected by the Command Handler, with
result status code ENOSYS.
53
©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
Summary of Host Commands
Summary of Host Commands
Table 20 on page 54 through Table 31 on page 56 show summaries of the host
commands. The commands are divided into the following sections:
• System Manager
• Overlay
• GPIO
• Flash Manager
• STE
• Sequencer
• Patch Loader
• Miscellaneous
• Calibration Stats
Following is a summary of the Host Interface commands. The description gives a quick
orientation. The “Type” column shows if it is an asynchronous or synchronous
command. For a complete list of all commands including parameters, consult the Host
Command Interface Specification document.
Table 20:
System Manager Host Command
System Manager Host Command
Value
Type
Description
Set State
0x8100
Asynchronous
Request the system enter a new state
Get State
0x8101
Synchronous
Get the current state of the system
Config Power Management
0x8102
Synchronous
Configures the power state of the system
Table 21:
Overlay Host Commands
Overlay Host Command
Value
Type
Enable Overlay
0x8200
Synchronous
Description
Enable or disable the overlay subsystem
Get Overlay State
0x8201
Synchronous
Retrieves the state of the overlay subsystem
Set Calibration
0x8202
Synchronous
Set the calibration offset
Set Bitmap Property
0x8203
Synchronous
Set a property of a bitmap
Get Bitmap Property
0x8204
Synchronous
Get a property of a bitmap
Set String Property
0x8205
Synchronous
Set a property of a character string
Load Buffer
0x8206
Asynchronous
Load an overlay buffer with a bitmap (from Flash)
Load Status
0x8207
Synchronous
Retrieve status of an active load buffer operation
Write Buffer
0x8208
Synchronous
Write directly to an overlay buffer
Read Buffer
0x8209
Synchronous
Read directly from an overlay buffer
Enable Layer
0x820A
Synchronous
Enable or disable an overlay layer
Get Layer Status
0x820B
Synchronous
Retrieve the status of an overlay layer
Set String
0x820C
Synchronous
Set the character string
Get String
0x820D
Synchronous
Get the current character string
Load String
0x820E
Asynchronous
Load a character string (from Flash)
AP0100CS/D Rev. 6, Pub. 1/16 EN
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©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
Summary of Host Commands
Table 22:
STE Manager Host Commands
STE Manager Host
Command
Value
Type
Description
Config
0x8310
Synchronous
Load Config
0x8311
Asynchronous Load a configuration from SPI NVM to the configuration cache
Load Status
0x8312
Synchronous
Get status of a Load Config request
Write Config
0x8313
Synchronous
Write a configuration (via CCIS) to the configuration cache
Table 23:
Configure using the default NTSC or PAL configuration stored in ROM
GPIO Host Commands
GPIO Host Command
Value
Type
Description
Set GPIO Property
0x8400
Synchronous
Set a property of one or more GPIO pins
Get GPIO Property
0x8401
Synchronous
Retrieve a property of a GPIO pin
Set GPIO State
0x8402
Synchronous
Set the state of a GPO pin or pins
Get GPIO State
0x8403
Synchronous
Get the state of a GPI pin or pins
Set GPI Association
0x8404
Synchronous
Associate a GPI pin state with a Command Sequence stored in SPI
NVM
Get GPI Association
0x8405
Synchronous
Retrieve a GPIO pin association
Table 24:
Flash Manager Host Command
Flash Mgr Host Command
Value
Type
Get Lock
0x8500
Asynchronous
Description
Request the Flash Manager access lock
Lock Status
0x8501
Synchronous
Retrieve the status of the access lock request
Release Lock
0x8502
Synchronous
Release the Flash Manager access lock
Config
0x8503
Synchronous
Configure the Flash Manager and underlying SPI NVM subsystem
Read
0x8504
Asynchronous
Read data from the SPI NVM
Write
0x8505
Asynchronous
Write data to the SPI NVM
Erase Block
0x8506
Asynchronous
Erase a block of data from the SPI NVM
Erase Device
0x8507
Asynchronous
Erase the SPI NVM device
Query Device
0x8508
Asynchronous
Query device-specific information
Status
0x8509
Synchronous
Obtain status of current asynchronous operation
Config Device
0x850A
Synchronous
Configure the attached SPI NVM device
Type
Description
Table 25:
Sequencer Host Command
Sequencer Host Command
Value
Refresh
0x8606
Asynchronous
Refresh the automatic image processing algorithm configuration
Refresh Status
0x8607
Synchronous
Retrieve the status of the last Refresh operation
Table 26:
Patch Loader Host Command
Patch Loader Host
Command
Value
Type
Load Patch
0x8700
Asynchronous
Load a patch from SPI NVM and automatically apply
Status
0x8701
Synchronous
Get status of an active Load Patch or Apply Patch request
AP0100CS/D Rev. 6, Pub. 1/16 EN
Description
55
©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
Summary of Host Commands
Table 26:
Patch Loader Host Command
Patch Loader Host
Command
Value
Type
Apply Patch
0x8702
Asynchronous
Apply a patch (already located in Patch RAM)
Reserve RAM
0x8706
Synchronous
Reserve RAM to contain a patch
Table 27:
Description
Miscellaneous Host Command
Miscellaneous Host Command
Value
Type
Description
Invoke Command Seq
0x8900
Synchronous
Invoke a sequence of commands stored in SPI NVM
Config Command Seq Processor
0x8901
Synchronous
Configures the Command Sequence processor
Wait for Event
0x8902
Synchronous
Wait for a system event to be signalled
Table 28:
Calibration Stats Host Commands
Calibration Stats Host Command
Value
Calib Stats Control
Calib Stats Read
Table 29:
Type
Description
0x8B00
Asynchronous
Start statistics gathering
0x8B01
Synchronous
Read the results back
Event Monitor Host Command
Event Monitor Host Command
Value
Type
Event Monitor Set Association
0x8C00
Synchronous
Associate an system event with a Command Sequence stored in
NVM
Event Monitor Get Association
0x8C01
Synchronous
Retrieve an event association
Table 30:
Description
CCI Manager Host Commands
CCI Manager Host
Command
Value
Type
Description
Get Lock
0x8D00
Asynchronous
Request the CCI Manager access lock
Lock Status
0x8D01
Synchronous
Retrieve the status of the access lock request
Release Lock
0x8D02
Synchronous
Release the CCI Manager access lock
Config
0x8D03
Synchronous
Configure the CCI Manager and underlying CCI subsystem
Set Device
0x8D04
Synchronous
Set the target CCI device address
Read
0x8D05
Asynchronous
Read one or more bytes from a 16-bit address
Write
0x8D06
Asynchronous
Write one or more bytes to a 16-bit address
Write Bitfield
0x8D07
Asynchronous
Read-modify-write 16-bit data to a 16-bit address
CCI Status
0x8D08
Synchronous
Obtain status of current asynchronous operation
Table 31:
Sensor Manager Host Commands
Sensor Manager Host Command
Value
Type
Discover Sensor
0x8E00
Synchronous
Discover sensor
Initialize Sensor
0x8E01
Synchronous
Initialize attached sensor
AP0100CS/D Rev. 6, Pub. 1/16 EN
56
Description
©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
Usage Modes
Usage Modes
How a camera based on the AP0100CS will be configured depends on what features are
used. In the simplest case, an AP0100CS operating in Auto-Config mode with no
customized settings might be sufficient. A back-up camera with dynamic input from the
steering system will require a µC with a system bus interface. Flash sizes vary depending
on the register and firmware data being transferred—somewhere between 1KB to 16MB.
The two-wire bus is adequate since only high-level commands are used.
In the simplest case no EEPROM or Flash memory or µC is required, as shown in
Figure 39. This is truly a single chip operation.
Figure 39:
Auto-Config Mode
AP0100CS + image sensor
Auto-Config Mode
Analog Output
Digital Out
The AP0100CS can be configured by a serial EEPROM or Flash through the SPI Interface.
Figure 40:
Flash Mode
AP0100CS
+ image sensor
Serial
EEPROM/Flash
SPI
Figure 41:
Host Mode with Flash
AP0100CS
+ image sensor
8/16bit μC
System Bus
AP0100CS/D Rev. 6, Pub. 1/16 EN
two-wire
Serial
EEPROM/Flash
SPI
57
©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
Usage Modes
In this configuration all settings are communicated to the AP0100CS and sensor through
the microcontroller.
Figure 42:
Host Mode
8/16bit μC
System Bus
AP0100CS/D Rev. 6, Pub. 1/16 EN
AP0100CS
+ image sensor
two-wire
58
©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
Usage Modes
Caution
Table 32:
Stresses greater than those listed in Table 32 may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Absolute Maximum Ratings
Rating
AP0100CS/D Rev. 6, Pub. 1/16 EN
Parameter
Min
Max
Unit
Digital power (1.8V)
Host I/O power (2.5V,3.3V)
Sensor I/O power (1.8V, 2.8V)
Digital DAC power
PLL power
Digital core power
OTPM power (2.5V, 3.3V)
DC Input Voltage
DC Output Voltage
Storage temperature
-0.3
2.25
1.7
1.1
1.1
1.1
2.25
-0.3
-0.3
-50
4.95
5.4
5.4
2.5
2.5
2.5
5.4
VDDIO_*+0.3
VDDIO_*+0.3
150
V
V
V
V
V
V
V
V
V
°C
59
©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
Usage Modes
Table 33:
Electrical Characteristics and Operating Conditions
Parameter
Min
Typ
Max
Unit
Supply input to on-chip regulator (VDD_REG)
Condition
1.62
1.8
1.98
V
Host IO voltage (VDDIO_H)
2.25
2.5/3.3
3.6
V
Sensor IO voltage (VDDIO_S)
1.7
1.8/2.8
3.1
V
Core voltage (VDD)
1.08
1.2
1.32
V
PLL voltage (VDD_PLL)
1.08
1.2
1.32
V
DAC digital voltage (VDD_DAC)
1.08
1.2
1.32
V
DAC analog voltage (VDDA_DAC)
3
3.3
3.6
V
HiSPi PHY votlage (VDD_PHY)
2.3
2.8
3.1
V
OTPM power supply (VDDIO_OTPM)
2.25
2.5/3.3
3.6
V
Functional operating temperature
(ambient - TA)
-30
70
°C
Storage temperature
-55
150
°C
AP0100CS/D Rev. 6, Pub. 1/16 EN
60
©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
Usage Modes
Table 34:
AC Electrical Characteristics
Default Setup Conditions: fEXTCLK= 27 MHz, VDDIO_H = VDD_OTPM = 2.8V, VDD_REG = VDDIO_S = 1.8V, VDDA_DAC=3.3V,
VDD_DAC=1.2V; TA = 25°C unless otherwise stated
Symbol
Parameter
fEXTCLK
External clock frequency
Conditions
Min
Typ
6
Max
Unit
Notes
30
MHz
1
tR
External input clock rise time
10%-90% VDDIO_H
–
2
5
ns
2
tF
External input clock fall time
90%-10% VDDIO_H
–
2
5
ns
2
DEXTCLK
External input clock duty cycle
40
50
60
%
tJITTER
External input clock jitter
–
500
–
ps
Pixel clock frequency (one-clock/pixel)
6
74.125
MHz
Pixel clock frequency (two-clocks/pixel)
6
84
fPIXCLK
tRPIXCLK
Pixel clock rise time (10-90%)
CLOAD=35pf
–
2
5
ns
tFPIXCLK
Pixel clock fall time (10-90%)
CLOAD=35pf
–
2
5
ns
tPD
PIXCLK to data valid
–
1
5
ns
tPFH
PIXCLK to FV HIGH
–
1
5
ns
tPLH
PIXCLK to LV HIGH
–
1
5
ns
tPFL
PIXCLK to FV LOW
–
1
5
ns
tPLL
PIXCLK to LV LOW
–
1
5
ns
Notes:
Table 35:
1. VIH/VIL restrictions apply.
2. This is applicable only a when the PLL is bypassed. When the PLL is being used then the user should
ensure that VIH/VIL is met.
DC Electrical Characteristics
Symbol
Parameter
VIH
Input HIGH voltage
VIL
Input LOW voltage
IIN
Input leakage current
VOH
Output HIGH voltage
VOL
Output LOW voltage
Notes:
Table 36:
Condition
Min
Max
Unit
Notes
VDDIO_H or VDDIO_S *
0.8
–
–
V
1
VDDIO_H or VDDIO_S *
0.2
10
V
1
A
2
–
V
VDDIO_H or VDDIO_S *
0.2
V
VIN= 0V or VIN = VDDIO_H
or VDDIO_S
VDDIO_H or VDDIO_S*
0.80
–
1. VIL and VIH have min/max limitations specified by absolute ratings.
2. Excludes pins that have internal PU resistors.
Video DAC Electrical Characteristics
Default Setup Conditions: fEXTCLK= 27 MHz, VDDIO_H = VDD_OTPM = 2.8V, VDD_REG = VDDIO_S = 1.8V,
VDDA_DAC=3.3V, VDD_DAC=1.2V; TA = 25°C unless otherwise stated
Parameter
Symbol
Min
Typ
Max
Unit
Comments
DC Accuracy
Differential Nonlinearity
DNL
±1
LSB
Integral Nonlinearity
INL
±3
LSB
Load Capacitance
AP0100CS/D Rev. 6, Pub. 1/16 EN
CLOAD
10
61
pF
At maximum output current
©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
Usage Modes
Table 36:
Video DAC Electrical Characteristics
Default Setup Conditions: fEXTCLK= 27 MHz, VDDIO_H = VDD_OTPM = 2.8V, VDD_REG = VDDIO_S = 1.8V,
VDDA_DAC=3.3V, VDD_DAC=1.2V; TA = 25°C unless otherwise stated
Parameter
Symbol
Offset Error
OER
Gain Error
Absolute Gain Error
Figure 43:
Min
Typ
Max
Unit
Comments
±1
% FS
For differental output only
DGER
±2
% FS
GER
±5
% FS
Frame_Sync (Interlaced Operation) Diagram
Table 37:
AP0100CS/D Rev. 6, Pub. 1/16 EN
Frame_Sync (Interlaced Operation) Parameters
Parameter
Name
Conditions
Min
Typ
Max Unit
T_FRAME_SYNC
T_FRAME_SYNC
T_RESYNC
T_RESYNC
NTSC
100
ms
T_RESYNC
T_RESYNC
PAL
120
ms
3
62
EXTCLK cycles
©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
Usage Modes
Figure 44:
Frame_Sync (Progressive Operation) Diagram
Table 38:
Trigger Timing
Parameter
Name
FRAME_SYNC to FV_OUT
tFRMSYNC_FVH
FRAME_SYNC to
TRIGGER_OUT
tFRAME_SYNC
AP0100CS/D Rev. 6, Pub. 1/16 EN
Conditions
Min
Typ
Max
Unit
–
–
Lines
tTRIGGER_PROP
8 lines+ exposure
time + sensor delay
–
–
9
ns
tFRAMESYNC
3
–
–
EXTCLK cycles
63
©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
Usage Modes
NTSC Signal Parameters
Table 39:
NTSC Signal Parameters
Default Setup Conditions: fEXTCLK= 27 MHz, VDD_REG = 1.8V, VDD_IO_S = 1.8V, VDDA_DAC= 3.3V,
VDDIO_OTPM=2.5V, VDD_PHY = 2.5V
Parameter
Min
Typ
Max
Units
Line Frequency
15734.25
15734.27
15734.28
Hz
Field Frequency
59.94
59.94
59.94
Hz
Sync Rise Time
111
148
222
ns
Sync Fall Time
111
148
222
ns
Sync Width
4.60
4.74
4.80
s
Notes
Sync Level
39
40
41
IRE
2
Burst Level
36
40
44
IRE
2
Sync to Setup
(with pedestal off)
9.2
9.5
10.3
s
Sync to Burst Start
4.71
5.3
5.71
s
Front Porch
1.27
1.7
2.22
s
Black Level
5
7.5
10
IRE
1, 2, 3
White Level
90
100
110
IRE
1, 2, 3
Notes:
AP0100CS/D Rev. 6, Pub. 1/16 EN
1. Black and white levels are referenced to the blanking level.
2. NTSC convention standardized by the IRE (1 IRE = 7.14mV).
3. DAC ref = 3.74k, load = 37.5
64
©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
Usage Modes
Figure 45:
Video Timing
A
D
E
C
B
J
F
K
H
Table 40:
A
B
C
D
E
F
G
H
AP0100CS/D Rev. 6, Pub. 1/16 EN
G
H
Video Timing: Specification from Rec. ITU-R BT.470
Signal
NTSC
27 MHz
PAL
27 MHz
Units
H Period
Hsync to burst
burst
Hsync to Signal
Video Signal
Front
Hsync Period
Sync rising/falling edge
63.556
4.71 to 5.71
2.23 to 3.11
9.20 to 10.30
2.655 ±0.20
1.27 to 2.22
4.70 ± 0.10
0.25
64.00
5.60 ± 0.10
2.25 ± 0.23
10.20 ± 0.30
52 +0, -0.3
1.5 +0.3, -0.0
4.70 ± 0.20
0.20 ±0.10
s
s
s
s
s
s
s
s
65
©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
Usage Modes
Figure 46:
Equalizing Pulse
L
I
J
K
Table 41:
I
J
K
L
AP0100CS/D Rev. 6, Pub. 1/16 EN
K
Equalizing Pulse: Specification from Rec. ITU-R BT.470
Signal
NTSC
27 MHz
H/2 Period
Pulse width
Pulse rising/falling edge
Signal to pulse
31.778
2.30 ± 0.10
0.25
1.50 ± 0.10
66
PAL
27 MHz
32.00
2.35 ± 0.10
0.25 ± 0.05
3.0 ± 2.0
Units
s
s
s
s
©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
Usage Modes
Figure 47:
V Pulse
M
O
N
P
Table 42:
M
N
O
P
Table 43:
P
V Pulse: Specification from Rec. ITU-R BT.470
Signal
NTSC
27 MHz
PAL
27 MHz
Units
H/2 Period
Pulse width
V pulse interval
Pulse rising/falling edge
31.778
27.10 (nominal)
4.70 ± 0.10
0.25
32.00
27.30 ± 0.10
4.70 ± 0.10
0.25 ± 0.05
s
s
s
s
Standby Current Consumption
Default Setup Conditions: fEXTCLK = 27 MHz, VDD_REG=1.8V; VDDIO_H not included in measurement
VDDIO_S= 1.8V, VDDA_DAC=3.3V, VDDIO_OTPM=2.5V, VDD_PHY=2.5V, TA = 70°C unless otherwise stated
Parameter
Condition
Total standby current when asserting the STANDBY signal
fEXTCLK = 27 MHz
Total standby current
AP0100CS/D Rev. 6, Pub. 1/16 EN
67
Typ
3.2
6.9
3.5
7.6
Max
Unit
mA
mW
mA
mW
©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
Usage Modes
Table 44:
Operating Current Consumption
Default Setup Conditions: fEXTCLK = 27 MHz, VDD_REG=1.8V; VDDIO_H not included in measurement
VDDIO_S= 1.8V, VDDA_DAC=3.3V, VDDIO_OTPM=2.5V, VDD_PHY=2.5V, TA = 70°C unless otherwise stated
Symbol
Conditions
Min
Typ
Max
Unit
VDD_REG
1.62
1.8
1.98
V
VDDIO_H=2.5V
2.25
2.5
2.75
V
VDDIO_H=3.3V
3
3.3
3.6
V
VDDIO_S=1.8V
1.7
1.8
1.9
V
VDDIO_S=2.8V
2.5
2.8
3.1
V
VDDIO_OTPM=2.5V
2.25
2.5
2.75
V
VDDIO_OTPM=3.3V
3
3.3
3.6
V
VDDA_DAC
3
3.3
3.6
V
2.8
3.1
VDD_PHY
2.3
IDD_REG
IDDIO_S
IDDIO_OTPM
mA
NTSC HiSPi 14-bit
63.6
mA
NTSC
64.1
mA
PAL
59.5
mA
NTSC HiSPi 12-bit
3.2
mA
NTSC HiSPi 14-bit
3.2
mA
NTSC
3.3
mA
PAL
3.3
mA
NTSC HiSPi 12-bit
0.1
mA
NTSC HiSPi 14-bit
0.1
mA
NTSC
0.1
mA
0.1
mA
NTSC HiSPi 12-bit
1, 2
19.54
mA
NTSC HiSPi 14-bit
1, 2
19.54
mA
NTSC
1, 2
19.54
mA
PAL
1, 2
19.54
mA
NTSC HiSPi 12-bit
0.3
mA
NTSC HiSPi 14-bit
0.3
mA
NTSC
0.0
mA
PAL
IDD_PHY
Total power consumption
Notes:
AP0100CS/D Rev. 6, Pub. 1/16 EN
63.7
PAL
IDDA_DAC
V
NTSC HiSPi 12-bit
0.0
mA
NTSC HiSPi 12-bit
185.66
mW
NTSC HiSPi 14-bit
185.56
mW
NTSC
185.56
mW
PAL
177.46
mW
1. R_DAC_POS=75, R_DAC_NEG=37.5, R_DAC_REF= 3.74k
2. . Current in single ended mode. When in differential mode the current will be 37.9mA.
68
©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
Usage Modes
Table 45:
AP0100CS/D Rev. 6, Pub. 1/16 EN
Inrush Current
Supply
Voltage
Max Current
(mA)
AVDD
VDDIO_H
VDDIO_S
VDDIO_S
VDDA_DAC
VDDIO_OTPM
1.8
2.5/3.3
1.8
2.8
3.3
2.5/3.3
240
260
15
55
270
180
69
©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
Two-Wire Serial Register Interface
Two-Wire Serial Register Interface
The electrical characteristics of the two-wire serial register interface (SCLK, SDATA) are
shown in Figure 48 and Table 46.
Figure 48:
Slave Two Wire Serial Bus Timing Parameters (CCIS)
SDATA
tLOW
tf
tSU;DAT
tr
tf
tHD;STA
tr
tBUF
SCLK
tHD;STA
S
Table 46:
tHD;DAT
tHIGH
tSU;STA
tSU;STO
Sr
P
S
Slave Two-Wire Serial Bus Characteristics (CCIS)
Default Setup Conditions: fEXTCLK = 27 MHz; VDDIO_H = VDD_OTPM = 2.8V; VDD_REG = VDDIO_S = 1.8V; VDDA_DAC=
3.3V; VDD_DAC = 1.2V; TA = 25°C unless otherwise stated
Standard-Mode
Parameter
SCLK Clock Frequency
Fast-Mode
Symbol
Min
Max
Min
Max
Unit
fSCL
0
100
0
400
KHz
tHD;STA
4.0
-
0.6
-
s
tLOW
4.7
-
1.3
-
s
Hold time (repeated) START condition.
After this period, the first clock pulse is generated
LOW period of the SCLK clock
tHIGH
4.0
-
0.6
-
s
tSU;STA
4.7
-
0.6
-
s
Data hold time
tHD;DAT
02
3.453
0
0.93
s
Data set-up time
tSU;DAT
250
-
100
-
ns
HIGH period of the SCLK clock
Set-up time for a repeated START condition
Rise time of both SDATA and SCLK signals (10-90%)
tr
-
1000
20 + 0.1Cb4
300
ns
Fall time of both SDATA and SCLK signals (10-90%)
tf
-
300
20 + 0.1Cb4
300
ns
tSU;STO
4.0
-
0.6
-
s
Bus free time between a STOP and START
condition
tBUF
4.7
-
1.3
-
s
Capacitive load for each bus line
Cb
-
400
-
400
pF
Set-up time for STOP condition
Serial interface input pin capacitance
SDATA max load capacitance
SDATA pull-up resistor
Notes:
CIN_SI
-
3.3
-
3.3
pF
CLOAD_SD
-
30
-
30
pF
RSD
1.5
4.7
1.5
4.7
K
1. All values referred to VIHmin = 0.9 VDD and VILmax = 0.1VDD levels. EXCLK = 27 MHz.
2. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the
undefined region of the falling edge of SCLK.
3. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of
the SCLK signal.
4. Cb = total capacitance of one bus line in pF.
The electrical characteristics of the master two-wire serial register interface (M_SCLK,
M_SDATA) are shown in Figure 49 and Table 47.
AP0100CS/D Rev. 6, Pub. 1/16 EN
70
©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
Two-Wire Serial Register Interface
Figure 49:
Master Two Wire Serial Bus Timing Parameters (CCIM)
SDATA
tLOW
tf
tSU;DAT
tr
tf
tHD;STA
tr
tBUF
SCLK
S
Table 47:
tHD;STA
tHD;DAT
tHIGH
tSU;STA
tSU;STO
Sr
P
S
Master Two-Wire Serial Bus Characteristics (CCIM)
Default Setup Conditions: fEXTCLK = 27 MHz; VDDIO_H = VDD_OTPM = 2.8V; VDD_REG = VDDIO_S = 1.8V; VDDA_DAC=
3.3V; VDD_DAC = 1.2V; TA = 25°C unless otherwise stated
Standard-Mode
Parameter
M_SCLK Clock Frequency
Fast-Mode
Symbol
Min
Max
Min
Max
Unit
fSCL
0
100
0
400
KHz
tHD;STA
4.0
-
0.6
-
s
tLOW
4.7
-
1.2
-
s
Hold time (repeated) START condition.
After this period, the first clock pulse is generated
LOW period of the M_SCLK clock
tHIGH
4.0
-
0.6
-
s
tSU;STA
4.7
-
0.6
-
s
Data hold time
tHD;DAT
02
3.453
0
0.93
s
Data set-up time
tSU;DAT
250
-
100
-
ns
300
ns
300
ns
HIGH period of the M_SCLK clock
Set-up time for a repeated START condition
Rise time of both M_SDATA and M_SCLK time (10-90%)
tr
-
1000
20 + 0.1Cb4
Fall time of both M_SDATA and M_SCLK time (10-90%)
tf
-
300
20 + 0.1Cb4
tSU;STO
4.0
-
0.6
-
s
tBUF
4.7
-
1.3
-
s
Cb
-
400
-
400
pF
CIN_SI
-
3.3
-
3.3
pF
Set-up time for STOP condition
Bus free time between a STOP and START condition
Capacitive load for each bus line
Serial interface input pin capacitance
M_SDATA max load capacitance
M_SDATA pull-up resistor
Notes:
AP0100CS/D Rev. 6, Pub. 1/16 EN
CLOAD_SD
-
30
-
30
pF
RSD
1.5
4.7
1.5
4.7
K
1. All values referred to VIHmin = 0.9 VDD and VILmax = 0.1VDD levels. EXCLK = 27 MHz.
2. A device must internally provide a hold time of at least 300 ns for the M_SDATA signal to bridge the
undefined region of the falling edge of M_SCLK.
3. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of
the M_SCLK signal.
4. Cb = total capacitance of one bus line in pF.
71
©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
Package Diagram
Package Diagram
Figure 50:
Package Diagram
VFBGA100 7x7
CASE 138AH
ISSUE O
DATE 30 DEC 2014
AP0100CS/D Rev. 6, Pub. 1/16 EN
72
©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
Package Diagram
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AP0100CS/D Rev. 6, Pub. 1/16 EN
73
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