CAT1320, CAT1321 H EE GEN FR ALO Supervisory Circuits with I2C Serial 32K CMOS EEPROM LE A D F R E ETM FEATURES ■ 3.0V to 5.5V operation ■ Precision power supply voltage monitor ■ Low power CMOS technology — 5V, 3.3V and 3V systems ■ 64-Byte page write buffer - +5.0V (+/- 5%, +/- 10%) - +3.3V (+/- 5%, +/- 10%) - +3.0V (+/- 10%) ■ 1,000,000 Program/Erase cycles ■ 100 year data retention ■ Active low reset, CAT1320 ■ 8-pin DIP, SOIC, TSSOP and TDFN packages ■ Active high reset, CAT1321 ■ Industrial temperature range ■ Valid reset guaranteed at VCC=1V ■ 400kHz I2C bus DESCRIPTION The CAT1320 and CAT1321 are complete memory and supervisory solutions for microcontroller-based systems. A 32kbit serial EEPROM memory and a system power supervisor with brown-out protection are integrated together in low power CMOS technology. Memory interface is via a 400kHz I2C bus. active, preventing the system microcontroller, ASIC or peripherals from operating. Reset signals become inactive typically 200 ms after the supply voltage exceeds the reset threshold level. With both active high and low reset options, interface to microcontrollers and other ICs is simple. In addition, the RESET (CAT1320) pin can be used as an input for push-button manual reset capability. The CAT1320 provides a precision VCC sense circuit and drives an open drain output, RESET low whenever The CAT1320/21 memory features a 64-byte page. In addition, hardware data protection is provided by a VCC VCC falls below the reset threshold voltage. sense circuit that prevents writes to memory whenever VCC The CAT1321 provides a precision VCC sense circuit falls below the reset threshold or until VCC reaches the reset that drives an open drain output, RESET high whenever threshold during power up. VCC falls below the reset threshold voltage. Available packages include an 8-pin DIP, SOIC, TSSOP The power supply monitor and reset circuit protect and 4.9 x 3mm TDFN. memory and system controllers during power up/down and against brownout conditions. Five reset threshold voltages support 5V, 3.3V and 3V systems. If power supply voltages are out of tolerance reset signals become PIN CONFIGURATION PDIP (L) SOIC (W) TDFN PACKAGE: 4.9MM X 3MM (ZD2) TSSOP (Y) 8 VCC 7 RESET A0 1 A1 2 6 SCL A2 3 6 SCL A2 3 VSS 4 5 SDA VSS 4 5 SDA VSS A0 1 8 VCC A0 1 7 RESET A1 2 8 VCC 7 RESET A2 3 6 SCL A2 3 VSS 4 5 SDA VSS 4 A0 1 A1 2 CAT1320 A2 3 A1 2 CAT1321 8 VCC 7 RESET A0 1 © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice. A1 2 CAT1320 CAT1321 1 8 VCC 7 RESET 6 SCL 4 5 SDA A0 1 8 VCC A1 2 7 RESET 6 SCL A2 3 6 SCL 5 SDA VSS 4 5 SDA CAT1320 CAT1321 Doc. No. MD-3014, Rev. D CAT1320, CAT1321 Threshold Voltage Options BLOCK DIAGRAM — CAT1320, CAT1321 Part Dash Minimum Number Threshold EXTERNAL LOAD SENSE AMPS SHIFT REGISTERS DOUT ACK VCC WORD ADDRESS BUFFERS VSS COLUMN DECODERS START/STOP LOGIC SDA 32kbit EEPROM XDEC Maximum Threshold -45 4.50 4.75 -42 4.25 4.50 -30 3.00 3.15 -28 2.85 3.00 -25 2.55 2.70 OPERATING TEMPERATURE RANGE CONTROL LOGIC Industrial -40˚C to 85˚C DATA IN STORAGE HIGH VOLTAGE/ TIMING CONTROL RESET Controller Precision Vcc Monitor STATE COUNTERS SCL SLAVE ADDRESS COMPARATORS A0 A1 A2 RESET (CAT1320) RESET (CAT1321) PIN FUNCTIONS Pin Name RESET Function Active Low Reset Input/Output (CAT1320) VSS Ground SDA Serial Data/Address SCL Clock Input RESET VCC Active High Reset Output (CAT1321) Power Supply PIN DESCRIPTION RESET RESET/RESET RESET: RESET OUTPUTS These are open-drain pins and RESET can also be used as a manual reset trigger input. By forcing a reset condition on the pin the device will initiate and maintain a reset condition. The RESET pin must be connected through a pull-down resistor and the RESET pin must be connected through a pull-up resistor. SCL: SERIAL CLOCK Serial clock input. A0, A1, A2: DEVICE ADDRESS INPUTS When hardwired, up to eight CAT1320/21 devices may be addressed on a single bus system (refer to Device Addressing). When the pins are left unconnected, the default values are zeros. SDA: SERIAL DATA ADDRESS The bidirectional serial data/address pin is used to transfer all data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs. Doc. No. MD-3014, Rev. D 2 © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice. CAT1320, CAT1321 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Temperature Under Bias .................... -40°C to +85°C Storage Temperature ........................ -65°C to +105°C Voltage on any Pin with Respect to Ground(1) ............. -0.5V to +VCC +2.0V Note: (1) Output shorted for no more than one second. No more than one output shorted at a time. VCC with Respect to Ground ................ -0.5V to +7.0V Package Power Dissipation Capability (TA = 25°C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300°C Output Short Circuit Current(1) ........................ 100 mA D.C. OPERATING CHARACTERISTICS VCC = +3.0V to +5.5V and over the recommended temperature conditions unless otherwise specified. Symbol Parameter Test Conditions Min ILI Input Leakage Current VIN = GND to Vcc ILO Output Leakage Current VIN = GND to Vcc ICC1 Power Supply Current (Write) ICC2 Max Units -2 10 µA -10 10 µA fSCL = 400kHz VCC = 5.5V 3 mA Power Supply Current (Read) fSCL = 400kHz VCC = 5.5V 1 mA ISB Standby Current Vcc = 5.5V, VIN = GND or Vcc 40 µA VIL2 Input Low Voltage -0.5 0.3 x Vcc V VIH 2 Input High Voltage 0.7 x Vcc Vcc + 0.5 V VOL Output Low Voltage (SDA, RESET) IOL = 3mA VCC = 3.0V 0.4 V VOH Output High Voltage (RESET) IOH = -0.4mA VCC = 3.0V Vcc 0.75 CAT132x-45 (VCC = 5V) 4.50 4.75 CAT132x-42 (VCC = 5V) 4.25 4.50 CAT132x-30 (VCC = 3.3V) 3.00 3.15 CAT132x-28 (VCC = 3.3V) 2.85 3.00 CAT132x-25 (VCC = 3V) 2.55 2.70 VTH Reset Threshold Typ V V VRVALID1 Reset Output Valid VCC Voltage 1.00 V VRT1 Reset Threshold Hysteresis 15 mV Notes: 1. This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested. 2. VIL min and VIH max are reference values only and are not tested. © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice. 3 Doc No. MD-3014, Rev. D CAT1320, CAT1321 CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V Symbol COUT (1) Test Test Conditions Max Units VOUT = 0V 8 pF VIN = 0V 6 pF Output Capacitance CIN(1) Input Capacitance A.C. CHARACTERISTICS VCC = 3.0V to 5.5V and over the recommended temperature conditions, unless otherwise specified. Memory Read & Write Cycle2 Symbol Parameter fSCL Max Units Clock Frequency 400 kHz tSP1 Input Filter Spike Suppression (SDA, SCL) 100 ns tLOW Clock Low Period 1.3 µs tHIGH Clock High Period 0.6 µs 1 Min tR SDA and SCL Rise Time 300 ns tF1 SDA and SCL Fall Time 300 ns tHD;STA Start Condition Hold Time 0.6 µs tSU;STA Start Condition Setup Time (for a Repeated Start) 0.6 µs tHD;DAT Data Input Hold Time 0 ns tSU;DAT Data Input Setup Time 100 ns tSU;STO Stop Condition Setup Time 0.6 µs tAA SCL Low to Data Out Valid tDH Data Out Hold Time 50 ns tBUF1 Time the Bus must be Free Before a New Transmission Can Start 1.3 µs tWC3 Write Cycle Time (Byte or Page) 900 5 ns ms Notes: 1. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested. 2. Test Conditions according to “AC Test Conditions” table. 3. The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address. Doc. No. MD-3014, Rev. D 4 © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice. CAT1320, CAT1321 RESET CIRCUIT A.C. CHARACTERISTICS Symbol Parameter Test Conditions Min Ty p Max Units tPURST Reset Timeout Note 2 130 200 270 ms tRPD VTH to RESET output Delay Note 3 5 µs tGLITCH VCC Glitch Reject Pulse Width Note 4, 5 30 ns MR Glitch Manual Reset Glitch Immunity Note 5 100 ns tMRW MR Pulse Width Note 5 5 Test Conditions Min µs POWER-UP TIMING5,6 Symbol Parameter tPUR tPUW Ty p Max Units Power-Up to Read Operation 270 ms Power-Up to Write Operation 270 ms Notes: 1. Test Conditions according to “AC Test Conditions” table. 2. Power-up, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table 3. Power-Down, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table 4. VCC Glitch Reference Voltage = VTHmin; Based on characterization data 5. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested. 6. tPUR and tPUW are the delays required from the time VCC is stable until the specified memory operation can be initiated. AC TEST CONDITIONS Input pulse voltages 0.2VCC to 0.8VCC Input rise and fall times 10 n s Input reference voltages 0.3VCC, 0.7VCC Output reference voltages 0.5VCC Output Load Current Source: IOL = 3mA; CL = 100pF RELIABILITY CHARACTERISTICS Symbol NEND (1) Parameter Reference Test Method Min Max Units Endurance MIL-STD-883, Test Method 1033 1,000,000 Data Retention MIL-STD-883, Test Method 1008 100 Years VZAP ESD Susceptibility MIL-STD-883, Test Method 3015 2000 Volts ILTH(1)(2) Latch-Up JEDEC Standard 17 100 mA TDR(1) (1) Cycles/Byte Notes: 1. This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested. 2. Latch-up protection is provided for stresses up to 100mA on input and output pins from -1V to VCC + 1V. © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice. 5 Doc No. MD-3014, Rev. D CAT1320, CAT1321 DEVICE OPERATION Reset Controller Description The CAT1320/21 precision Reset controllers ensure correct system operation during brownout and power up/down conditions. They are configured with opendrain RESET/RESET outputs. When RESET I/O is driven to the active state, the 200 msec timer will begin to time the reset interval. If external reset is shorter than 200 ms, Reset outputs will remain active at least 200 ms. During power-up, the RESET/RESET output remains active until VCC reaches the VTH threshold and will continue driving the outputs for approximately 200ms (tPURST) after reaching VTH. After the tPURST timeout interval, the device will cease to drive the reset output. At this point the reset output will be pulled up or down by their respective pull up/down resistors. Glitches shorter than 100 ns on RESET input will not generate a reset pulse. Hardware Data Protection The CAT1320/21 family has been designed to solve many of the data corruption issues that have long been associated with serial EEPROMs. Data corruption occurs when incorrect data is stored in a memory location which is assumed to hold correct data. During power-down, the RESET/RESET output will be active when VCC falls below VTH. The RESET/RESET output will be valid so long as VCC is >1.0V (VRVALID). The device is designed to ignore the fast negative going VCC transient pulses (glitches). Whenever the device is in a Reset condition, the embedded EEPROM is disabled for all operations, including write operations. If the Reset output is active, in progress communications to the EEPROM are aborted and no new communications are allowed. In this condition an internal write cycle to the memory can not be started, but an in progress internal non-volatile memory write cycle can not be aborted. An internal write cycle initiated before the Reset condition can be successfully finished if there is enough time (5ms) before VCC reaches the minimum value of 2V. Reset output timing is shown in Figure 1. Manual Reset Operation The RESET pin can operate as reset output and manual reset input. The input is edge triggered; that is, the RESET input will initiate a reset timeout after detecting a high to low transition. Figure 1. RESET/RESET Output Timing t GLITCH VTH VRVALID VCC t PURST t RPD t PURST t RPD RESET RESET Doc. No. MD-3014, Rev. D 6 © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice. CAT1320, CAT1321 Figure 2. RESET as Manual Reset Input Operation and Timing t MRW RESET (Input) t PURST RESET (Output) Figure 3. Bus Timing tF tHIGH tLOW tR tLOW SCL tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO SDA IN tAA tDH tBUF SDA OUT © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice. 7 Doc No. MD-3014, Rev. D CAT1320, CAT1321 EMBEDDED EEPROM OPERATION SDA when SCL is HIGH. The CAT1320/21 monitors the SDA and SCL lines and will not respond until this condition is met. The CAT1320 and CAT1321 feature a 32kbit embedded serial EEPROM that supports the I2C Bus data transmission protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. The transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. Both the Master device and Slave device can operate as either transmitter or receiver, but the Master device controls which mode is activated. STOP Condition A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition. DEVICE ADDRESSING The Master begins a transmission by sending a START condition. The Master sends the address of the particular slave device it is requesting. The four most significant bits of the 8-bit slave address are programmable in metal and the default is 1010. I2C Bus Protocol The features of the I2C bus protocol are defined as follows: (1) Data transfer may be initiated only when the bus is not busy. The last bit of the slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected. (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition. After the Master sends a START condition and the slave address byte, the CAT1320/21 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT1320/21 then performs a Read or Write operation depending on the R/W bit. START Condition The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of Figure 4. Write Cycle Timing SCL SDA 8TH BIT BYTE n ACK tWR STOP CONDITION Doc. No. MD-3014, Rev. D 8 START CONDITION ADDRESS © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice. CAT1320, CAT1321 ACKNOWLEDGE WRITE OPERATIONS After a successful data transfer, each receiving device is required to generate an acknowledge. The acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. Byte Write In the Byte Write mode, the Master device sends the START condition and the slave address information (with the R/W bit set to zero) to the Slave device. After the Slave generates an acknowledge, the Master sends two 8-bit address bytes that are to be written into the address pointers of the device. After receiving another acknowledge from the Slave, the Master device transmits the data to be written into the addressed memory location. The CAT1320/ 21 acknowledges once more and the Master generates the STOP condition. At this time, the device begins an internal programming cycle to non-volatile memory. While the cycle is in progress, the device will not respond to any request from the Master device. The CAT1320/21 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8bit byte. When the CAT1320/21 begins a READ mode it transmits 8 bits of data, releases the SDA line and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT1320/21 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. Figure 5. Start/Stop Timing SDA SCL START BIT STOP BIT Figure 6. Acknowledge Timing SCL FROM MASTER 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE Figure 7. Slave Address Bits Default Configuration CAT © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice. 1 0 1 0 A2 A1 9 A0 R/W Doc No. MD-3014, Rev. D CAT1320, CAT1321 Page Write The CAT1320/21 writes up to 64 bytes of data in a single write cycle, using the Page Write operation. The page write operation is initiated in the same manner as the byte write operation, however instead of terminating after the initial byte is transmitted, the Master is allowed to send up to additional 63 bytes. After each byte has been transmitted, the CAT1320/21 will respond with an acknowledge and internally increment the lower order address bits by one. The high order bits remain unchanged. If the Master transmits more than 64 bytes before sending the STOP condition, the address counter ‘wraps around,’ and previously transmitted data will be overwritten. When all 64 bytes are received, and the STOP condition has been sent by the Master, the internal programming cycle begins. At this point, all received data is written to the CAT1320/21 in a single write cycle. Figure 8. Byte Write Timing BUS ACTIVITY: MASTER SDA LINE S T A R T SLAVE ADDRESS BYTE ADDRESS A15–A8 A7–A0 S A C K S T O P DATA P ** * * A C K A C K A C K *=Don’t Care Bit Figure 9. Page Write Timing BUS ACTIVITY: MASTER SDA LINE S T A R T SLAVE ADDRESS BYTE ADDRESS A15–A8 A7–A0 S DATA DATA n S T O P DATA n+63 P **** A C K A C K A C K A C K A C K A C K A C K *=Don’t Care Bit Doc. No. MD-3014, Rev. D 10 © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice. CAT1320, CAT1321 Acknowledge Polling Read Operations Disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host’s write opration, the CAT1320/21 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the device is still busy with the write operation, no ACK will be returned. If a write operation has completed, an ACK will be returned and the host can then proceed with the next read or write operation. The READ operation for the CAT1320/21 is initiated in the same manner as the write operation with one exception, that R/W bit is set to one. Three different READ operations are possible: Immediate/Current Address READ, Selective/Random READ and Sequential READ. Figure 10. Immediate Address Read Timing BUS ACTIVITY: MASTER SDA LINE S T A R T S T O P SLAVE ADDRESS S P A C K DATA N O A C K SCL SDA 8 9 8TH BIT DATA OUT © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice. NO ACK 11 STOP Doc No. MD-3014, Rev. D CAT1320, CAT1321 Immediate/Current Address Read Sequential Read The CAT1320 and CAT1321 address counter contains the address of the last byte accessed, incremented by one. In other words, if the last READ or WRITE access was to address N, the READ immediately following would access data from address N+1. For all devices, N=E=4,095. The counter will wrap around to Zero and continue to clock out valid data. After the CAT1320 and CAT1321 receives its slave address information (with the R/W bit set to one), it issues an acknowledge, then transmits the 8-bit byte requested. The master device does not send an acknowledge, but will generate a STOP condition. The Sequential READ operation can be initiated by either the Immediate Address READ or Selective READ operations. After the CAT1320 and CAT1321 sends the inital 8-bit byte requested, the Master will responds with an acknowledge which tells the device it requires more data. The CAT1320 and CAT1321 will continue to output an 8-bit byte for each acknowledge, thus sending the STOP condition. The data being transmitted from the CAT1320 and CAT1321 is sent sequentially with the data from address N followed by data from address N+1. The READ operation address counter increments all of the CAT1320 and CAT1321 address bits so that the entire memory array can be read during one operation. Selective/Random Read Selective/Random READ operations allow the Master device to select at random any memory location for a READ operation. The Master device first performs a ‘dummy’ write operation by sending the START condition, slave address and byte addresses of the location it wishes to read. After the CAT1320 and CAT1321 acknowledges, the Master device sends the START condition and the slave address again, this time with the R/W bit set to one. The CAT1320 and CAT1321 then responds with its acknowledge and sends the 8-bit byte requested. The master device does not send an acknowledge but will generate a STOP condition. Figure 11. Selective Read Timing S T A R T BUS ACTIVITY: MASTER SDA LINE SLAVE ADDRESS S T A R T BYTE ADDRESS A15–A8 A7–A0 **** S SLAVE ADDRESS S T O P DATA S A C K A C K P A C K A C K N O A C K *=Don’t Care Bit Figure 12. Sequential Read Timing BUS ACTIVITY: MASTER SLAVE ADDRESS DATA n DATA n+1 DATA n+2 S T O P DATA n+x SDA LINE P A C K A C K A C K A C K N O A C K Doc. No. MD-3014, Rev. D 12 © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice. CAT1320, CAT1321 PACKAGE OUTLINE DRAWINGS PDIP 8-Lead 300mils (L) SYMBOL MIN NOM A A1 E1 5.33 0.38 A2 2.92 3.30 b 0.36 0.46 0.56 b2 1.14 1.52 1.78 4.95 c 0.20 0.25 0.36 D 9.02 9.27 10.16 E 7.62 7.87 8.25 e PIN # 1 IDENTIFICATION MAX 2.54 BSC E1 6.10 eB 7.87 L 2.92 6.35 7.11 10.92 3.30 3.80 D TOP VIEW E A2 A A1 c b2 L e eB b SIDE VIEW END VIEW Notes: 1. Al dimensions are in millimeters. Angles in degrees. 2. Complies with JEDEC standard MS-001. © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice. 13 Doc No. MD-3014, Rev. D CAT1320, CAT1321 SOIC 8-Lead 150mils (W) E1 E SYMBOL MIN A 1.35 A1 0.10 0.25 b 0.33 0.51 MAX 0.25 1.75 c 0.19 D 4.80 5.00 E 5.80 6.20 E1 3.80 e PIN # 1 IDENTIFICATION NOM 4.00 1.27 BSC h 0.25 0.50 L 0.40 1.27 θ 0º 8º TOP VIEW D h A1 θ A c e b L SIDE VIEW END VIEW Notes: 1. Al dimensions are in millimeters. Angles in degrees. 2. Complies with JEDEC standard MS-012. Doc. No. MD-3014, Rev. D 14 © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice. CAT1320, CAT1321 TSSOP 8-Lead 4.4mm (Y) b SYMBOL MIN NOM A E1 E MAX 1.20 A1 0.05 A2 0.80 b 0.19 c 0.09 D 2.90 0.15 0.90 1.05 0.30 0.20 3.00 3.10 E 6.30 6.40 6.50 E1 4.30 4.40 4.50 e 0.65 BSC L 1.00 REF L1 0.50 θ1 0° 0.60 0.75 8° e TOP VIEW D A2 A A1 c θ1 L1 SIDE VIEW L END VIEW Notes: 1. Al dimensions are in millimeters. Angles in degrees. 2. Complies with JEDEC standard MS-153. © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice. 15 Doc No. MD-3014, Rev. D CAT1320, CAT1321 TDFN-S-MSOP 8-Pad 3 x 4.9mm (ZD2) D A DETAIL A DAP SIZE 2.6 x 3.3mm E E2 PIN #1 IDENTIFICATION A1 PIN #1 IDENTIFICATION D2 TOP VIEW SYMBOL MIN SIDE VIEW NOM A 0.70 0.75 0.80 0.00 0.02 0.05 A2 0.45 0.55 0.65 A1 A3 FRONT VIEW 0.20 REF b 0.25 0.30 0.35 3.10 D 2.90 3.00 D2 0.90 1.00 1.10 E 4.80 4.90 5.00 E2 0.90 1.00 1.10 e L A2 A MAX A1 A3 BOTTOM VIEW b L e 0.65 TYP 0.50 0.60 DETAIL A 0.70 Notes: 1. Al dimensions are in millimeters. Angles in degrees. 2. Complies with JEDEC standard MS-229. Doc. No. MD-3014, Rev. D 16 © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice. CAT1320, CAT1321 EXAMPLE OF ORDERING INFORMATION Prefix CAT Optional Company ID Device # Suffix 1320 W Product Number 1320: 32K 1321: 32K L: W: Y: ZD2: -30 I Temperature Range I = Industrial (-40˚C to 85˚C) Reset Threshold Voltage 45: 4.5-4.75V 42: 4.25-4.5V 30: 3.0-3.15V 28: 2.85-3.0V 25: 2.55-2.7V Package PDIP SOIC TSSOP TDFN 4.9x3mm (5) -G T3 Tape & Reel T: Tape & Reel 3: 3,000/Reel Lead Finish Blank: Matte-Tin G: NiPdAu ORDERING INFORMATION Orderable Part Number CAT1320LI-45-G CAT1321LI-45-G CAT1320LI-42-G CAT1321LI-42-G CAT1320LI-30-G CAT1321LI-30-G CAT1320LI-28-G CAT1321LI-28-G CAT1320LI-25-G CAT1321LI-25-G CAT1320WI-45-GT3 CAT1321WI-45-GT3 CAT1320WI-42-GT3 CAT1321WI-42-GT3 CAT1320WI-30-GT3 CAT1321WI-30-GT3 CAT1320WI-28-GT3 CAT1321WI-28-GT3 CAT1320WI-25-GT3 CAT1321WI-25-GT3 CAT1320YI-45-GT3 CAT1321YI-45-GT3 CAT1320YI-42-GT3 CAT1321YI-42-GT3 CAT1320YI-30-GT3 CAT1321YI-30-GT3 CAT1320YI-28-GT3 CAT1321YI-28-GT3 CAT1320YI-25-GT3 CAT1321YI-25-GT3 CAT1320ZD2I45GT3* CAT1321ZD2I45GT3* CAT1320ZD2I42GT3* CAT1321ZD2I42GT3* CAT1320ZD2I30GT3* CAT1321ZD2I30GT3* CAT1320ZD2I28GT3* CAT1321ZD2I28GT3* CAT1320ZD2I25GT3* CAT1321ZD2I25GT3* * Part number is not exactly the same as the "Example of Ordering Information" shown above. For part numbers marked with * there are NO hyphens in the orderable part numbers. Notes: (1) All packages are RoHS-compliant (Lead-free, Halogen-free). (2) The standard lead finish is NiPdAu. (3) The device used in the above example is a CAT1320WI-30-GT3 (SOIC, Industrial Temperature, 3.0 - 3.15V, NiPdAu, Tape & Reel, 3,000/Reel). (4) For additional package and temperature options, please contact your nearest ON Semiconductor Sales office. (5) TDFN not available in NiPdAu (-G) version. © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice. 17 Doc No. MD-3014, Rev. D CAT1320, CAT1321 REVISION HISTORY Date 25-Jan-05 Revision 00 Description Initial issue 21-Jan-08 B Update Package Outline Drawings Update Example of Ordering Information Add Ordering Part Number Change document number from 25085, Rev.00 12-Nov-08 C Change logo and fine print to ON Semiconductor 14-Jul-09 D Update Ordering Information table ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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