ESD7181MU D

ESD7181, SZESD7181
Low Capacitance ESD
Protection Diodes
Micro−package Diodes for ESD Protection
The ESD7181 is designed to protect voltage sensitive components
that require ultra−low capacitance from ESD and transient voltage
events. Excellent clamping capability, low capacitance, low leakage,
and fast response time make these parts ideal for ESD protection on
designs where board space is at a premium. It has industry leading
capacitance linearity over voltage making it ideal for RF applications.
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2
Features
•
•
•
•
•
•
•
•
•
•
•
Low Capacitance 0.3 pF (Typical)
Low Clamping Voltage
Small Body Outline Dimensions: (0.62 x 0.32 mm) − 0201
Low Body Height: 0.3 mm
Working Voltage: ±18.5 V
Low Leakage < 1 nA (Typical)
Low Insertion Loss
Low Dynamic Resistance: < 1 W
IEC61000−4−2 Level 4 ESD Protection
SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
•
•
•
•
RF Signal ESD Protection
Wireless Charger
RF Switching, PA, and Antenna ESD Protection
Near Field Communications
Value
Unit
IEC 61000−4−2 (ESD) (Note 1) Air
15
kV
IEC 61000−4−2 (ESD) (Note 1) Contact
12
kV
IEC 61000−4−5 (ESD) (Note 2)
1
A
°PD°
RqJA
250
400
mW
°C/W
TJ, Tstg
−55 to
+150
°C
TL
260
°C
Total Power Dissipation (Note 3) @ TA = 25°C
Thermal Resistance, Junction−to−Ambient
Junction and Storage Temperature Range
Lead Solder Temperature − Maximum
(10 Second Duration)
Symbol
PIN 1
X3DFN2
CASE 152AF
2
M
2M
= Specific Device Code
= Date Code
*Date Code orientation and/or position may vary depending upon manufacturing location.
ORDERING INFORMATION
Device
Package
Shipping†
ESD7181MUT5G
X3DFN2
(Pb−Free)
10000 / Tape &
Reel
SZESD7181MUT5G
X3DFN2
(Pb−Free)
15000 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
MAXIMUM RATINGS (TA = 25°C unless otherwise noted)
Rating
MARKING
DIAGRAM
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Non−repetitive current pulse at TA = 25°C, per IEC61000−4−2 waveform.
2. Non−repetitive current pulse at TA = 25°C, per IEC61000−4−5 waveform.
3. Mounted with recommended minimum pad size, DC board FR−4
© Semiconductor Components Industries, LLC, 2016
May, 2016 − Rev. 6
1
Publication Order Number:
ESD7181MU/D
ESD7181, SZESD7181
ELECTRICAL CHARACTERISTICS
I
(TA = 25°C unless otherwise noted)
IPP
Parameter
Symbol
IPP
Maximum Reverse Peak Pulse Current
VC
Clamping Voltage @ IPP
VRWM
IT
VC VBR VRWM IR
IR VRWM VBR VC
IT
Working Peak Reverse Voltage
IR
V
Maximum Reverse Leakage Current @ VRWM
VBR
Breakdown Voltage @ IT
IT
IPP
Test Current
Bi−Directional TVS
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Parameter
Symbol
AC Working Voltage
Condition
Min
Typ
Max
Unit
−
−
±18.5
V
20.5
−
35
V
−
<1
50
nA
VRWM
Breakdown Voltage (Note 4)
VBR
IT = 1 mA
VRVM = ±18.5 V
AC Reverse Current
IR
Clamping Voltage (Note 5)
VC
IEC61000−4−2, ±8 kV Contact
See Figures 1 and 2
Clamping Voltage TLP
(Note 6)
VC
IPP = 8 A
IPP = 16 A
IPP = −8 A
IPP = −16 A
37.7
40.4
−38.4
−41.1
Clamping Voltage (Note 6)
Vc
IPP = 1 A @ 8/20 ms
−
35
−
V
Junction Capacitance
CJ
VR = 0 V, f = 1 MHz
VR = 0 V, f = 1 GHz
0.1
0.1
0.3
0.15
0.50
0.50
pF
Dynamic Resistance
RDYN
Insertion Loss
V
TLP Pulse
0.44
W
f = 1 MHz
f = 8.5 GHz
−0.045
−0.335
dB
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Breakdown voltage is tested from pin 1 to 2 and pin 2 to 1.
5. For test procedure see Figures 3 and 4 and application note AND8307/D.
6. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns.
160
20
140
0
120
−20
100
−40
VOLTAGE (V)
VOLTAGE (V)
TYPICAL CHARACTERISTICS
80
60
40
20
−60
−80
−100
−120
0
−140
−20
−25
0
25
50
75
100
125
150
−160
−25
175
0
25
50
75
100
125
150
175
TIME (ns)
TIME (ns)
Figure 1. Typical IEC61000−4−2 + 8 kV Contact
ESD Clamping Voltage
Figure 2. Typical IEC61000−4−2 − 8 kV Contact
ESD Clamping Voltage
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ESD7181, SZESD7181
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
Ipeak
Level
Test Voltage (kV)
First Peak
Current
(A)
Current at
30 ns (A)
Current at
60 ns (A)
1
2
7.5
4
2
2
4
15
8
4
3
6
22.5
12
6
4
8
30
16
8
100%
90%
I @ 30 ns
I @ 60 ns
10%
tP = 0.7 ns to 1 ns
Figure 3. IEC61000−4−2 Spec
ESD Gun
Oscilloscope
TVS
50 W
Cable
50 W
Figure 4. Diagram of ESD Clamping Voltage Test Setup
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
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3
18
−18
16
−16
14
−14
12
−12
CURRENT (A)
CURRENT (A)
ESD7181, SZESD7181
10
8
6
−10
−8
−6
4
−4
2
−2
0
0
0
NOTE:
5
10
15
20
25
30
35
40
45
0
−5
−10
−15
−20
−25
−30
−35
−40
VOLTAGE (V)
VOLTAGE (V)
Figure 5. Typical Positive TLP IV Curve
Figure 6. Typical Negative TLP IV Curve
−45
TLP parameter: Z0 = 50 W, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns.
Transmission Line Pulse (TLP) Measurement
L
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 7. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 8 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels.
S Attenuator
÷
50 W Coax
Cable
10 MW
IM
50 W Coax
Cable
VM
DUT
VC
Oscilloscope
Figure 7. Simplified Schematic of a Typical TLP
System
Figure 8. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
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ESD7181, SZESD7181
TYPICAL CHARACTERISTICS
1.0
1.E−03
0.9
1.E−04
0.8
CAPACITANCE (pF)
1.E−02
CURRENT (A)
1.E−05
1.E−06
1.E−07
1.E−08
0.7
0.6
0.5
0.4
0.3
1.E−09
0.2
1.E−10
0.1
1.E−11
−30 −25 −20 −15 −10 −5
0
5
10
15
20
25
0
−20
30
−15
−10
−5
0
5
10
15
VOLTAGE (V)
VBias (V)
Figure 9. Typical IV Characteristics
Figure 10. Typical CV Characteristics
1
20
0.6
0
0.5
CAPACITANCE (pF)
−1
S21 (dB)
−2
−3
−4
−5
−6
−7
−8
0.4
0.3
0.2
0.1
−9
−10
0
1.E+07
1.E+08
1.E+09
0.E+00
1.E+10
1.E+09
2.E+09
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 11. Typical Insertion Loss
Figure 12. Typical Capacitance over
Frequency
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5
3.E+09
ESD7181, SZESD7181
PACKAGE DIMENSIONS
X3DFN2, 0.62x0.32, 0.355P, (0201)
CASE 152AF
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
A B
D
PIN 1
INDICATOR
(OPTIONAL)
DIM
A
A1
b
D
E
e
L2
E
TOP VIEW
0.05 C
A
RECOMMENDED
MOUNTING FOOTPRINT*
0.05 C
2X
A1
SIDE VIEW
MILLIMETERS
MIN
MAX
0.25
0.33
−−−
0.05
0.22
0.28
0.58
0.66
0.28
0.36
0.355 BSC
0.17
0.23
C
SEATING
PLANE
0.74
2X
0.30
1
e
2X
1
b
2
2X
0.31
DIMENSIONS: MILLIMETERS
2X
0.05
M
0.05
L2
M
C A B
See Application Note AND8398/D for more mounting details
C A B
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
BOTTOM VIEW
ON Semiconductor and the
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SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
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Sales Representative
ESD7181MU/D
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