ESD7321 D

ESD7321
ESD Protection Diodes
Low Capacitance ESD Protection Diode
for High Speed Data Lines
The ESD7321 ESD protection diodes are designed to protect high
speed data lines from ESD. Low capacitance and low ESD clamping
voltage make this device an ideal solution for protecting voltage
sensitive high speed data lines.
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MARKING
DIAGRAM
Features
• Low Capacitance (0.5 pF Max, I/O to GND)
• Protection for the Following IEC Standards:
IEC 61000−4−2 (Level 4)
Low ESD Clamping Voltage
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
•
•
•
•
X3DFN2
CASE 152AF
T
•
•
PIN 1
M
T = Specific Device Code
(Rotated 90° clockwise)
M = Date Code
PIN CONFIGURATION
AND SCHEMATIC
USB 3.x
MHL 2.0
SATA/SAS
PCI Express
1
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
2
ORDERING INFORMATION
Rating
Symbol
Value
Unit
Operating Junction Temperature Range
TJ
−55 to +125
°C
Storage Temperature Range
Tstg
−55 to +150
°C
Lead Solder Temperature −
Maximum (10 Second Duration)
TL
260
°C
IEC 61000−4−2 Contact (ESD)
IEC 61000−4−2 Air (ESD)
ESD
ESD
±15
±15
kV
kV
Device
ESD7321MUT5G
Package
Shipping†
X3DFN2
(Pb−Free)
10000 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
© Semiconductor Components Industries, LLC, 2016
May, 2016 − Rev. 2
1
Publication Order Number:
ESD7321/D
ESD7321
ELECTRICAL CHARACTERISTICS
I
(TA = 25°C unless otherwise noted)
IPP
Parameter
Symbol
IPP
Maximum Reverse Peak Pulse Current
VC
Clamping Voltage @ IPP
VRWM
IR
IR VRWM VBR VC
IT
Working Peak Reverse Voltage
V
Maximum Reverse Leakage Current @ VRWM
VBR
IT
IT
VC VBR VRWM IR
Breakdown Voltage @ IT
IPP
Test Current
Bi−Directional ESD
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Parameter
Reverse Working Voltage
Breakdown Voltage
Symbol
Condition
Min
Typ
VRWM
VBR
IT = 1 mA (Note 1)
Max
Unit
7.0
V
8.0
Reverse Leakage Current
IR
VRWM = 7.0 V, I/O to GND
Clamping Voltage
VC
IPP = 8 A − (IEC61000−4−2 Level 2 Equivalent
(±4 kV Contact, ±8 kV Air))
ESD Clamping Voltage
VC
Per IEC 61000−4−2
Junction Capacitance
CJ
VR = 0 V, f = 1 MHz
Dynamic Resistance
RDYN
V
200
18
nA
V
See Figures 1 and 2
0.5
TLP Pulse
1
pF
W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Breakdown voltage is tested from pin 1 to 2 and pin 2 to 1.
Figure 1. ESD Clamping Voltage Screenshot
Positive 8 kV Contact per IEC61000−4−2
Figure 2. ESD Clamping Voltage Screenshot
Negative 8 kV Contact per IEC61000−4−2
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2
ESD7321
TYPICAL CHARACTERISTICS
Figure 4. CV Characteristics
20
0
18
−2
16
−4
14
−6
CURRENT (A)
CURRENT (A)
Figure 3. IV Characteristics
12
10
8
−8
−10
−12
6
−14
4
−16
2
−18
0
0
5
10
15
20
VOLTAGE (V)
25
−20
−30
30
Figure 5. Positive TLP I−V Curve
−25
−20
−15
−10
VOLTAGE (V)
−5
Figure 6. Negative TLP I−V Curve
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3
0
ESD7321
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
Ipeak
Level
Test Voltage (kV)
First Peak
Current
(A)
Current at
30 ns (A)
Current at
60 ns (A)
1
2
7.5
4
2
2
4
15
8
4
3
6
22.5
12
6
4
8
30
16
8
100%
90%
I @ 30 ns
I @ 60 ns
10%
tP = 0.7 ns to 1 ns
Figure 7. IEC61000−4−2 Spec
Transmission Line Pulse (TLP) Measurement
L
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 8. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 9 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels.
S Attenuator
÷
50 W Coax
Cable
10 MW
IM
50 W Coax
Cable
VM
DUT
VC
Oscilloscope
Figure 8. Simplified Schematic of a Typical TLP
System
Figure 9. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
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4
ESD7321
PACKAGE DIMENSIONS
X3DFN2, 0.62x0.32, 0.355P, (0201)
CASE 152AF
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
A B
D
PIN 1
INDICATOR
(OPTIONAL)
DIM
A
A1
b
D
E
e
L2
E
TOP VIEW
0.05 C
MILLIMETERS
MIN
MAX
0.25
0.33
−−−
0.05
0.22
0.28
0.58
0.66
0.28
0.36
0.355 BSC
0.17
0.23
A
0.05 C
2X
A1
SIDE VIEW
C
RECOMMENDED
MOUNTING FOOTPRINT*
SEATING
PLANE
0.74
e
2X
1
1
b
2
2X
2X
0.05
M
2X
0.30
0.05
L2
M
0.31
C A B
DIMENSIONS: MILLIMETERS
C A B
See Application Note AND8398/D for more mounting details
BOTTOM VIEW
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
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ESD7321/D
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