NCP12510 Product Preview Current-Mode PWM Controller for Off-line Power Supplies The NCP12510 is a highly integrated PWM controller capable of delivering a rugged and high performance offline power supply in a tiny TSOP−6 package. With a voltage supply range up to 35 V, the controller hosts a jittered 65−kHz or 100−kHz switching circuitry operated in peak current mode control. When the power on the secondary side starts decreasing, the controller automatically folds back its switching frequency down to a minimum level of 26 kHz. As the power further goes down, the part enters skip cycle while limiting the peak current. Over Power Protection (OPP) is a difficult exercise especially when no−load standby requirements drive the converter specifications. The ON Semiconductor proprietary integrated OPP allows harness the maximum delivered power without affecting the standby performance simply via two external resistors. An Over Voltage Protection (OVP) input is also combined on the same pin and protects the whole circuitry in case of optocoupler destruction or adverse open loop operation. Finally, a timer−based short−circuit protection offers the best protection scheme, allowing precisely select the protection trip point without caring of a loose coupling between the auxiliary and the power windings. NCP12510 is improved and pin compatible controller based on very popular flyback controller NCP1250. Features • Fixed−Frequency 65 kHz or 100 kHz Current−Mode Control • • • • • • • • • • • • • www.onsemi.com MARKING DIAGRAM TSOP−6 (SOT23−6) SN SUFFIX CASE 318G STYLE 13 1 5Dx x A Y W G 5DxAYWG G 1 = Specific Device Code = A, 2, J, or K = Assembly Location = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) PIN CONNECTIONS GND 1 6 DRV FB 2 5 VCC OPP/Latch 3 4 CS Operation (Top View) Frequency Foldback Down to 26 kHz and Skip−Cycle in Light Load Conditions ORDERING INFORMATION Frequency Jittering in Normal and Frequency Foldback Modes See detailed ordering, marking and shipping information on Internal and Adjustable Over Power Protection (OPP) Circuit page 2 of this data sheet. Auto−Recovery Over Voltage Protection (OVP) on the VCC Pin Internal and Adjustable Slope Compensation Internal Fixed 4 ms Soft−Start Auto−Recovery or Latched Short−Circuit Protection • EPS 2.0 Compliant Pre−Short Ready for Latched OCP Version • This is a Pb−Free Device OVP/OTP Latch Input for Improved Robustness Typical Applications +300 mA/ −500 mA Source/Sink Drive Capability • Ac−dc Converters for TVs, Set−top Boxes and DVD Improved Consumption Players Improved Reset Time in Latch State • Offline Adapters for Notebooks and Netbooks High Robustness and High ESD Capabilities This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. © Semiconductor Components Industries, LLC, 2016 May, 2016 − Rev. P0 1 Publication Order Number: NCP12510/D NCP12510 Figure 1. Typical Application Example Table 1. PIN DESCRIPTION Pin No Pin Name Function Pin Description 1 GND − 2 FB Feedback pin 3 OPP/Latch Adjust the Over Power Protection Latches off the part 4 CS Current sense + slope compensation 5 VCC Supplies the controller − protects the IC 6 DRV Driver output The controller ground. Hooking an optocoupler collector to this pin will allow regulation. A resistive divider from the auxiliary winding to this pin sets the OPP compensation level during the on−time. When the voltage exceeds a certain level at turn off, the part is fully latched off. This pin monitors the primary peak current but also offers a means to introduce slope compensation. This pin is connected to an external auxiliary voltage. When the VCC exceeds a certain level, the part enters an auto−recovery hiccup. The driver output to an external MOSFET gate. Table 2. ORDERING INFORMATION Package Marking OCP Protection OVP/OTP Protection Switching Frequency NCP12510ASN65T1G 5DA Latched Latched 65 kHz NCP12510BSN65T1G 5D2 Auto−recovery Latched 65 kHz NCP12510ASN100T1G 5DJ Latched Latched 100 kHz NCP12510BSN100T1G 5DK Auto−recovery Latched 100 kHz Controller (Note 1) Package Shipping† TSOP−6 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 1. Other options available upon customer request. www.onsemi.com 2 NCP12510 OPP/ Latch VOPP VCC(OVP) DRV stop Latch / Autorecovery mode RST + tlatch(del) VCC(min) Latch / Auto-revery management OVP/OTP Latch Note: depend on IC option OCP Fault Up Counter to 4 Pre-short _ + Vlatch OVP/OTP Latch Latch / Autorecovery mode IC start IC stop VCC and logic management DRV pulse tlatch(blank) IC reset Internal supply Armed flag VCC(on) VCC(OVP) VCC + tOVP(del) _ st 1 DRV pulse during IC start S Q Pre-short R Q (for OCP&UVLO latched option ) IC in regulation FB@gnd + VOVP VCC(min) Clamp DRV pulse DRV pulse Jittering 65 / 100 kHz Oscillator Frequency foldback Rramp Dmax S Q R Q DRV IC stop DRV pulse DRV stop _ + + Vskip VFB(open) IC in regulation Req Kratio FB Up counter to 8 _ + RST peak current freeze Error flag Soft-start LEB R Q S Q RST + VOPP + Vlimit + VOPP Fault timer OCP Fault _ CS + Vlimit GND Figure 2. Internal Circuit Architecture www.onsemi.com 3 NCP12510 Table 3. MAXIMUM RATINGS TABLE Symbol Rating VCC Power Supply voltage, VCC pin, continuous voltage VDRV(tran) Maximum DRV pin voltage when DRV in H state, transient voltage (Note 1) VCS, VFB, VOPP Unit −0.3 to 35 V −0.3 to VCC + 0.3 V −0.3 to 5.5 V VOPP(tran) Maximum negative transient voltage on OPP pin (Note 2) −1 V Isource,max Maximum sourced current, pulsed width < 800 ns 0.6 A Isink,max Maximum voltage on low power pins CS, FB and OPP (Note 2) Value Maximum sinked current, pulse width < 800 ns 1.0 A IOPP Maximum injected negative current into the OPP pin (pin 3) −2 mA RθJ−A Thermal Resistance Junction−to−Air 360 °C/W TJ,max Maximum Junction Temperature 150 °C −60 to +150 °C 4 kV 750 V Storage Temperature Range HBM Human Body Model ESD Capability per JEDEC JESD22−A114F (All pins) CDM Charged−Device Model ESD Capability per JEDEC JESD22−C101E Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. The transient voltage is a voltage spike injected to DRV pin being in high state. Maximum transient duration is 100 ns. 2. See the Figure 3 for detailed specification of transient voltage. 3. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78. on-time 500 ns t 0V VCS VFB VOPP VOPP (t) 7.5 V – Max transient voltage cycle-by-cycle VOPP, max 5.5 V – Max DC voltage VOPP,max = -0.75 V, Tj = -25 °C VOPP,max = -0.65 V, Tj = 25 °C VOPP,max = -0.3 V, Tj = 125 °C – Worst case VOPP -1 V SOA VOPP must stay between 0V and –0.3 V for a linear OPP operation 500 ns Max current during overshoot can 't exceed 3 mA 0V t Figure 3. Negative Pulse for OPP Pin during On−time and Positive Pulse for All Low Power Pins www.onsemi.com 4 NCP12510 Table 4. ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VCC = 12 V unless otherwise noted) Rating Symbol Pin Min Typ Max Unit SUPPLY SECTION VCC(on) VCC increasing level at which driving pulses are authorized 5 16 18 20 V VCC(min) VCC decreasing level at which driving pulses are stopped 5 8.3 8.9 9.5 V VCC(hyst) Hysteresis VCC(on) – VCC(min) 5 7.7 − − V VCC(reset) Latched state reset voltage 5 − 8.6 − V VCC(reset_ Defined hysteresis between minimum and reset voltage VCC(min) – VCC(reset) 5 0.15 0.30 0.45 V Defined hysteresis for hiccupping between two voltage levels in latch mode 5 − 0.55 − V ICC1 Start−up current (VCC(on) – 100 mV) 5 − 6 10 mA ICC2 Internal IC consumption with VFB = 3.2 V, fSW = 65 kHz and CL = 0 nF Internal IC consumption with VFB = 3.2 V, fSW = 100 kHz and CL = 0 nF 5 − 1.0 1.1 1.4 1.5 mA ICC3 Internal IC consumption with VFB = 3.2 V, fSW = 65 kHz and CL = 1 nF Internal IC consumption with VFB = 3.2 V, fSW = 100 kHz and CL = 1 nF 5 − 1.7 2.3 2.7 3.0 mA Internal consumption in skip mode – non switching, VFB = 0 V 5 − 300 − mA Internal consumption in fault mode – during going−down VCC cycle, VFB = 4 V 5 − 340 − mA Internal IC consumption in skip mode for 65 kHz version (VCC = 14 V, driving a typical 7−A/600−V MOSFET, includes opto current) – (Note 5) 5 − 420 − mA hyst) VCC(latch_hyst) ICC(no−load) ICC(fault) ICC(standby) DRIVE OUTPUT tr Output voltage rise−time @ CL = 1 nF, 10−90% of output signal 6 − 40 − ns tf Output voltage fall−time @ CL = 1 nF, 10−90% of output signal 6 − 30 − ns ROH Source resistance, VCC = 12 V, IDRV = 100 mA 6 − 28 − W ROL Sink resistance, VCC = 12 V, IDRV = 100 mA 6 − 7 − W Peak source current, VGS = 0 V (Note 4) 6 − 300 − mA Peak sink current, VGS = 12 V (Note 4) 6 − 500 − mA VDRV(low) DRV pin level at VCC = VCC(min) + 100 mV with a 33 kW resistor to GND 6 8 − − V VDRV(high) DRV pin level at VCC = VOVP – 100 mV (DRV unloaded) 6 10 12 14 V Maximum internal current set point – TJ = 25°C – pin 3 grounded Maximum internal current set point – TJ = −40°C to 125°C – pin 3 grounded 4 0.744 0.720 0.8 0.8 0.856 0.880 V Internal voltage setpoint for frequency foldback trip point – 59% of Vlimit 4 − 475 − mV Isource Isink CURRENT COMPARATOR Vlimit VCS(fold) VCS(freeze) Internal peak current setpoint freeze (≈31% of Vlimit) 4 − 250 − mV tDEL Propagation delay from CS pin to DRV output 4 − 50 80 ns tLEB Leading Edge Blanking Duration 4 − 300 − ns tSS Internal soft−start duration activated upon startup or auto−recovery 4 − 4 − ms IOPPs Set point decrease for pin 3 grounded 3 − 0 − % IOPPo Set point decrease for pin 3 biased to −250 mV (Note 4) 3 − 31.3 − % IOOPv Voltage set point for pin 3 biased to −250 mV, TJ = 25°C Voltage set point for pin 3 biased to −250 mV, TJ = −40° to 125°C 3 0.51 0.50 0.55 0.55 0.60 0.62 V Oscillation frequency (65 kHz version) Oscillation frequency (100 kHz version) − 61 92 65 100 71 108 kHz Maximum duty−ratio − 76 80 84 % INTERNAL OSCILLATOR fOSC(nom) Dmax 4. Guaranteed by design. 5. Application parameter for information only. 6. 1−MW resistor is connected from pin 4 to the ground for the measurement. www.onsemi.com 5 NCP12510 Table 4. ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VCC = 12 V unless otherwise noted) Symbol Rating Pin Min Typ Max Unit INTERNAL OSCILLATOR fjitter Frequency jittering in percentage of fOSC – jitter is kept even in foldback mode − − ±5 − % fswing Swing frequency − − 240 − Hz FEEDBACK SECTION Req Internal equivalent feedback resistance 2 − 29 − kW Kratio FB pin to current set point division ratio − − 4 − − Feedback voltage below which the peak current is frozen 2 − 1.2 − V VFB(limit) Feedback voltage corresponding with maximum internal current set point 2 − 3.2 − V VFB(open) Internal pull−up voltage on FB pin 2 − 4 − V Frequency foldback level on the FB pin – ≈59% of maximum peak current − − 1.9 − V Minimum operating frequency − 22 26 30 kHz End of frequency foldback feedback level, fsw = ftrans − − 1.5 − V Skip−cycle level voltage on the feedback pin − − 0.8 − V Hysteresis on the skip comparator (Note 4) − − 50 − mV VFB(freeze) FREQUENCY FOLDBACK Vfold(start) ftrans Vfold(end) Vskip Vskip(hyst) INTERNAL SLOPE COMPENSATION Vramp Internal ramp level @ 25°C (Note 6) 4 − 2.5 − V Rramp Internal ramp resistance to CS pin 4 − 20 − kW PROTECTIONS Vlatch Latching level input on OPP/Latch pin 3 2.85 3.0 3.15 V tlatch(blank) Blanking time after Drive output turn off (Note 4) 3 − 1 − ms tlatch(count) Number of clock cycles before latch is confirmed (Note 4) 3 − 4 − OVP/OTP delay time constant before latch is confirmed (Note 4) 3 − 600 − ns Over voltage protection on the VCC pin 5 24.0 25.5 27.0 V Delay time constant before OVP on VCC is confirmed (Note 4) 5 − 20 − ms Internal fault timer duration − 100 115 130 ms tlatch(del) VOVP tOVP(del) tfault 4. Guaranteed by design. 5. Application parameter for information only. 6. 1−MW resistor is connected from pin 4 to the ground for the measurement. www.onsemi.com 6 NCP12510 TYPICAL CHARACTERISTICS 20.0 9.0 19.5 8.9 8.8 8.7 VCC(reset) (V) VCC(on) (V) 19.0 18.5 18.0 17.5 8.4 8.2 16.5 −25 0 25 50 75 100 8.1 8.0 −50 125 −25 0 25 50 75 TEMPERATURE (°C) TEMPERATURE (°C) Figure 4. Figure 5. 9.4 500 9.3 450 VCC(reset_hyst) (mV) 9.2 9.1 VCC(min) (V) 8.5 8.3 17.0 16.0 −50 8.6 9.0 8.9 8.8 8.7 100 125 100 125 100 125 400 350 300 250 200 8.6 8.5 8.4 −50 150 −25 0 25 50 75 100 100 −50 125 25 50 75 TEMPERATURE (°C) Figure 6. Figure 7. 900 9.5 800 VCC(latch_hyst) (V) 9.4 VCC(hyst) (V) 0 TEMPERATURE (°C) 9.6 9.3 9.2 9.1 9.0 700 600 500 400 300 8.9 8.8 −50 −25 −25 0 25 50 75 100 200 −50 125 −25 0 25 50 75 TEMPERATURE (°C) TEMPERATURE (°C) Figure 8. Figure 9. www.onsemi.com 7 NCP12510 TYPICAL CHARACTERISTICS 500 9 450 8 400 ICC(no−load) (mA) 10 ICC1 (mA) 7 6 5 4 350 300 250 3 200 2 150 1 −50 −25 0 25 50 75 100 100 −50 125 −25 0 25 50 75 TEMPERATURE (°C) TEMPERATURE (°C) Figure 10. Figure 11. 100 125 100 125 500 1.6 65 kHz 1.5 450 1.4 400 ICC(fault) (mA) ICC2 (mA) 1.3 1.2 1.1 1.0 0.9 350 300 250 200 0.8 0.7 0.6 −50 150 −25 0 25 50 75 100 100 −50 125 −25 0 25 50 75 TEMPERATURE (°C) TEMPERATURE (°C) Figure 12. Figure 13. 2.4 4.0 65 kHz 2.3 3.5 2.2 3.0 2.0 ICC (mA) ICC3 (mA) 2.1 1.9 1.8 1.7 2.5 2.0 1.5 1.0 1.6 1.5 1.4 −50 0.5 VIN = 120 Vac 0 −25 0 25 50 75 100 125 0 0.5 1.0 1.5 2.0 2.5 TEMPERATURE (°C) ADAPTER OUTPUT CURRENT (A) Figure 14. Figure 15. www.onsemi.com 8 3.0 3.5 NCP12510 TYPICAL CHARACTERISTICS 65 50 60 45 55 40 45 ROH (W) tr (ns) 50 40 35 35 30 25 30 20 25 20 15 −50 15 −25 0 25 50 75 100 10 −50 125 −25 0 25 50 75 TEMPERATURE (°C) TEMPERATURE (°C) Figure 16. Figure 17. 100 125 100 125 100 125 16 55 50 14 45 VDRV(low) (W) tf (ns) 40 35 30 25 20 15 10 5 −50 10 8 6 −25 0 25 50 75 100 4 −50 125 −25 0 25 50 75 TEMPERATURE (°C) TEMPERATURE (°C) Figure 18. Figure 19. 22 40 20 35 18 VDRV(high) (W) 30 ROL (W) 12 25 20 15 16 14 12 10 8 10 6 5 0 −50 −25 0 25 50 75 100 4 2 −50 125 −25 0 25 50 75 TEMPERATURE (°C) TEMPERATURE (°C) Figure 20. Figure 21. www.onsemi.com 9 NCP12510 TYPICAL CHARACTERISTICS 1.00 55 0.95 50 45 tDEL (ns) Vlimit (V) 0.90 0.85 0.80 25 0.70 −25 0 25 50 75 100 15 −50 125 280 tLEB (ns) 550 500 450 350 200 25 50 75 100 180 −50 125 −25 0 25 50 75 TEMPERATURE (°C) TEMPERATURE (°C) Figure 24. Figure 25. 350 6.0 325 5.5 300 5.0 275 4.5 250 3.5 200 3.0 175 2.5 50 75 100 2.0 −50 125 −25 0 25 50 75 TEMPERATURE (°C) TEMPERATURE (°C) Figure 26. Figure 27. www.onsemi.com 10 125 100 125 100 125 4.0 225 25 100 240 220 0 75 260 400 −25 50 Figure 23. 300 150 −50 25 Figure 22. 600 0 0 TEMPERATURE (°C) 320 −25 −25 TEMPERATURE (°C) tSS (ms) VCS(fold) (mV) 20 650 300 −50 VCS(freeze) (mV) 35 30 0.75 0.65 −50 40 NCP12510 TYPICAL CHARACTERISTICS 125 0.9 120 0.8 115 fOSC(nom) (kHz) 1.0 IOPPv (V) 0.7 0.6 0.5 0.4 105 100 95 90 85 0.2 80 75 −50 −25 0 25 50 75 100 125 0 25 50 75 TEMPERATURE (°C) Figure 28. Figure 29. 50 95 45 90 100 125 100 125 100 125 Dmax (%) 85 35 30 80 75 25 70 20 15 −50 −25 TEMPERATURE (°C) 40 IOPPo (%) 110 0.3 0.1 −50 100 kHz −25 0 25 50 75 100 65 −50 125 −25 0 25 50 75 TEMPERATURE (°C) TEMPERATURE (°C) Figure 30. Figure 31. 295 90 65 kHz 85 285 275 75 fswing (Hz) fOSC(nom) (kHz) 80 70 65 60 265 255 245 55 235 50 45 −50 −25 0 25 50 75 100 225 −50 125 −25 0 25 50 75 TEMPERATURE (°C) TEMPERATURE (°C) Figure 32. Figure 33. www.onsemi.com 11 NCP12510 TYPICAL CHARACTERISTICS 2.8 45 2.6 40 2.4 Vfold(start) (V) Req (kW) 35 30 25 2.2 2.0 1.8 1.6 20 15 −50 1.4 −25 0 25 50 75 100 1.2 −50 125 −25 0 25 50 75 TEMPERATURE (°C) TEMPERATURE (°C) Figure 34. Figure 35. 100 125 100 125 100 125 2.4 7.5 2.2 6.5 2.0 Vfold(end) (V) Kratio (−) 5.5 4.5 3.5 1.8 1.6 1.4 1.2 2.5 1.5 −50 1.0 −25 0 25 50 75 100 0.8 −50 125 −25 0 25 50 75 TEMPERATURE (°C) TEMPERATURE (°C) Figure 36. Figure 37. 1.4 2.0 1.8 1.2 1.0 1.4 Vskip (V) VFB(freeze) (V) 1.6 1.2 1.0 0.8 0.6 0.8 0.6 0.4 0.4 0.2 −50 −25 0 25 50 75 100 0.2 −50 125 −25 0 25 50 75 TEMPERATURE (°C) TEMPERATURE (°C) Figure 38. Figure 39. www.onsemi.com 12 NCP12510 TYPICAL CHARACTERISTICS 27.5 70 65 27.0 26.5 55 VOVP (V) Vskip(hyst) (mV) 60 50 45 26.0 25.5 40 25.0 35 30 −50 −25 0 25 50 75 100 24.5 −50 125 0 25 50 75 TEMPERATURE (°C) TEMPERATURE (°C) Figure 40. Figure 41. 34 130 32 125 30 100 125 100 125 tfault (ms) 120 28 26 115 110 24 105 22 20 −50 −25 0 25 50 75 100 100 −50 125 −25 0 25 50 75 TEMPERATURE (°C) TEMPERATURE (°C) Figure 42. Figure 43. 4.5 4.0 3.5 Vlatch (V) ftrans (kHz) −25 3.0 2.5 2.0 1.5 −50 −25 0 25 50 75 TEMPERATURE (°C) Figure 44. www.onsemi.com 13 100 125 NCP12510 APPLICATION INFORMATION Introduction NCP12510 implements a standard current mode architecture where the switch−off event is dictated by the peak current set point. This component represents the ideal candidate where low part−count and cost effectiveness are the key parameters, particularly in low−cost ac−dc adapters, open−frame power supplies etc. Updated controller, the NCP12510 packs all the necessary components normally needed in today modern power supply designs, bringing several enhancements such as a non−dissipative OPP, OVP/OTP implementation, short−circuit protection with pre−short ready for latched version and improved consumption, robustness and ESD capabilities. • Current−mode operation with internal slope compensation: implementing peak current mode control at a 65 or 100 kHz switching frequency, the NCP12510 offers an internal slope compensation signal that can easily by summed up to the sensed current. Sub harmonic oscillations can thus be fought via the inclusion of a simple resistor in series with the current−sense information. • Internal OPP: by routing a portion of the negative voltage present during the on−time on the auxiliary winding to the dedicated OPP pin (pin 3), the user has a simple and non−dissipative means to alter the maximum peak current set point as the bulk voltage increases. If the pin is grounded, no OPP compensation occurs. If the pin receives a negative voltage, then a peak current is reduced down. • Low startup and standby current: reaching a low no−load standby power always represents a difficult exercise when the controller draws a significant amount of current during startup. The NCP12510 brings improved consumption to easing the design of low standby power adapters. • EMI jittering: an internal low−frequency modulation signal varies the pace at which the oscillator frequency is modulated. This helps spreading out energy in conducted noise analysis. To improve the EMI signature at low power levels, the jittering is kept in frequency foldback mode (light load conditions). • Frequency foldback capability: a continuous flow of pulses is not compatible with no−load/light−load standby power requirements. To excel in this domain, the controller observes the feedback pin and when it reaches a level of Vfold(start) , it starts reduce switching frequency. When the feedback level reaches Vfold(end) , the frequency hits its lower stop at ftrans . When the feedback pin goes further down and reaches VFB(freeze) , the peak current setpoint is internally frozen. Below this point, if power continues to drop, the controller enters • • • • classical skip−cycle mode, as both frequency and peak current are frozen. Internal soft−start: a soft−start precludes the main power switch from being stressed upon start−up. The soft−start duration is internally fixed for time tSS and it is activated during new startup sequence or during recovering after auto−recovery double hiccup. Latch input: the controller includes a latch input (pin 3) that can be used to sense an over voltage or an over temperature event on the adapter. If this pin is brought higher than the internal reference voltage Vlatch for four consecutive cycles, then the circuit is latched off – VCC hiccups from VCC(min) voltage level with hysteresis VCC(latch_hyst) = 550 mV typically, until a reset occurs. The latch reset occurs when the user disconnects the adapter from the mains and lets the VCC falls below the VCC(reset) level. For the C version, despite an OVP/OTP detection, the circuit autorecovers and never latches. Auto−recovery OVP on VCC: an OVP protects the circuit against VCC runaways. If the fault is present at least for time tOVP(del) then the OVP is validated and the controller enters double hiccup mode. When the VCC returns to a nominal level, the controller resumes operation. Short−circuit protection: short−circuit and especially overload protections are difficult to implement when a strong leakage inductance between auxiliary and power windings affects the transformer (the aux winding level does not properly collapse in presence of an output short). In this controller, every time the internal maximum peak current limit Vlimit is activated (or less when OPP is used), an error flag is asserted and a time period starts thanks to an internal timer. When the timer has elapsed while a fault is still present, the controller is latched or enters an auto−recovery mode, depending on the selected OCP option. Please note that with the latched OCP&UVLO option, the part becomes sensitive to the first UVLO event during the start−up sequence. Any other UVLO events are ignored afterwards – auto−recovery operation. With the first drive pulse is generated armed flag. Armed flag is reset after the first successful start−up sequence (the controller gets into regulation). This is to pass the pre−short test at power up: 1. if the internal armed flag is active and an UVLO event is sensed, the part is immediately latched. 2. if an UVLO signal is detected but the armed flag is not asserted, double−hiccup auto−recovery occurs. 3. if the controller gets into regulation, the armed flag is reset. Then UVLO event is sensed, the part is in auto−recovery operation. www.onsemi.com 14 NCP12510 Start−up Sequence the start−up time. To further reduce the standby power, the start−up current of the controller is extremely low, below 10 mA. The start−up resistor can therefore be connected to the bulk capacitor or directly to the mains input voltage to further reduce the power dissipation. The NCP12510 start−up voltage is made purposely high to permit large energy storage in a small VCC capacitor value. This helps operate with a small start−up current which, together with a small VCC capacitor, will not hamper Rstart-up + Input mains Cbulk VCC + + aux. winding CVCC Figure 45. The startup resistor can be connected to the input mains for further power dissipation reduction. To make sure this current is always greater than 26 mA, then, the minimum value for Rstart−up can be extracted: The first step starts with the calculation of the needed VCC capacitor which will supply the controller which it operates until the auxiliary winding takes it over. Experience shows that this time t1 can be between 5 and 20 ms. If we consider we need at least an energy reservoir for a t1 time of 10 ms, the VCC capacitor must be larger than: C VCC w I CC @ t 1 V CC(on) * V CC(min) w 1.7 m @ 10 m 18 * 8.9 R start*up v V CC(on) @ C VCC t start*up w 18 @ 2.2 m 2.5 w 16 mA (eq. 1) PR (eq. 2) If we account for the 10 mA (maximum) that will flow to the controller, then the total charging current delivered by the start−up resistor must be 26 mA. If we connect the start−up network to the mains (half−wave connection then), we know that the average current flowing into this start−up resistor will be the smallest when VCC reaches the VCC(on) of the controller: I CVCC,min + V ac,rmsǸ2 * V CC(on) p R start*up I CVCC(min) v 85Ǹ2 p * 18 26 m v 779 kW (eq. 4) This calculation is purely theoretical, considering a constant charging current. In reality, the take over time can be shorter (or longer!) and it can lead to a reduction of the VCC capacitor. Thus, a decrease in charging current and an increase of the start−up resistor can be experimentally tested, for the benefit of standby power. Laboratory experiments on the prototype are thus mandatory to fine tune the converter. If we chose the 750 kW resistor as suggested by Equation 4, the dissipated power at high line amounts to: w 1.9 mF Let us select a 2.2 mF capacitor at first and experiments in the laboratory will let us know if we were too optimistic for the time t1 . The VCC capacitor being known, we can now evaluate the charging current we need to bring the VCC voltage from 0 V to the VCC(on) of the IC. This current has to be selected to ensure a start−up at the lowest mains (85 Vrms) to be less than 3 s (2.5 s for design margin): I charge w V ac,rmsǸ2 * V CC(on) p start*up,max [ V ac,peak 2 4 @ R start*up [ ǒ230 @ Ǹ2Ǔ 4 @ 750 k 2 [ 35 mW (eq. 5) Now that the first VCC capacitor has been selected, we must ensure that the self−supply does not disappear when in no−load conditions. In this mode, the skip−cycle can be so deep that refreshing pulses are likely to be widely spaced, inducing a large ripple on the VCC capacitor. If this ripple is too large, chances exist to touch the VCC(min) and reset the controller into a new start−up sequence. A solution is to grow this capacitor but it will obviously be detrimental to the start−up time. The option offered in Figure 45 elegantly solves this potential issue by adding an extra capacitor on the auxiliary winding. However, this component is separated (eq. 3) www.onsemi.com 15 NCP12510 have amplitude depending on the input voltage. The idea implemented in this chip is to sum a portion of this negative swing with the internal voltage reference Vlimit = 0.8 V. For instance, if the voltage swings down to −150 mV during the on−time, then the internal peak current set point will be fixed to the value 0.8 V – 0.150 V = 650 mV. The adopted principle appears in Figure 47 and shows how the final peak current set point is constructed. Let’s assume we need to reduce the peak current from 2.5 A at low line, to 2 A at high line. This corresponds to a 20% reduction or a set point voltage of 640 mV. To reach this level, then the negative voltage developed on the OPP pin must reach: from the VCC pin via a simple diode. You therefore have the ability to grow this capacitor as you need to ensure the self−supply of the controller without affecting the start−up time and standby power. Internal Over Power Protection There are several known ways to implement Over Power Protection (OPP), all suffering from particular problems. These problems range from the added consumption burden on the converter or the skip−cycle disturbance brought by the current−sense offset. A way to reduce the power capability at high line is to capitalize on the negative voltage swing present on the auxiliary diode anode. During the turn−on time, this point dips to –N2 Vbulk , where N2 being the turns ratio between the primary winding and the auxiliary winding. The negative plateau observed on Figure 46 will V OPP + 0.8 @ V limit * V limit + 0.64 * 0.8 + −160 mV (eq. 6) 1 v(24) 40.0 off−time N1(Vout+Vf) 20.0 Plot1 v(24) in volts 1 0 −N2Vbulk −20.0 on−time −40.0 464u 472u 480u time in seconds 488u 496u Figure 46. The signal obtained on the auxiliary winding swings negative during the on−time. www.onsemi.com 16 NCP12510 ROPPU This point will be adjusted to reduce the „ref“ at hi line to the desired level swings to: N1Vout during toff -N2Vin during ton VCC + aux. winding ref = 0.8V + VOPP (VOPP is negative) IOPP driver reset K1 ref SUM _ OPP K2 + + Vlimit = 0.8 V ± 7% ROPPL CS Rsense Figure 47. The OPP circuitry affects the maximum peak current set point by summing a negative voltage to the internal voltage reference. Let us assume that we have the following converter characteristics: Vout = 19 V Vin = 85 to 265 Vrms N1 = Np:Ns = 1:0.25 N2 = Np:Naux = 1:0.18 Given the turns ratio between the primary and the auxiliary windings, the on−time voltage at high line (265 Vrms) on the auxiliary winding swings down to: V aux + −N 2 @ V in,max + −0.18 @ 375 + −67.5 V Div + V OPP + −0.16 [ 2.4 m −67.5 V aux (eq. 8) If we arbitrarily fix the pull−down resistor ROPPL to 1 kW, then the upper resistor can be obtained by: R OPPU + V aux * V OPP VOPP ROPPL + −67.5 ) 0.16 [ 422 kW (eq. 9) −0.16 1k If we now plot the peak current set point obtained by implementing the recommended resistor values, we obtain the following curve, as shown in Figure 48. (eq. 7) To obtain a level as imposed by Equation 7, we need to install a divider featuring the following ratio: Peak current setpoint 100% 80% Vbulk 375 V Figure 48. The peak current regularly reduces down to 80% at 375 Vdc. www.onsemi.com 17 NCP12510 Frequency Foldback The OPP pin is surrounded by Zener diodes stacked to protect the pin against ESD pulses. These diodes accept some peak current in the avalanche mode and are designed to sustain a certain amount of energy. On the other side, negative injection into these diodes (or forward bias) can cause substrate injection which can lead to an erratic circuit behavior. To avoid this problem, the pin is internal clamped slightly below –300 mV which means that if more current is injected before reaching the ESD forward drop, then the maximum peak reduction is kept to 40%. If the voltage finally forward biases the internal zener diode, then care must be taken to avoid injecting a current beyond –2 mA. Given the value of ROPPU , there is no risk in the present example. Finally, please note that another comparator internally fixes the maximum peak current set point to value Vlimit even if the OPP pin is adversely biased above 0 V. The reduction of no−load standby power associated with the need for improving the efficiency, requires a change in the traditional fixed−frequency type of operation. This controller implements a switching frequency foldback when the feedback voltage passes below a certain level, Vfold(start) . At this point, the oscillator turns into a Voltage−Controlled Oscillator (VCO) and reduces switching frequency down to ftrans value, till to feedback voltage reaches the level Vfold(end) . Below this level Vfold(end) , the frequency is fixed and cannot go further down. The peak current setpoint is following the feedback pin until its level reaches VFB(freeze) . Below this value, the peak current setpoint is frozen to VCS(freeze) value or ≈31% of the maximum Vlimit setpoint. The only way to further reduce the transmitted power is to enter skip cycle, which is set when the feedback voltage reaches the level Vskip . Skip cycle offers the best noise−free performance in no−load conditions. Figure 49 and depicts the adopted scheme for the part. Frequency Peak current setpoint fSW VCS max Vlimit fOSC(nom) FB VCS(fold) ftrans VCS(freeze) VFB min Vskip VFB(freeze) Vskip Vfold(end) Vfold(start) VFB(limit) VFB(open) Vfold(start) VFB(limit) VFB Figure 49. By observing the voltage on the feedback pin, the controller reduces its switching frequency for an improved performance at light load. VFB [V] Open loop VFB(open ) Peak current is clamped VFB(limit) Vfold(start) Vfold(end) Ipeak , max fSW is fixed to f OSC(nom) Peak current is chang ing fOSC(nom) fSW is changing ftrans Ipeak , min VFB(freeze ) Vskip Peak current is frozen Skip mode t Figure 50. Another look at the relationship between feedback and current setpoint while in frequency reduction mode. www.onsemi.com 18 NCP12510 Auto−Recovery Short−Circuit Protection up again thanks to the resistive starting network. When VCC reaches VCC(on) , the controller purposely ignores the re−start and waits for another VCC cycle: this is the so−called double hiccup auto−recovery mode. By lowering the duty ratio in fault condition, it naturally reduces the average input power and the rms current in the output cable. Illustration of such principle appears in Figure 51. Please note that soft−start is activated upon re−start attempt. In case of output short−circuit or if the power supply experiences a severe overloading situation, an internal error flag is raised and starts a countdown fault timer. If the UVLO has come or the flag is asserted longer than fault timer value tfault (depends on chosen option), the driving pulses are stopped and the VCC falls down as the auxiliary pulses are missing. When it crosses VCC(min) , the controller consumption is down to a few mA and the VCC slowly builds VCC (t) Short-circuit -> start timer -> Error flag + UVLO -> auto-recovery Overload -> start fault timer -> timer elapsed -> auto-recovery VCC(on) VCC(min) t VDRV (t) t Error flag Fault timer has elapsed Fault timer has elapsed t VCS (t) SS Vlimit t Figure 51. An auto−recovery double hiccup mode is entered in case a faulty event longer than programmable fault timer value is acknowledged by the controller. Latched Short−Circuit Protection with Pre−Short pre−short situation: upon start−up with first drive pulse, the armed flag is raised until regulation is met. If during the time the flag is raised an UVLO event is detected, the part latches off immediately. When IC is latched, VCC enters hiccup mode. In normal operation, if an UVLO event is detected for any reason, the controller will naturally resume operations. Details of this behavior are given in Figure 52. UVLO latch is made available solely during the start−up sequence. When the power supply starts−up, the armed flag is asserted with the first drive pulse. If an UVLO event occurs when the armed flag is asserted, the part immediately latches off. If no UVLO occurs, once the output voltage has reached regulation after 8 consecutive cycles, the internal armed flag is released and the latch authorizing UVLO detections is reset: any new UVLO events will simply be ignored. In the latched option OCP&UVLO, the UVLO test is available at the first power−up or when the part recovering from double hiccup mode. In some applications, the controller must be fully latched in case of an output short circuit presence. In that case, you would select a controller with an OCP latched option in the Options table. When the error flag is asserted, meaning the controller is asked to deliver its full peak current, the controller latches off upon timer completion: all pulses are immediately stopped and VCC hiccups between the two voltage levels, given by a VCC(min) level and added hysteresis VCC(latch_hyst) , until a reset occurs (VCC falls down below VCC(reset) ). However, in presence of a small VCC capacitor, it can very well be the case where the stored energy does not give enough time to let the timer elapse before VCC touches the UVLO. When this happens, the latch is not acknowledged since the timer countdown has been prematurely aborted. To avoid this problem, NCP12510 (with latched OCP&UVLO option) combines the armed flag assertion together with the UVLO event to confirm a www.onsemi.com 19 NCP12510 latched new sequence resumed resumed latched VCC (t) VCC(on) VCC(latch_hyst) VCC(min) VCC(reset) t UVLO@start-up AND armed flag VDRV (t) UVLO after regulation UVLO@recovering NO AND armed flag armed flag glitch t Armed flag 1 1 0 t VCS (t) 8 cycles 8 cycles Vlimit t Figure 52. Full latch occurs in case the UVLO@start−up or @recovering is detected while the armed flag is asserted restart latched latched VCC (t) VCC(on) The V CC hysteresis in latch mode significantly improves the reset time . VCC(latch_hyst) VCC(min) VCC(reset) t When the IC is latched, the user have to unplugged and plugged the adapter to the outlet VDRV (t) Armed flag Error flag t 1 Fault timer has elapsed 0 VCS (t) UVLO@start-up AND armed flag Armed flag t Error flag 8 cycles SS Vlimit t Figure 53. Full latch occurs in case the fault timer has elapsed or UVLO@start−up is detected with asserted armed flag. www.onsemi.com 20 NCP12510 Operation with Grounded Feedback Pin When the VCC touches VCC(on) level, the controller internal logic starts and thus, first DRV pulse is authorized after the safety period of 200 ms passes. But the last DRV pulse can comes just before VCC(min) level. Therefore, there are extended rules to generation and cancellation the armed flag to avoid the false pre−short condition if the controller can’t start properly because of the grounded FB pin. The NCP12510 offers the operation mode when the NCP12510 could be controlled by Master system via Feedback pin (pin 2). When FB pin is grounded, the controller driver pulses are stopped. This is the same situation, when the controller is in skip mode, but with the difference that FB pin could be forced to ground by Master system anytime during operation, even at start−up sequence. latched VFB (t) new sequence latched new sequence latched FB@ gnd FB@gnd t VCC (t) VCC(on) VCC(latch_hyst) VCC(min) VCC(reset) t UVLO@start-up AND armed flag UVLO@start-up AND armed flag VDRV (t) Armed flag 1 0 t 1 1 Grounded FB@VCC(on) → No Armed flag UVLO AND Armed flag Grounded FB @first goingdown V CC cycle → Double hiccup → switching allowed every odd V CC(on) t VCS (t) Vlimit t Figure 54. The controller start−up sequence with grounded FB pin and Pre−short condition. auto-recovery new sequence auto-recovery auto-recovery VFB (t) FB@ gnd FB@ gnd FB@ gnd FB@ gnd t VCC (t) VCC(on) VCC(min) VCC(reset) t VDRV (t) UVLO and NO armed flag UVLO and NO armed flag UVLO t 1 Armed flag 1 1 1 1 0 VCS (t) t 8 cycles 8 cycles Vlimit t Figure 55. The controller behaviour during start−up sequence interupted by grounded FB pin. www.onsemi.com 21 NCP12510 – this is the second armed flag cancelation condition. The Figure 55 shows the cases of interrupted start−up sequence by grounded FB pin. If the start−up sequence is interrupted by grounded FB pin, the armed flag is canceled. Then, if UVLO comes, the controller newly starts after double−hiccup auto−recovery sequence. Then, if UVLO comes again, the controller is latched off. The Figure 56 shows the case of operation, when the controller can operate under some master system with superordinate function. Then, the FB pin is used for authorization or denial DRV pulses. If the normal operation state is interrupted for a long time and afterwards the soft−start is demanded for proper start−up of power supply, the VCC have to be pulled−down below VCC(reset) level. Then, if the FB isn’t grounded, the new start−up sequence are initialized when VCC touches VCC(on) level + 200 ms safety period. During this new start−up sequence is generated the armed flag. The armed flag is generated with first DRV pulse, but only if the first DRV pulse is synchronized with VCC(on) event. If the FB pin is forced to ground during the VCC(on) event and it is released afterwards, the armed flag is not generated. The Figure 54 shows the cases of grounded FB pin at the beginning of start−up sequence. If the armed flag isn’t active and UVLO comes, the controller newly starts after double−hiccup auto−recovery sequence. Then, if UVLO comes again, the controller is latched off. DRV pulses are authorized during the whole first VCC going−down cycle. If any DRV pulse doesn’t come during this time, the double−hiccup auto−recovery sequence is coming. The armed flag could be canceled by two conditions. When the controller gets into regulation after start−up sequence, i.e. during the eight consecutive switching cycles is current setpoint voltage under Vlimit , the armed flag is called off – this is the first armed flag cancelation condition. When the start−up sequence isn’t complete and is interrupted by grounded FB pin, the armed flag is called off new sequence VFB (t) FB@ gnd FB@ gnd FB@ gnd t VCC (t) VCC(on) Supply voltage V CC is The IC must be reset to ensure the soft -start after release the FB Stop DRV pulses by Master Sytem controlled by Master System VCC(min) VCC(reset) t VDRV (t) Armed flag t 1 Grounded FB @VCC(on) → No Armed flag 0 VCS (t) 8 cycles 8 cycles 1 8 cycles t Vlimit t Figure 56. The Master system driving the controller by forcing the FB pin to ground. Slope Compensation half the switching frequency and occur only during Continuous Conduction Mode (CCM) with a duty ratio greater than 50%. To lower the current loop gain, one usually injects between 50 and 100% of the primary inductance downslope. Figure 57 depicts how the ramp is generated internally. Please note that the ramp signal will be disconnected from the CS pin during the off−time. The NCP12510 includes an internal slope compensation signal. This is the buffered oscillator clock delivered during the on−time only. Its amplitude is around 2.5 V at the maximum duty ratio. Slope compensation is a known means used to cure sub harmonic oscillations in CCM−operated current−mode converters. These oscillations take place at www.onsemi.com 22 NCP12510 2.5 V 0V Dmax TSW Driver reset ON time Rramp 20 kΩ + tLEB _ CS Rcomp Rsense From FB Figure 57. Inserting a resistor in series with the current sense information brings slope compensation and stabilizes the converter in CCM operation. current sense pin to the controller ground for an improved immunity to the noise. Please make sure both components are located very close to the controller. In the NCP12510 controller, the oscillator ramp features a 2.5 V swing. If the clock operates at a 65 kHz frequency, then the available oscillator slope corresponds to: S ramp + V ramp,peak D max @ T SW + 2.5 + 208 mVńms (eq. 10) 0.8 @ 15 m Latching Off the Controller The OPP pin not only allows a reduction of the peak current set point in relationship to the line voltage, it also offers a means to permanently latch−off the part. When the part is latched−off, all pulses are immediately stopped and VCC hiccups from VCC(min) voltage level with hysteresis VCC(latch_hyst) until a reset occurs (VCC falls down below level VCCreset ), e.g. by un−plugging the converter from the mains outlet. The VCC hysteresis helps significantly reduce the reset time, because when the user unplugged the adapter from the outlet in the less favourable time (VCC is in its maximum), the VCC has to fall down from voltage level given by 480 mV + 250 mV typically to reset level. The latch detection is made by observing the OPP pin by a comparator featuring a Vlatch reference voltage. However, for noise reasons and in particular to avoid the leakage inductance contribution at turn off, a blanking delay tlatch−blank is introduced before the output of the OVP comparator is checked. Then, the OVP comparator output is validated only if its high−state duration lasts for a minimum time tlatch−del . Below this value, the event is ignored. Then, a counter ensures that only 4 successive OVP events have occurred before actually latching the part. There are several possible implementations, depending on the needed precision and the parameters you want to control. The first and easiest solution is the additional resistive divider on top of the OPP one. This solution is simple and inexpensive but requires the insertion of a diode to prevent disturbing the OPP divider during the on−time. In our flyback design, let’s assume that our primary inductance Lp is 770 mH, and the SMPS delivers 19 V with a Np :Ns ratio of 1:0.25. The off−time primary current slope Sp is thus given by: Sp + ǒVout ) VfǓ @ NNs p Lp + (19 ) 0.7) @ 4 + 102 mAńms 770 m (eq. 11) Given a sense resistor of 330 mW, the above current ramp turns into a voltage ramp of the following amplitude: S sense + S p @ R sense + 102 m @ 0.33 + 34 mVńms (eq. 12) If we select 50% of the downslope as the required amount of slope compensation, then we shall inject a ramp whose slope is 17 mV/ms. Our internal compensation being of 208 mV/ms, the divider ratio (divratio) between Rcomp and the internal Rramp = 20 kW resistor is: divratio + 0.5 @ S sense + 0.082 S ramp (eq. 13) The series compensation resistor value is thus: R comp + R ramp @ divratio + 20 k @ 0.082 + 1.64 kW (eq. 14) A resistor of the calculated value will then be inserted from the sense resistor to the current sense pin. We recommend adding a small capacitor of 100 pF, from the www.onsemi.com 23 NCP12510 Vlatch (t) The IC is latched after the fault is confirmed for 4 consecutive DRV cycles Vlatch The user unplugged and plugged the adapter to the outlet t VCC (t) VCC(on) VCC(latch_hyst) VCC(min) VCC(reset) t VDRV (t) The time needs for IC reset is significantly shorter due to the VCC hysteresis used in latch mode . t Figure 58. Latching off the controller and resuming operation. ROVP D1 ROPPU V CC + 100p ROPPL OPP/ Latch + + _ C1 OVP Vlatch aux. winding OPP Figure 59. A simple resistive divider brings the OPP pin above 3 V in case of a VCC voltage runaway above 18 V. First, calculate the OPP network with the above equations. Then, suppose we want to latch off our controller when Vout exceeds 25 V. On the auxiliary winding, the plateau reflects the output voltage by the turns ratio between the power and the auxiliary winding. In case of voltage runaway for our 19 V adapter, the plateau will go up to: V aux,OVP + V out @ Ns + 25 @ 0.18 + 18 V 0.25 N aux R OVP + V out @ VOVP ROPPL + 18 * 3 + 5 kW 3 (eq. 16) 1k In nominal conditions, the plateau establishes to around 14 V. Given the divide by 6 ratio, the OPP pin will swing to 14/6 = 2.3 V during normal conditions, leaving 700 mV for the noise immunity. A 100 pF capacitor can be added to improve it and avoid erratic trips in presence of external surges. Do not increase this capacitor too much otherwise the OPP signal will be affected by the integrating time constant. A second solution for the OVP detection alone is to use a Zener diode wired as recommended by Figure 60. (eq. 15) Since our OVP comparator trips at level Vlatch = 3 V, across the 1 kW selected OPP pull−down resistor, it implies a 3 mA current. From 3 V to go up to 18 V, we need an additional 15 V. Under 3 mA and neglecting the series diode forward drop, it requires a series resistor of: 15 V V aux,OVP * V latch D1 R OPPU V CC + R OPPL + + _ C1 22p OPP / Latch V latch OVP aux . winding OPP Figure 60. A Zener diode in series with a diode helps to improve the noise immunity of the system. www.onsemi.com 24 NCP12510 In this case, to still trip at 18 V level, we have selected a 15 V Zener diode. In nominal conditions, the voltage on the OPP pin is almost 0 V during the off−time as the Zener is fully blocked. This technique clearly improves the noise immunity of the system compared to that obtained from a resistive string as in Figure 59. Please note the reduction of the capacitor on the OPP pin to 10−22 pF. This is because of the potential spike going through the Zener parasitic capacitor and the possible auxiliary level shortly exceeding its breakdown voltage during the leakage inductance reset period (hence the internal blanking delay tlatch−blank at turn off). This spike despite its very short time is energetic enough to charge the added capacitor C1 and given the time constant, could make it discharge slower, potentially NTC disturbing the blanking circuit. When implementing the Zener option, it is important to carefully observe the OPP pin voltage (short probe connections!) and check that enough margin exists to that respect. Over Temperature Protection In a lot of designs, the adapter must be protected against thermal runaways, e.g. when the temperature inside the adapter box increases a certain value. Figure 61 shows how to implement a simple OTP using an external NTC and a series diode. The principle remains the same: make sure the OPP network is not bothered by the additional NTC hence the presence of this diode. D1 ROPPU VCC + + + _ ROPPL OPP/ Latch OVP Vlatch aux. winding OPP Figure 61. The internal circuitry hooked to OPP/Latch pin can be used to implement over temperature protection (OTP). 200 mV decrease from the Vlimit setpoint and the on−time swing on the auxiliary anode is −67.5 V, then we need to drop over ROPPU a voltage of: When the NTC resistor will diminish as the temperature increases, the voltage on the OPP pin during the off−time will slowly increase and, once it passes Vlatch level for 4 consecutive clock cycles, the controller will permanently latch off. Back to our 19 V adapter, we have found that the plateau voltage on the auxiliary diode was 14 V in nominal conditions. We have selected an NTC which offers a 470 kW resistance at 25°C and drops to 8.8 kW at 110°C. If our auxiliary winding plateau is 14 V and we consider a 0.7 V forward drop for the diode, then the voltage across the NTC in fault mode must be: VR OPPU The current circulating the pull down resistor ROPPL in this condition will be: IR Based on the 8.8 kW NTC resistor at 110°C, the current inside the device must be: V latch + 2.5 kW I NTC V OPP + −0.2 + −80 mA R OPPL 2.5 k (eq. 21) VR IR OPPU OPPU + −67.3 [ 841 kW −80 m (eq. 22) Combining OVP and OTP The OTP and Zener−based OVP can be combined together as illustrated by Figure 62. In nominal VCC/output conditions, when the Zener is not activated, the NTC can drive the OPP pin and trigger the adapter in case of a fault. On the contrary, in nominal temperature conditions, if the loop is broken, the voltage runaway will be detected and acknowledged by the controller. In case the OPP pin is not used for either OPP or OVP, it can simply be grounded. (eq. 18) As such, the bottom resistor ROPPL , can easily be calculated: R OPPL + + R OPPU + (eq. 17) I NTC + + 10.3 + 1.2 mA R NTC(110) 8.8 k OPPL The ROPPU value is therefore easily derived: V NTC + V aux * V latch * V F + 14 * 3 * 0.7 + 10.3 V V NTC + V aux * V OPP + −67.5 ) 0.2 + −67.3 V (eq. 20) (eq. 19) Now the pull down OPP resistor is known, we can calculate the upper resistor value ROPPU to adjust the power limit at the chosen output power level. Suppose we need a www.onsemi.com 25 NCP12510 15 V D1 NTC R OPPU V CC + + + aux. winding _ R OPPL OPP / Latch OVP V latch OPP Figure 62. With the NTC back in place, the circuit nicely combines OVP, OTP and OPP on the same pin. Filtering the Spikes recommend the installation of a small RC filter before the detection network as illustrated by Figure 63. The values of resistance and capacitance must be selected to provide the adequate filtering function without degrading the stand−by power by an excessive current circulation. The auxiliary winding is the seat of spikes that can couple to the OPP pin via the parasitic capacitances exhibited by the Zener diode and the series diode. To prevent an adverse triggering of the Over Voltage Protection circuitry, we 15 V NTC D1 Additional filter R OPPU R1 C1 + + + _ R OPPL OPP/ Latch V latch V CC OVP aux. winding OPP Figure 63. A small RC filter prevents the fast rising spikes from reaching the protection pin OPP/latch in presence of energetic perturbations superimposed on the input line. Parameters Options Second adjustable parameter is over voltage protection threshold on VCC pin – VOVP. Default value of VOVP is 25.5 V. Other option is 32 V. Third adjustable parameter is internal fault timer – tfault . Default value of tfault is 115 ms. Other possible options are 23 ms, 60 ms and 460 ms. Guaranteed dispersion of this parameter is ±15% for min and max marginal values. This chapter deals with options of the parameters which could be change on the current silicon upon customer request. First adjustable parameter is frozen internal peak current setpoint – VCS(freeze) . This parameter determines the efficiency vs. acoustic noise performance for light loads. Default value of VCS(freeze) is set at 250 mV (≈31% of Vlimit). Other possible options are 275 mV (≈34% of Vlimit) and 300 mV (≈38% of Vlimit). www.onsemi.com 26 NCP12510 PACKAGE DIMENSIONS TSOP−6 CASE 318G−02 ISSUE V D H 6 5 ÉÉ E1 1 2 4 L2 GAUGE PLANE E 3 NOTE 5 L M b C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D AND E1 ARE DETERMINED AT DATUM H. 5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE. SEATING PLANE DETAIL Z e A 0.05 c A1 DETAIL Z DIM A A1 b c D E E1 e L L2 M MIN 0.90 0.01 0.25 0.10 2.90 2.50 1.30 0.85 0.20 0° MILLIMETERS NOM MAX 1.00 1.10 0.06 0.10 0.38 0.50 0.18 0.26 3.00 3.10 2.75 3.00 1.50 1.70 0.95 1.05 0.40 0.60 0.25 BSC 10° − STYLE 13: PIN 1. GATE 1 2. SOURCE 2 3. GATE 2 4. DRAIN 2 5. SOURCE 1 6. DRAIN 1 RECOMMENDED SOLDERING FOOTPRINT* 6X 0.60 6X 3.20 0.95 0.95 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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