AND9131/D Designing a LED Driver with the NCL30080/81/82/83 www.onsemi.com Introduction As LED lighting finds its way into low wattage applications, lamp designers are challenged for a variety of conflicting requirements. Size is often dictated by the incumbent lamp and fixture size whether it’s A19, GU10, etc. Thermal performance, reliability, safety, and EMC requirements also present design challenges. The NCL3008X family of controllers incorporates all the features and protection needed to design compact low wattage LED drivers with a minimum of external components. APPLICATION NOTE Overview The NCL3008X is a family of 4 controllers in 2 different packages (Micro 8 and TSOP6). The 8 pin packaged parts have 2 extra pins for Dimming and thermal/over voltage protection. The 6 pin package parts have all the basic control and protection feature required to make a low parts count LED driver. Table 1. PRODUCT MATRIX Product Package Thermal Foldback Analog/Digital Dimming 5 Step LOG Dimming NCL30080A/B TSOP6 No No No NCL30081A/B TSOP6 No No Yes NCL30082A/B Micro-8 Yes Yes No NCL30083A/B Micro-8 Yes Soft-start Yes output current, the leakage inductor current must be taken into account. This is accomplished by sensing the clamping network current. Practically, a node of the clamp capacitor is connected to Rsense instead of the bulk voltage Vbulk. Then, by reading the voltage on the CS pin, we have an image of the primary current (red curve in Figure 3). When the diode conducts, the secondary current decreases linearly from ID,pk to zero. When the diode current has turned off, the drain voltage begins to oscillate because of the resonating network formed by the inductors (Lp + Lleak) and the lump capacitor. This voltage is reflected on the auxiliary winding wired in fly-back mode. Thus, by looking at the auxiliary winding voltage, we can detect the end of the conduction time of secondary diode. The constant current control block picks up the leakage inductor current, the end of conduction of the output rectifier and controls the drain current to maintain the output current Iout constant. We have: In the A versions of the NCL3008X, some protections are latched. In the B versions, all faults are auto-recoverable. The controllers have a built in control algorithm that allows to precisely regulate the output current of a Flyback converter from the primary side. This eliminates the need for an optocoupler and associated circuitry. The control scheme also support Buck-boost and SEPIC topology. The output current regulation is within ±2% over a line range of 85-265 V rms. The power control uses a Critical Conduction Mode (CrM) approach with valley switching to optimize efficiency and EMI filtering. The controller selects the appropriate valley for operation which keeps the frequency within a tighter range than would normally be possible with simple CrM operation. Constant Current Control In a Flyback converter, the leakages inductances slow down the primary current decay and the secondary current rise. Thus, the current transfer from primary to secondary side is delayed and the secondary peak current is reduced: I D,pk t I L,pk N sp I out + December, 2014 − Rev. 1 (eq. 2) The output current value is set by choosing the sense resistor: (eq. 1) R sense + The diode current reaches its peak when the leakage inductor is reset. Thus, in order to accurately regulate the © Semiconductor Components Industries, LLC, 2014 V REF 2N spR sense 1 V ref 2N spI out (eq. 3) Publication Order Number: AND9131/D AND9131/D From (eq.2), the first key point is that the output current is independent of the inductor value. Moreover, the leakage inductance does not influence the output current value as the reset time is taken into account by the controller. Vbulk Vout Rclamp IL,pk ID,pk Ipri(t) Cclamp Isec(t) CS RCS t2 t1 Rsense CCS Vaux(t) tdemag Figure 1. Fly-back Currents and Auxiliary Winding Voltage in DCM Figure 2. Fly-back Converter Design Rules for Accurate Current Control In order to have an accurate regulation of the secondary current, the current-sense voltage shape must be the same as the primary current. Figure 3 portrays the current sense waveform in green for an accurate output current regulation. IL,pk Ipri(t) Ipri(t) ton t1 Figure 3. Current Sense Voltage Waveform for an Accurate Current Regulation of the CS voltage will influence the output current set-point. If the CS pin filter (RLFF, CCS) is too big, the output current setpoint will vary (Iout higher than expected value). Figure 5 shows the current-sense waveform in such case. The shape of the current-sense voltage will influence the output current regulation. Indeed, the controller monitors when the current-sense voltage crosses the threshold for leakage inductance reset VCS(low) and calculate the output current set-point based on this information. Thus, the shape www.onsemi.com 2 AND9131/D CS RLFF Ipri(t) Rsense CCS Figure 4. Current-sense Pin Figure 5. CS Pin Filter Not Optimized: CS Shape Differs from Primary Current Shape The ZCD pin voltage is used to detect when the secondary current becomes null. It is important to filter the ringing caused by the leakage inductance and the lump capacitor if these oscillations have not decayed when the internal blanking timer tBLANK has elapsed. The demagnetization must be longer than tBLANK for accurate current regulation. If not, the controller will not be able to detect correctly the exact moment when the secondary current becomes null and the current regulation will greatly degrade. tBLANK tdemag Figure 6. Optimal Filtering of ZCD Pin Voltage LED Driver Specification In order to illustrate the design method that will be described in this document, we consider the following specification for a flyback LED driver: Table 2. LED DRIVER SPECIFICATION Description Symbol Value Units LED Driver Specification Minimum Input Voltage Vin,min 85 V rms Maximum Input Voltage Vin,max 265 V rms Minimum Output Voltage Vout,min 12 V Maximum Output Voltage Vout,max 24 V Output Voltage at which the OVP is Activated Vout(OVP) 28 V Iout 0.5 A Output Current (Nominal) Output Rectifier Voltage Drop (Estimated) Input Voltage for Brown-in Start-up Time www.onsemi.com 3 Vf 0.6 V Vin(start) 72 Vrms tstartup ≤ 1.5 s AND9131/D Table 2. LED DRIVER SPECIFICATION (continued) Description Symbol Value Units h 85 % Clump 50 pF Fsw 45 kHz Vripple 30 V Other Parameters Estimated Efficiency Estimated Lump Capacitor Switching Frequency at Pout,max, Vin,min Estimated Bulk Voltage Ripple Sizing the components around the controller Dout Rclamp Cout RDUM DOVP Dclamp RZCD RBOU VDIM Rstart Cclamp CZCD M1 CCS RNTC CSD RZCDL (optional) Cbulk RLFF CBO RBOL CVCC Rsense Figure 7. Generic Application Schematic The RZCD resistor limits the current flowing in the ZCD pin. Also, this resistor together with the CZCD capacitor delays the zero voltage crossing event and helps to tune the turn-on instant when the drain voltage is in the valley. To calculate RZCD, we must first determine the auxiliary winding voltage value during the on-time and the off-time. During the on-time, the voltage amplitude will reach its maximum value for the highest input voltage: V aux(low) + *N auxpV in,max Ǹ2 Then, the highest value of the aux winding voltage is used to calculate RZCD: R ZCD w max Ǔ V aux(high) V aux(low) , I ZCD(max)) I ZCD(max*) (eq. 6) Design Example: The maximum input voltage is Vin,max = 265 V rms. Nauxp = 0.17. From the datasheet, we have: IZCD(max) = −2, + 5 mA (eq. 4) During the off-time, we must consider the maximum output voltage value to calculate the auxiliary winding maximum voltage: N auxp V aux(high) + (V out ) V f) N sp ǒ V aux(high) + N auxp (V out,max ) V f) + 0.17 (28 ) 0.5) + 28.5 V 0.17 N sp (eq. 7) V aux(low) + *N auxpV in,max Ǹ2 + *0.17 (eq. 5) + *63.7 V Where: Nauxp is the auxiliary to primary turn ratio: Nauxp = Naux/Np www.onsemi.com 4 265 Ǹ2 + (eq. 8) AND9131/D Ǔ + max 28.5 , *63.7 5m *2m + max (5.7k, 31.8k) + 31.8 kW (eq. 9) R ZCD w max ǒ V aux(high) , V aux(low) I ZCD(max)) I ZCD(max*) ǒ Ǔ Then, we can use this Bx value to approximate the resistance at 25°C of the thermistor needed: R 25 + e Bx ǒ R TFstart 1 T TFstart 1 25)273 Ǔ (eq. 12) Selecting the NTC Design Example: TTFstart = 75°C = 348 K TOTP = 95°C = 368 K There are different ways to select the thermistor depending on the critical parameter for the designer. We will consider the temperature TTFstart at which the thermal foldback starts and the temperature TOTP at which the over temperature protection (OTP) must triggers as our design parameters. The controller starts to reduce the output current when the voltage on SD pin drops below 1 V which correspond to a resistance between SD pin and ground: RSD ≤ 11.76 kW. The current reduction is stopped when RSD ≤ 8 kW: the output current is clamped to 50% of its nominal value. The controllers detects an over temperature and shuts down when RSD ≤ 5.88 kW. As a starting point, we can try to calculate the sensitivity index or constant B of the material needed to meet our temperature requirements. The formula for B can be found in the thermistor manufacturers’ application notes or datasheets. To calculate the B value, it is necessary to know the resistances R1 and R2 of the thermistor at the temperatures T1 and T2. B+ ǒ Ǔ R T 1T 2 ln 1 T 2*T 1 R2 Bx + R 25 + e Ǔ Bx ǒ (eq. 13) R TFstart 1 T TFstart 1 25)273 Ǔ 11.76k + e 4438 1 1 Ǔ ǒ348 298 + 99.9 kW (eq. 14) The SD pin capacitor must not exceed 4.7 nF so that the controller is able to start in every conditions, in particular when RSD is around 8 kW. Indeed at startup, the controller waits for 180 ms minimum before starting the DRV pulses in order to allow the current source to charge CSD. If a too big capacitor is used, the SD pin voltage will not be able to increase above 0.5 V before the 180 ms timer ends. Thus, the controller will detect an over temperature condition. Where: TTFstart is the temperature at which the thermal foldback should start RTFstart is the corresponding resistance mentioned above: RTFstart = 11.76 kW TOTP is the temperature at which the OTP must trigger ROTP is the corresponding resistance mentioned above: ROTP = 5.88 kW Designing the CS Pin Network (RLFF, CCS) The propagation delay tprop from the current-sense voltage reaching the programmed internal threshold Vcontrol to the MOSFET off-state influences the output current regulation and must be taken into account. The peak current increase caused by tprop must be compensated. Generally, the B given by the manufacturer is calculated for 25°C and 85°C. The value of B depends on the temperatures by which it is calculated. That’s why in our case it is an approximate value and we might consider looking for a material within ±5% of the calculated Bx. IL Rsense Ǔ Selecting the SD Pin Capacitor (eq. 11) Vcontrol ǒ Finally, we select a NTC with B25/85 = 4220 and R25 = 100 kW. From the manufacturer tables of resistance vs temperature R(T), we have the following values: R75 = 13.16 kW, R80 = 11.06 kW meaning the temperature foldback point is between 75°C and 80°C. R95 = 6.74 kW, R100 = 5.76 kW meaning the OTP trip point is between 95°C and 100°C. It is also possible to place a resistor in parallel of the NTC to modify its R(T) characteristic. In our case, this equation can be translated as follows: ǒ Ǔ + 4438 K (eq. 10) T T R B x + OTP TFstart ln TFstart T OTP*T TFstart R OTP ǒ T OTPT TFstart R ln TFstart + 348 368 ln 11.76k + 368*348 T OTP*T TFstart R OTP 5.88k DIL,pkH High Line DIL,pkL Low Line tprop tprop Figure 8. Propagation Delay Effect on Peak Current www.onsemi.com 5 time AND9131/D As a first approximation, to calculate RLFF, start with tprop = 150 ns. Then, the offset resistor value can be adjusted by experiments to obtain a flat output current. Using (eq.16), we can calculate the first value of RLFF for our design: The propagation delay effect is compensated by applying an offset current proportional to the line voltage on the CS pin during the MOSFET on-time only. The offset current is clamped when VpinVIN > 5 V: Ioffset(MAX) = 76.5 mA typical. The offset voltage amount is adjusted by connecting a resistor RLFF between the CS pin and the sense resistor: V CS(offset) + K LFFV pinVINR LFF ǒ (eq. 15) R LFF + 1 ) As a starting point, the offset resistor value can be estimated with: ǒ Ǔ t pro pR sense R R LFF + 1 ) BOU R BOL L pK LFF Ǔ R BOU t pro pR sense + R BOL L pK LFF ǒ Ǔ 9.9Meg 150n + 1) 100k 1900m (eq. 16) (eq. 17) 1.5 + 696 W 17m After experiments in the lab, RLFF value was increased to 820 W. Where: KLFF is the voltage to current conversion ratio on VIN pin and can be found in the datasheets of the NCL30080/81/82/83. Its typical value is 17 mA/V. RBOU and RBOL are the brown-out resistors calculated in the next paragraph. Selecting the CS Pin Capacitor The shape of the current-sense voltage influences the output current regulation. If the CS pin filter (RLFF, CCS) is too big, the output current setpoint will vary (Iout higher than expected value). Thus, once RLFF has been chosen, it is important to keep the value of CCS small to have a good regulation of the output current. CCS should be in the range of 10 – 100 pF. The parameter tprop includes the propagation delay of the controller (50 ns typical from the datasheet) and of the MOSFET gate drive. Thus, it varies with the chosen MOSFET and with the external elements added between the DRV pin and the MOSFET gate (series resistor, PNP transistor, ...). As a consequence, it is difficult to have an exact value for this parameter prior to the LED driver design. Selecting the Brown-out Resistors The controller starts switching when VCC > VCC(on) and when VpinVIN > VBO(on). Vbulk RBOU VIN + 50 ms blanking time BO_NOK − CBO RBOL Fixed internal ON / OFF thresholds: – Controller starts switching if VpinVIN > VBO(on) (1 V) – Controller stops switching if VpinVIN < VBO(off) (0.9 V) after 50 ms Figure 9. Brown-out Circuit The controller detects a brown-out condition and shuts down when the pin VIN voltage stays below VBO(off) during 50 ms. Thus, we can deduce the line voltage Vin(stop) at which the controller stops switching: First, select a value for RBOL in the range of 10 kW to 100 kW. In order to decrease the power losses in the resistor network, it is better to choose a resistor in the range of 62 kW to 100 kW. For our design, we select RBOL = 100 kW. After that, select the input voltage at which the controller must start switching Vin(start). The upper brown-out resistor RBOU value can be calculated with: R BOU + R BOL ǒ V in(start) Ǹ2 *1 V BO(on) Ǔ R ) R BOL V in(stop) + 1 BOU V BO(off) Ǹ2 R BOL Design Example: Vin(start) = 71 V rms RBOL = 100 kW. (eq. 18) www.onsemi.com 6 (eq. 19) AND9131/D R BOU + R BOL ǒ V in(start) Ǹ2 *1 V BO(on) Ǔ + 100k ǒ Ǔ The DIM pin combines analog and PWM dimming capability. If a signal lower than VDIM100 is applied to this pin, the controller decreases the output current proportionally to the applied voltage. The following equation gives the relationship between the output current and the DIM pin voltage: 71 Ǹ2 *1 + 1 + 9.94 MW (eq. 20) We choose RBOU = 9.9 MW. R ) R BOL V in(stop) + 1 BOU V BO(off) + Ǹ2 R BOL I out(%) + 100 V DIM*0.4 175 + 1 9.9M ) 100k 0.9 + 63.6 Vrms Ǹ2 100k (eq. 22) For normal PWM dimming, apply a signal with a low state value below VDIM(EN) and high state value above VDIM100. It is also possible to apply a square signal with a high state value below VDIM100 to further reduce the output current in PWM dimming (Deep PWM dimming in Figure 10). (eq. 21) The controller stops when Vin < 63.6 V rms. Dimming Pin (NCL30082 Only) The NCL30082 DIM pin has an enable threshold VDIM(EN). In order to start pulsing, the DIM pin voltage must be higher than VDIM(EN). VDIM Analog dimming 0.7 V PWM dimming VDIM100 100% Iout VDIM(EN) 0% Iout Figure 10. Analog / PWM Dimming www.onsemi.com 7 Deep PWM dimming AND9131/D STARTUP NETWORK The NCL3008X consumes a low current during the startup (14 mA typ., 30 mA max.). Thus, depending on the required startup time, high values of startup resistors can be used to reduce the power dissipation in the startup network. However, the device consumes a slightly higher current (60 mA max.) during startup in fault mode, when the 4-s auto-recovery timer is counting. The power supply designer must ensure that the startup current noted Istartup on Figure 11 is always above 60 mA. The startup resistor Rstartup can either be connected to the bulk rail or to half-wave (Figure 11). Connecting the startup resistor to the half-wave allows decreasing the power dissipated in the startup resistor. Istartup Istartup Rstartup Rstartup / p CVcc Laux CVcc Bulk rail connection Laux Half−wave connection Figure 11. The Startup Resistor can be Connected to the Bulk Rail or to the Half Wave Calculating the Startup Capacitor of the LED string. Thus, we can consider that all the current charges the output capacitor. We can then roughly estimate the time treg: The startup capacitor is calculated to allow the power supply to close the loop before VCC falls below VCC(off). Thus, CVcc must be able to supply the controller alone until the auxiliary winding voltage Vaux is high enough to supply the controller. The time duration where the controller is supplied by CVcc alone is noted treg (Figure 12). At startup, almost no current will flow through the LED string until the output voltage exceeds the forward threshold t reg + N auxp C out (V ) V f) I out out1 N sp (eq. 23) Where: Vout1 is the corresponding output voltage at which the auxiliary winding should start to supply the controller tstartup treg Figure 12. VCC Waveform during Startup www.onsemi.com 8 AND9131/D The startup capacitor value can be calculated as follows: C Vcc w (I CC2 ) Q g F sw)t reg V CC(on),min*V CC(off),max Where: ICvcc is the current needed to charge the VCC pin capacitor ICC(start) is the current consumed by the controller during startup Vin,min is the minimum input voltage (eq. 24) The current needed to charge CVcc alone during the startup is: IC Vcc + V CC(on),max C Vcc t startup The maximum power dissipated by the startup resistor connected to the bulk rail is: (eq. 25) Design Example: Four our 10 W LED driver, we chose a 3-A, 800-V MOSFET (STP3NK80 from ST Microelectronics). The total gate charge is: Qg = 19 nC The switching frequency at low line, maximum output load is: Fsw = 55 kHz. The total startup time of the LED driver must be below 1.5 second at Vin = 90 V rms. We choose: Vout1 = 15 V From the datasheet, we can extract the values of the following parameters: ICC2 = 2.1 mA VCC(on),min = 16 V VCC(on),max = 20 V VCC(off),max = 9.4 V P startup + *6 R startup1ń2 + (2.1m ) 19n 55k) 16*9.4 4m P startup1ń2 + Vcc + R startup p (eq. 31) ǒ V in,max p Ǹ2 *V CC Ǔ 2 (eq. 32) R startup1ń2 From the datasheet, the typical value of ICC(start) is 14 mA. We deduce: V in,min Ǹ2 85 Ǹ2 + + 1.56 MW 63m ) 14m I Cvcc ) I CC(start),max (eq. 33) (eq. 26) V in,min Ǹ2 R startup1ń2 + p I Cvcc ) I CC(start) + 85Ǹ2 p 63m ) 14m [ 497 kW (eq. 34) The power dissipated for each resistor at maximum input voltage is: + 1.91 mF V CC(on),max C Vcc 20 4.7m + [ 63 mA t startup 1.5 (eq. 27) P startup + P startup1ń2 + (eq. 28) Ǹ2 *V Ǔ CC 2 R startup + ǒ265 Ǹ2 *20Ǔ 1.56 2 + 81 mW 10 6 ǒ V in,max p Ǹ2 *V CC R startup1ń2 Ǔ 2 + ǒ Ǔ 265Ǹ2 p *20 497k 2 + 20 mW (eq. 36) Connecting the startup resistor to the half-wave allows saving 60 mW! Thus, we choose this approach for our LED driver design. • Bulk Connection: If the resistor is connected to the bulk rail, the following formula can be used to calculate its value: V in,min Ǹ2 I Cvcc ) I CC(start) ǒV in,max (eq. 35) Startup Resistor Calculation R startup + + Design Example: We could choose a 2.2 mF capacitor for CVcc but we must also consider the step dimming case of the NCL30083 where the output current is decreased by discrete steps each time a brown-out condition is detected. Thus, we select a 4.7 mF capacitor. The current needed to charge CVcc is: IC p I Cvcc ) I CC(start) The maximum power dissipated by the startup resistor connected to the half-wave is thus: (I CC2 ) Q g F sw)t reg C Vcc + + V CC(on),min*V CC(off),max + (eq. 30) R startup V in,min Ǹ2 R startup + (15 ) 0.6) 0.17 [ 4 ms 0.17 2 If the resistor is connected to the half-wave: N auxp C out (V ) V f) + I out out1 N sp + 120 10 0.470 Ǹ2 *V Ǔ CC • Half-wave Connection: We can deduce: t reg + ǒV in,max (eq. 29) www.onsemi.com 9 AND9131/D FLYBACK TRANSFORMER DESIGN frequency for this operating point Fsw,min, we can calculate the maximum peak current and the primary inductance value: The transformer is an important part of the power supply design as it will influence the choice of the MOSFET, the output rectifier and the RCD clamp network. The transformer design is a compromise between performance and cost of the solution. For example, allowing higher drain-source voltage excursion will imply to use a MOSFET with a larger breakdown voltage, but it will allow using an output rectifier with a smaller breakdown voltage. It will also decrease the power losses in the RCD clamp as we will be able to use higher clamping resistor value (provided that the leakage inductance of the transformer is kept under control). Reflecting more output voltage will also decrease the maximum necessary primary peak current, but it will increase the secondary peak current. I L,pk + 2 )p 0.5 (eq. 37) I L,pk + 2 N sp + f 2P out,max (eq. 41) 2 I L,pk F sw,min h ǒ Ǔ N sp 1 ) V in,min Ǹ2 *V ripple V out(OVP) ) V f out,maxC lumpF sw,min h ) + ǒ (eq. 38) Ǔ 1 + 2 28 0.5 ) 0.167 ) 0.85 85 Ǹ2 *30 28 ) 0.6 )p 24)0.6 *(V out,max ) V f) *(24 ) 0.6) + 0.55 å V in,min 85 Ǹ2 å N sp + 0.167 Ǹ2P )p For our LED driver, we decide to have a duty-cycle around 55% at Vout,max and Vin,min: 0.55 P out,max h f *(V out,max ) V f) Ǹ2 V (eq. 40) h Using equations (40) and (41), we can calculate the maximum peak current and the primary inductance of the flyback transformer: in,min V out,max)V out,maxC lumpF sw,min ) h is the estimated efficiency of the power supply The duty-cycle varies with the output load and the input voltage. In reality, we cannot have D > 0.5 for all input voltage/output loading conditions. Thus, we will design the transformer in order to have a duty cycle greater than 50% at a chosen operating point, for example maximum output load and minimum input voltage. N sp t Ǔ N sp 1 ) Ǹ V out(OVP) ) V f V in,min 2 *V ripple Where: Vripple is the bulk voltage ripple Clump is the total capacitor at the drain node of the MOFSET. For a first approximation, we can use COSS value. Vout(OVP) is the output voltage at which the over voltage protection must triggers The constant current algorithm implemented in the NCL3008X provides a better regulation of the output current if the duty-cycle of the MOSFET is equal or above 50%. The duty-cycle of a quasi-square wave resonant flyback converter operated in the 1st valley can be calculated with: V out,max)V Ǹ2P ǒ Lp + Turn Ratio Calculation V out ) v f D+ N spV in ) V out ) V f P out,max h Ǹ2 28 0.5 50p 0.85 50k å I L,pk + 0.59 A (eq. 42) Lp + (eq. 39) Maximum Primary Peak Current and Inductance 2P out,max 2 I L,pk F sw,min h + å L p + 1900 mH The peak current is highest at minimum input voltage and maximum output load Pout,max. By selecting a switching www.onsemi.com 10 2 0.59 2 28 0.5 å 50k 0.84 (eq. 43) AND9131/D Choosing the MOSFET Breakdown Voltage BVdss 15% derating Vds,max Vos Vclamp Vreflect Vbulk,max Figure 13. MOSFET Drain-source Voltage at High Line Figure 13 shows the waveform of the drain-source voltage of a MOSFET operated in the 1st valley. We can estimate the maximum voltage reached on the drain node, considering Vout(OVP) level as the maximum output voltage: V ds,max + V in,max Ǹ2 ) (V out(OVP) ) V f) N sp k c ) V os Using (eq.44), we calculate the MOSFET Vds,max in our design: V ds,max + V in,max Ǹ2 ) + 265 Ǹ2 ) (eq. 44) k c ) V os + (28 ) 0.6) 1.6 ) 20 + 668 V 0.167 Looking at Table 3, we select an 800 V MOSFET. Choosing the MOSFET RDSon Space is very limited in a LED bulb, and there is no space to add a heatsink for the power MOSET or the output rectifier. Thus, the MOSFET will be chosen such that it can dissipate the power in all conditions without using a heatsink. Knowing the chosen package thermal resistance RqJA, we first calculate the power that can be dissipated by this package at a chosen maximum ambient temperature TA(MAX). After calculating the maximum drain-source voltage, we apply a safety factor of 15% in order to select the breakdown voltage of the MOSFET, meaning that: V ds,max (1*0.15) N sp (eq. 46) Where: kc is the clamping coefficient (kc = Vclamp / Vreflect) [1]. kc should be keep in the range of 1.3 to 1.5 times the reflected voltage. Vos is the drain voltage overshoot caused by the clamping diode recovery time. B Vdss w (V out(OVP) ) V f) (eq. 45) The following table gives the maximum drain-source voltage considering a 15% derating factor for MOSFET breakdown voltage found on the market. P pack + Maximum drain-source voltage (Vds,max) 500 V 425 V 600 V 510 V 650 V 553 V 800 V 680 V (eq. 47) In a quasi-square wave resonant power supply operating at low line and full load, the MOSFET losses are mainly conduction losses. The MOSFET RDSon at TJ(MAX) can be estimated: Table 3. Vds,max AFTER 15% DERATING HAS BEEN APPLIED TO BVdss Breakdown Voltage (BVdss) T J(MAX)*T A(MAX) R qJA R + DSonǒT JǓ I P pack 2 (eq. 48) pri,rms In equation (48), Ipri,rms is the rms current in the primary side of the flyback transformer at lowest input voltage and full output load: www.onsemi.com 11 AND9131/D I pri,rms + I L,pk Ǹǒ 1 3 I L,pk L p F sw,min Ǹ2 *V V in,min ripple Ǔ (eq. 49) We choose a TO-220FP isolated package for the MOSFET. From the manufacturer datasheet, we have: RqJA = 62.5°C/W. We consider a maximum junction temperature of 125°C for this device. The maximum ambient temperature is 80°C. P pack + T J(MAX)*T A(MAX) + 125*80 + 0.72 W 62.5 R qJA (eq. 50) The primary peak current and the primary inductance have been calculated in (42) and (43). We can deduce the primary rms current value: I pri,rms + I L,pk Ǹǒ + 0.62 1 3 I L,pk L p F sw,min Ǹ2 *V V in,min ripple Ǔ Vf1, If1 Vf2, If2 + (eq. 51) Ǹǒ Ǔ 1 0.59 1900m 50k + 0.268 A 3 82 Ǹ2 *30 We deduce the RDSon value at TJ = 125°C: R DSon(125 oC) + P pack I pri,rms 2 + 0.72 2 + 10 W 0.268 (eq. 52) The MOSFET manufacturers generally specify the RDSon at 25°C. The RDSon value at 25°C is roughly half the value at TJ = 125°C, so we will choose a MOSFET with a RDSon(25°C) ≤ 5 W. Selecting the Output Diode Figure 14. MURS220 Curves In order to select the output diode, it is important to consider also the losses caused by the secondary rms current which interact with the diode dynamic resistance rd: P diode + V f I out ) r d I sec,rms 2 Look at the forward voltage drop at If1 = Iout, then choose an operating point slightly below the previous one and note Vf2, If2. From these values, you can calculate the dynamic resistance: (eq. 53) The diode dynamic resistance can be extracted from the I-V curves drawn in the datasheet of the diode or measured. rd + www.onsemi.com 12 V f1*V f2 I f1*I f2 (eq. 54) AND9131/D We choose a MURS220 diode in SMB package. We extract its dynamic resistance from the curves in Figure 14: rd = 167 mW. The rms value of the current circulating in the secondary side of the transformer is: I sec,rms + I L,pk N sp + 0.59 0.167 Ǹǒ 1 3 1* I L,pk L p F sw,min Ǹ2 *V V in,min ripple Ǔ Considering a thermal resistance RqJA = 100°C/W for the SMB package and a maximum junction temperature of 150°C for the diode, we calculate the power dissipation of the package using (eq. 47): P pack + + Since the worst case power losses in the output diode is 0.59 W and the package can dissipate 0.7 W at an ambient temperature of 80°C, we can consider our design safe. (eq. 55) Ǹǒ Ǔ 1 1* 0.59 1900m 50k + 1.25 A 3 82 Ǹ2 *30 Conclusion This application note provides the key equations and design criteria to dimension a primary-side constant current flyback converter operated by the NCL30080/81/82/83. The design method is illustrated by an implementation of a 12 W, wide mains LED driver. Table 4 summarizes the equations useful to select the components around the NCL3008X controllers. For detailed information on the performance of the 10 W LED driver designed in this document, you can refer to AND9132/D [2]. The forward voltage drop of the MURS220 diode at Iout = 0.5 A and TJ = 100°C is 0.65 V (Figure 14). We can deduce the power dissipated by the diode: 2 P diode + V f I out ) r d I sec,rms + + 0.65 0.5 ) 0.167 T J(MAX)*T A(MAX) + 150*80 + 0.7 W (eq. 57) 100 R qJA (eq. 56) 1.25 2 + 0.59 W When selecting the output diode, the power supply designer must ensure that the diode package is able to dissipate the calculated power: Ppack > Pdiode. Table 4. GENERAL EQUATIONS SUMMARY ZCD Pin ZCD Pin Resistor R ZCD w max SD Pin NTC Bx Coefficient and Resistance at 25°C Bx + ǒ e VIN Pin Bx ǒ 11.76k 1 T TFstart C SD v 4.7 nF SD Pin Capacitor ǒ LFF Resistor R LFF + 1 ) CS Pin Capacitor 10 – 100 pF Lower Resistor 10 – 100 kW Upper Resistor R BOU + R BOL DIM Pin Output Current Variation with DIM Pin Voltage Startup Network VCC Capacitor Ǔ V aux(high) V aux(low) , 5m 2m T OTPT TFstart ln 11.76k T OTP*T TFstart 5.88k R 25 + CS Pin ǒ 1 25)273 Ǔ Ǔ R BOU t pro pR sense R BOL L p17m ǒ V in(start) Ǹ2 *1 V BO(on) Ǔ I out(%) + 100 V DIM*0.4 175 C Vcc w (I CC2 ) Q g F sw)t reg V CC(on),min*V CC(off),max Startup Resistor R startup + V in,min Ǹ2 I Cvcc ) 14m (Bulk connection) R startupńp (Half-wave connection) I start w 60 mA ! Startup Current www.onsemi.com 13 Ǔ AND9131/D Table 4. GENERAL EQUATIONS SUMMARY (continued) Sense Resistor Set the Output Current Value Transformer Design Turn-ratio R sense + 0.25 2 N sp I out V out,max)V f *(V out,max ) V f) Ǹ2 V 0.5 N sp t in,min Maximum Primary Peak Current I L,pk + 2 P out,max h )p Primary Inductance MOSFET Selection Lp + Breakdown Voltage Ǹ2P ǒ out,maxC lumpF sw,min h 2P out,max 2 I L,pk F sw,min h B Vdss w V ds,max (1*0.15) V ds,max + V in,max Ǹ2 ) RDS(on) at TJ = 125°C R DSon(125 oC) + I pri,rms + I L,pk P pack + Output Diode Diode Losses Ǔ N sp 1 ) V in,min Ǹ2 *V ripple V out(OVP) ) V f (V out(OVP) ) V f) N sp P pack I pri,rms 2 Ǹǒ 1 3 I L,pk L p F sw,min Ǹ2 *V V in,min I sec,rms + 14 ripple Ǔ 125*T A(MAX) R qJA P diode + V f I out ) r d I sec,rms www.onsemi.com k c ) V os I L,pk N sp Ǹǒ 1 3 1* 2 I L,pk L p F sw,min Ǹ2 *V V in,min ripple Ǔ ) AND9131/D REFERENCES [1] Christophe Basso, “Switch-mode Power Supplies”, McGraw-Hill, 2008. [2] Stephanie Cannenterre, “Performance of a 10 W LED driver controlled by the NCL30080-81-82-83”, AND9132/D ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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