AND8431/D Designing a Quasi-Resonant Adaptor Driven by the NCP1380 Prepared by Stéphanie CONSEIL http://onsemi.com ON Semiconductor APPLICATION NOTE Quasi−square wave resonant converters also known as Quasi−Resonant (QR) converter are widely used in the adaptor market. They allow designing flyback Switched−Mode Power Supply (SMPS) with reduced Electro−Magnetic Interference (EMI) signature and improved efficiency. However, as the switching frequency of QR converter increases as the load decreases, the frequency must be limited. In traditional QR converter, the frequency is limited by a frequency clamp. But, when the switching frequency of the system reaches the frequency clamp limit, valley jumping occurs: the controller hesitates between two valleys resulting in an unstable operation and noise in the transformer at medium and light output loads. In order to overcome this problem, the NCP1380 and the NCP1379 feature a “valley lockout” circuit: the switching frequency is decreased step by step by changing valley as the load decreases. Once the controller selects a valley, it stays locked in this valley until the output power changes significantly. This technique extends the QR operation of the system towards lighter loads without degrading the efficiency. This application note focuses on the design of an adapter driven by the NCP1380. The equations developed are further used to design a 60 W adapter. The same equations can be applied to the NCP1379. HV−bulk R clamp R zcd ZCD / OPP EMI Filter Cbulk D1 GND NCP1380 A/B 1 8 2 7 3 6 4 5 Vout Cout D clamp R stup R opu Ac line C clamp R led OVP M1 R upper Czero OTP R opl C zcd Cfb R sense Ct C VCC1 CVCC2 Figure 1. Application Schematic for Versions A and B © Semiconductor Components Industries, LLC, 2009 December, 2009 − Rev. 1 1 R lower GND Publication Order Number: AND8431/D AND8431/D HV−bulk R clamp R zcd ZCD / OPP EMI Filter D1 Cbulk Rstup Rbou NCP1380 C/D 1 8 2 7 3 6 4 5 Vout Cout D clamp R opu Ac line C clamp GND R led OVP M1 R upper Czero BO R opl C zcd Cfb Ct C VCC1 Rbol CVCC2 Figure 2. Application Schematic for Versions C and D R sense R lower GND Introduction The NCP1379 and NCP1380 implement a standard current−mode architecture operating in quasi−resonance. Due to a proprietary circuitry, the controller prevents valley−jumping instability and steadily locks out in selected valley as the power demand goes down. Once the fourth valley is reached, the controller continues to reduce the frequency further down, offering excellent efficiency over a wide operating range. Due to a fault timer combined to an OPP circuitry, the controller is able to efficiently limit the output power at high−line. • Quasi−Resonance Current−mode operation: implementing quasi−resonance operation in peak current−mode control, the NCP1379 and NCP1380 optimize the efficiency by switching in the valley of the MOSFET drain−source voltage. Due to a proprietary circuitry, the controller locks−out in a selected valley and remains locked until the output loading significantly changes. When the load becomes lighter, the controller jumps into the next valley. It can go down to the 4th valley if necessary. Beyond this point, the controller reduces its switching frequency by freezing the peak current setpoint. During quasi−resonance operation, in case of very damped valleys, a 5.5 ms timer emulates the missing valleys. • Frequency reduction in light−load conditions: when the 4th valley is left, the controller reduces the switching frequency which naturally improves the standby power by a reduction of all switching losses. • Overpower protection (OPP): When the voltage on ZCD pin swings in flyback polarity, a direct image if the input voltage is applied on ZCD pin. We can thus reduce the peak current depending of VZCD during the on−time. • Internal soft−start: a soft−start precludes the main power switch from being stressed upon start−up. Its duration is fixed and equal to 4 ms. • Fault input (NCP1380 A and B versions): by combining a dual threshold on the Fault pin, the controller allows the direct connection of an NTC to ground plus a zener diode to a monitored voltage. In case the pin is brought below the OTP threshold by the NTC or above the OVP threshold by the zener diode, the circuit permanently latches−off and VCC is clamped to 7.2 V. • Fault input (NCP1380 C and D versions and NCP1379): the C and D versions of NCP1380 and the NCP1379 include a brown−out circuit which safely stops the controller in case the input voltage is too low. Restart occurs via a complete startup sequence (latch reset and soft−start). During normal operation, the voltage on this pin is clamped to Vclamp to give enough room for OVP detection. If the voltage on this pin increases above 2.5 V, the part latches−off. • Short−circuit protection: short−circuit and especially over−load protections are difficult to implement when a strong leakage inductance between auxiliary and power windings affects the transformer (where the auxiliary winding level does not properly collapse in presence of an output short). Here, when the internal 0.8 V maximum peak current limit is activated, the timer starts counting up. If the fault disappears, the timer counts down. If the timer reaches completion while the error flag is still present, the controller stops the pulses. This protection is latched on A and C version (the user must unplug and re−plug the power supply to restart the controller) and auto−recovery on B and D versions (if the fault disappears, the SMPS automatically resumes operation). In addition, all versions feature a winding short−circuit protection, that senses the CS signal and stops the controller if VCS reaches 1.5 x VILIM (after a reduced LEB of tBCS). This additional comparator is enabled only during the main LEB duration tLEB, for noise immunity reason. http://onsemi.com 2 AND8431/D Specifications of the Adapter In order to illustrate this application note, a 19 V, 60 W adapter will be the design example. The specifications are detailed in Table 1. Table 1. SPECIFICATIONS OF THE 19 V, 60 W ADAPTER Parameter Symbol Value Minimum input voltage Vin(min) 85 Vrms Maximum input voltage Vin(max) 265 Vrms Vout 19 V Pout(nom) 60 W Fsw 45 kHz Tstartup 3s Output voltage Nominal output power Switching frequency at Vin(min), Pout(nom) Maximum startup time The experimental results of the 60 W adapter are detailed in the application note NCP1380EVB/D [1]. For details concerning the QR transformer calculation, the power supply designer can refer to the tutorial TND348/D [2]. Predicting the Switching Frequency As the controller changes valley as the load decreases, the switching frequency of the power supply is naturally limited by the valley lockout. But equations are needed to predict the switching frequency evolution as the output power varies. The datasheet gives the FB thresholds at which the controller changes valley, depending if the output power increases or decreases. Figure 3. Operating Valley According to FB Voltage With these thresholds, we can calculate the maximum switching frequency inside each valley depending if the output power decreases or increases: F SW + ǒ V FB 4R sense ) V in(rms) Ǹ2 ǓL ǒ t prop Lp p 1 1 V in(rms) Ǹ2 ) Where: • VFB is the FB threshold at which the controller changes valley • • • • • • Rsense is the sense resistor value Vin(rms) is the rms value of the input voltage tprop is the propagation delay Lp is the primary inductance Vout is the output voltage Vf is the forward voltage drop of the output diode http://onsemi.com 3 N ps V )V out Ǔ f ) (1 ) 2n)p ǸL pC lump (eq. 1) AND8431/D • Clump regroups all capacitances surrounding the drain node (MOSFET capacitor, transformer parasitics...). As a first approximation, the MOSFET drain−source capacitance COSS can be used instead of Clump. • n is an integer representing the operating valley: n = 0 for 1st valley, n = 1 for 2nd valley, n = 2 for 3rd valley and n = 3 for the 4th valley. The corresponding output power can be calculated using the traditional formula: P out + ǒ Ǔ t prop V FB 1 Lp ) V in(rms) Ǹ2 2 4R sense Lp 2 F SWh (eq. 2) Using the previous equations, we can calculate the maxima of the switching frequency and the corresponding output power for our 60 W adapter. In order to help the power supply designer, the previous equations have been entered inside a Mathcad spreadsheet that automatically predicts the evolution of the switching frequency as a function of the output power (Figure 4). Figure 4. Switching Frequency versus Output Power at Vin = 90 Vrms VCO Mode 1. Operating Details At nominal power, the power supply operates in a variable frequency system where discrete frequency steps occur as the controller looks for the different valley positions. At low output power, the controller enters a Voltage−Controlled Oscillator (VCO) mode where the switching frequency is folded back. This mode is entered when VFB drops below 0.8 V. The controller remains in this mode until VFB increases above 1.4 V. During the VCO operation (VFB < 0.8 V), the peak current is frozen to 17.5% of its maximum value and the frequency diminishes as the output power decreases. http://onsemi.com 4 AND8431/D Figure 5. Idrain, Vdrain, VCt, at Different Output Loads in VCO Mode 2. Choosing the Timing Capacitor Ct The timing capacitor must be selected with care. Indeed, when the controller leaves the valley switching mode to enter the VCO mode, the frequency changes from a valley−position−controlled value to a switching frequency imposed by the Ct capacitor. If a too big gap exists between the switching frequency in the 4th valley and the switching frequency imposed by the Ct capacitor, the frequency jump may create instability: hesitation between 4th valley and the VCO mode takes place (Figure 6) and can create output ripple and noise. VFB Vdrain 4th valley VCO mode Figure 6. The Controller Hesitates Between VCO Mode and 4th Valley: Ct is Too Big! Figure 7 shows a normal transition from 4th valley to the VCO mode. At the beginning, the output load is such that it imposes a VFB near 0.8 V in 4th valley operation, with a switching period Tsw1. Then, if the load is slightly decreased, the FB voltage also passes below the 0.8 V threshold: the VCO mode is entered and the switching frequency decreases. (In VCO mode, the switching frequency is imposed by the FB voltage regardless of the position in the drain signal). The controller will stay in VCO mode until the FB voltage increases above 1.4 V. If we have an optimum timing capacitor value, the new steady state point is such that VFB is near 1.4 V and imposes a switching period Tsw2 larger than Tsw1. http://onsemi.com 5 AND8431/D Figure 7. 4th Valley to VCO Mode Transition with an Optimum Timing Capacitor Ct To calculate Ct, we first need to estimate the switching period at the end of the 4th valley operation, for a FB voltage near 0.8 V by using Equation 3 or by directly measuring it on our adapter: T SW + ǒ 0.8 4R sense ) V in(max) Ǹ2 Ǔ t prop Lp ǒ Lp 1 V in(max) Ǹ2 ) N ps Ǔ V out ) V f ) 7p ǸL pC lump (eq. 3) Where: • 0.8 is the FB voltage where the controller leaves the 4th valley and enter VCO mode. • Vin(max) is the maximum input voltage • Based on lab experiments, the switching period gap between the end of 4th valley operation (Tsw1) and VCO mode (Tsw2) for a FB voltage near 1.4 V (which is the threshold for VCO mode to 4th valley transition, VFB increasing ) must not exceed 10 ms. Thus, for VFB = 1.4 V, we will have: T SW2 + T SW1 ) 8 ms (eq. 4) In VCO mode, the timing capacitor voltage VCt is dependant of the FB voltage as follows: V Ct + 6.5 * 10 V 3 FB (eq. 5) The Equation 5 allows calculating VCt for VFB = 1.4 V: V Ct + 6.5 * (10ń3) 1.4 + 1.83 V (eq. 6) Thus, we can deduce the timing capacitor value knowing VCt, Tsw2 and the charging current source ICt (20 mA typ from datasheet): Ct + I CtT SW2 (eq. 7) 1.83 Application Example: 19 V, 60 W Adapter • • • • • • Vin(max) = 265 Vrms Vout + Vf = 19 + 0.8 V Lp = 285 mH Clump = 250 pF Nps = 0.25 Rsense = 0.23 http://onsemi.com 6 AND8431/D First, with Equation 3, we estimate Tsw1 which is the switching period of our power supply for an output load corresponding to a VFB = 0.8 V: T SW1 + + ǒ 0.8 4R sense ǒ4 Ǔ t prop ) V in(max) Ǹ2 Lp ǒ Lp 1 V in(max) Ǹ2 ) N ps ǒ Ǔ Ǔ V out ) V f ) 7p ǸL pC lump Ǔ 0.8 300x10 −9 0.25 1 ) 265 Ǹ2 285x10 −6 ) ) 7p Ǹ285x10 −6 −6 Ǹ 0.23 285x10 265 2 19 ) 0.8 250x10 −12 (eq. 8) + 10.7 msǒ93 kHzǓ When measured on the adapter we obtain: Tsw1 = 11.1 ms (Fsw1 = 90 kHz) which corresponds to an output power of 23 W. We calculate the timing capacitor value: Ct + I CtǒT SW1 ) 10mǓ 1.83 + 20x10 −6 ǒ10.7x10 −6 ) 10x10 −6Ǔ 1.83 (eq. 9) + 226 pF We select Ct = 200 pF. Zero Crossing Detection The NCP1380 combines on a single pin the inductor reset detection and the Over Power Protection (OPP). Zero crossing detection and OPP are achieved by observing the auxiliary winding voltage. The negative part of the voltage is used for the over power protection and the positive part is used for zero crossing detection. The schematic of the zero−crossing detection bloc is shown in Figure 8. R zcd R opu Vdd ZCD/OPP 1 R opl Aux C zcd + demag − 10 V ESD LOGIC BLOCK Vth leakage blanking DRV 3 us Pulse TimeOut SS end 5.5 ms time out SS end 40 ms time out Figure 8. Zero−Crossing Detection Bloc Schematic 1. Choosing the zero−crossing resistor (Rzcd) value In order to allow enough voltage on the ZCD pin during soft−start, the ratio between Rzcd and Ropl should be equal to 1 or lower than 1: R zcd R opl v1 (eq. 10) Practically, we recommended a value of 1 kW for Rzcd and to keep the value of Ropl in the range of 1 kW to 3 kW. http://onsemi.com 7 AND8431/D 2. Time Out In case of extremely damped free oscillations, the ZCD comparator can be unable to detect the valleys. To avoid such situation, NCP1380 integrates a Time Out function that acts as a substitute clock for the decimal counter inside the logic bloc. The controller thus continues its normal operation. To avoid having a too big step in frequency, the time−out duration is set to 5.5 ms. The NCP1380 also features an extended time out during the soft−start. Indeed, at startup, the output voltage reflected on the auxiliary winding is low. Because of the voltage drop introduced by the Over Power Compensation diode (Figure 9) the voltage on the ZCD pin is very low and the ZCD comparator might be unable to detect the valleys. In this condition, setting the DRV Latch with the normal 5 ms time−out leads to a continuous conduction mode operation (CCM) at the beginning of the soft−start. This CCM operation only last a few cycles until the voltage on ZCD pin becomes high enough to be detected by the ZCD comparator. To avoid this, the time−out duration is extended to 40 ms during the soft−start in order to ensure that the transformer is fully demagnetized before the MOSFET is turned−on. Over Power Protection 1. Operating Details A flyback operated in Quasi Resonance exhibits wide peak current variations in relationship to the input voltage conditions. As a result, the converter output power range widens as the input voltage increases. To cope with safety requirements, the designer needs to limit the power output capability over the input voltage range. A possible way of doing it is call Over Power Protection (OPP). Please note that a quasi−resonant converter output power cannot be limited to a very tight range for a universal input voltage specification (85 Vrms to 265 Vrms). Indeed, the quasi−resonance mode exhibits high current slope in the transformer, causing wide peak current variation over the input voltage range compared to a Continuous Conduction Mode (CCM) design. Thus, if a very tight range for the output power capability is needed, the power supply designer should use a CCM design. The novel technique implemented in the NCP1380 and the NCP1379 takes benefits of the auxiliary winding voltage whose negative amplitude relates to the input rail voltage. When the power MOSFET is conducting, the auxiliary winding voltage becomes the input voltage Vin affected by the auxiliary to primary turn ratio (Np,aux = Naux/Np): V aux + −N p,auxV in (eq. 11) By applying this voltage through a resistor divider on the ZCD pin, we have an image of the input voltage transferred to the controller via this pin. This voltage is added internally to the 0.8 V reference and affects the maximum peak current (Figure 9). As the OPP voltage is negative, an increase of input voltage implies a decrease of the maximum peak current setpoint: V CS(max) + 0.8 ) V OPP (eq. 12) R zcd R opu CS ZC D /OPP OPP IpFlag 1 R opl Au x C zcd ESD pr ot ect ion V IL IMIT + − Vth leakage blanking Tblank DRV Figure 9. ZCD and OPP Circuit http://onsemi.com 8 Demag AND8431/D The maximum OPP voltage that can be applied to ZCD pin is –300 mV, which corresponds to a peak current decrease of 37.5%. In order to avoid saturating the input transistors of the OPP comparator, the positive voltage excursion on the ZCD pin must also be limited. Thus, we recommend adding a diode between ZCD and GND to limit the positive voltage to 0.6 V. This is not mandatory, but if higher positives voltages are applied to this pin, the propagation delay of the OPP comparator will increase. 2. Calculating the needed OPP amount for the design Because of the propagation delay, the maximum peak current at high line is: I pk(high) + 0.8 R sense The corresponding switching period and output power are: ǒ T SW(high) + I pk(high)L p 1 V in(max),dc P out(high) + ) N ps t prop ) V in(max),dc Ǔ V out ) V f (eq. 13) Lp ) p ǸL pC lump (eq. 14) 1 1 L pI pk(high) 2 h 2 T SW(high) (eq. 15) We would like to limit the output power to Pout(limit) > Pout(nom) at maximum input voltage. In order to perform over power compensation, we need to calculate the peak current Ipk(limit) corresponding to Pout(limit). ǒ Lp V 1 in(max),dc )V N ps )V out I pk(limit) + Ǔ ) ǸL ǒ 2 p f 1 V in(max),dc )V )V out Ǔ )2 2 N ps f L ph P out(limit) p ǸL pC lump (eq. 16) L ph P The amount of OPP voltage needed is thus: out(limit) ǒ V OPP + 0.8 1 * I pk(limit) I pk(max) Ǔ (eq. 17) As an example, in order to provide a 15% power margin to our 60 W adapter, we want to limit the output power to 70 W at high line. Using Equations 13 to 15, we obtain: I pk(high) + 0.8 4R sense ǒ T SW(high) + I pk(high)L p + 4.32 P out(high) + ) V in(max),dc 1 V in(max),dc 285x10 −6 ǒ ) N ps t prop + Lp Ǔ V out ) V f 0.8 600x10 −9 ) 375 + 4.32 A 4 0.23 285x10 −6 (eq. 18) ) p ǸL pC lump (eq. 19) Ǔ 0.25 1 ) ) p Ǹ285x10 −6 375 19 ) 0.8 1 1 1 L pI pk(high) 2 h + 285x10 −6 2 2 T SW(high) 4.32 2 250x10 −12 + 19.5 ms 1 19.5x10 −6 0.85 + 116 W (eq. 20) If no over power compensation is applied, the adapter will be able to deliver 116 W at high line! In order to limit the output power to 70 W at 265 Vrms, the peak current must be reduced to: http://onsemi.com 9 AND8431/D L ǒ p V 1 in(max),dc I pk(limit) + )V N ps Ǔ ) ǸL ǒ p out)V f 2 1 V in(max),dc Ǔ )2 2 L ph P out)V f out(limit) p ǸL pC lump L ph P 285x10 −6ǒ375 ) 19)0.8Ǔ ) 0.25 1 + )V N ps Ǹǒ285x10 −6Ǔ (eq. 21) out(limit) 2 1 0.25 ǒ375 ) 19)8 Ǔ 2 )2 285x10 −6 0.85 70 p Ǹ285x10 −6 250x10 −12 285x10 −6 0.85 70 + 2.67 A The amount of OPP voltage that must be applied to the design is: ǒ V OPP + 0.8 1 * I pk(limit) I pk(max) Ǔ ǒ + 0.8 1 * Ǔ 2.67 + 300 mV 4.32 (eq. 22) 3. Calculating the OPP resistors Looking at Figure 9, if we apply the resistor divider law on the pin 1 during the on−time, we obtain the following relationship: R zcd ) R opu R opl + N p,auxV in,dc * V OPP (eq. 23) V OPP By choosing a value for Ropl (for example 1 kW), we can easily deduce Ropu as we already know Rzcd value. Following our example from before, we need 300 mV of OPP voltage to limit the output power to 70 W at 265 Vrms. We choose: Ropl = 1 kW R opu + N p,auxV in,dc * V OPP V OPP R opl * R zcd + 0.18 375 * (0.3) (0.3) 1000 * 1000 + 223 kW (eq. 24) Finally, we choose a 220 kW resistor for Ropu. 4. A Non−Dissipative OPP The input voltage information is given by the auxiliary winding which offers lower voltage values compared to the bulk rail. In addition, in VCO mode, the switching frequency expands. Thus, the average current in the OPP bridge decreases. Let us calculate the average current circulating in the OPP bridge at light load: T SW I bridge(mean) + 1 T SW ŕŤ 0 V aux(t) Ť R zcd ) R opu ) R opl dt (eq. 25) We obtain: I bridge(mean) + t off t on 1 1 ǒV ) VfǓ N p,auxV in Ǹ2 ) R zcd ) R opu ) R opl T SW R opu ) R opl T SW CC (eq. 26) On our 60 W adapter, for an output power of 4 W, we measured: • ton = 1.2 ms • toff = 3.6 ms • Tsw = 40 ms • VCC + Vf = 12 V We can calculate the OPP bridge current at highest input voltage (265 Vrms): I bridge(mean) + + T off t on 1 1 ǒV ) VfǓ N p,auxV in Ǹ2 ) R zcd ) R opu ) R opl T SW R opu ) R opl T SW CC 1.2m 1 0.18 220k ) 1k ) 1k 40m 265 Ǹ2 ) 3.6m 1 12 + 14 mA 220k ) 1k 40m As the bridge current is very low, the power dissipated by the OPP bridge can be neglected. http://onsemi.com 10 (eq. 27) AND8431/D Startup Network for NCP1380 The NCP1379 has a low VCC(on) threshold (around 12 V), allowing to use an auxiliary power supply to bias the controller. Also, the NCP1379 will consume much current during the startup phase (1.2 mA), thus if the power designer wants to use startup resistors instead of an auxiliary power supply, the power dissipated in the startup resistors will be high. On the contrary, the NCP1380 has an higher VCC(on) threshold but consumes a very low current during the startup (10 mA typ, 20 mA max). Thus, high values of startup resistors can be used leading to lower power dissipation in the startup network. The startup resistor Rstartup can either be connected to the bulk rail or to half−wave (Figure 10). Connecting the startup resistor to the half−wave allows decreasing the power dissipated in the startup resistor. Figure 10. The Startup Resistor can be Connected to the Bulk Rail or to the Half Wave 1. Calculating the Startup Capacitor The startup capacitor is calculated to allow the power supply to close the loop before VCC falls below VCC(off). Thus, CVcc must be able to supply the controller alone during a limited time treg (Figure 11). Figure 11. VCC Waveform During Startup The startup capacitor value can be calculated as follows: C VCC + ǒI CC3A ) Q gFSWǓtreg V CC(on) * V CC(off) http://onsemi.com 11 (eq. 28) AND8431/D The current needed to charge CVcc alone during the startup is: V CC(on)C VCC I CVCC + (eq. 29) t startup Design Example: For our 19 V, 60 W adapter, we chose a 9 A, 600 V MOSFET (IPA60R385 from Infineon). The total gate charge is: Qg = 17 nC The switching frequency at low line, maximum output load is: Fsw = 45 kHz The total startup time of the adapter must be below 3 s. We will consider a startup time tstartup of 2.8 s. The value of treg can be estimated around 10 ms. From the datasheet, we can extract the values of the following parameters: ICC3A = 2.4 mA VCC(on) = 17 V VCC(off) = 9 V We can deduce: C VCC + ǒI CC3A ) Q gFSWǓtreg V CC(on) * V CC(off) + (2.4m ) 17n 45000) 17 * 9 10m + 3.9 mF (eq. 30) We choose a 4.7 mF capacitor for CVcc. The current needed to charge CVcc is: I CVCC + V CC(on)C VCC t startup + 17 4.7m 2.8 (eq. 31) + 28.5 mA 2. Startup Resistor Calculation *Bulk connection If the resistor is connected to the bulk rail, the following formula can be use to calculate its value: R startup + V in(min) Ǹ2 (eq. 32) I CVCC ) I CC(start) Where: • ICvcc is the current needed to charge the VCC pin capacitor • ICC(start) is the current consumed by the controller during startup • Vin(min) is the minimum input voltage The power dissipated by the startup resistor connected to the bulk rail is: *Half−wave connection If the resistor is connected to the half−wave: V R startup1ń2 + Ǹ2 in(min) p I CVCC ) I CC(start) + R startup (eq. 33) p The power dissipated by the startup resistor connected to the half−wave is thus: P startup1ń2 + ǒ V in(max) p Ǹ2 R startup1ń2 http://onsemi.com 12 Ǔ * V CC 2 (eq. 34) AND8431/D Design Example: From the datasheet, the maximum value of ICC(start) is 20 mA. We will consider a typical value of 15 mA for this parameter. In standby, the supply voltage of the controller decreases to 11 V. We deduce: V in(min) Ǹ2 R startup + + I CVCC ) I CC(start) V R startup1ń2 + 85 Ǹ2 28.5m ) 10m Ǹ2 I CVCC ) I CC(start) + (eq. 35) [ 1 MW (eq. 36) 85Ǹ2 p in(min) p [ 3.2 MW 28.5m ) 10m The power dissipated for each resistor is: P startup + ǒVin(max) Ǹ2 * VCCǓ 2 R startup ǒ P startup1ń2 + V in(max) p Ǹ2 Ǔ + 3.2x10 6 2 + 44 mW (eq. 37) 2 * V CC R startup1ń2 ǒ265 Ǹ2 * 11Ǔ + ǒ 265Ǹ2 p Ǔ * 11 1x10 6 2 (eq. 38) + 14 mW Connecting the startup resistor to the half−wave allows saving 30 mW! Fault Pin The Fault pin combines different safety features in order to provide compact design of power supply. The safeties provided vary according to the version of the NCP1380 or NCP1379. Table 2 summarizes the possible combinations: Table 2. NCP1379 AND NCP1380 FAULT PIN OPTIONS Over Voltage Protection Over Temperature Protection Brown−Out NCP1379 3 NCP1380 A 3 3 NCP1380 B 3 3 NCP1380 C 3 3 NCP1380 D 3 3 3 1. Over Temperature Protection The adapter operating in a confined area, e.g. the plastic case protecting the converter, it is important to look after the internal ambient temperature. If this temperature would increase beyond a certain point, catastrophic failures could occur through semiconductors thermal runaway or transformer saturation. To prevent this from happening, the versions A and B of the NCP1380 embed an Over Temperature Protection (OTP) circuitry which can be combined with an Over Voltage Protection appearing in Figure 12. http://onsemi.com 13 AND8431/D Figure 12. OTP/OVP Combination in NCP1380 A and B Versions The IOTP(REF) current (91 mA typ.) biases the Negative Temperature Coefficient sensor (NTC), naturally imposing a dc voltage on the OTP pin. When the temperature increases, the NTC’s resistance reduces bringing the pin 7 voltage down until it reaches a typical value of 0.8 V: the comparator trips and latches−off the controller. During the latch−off phase, the VCC is pulled down to 7.2 V by an internal clamp circuit. The controller reset occurs when the current circulating in the VCC pin drop below 30 mA or when the VCC is cycled from on to off. During start−up and soft−start, the output of the OTP comparator is masked to allow the voltage on pin OTP to grow if a filtering capacitor is installed across the NTC. The filtering capacitor value should be 1 nF. In the NCP1380, the OTP trip point corresponds to a resistance of: R NTC + V OTP I OTP(REF) + 0.8 + 8.79 kW 91m (eq. 39) 2. Brown−Out The NCP1379, the C and D versions of NCP1380 feature a Brown−Out (BO) circuit which protects the power supply against low input voltage conditions (Figure 13). The Brown−Out function is combined with an Over voltage Protection on pin 7. This pin permanently monitors a fraction of the bulk voltage through a voltage divider. When this image of bulk voltage is below the BO threshold, the controller stops switching. When the bulk voltage comes back within safe limits, the circuit goes through a new startup sequence including soft−start and re−starts switching. The hysteresis on brown−out pin is implemented with a high side current source sinking 10 mA when the brown−out comparator is high (Vbulk > Vbulk(on)). Figure 13. BO / OVP Combination in NCP1379, NCP1380 C and D Versions http://onsemi.com 14 AND8431/D Calculating the BO Resistors The following equations show how to calculate the brownout resistors. First of all, select the bulk voltage value at which the controller must start switching (Vbulk(on)) and the bulk voltage for shutdown (Vbulk(off)). Then use the following equation to calculate Rbou and Rbol. R bol + R bou + V BOǒV bulk(on) * V bulk(off)Ǔ (eq. 40) I BOǒV bulk(on) * V BOǓ R bolǒV bulk(on) * V BOǓ (eq. 41) V BO Design example • VBO = 0.8 V • IBO = 10 mA • Vbulk(on) = 110 V • Vbulk(off) = 50 V R bol + R bou + V BOǒV bulk(on) * V bulk(off)Ǔ I BOǒV bulk(on) * V BOǓ R bolǒV bulk(on) * V BOǓ V BO + + 0.8(110 * 50) 10x10 −6(110 * 0.8) 43.9x10 3(110 * 0.8) 0.8 + 43.9 kW (eq. 42) (eq. 43) + 6.0 MW 3. Over Voltage Protection The NCP1379 and the NCP1380 features a protection against an over voltage condition, e.g in case of the optocoupler destruction. This over voltage protection is combined either with an OTP or a BO protection, as shown previously on Figures 12 and 13. Only a zener diode needs to be added between the VCC rail and the Fault pin in order to detect an over voltage condition. In case of over voltage, the zener diode starts to conduct and inject current inside the internal clamp resistor Rclamp thus causing the pin 7 voltage to increase. When this voltage reaches the OVP threshold (2.5 V typ), the controller is latched−off. The amount of current that must be injected inside the controller by the zener diode depends on the circuit version and can be calculated as follows: I Fault + V OVP * V Clamp (eq. 44) R Clamp Thus, for the NCP1379 and the NCP1380 C&D, the amount of current needed is: I Fault + V OVP * V Clamp R Clamp + 2.5 * 1.2 1.6x10 3 + 812.5 mA (eq. 45) For the versions A and B of the NCP1380, the amount of current to be injected in the pin Fault is: I Fault + V OVP * V Clamp R Clamp + 2.5 * 1.35 1.6x10 3 + 719 mA (eq. 46) Note: In the NCP1379, the internal latch is reset either by a BO condition or when VCC falls below VCC(reset). Conclusion This application note has described the equations needed to design a QR adapter driven by the NCP1380. These equations can be applied to the NCP1379. All the equations presented have been implemented inside a Mathcad spreadsheet that can be downloaded from our website: http://www.onsemi.com/ References 1. Stéphanie Conseil, “Performances of a 60 W Quasi−resonant adapter driven by the NCP1380”, Application Note NCP1380EVB/D. 2. Stéphanie Conseil, “QR − Analysis and Design of Quasi−Resonant Converters”, Tutorial TND348/D. http://onsemi.com 15 AND8431/D ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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