MC100LVELT23 D

MC100LVELT23
3.3 V Dual Differential
LVPECL/LVDS to LVTTL
Translator
Description
The MC100LVELT23 is a dual differential LVPECL/LVDS to
LVTTL translator. Because LVPECL (Positive ECL) or LVDS levels
are used only +3.3 V and ground are required. The small outline 8-lead
package and the dual gate design of the LVELT23 makes it ideal for
applications which require the translation of a clock and a data signal.
The LVELT23 is available in only the ECL 100K standard. Since
there are no LVPECL outputs or an external VBB reference, the
LVELT23 does not require both ECL standard versions. The LVPECL
inputs are differential. Therefore, the MC100LVELT23 can accept any
standard differential LVPECL input referenced from a VCC of +3.3 V.
Features
•
•
•
•
MARKING
DIAGRAMS*
8
8
1
SOIC−8
D SUFFIX
CASE 751
1
8
8
2.0 ns Typical Propagation Delay
Maximum Frequency > 180 MHz
Differential LVPECL Inputs
PECL Mode Operating Range:VCC = 3.0 V to 3.8 V
with GND = 0 V
24 mA LVTTL Outputs
Flow Through Pinouts
Internal Pulldown and Pullup Resistors
Pb−Free Packages are Available
KVT23
ALYW
G
1
TSSOP−8
DT SUFFIX
CASE 948R
1
KR23
ALYWG
G
4J M G
G
•
•
•
•
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1
1
4
DFN8
MN SUFFIX
CASE 506AA
A
L
Y
W
M
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2010
August, 2010 − Rev. 18
1
Publication Order Number:
MC100LVELT23/D
MC100LVELT23
Table 1. PIN DESCRIPTION
D0
D0
1
8
2
LVPECL
VCC
7
Q0
Pin
Q0, Q1
D0*, D1*
D0*, D1*
VCC
GND
EP
LVTTL
D1
3
6
Q1
D1
4
5
GND
Function
LVTTL Outputs
Differential LVPECL Inputs
Positive Supply
Ground
(DFN8 only) Thermal exposed pad must
be connected to a sufficient thermal conduit. Electrically connect to the most negative supply (GND) or leave unconnected, floating open.
** Pins will default to VCC/2 when left open.
Figure 1. 8−Lead Pinout (Top View)
and Logic Diagram
Table 2. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
50 kW
Internal Input Pullup Resistor
50 kW
ESD Protection
Human Body Model
Machine Model
CDM
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
> 1500 V
> 100 V
> 2000 V
Level 1
UL 94 V−0 @ 0.125 in
91
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. Refer to Application Note AND8003/D for additional information.
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2
MC100LVELT23
Table 3. MAXIMUM RATINGS
Symbol
Rating
Unit
VCC
PECL Power Supply
Parameter
GND = 0 V
Condition 1
3.8
V
VI
Input Voltage
GND = 0 V,
VI not more positive than VCC
3.8
V
Iout
Output Current
Continuous
Surge
50
100
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
SOIC−8
SOIC−8
190
130
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
SOIC−8
41 to 44 ± 5%
°C/W
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
TSSOP−8
TSSOP−8
185
140
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
TSSOP−8
41 to 44 ± 5%
°C/W
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
DFN8
DFN8
129
84
°C/W
°C/W
Tsol
Wave Solder
<2 to 3 sec @ 248°C
<2 to 3 sec @ 260°C
265
265
°C
qJC
Thermal Resistance (Junction−to−Case)
35 to 40
°C/W
Pb
Pb−Free
Condition 2
(Note 2)
DFN8
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)
Table 4. LVPECL INPUT DC CHARACTERISTICS VCC = 3.3 V; GND = 0 V (Note 3)
−40°C
Symbol
Characteristic
25°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
10
20
35
10
20
35
10
20
35
mA
15
27
40
15
27
40
15
27
40
mA
2420
2135
2420
2135
2420
mV
1825
1490
1825
1490
1825
mV
VCC
1.2
VCC
1.2
VCC
V
150
mA
ICCH
Power Supply Current (Outputs set to HIGH)
ICCL
Power Supply Current (Outputs set to LOW)
VIH
Input HIGH Voltage (Note 5)
2135
VIL
Input LOW Voltage (Note 5)
1490
VIHCMR
Input HIGH Voltage Common Mode Range
(Notes 4 and 5)
1.2
IIH
Input HIGH Current
IIL
Input LOW Current
150
D
85°C
−150
150
−150
−150
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. All values vary 1:1 with VCC. VCC can vary ±0.3 V.
4. VIHCMR min varies 1:1 with GND, max varies 1:1 with VCC.
5. LVTTL output RL = 500 W to GND.
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MC100LVELT23
Table 5. LVTTL OUTPUT DC CHARACTERISTICS VCC = 3.3 V; GND = 0V (Note 6)
−40°C
Characteristic
Min
VOH
Output HIGH Voltage (IOH = −3.0 mA) (Note 7)
2.4
VOL
Output LOW Voltage (IOL = 24 mA) (Note 7)
IOS
Output Short Circuit Current
Symbol
Typ
25°C
Max
Min
85°C
Typ
Max
2.4
−50
Typ
Max
2.4
0.5
−180
Min
V
0.5
−180
−50
Unit
−180
0.5
V
−50
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
6. All values vary 1:1 with VCC. VCC can vary ±0.3 V.
7. LVTTL output RL = 500 W to GND.
Table 6. AC CHARACTERISTICS VCC = 3.3 V; GND = 0 V (Notes 8, 9)
−40°C
Symbol
Min
Characteristic
Fmax
Maximum Toggle Frequency (Note 10)
180
tPLH,
tPHL
Propagation Delay to
Output Differential
1.0
tSK+ +
tSK− −
tSKPP
Typ
25°C
Max
85°C
Typ
Max
180
1.5
2.5
Output−to−Output Skew++
Output−to−Output Skew− −
Part−to−Part Skew (Note 11)
15
35
70
tJITTER
Random Clock Jitter (RMS)
VPP
Input Voltage Swing (Differential Configuration)
(Note 12)
tr
tf
Output Rise/Fall Times
(0.8 V − 2.0 V)
Q, Q
Min
Min
Typ
Max
180
1.0
1.7
2.5
60
80
500
15
40
70
4.0
10
200
800
1000
330
600
900
1.0
Unit
MHz
1.7
2.5
ns
70
80
500
30
40
140
125
80
500
ps
4.0
10
4.0
10
ps
200
800
1000
200
800
1000
mV
330
600
900
330
650
900
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
8. All values vary 1:1 with VCC. VCC can vary ±0.3 V.
9. LVTTL output RL = 500 W to GND and CL = 20 pF to GND. Refer to Figure 2.
10. Fmax guaranteed for functionality only. VOL and VOH levels are guaranteed at DC only.
11. Skews are measured between outputs under identical conditions.
12. 200 mV input guarantees full logic swing at the output.
APPLICATION
TTL RECEIVER
CHARACTERISTIC TEST
*CL includes
fixture
capacitance
CL *
RL
AC TEST LOAD
GND
Figure 2. TTL Output Loading Used for Device Evaluation
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4
MC100LVELT23
ORDERING INFORMATION
Package
Shipping†
SOIC−8
98 Units / Rail
MC100LVELT23DG
SOIC−8
(Pb−Free)
98 Units / Rail
MC100LVELT23DR2
SOIC−8
2500 / Tape & Reel
MC100LVELT23DR2G
SOIC−8
(Pb−Free)
2500 / Tape & Reel
MC100LVELT23DT
TSSOP−8
100 Units / Rail
MC100LVELT23DTG
TSSOP−8
(Pb−Free)
100 Units / Rail
MC100LVELT23DTR2
TSSOP−8
2500 / Tape & Reel
MC100LVELT23DTRG
TSSOP−8
(Pb−Free)
2500 / Tape & Reel
MC100LVELT23MNRG
DFN8
(Pb−Free)
1000 / Tape & Reel
Device
MC100LVELT23D
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
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5
MC100LVELT23
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AJ
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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6
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
MC100LVELT23
PACKAGE DIMENSIONS
TSSOP−8
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948R−02
ISSUE A
8x
0.15 (0.006) T U
0.10 (0.004)
S
2X
L/2
L
8
5
1
PIN 1
IDENT
0.15 (0.006) T U
K REF
M
T U
V
S
0.25 (0.010)
B
−U−
4
M
A
−V−
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
S
F
DETAIL E
C
0.10 (0.004)
−T− SEATING
PLANE
D
−W−
G
DETAIL E
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7
DIM
A
B
C
D
F
G
K
L
M
MILLIMETERS
MIN
MAX
2.90
3.10
2.90
3.10
0.80
1.10
0.05
0.15
0.40
0.70
0.65 BSC
0.25
0.40
4.90 BSC
0_
6_
INCHES
MIN
MAX
0.114
0.122
0.114
0.122
0.031
0.043
0.002
0.006
0.016
0.028
0.026 BSC
0.010
0.016
0.193 BSC
0_
6_
MC100LVELT23
PACKAGE DIMENSIONS
DFN8 2x2, 0.5P
CASE 506AA−01
ISSUE E
D
A
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.20 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L
L
L1
PIN ONE
REFERENCE
2X
0.10 C
2X
0.10 C
ÇÇ
ÇÇ
DETAIL A
E
OPTIONAL
CONSTRUCTIONS
ÉÉ
ÉÉ
EXPOSED Cu
TOP VIEW
A
DETAIL B
0.10 C
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
MOLD CMPD
DETAIL B
OPTIONAL
CONSTRUCTION
0.08 C
(A3)
NOTE 4
SIDE VIEW
DETAIL A
A1
D2
1
4
C
8X
SEATING
PLANE
RECOMMENDED
SOLDERING FOOTPRINT*
L
8
5
e/2
e
8X
1.30
PACKAGE
OUTLINE
E2
K
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.20
0.30
2.00 BSC
1.10
1.30
2.00 BSC
0.70
0.90
0.50 BSC
0.30 REF
0.25
0.35
−−−
0.10
0.90
b
8X
0.50
2.30
1
0.10 C A B
0.05 C
8X
0.30
NOTE 3
BOTTOM VIEW
0.50
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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For additional information, please contact your local
Sales Representative
MC100LVELT23/D