AK8443

[AK8443]
AK8443
16bit 30MSPS video ADC with CCD/CIS interface
Features
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CCD I/F
Channel number
D-Range
CDS circuit
ADC
Max. Conversion Rate
Resolution
Offset DAC
Range
Resolution
PGA
Range
Resolution
Output format
Power supply
CPU I/F
Power consumption
Operation Temperature:
Package
3ch (2ch.)
1.764Vpp / 2.341Vpp ( typ.)
Pos. /Neg. polarity
30MSPS (10MSPS/ch)
16bit (straight binary code)
±321mV (normal input range)
8bit
0dB~22dB
7bit
8bit x 2 Æ 16bit or 4bit x 4 Æ 16bit
3.3V±0.3V
3 Wire Serial Interface
365 mW (typ.)
0°C~70°C
28pin QFN with radiation PAD in solder side
VCLP
AVDD
Black Correction
CCDIN0
CDS /
Clamp
7b
16bit
ADC
Reg.
7b
Reg.
LIMIT
+
Output
Control
8b or 4b
Serial
I/F
7b
SHR
D1(SDATA)
SDENB
Reg.
RESETB
CKGEN
SHD
D2∼D7
D0(SDCLK)
PGA
8bit DAC
VCOM
sign+17b
PGA
CDS /
Clamp
VRN
Reference Voltage
3:1 MUX
CDS /
Clamp
8bit DAC
CCDIN2
VRP
PGA
8bit DAC
CCDIN1
AVSS
MCLK
DVDD
MS1280-E-00
DVSS
2011/8
1
[AK8443]
Circuit Block
„ Clamp, CDS Block
The clamp circuit and correlated double sample circuits are provided for CCD output signal.
In CDS mode, the difference between the feed threw level of signal and the data level is sampled.
In clamp mode, the difference between the internal reference VCLP and the data level of signal is
sampled. Clamp pull the feed threw level into VCLP level when SHR is high.
„ Black Correction
Circuit to add an offset voltage to the sampled signal level. Voltage range of DAC which
generates Offset is ±321 mV(typ.) and its resolution is 8 bit.
„ MUX Block
MUX is a select switch that selects one signal from three ADC output signals sequentially.
The AK8443 has 2-channel mode and 3-channel mode. Each mode is selected by control
register.
„ ADC Block
The ADC coverts PGA output signal to digital data. The resolution is 16-bit and the maximum
conversion rate is 30MSPS. The output code is straight binary. The output data corresponding
to black is 0000h, and the data corresponding to white is FFFFh.
„ Output Control Block
The output control multiplexes a 16-bit word ADC data into two cycle 8-bit word data or four
cycle 4-bit word data.
„ Reference Voltage Gen1erator Block
All reference voltage is generated internally.
MS1280-E-00
2011/8
2
[AK8443]
Pin descriptions
No.
1
Name
VCLP
IO
I/O
@PD
VSS
(note1)
2
3
CCDIN0
VCOM
I
O
Hi-Z
4
5
6
7
8
9
10
11
12
13
CCDIN1
AVSS
AVDD
CCDIN2
NC
NC
MCLK
SHR
SHD
I
P
P
I
I
I
I
O
Low
Description
CDS, Clamp mode: Clamp Voltage output, Connect
capacitor0.1uF between AVSS and this pin.
DC direct mode: sensor reference voltage input
Sensor signal input
ADC reference voltage.
Connect capacitor0.1uF between AVSS and this pin.
Sensor signal input
Analog ground
Analog VDD
Sensor signal input
No connection(note 2)
No connection(note 2)
Main clock
Reference level sampling clock
Data level sampling clock
Data output (MSB)
14
15
16
17
18
19
D7
D6
D5
D4
DVDD
DVSS
D3
O
O
O
P
P
O
Low
Low
Low
Data output
Data output
Data output
Digital VDD
Digital Ground
Low
Data output
20
D2
O
Low
21
D1/SDATA
I/O
Data output
Data output / Serial I/F Data input
22
D0/SDCLK
I/O
Low
(note 3)
Low
(note 3)
23
24
25
26
27
SDENB
RESETB
AVDD
AVSS
VRN
I
I
P
P
O
VSS
28
VRP
O
VSS
Data output (LSB) / Serial I/F Clock input
Serial I/F Enable.
Reset input. Pull-up 100kΩ to AVDD.
Analog VDD
Analog ground
ADC reference voltage; Negative side.
Connect capacitor0.1uF between AVSS and this pin.
And connect capacitor 1uF between VRP and this pin.
ADC reference voltage; Positive side.
Connect capacitor0.1uF between AVSS and this pin.
And connect capacitor 1uF between VRN and this pin.
(note1) It is connect with VSS via internal resistance by CDS, Clamp mode or DC direct mode
(note2) Do not connect it anywhere.
(note3) When SDENB is Hi, it will be output condition as VSS. When SDENB is Low, it will be
input condition.
MS1280-E-00
2011/8
3
[AK8443]
Pin Layout
D5 15
D4 16
DVDD 17
DVSS 18
D3 19
D2 20
D1/SDATA 21
D0/SDCLK 22
14 D6
SDENB 23
13 D7
RESETB 24
12 SHD
AK8443VN
Top View
AVDD 25
11 SHR
AVSS 26
10 MCLK
VRN 27
9 NC
VRP 28
8 NC
7 CCDIN2
6 AVDD
CCDIN1
5 AVSS
4
3 VCOM
2 CCDIN0
1 VCLP
MS1280-E-00
2011/8
4
[AK8443]
Absolute Maximum Ratings
All voltage defined to their corresponding ground. AVSS=DVSS==0V
Item
Symbol
Min.
Max.
Unit
Analog Supply
AVDD
−0.3
4.6
V
Digital Supply
DVDD
−0.3
4.6
V
VINA
−0.3
AVDD+0.3
V
Input Voltage
Remarks
Storage Temperature
Tstg
−65
150
°C
Stress above these ratings may cause permanent damage to the device. Functional operation
of the device at these ratings is not implied.
Recommended Operating Conditions
All voltage defined to their corresponding ground, AVSS=DRVSS=0V
Item
Symbol
Min.
Typ.
Max.
Unit
Analog Supply
AVDD
3.0
3.3
3.6
V
Digital Supply
DVDD
3.0
3.3
3.6
V
Ta
0
70
°C
Operating Temperature
Remarks
**At the power up, the device must be reset once by RESETB pin.
**When power on AVDD, please set up the same time with DVDD or DVDD first.
**When power down AVDD, please set up the same time with DVDD or before DVDD.
**| AVDD-DVDD | < = 0.3V
MS1280-E-00
2011/8
5
[AK8443]
Electrical Characteristics
Analog Characteristics
Item
(AVDD=DVDD=3.3V, Ta= 25°C, MCLK=30MHz unless otherwise specified)
Symbol
Condition
min
typ
max
Unit
Negative, Normal range
2.2
2.3
2.4
V
Negative, Large range
2.5
2.6
2.7
V
Positive, Normal range
0.7
0.8
0.9
V
Positive, Large range
0.5
0.6
0.7
V
0.94
1.1
1.26
V
VCOM
1.15
1.25
1.35
V
VRP
1.7
1.8
1.9
V
VRN
0.6
0.7
0.8
V
Normal range
1.56
1.764
Vpp
Large range
2.07
2.341
Vpp
DC direct mode
1.1
Vpp
noise 100mVpp 0.5MHz
-30
dB
2080
usec
Reference Voltage Block
Clamp voltage
DC
direct
VCLP
VCLP
External input
reference level
Common voltage
ADC
positive
reference voltage
ADC
negative
reference voltage
Clamp and CDS Block
Input range
(*note 1)
CDS effect
VI
CDS
(note 2)
Clamp bandwidth
PGA gain=0dB setting
Signal
CLPBW
1.6Vpp 2MHz
(Design target value)
External cap=0.1uF
These characteristics are a value at the time of the external part value which was shown in the
external-circuit instance.
(note 1) Be careful an input signal which doesn't cross a power supply voltage in case of the
positive-polarity and large-range. DC direct mode only use normal range, when input is
1.1Vpp, PGA is 30H setting, it will be full scale. (@VCLP voltage=1.1V)
(note 2) When SHR width is minimum.
MS1280-E-00
2011/8
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[AK8443]
Item
(AVDD=DVDD=3.3V, Ta= 25°C, MCLK=30MHz unless otherwise specified)
Symbol
Condition
min
typ
max
Unit
Offset DAC
Resolution
DRES
Range
DRNG
8
Input conversion value
(note 1)
Range2
DRNG2
DRNG3
Positive
271
321
371
mV
Negative
-373.5
-323.5
-273.5
mV
Input conversion value
(note 2)
Range3
Positive
350.7
mV
Negative
-353.5
mV
307
mV
Input conversion value
(note 3)
Positive
Negative
Differential
DNL
nonlinearity
bit
The
-309.4
Monotonicity
-1.0
+1.0
mV
LSB
guarantee
These characteristics are a value at the time of the external part value which was shown in the
external-circuit instance.
(note 1) Normal range input.
(note 2) Large range input.
(note 3) DC direct mode.
MS1280-E-00
2011/8
7
[AK8443]
(AVDD=DVDD=3.3V, Ta= 25°C, MCLK=30MHz unless otherwise specified.)
Item
Maximum gain
Symbol
GMAX
Condition
PGA
CCDIN~ADC
min
typ
max
Unit
20.3
21.3
22.3
dB
0.001
0.06
Relative value to 0dB
setting
Step width
GSTA
The
Monotonicity
dB
guarantee
ADC
Resolution
Differential
nonlinearity
RES
DNL
No input noise
(note 1)
Offset voltage
(note 2)
NI
Crosstalk
XTALK1
XTALK2
VOFST
CCDIN~ADC
12bit accuracy
No missing code
16
+16
−16
Noise, Internal offset, Crosstalk
PGA gain=0dB
PGA gain=21.3dB
CDS, Clamp(normal input) -120
CDS, Clamp(Large input)
-145
DC Direct
−100
PGA gain=0dB
(note 3)
(note 4)
Power consumption
(note 5)
(note 6)
9
65
bit
LSB
LSBrms
120
145
100
128
64
mV
LSB
LSB
Normal
AVDD
97.1
123
mA
operation
DVDD
13.4
27.5
Power down
IPD
0.1
mA
These characteristics are a value at the time of the external part value which was shown in
the external-circuit instance.
(note 1) This is defined as sigma of the ADC output cord scattering at no input.
(note 2) Definition is that the Offset DAC setting value in no input signal condition exists between
Offset DAC setting values, (equivalent to an input-referred – 120mV) and (equivalent to an
input-referred + 120mV) where ADC output code changes from 000h to 001h. Since a total
adjustable range of Offset Adjust DAC includes this internal Offset adjust range, a practical
adjustable range of input signal is reduced by the internal Offset amount.
(note 3) Definition at MCLK=30MHz, 3ch, CDS mode. PGA gain of the channel to be measured is
set at its maximum value, all other channels’ PGA gains are set at minimum values. Then
measure how much the output code of the target channel to be measured fluctuates when input
to the measures channel is fixed and a full-scale minus 1 dB step signal is input on all other
channels.
(note 4) Definition at MCLK=30MHz, 3ch, CDS mode. All channels’ PGA gains at minimum
values. Then measure how much the output code of the target channel to be measured fluctuates
when input to the measures channel is fixed and a full-scale minus 1 dB step signal is input on all
other channels.
(note 5) At MCLK=30MHz, and 1.569 Vpp, 1MHz sine-wave signal fed on all 3 channel.
(note 6) At the capacitive load is 20pF.
MS1280-E-00
2011/8
8
[AK8443]
2) Digital DC Characteristics
(AVDD=DVDD=3.0V~3.6V,Ta= 0~70°C)
Item
Symbol
Pin
Min.
High level input voltage
VIH
**1
0.7*AVDD
Low level input voltage
VIL
**1
High
level
output
VOH
**2
level
output
VOL
**2
ILIKG
**1
voltage
Low
0.8*DVDD
−10
Unit
Remark
V
0.3*AVDD
voltage
Input leakage current
Max.
V
V
IOH=-1mA
0.2*DVDD
V
IOL=1mA
10
μA
**1 MCLK, SHR, SHD,D0(SDCLK), D1(SDATA), SDENB, RESETB
**2 D0~D7
MS1280-E-00
2011/8
9
[AK8443]
„ Switching characteristics
(AVDD=DVDD=3.0V~3.6V,Ta=0~70°C, 8bit bus, unless otherwise specified)
No.
Item
Pin
Min.
Typ.
Max.
ns
1
MCLK cycle time(T)
MCLK
33.3
2
MCLK Low width
MCLK
15
ns
3
MCLK High width
MCLK
15
ns
4
SHR,SHD cycle time
SHR
100
3T
6000
SHD
66.7
2T
4000
5
SHR pulse width
SHR
8
ns
6
SHR delay
(referenced to SHD↓)
SHR
2
ns
7
SHD↑delay
(referenced to SHR↓)
SHD
2
ns
8
SHD pulse width
SHD
8
ns
9
SHD setup time
(referenced to MCLK↑)
SHD
0
ns
10
SHD delay
(referenced to MCLK↓)
SHD
10
ns
11
SHR aperture delay
SHR
2
ns
12
SHD aperture delay
D0~7 output delay
SHD
2
ns
13
(
referenced
2000
Unit Condition
ns
to D7~D0
Pipeline delay
(SHD conversion)
SHD=”H”
15
2ch
Hold
2
12
ns
MCLK↑or MCLK↓)
14
3ch
setup
C=20pF
3
D7~D0
4
clock
3ch mode
2ch mode
inhibition
period
( After referenced to
SHD
T+10
ns
3ch mode
2ch mode
SHD↓, first MCLK↑)
MS1280-E-00
2011/8
10
[AK8443]
(AVDD=DVDD=3.0V~3.6V,Ta=0~70°C, 4 bit bus, unless otherwise specified)
No.
Item
Pin
Min.
Typ.
Max.
ns
1
MCLK cycle time (T)
MCLK
33.3
2
MCLK Low width
MCLK
15
ns
3
MCLK High width
MCLK
15
ns
4
SHR,SHD cycle time
SHR
199.8
6T
12000
SHD
133.2
4T
8000
5
SHR pulse width
SHR
8
ns
6
SHR delay
(referenced to SHD↓)
SHR
2
ns
7
SHD↑ delay
(referenced to SHR↓)
SHD
2
ns
8
SHD pulse width
SHD
8
ns
9
SHD setup time
(referenced to MCLK↑)
SHD
0
ns
10
SHD delay time
(referenced to MCLK↑)
SHD
10
ns
11
SHR aperture delay
SHR
2
ns
12
SHD aperture delay
D0~7 delay time
SHD
2
ns
13
(reference to MCLK ↑or
2000
Unit Condition
ns
D3~D0
2
12
ns
SHD=”H”
15
setup
C=20pF
Pipeline delay
(MCLK
2ch
hold
MCLK ↓)
14
3ch
conversion)
D3~D0
15
clock
3ch mode
2ch mode
inhibition
period
( After referenced to
SHD
2T+10
ns
3ch mode
2ch mode
SHD↓, first MCLK↑)
MS1280-E-00
2011/8
11
[AK8443]
CCDIN
0
1
2
3
MCLK
SHR
SHD
D7~0
M
L
CCDIN0
M
L
CCDIN1
M
L
CCDIN2
M
L
CCDIN0
M
L
CCDIN1
M
L
CCDIN2
0
M
L
CCDIN0
1
L among D7 to D0 indicates LSB data, and M indicates MSB data.
CCDIN0(n)
CCDIN0(n+1)
CCDIN1(n)
CCDIN1(n+1)
CCDIN2(n)
CCDIN2(n+1)
CCDIN
11
7
5
6
12
SHR
10
4
8 9
15
SHD
1
3
4
2
MCLK
13
D7~0
MSB
LSB
CCDIN1(n-4)
MSB
13
LSB
CCDIN2 (n-4)
MSB
LSB
MSB
CCDIN0(n-3)
LSB
MSB
LSB
CCDIN1(n-3) CCDIN2 (n-3)
MSB
LSB
CCDIN0(n-2)
MSB
LSB
CCDIN1(n-2)
3ch and 8bit bus mode
MS1280-E-00
2011/8
12
[AK8443]
CCDIN
0
1
2
3
MCLK
SHR
SHD
15clock 目
D3~0
CCDIN0
CCDIN1
CCDIN2
0
D3 ~ D0 output order is ADout[15:12]→ADout[11:8]→ADout[7:4]→ADout[3:0].
CCDIN0(n+1)
CCDIN0(n)
CCDIN1(n)
CCDIN1(n+1)
CCDIN2(n)
CCDIN2(n+1)
CCDIN
11
7
5
12
6
SHR
10
8
4
9
15
SHD
3
1
4
2
MCLK
13
13
ADout15~12
ADout7~4
D3~0
ADout11~8
CCDIN2(n-4)
CCDIN0(n-3)
CCDIN1(n-3)
CCDIN2(n-3)
ADout3~0
CCDIN0(n-2)
CCDIN1(n-2)
CCDIN2(n-2)
3ch and 4bit bus mode
MS1280-E-00
2011/8
13
[AK8443]
CCDIN
0
1
2
3
MCLK
SHR
SHD
D7~0
M
L
CCDIN0
M
L
CCDIN1
M
L
M
CCDIN0
L
CCDIN1
M
L
M
CCDIN0
0
L
CCDIN1
M
L
CCDIN0
1
2
L among D7 to D0 indicates LSB data, and M indicates MSB data.
CCDIN
CCDINO(n)
CCDIN0(n+1)
CCDIN0(n+2)
CCDIN1(n)
CCDIN1(n+1)
CCDIN1(n+2)
11
7
5
6
12
SHR
10
4
8 9
15
SHD
1
3
4
2
MCLK
13
D7~0
MSB
LSB
CCDIN0(n-5)
MSB
13
LSB
CCDIN1 (n-5)
MSB
LSB
CCDIN0(n-4)
MSB
LSB
CCDIN1(n-4)
MSB
LSB
CCDIN0 (n-3)
MSB
LSB
CCDIN1(n-3)
MSB
LSB
CCDIN0(n-2)
2ch and 8 bit bus mode
MS1280-E-00
2011/8
14
[AK8443]
CCDIN
0
2
1
3
4
5
6
MCLK
SHR
SHD
15clock 目
D3~0
CCDIN0
CCDIN1
0
D3 ~ D0 output order is ADout[15:12]→ADout[11:8]→ADout[7:4]→ADout[3:0].
CCDIN
CCDIN0(n)
CCDIN0(n+1)
CCDIN0(n+2)
CCDIN1(n)
CCDIN1(n+1)
CCDIN1(n+2)
11
12
7
5
6
SHR
10
8
4
9
15
SHD
1
3
4
2
MCLK
ADout11~8
ADout3~0
13
13
D3~0
ADout15~12
ADout7~4
CCDIN1(n-5)
CCDIN0(n-4)
CCDIN1(n-4)
CCDIN0(n-3)
CCDIN1(n-3)
CCDIN0(n-2)
2ch and 4bit bus mode
MS1280-E-00
2011/8
15
[AK8443]
„ Serial Interface switching characteristics
No.
1
2
3
4
5
6
7
8
9
10
11
12
(AVDD=3.0~3.6V, DVDD=3.0~3.6V ,Ta= 0~70°C unless otherwise specified.)
Item
Pin
Min.
Typ. Max.
Unit
Condition
Clock cycle
SDCLK
0.1
10
MHz
Clock pulse width(High)
SDCLK
40
ns
Clock pulse width(Low)
SDCLK
40
ns
SDENB setup time
SDENB
80
ns
( to SDCLK rising↑)
SDENB hold time
SDENB
80
ns
( from SDCLK rising↑)
Data High-Z delay
D0, D1
0
40
ns
( from SDENB falling↓)
Data enable delay
D0, D1
0
40
ns
( to SDENB rising↑)
SDATA setup time
SDATA
40
ns
( to SDCLK rising↑)
SDATA hold time
SDATA
40
ns
( from SDCLK rising↑)
SDENB
SDCLK,SDENB rising time
SDCLK
6
ns
SDENB
SDCLK,SDENB falling time
SDCLK
6
ns
SDENB
SDENB High level width
SDENB
40
ns
12
SDENB
0.7AVDD
0.7AVDD
0.3AVDD
0.3AVDD
11
10
6
7
0.7DVDD
D0
0.3DVDD
4
1
5
0.7AVDD
SDCLK
0.3AVDD
6
10
3
2
11
7
0.7DVDD
D1
SDATA
0.3DVDD
0.7AVDD
0.3AVDD
8
9
Serial interface write timing
MS1280-E-00
2011/8
16
[AK8443]
Clock Input pin SDCLK and Data Input pin SDATA for Serial Interface are shared with A/D Data
Output pins, D0 and D1 respectively. When SDENB becomes low, D0 and D1 are put into High-Z
conditions and it is enabled to input SDCLK and SDATA. SDATA is captured at the rising edge of
SDCLK. SDATA is 16 Bit long. Write “zeros“ from first Bit to 4th Bit. 5th ~8th Bits are assigned for
Register Address where the 5th Bit is MSB and the 8th Bit is LSB. 9th~ 16th Bits are assigned for
Data where the 9th Bit is MSB and the 16th Bit is LSB.
16 and more rising edges of SDCLK are required while SDENB is low, from the time to fall to the
time to rise. When it is less than 16 rises, registers will not be written properly.
If it is more than 16 rises while SDENB is low, from falling to rising, the last 16 edges become
effective. There is a possibility that an erroneous data will be written into registers if noises occur
on D0 Output / SDCLK input pin and D1 Output / SDATA input pin when these pins are at High-Z
conditions. To avoid this, resistors should be connected between D0 / SDCLK pin, D1 / SDATA
pin and AVSS respectively to pull-down these pins.
SDENB
High-Z
D0
SDCLK
High-Z
D1
SDATA
0
0
0
0
A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0
0
0
Wright Register
MS1280-E-00
2011/8
17
[AK8443]
- Power on reset
AVDD
100kΩ
RESETB
0.33μF
AK8443
0.9xAVDD
AVDD
AVDD rise time
max. 10ms
It becomes possible for
the register writing
after 100 ms.
RESETB
max. 100ms
Power on reset
At the power-on, Power-On-Reset must be executed by using RESETB pin. When a 0.33 μF
external capacitor on RESETB pin is used, the rise time of AVDD must be shorter than 10 ms in
order to assure proper Power-On-Reset operation. Maximum time from AVDD power-on to the
release from Power-On-Reset is 100 ms. Registers should be written after waiting for longer than
100 ms after AVDD power-on.
As electric charge is retained in the external capacitor even after AVDD is made to 0V, voltage on
RESETB pin does not go to 0V immediately. If AVDD is powered-up again before RESETB pin
returns to 0V, a proper Power-On-Reset operation is not made. In order to assure proper
Power-On-Reset operation when to power-up AVDD again, it is required that AVDD time to be
kept at 0V is longer than 300 ms. If the 300 ms AVDD time to be kept at 0V, is not obtainable, the
device must be reset by applying a low pulse externally on RESETB pin.
When the condition doesn’t fill above, please make the RESETB high after power supply start-up,
Without CAP connect to RESETB pin.
MS1280-E-00
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18
[AK8443]
In RESETB pin use
Trst1
Trst2
0.9×AVDD
AVDD
RESETB
0.3×AVDD
0.3×AVDD
0.3×AVDD
(AVDD=DVDD=3.0~3.6V、Ta=0~70 )
Item
Symbol
Pin
min
Reset period 1
Trst1
RESETB
100
ns
Reset period 2
Trst2
RESETB
100
ns
MS1280-E-00
typ
max
Unit
Condition
2011/8
19
[AK8443]
Register map
Sub
Adrs
Bits
Default
Register
Function
1H
6
5
4
3
2:0
7:0
Value
*0******
**0*****
***0****
****0***
*****000
00000000
Name
TEST
BUS
INPUTRANG
REVERSE
MODE
OFF0
Test register
Output bus setting
Input range setting
Input inverted setting
Operation mode setting
CCDIN0 offset setting
2H
7:0
00000000
OFF1
CCDIN1 offset setting
3H
7:0
00000000
OFF2
CCDIN2 offset setting
4H
6:0
*0000000
GAIN0
CCDIN0 gain setting
5H
6:0
*0000000
GAIN1
CCDIN1 gain setting
6H
6:0
*0000000
GAIN2
CCDIN2 gain setting
7H
1:0
******00
DIRECT
DC direct mode setting register
0H
Address “08H”~”0EH” is test register. Please do not access the test register.
MS1280-E-00
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[AK8443]
Operation mode setting (Address “00H”)
Reset *000 0000
Please set “0” to test register
Output mode setting register
BUS
Output mode
0
8bit bus mode
1
4bit bus mode
Input range change register
Input Range
Input range
0
1.764V
1
2.341V
Input inverted mode register
Reverse
0
Input mode
Input downstream from VCLP
1
Input upstream from VCLP
Operation mode setting
MODE
Operation mode
000
Power down
100
101
3ch
2ch(0, 1ch active)
110
2ch(1, 2ch active)
111
2ch(0, 1ch active)
Other
Inhibition
(*) Unused input pin be Hi-z by 2ch mode.
MS1280-E-00
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[AK8443]
Offset setting (Address “01H”~ “03H”)
01H
CCDIN0 offset setting
02H
CCDIN1 offset setting
03H
CCDIN2 offset setting
Reset
0000 0000
OFF*[7:0]
Offset
0111 1111
Normal range
+321.0mV
0111 1110
・・・
+318.5mV
0000 0001
+2.5mV
0000 0000
0
-2.5mV
・・・
1111 1111
・・・
・・・
-321.0mV
1000 0001
-323.5mV
1000 0000
Note1) At an offset of +2.5 mV, the signal fraction is corrected toward 2.5 mV subtraction.
Note2) The value for the normal range input.
By large range, 1.093 times x normal range.
By DC direct mode, 0.956 times x normal range.
Gain setting (Address “04H”~ “06H”)
04H
CCDIN0 gain setting
05H
CCDIN1 gain setting
06H
CCDIN2 gain setting
Reset *000 0000
GAIN*
gain
000 0000
0
0.06 dB
000 0001
000 0010
・・・
0.13 dB
111 1110
20.58 dB
・・・
21.28 dB
111 1111
Note) Gain is expressed by the following equations.
This value is relative gain from “000 0000” setting
Vout =
204
× Vin
12 + (127 − x)
( x = 0 ~ 127) Input range=1.764V
Vout =
168
× Vin
12 + (127 − x)
( x = 0 ~ 127) Input range=2.341V
MS1280-E-00
2011/8
22
[AK8443]
Operation mode setting 2 (Address “07H”)
Reset **** **00
DC direct mode setting register
DIRECT
00
CDS mode, Clamp mode
11
DC direct mode
When DC direct mode setting, internal VCLP pin connect GND via 12kΩ.
MS1280-E-00
2011/8
23
[AK8443]
IO Pin Connection Information
Input Output equivalent circuit
SHR, SHD, MCLK
AVDD
P
N
AVSS
RESETB
AVDD
DVDD
P
100kΩ
N
AVSS
AVSS
SDENB
DVDD
AVDD
P
N
AVSS
AVSS
MS1280-E-00
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24
[AK8443]
CCDIN, VCLP
AVDD
CCDIN
SHR
AVSS
SHR
AVDD
VCLP
Clamp AMP
AVSS
VRP, VCOM, VRN
5.5k
AVDD
reference VGB
VRP(1.8V)
(1.152V)
AVSS
1.54k
0.98k
AVDD
VCOM(1.25V)
AVSS
4.52k
AVDD
VRN(0.7V)
AVSS
7k
MS1280-E-00
2011/8
25
[AK8443]
D0
3-state
Hi-Z : SDENB=”L”
Enable: SDENB=”H”
DVDD
P
DVDD
D0
DVSS
AVDD
N
AVSS
SDCLK
AVSS
D1
3-state
Hi-Z : SDENB=”L”
Enable: SDENB=”H”
DVDD
P
DVDD
D0
DVSS
AVDD
N
AVSS
SDATA
AVSS
D2 ~ D7
DVDD
P
DVDD
D2 ~ D7
DVSS
N
AVSS
MS1280-E-00
2011/8
26
[AK8443]
External circuit example
CDS, Clamp mode
DVDD:3.3V
0.1μF
min.10 kΩ
DVSS
15
D5
D4
DVDD
22
0.33μF
16
17
18
DVSS
D3
19
D2
20
D1
21
min.10 kΩ
14
D0
D6
23
13
SDENB
D7
24
AK8443
RESETB
0.1μF
12
25
AVDD
11
SHR
26
10
0.1μF
AVSS
27
9
1μF
VRN
NC
28
8
MCLK
CCDIN2
7
0.1μF 0.1μF
AVDD
6
AVSS
5
CCDIN1
4
0.1μF 0.1μF
VCOM
3
CCDIN0
2
1
VCLP
VRP
0.1μF
AVDD
3.3V
SHD
Top View
NC
0.1μF 0.1μF
AVSS
DC Direct mode
DVDD:3.3V
min.10 kΩ
0.1μF
DVSS
15
D5
16
D4
17
DVDD
18
DVSS
19
D3
20
D2
21
D1
min.10 kΩ
22
D0
0.33μF
14
D6
23
SDENB
13
D7
24
RESETB
0.1μF
12
AK8443
SHD
Top View
25
AVDD
11
1μF
MCLK
27
VRN
9
NC
7
CCDIN2
6
0.1μF
AVDD
5
AVSS
4
CCDIN1
3
VCOM
2
CCDIN0
1
VCLP
0.1μF
10
AVSS
28
VRP
3.3V
SHR
26
0.1μF
AVDD
8
NC
0.1μF
AVSS
* The radiation PAD on the package solder side connects with analog ground (AVSS).
MS1280-E-00
2011/8
27
[AK8443]
Package
„ Package dimension
unit [mm]
„ Marking
1.
Marketing code
:8443
2.
Date code
:XXX
Week code
:Y
The company management code
8443
XXXY
Marking
MS1280-E-00
2011/8
28
[AK8443]
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales
office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current
status of the products.
z Descriptions of external circuits, application circuits, software and other related information
contained in this document are provided only to illustrate the operation and application
examples of the semiconductor products. You are fully responsible for the incorporation of
these external circuits, application circuits, software and other related information in the design
of your equipments. AKM assumes no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for
infringement of any patent, intellectual property, or other rights in the application or use of
such information contained herein.
z Any export of these products, or devices or systems containing them, may require an export
license or other official approval under the law and regulations of the country of export
pertaining to customs and tariffs, currency exchange, or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any
safety, life support, or other hazard related device or systemNote2), and AKM assumes no
responsibility for such use, except for the use approved with the express written consent by
Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system
containing it, and which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to
function or perform may reasonably be expected to result in loss of life or in significant injury or damage
to person or property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of,
or otherwise places the product with a third party, to notify such third party in advance of the
above content and conditions, and the buyer or distributor agrees to assume any and all
responsibility and liability for and hold AKM harmless from any and all claims arising from the
use of said product in the absence of such notification.
MS1280-E-00
2011/8
29
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