IR3Y48M
IR3Y48M
CCD Signal Process & Digital Interface IC
DESCRIPTION
PIN CONNECTIONS
The IR3Y48M is a CMOS single-chip signal
processing IC for CCD area sensors which includes
correlated double sampling circuit (CDS), clamp
circuit, automatic gain control amplifier (AGC),
reference voltage generator, black level detection
circuit, 20 MHz 10-bit analog-to-digital converter
(ADC), timing circuit for internally required pulses,
and serial interface for internal circuits.
TOP VIEW
DO9
DO8
DO7
DO6
DO5
DVDD
DVSS
DO4
DO3
DO2
DO1
DO0
48-PIN QFP
48 47 46 45 44 43 42 41 40 39 38 37
NC 1
AVDD4 2
NC 3
VRN 4
VRP 5
AVDD2 6
AVDD2 7
AVSS2 8
AVSS2 9
VCOM 10
CCDIN 11
REFIN 12
FEATURES
• Low power consumption :
110 mW (TYP.) at 20 MHz mode
• Wide AGC range : 0 to 36 dB
(Gain step : 0.094 dB/step)
• High speed sample-and-hold circuits :
pulse width 10 ns (MIN.)
• Power save operation :
84 mW (TYP.) at 15 MHz mode
• Standby mode : less than 0.3 mW
• Built-in serial interface
• 10-bit ADC operating up to 20 MHz
– Non-linearity
DNL : 0.6 LSB (TYP.)
INL : 1.5 LSB (TYP.)
• Maximum input level of CCD signals : 1.1 Vp-p
• Accepts a direct signal input to ADC or AGC
(input level : 1 Vp-p (TYP.))
• Single +3 V power supply
• Package :
48-pin QFP (QFP048-P-0707) 0.5 mm pin-pitch
36 OP
35 RESETN
34 AVDD3
33 AVSS3
32 STBYN
31 CSN
30 SDATA
29 SCK
28 OBP
27 CCDCLP
26 BLK
25 ADCLP
CLPCAP
ADIN
OBCAP
MONOUT
NC
AISET
AVDD1
AVSS1
NC
ADCK
SHR
SHD
13 14 15 16 17 18 19 20 21 22 23 24
(QFP048-P-0707)
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in
catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
1
IR3Y48M
BLOCK DIAGRAM
SHR
23
CLPCAP
SHD
24
CLPCAP
AGC
ROUGH
CDS
12
S/H
CCDIN
11
CCD
BANDGAP
VREF
DC CLAMP
13
CCDCLP
REFIN
MONOUT
16
ADCLP
6 dB/STEP
(0 to 12 dB)
AGC
FINE
10-BIT
ADC
+
6 dB/STEP 0.094 dB/STEP
(0 to 18 dB)
(0 to 6 dB)
34 AVDD3
15
DAC
COMPARE
OBP
REGISTER (7-BIT)
AISET
DO0 to DO9
37 to 41, 44 to 48
19 AVDD1
6,7 AVDD2
ADIN 14
OBCAP
VRP
5
VCOM
10
4 VRN
2 AVDD4
20 AVSS1
8,9 AVSS2
18
TIMING
GENERATOR
ADCK 22
33 AVSS3
SERIAL
REGISTER
43 DVDD
42 DVSS
26
BLK
28
27
25
31
29
30
OBP CCDCLP ADCLP CSN SCK SDATA
2
36
OP
35
RESETN
32
STBYN
IR3Y48M
PIN DESCRIPTION
PIN NO. SYMBOL
1 NC
2
3
AVDD4
NC
I/O
–
EQUIVALENT CIRCUIT
DESCRIPTION
No connection.
–
–
Supply of 2.7 to 3.6 V analog power.
No connection.
VDD
4
VRN
O
ADC internal negative reference
voltage.
(Connect to AVSS via 0.1 µF.)
ADC internal positive reference
5
VRP
O
◊
GND
voltage.
(Connect to AVSS via 0.1 µF.)
6
7
AVDD2
–
Supply of 2.7 to 3.6 V analog power.
AVDD2
–
Supply of 2.7 to 3.6 V analog power.
8
AVSS2
9
AVSS2
–
–
An analog grounding pin.
An analog grounding pin.
VDD
ADC internal common reference
voltage.
(Connect to AVSS via 0.1 µF.)
10
VCOM
O
10
◊
GND
CDS circuit data input.
VDD
11
CCDIN
I
CDS circuit reference input.
12
REFIN
I
◊
GND
13
CLPCAP
O
14
ADIN
I
15
OBCAP
O
16
MONOUT
O
Clamp level output.
VDD
(Connect to AVSS via 0.1 µF.)
ADIN signal input.
Black level integration voltage.
(Connect to AVSS via 0.033 µF.)
◊
GND
◊ Internal gate
3
Monitor output of CDS or AGC.
IR3Y48M
PIN NO. SYMBOL
17 NC
I/O
EQUIVALENT CIRCUIT
DESCRIPTION
No connection.
–
VDD
18
AISET
I
Internal analog circuit bias input.
(Connect to AVSS via 4.7 k$.)
18
◊
GND
19
AVDD1
AVSS1
–
–
Supply of 2.7 to 3.6 V analog power.
20
21
22
NC
ADCK
–
I
No connection.
ADC sampling clock input.
23
SHR
SHD
I
I
Reference sampling pulse input.
25
ADCLP
I
26
BLK
I
for ADIN signal.
Blanking pulse input.
27
CCDCLP
OBP
I
I
Clamp control input.
Black level period pulse input.
24
28
29
An analog grounding pin.
VDD
Data sampling pulse input.
Clamp and black calibration control
Serial port clock input.
SCK
I
30
31
SDATA
CSN
I
I
Serial port data input.
32
STBYN
I
Standby control (standby at low).
33
34
AVSS3
–
An analog grounding pin.
AVDD3
–
GND
Serial port chip selection (active at low).
Supply of 2.7 to 3.6 V analog power.
Reset signal input (reset at low).
VDD
35
RESETN
I
Serial I/F operation code enable pin
36
OP
(active at low).
I
GND
◊ Internal gate
4
IR3Y48M
PIN NO. SYMBOL
37
DO0
I/O
EQUIVALENT CIRCUIT
DESCRIPTION
ADC digital output (LSB).
O
(Capable of High-Z)
VDD
ADC digital output.
38
DO1
O
39
DO2
O
ADC digital output.
(Capable of High-Z)
40
DO3
O
ADC digital output.
(Capable of High-Z)
(Capable of High-Z)
GND
41
DO4
ADC digital output.
O
(Capable of High-Z)
Digital output driver GND. A digital
42
DVSS
–
43
DVDD
–
44
DO5
O
45
DO6
O
ADC digital output.
(Capable of High-Z)
46
DO7
O
ADC digital output.
(Capable of High-Z)
47
DO8
O
grounding pin.
Digital output driver power supply.
(2.7 to 3.6 V)
ADC digital output.
(Capable of High-Z)
VDD
ADC digital output.
GND
48
DO9
(Capable of High-Z)
ADC digital output (MSB).
O
(Capable of High-Z)
NOTES :
• NC pins are recommended to be connected to AVSS on PCB even they are not connected electrically in the chip.
• High-Z at standby.
5
IR3Y48M
FUNCTIONAL DESCRIPTION
Outline
The configuration of IR3Y48M is described below.
SHR
MONOUT
SHD
IR3Y48M
Clamp
VREF
REFIN
+
CDS
CCDIN
10-bit
ADC
AGC
CCD
ADIN
Black
Control
Serial
Register
Timing
Generator
ADCK
BLK
OBP CCDCLP ADCLP
CSN
SCK
SDATA
GENERAL TIMING
CCD
OB
Effective Pixel
(OB)
Blanking
ADCK
BLK
OBP
CCDCLP
DO0-DO9
Data Output
Black Code
6
DO0 toDO9
IR3Y48M
CDS Circuit
CDS has the gain of maximum 12 dB (6 dB/step).
This gain is a part of total gain and it is controlled
by register value similar to gain in AGC circuit.
Connect signal from CCD sensor to CCDIN pin
through C-coupling. Place the same capacitor
between REFIN and AVSS.
CDS circuit holds CCD precharge (reference) level
at SHR pulse, then it samples CCD pixel data at
SHD pulse. Correlated (common) noise is removed
by subtraction of precharge level from pixel data
level.
Reference Clock (SHR)
Data Clock (SHD)
REFIN
CDS
CCD
CCDIN
CDS Output
= V (CDS)
= V (DAT) – V (PREC)
CDS Operation
Reset
Pulse
Reset
Pulse
V (PREC)
V (CDS)
V (DAT)
MAX. Level
SHR
SHR
SHD
SIG
SHD
SIG
fSMAX = 20 MHz/tSMIN = 50 ns
7
IR3Y48M
Clamp Circuit
DC CLAMP
DC level of the analog input is fixed by internal DC
clamp circuit. DC level of C-coupled CCD signal at
CDS input is set to CLPCAP by DC clamping.
SHR
Normally clamp switch is turned on at black level
calibration period. Place 0.1 µF external
capacitance between CLPCAP and AVSS.
Clamp Timing
SHD CCDCLP
Timing Control
(Register Conditions)
CCD
REFIN
ADCK
CCDIN
(CCDCLP)
Clamp
Source
CLPCAP
CCDCLP
DC Clamp Function
CLPCAP Level
CLPCAP
REFIN, CCDIN
Clamp Level
CLAMP OF ADIN SIGNAL
Clamp operation for ADIN path is also available.
Note that clamp voltage [CLPCAP] is different
between CCD input and ADIN.
ADCLP signal is used for both clamp and black
level control at ADIN input mode. It is also possible
to turn off clamp operation by register setting.
ADCLP
Timing Control
CLAMP CONTROL
Following items are selectable through register
setting.
a) Clamp current
Normal or fast clamp is selectable for charge
current. (Select normal clamp in general)
b) Clamp target
Input signal (REFIN and CCDIN) to be
clamped is selectable. It is also possible to turn
off the clamp function.
ADIN
To AGC
or To ADC
(ADCLP)
CLPCAP
ADIN DC Clamp Function
8
IR3Y48M
Black Level Cancel Circuit
The OBP voltage is discharged under following
status :
q Set black level reset register to 1
w Set RESET pin low
e Power down (by STBYN or register control)
The period to reach the final value depends on the
status of chip. It may take more than one thousand
pixels at start-up or after reset. It may take only
several pixels when the status is not changed. DC
clamp [CCDCLP] is allowed during OBP low.
Black level cancelling for ADIN signal (broken line
in the chart) is controlled by ADCLP pulse (clamp
and OB control are done simultaneously) instead of
OBP.
The purpose of black level cancel is to adjust the
AGC input level which can equalize the ADC output
code to black level code written in the register. The
black level cancelling is generally done during OB
(optical black period) pulsed by OBP pulse. The
register value ((1 to) 16 to 127 LSB : default 64
LSB) is written by serial interface.
Black level cancel loop is established while OBP is
low (when pulse is not inverted).
In this loop, ADC output code is compared with
register setting. During OB period, the OBP voltage
gradually terminates into certain voltage resulting
the output code equal to the register setting.
AGC
Rough
CDS
REFIN
AGC
Fine
10-bit
ADC
+
S/H
CCDIN
ADIN
OBCAP
DAC
DO0-DO9
Compare
OBP
(Path for ADIN)
Register (7-bit)
ADCLP
OBP
ADCLP
Black Level Calibration
Blanking
Effective
Pixel Signal
Optical Black Period
Blanking
Effective
Pixel Signal
CCD
ADCK
OBP
OBCAP
Resulting Black
Calibration Level
(Hold)
Previous
Black Level
Black Level Calibration Timing
9
IR3Y48M
Gain Control Circuit
controlled (as described below) by 9-bit gain control
register. The gain is fixed to maximum gain when
the code exceeds 382 (decimal).
The gain of ADIN (which bypassing CDS) is 0 to
24 dB.
The total gain for CCD input signal covers from 0 to
36 dB.
This range consists of CDS (0 to 12 dB (6 dB/
step)), AGC rough (0 to 18 dB (6 dB/step)), and
AGC fine (0 to 6 dB (0.094 dB/step)). Total gain is
0.094 dB
1 step
35.91 dB
0 dB
0D
383D
AGC Block
CDS
6 dB/step
(0 to 12 dB)
Rough
6 dB/step
(0 to 18 dB)
Total Gain = 0 to 35.91 dB
Gain Control
10
Fine
0.094 dB/step
(0 to 6 dB)
IR3Y48M
ADC OUTPUT CODE LOGIC
ADC digital output is High-Z under following
conditions :
q Set ADC output register to 1
w Set SYBYN pin low
e Power down (by STBYN or register control)
A/D Converter Circuit
IR3Y48M integrates 20 MHz 10-bit full pipeline A/D
converter (ADC).
A/D CONVERSION RANGE
The analog input range of the ADC is determined
by VREF circuit integrated in IR3Y48M. At ADC
direct input (ADIN) mode (Mode (1) Register D5 =
1), feed 1 Vp-p (full scale) signal based on clamp
level as zero reference into ADIN input pin.
DIGITAL OUTPUT CODE
According to ADIN, digital codes are determined as
follows :
Data Output at Straight Binary
[Mode (1) Register D2 = 0, D5 = 1]
A/D CONVERTER OUTPUT CODE
(AT MODE (1) REGISTER D5 = 1)
The digital output format is binary.
Thus, "all zero" digital output with zero reference
input (ADIN = CLPCAP), "all one" digital output with
full-scale input (ADIN = CLPCAP + 1 V (TYP.)).
ADIN
DIGITAL CODE
MSB
LSB
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Clamp
1
reference + 1 V
CLOCK, PIPELINE DELAY AND OUTPUT DIGITAL
DATA TIMING
The A/D conversion is performed based on the
clock fed to ADCK pin.
The track-and-hold operation is completed at falling
(when not inverted) edge of ADCK.
The 10-bit width parallel data is obtained at rising
edge after 5.5 clock pipeline delay. (Sampling edge
is selectable by register setting.)
1
1
1
1
1
1
1
:
1
0
0
0
0
0
0
0
0
0
:
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
:
:
Clamp
reference
11
1
:
:
CODE AT CLAMP LEVEL
(AT MODE (1) REGISTER D5 = 0, D4 = 1)
The output code at clamp level can be set
throughout (1 to) 16 to 127 LSB at the step of 1
LSB by register setting.
1
0
0
0
0
0
IR3Y48M
Other Functions
ADC DIRECT INPUT (ADIN MODE)
Direct input path to ADC or AGC is realized by
register setting. This direct path can be turned off
by register. Black level cancel and clamp are
performed at the same timing of ADCLP low.
(N)
ADIN
(N+1)
These controls can be masked by register setting.
BLK, SHR, and SHD controls are ignored at ADIN
mode.
The signal at AGC input is shown below.
(N+2)
ADCK
(When ADCK is inverted,
signal (N) is sampled by this edge)
Black Cancel & Clamp
ADCLP
DO0-DO9
N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1
N
NOTE : For ADCLP low, both black level cancel and clamp are active at AGC input mode, and only clamp is active at
ADC input mode.
ADIN Signal Processing (AGC Input)
Operation at ADC direct input is shown below.
The zero reference (CLPCAP) is established by
ADCLP pulse. The ADIN input range is from
CLPCAP + 1 V (TYP.) (full scale).
Full scale
CLPCAP + 1 V
ADC
dynamic range
= 1 Vp-p
ADIN
CLPCAP
ADCLP
Clamp ON
ADIN Signal Input Level
STANDBY MODE
The standby mode can be set either by register
setting or STBYN pin.
If one of the above is set, IR3Y48M powers down.
("OR" logic)
12
IR3Y48M
MONITOR OUTPUT
By setting the register, the signal from MONOUT is
selectable. Alternatives are OFF, CDS output, AGC
output, or REFIN/CCDIN output. Even at the CDS
gain is set to a certain gain, the CDS output on
MONOUT is multiplied by 1/gain resulting the level
before CDS amplification.
The output level of MONOUT is shown below. The
CCD
MONOUT level is VCOM (1.1 V, TYP.) at zero
reference level. For the maximum amplitude (1.1 Vp-p),
the output level is 2.2 V (TYP.).
CAUTION :
VCOM pin does not have enough driving capabilities.
V1
V3
V2
V0 = No signal
MAX. signal = 1.1 V
MAX. level = VCOM + 1.1 V
= 2.2 V
V0 = No signal level
MONOUT
MON reference level = VCOM = 1.1 V (TYP.)
V1
V2
V3
Monitor Output Level
POLARITY INVERSION
Following timing pulse of IR3Y48M control can be
inverted by register setting :
q ADCK (A/D converter sampling pulse)
w SHR, SHD (CDS sampling clock)
e BLK, OBP, CCDCLP, ADCLP (Enable controls)
General Notice for Power Supply
It is recommended to supply both AVDD and DVDD
supply from single regulator.
(Observe absolute maximum rating specification :
DVDD ≤ (AVDD + 0.3 V) even at the power-up and
power-down sequence.)
Refer to "APPLICATION CIRCUIT EXAMPLE"
against noise of power supply.
POWER SAVE
Power save mode is selectable for the sampling
frequency below 15 MHz.
The power consumption at this mode is lower than
20 MHz mode.
13
IR3Y48M
Serial Interface Circuit
The written data comes effective at rising edge of
CSN.
Fix CSN to high when no access is conducted.
It is forbidden to write data to the address that is
not listed.
Always give 16 times SCK rising during CSN low.
All data are ignored when SCK rising during CSN
low is less than 16.
The internal registers of IR3Y48M are controlled
through 3-wire serial interface.
The 16-bit length control data consists of 2-bit
operation code, 4-bit address, and 10-bit data. The
controller should set each bit synchronizing to SCK
falling since IR3Y48M (receiver) acquire data at
SCK rising edge. The data is valid while CSN is
low.
CSN
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
O0
O1
A0
A1
A2
A3
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
SCK
SDATA
Ope
Code
Address
Data
Serial Write Control
The effect of operation code is determined by OP
pin control.
When OP pin is high, the data are always valid
regardless of O0 and O1.
When OP pin is low, operation code control is
active, and the data is written only when both O0 =
0 and O1 = 1 are true.
14
IR3Y48M
Registers
IR3Y48M has 10-bit x 5 registers to control its
operations.
All registers are write only. The serial registers are
written by serial interface.
Register Map
R/W
ADDRESS
REFERENCE NAME
A3 A 2 A1 A0
MAJOR FUNCTIONS [DATA]
ADCK polarity/ADIN connection/Frequency mode/ADC output/Black
W
0
0
0
0 Mode (1)
W
0
0
0
1 Mode (2)
W
W
0
0
0
0
1
1
0 Gain
1 Black level
Total gain
ADC code at black level (1 LSB step)
W
0
1
0
0 Test register
Test mode (ADIN coupling mode)
1. Reference name
2. Register address
[Write]
level reset/Standby
Clamp current/ADIN clamp/Clamp target/S/H, enable logic/Monitor
selection
Mode (1)
A3 A2 A1 A0
0 0 0 0
3. Register bit assignment
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Default
Functions
ADCK polarity
ADIN connection
Frequency mode
ADC output
Black level reset
X X
X
0
0
0
0
0
0
0
<->
<---->
<->
<->
<->
Standby
<->
X : Don't care
15
IR3Y48M
4. Register operations
ADCK polarity
ADIN connection
Frequency mode
ADC output
Black level reset
CONTROLS
OPERATIONS
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
Normal operation as timing chart
1
ADCK clock inversion
0
0
0
1
1
X
NOTE
ADIN function OFF
ADIN signal to AGC
ADIN signal to ADC
0
1
20 MHz mode
15 MHz mode
0
1
0
1
Standby
Normal operation [ADC data output]
ADC output High-Z [or logic of STBYN]
1
Normal operation
Black level reset [or logic of RESETN]
2
0 Normal operation
1 Standby [or logic of STBYN]
NOTES :
X : Don't care
1. ADC output is set to high impedance if one of following case is true.
Case 1 : Set "ADC output" bit to "1".
Case 2 : Set STBYN pin to low.
Case 3 : Set "Standby" bit to "1".
2. Black level integral CAP [OBCAP] is discharged if following case is true.
Case 1 : Set "Black level reset" to "1".
Case 2 : Set RESETN pin to low.
16
IR3Y48M
1. Reference name
2. Register address
[Write]
Mode (2)
A3 A2 A1 A0
0
0
0
1
3. Register bit assignment
Default
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X X 0 0 0 0 0 0 0 0
Functions
Clamp current
ADIN clamp
<->
<->
Clamp target
S/H, enable logic
<---->
<---->
Monitor selection
<---->
X : Don't care
4. Register operations
CONTROLS
D 9 D8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0
Clamp current
ADIN clamp
Clamp target
S/H, enable logic
Monitor selection
NOTE
Normal clamp
0
1
Fast clamp
0
1
Clamp operation active for ADIN
No clamp for ADIN
0
0
0
1
Normal mode [clamp both REFIN & CCDIN]
Clamp REFIN only
1
1
0
1
Clamp CCDIN only
Clamp OFF
0
0
0
1
Normal operation as timing chart
1
0
Enable control polarity inversion
1
1
S/H control polarity inversion
1
2
0
Both of S/H and enable inversion
0 Monitor OFF
0
1 CDS signal to monitor
3
1
0 AGC output monitor
4
1
1 Output REFIN and CCDIN (for calibration)
NOTES :
1.
2.
3.
4.
OPERATIONS
The S/H signals are SHR and SHD.
The enable controls are BLK, OBP, CCDCLP, and ADCLP.
At this mode, monitor output gain = 0 dB regardless of CDS gain.
At this mode, monitor output depends on CDS gain.
17
IR3Y48M
1. Reference name
2. Register address
[Write]
Gain
A3 A2 A1 A0
0
0
1
0
3. Register bit assignment
Default
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X 0 0 0 0 0 0 0 0 0
Functions
Total gain
<------------------------------------->
X : Don't care
4. Register operations
CONTROLS
D 9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Total gain
(For CCDIN input)
DECIMAL
HEX
TOTAL
GAIN (dB)
0.000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
2
0
1
2
0
0
0
0
0
0
0
0
π
0
0
0
0
0
1
1
0
1
0
3
4
3
4
0.281
0.375
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
1
62
63
3E
3F
5.813
5.906
0
0
0
0
1
1
0
0
π
0
0
0
0
0
0
0
0
0
1
64
65
40
41
6.000
6.094
0
1
0
0
π
0
0
0
0
0
128
80
12.000
0
1
1
0
π
0
0
0
0
0
192
C0
18.000
1
0
0
0
π
0
0
0
0
0
256
100
24.000
1
0
1
0
π
0
0
0
0
0
320
140
30.000
1
0
1
1
1
1
1
0
0
380
17C
35.625
1
1
0
0
1
1
1
1
1
1
1
1
1
1
0
1
1
0
381
382
17D
17E
35.719
35.813
1
0
1
1
1
1
383
17F
35.906
1
0
1
0
1
1
1
0
0
0
0
0
384
180
35.906
1
1
1
1
1
511
1FF
35.906
0.094
0.188
1
π
1
1
1
1
NOTE
18
IR3Y48M
CONTROLS
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Total gain
(For AGC input)
DECIMAL
HEX
TOTAL
0
0
0
0
0
0
0
0
0
0
0
GAIN (dB)
0.000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
2
1
2
0.094
0.188
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
3
4
3
4
0.281
0.375
0
0
0
π
1
1
1
1
1
0
62
3E
5.813
0
0
0
1
1
1
1
1
1
63
3F
5.906
0
0
1
0
0
0
0
0
0
64
40
6.000
0
0
1
0
0
0
0
0
1
65
41
6.094
π
0
0
0
0
0
0
128
80
12.000
0
0
0
0
0
192
C0
18.000
0
1
0
0
1
1
NOTE
π
0
π
0
1
1
1
1
1
1
1
0
254
FE
23.813
0
1
1
1
1
1
1
1
1
255
FF
23.906
1
0
0
0
0
0
0
0
0
256
100
23.906
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
257
258
101
102
23.906
23.906
1
1
1
π
1
1
1
1
1
1
511
1FF
23.906
2
NOTES :
1. Gain is always (35.90625 dB, TYP.) for code greater than 382 (decimal).
2. Gain is always (23.906 dB, TYP.) for code greater than 254 (decimal).
19
IR3Y48M
1. Reference name
2. Register address
[Write]
Black level
A3 A2 A1 A0
0
0
1
1
3. Register bit assignment
Default
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X X X 1 0 0 0 0 0 0
Functions
Black level
<----------------------------->
X : Don't care
4. Register operations
OPERATIONS [ADC CODE : BINARY]
B 9 B 8 B7 B 6 B5 B4 B 3 B2 B1 B 0
Black level
0
0
0
0
FORBIDDEN
1
1
1
1
1
1
1
15
F
0
0
0
0
0
1
16
17
10
11
0
0
0
0
0
0
1
1
0
0
0
1
FORBIDDEN
1
0
0
0
0
0
HEX
0
0
π
1
0
0
DECIMAL
0
0
1
0
0
1
0
18
12
0
0
1
0
0
1
1
19
13
0
1
0
0
π
0
0
0
32
20
1
0
0
0
0
0
0
64
40
π
π
1
1
1
1
1
0
0
124
7C
1
1
1
1
1
0
1
125
7D
1
1
1
1
1
1
0
126
7E
1
1
1
1
1
1
1
127
7F
NOTE :
1. Codes 1 to 15 are available but not recommended black calibration period is specified under 15 < code < 128.
20
NOTE
IR3Y48M
1. Reference name
2. Register address
[Write]
Test register
A3 A2 A1 A0
0
1
0
0
3. Register bit assignment
Default
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X X X 0 0 0 0 0 0 0
Functions
ADIN test mode
<->
X : Don't care
4. Register operations
CONTROLS
D9 D 8 D7 D6 D5 D4 D3 D2 D1 D0
ADIN test mode
0
1
OPERATIONS
Normal operation
VCOM centered ADIN for AC coupling
NOTE :
D5 to D0 must always be "0".
Test register (D6) is prepared for ADIN AC coupled
input. Using this mode the signal center is set to
VCOM. No clamp signals are required at this mode.
Connect C-coupled output to ADIN. The resistance
50 k$ between ADIN (14 pin) and CLPCAP (13
pin) stabilize the DC level at ADIN pin.
21
IR3Y48M
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Power supply voltage
SYMBOL
AVDD
Voltage difference
Input current
Analog input voltage
Digital input voltage
(Input pin)
Digital input voltage
(Output pin)
(AVSS = DVSS = 0 V, all voltages are with respect to GND.)
RATING
–0.3 to +4.5
UNIT
V
NOTE
–0.3 to +4.5 or AVDD + 0.3
V
1
CONDITIONS
DVDD
VDLT
DVDD – AVDD
0.3
V
IIN
Except PS
±10
mA
VINA
AVSS – 0.3 to AVDD + 0.3
V
VINL
AVSS – 0.3 to AVDD + 0.3
V
VONL
AVSS – 0.3 to AVDD + 0.3
V
Operating temperature
TOPR
–30 to +85
˚C
Storage temperature
TSTG
–40 to +125
˚C
NOTES :
2
WARNING :
1. The higher voltage of 4.5 V and AVDD + 0.3 V specifies
maximum value of DVDD absolute maximum rating.
2. The VONL limits the excess voltage applied to digital
output pins.
Operation at or beyond these limits may result in permanent
damage to the device. Normal operating specifications are
not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS = DVSS = 0 V, all voltages are with respect to GND.)
PARAMETER
Analog
Supply voltage
Digital output
SYMBOL
CONDITIONS
AVDD
At start-up, turn on AVDD before (or at
DVDD
the same time as) turning on DVDD.
MIN.
2.7
TYP.
3.0
MAX.
3.6
UNIT
V
2.7
3.0
AVDD
V
ELECTRICAL CHARACTERISTICS
Supply Current
(TA = +25 ˚C, AVDD = DVDD = 3.0 V)
PARAMETER
Analog
SYMBOL
IA15
CONDITIONS
fs = 15 MHz
MIN.
TYP.
28
MAX.
34
UNIT
mA
Supply current at
Digital
ID15
(At 15 MHz mode)
3
6
mA
normal operation
Analog
Digital
IA20
ID20
fs = 20 MHz
(At 20 MHz mode)
36
3.5
44
7
mA
mA
IPE
IPD
(At 20 MHz mode)
38
46
0.1
mA
mA
Supply current at monitor active
Supply current at power down
NOTES :
1. Specified under monitor function off.
2. Measured under no analog input and clock fixed at low.
22
NOTE
1
2
IR3Y48M
Analog Specifications
(Unless otherwise specified, AVDD = DVDD = 3.0 V, TA = +25 ˚C, signal frequency fIN = 1 MHz,
signal level = –1 dB (full scale))
The current direction flowing into the pin is positive direction.
CDS & CLAMP CIRCUITS
PARAMETER
Analog input range
Input referred noise
Input capacitance
Input Bandwidth
Clamp voltage
Black calibration period
(Sampling frequency fS = 20 MHz)
SYMBOL
VICDS
VIAI
NI
CIN
CONDITIONS
Normally
At ADIN
At fs = 20 MHz
MIN.
TYP.
1.1
1.1
100
µVrms
At gain = min.
400
µVrms
CCDIN, ADIN & REFIN
15
Normally
1.65
1.8
At ADIN
1.15
1.3
tBKCAL
UNIT
Vp-p
Vp-p
At gain = max.
CBW
VCLPCAP
MAX.
NOTE
1
2
pF
1
1.95
pixel
V
1.45
V
2000
pixel
3
4, 5
NOTES :
1. Normally : Signal path through CDS/AGC/ADC
In this case analog input range is downward
from clamp voltage.
ADIN
: Signal bypassing CDS (Direct AGC or ADC
input)
In this case analog input range is upward
from clamp voltage.
2. Specified at MONOUT pin. The noise bandwidth is 100
kHz to 5 MHz.
3. Bandwidth from CCDIN/REFIN to ADC. The bandwidth
is specified as the settling time of ADC output for step
input (full scale – 1 dB) response (at gain = min.).
4. Black calibration period is the period of stabilization of
output code within ±1 LSB (average) compared to register
value for the black level code of 0 to 50% of the full scale
input. (Assuming external capacitance = 0.033 µF.)
External capacitor value to OBCAP pin determines the
bandwidth of the black level cancel loop. Since the gain
of the loop depends on sampling frequency, the
maximum frequency (settling within certain pixels) and
the minimum frequency (avoiding oscillation of the circuit)
are defined.
5. Select the external capacitor referring the following list
based on the minimum and maximum operating
frequencies.
If the black level settling specification (within 2 000
pixels) could be ignored, the maximum sampling
frequency for 0.1 µF and 0.33 µF will extend according
to the increment.
PARAMETER MODE OBCAP MIN. MAX. UNIT
20 MHz
0.033 µF 7.6
20 MHz
Available
mode
sampling
0.033 µF 5.8
15 MHz
15 MHz
frequency
0.1 µF
2.2
5.7 MHz
mode
0.33 µF 0.6
1.7 MHz
23
IR3Y48M
TOTAL GAIN
PARAMETER
Min. gain
SYMBOL
CONDITIONS
Gain between
GMNN
At normal operation Max. gain
Gain step
GMXN
Min. gain
GMNNA
Max. gain
Gain step
GMXNA
At ADIN operation
CDS and AGC total gain relative
accuracy
GST
GSTA
REFIN/CCDIN and
MONOUT
Gain between ADIN and
MONOUT
MIN.
–1.9
TYP.
–0.9
MAX.
0.1
34.906 35.906 36.906
0
0.094 0.188
–1.3
–0.3
0.7
22.906 23.906 24.906
0
0.094 0.188
±1
ERPA
UNIT
dB
NOTE
dB
dB
1
dB
dB
dB
1
LSB
2
NOTES :
1. Gain is specified for gain between AGC input and MONOUT output.
2. Gain measured at MONOUT pin.
A/D CONVERTER CIRCUIT
PARAMETER
Resolution
(fS = 20 MHz. Signal is given to ADIN.)
SYMBOL
RES
CONDITIONS
MIN.
fs = 20 MHz
TYP.
MAX.
10
UNIT
bits
±1.5
±2.5
LSB
±0.5
±1.0
LSB
Integral non-linearity
INL
Differential non-linearity
DNL
S/N
S/ (N+D)
SN
SND
ADC common voltage
VREF voltage (positive)
VCOM
1.0
1.1
1.2
V
VRP
1.25
1.35
1.45
V
VREF voltage (negative)
VRN
0.75
0.85
0.95
V
ADC output black level
calibration code
CCAL
16
127
LSB
Black level step
STCAL
(At 20 MHz mode)
fs = 15 MHz
(At 15 MHz mode)
58
56
1
NOTE :
1. Black level calibration period (tBKCAL) is specified for code = 16 to 127 LSB.
Although black level code of 1 to 15 could be set, tBKCAL is not guaranteed for these codes.
24
NOTE
dB
dB
LSB
1
IR3Y48M
Switching Characteristics
(AVDD, DVDD = 2.7 to 3.6 V, AVSS, DVSS = 0 V, TOPR = –30 to +85 ˚C, CL < 10 pF)
PARAMETER
Conversion speed
Clock cycle period
SYMBOL
fS
tCYC
CONDITIONS
MIN.
0.5
TYP.
MAX.
20
Clock rise time
tR
Clock fall time
tF
(30%/70%) AVDD, DVDD
(70%/30%) AVDD, DVDD
Clock low period
Clock high period
tL
tH
23
23
ns
ns
Min. reference pulse
tWR
10
ns
Min. data pulse
Reference sampling delay
tWD
tDR
10
50
UNIT
MHz
NOTE
ns
2
2
4
ns
ns
ns
Data sampling delay
tDD
Reference pulse setup
tSUR
–3
ns
ns
1
Data pulse setup
tSUD
–3
ns
2
Reference pulse hold
5
ns
Data pulse hold
tHR
tHD
5
ns
Enable pulse setup
Enable pulse hold
tSUE
tHE
10
10
ns
ns
Tristate disable delay
tDLD
Active/High-Z
20
ns
Tristate enable delay
tDLE
tDL1
High-Z/Active
20
ns
ns
ADC output data delay
4
ns
2
tDL2
35
NOTES :
1. When SHR› is earlier than ADCKfi, assumed positive.
(In the above table, SHR› can be delayed a maximum of 3 ns behind ADCKfi.)
2. When SHD› is earlier than ADCK›, assumed positive.
(In the above table, SHD› can be delayed a maximum of 3 ns behind ADCK›.)
25
ns
IR3Y48M
TIMING CHART
tDR
tDD
CCD
Reference sampling
tWR
Data sampling
tHR
tSUR
SHR
tWD
tHD
tSUD
SHD
tCYC
tH
tL
ADCK
tDL
DO0-DO9
tHE
tSUE
BLK
OBP
CCDCLP
ADCLP
ADIN : ADC Direct Input
0.7AVDD
ADCK
0.3AVDD
ADC Input
N+6
N+5
N+1
N+4
5.5 clk
delay
N
tDL1
Sampling Point
0.7DVDD
Digital Output
N–6
N–5
N–2
tDL2
26
N–1
N
0.3DVDD
IR3Y48M
[When ADCK Inverted by Register]
0.7AVDD
ADCK
0.3AVDD
ADC Input
N+6
N+5
N+1
6.0 clk
delay
N+4
N
tDL1
Sampling Point
0.7DVDD
N–6
Digital Output
N–5
N–2
N–1
N
0.3DVDD
tDL2
NOTE : At default condition of ADIN mode, falling edge of sampling and rising edge of data out are selected. If each edge
should be a rising edge, invert the ADCK by register setting. (The figure shown on the previous page is the default, the
following is the inverted one.)
Clock Waveform
tH
0.7AVDD
0.3AVDD
tR
tF
tL
tCYC
27
IR3Y48M
CONTROL INTERFACE TIMING
(AVDD, DVDD = 2.7 to 3.6 V, AVSS, DVSS = 0 V, TOPR = –30 to +85 ˚C)
PARAMETER
SCK clock cycle time
SCK clock low width
SYMBOL
fSCYC
tSLO
CONDITIONS
MIN.
TYP.
MAX.
10
40
UNIT
MHz
ns
SCK clock high width
tSHI
40
ns
Setup time
Hold time
tSSU
tSH
20
20
ns
ns
SCK, CSN rise time
tSR
30%/70%
6
SCK, CSN fall time
tSF
70%/30%
6
Serial data number
SNUM
16
ns
ns
pcs
50%DVDD
CSN
tSSU
fSCYC
tSLO
tSHI
tSH
50%DVDD
SCK
tSSU tSH
O0
O1
D9
D8
A0 π
50%DVDD
SDATA
SNUM
Serial I/F Timing
Digital DC Characteristics
(AVDD, DVDD = 2.7 to 3.6 V, AVSS, DVSS = 0 V, TOPR = –30 to +85 ˚C, measured as DC characteristics.)
PARAMETER
Input "Low" voltage
Input "High" voltage
SYMBOL
VIL1
VIH1
CONDITIONS
MIN.
TYP.
MAX. UNIT
0.3AVDD
V
0.7AVDD
V
Output "Low" voltage
VOL
IOL = 1 mA
Output "High" voltage
VOH
IOH = –1 mA
"High" leakage current
ILING
±10
µA
High-Z leakage current
IOZ
±10
µA
0.3DVDD
0.7DVDD
V
V
NOTE :
1. Specified for SHD, SHR, ADCK, BLK, OBP, CCDCLP, ADCLP, CSN, SCK, SDATA, RESETN, STBYN, and OP.
28
NOTE
1
IR3Y48M
Data Output Sequence
CCD
0
1
2
3
4
5
6
7
8
SHR
SHD
ADCK
BLK
DO0-DO9
0
Black Level Code
Pixel Data Readout Sequence (1) : Conversion Start
CCD
(N – 1)
(N)
SHR
SHD
ADCK
BLK
DO0-DO9
N–8 N–7
N–6 N–5
N–4 N–3 N–2 N–1
N
Pixel Data Readout Sequence (2) : Conversion End
29
1
2
3
IR3Y48M
APPLICATION CIRCUIT EXAMPLE
The following schematic is the reference circuit for
system design.
Optimize capacitance and resistance according to
the system environment.
CHIP
CONTROL
SIO
ANALOG
CONTROL PULSE
0.1 µF
36
35
34
33
32
31
30
29
28
27
26
25
OP
RESETN
AVDD3
AVSS3
STBYN
CSN
SDATA
SCK
OBP
CCDCLP
BLK
ADCLP
DIGITAL
37 DO0
SHD 24
38 DO1
SHR 23
39 DO2
ADCK 22
40 DO3
NC 21
41 DO4
AVSS1 20
42 DVSS
AVDD1 19
SAMPLING
PULSE
0.1 µF
DIGITAL
OUT
0.1 µF
4.7 k$
TOP VIEW
43 DVDD
AISET 18
44 DO5
NC 17
45 DO6
MONOUT 16
MONITOR
0.033 µF
3 V (TYP.)
AVSS2
VCOM
CCDIN
5
6
7
8
9
10
11
0.1 µF
CCD
30
REFIN
AVSS2
4
0.1 µF
AVDD2
3
0.1 µF
AVDD2
2
0.1 µF
1
0.1 µF
VRP
CLPCAP 13
VRN
48 DO9
NC
ADIN 14
AVDD4
47 DO8
NC
OBCAP 15
0.1 µF
10 µF
+
46 DO7
12
0.1 µF
ADIN
0.1 µF
0.1 µF
PACKAGES FOR CCD AND CMOS DEVICES
PACKAGE
(Unit : mm)
48 QFP (QFP048-P-0707)
0.15±0.05
0.2±0.08
M
(1.0)
25
36
37
48
13
7.0±0.2
12
(1.0)
0.1±0.1
31
0.1
8.0±0.2
0.65±0.2
1.45±0.2
9.0±0.3
Package
base plane
1
(1.0)
(1.0)
7.0±0.2
0.08
24
9.0±0.3
0.5TYP.