AK9822M

ASAHI KASEI
[AK9822]
AK9822
2Kbit EEPROM with 2ch 8bit D/A Converter
General Description
The AK9822 includes 2 channel, 8 bit D/A converters with on-chip output buffer amps and it is
capable to store the input digital data of each D/A converter by on-chip non-volatile CMOS EEPROM.
The AK9822 is optimally designed for various circuit adjustments for consumer and industrial
equipments and it is ideally suited for replacing mechanical trimmers.
Feature
□
EEPROM section
128 words×16bit
One chip microcomputer interface
Sequential register read
□
D/A Converter section
2 channel
Resolution : 8bit
Differential Non-Linearity
Linearity Error
Output Voltage Range
□
□
: 1.8V~5.5V
: 2.7V~5.5V
Power Down Function
CS
Control Logic
DO
±1.0 LSB
±1.5 LSB
GND ~ VCC
Wide VCC operation
・EEPROM section
・D/A Converter Section
SK
DI
:
:
:
Latch
Decorder
Instruction
Register
Data
Register
8
8bit
Latch
8bit
Latch
EEPROM
128×16
GND
8
8bit
D/A
+
AO0
8
8bit
D/A
+
AO1
VCC
Block Diagram
DAD01E-01
2012/09
- 1 -
ASAHI KASEI
■
[AK9822]
Ordering Guide
AK9822M
■
-40C~+85C
8pin SSOP
Pin Layout
AO1
、
CS
SK
DO
1
2
3
4
8
7
6
5
AO0
VCC
DI
GND
8pin SSOP(Pin pitch:0.65mm)
■
Pin Description
No.
Pin Name
1
AO1
2
CS
I/O
O
I
Function
Analog Output Pin
Chip Select Pin
(Schmitt-trigger input)
(Schmitt-trigger input)
3
SK
I
Serial Clock Pin
4
DO
O
Serial Data Output Pin
5
GND
-
Ground Pin
6
DI
7
VCC
-
Power Supply
8
AO0
O
Analog Output Pin
I
Serial Data Input Pin
DAD01E-01
2012/09
- 2 -
ASAHI KASEI
[AK9822]
Functional Description
The AK9822 is composed of EEPROM and the 8bit D/A converter of two channels with the output
buffer amplifier.
The AK9822 can connect to the serial communication port of popular one chip microcomputer
directly (3 line negative clock synchronous interface).
The AK9822 takes the data of the DI pin by the rising edge of the SK pin and outputs the data from
the DO pin by the falling edge of the SK pin.
The AK9822 has 7 instructions such as READ, WRITE, WREN, WRDS, PDEN, PDDS and CALL.
The AK9822 is operated by inputting these instructions from the serial interface. Each instruction is
organized by op-code block (8bits), address block (8bits) and data (8bits×2).
The DO pin is "Hi-Z" state except that the DO pin outputs the data of the internal register and the
status of Ready/Busy.
WRITE protection function
There are two states such as the WRITE enable state and the WRITE disable state in the AK9822.
In the WRITE disable state the WRITE instruction becomes invalid and is not executed.
When Vcc is applied to the part, the part powers up in the WRITE disable state and the part
becomes the WRITE enable state by inputting the WREN instruction. The WRITE enable state
continues until the WRDS instruction is executed or Vcc is removed from the part.
Execution of a READ instruction is independent of both WREN and WRDS instructions.
■
Power down function
There are two modes such as the power down mode and the normal mode in the AK9822. When
the AK9822 is in the power down mode, the D/A converter section is in the standby state. At this
time, the outputs of the D/A converters become "Hi-Z".
■
When Vcc is applied to the part, the AK9822 is in the power down mode. When a AUTO READ
function is executed, the part becomes the normal mode. After the AUTO READ function is
executed, the mode of the part can be switched by the PDEN and PDDS instructions. The AK9822
becomes the power down mode by inputting the PDEN instruction. The part is in the power down
mode until the PDDS instruction is executed. When the PDDS instruction is executed, the part
becomes the normal mode.
When returning to the normal mode from the power down mode, the D/A converters output the
voltage value set before entering the power down mode. The relation between the D/A converter
state and the mode are shown in the table 1.
Mode
State of D/A converter
Power down mode
standby
Normal mode
normal
Table 1. The relation between the state of D/A converter and the mode
DAD01E-01
2012/09
- 3 -
ASAHI KASEI
[AK9822]
Output of D/A converter
The output of the D/A converters can be set by the WRITE and the CALL instructions.
Upper 8bit data (D15~D8) of the first address of the internal EEPROM (the address "0")
corresponds to "AO" of the D/A converter output. Lower 8bit data (D7~D0) of the address
"0" corresponds to "A1". The internal composition of EEPROM is shown in the table2.
Address
D15~D8
D7~D0
0
Set data of A0
Set data of A1
1
General purpose memory
■
~
~
127
General purpose memory
Table2. Internal composition of EEPROM
If the WRITE instruction by which the address "0" is specified is executed at the normal mode, the
outputs of the D/A converter of A0 and A1 are set by the specified data.
When the WRITE instruction by which the address "0" is specified is executed at the WRITE enable
state and the normal mode, the data is written in the address "0" of EEPROM and the outputs of the
D/A converter are set. When the WRITE instruction by which the address "0" is specified is
executed at the WRITE disable state and the normal mode, the data is not written in EEPROM and
the outputs of the D/A converter are set. Table3 shows the relation between EEPROM, D/A
converter and WRITE instruction.
State of AK9822
Power down
mode
Normal mode
State of address"0"
WRITE enable
The data change to the specified data.
WRITE disable
The data does not change.
WRITE enable
The data change to the specified data.
WRITE disable
The data does not change.
Output of A0 and A1
The DAC outputs
are "Hi-Z".
The DAC outputs
change to the
specified data.
Table3. Relation between EEPROM, D/A converter and WRITE instruction
If the CALL instruction is executed, the outputs of the D/A converter are set by the data of the
general purpose memory (the address "1" -"127"). The CALL instruction is composed by the
op-code and the address.
When the CALL instruction is executed at the normal mode, the D/A converter output of A0 is set by
the upper 8bit data (D15~D8) of the specified address and the output of A1 is set by the lower 8bit
data (D7~D0). The CALL instruction is not executed at the power down mode.
DAD01E-01
2012/09
- 4 -
ASAHI KASEI
[AK9822]
AUTO READ function
AUTO READ function automatically reads the content of EEPROM and sets the output of the D/A
converter of two channels, when Vcc is applied to the part.
When Vcc is applied to the part in CS="L", the AUTO READ function starts by falling CS pin first.
After the CS pin is made a low level, the output of AO0 and AO1 is set within 2ms. At this time, the
input pins (SK, DI) other than the CS pin are not accepted, and the serial data is not output from the
DO pin. If the WREN instruction is executed after the AUTO READ function finished, AK9822
becomes the WRITE enable state.
After Vcc is applied to the part, the AUTO READ function is executed only once.
AUTO READ function is executed when Vcc is applied to the part in CS="L".
■
(note) Because AK9822 always executes the AUTO READ function first after Vcc is applied to the
part, AK9822 is not able to accept the instruction for the first period of "L" of the CS.
VCC
AK9822 can accept the instruction.
CS
1
SK
DI
1
2
0
3
1
4
0
Hi-Z
AO0,AO1
Min.2ms
■ Instruction and Composition of the data
Each instruction consist of op-code, address, and data (8bit×2) composed in each 8bit.
composition of the WRITE instruction is shown as follows.
First
MSB
1
The
Last
LSB
0
1
0
0
1
0
0
A6 A5 A4 A3 A2 A1 A0
0 D15 D14 D13 D12
Op- Code
D2 D1 D0
Data bit
Address bit
D15~D8
D7~D0
Set data A0
Set data of A1
A6 A5 A4 A3 A2 A1 A0
0
0
0
0
0
0
0
0
0
0
0
~
0
0
1
1
1
1
1
1
1
1
General purpose memory
Serial input decode table
MSB
D/A output
LSB
0
0
0
0
0
0
0
≒
( VCC / 256 )
×1
0
0
0
0
0
~
0
0
1
≒
( VCC / 256 )
×2
1
1
1
1
1
1
1
0
≒
( VCC / 256 )
×255
1
1
1
1
1
1
1
1
≒
~
0
VCC
DAD01E-01
2012/09
- 5 -
ASAHI KASEI
[AK9822]
Instruction Set
The AK9822 has 7 instructions such as READ, WRITE, WREN, WRDS, PDEN, PDDS, CALL.
Each instruction consists of Op-code, address and data. The instruction set is shown in the table4.
When the instructions are executed consecutively, the CS pin should be brought to a high level for a
minimum of tCS between consecutive instruction cycle.
Instruction
Op-code
Address
Data
READ
1 0 1 0 1 0 0 0 A6 A5 A4 A3 A2 A1 A0 0 D15~D0
WRITE 1 0 1 0 0 1 0 0 A6 A5 A4 A3 A2 A1 A0 0 D15~D0
WREN 1 0 1 0 0 0 1 1 * * * * * * * * *~
WRDS 1 0 1 0 0 0 0 0 * * * * * * * * *~
PDEN
1 0 1 0 1 1 0 0 * * * * * * * * *~
PDDS
1 0 1 0 0 1 1 0 * * * * * * * * *~
CALL
1 0 1 0 0 0 1 0 A6 A5 A4 A3 A2 A1 A0 0
*~
TEST
1 0 1 0 1 1 1 1 * * * * * * * * *~
(note) User can't use this instruction.
Table4. Instruction set for AK9822
Comments
read memory
write memory
write enable
write disable
power down enable
power down disable
set DAC outputs
TEST (note)
*: Don't Care
■ WRITE
The WRITE instruction is followed by 16 bits of data to be written into the specified address. After
the 32nd rising edge of SK to read the DI pin in, the AK9822 will be put into the automatic write
time-out period.
The DO pin indicates the Ready/Busy status of the EEPROM in the AK9822. After the 32nd rising
edge of SK to read the Di pin in, the AK9822 will be put into the automatic write time-out period.
When the automatic write time-out period starts, the DO pin outputs the Ready/Busy status. When
the DO pin outputs the low level, the AK9822 is in the automatic write time-out and the next
instruction can not be accepted. When the DO pin outputs the high level, the automatic write
time-out period has ended and the AK9822 is ready for a next instruction.
When the CS pin is changed to high level after confirmation of Ready/Busy signal on the DO pin, the
DO pin becomes "Hi-Z". The Ready/Busy signal outputs until the CS pin is changed to high level,
or the initial 1 bit ("1") of the next instruction is given to the part.
CS
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19
31 32
1
0
1
0
0
1
0
0 A6 A5 A4 A3 A2 A1 A0 0 D15 D14 D13
D1 D0
SK
DI
DO
Hi-Z
BUSY
The AK9822 output the high level (Ready status),
if a previous instruction is WRITE.
READY
tE/W
WRITE
DAD01E-01
2012/09
- 6 -
ASAHI KASEI
[AK9822]
■ READ
The READ instruction is the only instruction which outputs serial data on the DO pin. When the
17th falling edge of SK is received, the Do pin will come out of high impedance state and shift out
the data from D15 first in descending order which is located at the address specified in the
instruction.
○ Sequential READ
When the clock is provided on the SK pin after the data in the specified address is read, the data
in the next address is read.
When the clock is provided on the SK pin after the data in the address:1111111 is read, the data
in the address:0000000 is read.
CS
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19
1
0
1
0
1
0
0
0 A6 A5 A4 A3 A2 A1 A0 0
31 32 33 34 35
SK
DI
Hi-Z
DO
D15 D14 D13
The AK9822 output the high level (Ready status),
if a previous instruction is WRITE.
D1 D0 D15 D14 D13
1st Data
Hi-Z
2nd Data
READ
■ WREN/WRDS
There are two states such as the WRITE enable state and the WRITE disable state in the AK9822.
In the WRITE disable state the WRITE instruction becomes invalid and is not executed. When Vcc
is applied to the part, it powers up in the WRITE disable state. The WRITE instruction must be
preceded by a WREN instruction. This state remains enabled until a WRDS instruction is executed
or Vcc is removed from the part.
Execution of a read instruction is not affected by both WREN and WRDS instruction.
CS
1
2
3
4
5
6
1
0
1
0
0
0
7
8
9 10 11 12 13 14 15 16 17
SK
DI
X
X
X
WREN=11
WRDS=00
X
X
X
X
X
Hi-Z
DO
The AK9822 output the high level (Ready status),
if a previous instruction is WRITE.
WREN/WRDS
DAD01E-01
2012/09
- 7 -
ASAHI KASEI
[AK9822]
■ PDEN/PDDS
There are two modes such as the power down mode and the normal mode in the AK9822. The
mode of the part can be switched by the PDEN and PDDS instructions. The AK9822 becomes the
power down mode by inputting the PDEN instructions. When the PDDS instruction is executed, the
part becomes the normal mode.
When returning to the normal mode from the power down mode, the D/A converters output the
voltage value set before entering the power down mode.
CS
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17
1
0
1
0
1
1
0
0
X
SK
DI
X
X
X
X
X
X
X
Hi-Z
DO
The AK9822 output the high level (Ready status),
if a previous instruction is WRITE.
PDEN
CS
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17
1
0
1
0
0
1
1
0
X
SK
DI
X
X
X
X
X
X
X
Hi-Z
DO
The AK9822 output the high level (Ready status),
if a previous instruction is WRITE.
PDDS
■ CALL
The outputs of the D/A converters is set by inputting a CALL instruction. Upper 8bit data (D15~D8)
of the specified address corresponds to "A0". Lower 8bit data (D7~D0) of the specified address
corresponds to "A1".
The CALL instruction is not executed at the power down mode.
CS
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
1
0
1
0
0
0
1
0 A6 A5 A4 A3 A2 A1 A0
SK
DI
DO
0
Hi-Z
The AK9822 output the high level (Ready status),
if a previous instruction is WRITE.
AO0
AO1
tLDD
CALL
DAD01E-01
2012/09
- 8 -
ASAHI KASEI
[AK9822]
Absolute Maximum Ratings
Parameter
Power supply
Input voltage
Ambient temperature
Storage temperature
Symbol
Conditions
Spec.
Units
VCC
VIO
Ta
TST
Relative to GND
Relative to GND
-0.6~+7.0
-0.6~VCC+0.6
-40~+85
-65~+150
V
V
℃
℃
Recommended Operating conditions
Parameter
Power supply
Analog output
source current1
Analog output
sink current1
Analog output
source current2
Analog output
sink current2
Analog output
load capacitance
Symbol
max
5.5
5.5
Units
1
mA
IAH1
1
mA
IAL2
500
μA
IAH2
500
μA
AOC
1.0
μF
VCC1
VCC2
Conditions
DAC operation
EEPROM operation
IAL1
min
2.7
1.8
typ
V
V
3.6V≦VCC≦5.5V
2.7V≦VCC<3.6V
DAD01E-01
2012/09
- 9 -
ASAHI KASEI
[AK9822]
Electrical characteristics
■ DC characteristics
(VCC=+1.8V~5.5V, GND=0V, Ta=-40~+85℃ unless otherwise specified)
Parameter
Operating
power consumption
Symbol
IDD1
IDD2
(note1)
Standby
(note2)
power consumption
Input high voltage
CS,SK pin
Input high voltage
DI pin
Input low voltage
CS,SK pin
Input low voltage
DI pin
Output high voltage
Output low voltage
Input leakage current
3 state
leakage current
IDD3
IDD4
VIH1
VIH2
VIH3
VIH4
VIL1
VIL2
VIL3
VIL4
VOH1
VOH2
VOL1
VOL2
ILI
IOZ
Conditions
Normal mode
WRITE, 1/tSKP=2MHz
Normal mode
READ, 1/tSKP=2MHz
Power down mode
READ, 1/tSKP=2MHz
Power down mode
standby(CS="H")
2.5V≦VCC≦5.5V
1.8V≦VCC<2.5V
2.5V≦VCC≦5.5V
1.8V≦VCC<2.5V
2.5V≦VCC≦5.5V
1.8V≦VCC<2.5V
2.5V≦VCC≦5.5V
1.8V≦VCC<2.5V
(note4)、IOH=-50uA
(note5)、IOH=-50uA
(note4)、IOL=1.0mA
(note5)、IOL=0.1mA
VCC=5.5V、VIN=VCC
VCC=5.5V、DO=VCC
CS="H"
min
max
5.5
Units
mA
2.3
mA
0.75
mA
1.0
μA
0.8×VCC
0.9×VCC
0.7×VCC
0.8×VCC
0.2×VCC
0.1×VCC
0.3×VCC
0.2×VCC
VCC-0.3
VCC-0.3
0.4
0.4
±1.0
±1.0
V
V
V
V
V
V
V
V
V
V
V
V
μA
μA
note1. VCC=5.5V、VIN=VIH/VIL、DO=open
note2. VCC=5.5V、SK/DI=VCC/GND、DO=open
note3. Please refer to the "Power down function" regarding the power down mode.
note4. 2.5V≦VCC≦5.5V
note5. 1.8V≦VCC<2.5V
DAD01E-01
2012/09
- 10 -
ASAHI KASEI
[AK9822]
■ AC characteristics
1)EEPROM section
(VCC=+1.8V~5.5V, GND=0V, Ta=-40~+85℃ unless otherwise specified)
Parameter
SK cycle
SK pulse width
SK pulse high level width
(note10)
CS setup time
CS hold time
Symbol
tSKP1
tSKP2
tSKW1
tSKW2
tSKH1
tSKH2
tSKH3
tCSS
tCSH1
READ,
WREN,WRDS
PDEN,PDDS
CALL,
tCSH2
WRITE (note9)
SK setup time
tSKS
Data setup time
tDIS1
tDIS2
tDIS3
tDIH1
tDIH2
tDIH3
tPD1
tPD2
tPD3
tE/W
tRC
tCS
tOZ
data hold time
DO pin output delay
(note11), (note13)
Selftimed program time
Write recovery time
Min. CS high time (note12)
DO pin high-Z time
Conditions
(note6),(note7)
(note8)
(note6),(note7)
(note8)
(note6)
(note7)
(note8)
(note6)
(note7)
(note8)
(note6)
(note7)
(note8)
(note6)
(note7)
(note8)
min
500
1.5
250
750
250
500
750
100
100
max
Units
ns
μs
ns
ns
ns
ns
ns
ns
ns
2
μs
100
ns
100
150
200
100
150
200
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
150
250
500
10
100
250
500
note6. 4.0V≦VCC≦5.5V
note7. 2.5V≦VCC<4.0V
note8. 1.8V≦VCC<2.5V
note9. In case of the following case, tCSH is min.100ns.
・The WRITE instruction by which the address "0" is specified is executed at the
WRITE enable state.
・The WRITE instruction by which the address "1~127" is specified is executed.
note10. The tSKH is the high pulse width of 16th SK pulse in READ operation. When the
data in the next address are read sequentially by continuing to provide clock, tSKH
are applied to the high pulse width of 32nd and 48th (multiple of 16) SK pulse in
READ operation.
note11. In case that Ready/Busy signal output, tPD is min.1μs.
note12. The first CS high time is the tACS after Vcc is applied to the part.
note13. CL=100pF
DAD01E-01
2012/09
- 11 -
ASAHI KASEI
[AK9822]
2)D/A converter section
(2.7V≦VCC≦5.5V, GND=0V, Ta=-40~+85℃ unless otherwise specified)
Parameter
Resolution
Differential non-linearity
linearity error (note14)
Buffer amp
output voltage range
3.6V≦VCC≦5.5V
Buffer amp
output voltage range
2.7V≦VCC<3.6V
CS setup time when
VCC is applied to the part
CS hold time in AUTOREAD
DAC setting time (note15)
Symbol
Conditions
Monotonic
min
typ
AO=OPEN
-1.0
-1.5
0
0
max
8
+1.0
+1.5
Units
bit
LSB
LSB
DNL
NL
0.1≦AO≦VCC-0.1
VAO1
|IAO|= 0μA
0.1
VCC-0.1
V
VAO2
|IAO|≦1mA
0.3
VCC-0.3
V
VAO3
|IAO|= 0μA
0.1
VCC-0.1
V
VAO4
tCSA
|IAO|≦500μA
0.3
5.0
VCC-0.3
V
μs
tACS
tLDD1
tLDD2
5.0
3.6V≦VCC≦5.5V
2.7V≦VCC<3.6V
100
200
400
μs
μs
μs
note14.
Integral non-linearity is the error between the actual line and the ideal line. The
ideal line exhibits a perfect linear D/A converter output characteristics between the
input digital data "00" and the input digital data "FF".
note15. CL=100pF
DAD01E-01
2012/09
- 12 -
ASAHI KASEI
[AK9822]
■ Timing waveform
tCS
tCSS
CS
tSKP
tSKS
tSKWL
tSKWH
SK
tDIS
tDIH
DI
tRC
Hi-Z
DO
Instruction input timing
CS
tSKH
tCSH1
SK
DI
0
tPD
DO
D15
D2
tOZ
D1
D0
Data latch timing in READ operation
CS
tCSH2
SK
DI
A1
A0
0
tLDD
90%
D/A
10%
D/A converter output timing in CALL instruction
DAD01E-01
2012/09
- 13 -
ASAHI KASEI
[AK9822]
CS
tCSH2
SK
DI
D2
D1
D0
tLDD
90%
D/A
10%
Programming timing in WRITE instruction
CS
SK
DI
D0
tPD
DO
tE/W
tOZ
BUSY
READY
tLDD
90%
D/A
10%
READY/BUSY signal output timing
note : READY/BUSY signal does not output when WRITE instruction is executed in WRITE
disable state.
VCC
CS
min. 2ms
tCSA tACS
AO0
(D/A OUT)
AO1
(D/A OUT)
Hi-Z
Hi-Z
AUTO READ timing
DAD01E-01
2012/09
- 14 -
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office
of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current status of the
products.
• Descriptions of external circuits, application circuits, software and other related information contained
in this document are provided only to illustrate the operation and application examples of the
semiconductor products. You are fully responsible for the incorporation of these external circuits,
application circuits, software and other related information in the design of your equipments. AKM
assumes no responsibility for any losses incurred by you or third parties arising from the use of these
information herein. AKM assumes no liability for infringement of any patent, intellectual property, or
other rights in the application or use of such information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license
or other official approval under the law and regulations of the country of export pertaining to customs
and tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components Note1) in any safety,
life support, or other hazard related device or system Note2) , and AKM assumes no responsibility for
such use, except for the use approved with the express written consent by Representative Director of
AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it,
and which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to
function or perform may reasonably be expected to result in loss of life or in significant injury or damage to
person or property.
• It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or
otherwise places the product with a third party, to notify such third party in advance of the above
content and conditions, and the buyer or distributor agrees to assume any and all responsibility and
liability for and hold AKM harmless from any and all claims arising from the use of said product in the
absence of such notification.
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