AK6440BH

ASAHI KASEI
[AK6440B]
AK6440B
4096bit Serial CMOS EEPROM
Features








ADVANCED CMOS EEPROM TECHNOLOGY
Wide VCC (1.8V ~ 5.5V) operation
4096 bits: 256×16 organization
ONE CHIP MICROCOMPUTER INTERFACE
- Interface with one chip microcomputer's serial communication port directly
LOW POWER CONSUMPTION
- 0.75mA Max. (Read operation)
- 0.8µA Max. (Standby mode)
HIGH RELIABILITY
- Endurance
: 100K cycles
- Data Retention
: 10 years
SPECIAL FEATURES
- High speed operation ( f MA X =1MHz: VCC=2.5V )
- Automatic write cycle time-out with auto-ERASE
- Automatic address increment (READ)
- Software and Hardware controlled write protection
IDEAL FOR LOW DENSITY DATA STORAGE
- Low cost, space saving, 8-pin package (MSOP, SON)
DO
DATA
REGISTER
DI
INSTRUCTION
REGISTER
INSTRUCTION
DECODE,
CONTROL
AND
CLOCK
GENERATION
16
ADD.
BUFFERS
R/W AMPS
AND
AUTO ERASE
16
DECODER
EEPROM
4096bit
256 ×16
CS
VPP SW
SK
RESET
VREF
VPP
GENERATOR
Block diagram
DAS03E-01
2012/09
- 1 -
ASAHI KASEI
[AK6440B]
General Description
The AK6440B is a 4096bit, serial, read/write, non-volatile memory device fabricated using
an advanced CMOS EEPROM technology.
The AK6440B has 4096bits of memory
organized into 256 registers of 16 bits each. The AK6440B can operate full function under
wide operating voltage range from 1.8V to 5.5V. The charge up circuit is integrated for high
voltage generation that is used for write operation.
The AK6440B can connect to the serial communication port of popular one chip
microcomputer directly (3 line negative clock synchronous interface). At write operation,
AK6440B takes in the write data from data input pin (DI) to a register synchronously with
rising edge of input pulse of serial clock pin (SK). And at read operation, AK6440B takes
out the read data from a register to data output pin (DO) synchronously with falling edge of
SK.
The AK6440B has 4 instructions such as READ, WRITE, WREN (write enable) and WRDS
(write disable). Each instruction is organized by op-code block (8bits), address block (8bits)
and data (8bits×2). When input level of SK pin is high level and input level of chip select
(CS) pin is changed from high level to low level, AK6440B can receive the instructions.
Special features of the AK6440B include : automatic write time-out with auto-ERASE,
Ready/Busy status signal output and ultra-low standby power mode when deselected
(CS=high).
・ Software and Hardware controlled write protection
The AK6440B has 2 (hardware and software) write protection functions.
After power on or after execution of WRDS (write disable) instruction, execution of WRITE
instruction will be disabled.
This write protection condition continues until WREN
instruction is executed or VCC is removed from the part.
Execution of READ instruction is independent of both WREN and WRDS instructions.
Reset pin should be low level when WRITE instruction is executed. When the Reset pin is
high level, the WRITE instruction is not executed.
・ Ready/Busy status signal
The DO pin indicates the Busy status. When input level of SK pin is low level and input
level of CS pin is changed from high level to low level, the AK6440B is in the status output
mode and the DO pin indicates the Ready/Busy status. The Ready/Busy status outputs on
DO pin until CS pin is changed from low level to high level, or first bit ("1") of op-code of
next instruction is given to the part. Except when the device is in the status output mode or
outputs data, the DO pin is in the high impedance state.
 Type of Products
Model
AK6440BH
AK6440BL
Memory Size
4Kbits
Temp.Range
-40C ~ +85C
-40C ~ +85C
DAS03E-01
VCC
1.8V ~ 5.5V
1.8V ~ 5.5V
Package
8pin Plastic MSOP
8 pin Plastic SON
2012/09
- 2 -
ASAHI KASEI
[AK6440B]
Pin Arrangement
AK6440BH
CS
SK
DI
DO
1
2
3
4
8
7
6
5
AK6440BL
VCC
NC
RESET
GND
CS
SK
DI
DO
8pin MSOP
Pin Name
CS
SK
DI
DO
RESET
VCC
GND
NC
1
2
3
4
8
7
6
5
VCC
NC
RESET
GND
8pin SON
Function
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
RESET Input
Power Supply
Ground
Not Connected
*1
*1: Please Open NC pin.
DAS03E-01
2012/09
- 3 -
ASAHI KASEI
[AK6440B]
Pin Description
CS (Chip Select)
When SK is high level and CS is changed from high level to low level, AK6440B can receive
the instructions. CS should be kept low level while receiving op-code, address and data
and while outputting data.
If CS is changed to high level during the above period, AK6440B stops the instruction
execution.
When SK is low and CS is changed from high level to low level, AK6440B will be in status
output mode. The CS need not be low level during the automatic write time-out period
(BUSY status).
SK (Serial Clock)
The SK clock pin is the synchronous clock input for input/output data. At write operation,
AK6440B takes in the write data from data input pin (DI) synchronously with rising edge of
input pulse of serial clock pin (SK). And at read operation, AK6440B takes out the read
data to data output pin (DO) synchronously with falling edge of SK. The SK clock is not
needed during the automatic write time-out period (BUSY status), the status output period
and when the device isn't selected (CS = high level).
DI (Data Input)
The op-code, address and write data is input to the DI pin.
DO (Data Output)
The DO pin outputs the read data and status signal and will be high impedance except for
this timing.
RESET (Reset)
The AK6440B stops executing the write instruction when the RESET pin is high level. The
RESET pin should be low level while the write instruction input period and the automatic
write time-out period. If the RESET pin is high level while the automatic write time-out
period, the AK6440B stops execution of internal programming and the device returns to
ready status. In this case the word data of the specified address will be incomplete.
When inputting the new instruction after RESET, the CS pin should be set to high level.
The read, write enable and write disable instructions are not affected by RESET pin status.
VCC (Power Supply)
GND (Ground)
DAS03E-01
2012/09
- 4 -
ASAHI KASEI
[AK6440B]
Functional Description
The AK6440B has 4 instructions such as READ, WRITE, WREN (write enable) and WRDS
(write disable). Each instruction is organized by op-code block (8bits), address block (8bits)
and data (8bits×2). When input level of SK pin is high level and input level of chip select
(CS) pin is changed from high level to low level, AK6440B can receive the instructions.
When the instructions are executed consecutively, the CS pin should be brought to high
level for a minimum of 250ns(tCS) between consecutive instruction cycle.
 Instruction Set
Instruction
WRITE
READ
WREN
WRDS
(WRAL)
Op-Code
10100100
10101000
10100011
10100000
10101111
Data
A0 D15-D0(IN)
A0 D15-D0(OUT)
X
X
X D15-D0(IN)
X: don’t care
(Note) The WRAL instruction is used for factory function test only. User can't use this
instruction.
A7
A7
X
X
X
A6
A6
X
X
X
Address
A5 A4 A3 A2
A5 A4 A3 A2
X X X X
X X X X
X X X X
A1
A1
X
X
X
Write
The write instruction is followed by 16 bits of data to be written into the specified address.
After the 32nd rising edge of SK to read D0 in, the AK6440B will be put into the automatic
write time-out period. During the automatic write time-out period (Busy status) and while
entering write instruction, the RESET pin should be low level. If the RESET pin is set to
high level during the automatic write time-out period, the AK6440B stops execution of
internal programming and the device returns to ready status. In this case the word data of
the specified address will be incomplete. When inputting the new instruction after RESET,
the CS pin should be set to high level. When the RESET pin is kept at high level, the write is
not executed. This becomes write protection function.
The CS pin need not be high level during automatic write time-out period (BUSY status).
RESET
CS
SK
DI
DO
1
2
1
3
0
4
1
5
0
6
0
7
1
8
0
9
0
A7
10
15
A6
A1
16
A0
17
18
D15 D14
30
D2
31
D1
32
D0
Hi-Z
tE/W
WRITE
DAS03E-01
2012/09
- 5 -
ASAHI KASEI
[AK6440B]
Read
The read instruction is the only instruction which outputs serial data on the DO pin. When
the 17th falling edge of SK is received, the DO pin will come out of high impedance state
and shift out the data from D15 first in descending order which is located at the address
specified in the instruction.
The data in the next address can be read sequentially by continuing to provide clock. The
address automatically cycles to the next higher address after the 16bit data shifted out.
When the highest address is reached ($FF), the address counter rolls over to address $00
allowing the read cycle to be continued indefinitely.
CS
SK
1
DI
2
1
3
0
4
1
5
0
6
1
7
0
8
0
9
0
10
A7
15
A6
A1
16
18
32
33
34
48
A0
Hi-Z
DO
17
D15 D14
D0
address [A7 ~ A0]
D15 D14
D0
address[A7 ~ A0]+1
READ
WREN / WRDS ( Write Enable and Write Disable )
When VCC is applied to the part, it powers up in the programming disable (WRDS) state.
Programming must be preceded by a programming enable (WREN) instruction.
Programming remains enabled until a programming disable (WRDS) instruction is executed
or VCC is removed from the part. The programming disable instruction is provided to
protect against accidental data disturb. Execution of a read instruction is not affected by
both WREN and WRDS instructions.
CS
SK
DI
DO
1
2
1
3
0
4
1
5
0
6
0
7
8
9
0
10
X
WREN=11
WRDS=00
11
X
X
12
X
13
X
14
X
15
X
16
17
18
X
Hi-Z
※ SK pulses exceeding 17 are ignored.
WREN / WRDS
DAS03E-01
2012/09
- 6 -
ASAHI KASEI
[AK6440B]
Absolute Maximum Ratings
Parameter
Power Supply
All Input Voltages
with Respect to Ground
Ambient Storage Temperature
Symbol
VCC
VIO
Min
-0.6
-0.6
Max
+7.0
VCC+0.6
Unit
V
V
Tst
-65
+150
°C
Stress above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of the specification is not implied.
Exposure to absolute maximum conditions for extended periods may affect
device reliability.
Recommended Operating Condition
Parameter
Power Supply
Ambient Operating Temperature
Symbol
VCC
Ta
DAS03E-01
Min
1.8
-40
Max
5.5
+85
Unit
V
°C
2012/09
- 7 -
ASAHI KASEI
[AK6440B]
Electrical Characteristics
(1) D.C. ELECTRICAL CHARACTERISTICS
(1.8VVCC5.5V, -40°CTa85°C, unless otherwise specified)
Parameter
Symbol
Condition
Min.
Max.
ICC1 VCC=5.5V,tSKP=500ns *1
4.0
Current Dissipation
(WRITE) ICC2 VCC=2.5V,tSKP=500ns *1
2.5
ICC3 VCC=1.8V,tSKP=1.5s *1
2.0
ICC4 VCC=5.5V,tSKP=500ns *1
0.75
Current Dissipation
(READ, WREN,
ICC5 VCC=2.5V,tSKP=500ns *1
0.3
WRDS)
ICC6 VCC=1.8V,tSKP=1.5s *1
0.15
Current Dissipation
ICCS VCC=5.5V
*2
0.8
(Standby)
Input High Voltage1
VIH1
0.8×VCC VCC+0.5
1.8VVCC5.5V
CS, SK, RESET pin
Input High Voltage2
VIH2
2.5VVCC5.5V
0.7×VCC VCC+0.5
DI pin
VIH3
1.8VVCC2.5V
0.8×VCC VCC+0.5
Input Low Voltage1
VIL1
0
0.2×VCC
1.8VVCC5.5V
CS, SK, RESET pin
Input Low Voltage2
VIL2
0
2.5VVCC5.5V
0.3×VCC
DI pin
VIL3
0
1.8VVCC2.5V
0.2×VCC
Output High Voltage VOH1 2.5VVCC5.5V
VCC-0.3
IOH=-50A
VOH2 1.8VVCC2.5V
VCC-0.3
IOH=-50A
Output Low Voltage
VOL1 2.5VVCC5.5V
0.4
IOL=1.0mA
VOL2 1.8VVCC2.5V
0.4
IOL=0.1mA
Input Leakage
ILI
VCC=5.5V,VIN=5.5V
1.0
Output Leakage
ILO
VCC=5.5V,VOUT=5.5V
CS=VCC
1.0
Unit
mA
mA
mA
mA
mA
mA
A
V
V
V
V
V
V
V
V
V
V
A
A
*1:VIN=VIH/VIL, DO=Open
*2:CS=VCC, SK/DI/RESET=VCC/GND, DO=Open
DAS03E-01
2012/09
- 8 -
ASAHI KASEI
[AK6440B]
(2) A.C. ELECTRICAL CHARACTERISTICS
(1.8VVCC5.5V, -40°CTa85°C, unless otherwise specified)
Parameter
SK Cycle Time
SK Pulse Width
SK High Pulse Width
*3
CS Setup Time
CS Hold Time
SK Setup Time
RESET Setup Time
Data Setup Time
Data Hold Time
DO pin
Output delay
Selftimed Programaing
Time
Min CS High Time
DO High-Z Time
Symbol
tSKP1
tSKP2
tSKW1
tSKW2
tSKH1
tSKH2
tSKH3
Condition
2.5VVCC5.5V
1.8VVCC2.5V
2.5VVCC5.5V
1.8VVCC2.5V
4.5VVCC5.5V
2.5VVCC4.5V
1.8VVCC2.5V
Min.
500
1.5
250
750
250
500
750
Max.
Unit
ns
s
ns
ns
tCSS
100
ns
tCSH
100
ns
100
ns
0
ns
100
200
100
200
150
300
500
ns
ns
ns
ns
ns
ns
ns
10
ms
500
ns
ns
tSKSH
/ tSKSL
tRESS
tDIS1
tDIS2
tDIH1
tDIH2
tPD1
tPD2
tPD3
4.5VVCC5.5V
1.8VVCC4.5V
4.5VVCC5.5V
1.8VVCC4.5V
4.5VVCC5.5V,
2.5VVCC4.5V,
1.8VVCC2.5V,
*4
*4
*4
tE/W
tCS
tOZ
250
*3: tSKH is the high pulse width of 16th SK pulse in READ operation. When the
data in the next address are read sequentially by continuing to provide clock,
tSKH are applied to the high pulse width of 32nd and 48th (multiple of 16) SK
pulse in READ operation.
*4: CL=100pF
DAS03E-01
2012/09
- 9 -
ASAHI KASEI
[AK6440B]
Synchronous Data Timing
tRESS
RESET
tCS
tCSS
CS
tSKP
tSKSH
tSKW
SK
1
tSKW
2
3
tDIS
DI
1
tDIH
0
1
Hi-Z
DO
Instruction Input
CS
"H"
tSKP
"L"
tSKW
SK
tSKW
15
16
tDIS
DI
tSKH
17
18
tDIH
A1
A0
tPD
DO
Hi-Z
tPD
D15
D14
Data Output (READ)
DAS03E-01
2012/09
- 10 -
ASAHI KASEI
[AK6440B]
CS
SK
31
32
DI
tOZ
DO
D1
D0
Data Output (READ)
RESET
CS
tCSH
SK
DI
DO
30
31
D2
32
D1
D0
Hi-Z
Data Input (WRITE)
DAS03E-01
2012/09
- 11 -
ASAHI KASEI
[AK6440B]
tCS
CS
tSKSL
SK
DI
32
D0
tPD
DO
tOZ
BUSY
READY
tE/W
Ready / BUSY Signal Output (DO pin)
DAS03E-01
2012/09
- 12 -
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office
of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current status of the
products.
• Descriptions of external circuits, application circuits, software and other related information contained
in this document are provided only to illustrate the operation and application examples of the
semiconductor products. You are fully responsible for the incorporation of these external circuits,
application circuits, software and other related information in the design of your equipments. AKM
assumes no responsibility for any losses incurred by you or third parties arising from the use of these
information herein. AKM assumes no liability for infringement of any patent, intellectual property, or
other rights in the application or use of such information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license
or other official approval under the law and regulations of the country of export pertaining to customs
and tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components Note1) in any safety,
life support, or other hazard related device or system Note2) , and AKM assumes no responsibility for
such use, except for the use approved with the express written consent by Representative Director of
AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it,
and which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to
function or perform may reasonably be expected to result in loss of life or in significant injury or damage to
person or property.
• It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or
otherwise places the product with a third party, to notify such third party in advance of the above
content and conditions, and the buyer or distributor agrees to assume any and all responsibility and
liability for and hold AKM harmless from any and all claims arising from the use of said product in the
absence of such notification.
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