AK8857VQ

[AK8857VQ]
AK8857VQ
Dual Channel Digital Video Decoder
Overview
The AK8857VQ is a single-chip digital video decoder for composite and s-video video signals. In case
of composite video signal, it can decode two inputs at the same time. Its output data is in YCbCr
format, compliant with ITU-R BT.601. Its output interface is ITU-R BT.656 compliant. A simple IP
conversion function is built internally and the output pixel size also can easily be changed using this
function. The operating temperature range is −40°C to 85°C. The package is 64-terminal LQFP.
Features
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Decodes two inputs of composite video signals NTSC (J, M, 4.43), PAL (B, D, G, H, I, M, N, Nc, 60),
SECAM at the same time.
Decodes S-video video signals NTSC (J, M, 4.43), PAL (B, D, G, H, I, M, N, Nc, 60), SECAM.
Four input channels, with internal video switch.
11-bit 54Mhz ADC 1 channel.
Digital PGA.
Adaptive automatic gain control (AGC).
Auto Color Control (ACC)
Simple IP conversion function (Line repeating process).
Image adjustment (contrast, saturation, brightness, hue, sharpness).
Automatic input signal detection.
Adaptive 2-D Y/C separation.
ITU-R BT.656 and ITU-R BT.601 format output (with 4:2:2_8 bit parallel_EAV/SAV).
Supported output pixel size : 720x487, 720x576, WVGA, VGA, WQVGA, QVGA
SYNC signal timing for external output : HSYNC/HACT, VSYNC/VACT, FIELD, DVALID
Closed-caption signal decoding (output via register).
VBID(CGMS-A) signal decoding (CRCC decode) (output via register).
WSS signal decoding (output via register).
Power down function.
I2C control.
1.70~2.00 V core power supply.
1.70~3.60 V interface power supply.
Operating temperature range: −40°C to 85°C.
64-pin LQFP package.
*Because the data is sampling to a fixed clock, it may not fullfilled the ITU-R BT.656 standard interface.
MS1189-E-01
2010/12
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[AK8857VQ]
1.Functional Block Diagram
TEST0 TEST1
XTO
SELA SDA SCL PDN RSTN
Clock Module
PLL
Microprocessor
Interface
XTI
TEST
LOGIC
OE_A OE_B
DATA_A[7:0]
HD_ACT_A
VD_ACT_A
DVALID_A
AIN1
CLAMP
AIN2
MUX
AIN3
MUX
CLAMP
Digital
PGA1
AAF
11-bit
ADC
MUX
Digital
PGA2
Decimation
Filter
Sync
Separation
Decimation
Filter
Sync
Separation
Composite Decode x 2
or
Y/C Docode x 1
Scaling
&
I/P
Buffer
AAF
FIELD_A
DTCLK
DATA_B[7:0]
HD_ACT_B
AIN4
VD_ACT_B
DVALID_B
FIELD_B
NSIG_A
VREF
NSIG_B
VRP VCOM VRN
IREF
AVDD
AVSS
DVDD
DVSS
PVDD1
PVDD2
In this specification, the output pins above the DTCLK pin on the right side of this block diagram is called [A BLOCK] and the output pins below the DTCLK pin
is called [B BLOCK].
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2.Pin assignment – 64 pins LQFP
DVSS
PVDD1
DATA_B6
DATA_B5
DATA_B4
DATA_B3
DATA_B2
DATA_B1
DATA_B0
PPDD1
DVSS
DVDD
TEST0
TEST1
NSIG_B
NSIG_A
48 47 46 45 4443424140 39 383736353433
OE_B
OE_A
PVDD2
RSTN
PDN
SDA
SCL
SELA
AVDD
XTO
AVSS
XTI
VRN
IREF
VRP
VCOM
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
DATA_B7
VD_ACT_B
HD_ACT_B
DVALID_B
FIELD_B
DTCLK
PVDD1
FIELD_A
DVALID_A
HD_ACT_A
VD_ACT_A
DATA_A7
DATA_A6
PVDD1
DVSS
DVDD
1 2 3 4 5 6 7 8 9 10 111213141516
DATA_A5
DATA_A4
DATA_A3
DATA_A2
DATA_A1
DATA_A0
PVDD1
DVSS
AVSS
AIN4
AVDD
AIN3
AVSS
AIN2
AVDD
AIN1
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3.Pin Functions
Pin
No.
Symbol
P/S1
I/O2
1
AIN1
A
I
2
AVDD
A
P
3
AIN2
A
I
4
AVSS
A
G
5
AIN3
A
I
6
AVDD
A
P
7
AIN4
A
I
8
9
10
AVSS
DVSS
PVDD1
A
D
P1
G
G
P
11
DATA_A0
P1
O
(I)
12
DATA_A1
P1
O
(I)
13
DATA_A2
P1
O
(I)
14
DATA_A3
P1
O
(I)
15
DATA_A4
P1
O
(I)
16
DATA_A5
P1
O
(I)
17
18
19
DVDD
DVSS
PVDD1
D
D
P1
P
G
P
20
DATA_A6
P1
O
(I)
Functional Description
Analog video signal input pin. Connect via 0.033 µF capacitor and
voltage-splitting resistors as shown in page 121. If it is not used,
connect to NC.
Analog ground pin.
Analog video signal input pin. Connect via 0.033 µF capacitor and
voltage-splitting resistors as shown in page 121. If it is not used,
connect to NC.
Analog ground pin.
Analog video signal input pin. Connect via 0.033 µF capacitor and
voltage-splitting resistors as shown in page 121. If it is not used,
connect to NC.
Analog ground pin.
Analog video signal input pin. Connect via 0.033 µF capacitor and
voltage-splitting resistors as shown in page 121. If it is not used,
connect to NC.
Analog ground pin.
Digital ground pin.
I/O power supply pin.
A block data output pin. Used as I/O pin in Test Mode.
See Table below for relation of output to OE_A, PDN and RSTN pin
status.
A block data output pin. Used as I/O pin in Test Mode.
See Table below for relation of output to OE_A, PDN and RSTN pin
status.
A block data output pin. Used as I/O pin in Test Mode.
See Table below for relation of output to OE_A, PDN and RSTN pin
status.
A block data output pin. Used as I/O pin in Test Mode.
See Table below for relation of output to OE_A, PDN and RSTN pin
status.
A block data output pin. Used as I/O pin in Test Mode.
See Table below for relation of output to OE_A, PDN and RSTN pin
status.
A block data output pin. Used as I/O pin in Test Mode.
See Table below for relation of output to OE_A, PDN and RSTN pin
status.
Digital power supply pin.
Digital ground pin.
I/O power supply pin.
A block data output pin. Used as I/O pin in Test Mode.
See Table below for relation of output to OE_A, PDN and RSTN pin
status.
MS1189-E-01
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[AK8857VQ]
Pin
No.
Symbol
P/S1
I/O2
21
DATA_A7
P1
O
(I)
22
VD_ACT_A
P1
O
(I)
23
HD_ACT_A
P1
O
(I)
24
DVALID_A
P1
O
(I)
25
FIELD_A
P1
O
(I)
26
PVDD1
P1
P
27
DTCLK
P1
O
28
FIELD_B
P1
O
(I)
29
DVALID_B
P1
O
(I)
30
HD_ACT_B
P1
O
(I)
31
VD_ACT_B
P1
O
(I)
Functional Description
A block data output pin. Used as I/O pin in Test Mode.
See Table below for relation of output to OE_A, PDN and RSTN pin
status.
A block VD(Vertical Drive) / VACT(Vertical Active) signal output pin.
VD signal output / VACT signal output can be selected by register
setting. Used as I/O pin in Test Mode.
See Table below for relation of output to OE_A, PDN and RSTN pin
status.
A block HD(Horizontal Drive) / HACT(Horizontal Active) signal
output pin. HD signal output / HACT signal output can be selected
by register setting. Used as I/O pin in Test Mode.
See Table below for relation of output to OE_A, PDN and RSTN pin
status.
A block DVALID signal output pin.
Used as I/O pin in Test Mode. See Table below for relation of output
to OE_A, PDN and RSTN pin status.
A block FIELD signal output pin.
Used as I/O pin in Test Mode. See Table below for relation of output
to OE_A, PDN and RSTN pin status.
I/O power supply pin.
Data clock output pin.
Approx. 27 MHz clock output. See Table below for relation of output
to OE_A, OE_B, PDN and RSTN pin status.
B block FIELD signal output pin.
Used as I/O pin in Test Mode. See Table below for relation of output
to OE_B, PDN and RSTN pin status.
B block DVALID signal output pin.
Used as I/O pin in Test Mode. See Table below for relation of output
to OE_B, PDN and RSTN pin status.
B block HD(Horizontal Drive) / HACT(Horizontal Active) signal
output pin.
HD signal output / HACT signal output can be selected by register
setting. Used as I/O pin in Test Mode.
See Table below for relation of output to OE_B, PDN and RSTN pin
status.
B block VD(Vertical Drive) / VACT(Vertical Active) signal output pin.
VD signal output / VACT signal output can be selected by register
setting. Used as I/O pin in Test Mode.
See Table below for relation of output to OE_B, PDN and RSTN pin
status.
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[AK8857VQ]
Pin
No.
Symbol
P/S1
I/O2
32
DATA_B7
P1
O
(I)
33
34
DVSS
PVDD1
D
P1
G
P
35
DATA_B6
P1
O
(I)
36
DATA_B5
P1
O
(I)
37
DATA_B4
P1
O
(I)
38
DATA_B3
P1
O
(I)
39
DATA_B2
P1
O
(I)
40
DATA_B1
P1
O
(I)
41
DATA_B0
P1
O
(I)
42
43
44
45
46
PVDD1
DVSS
DVDD
TEST0
TEST1
P1
D
D
P2
P2
P
G
P
I
I
47
NSIG_B
P2
O
(I)
48
NSIG_A
P2
O
(I)
Functional Description
B block data output pin. Used as I/O pin in Test Mode.
See Table below for relation of output to OE_B, PDN and RSTN pin
status.
Digital ground pin.
I/O power supply pin.
B block data output pin. Used as I/O pin in Test Mode.
See Table below for relation of output to OE_B, PDN and RSTN pin
status.
B block data output pin. Used as I/O pin in Test Mode.
See Table below for relation of output to OE_B, PDN and RSTN pin
status.
B block data output pin. Used as I/O pin in Test Mode.
See Table below for relation of output to OE_B, PDN and RSTN pin
status.
B block data output pin. Used as I/O pin in Test Mode.
See Table below for relation of output to OE_B, PDN and RSTN pin
status.
B block data output pin. Used as I/O pin in Test Mode.
See Table below for relation of output to OE_B, PDN and RSTN pin
status.
B block data output pin. Used as I/O pin in Test Mode.
See Table below for relation of output to OE_B, PDN and RSTN pin
status.
B block data output pin. Used as I/O pin in Test Mode.
See Table below for relation of output to OE_B, PDN and RSTN pin
status.
I/O power supply pin.
Digital ground pin.
Digital power supply pin.
Pin for test mode setting. Connect to DVSS.
Pin for test mode setting. Connect to DVSS.
Shows status of synchronization with input signal of B block.
Low: Signal present (synchronized).
High: Signal not present or not synchronized.
See Table below for relation of output to OE_B, PDN, RSTN pin
status.
Shows status of synchronization with input signal of A block.
Low: Signal present (synchronized).
High: Signal not present or not synchronized.
See Table below for relation of output to OE_A, PDN, RSTN pin
status.
MS1189-E-01
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[AK8857VQ]
Pin
No.
Symbol
P/S1
I/O2
49
OE_B
P2
I
50
OE_A
P2
I
51
PVDD2
P2
P
52
RSTN
P2
I
53
PDN
P2
I
54
SDA
P2
I/O
55
SCL
P2
I
56
SELA
P2
I
(O)
57
AVDD
A
P
58
XTO
A
O
59
AVSS
A
G
60
XTI
A
I
61
VRN
A
O
62
IREF
A
O
Functional Description
B block Output Enable pin.
L: Digital output pin in Hi-z output mode.
H: Data output mode.
Hi-z input to OE_B pin is prohibited.
A block Output Enable pin.
L: Digital output pin in Hi-z output mode.
H: Data output mode.
Hi-z input to OE_A pin is prohibited.
Microprocessor I/F power supply pin.
Reset signal input pin.
Hi-z input is prohibited.
L: Reset.
H: Normal operation.
Power-down control pin.
Hi-z input is prohibited.
L: Power-down.
H: Normal operation.
I2C data pin. Connect to PVDD2 via a pull-up register.
Hi-z input possible when RSTN=L.
Will not accept SDA input during reset sequence.
I2C clock input pin. Use PVDD2 or lower for input.
Hi-z input possible when PDN=L.
Will not accept SCL input during reset sequence.
I2C bus address selector pin.
PVDD2 connection: Slave address [0x8A]
DVSS connection: Slave address [0x88]
Analog power supply pin.
Crystal connection pin.
Connect to digital ground via 22 pF capacitor as shown in Sec. 10.
Use 24.576 MHz crystal.
When PDN=L, output level is DVSS.
If crystal is not used, connect to NC or DVSS.
Analog ground pin.
Crystal connection pin.
Connect to digital ground via 22 pF capacitor as shown in Sec. 10.
Use 24.576 MHz crystal resonator.
For input from 24.576 MHz crystal oscillator, use this pin.
Internal reference negative voltage pin for AD converter.
Connect to AVSS via ≥0.1 µF ceramic capacitor.
Reference current setting pin.
Connect to ground via 6.8 kΩ (≤1% accuracy) resistor.
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[AK8857VQ]
Pin
No.
Symbol
P/S1
I/O2
63
VRP
A
O
64
VCOM
A
O
1
Power supply
2
Input/Output
Functional Description
Internal reference positive voltage pin for AD converter.
Connect to AVSS via ≥0.1 µF ceramic capacitor.
Common internal voltage for AD convertor.
Connect to AVSS via ≥0.1 µF ceramic capacitor.
A: AVDD, D: DVDD, P1: PVDD1, P2: PVDD2
O: output pin, I: intput pin, I/O:input/output pin, P: power supply pin,G:ground connect-
ion pin.
Output pin status as determined by OE_A, OE_B, PDN, and RSTN pin status.
OE_A, OE_B (*2) PDN
RSTN
Output1 (*2)
Output2 (*2)
L
x
x
Hi-Z output
L output
H
L
x
L output
L output
L
L output
L output
H
H
H
Default Data Out (*3)
Default Data Out (*3)
2
Output1:
(A Block) DATA_A[7:0], HD_ACT_A, VD_ACT_A, DVALID_A, FIELD_A
(B Block) DATA_B[7:0], HD_ACT_B, VD_ACT_B, DVALID_B, FIELD_B
DTCLK.
If OE_A and OE_B both are in Low condition, the DTCLK pin output is Hi-Z.
Output2: NSIG_A, NSIG_B
If (OE_A=H or OE_B=H) and PDN=H just after power is turned on, output pin status will be
indefinite until internal state is determined by reset sequence.
3
In the absence of AIN signal input, output will be black data ((Y=0x10, Cb/Cr=0x80).
(Blueback output can be obtained by register setting.)
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4.Electrical specifications
(1) Absolute maximum ratings
Parameter
Min
Max
Units
Notes
Supply voltage
AVDD, DVDD,
−0.3
2.2
V
PVDD1, PCDD2
−0.3
4.2
V
Analog input pin voltage A
−0.3
AVDD + 0.3 ( ≤2.2)
V
(VinA)
Digital output pin voltage P1
−0.3
PVDD1 + 0.3 ( ≤4.2)
V
(*1)
(VioP1)
Digital output pin voltage P2
−0.3
PVDD2 + 0.3 ( ≤4.2)
V
(*2)
(VioP2)
Input pin current (Iin)
−10
10
mA
(except for power supply pin)
Storage temperature
−40
125
ºC
*The above supply voltages are referenced to ground pins (DVSS=AVSS) at 0 V (the Reference
Voltage).
All power supply grounds (AVSS, DVSS) should be at the same electric potential.
If digital output pins are connected to data bus, the data bus operating voltage should be in the same
range as shown above for the digital output pin.
(*1) DATA_A[7:0], HD_ACT_A, VD_ACT_A, DVALID_A, FIELD_A,
DATA_B[7:0], HD_ACT_B, VD_ACT_B, DVALID_B, FIELD_B, DTCLK.
(*2) OE_A, OE_B, SELA, PDN, RSTN, SDA, SCL, NSIG_A, NSIG_B, TEST0, TEST1.
(2) Recommended operating conditions
Parameter
Min
Typ
Max
Units
Condition
Analog supply voltage (AVDD)
1.70
1.80
2.00
V
AVDD=DVDD
Digital supply voltage (DVDD)
I/O supply voltage (PVDD1)
PVDD1≥DVDD
1.70
1.80
3.60
V
MPU I/F supply voltage (PVDD2)
PVDD2≥DVDD
Operating temp. (Ta)
−40
85
ºC
The above supply voltages are referenced to ground pins (DVSS=AVSS) at 0 V (the Reference
Voltage).
All power supply grounds (AVSS, DVSS) should be at the same electric potential.
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(3) DC characteristics
Where no specific condition is indicated in the following table, the supply voltage range
is the same as that shown for the recommended operating conditions in 4-2 above.
Parameter
Symbol
Digital P2 input high
voltage
VPIH
Digital P2 input low
voltage
VPIL
Digital input leak current
Digital P1 output high
voltage
Digital P1 output low
voltage
Digital P2 output high
voltage
Digital P2 output low
voltage
Min
Typ
Max
Units
Condition
0.8PVDD2
V
Case *1
0.7PVDD2
V
Case *2
0.2PVDD2
V
Case *1
0.3PVDD2
V
Case *2
±10
uA
IL
VP1OH 0.8PVDD1
VP1OL
0.2PVDD1
VP2OH 0.8PVDD2
VP2OL
0.2PVDD2
V
IOH = -600uA
V
IOL = 1mA
V
IOH = -600uA
V
IOL = 1mA
IOLC = 3mA
I C (SDA)L output
VOLC
0.4
V
PVDD2≥2.0V
0.2 PVDD2
PVDD2<2.0V
*1: < DVDD = 1.70V~2.00V, DVDD≤PVDD1<2.70V, DVDD≤PVDD2<2.70V, Ta: -40~85˚C >
*2: < DVDD = 1.70V~2.00V, 2.70V≤PVDD1≤3.60V, 2.70V≤PVDD2≤3.60V, Ta: -40~85˚C >
2
Definition of above input/output terms
Digital P2 input : Collective term for SDA, SCL, SELA, OE_A, OE_B, PDN, RSTN, TEST0, TEST1
pin inputs.
Digital P1 output : Collective term for DATA_A[7:0], HD_ACT_A, VD_ACT_A, DVALID_A, FIELD_A,
DATA_B[7:0], HD_ACT_B, VD_ACT_B, DVALID_B, FIELD_B, DTCLK pin outputs.
Digital P2 output : Collective term for NSIG_A, NSIG_B pin outputs.
SDA pin output: Not termed digital pin output unless otherwise specifically stated.
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[AK8857VQ]
(4) Analog characteristics (AVDD=1.8V, Temp.25˚C)
Selector clamp
Parameter
Symbol Min Typ Max Units
Maximum input range
VIMX
AD converter
Parameter
Resolution
Operating clock
frequency
0
0.50
0.60
Symbol
RES
Min
Typ
11
Condition
ADC output data is fullcode when
input range is 0.6Vpp input.
VPP
Max
Units
bit
FS
27
Integral nonlinearity
INL
±2.0
Differential nonlinearity
DNL
±0.5
S/N
S/(N+D)
ADC internal common voltage
ADC internal
positive VREF
ADC internal
negative VREF
*Fin = AIN input signal frequency
SN
SND
VCOM
54
52
0.96
dB
dB
V
VRP
1.28
V
VRN
0.64
V
AAF (Anti-Aliasing Filter)
Parameter
Pass band ripple
Stop band blocking
Symbol
Gp
Gs
MHz
+4.0
-4.0
+1.5
-1.0
Min
-1
20
LSB
LSB
Typ
35
Condition
ADC:54MHz
FS=27MHz,
Input range = 0.5Vpp
FS=27MHz,
Input range = 0.5Vpp
Fin=1MHz*, FS=27MHz,
Input range = 0.5Vpp
Max
+1
Units
dB
dB
Condition
6MHz
27MHz
(5) Current consumption (at DVDD = AVDD = PVDD1 = PVDD2 = 1.8V, Ta = −40 ~ 85˚C) (*1)
Parameter
Symbol Min
Typ Max Units
Condition
(Active mode)
Total
IDD1
IDD2
IDD3
86
63
75
130
Analog block
AIDD
39
mA
Digital block
DIDD
34
mA
I/O block
PIDD
13
mA
112
mA
mA
mA
CVBS : 2ch
CVBS : 1ch (*2)
S-Video
(*2)
CVBS : 2ch
With Xtal crystal connected.
CVBS : 2ch
Load condition: CL=12pF, 24pF*
(*DTCLK pin)
(Power down mode)
Total
SIDD
≤1
20
uA
PDN=L(DVSS) (*3)
Analog block
ASIDD
≤1
uA
Digital block
DSIDD
≤1
uA
I/O block
PSIDD
≤1
uA
(*1) With NTSC-J 100% color bar input.
(*2) Reference Value. During A Block is set to output, B Block is set to [No Decode].
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(*3)To perform power-down, OE_A, OE_B and RSTN pins must always be brought to the voltage
polarity to be used or to ground level.
(6) Crystal circuit block
Parameter
Frequency
Frequency tolerance
Load capacitance
Effective equivalent resistance
Crystal parallel capacitance
XTI terminal external
connection load capacitance
XTO terminal external
connection load capacitance
Symbol
f0
Δf / f
CL
Re
CO
Min
Typ
Max
(Ta : -40~85˚C)
Condition
0.9
Units
MHz
ppm
pF
Ω
pF
CXI
22
pF
CL=15pF
CXO
22
pF
CL=15pF
27
±100
15
100
(*1)
(*1) Effective equivalent resistance generally may be taken as Re = R1 x (1+CO/CL)2,
where R1
is the crystal series equivalent resistance.
Example connection
AK8857VQ internal circuit
Rf
XTI pin
XTO pin
External circuit
Rd (* 2)
CXI = 22pF
CXO = 22pF
(*2) Determine need for and appropriate value of limiting resistance (Rd) in accordance with
the crystal specifications.
AK8857VQ is hereafter the “AK8857”.
MS1189-E-01
2010/12
-12-
[AK8857VQ]
5. AC Timing
(DVDD=1.70V~2.00V, PVDD1=DVDD~3.60V, PVDD2=DVDD~3.60V, -40~85˚C)
Load condition: CL=12pF, 24pF(DTCLK pin)
(1) Clock Input
Set AK8857 clock input as follows.
fCLK
tCLKL
tCLKH
VIH
1/2 level
VIL
Parameter
Symbol
fCLK
tCLKH
tCLKL
Input CLK
CLK pulse width H
CLK pulse width L
Frequency tolerance
Min
Typ
Max
27
15
15
±100
Units
MHz
nsec
nsec
ppm
(2) Clock Output (DTCLK output)
Parameter
Symbol
DTCLK
fDTCLK
Min
Typ
54
27
Max
Units
MHz
Output Data Format
601,VGA, WVGA progressive output.
601,VGA, WVGA other than progressive output.
fDTCLK
0.5PVDD1
MS1189-E-01
2010/12
-13-
[AK8857VQ]
(3) Output Data Timing
DATA_A[7:0], HD_ACT_A, VD_ACT_A, FIELD_A, DVALID_A, DATA_A[7:0], HD_ACT_A,
VD_ACT_A, FIELD_A, DVALID_A
0.5PVDD1
DTCLK
tDS
tDH
0.5PVDD1
OUTPUT DATA
Parameter
Symbol
Output Data Setup Time
tDS
Output Data Hold Time
tDH
Min
Typ
Max
Units
DTCLK
10
nsec
27MHz
5
nsec
54MHz
10
nsec
27MHz
5
nsec
54MHz
(4) Register reset timing
RSTN
VIL
RESETTIMING
fCLK
Parameter
RSTN pulse width
Symbol
RESETTIMING
Min
100
(3.7)
Typ
Max
Units
CLK
(usec)
Notes
Based on clock leading
edge
Note. Clock input is necessary for reset operation.
RSTN pin must be pulled low following clock application.
MS1189-E-01
2010/12
-14-
[AK8857VQ]
(5) Power-down sequence and Reset sequence after power-down
Reset must be applied for at least 2048 clock cycles (or 83.33 µs) before setting PDN (PDN=Low).
Reset must be applied for at least 5 ms after PDN release (PDN=Hi).
CLKIN
RESh
RESs
RSTN
VIH
VIL
VIH
PDN
GND
Parameter
Symbol
Reset width before setting PDN
RESs
Reset width after PDN release
RESh
Min
2048
(75.85)
5
Typ
Max
Units
CLK
(usec)
msec
To perform power-down, all control signals must always be brought to the voltage polarity to be used or
to ground level.
For any power supply removal, all power supplies must be removed.
Clock input is necessary for resetting.
The power-down sequence for connection of the crystal is as follows.
AVDD/DVDD
PVDD1/PVDD2
PDN
RSTN
XTI
VCOM,VRP,VR
5 mS (max) to stable
crystal oscillator
RESh≧5mS(min)
* Reference value
PDN release
MS1189-E-01
2010/12
-15-
[AK8857VQ]
(6) Power-on reset
At power-on, reset must be applied until the analog reference voltage and current have stabilized.1 (*1)
The order of each power supply to be start up is not required. All the power supply must be on within
100msec during PDN pin status is low.
VDD
PDN
PWUPTIME
VIL
RSTN
VREF
RESPON
Parameter
Symbol
POWERUP TIME
PWUPTIME
RSTN pulse width
RESPON
Min
Typ
Max
100
5
Units
msec
msec
1
Clock input is necessary for resetting.
MS1189-E-01
2010/12
-16-
[AK8857VQ]
(7) I2C bus input timing
(DVDD=1.70V~2.00V, PVDD1=DVDD~3.60V, PVDD2=DVDD~3.60V, -40~85˚C)
(7-1) Timing 1
tBUF tHD : STA
tR
tF
tSU : STO
VIH
SDA
VIL
tF
tR
VIH
SCL
VIL
tLOW
tSU : STA
Parameter
Symbol
Min
Max
Units
Bus Free Time
tBUF
1.3
Usec
Hold Time (Start Condition)
tHD:STA
0.6
Usec
Clock Pulse Low Time
tLOW
1.3
Usec
Input Signal Rise Time
tR
300
Nsec
Input Signal Fall Time
tF
300
Nsec
Setup Time(Start Condition)
tSU:STA
Setup Time(Stop Condition)
tSU:STO
2
0.6
Usec
0.6
Usec
2
Note. The timing relating to the I C bus is as stipulated by the I C bus specification,
and not determined by the device itself. For details, see I2C bus specification.
(7-2) Timing 2
tHD : DAT
VIH
SDA
VIL
tHIGH
VIH
SCL
VIL
TSU : DAT
Parameter
Data Setup Time
Symbol
tSU:DAT
Min
Max
1
100
Data Hold Time
tHD:DAT
0.0
Clock Pulse High Time
tHIGH
0.6
Units
nsec
2
0.9
usec
usec
1
2
If I C is used in standard mode, tSU: DAT ≥ 250 ns is required.
2
This condition must be met if the AK8854 is used with a bus that does not extend tLOW (to use
tLOW at minimum specification).
MS1189-E-01
2010/12
-17-
[AK8857VQ]
6. Functional description
Analog interface
The AK8857 accepts composite video signal (CVBS), S-video input with 4 input pins available for
this purpose.
The decode signal is selected via the register (AINSEL[4:0]).
The AK8857 can decode 2ch of anolog video signal at the same time during composite video signal
input. The digital output data is output to A block and B block output block. It is possible to switch the
digital output data between A block and B block output block. It also possible to select one of digital
output data to be output at A block and B block output at the same time.
Analog Input Select
Definition
A block and B block output video signal selection :
[AINSEL4: AINSEL0]
[00000]: [A]: AIN1 (CVBS), [B]: AIN4(CVBS)
[00001]: [A]: AIN1 (CVBS), [B]: AIN3(CVBS)
[00010]: [A]: AIN1 (CVBS), [B]: AIN2(CVBS)
[00011]: [A]: AIN1 (CVBS), [B]: AIN1(CVBS)
[00100]: [A]: AIN1 (CVBS), [B]: Non-decode
[00101]: [A]: AIN2 (CVBS), [B]: AIN4(CVBS)
[00110]: [A]: AIN2 (CVBS), [B]: AIN3(CVBS)
[00111]: [A]: AIN2 (CVBS), [B]: AIN2(CVBS)
[01000]: [A]: AIN2 (CVBS), [B]: AIN1(CVBS)
[01001]: [A]: AIN2 (CVBS), [B]: Non-decode
[01010]: [A]: AIN3 (CVBS), [B]: AIN4(CVBS)
[01011]: [A]: AIN3 (CVBS), [B]: AIN3(CVBS)
[01100]: [A]: AIN3 (CVBS), [B]: AIN2(CVBS)
[01101]: [A]: AIN3 (CVBS), [B]: AIN1(CVBS)
[01110]: [A]: AIN3 (CVBS), [B]: Non-decode
[01111]: [A]: AIN4 (CVBS), [B]: AIN4(CVBS)
[10000]: [A]: AIN4(CVBS), [B]: AIN3(CVBS)
[10001]: [A]: AIN4 (CVBS), [B]: AIN2(CVBS)
[10010]: [A]: AIN4 (CVBS), [B]: AIN1(CVBS)
[10011]: [A]: AIN4 (CVBS), [B]: Non-decode
[10100]: [A]: Non-decode, [B]: AIN4 (CVBS)
[10101]: [A]: Non-decode, [B]: AIN3(CVBS)
[10110]: [A]: Non-decode, [B]: AIN2(CVBS)
[10111]: [A]: Non-decode, [B]: AIN1(CVBS)
[11000]: [A]: AIN1(Y) / AIN3(C), [B]: Non-decode
[11001]: [A]: AIN1(Y) / AIN3(C), [B]: AIN1(Y) / AIN3(C)
[11010]: [A]: AIN2(Y) / AIN4(C), [B]: Non-decode
[11011]: [A]: AIN2(Y) / AIN4(C), [B]: AIN2(Y) / AIN4(C)
[11100]: [A]: Non-decode, [B]: AIN1(Y) / AIN3(C)
[11101]: [A]: Non-decode, [B]: AIN2(Y) / AIN4(C)
The output block change to power-save mode when [Non-decode] is selected and digital circuit
operational is stoped. This will low down the internal power consumption.
The data output is low during this state.
Available pin : DATA_A[7:0], HD_ACT_A, VD_ACT_A, DVALID_A, FIELD_A, DATA_B[7:0],
HD_ACT_B, VD_ACT_B, DVALID_B, FIELD_B, NSIG_A, NSIG_B pins.
Note: Output control via pins OE_A, OE_B, PDN, and RSTN takes priority, regardless of the above
settings.
MS1189-E-01
2010/12
-18-
[AK8857VQ]
Analog band limiting filter and analog clamp circuit
Analog band limiting filter
The characteristics of the AK8857 internal analog band limiting filter (anti-aliasing), which is in front
of the AD converter input, are as follows:
Filterフィルター特性
Characteristic
±1dB (~6MHz )
10
0
−35dB (27MHz)….Typical value
-10
Gain[dB]
-20
-30
-40
-50
-60
-70
-80
0.1
1
10
100
Frequency[MHz]
Analog clamp circuit
In AK8857, the input video signal is clamping with analog circuit.
The clamping method is show as follows.
[CVBS signal decoding]
AK8857 clamps the input signal to sync tip. (analog sync tip clamp)
The clamp timing pulse, with its origin at the falling edge of the internally synchronized and
separated sync signal, is generated at approximately the central position of the sync signal.
[S-video signal decoding]
(Y signal)
AK8857 clamps the Y signal to sync tip. (analog sync tip clamp)
The clamp timing pulse, with its origin at the falling edge of the internally synchronized and
separated sync signal, is generated at approximately the central position of the sync signal.
(C signal)
AK8857 clamps the C signal to the middle level. (analog middle clamp)
The clamp timing pulse is generated at same timing with Y signal.
Y
analog sync tip clamp
CVBS
C
analog sync tip clamp
analog middle clamp
MS1189-E-01
2010/12
-19-
[AK8857VQ]
Additionary, the AK8857 can change the position, width and current value of clamp pulse by registers.
○CLPWIDTH[1:0]: Set the width of clamp pulse.
CLPWIDTH[1:0]-bit
Clamp width
[00]
296nsec
[01]
593nsec
[10]
1.1usec
[11]
2.2usec
Notes
○CLPSTAT[1:0]: Set the position of clamp pulse.
CLPSTAT[1:0]-bit
Clamp position
Notes
[00]
Sync tip/ middle/ bottom clamp: Centor of The positions of all clamp pulse are
horizontal sync
changed.
[01]
(1/128) H delay.
[10]
(2/128) H advance
[11]
(1/128) H advance
Clamp Timing Pulse
CLPWIDTH[1:0]
CLPSTAT[1:0] = 00
CLPSTAT[1:0] = 01
1/128H delay
CLPSTAT[1:0] = 11
1/128H advance
CLPSTAT[1:0] = 10
2/128H advance
○CLPG[1:0] : Set the current value of fine clamp in analog block.
CLPG[1:0]-bit
Clamp current value
[00]
Min.
[01]
Middle 1 (Default)
[10]
Middle 2
[11]
Max.
Notes
Middle 1 = (Min. x 3)
Middle 2 = (Min. x 5)
Max. = (Min. x 7)
○UDG[1:0]: Set the current value of rough clamp in analog block.
UDG[1:0]-bit
Clamp current value
Notes
[00]
Min. (Default)
Middle 1 = (Min. x 2)
[01]
Middle 1
Middle 2 = (Min. x 3)
[10]
Middle 2
Max. = (Min. x 4)
[11]
Max.
Its digital circuit clamps the digitized input data to the pedestal level (digital pedestal clamp), and will
be described later.
MS1189-E-01
2010/12
-20-
[AK8857VQ]
Output Data Format Setting (Pixel size / progressive output)
The AK8857 can convert the output pixel size from the original input pixel size.
The AK8857 also can convert the interlaced input signal to progressive output signal.
The AK8857 supported output format is shown below
Input signal
Output pixel size
525 Line
720x487 (ITU-R BT.601)
NTSC-M, J,
NTSC-4.43,
PAL-M,
PAL-60
800x480 (WVGA)
640x480 (VGA)
400x240 (WQVGA)
320x240 (QVGA)
400x234(EGA)
480x240(WEGA1)
480x234(WEGA2)
625 Line
Interlace / Progressive
output
Interlace
Progressive
Interlace
Progressive
Interlace
Progressive
Progressive
Progressive
Progressive
Progressive
Progressive
Output Clock
27MHz
54MHz
27MHz
54MHz
27MHz
54MHz
27MHz
27MHz
27MHz
27MHz
27MHz
Notes
(*1)
(*1)
(*1)
(*2)
(*2)
(*2)
(*2)
(*2)
720x576 (ITU-R BT.601)
Interlace
27MHz
Progressive
54MHz
(*1)
PAL-B,D,G,H,I,N,
800x480 (WVGA)
Interlace
27MHz
PAL-Nc
Progressive
54MHz
(*1)
SECAM
640x480 (VGA)
Interlace
27MHz
Progressive
54MHz
(*1)
400x240 (WQVGA)
Progressive
27MHz
(*2)
320x240 (QVGA)
Progressive
27MHz
(*2)
400x234(EGA)
Progressive
27MHz
(*2)
480x240(WEGA1)
Progressive
27MHz
(*2)
480x234(WEGA2)
Progressive
27MHz
(*2)
(*1) Interlcae signal to progressive signal conversion is using line repeating process.
The Frame rates for progressive output signal is selectable between 30frm/sec* and 60frm/sec*.
(*2) Only progressive output is support for this section.
It’s not mentioned here, during the pixel size conversion the data is interpolar before being generated
at the output.
If the input signal quality is poor, there is a case where it cannot satisfy the timing diagram shown
below.
Example: If the input signal line is shortened than the normal, it will effect EAV sync signal and HD
signal timing for the next line and for that reason the output signal will be effected as well.
*frm/sec: Frame number in 1 sec
MS1189-E-01
2010/12
-21-
[AK8857VQ]
The figure below shows the relationship between 1-line data pixel and sync signal timing for each
output pixel size.
*() in the figure below refers to clock pixels of 625-line input.
*Because the data is sampling to a fixed-clock, the cycle period from end of active signal to the next
line of horizontal sync signal is fixed is not guarantee.
○720x487, 720x576(ITU-R BT.601)
Video Signal
HD
DVALID
HACT
128CLK
244CLK
(264CLK)
1440CLK
Active Video section
32CLK
(24CLK)
○640x480(VGA)
Video Signal
HD
DVALID
HACT
128CLK
324CLK
(344CLK)
1280CLK
Active Video section
MS1189-E-01
112CLK
(104CLK)
2010/12
-22-
[AK8857VQ]
○800x480(WVGA)
Video Signal
HD
DVALID
HACT
128CLK
32CLK
(24CLK)
1600CLK
Active Video Section
84CLK
(104CLK)
○320x240(QVGA)
Video Signal
HD
DVALID
HACT
128CLK
644CLK
(664CLK)
640CLK
Active Video Section
432CLK
(424CLK)
○400x240(WQVGA), 400x234(EGA)
Video Signal
HD
DVALID
HACT
128CLK
564CLK
(584CLK)
800CLK
Active Video Section
MS1189-E-01
352CLK
(344CLK)
2010/12
-23-
[AK8857VQ]
○480x240(WEGA1), 480x234(WEGA2), 480x272
Video Signal
HD
DVALID
HACT
128CLK
484CLK
(504CLK)
960CLK
Active Video Section
272CLK
(264CLK)
Relationship between Sync timing of 1 frame to the next frame for each output pixel size is shown
below.
The timing of HD, HACT, DVALID and VACT signal shown in the figure is enlarge.
VACT falling edge timing
VACT rising edge timing
Input
Video Signal
HD
HACT
DVALID
VACT
MS1189-E-01
2010/12
-24-
[AK8857VQ]
Input: 525-line, horizontal : 487-line, Output : Interlace
Input
Video Signal
523
524
525
1
2
3
4
5
6
7
8
9
10
11
12
HD
HACT
DVALID
VD
VACT
FIELD
Input
Video Signal
ODD
EVEN
13
14
15
16
17
18
19
20
21
22
23
24
25
261
262
263
264
265
266
267
268
269
270
271
272
273
284
285
286
287
288
260
HD
HACT
DVALID
VD
VACT
FIELD
Input
Video Signal
274
275
HD
HACT
DVALID
VD
VACT
ODD
FIELD
Input
Video Signal
276
277
278
279
280
EVEN
281
282
283
522
HD
HACT
DVALID
VD
VACT
FIELD
MS1189-E-01
2010/12
-25-
[AK8857VQ]
Input: 525-line, horizontal: 487-line, Output: Progressive (60frm/sec)
Input
Video Signal
523
524
525
1
2
3
4
5
6
7
8
9
10
13
14
15
16
17
18
19
20
21
22
23
24
25
261
262
263
264
265
266
267
268
269
270
271
272
273
276
277
278
279
280
281
282
283
284
285
286
287
288
11
12
HD
HACT
DVALID
VD
VACT
FIELD
Input
Video Signal
260
HD
HACT
DVALID
VD
VACT
FIELD
Input
Video Signal
274
275
HD
HACT
DVALID
VD
VACT
FIELD
Input
Video Signal
522
HD
HACT
DVALID
VD
VACT
A
B
C
D
FIELD
Because of line repeating process during progressive signal conversion, as shown in the figure above
A line and B line / C line and D line is output as the same signal. The FIELD signal is being toggle.
* Both ODD/ EVEN field has 486-line during active section not 487-line.
MS1189-E-01
2010/12
-26-
[AK8857VQ]
Input : 525-line, Horizontal line : 487-line, Output : Progressive (30frm/sec) (ODD Field output)
Input
Video Signal
523
524
525
1
2
3
4
5
6
7
8
9
10
13
14
15
16
17
18
19
20
21
22
23
24
25
11
12
HD
HACT
DVALID
VD
VACT
FIELD
Input
Video Signal
260
HD
HACT
DVALID
VD
VACT
A
B
C
D
FIELD
Input
Video Signal
261
262
263
264
265
266
267
268
269
270
271
272
273
276
277
278
279
280
281
282
283
284
285
286
287
288
274
275
HD
HACT
DVALID
VD
VACT
FIELD
Input
Video Signal
522
HD
HACT
DVALID
VD
VACT
FIELD
Because of line repeating process during progressive signal conversion, as shown in the figure above
A line and B line / C line and D line is output as the same signal. The FIELD signal is being toggle.
* Both ODD/ EVEN field has 486-line during active section not 487-line.
MS1189-E-01
2010/12
-27-
[AK8857VQ]
Input : 525-line, Horizontal line : 487-line, Output : Progressive (30frm/sec) (EVEN Field output)
Input
Video Signal
523
524
525
1
2
3
4
5
6
7
8
9
10
13
14
15
16
17
18
19
20
21
22
23
24
25
261
262
263
264
265
266
267
268
269
270
271
272
273
276
277
278
279
280
281
282
283
284
285
286
287
288
11
12
HD
HACT
DVALID
VD
VACT
FIELD
Input
Video Signal
260
HD
HACT
DVALID
VD
VACT
FIELD
Input
Video Signal
274
275
HD
HACT
DVALID
VD
VACT
FIELD
Input
Video Signal
522
HD
HACT
DVALID
VD
VACT
A
B
C
D
FIELD
Because of line repeating process during progressive signal conversion, as shown in the figure above
A line and B line / C line and D line is output as the same signal. The FIELD signal is being toggle.
* Both ODD/ EVEN field has 486-line during active section not 487-line.
MS1189-E-01
2010/12
-28-
[AK8857VQ]
Input : 525-line, Horizontal line : 487-line, Output : Interlace
Input
Video Signal
523
524
525
1
2
3
4
5
6
7
8
9
10
11
12
HD
HACT
DVALID
VD
VACT
FIELD
ODD
EVEN
13
14
15
16
17
18
19
20
21
22
23
24
25
261
262
263
264
265
266
267
268
269
270
271
272
273
284
285
286
287
288
Input
Video Signal
260
HD
HACT
DVALID
VD
VACT
FIELD
Input
Video Signal
274
275
HD
HACT
DVALID
VD
VACT
ODD
FIELD
Input
Video Signal
276
277
278
279
280
EVEN
281
282
283
522
HD
HACT
DVALID
VD
VACT
FIELD
MS1189-E-01
2010/12
-29-
[AK8857VQ]
Input : 525-line, Horizontal line : 480-line, Output : Progressive (60frm/sec)
Input
Video Signal
523
524
525
1
2
3
4
5
6
7
8
9
10
13
14
15
16
17
18
19
20
21
22
23
24
25
261
262
263
264
265
266
267
268
269
270
271
272
273
276
277
278
279
280
281
282
283
284
285
286
287
288
11
12
HD
HACT
DVALID
VD
VACT
FIELD
Input
Video Signal
260
HD
HACT
DVALID
VD
VACT
FIELD
Input
Video Signal
274
275
HD
HACT
DVALID
VD
VACT
FIELD
Input
Video Signal
522
HD
HACT
DVALID
VD
VACT
A
B
C
D
FIELD
Because of line repeating process during progressive signal conversion, as shown in the figure above
A line and B line / C line and D line is output as the same signal. The FIELD signal is being toggle.
MS1189-E-01
2010/12
-30-
[AK8857VQ]
Input : 525-line, Horizontal line : 480-line, Output : Progressive (30frm/sec) (ODD field output)
Input
Video Signal
523
524
525
1
2
3
4
5
6
7
8
9
10
13
14
15
16
17
18
19
20
21
22
23
24
25
11
12
HD
HACT
DVALID
VD
VACT
FIELD
Input
Video Signal
260
HD
HACT
DVALID
VD
VACT
A
B
C
D
FIELD
Input
Video Signal
261
262
263
264
265
266
267
268
269
270
271
272
273
276
277
278
279
280
281
282
283
284
285
286
287
288
274
275
HD
HACT
DVALID
VD
VACT
FIELD
Input
Video Signal
522
HD
HACT
DVALID
VD
VACT
FIELD
Because of line repeating process during progressive signal conversion, as shown in the figure above
A line and B line / C line and D line is output as the same signal. The FIELD signal is being toggle.
MS1189-E-01
2010/12
-31-
[AK8857VQ]
Input : 525-line, Horizontal line : 480-line, Output : Progressive (30frm/sec) (EVEN field output)
Input
Video Signal
523
524
525
1
2
3
4
5
6
7
8
9
10
13
14
15
16
17
18
19
20
21
22
23
24
25
261
262
263
264
265
266
267
268
269
270
271
272
273
276
277
278
279
280
281
282
283
284
285
286
287
288
11
12
HD
HACT
DVALID
VD
VACT
FIELD
Input
Video Signal
260
HD
HACT
DVALID
VD
VACT
FIELD
Input
Video Signal
274
275
HD
HACT
DVALID
VD
VACT
FIELD
Input
Video Signal
522
HD
HACT
DVALID
VD
VACT
A
B
C
D
FIELD
Because of line repeating process during progressive signal conversion, as shown in the figure above
A line and B line / C line and D line is output as the same signal. The FIELD signal is being toggle.
MS1189-E-01
2010/12
-32-
[AK8857VQ]
Input : 525-line, Horizontal line : 240-line/234-line, Output : (ODD field output)
Input
Video Signal
523
524
525
1
2
3
4
5
6
7
8
9
10
11
12
HD
HACT
DVALID
VD
VACT
FIELD
Input
Video Signal
ODD
EVEN
13
14
15
16
17
18
19
20
21
22
23
24
25
261
262
263
264
265
266
267
268
269
270
271
272
273
284
285
286
287
288
260
HD
HACT
DVALID
VD
VACT
FIELD
Input
Video Signal
274
275
HD
HACT
DVALID
VD
VACT
ODD
FIELD
Input
Video Signal
276
277
278
279
280
EVEN
281
282
283
522
HD
HACT
DVALID
VD
VACT
FIELD
In 234-line output case, as shown above lines from line 22 to 24 and from line 259 to 261 is not count
as active line. For that reason, HACT, VACT and DVALID is “High” during the line mentioned above.
MS1189-E-01
2010/12
-33-
[AK8857VQ]
Input : 525-line, Horizontal line : 240-line/234-line, Output : (EVEN field output)
Input
Video Signal
523
524
525
1
2
3
4
5
6
7
8
9
10
11
12
HD
HACT
DVALID
VD
VACT
FIELD
Input
Video Signal
ODD
EVEN
13
14
15
16
17
18
19
20
21
22
23
24
25
261
262
263
264
265
266
267
268
269
270
271
272
273
284
285
286
287
288
260
HD
HACT
DVALID
VD
VACT
FIELD
Input
Video Signal
274
275
HD
HACT
DVALID
VD
VACT
ODD
FIELD
Input
Video Signal
276
277
278
279
280
EVEN
281
282
283
522
HD
HACT
DVALID
VD
VACT
FIELD
In 234-line output case, as shown above lines from line 22 to 24 and from line 259 to 261 is not count
as active line. For that reason, HACT, VACT and DVALID is “High” during the line mentioned above.
MS1189-E-01
2010/12
-34-
[AK8857VQ]
Input : 625-line, Horizontal line : 576-line
Input
Video Signal
620
621
622
623
624
625
1
2
3
4
5
6
7
8
9
HD
HACT
DVALID
VD
VACT
Input
Video Signal
ODD
EVEN
FIELD
10
21
22
23
24
25
26
27
28
29
30
31
309
310
311
312
313
314
315
316
317
318
319
340
341
342
343
344
306
HD
HACT
DVALID
VD
VACT
FIELD
307
Input
308
320
321
Video Signal
HD
HACT
DVALID
VD
VACT
ODD
FIELD
Input
Video Signal
322
277
334
335
336
EVEN
337
338
339
619
HD
HACT
DVALID
VD
VACT
FIELD
MS1189-E-01
2010/12
-35-
[AK8857VQ]
Input : 625-line, Horizontal line : 576-line, Output : Progressive (60frm/sec)
Input
Video Signal
620
621
622
623
624
625
1
2
3
4
5
6
7
21
22
23
24
25
26
27
28
29
30
31
8
9
HD
HACT
DVALID
VD
VACT
FIELD
Input
Video Signal
10
306
HD
HACT
DVALID
VD
VACT
FIELD
Input
Video Signal
307
308
309
310
311
312
313
314
315
316
317
318
319
322
277
334
335
336
337
338
339
340
341
342
343
344
320
321
HD
HACT
DVALID
VD
VACT
FIELD
Input
Video Signal
619
HD
HACT
DVALID
VD
VACT
A
B
C
D
FIELD
Because of line repeating process during progressive signal conversion, as shown in the figure above
A line and B line / C line and D line is output as the same signal. The FIELD signal is being toggle.
* In the above figure, both ODD/EVEN field line number is 574-line. To set the active line to 576-line,
set the VBIL[2:0] register to 0x01 value.
MS1189-E-01
2010/12
-36-
[AK8857VQ]
Input : 625-line, Horizontal line : 576-line, Output : Progressive (30frm/sec) (ODD field output)
Input
Video Signal
620
621
622
623
624
625
1
2
3
4
5
6
7
21
22
23
24
25
26
27
28
29
30
31
8
9
HD
HACT
DVALID
VD
VACT
FIELD
Input
Video Signal
10
306
HD
HACT
DVALID
VD
VACT
A
B
C
D
FIELD
Input
Video Signal
307
308
309
310
311
312
313
314
315
316
317
318
319
322
277
334
335
336
337
338
339
340
341
342
343
344
320
321
HD
HACT
DVALID
VD
VACT
FIELD
Input
Video Signal
619
HD
HACT
DVALID
VD
VACT
FIELD
Because of line repeating process during progressive signal conversion, as shown in the figure above
A line and B line / C line and D line is output as the same signal. The FIELD signal is being toggle.
* In the above figure, both ODD/EVEN field line number is 574-line. To set the active line to 576-line,
set the VBIL[2:0] register to 0x01 value.
MS1189-E-01
2010/12
-37-
[AK8857VQ]
Input : 625-line, Horizontal line : 576-line, Output : Progressive (30frm/sec) (EVEN field output)
Input
Video Signal
620
621
622
623
624
625
1
2
3
4
5
6
7
21
22
23
24
25
26
27
28
29
30
31
8
9
HD
HACT
DVALID
VD
VACT
FIELD
Input
Video Signal
10
306
HD
HACT
DVALID
VD
VACT
FIELD
Input
Video Signal
307
308
309
310
311
312
313
314
315
316
317
318
319
322
277
334
335
336
337
338
339
340
341
342
343
344
320
321
HD
HACT
DVALID
VD
VACT
FIELD
Input
Video Signal
619
HD
HACT
DVALID
VD
VACT
A
B
C
D
FIELD
Because of line repeating process during progressive signal conversion, as shown in the figure above
A line and B line / C line and D line is output as the same signal. The FIELD signal is being toggle.
* In the above figure, both ODD/EVEN field line number is 574-line. To set the active line to 576-line,
set the VBIL[2:0] register to 0x01 value.
MS1189-E-01
2010/12
-38-
[AK8857VQ]
Input : 625-line, Horizontal line : 480-line
Input
Video Signal
620
621
622
623
624
625
1
2
3
4
5
6
7
8
9
HD
HACT
DVALID
VD
VACT
Input
Video Signal
ODD
EVEN
FIELD
10
21
22
23
24
25
26
27
28
29
30
31
309
310
311
312
313
314
315
316
317
318
319
340
341
342
343
344
306
HD
HACT
DVALID
VD
VACT
FIELD
Input
Video Signal
307
308
320
321
HD
HACT
DVALID
VD
VACT
ODD
FIELD
Input
Video Signal
322
277
334
335
336
EVEN
337
338
339
619
HD
HACT
DVALID
VD
VACT
FIELD
As shown in the figure above, start from line 25 / line 338 to the next starting line of each 5 line, the line
is output as not active line. HACT and DVALID is “High” during the line mentioned.
EAV sync code is added to the line mentioned above and SAV sync code is not.
MS1189-E-01
2010/12
-39-
[AK8857VQ]
Input : 625-line, Horizontal line : 480-line, Output : Progressive (60frm/sec)
Input
Video Signal
620
621
622
623
624
625
1
2
3
4
5
6
7
21
22
23
24
25
26
27
28
29
30
31
8
9
HD
HACT
DVALID
VD
VACT
FIELD
Input
Video Signal
10
306
HD
HACT
DVALID
VD
VACT
FIELD
Input
Video Signal
307
308
309
310
311
312
313
314
315
316
317
318
319
322
277
334
335
336
337
338
339
340
341
342
343
344
320
321
HD
HACT
DVALID
VD
VACT
FIELD
Input
Video Signal
619
HD
HACT
DVALID
VD
VACT
A
B
C
D
FIELD
Because of line repeating process during progressive signal conversion, as shown in the figure above
A line and B line / C line and D line is output as the same signal. The FIELD signal is being toggle.
As shown in the figure above, start from line 25 / line 338 to the next starting line of each 10 line, the
line is output as not active line. HACT and DVALID is “High” during the line mentioned.
EAV sync code is added to the line mentioned above and SAV sync code is not.
* In the above figure, both ODD/EVEN field line number is 478-line. To set the active line to 480-line,
set the VBIL[2:0] register value to 0x01.
MS1189-E-01
2010/12
-40-
[AK8857VQ]
Input : 625-line, Horizontal line : 480-line, Output : Progressive (30frm/sec) (ODD field output)
Input
Video Signal
620
621
622
623
624
625
1
2
3
4
5
6
7
21
22
23
24
25
26
27
28
29
30
31
8
9
HD
HACT
DVALID
VD
VACT
FIELD
Input
Video Signal
10
306
HD
HACT
DVALID
VD
VACT
A
B
C
D
FIELD
Input
Video Signal
307
308
309
310
311
312
313
314
315
316
317
318
319
322
277
334
335
336
337
338
339
340
341
342
343
344
320
321
HD
HACT
DVALID
VD
VACT
FIELD
Input
Video Signal
619
HD
HACT
DVALID
VD
VACT
FIELD
Because of line repeating process during progressive signal conversion, as shown in the above figure
A line and B line / C line and D line is output as the same signal. The FIELD signal is being toggle.
As shown in the figure above, start from line 25 to the next starting line of each 10 line, the line is
output as not active line. HACT and DVALID is “High” during the line mentioned.
EAV sync code is added to the line mentioned above and SAV sync code is not.
* In the above figure, both ODD/EVEN field line number is 478-line. To set the active line to 480-line,
set the VBIL[2:0] register value to 0x01.
MS1189-E-01
2010/12
-41-
[AK8857VQ]
Input : 625-line, Horizontal line : 480-line, Output : Progressive (30frm/sec) (EVEN field output)
Input
Video Signal
620
621
622
623
624
625
1
2
3
4
5
6
7
21
22
23
24
25
26
27
28
29
30
31
8
9
HD
HACT
DVALID
VD
VACT
FIELD
Input
Video Signal
10
306
HD
HACT
DVALID
VD
VACT
FIELD
Input
Video Signal
307
308
309
310
311
312
313
314
315
316
317
318
319
322
277
334
335
336
337
338
339
340
341
342
343
344
320
321
HD
HACT
DVALID
VD
VACT
FIELD
Input
Video Signal
619
HD
HACT
DVALID
VD
VACT
A
B
C
D
FIELD
Because of line repeating process during progressive signal conversion, as shown in the figure above,
A line and B line / C line and D line is output as the same signal. The FIELD signal is being toggle.
As shown in the figure above, start from line 338 to the next starting line of each 10 line, the line is
output as not active line. HACT and DVALID is “High” during the line mentioned.
EAV sync code is added to the line mentioned above and SAV sync code is not.
* In the above figure, both ODD/EVEN field line number is 478-line. To set the active line to 480-line,
set the VBIL[2:0] register value to 0x01.
MS1189-E-01
2010/12
-42-
[AK8857VQ]
Input : 625-line, Horizontal line : 240-line/234-line, Output : Progressive (ODD field output)
Input
Video Signal
620
621
622
623
624
625
1
2
3
4
5
6
7
8
9
HD
HACT
DVALID
VD
VACT
Input
Video Signal
ODD
EVEN
FIELD
10
21
22
23
24
25
26
27
28
29
30
31
309
310
311
312
313
314
315
316
317
318
319
340
341
342
343
344
306
HD
HACT
DVALID
VD
VACT
FIELD
Input
Video Signal
307
308
320
321
HD
HACT
DVALID
VD
VACT
ODD
FIELD
Input
Video Signal
322
277
334
335
336
EVEN
337
338
339
619
HD
HACT
DVALID
VD
VACT
FIELD
As shown in the figure above, start from line 25 to the next starting line of each 5 line, the line is output
as not active line. HACT and DVALID is “High” during the line mentioned.
EAV sync code is added to the line mentioned above and SAV sync code is not.
In 234-line output case, as shown above, lines from line 23 to 26 and from line 308 to 310 is not count
as active line. For that reason, HACT, VACT and DVALID output is “High” during the line mentioned
above.
MS1189-E-01
2010/12
-43-
[AK8857VQ]
Input : 625-line, Horizontal line : 240-line/234-line, Output : Progressive (EVEN field output)
Input
Video Signal
620
621
622
623
624
625
1
2
3
4
5
6
7
8
9
HD
HACT
DVALID
VD
VACT
Input
Video Signal
ODD
EVEN
FIELD
10
21
22
23
24
25
26
27
28
29
30
31
309
310
311
312
313
314
315
316
317
318
319
340
341
342
343
344
306
HD
HACT
DVALID
VD
VACT
FIELD
Input
Video Signal
307
308
320
321
HD
HACT
DVALID
VD
VACT
ODD
FIELD
Input
Video Signal
322
277
334
335
336
EVEN
337
338
339
619
HD
HACT
DVALID
VD
VACT
FIELD
As shown in the figure above, start from line 338 to the next starting line of each 5 line, the line is
output as not active line. HACT and DVALID is “High” during the line mentioned.
EAV sync code is added to the line mentioned above and SAV sync code is not.
In 234-line output case, as shown above, lines from line 336 to 339 and from line 621 to 623 is not
count as active line. For that reason, HACT, VACT and DVALID output is “High” during the line
mentioned above.
MS1189-E-01
2010/12
-44-
[AK8857VQ]
Input video signal categorization
The AK8857 can decode the following video signals, in accordance with the register setting.
NTSC-M,J
NTSC-4.43
PAL-B,D,G,H,I,N
PAL-Nc
PAL-M
PAL-60
SECAM
The register settings for the input signal characterization are essentially as follows.
○VSCF[1:0]-bi: Setting for subcarrier frequency of input signal
VSCF[1:0]-bit
Subcarrier frequency (MHz)
Notes
[00]
3.57954545
NTSC-M,J
[01]
3.57561149
PAL-M
[10]
3.58205625
PAL-Nc
PAL-B,D,G,H,I,N , NTSC-4.43 , PAL-60
[11]
4.43361875
SECAM*
*For SECAM input signal, set VSCF[1:0] to [11].
○VCEN[1:0]-bit: Setting for color encode format of input signal.
VCEN[1:0]-bit
[00]
[01]
[10]
[11]
Color encode format
NTSC
PAL
SECAM
Reserved
Notes
○VLF-bit : Setting for line frequency of each input frame.
VLF-bit
Number of lines
Notes
[0]
525
NTSC-M,J , NTSC-4.43 , PAL-M, PAL-60
[1]
625
PAL-B,D,G,H,I,N,Nc , SECAM
○BW-bit: Setting for decoding of input signal as monochrome signal (monochrome mode)
BW-bit
Signal type
Notes
[0]
Not monochrome (monochrome mode OFF)
[1]
Decode as monochrome signal (monochrome mode ON)
In the monochrome mode at CVBS decoding, the input signal is treated as a monochrome signal, and all
sampling data digitized the the AD converter passes through the luminance process and is processed as
a luminance signal. Thus, with this bit ON, the signal input to the Y/C separation block is all output as
luminance signal data to the luminance signal processing block.
In the monochrome mode at S-video decoding, Y signal is only decoded.
In the monochrome mode, the CbCr code is output as 0x80 (601 level data) regardless of the input.
MS1189-E-01
2010/12
-45-
[AK8857VQ]
○SETUP-bit: Setting for presence or absence of input signal SETUP.
SETUP-bit
SETUP presence/absence
Notes
[0]
Setup absent
[1]
Setup present
7.5IRE Setup
With the Setup present setting, the luminance and color signals are processed as follows:
Luminance signal: Y=(Y-7.5)/0.925
Color signal: U=U/0.925, V=V/0.925
MS1189-E-01
2010/12
-46-
[AK8857VQ]
Input Signal Auto Detection Function
The register settings for auto detection are essentially as follows.
○AUTODET-bit: Settings for auto detection of input signal (auto detection mode)
AUTODET-bit
Auto detection
Notes
[0]
OFF
Manual setting
[1]
ON
The auto detection recognizes the following parameters.
Number of lines per frame: 525/625
Carrier frequencies: 3.57954545
3.57561149
3.58205625
4.43361875
Color encoding formats:
NTSC
PAL
SECAM
Monochrome signal: Not monochrome/monochrome
Note: Automatic monochrome detection is active if the color kill setting is ON (COLKILL-bit = [1].)
The AK8857 stores the detected parameter to the Input Video Status Register (thus, as an internal
notice function).
This enables the host to distinguish among the formats NTSC-M, J; NTSC-4.43; PAL-B, D, G, H, I, N;
PAL-M; PAL-Nc; PAL-60; SECAM; and monochrome.
It should be noted that it does not detect NTSC-M, NTSC-J, or PAL-B, D, G, H, I, N formats.
(Notice)
“Direct SYNC VLOCK” (Sub-Address0x03[7]=1) must not use when it is being operated on auto
detection function.
MS1189-E-01
2010/12
-47-
[AK8857VQ]
Limiting auto input video signal detection function
The AK8857 has the function to limit the input video signal to be detected during auto detection
mode.
○NDMODE Register: For limiting auto detection candidates
Bit
Register Name
R/W Definition
bit 0 NDPALM
No Detect PAL-M bit
R/W
[0]: PAL-M candidate
[1]: PAL-M non-candidate
bit 1 NDPALNC
No Detect PAL-Nc bit
R/W
0]: PAL-Nc candidate
[1]: PAL-Nc non-candidate
bit 2 NDSECAM
No Detect SECAM bit
R/W
[0]: SECAM candidate
[1]: SECAM non-candidate
bit 3 Reserved
Reserved
R/W
Reserved
bit 4 NDNTSC443
No Detect NTSC-4.43
R/W
bit
0]: NTSC-4.43 candidate
[1]: NTSC-4.43 non-candidate
bit 5 NDPAL60
No Detect PAL-60 bit
R/W
[0]: PAL-60 candidate
[1]: PAL-60 non-candidate
bit 6 ND525L
No Detect 525Line bit
R/W
[0]: 525 line candidate
[1]: 525 line non-candidate
bit 7 ND625L
No Detect 625Line bit
R/W
[0]: 625 line candidate
[1]: 625 line non-candidate
In making the above register settings, the following restrictions is apply,
1. Setting both NDNTSC443(bit 4) and NDPAL60(bit 5) to [1] (High) is prohibited.
2. Setting both ND525L(bit 6) and ND625L(bit 7) to [1] (High) is prohibited.
3. To limit candidate formats, it is necessary to have the auto detection mode OFF while first
setting the register to non-limited signal status and next the NDMODE settings, and then
setting the auto detection mode to ON.
Set auto detection mode to OFF
Set Input Video Standard Register to non-limited signal status
Enter NDMODE Register Settings
Set auto detection mode to ON
MS1189-E-01
2010/12
-48-
[AK8857VQ]
Output Data format
In the AK8857, the settings for the output code and the vertical blanking intervals for the output signal
are as follows.
○601LIMIT-bit: Settings for output data code Min/Max
601LIMIT-bit
Output data code Min~Max
Notes
Y: 1~254
[0]
Default
Cb, Cr: 1~254
Y: 16~235
[1]
Cb, Cr: 16~240
All internal calculating operations are made with Min = 1, Max = 254.
With 601LIMIT-bit set to [1], codes 1~15 and 236~254 are respectively clipped to 16,235.
○TRSVSEL-bit: Settings for V-bit handling in ITU-R BT.656 format
525-line
625-line
TRSVSEL-bit
V-bit=0
V-bit=1
V-bit=0
V-bit=1
[0]
Line10~Line263
Line1~Line9
ITU-R BT 656-3
Line273~Line525 Line264~Line272
Line1~Line22
Line23~Line310
Line311~Line335
[1]
Line336~Line623
Line20~Line263
Line1~Line19
Line624~Line625
ITU-R BT 656-4
Line283~Line525 Line264~Line282
SMPTE125M
The TRSVSEL register only available during the interlace output decode by ITU-R BT.601 output size.
These values are unaffected by the VBIL[2:0]-bits setting.
○VBIL[2:0]-bit: Settings for vertical blanking interval
VBIL[2:0]-bit
Line Adjustment width
[000]
Default
[001]
1Line advance
2Line advance
*1
*2
2Lines advance
*1
4Lines advance
*2
3Lines advance
*1
6Lines advance
4Lines advance
8Lines advance
*2
*1
*2
5Lines advance
*1
[010]
[011]
[100]
[101]
10Lines advance
6Lines advance
[110]
12Lines advance
7Lines advance
[111]
14Lines advance
*1: Other than progressive output
*2: Progressive output
Notes
*2
*1
*2
*1
*2
The starting position of HACT signal and DVALID signal is changed according to VACT signal
starting position.
MS1189-E-01
2010/12
-49-
[AK8857VQ]
*1
Input
Video Signal
18
19
20
21
22
23
24
25
HD
HACT
VBIL=[000]
DVALID
VACT
HACT
VBIL=[001]
DVALID
VACT
*2
18
19
20
21
22
23
24
25
Input
Video Signal
HD
HACT
VBIL=[000]
DVALID
VACT
VBIL=[001]
DVALID
VACT
HACT
○SLLVL-bit: Settings for slice level
SLLVL-bit
Slice level
[0]
25IRE
[1]
50IRE
The results of VBI slicing by the AK8857 slicing function are output as ITU-R BT.601 digital data. The
VBI interval is set via VBIL[2:0]-bits. VBI slicing is performed in the luminance signal processing path,
so that the Cb/Cr value of the effective line 601 output code is output at the same level as the
corresponding luminance signal.
The slice level and the output code are set via the register. The output code value is set via the
Hi/Low Slice Data Set Register, as follows.
Hi Slice Data Set Register*:
Setting for higher of two values resulting from slicing.
Default: 0xEB(235)
Low Slice Data Set Register*: Setting for lower of two values resulting from slicing.
Default: 0x10(16)
*Note that a setting of 0x00 or 0xFF corresponds to a special 601 code.
MS1189-E-01
2010/12
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[AK8857VQ]
○VBIDEC[1:0]-bit: Settings for decode data in the VBI period
VBIDEC[1:0]-bit
Decode data
Notes
Y = 0x10
Cb/Cr = 0x80
Y = data converted to 601 level
[01]
Monochrome mode
Cb/Cr = 0x80
Sliced data output
Y/Cb/Cr = value corresponding to slice level
[10]
during VBI
(Value set at Hi/Low Slice Data Set Register)
[11]
Reserved
Reserved
Note that, with VBI period settings of Lines 1~9 and 263.5~272.5 in the 525 Line and Lines 623.5~6.5
and 311~318 in the 625 Line, the setting VBIDEC[1:0] will not be entered and the output will be in
Black level code.
[00]
Black level output
(mV*)
NTSC/PAL
601 Code
714/700
235
100% White
357/350
127
50IRE threshold with
setting SLLVL = [1]
180/175
63
25IRE threshold with
setting SLLVL = [0]
L:
H:
L
`````
L
Cb/Y
````
``````
L
L
Cr/Y
H
H
Cb/Y
````
``````
H
H
Cr/Y
L
Value set by Low Slice
Data Set Register
Value set by High Slice
Data Set Register
```````
*Threshold values (mV) are approximate.
High/Low conversion is performed for either the Cb/Y or the Cr/Y combination.
is an example of the conversion points for Cb/Y.
MS1189-E-01
The above figure
2010/12
-51-
[AK8857VQ]
Output pin status
For normal operation, the output from the DATA_A[7:0], HD_ACT_A, VD_ACT_A,
DVALID_A, FIELD_A, NSIG_A, DATA_B[7:0], HD_ACT_B, VD_ACT_B, DVALID_B, FIELD_B,
NSIG_B pins can each be fixed at Low via the Output Control Register.
The black level and blue level output have the priority to be output from the DATA_A[7:0] and
DATA_B[7:0] pins regardless of these register settings.
Note, however, that the OE_A, OE_B, PDN, RSTN pins and AINSEL[4:0] (non decode) states will
have priority regardless of these register settings.
Output pin timing signal
The timing signal can be output from the HD_ACT_A, VD_ACT_A, DVALID_A, FIELD_A,
HD_ACT_B, VD_ACT_B, DVALID_B, FIELD_B pins. The polarity of each timing signal at the output
pin can be invert by register setting.
At the HD_ACT output pin, the output signal can be selected between HD signal and HACT signal by
register setting.
At the VD_ACT output pin, the output signal can be selected between VD signal and VACT signal by
register setting.
○VDACTSEL-bit : VD/ VACT signal output setting
VDACTSEL-bit
VD_ACT output pin setting
[0]
VD signal is output
[1]
VACT signal is output
○HDACTSEL-bit : HD/ HACT signal output setting
HDACTSEL-bit
HD_ACT output pin setting
[0]
HD signal is output
[1]
HACT signal is output
The polarity of output from the DATA_A[7:0] / DATA_B[7:0] and DTCLKcan be inverted.
○CLKINV-bit: DTCLK signal polarity setting
CLKINV-bit
Polarity setting
[0]
Rising edge
[1]
Falling edge
If each of A or B output 54MHz, DTCLK pin output 54MHz. So, Not IP conversion data is alternated by
2CLK.
MS1189-E-01
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-52-
[AK8857VQ]
A and B block at 27Mhz/54Mhz
output
CLKINV-bit
A block : IP conversion output
DTCLK
A Block : CLKINV=[0]
B Block : CLKINV=[0]
DTCLK
DATA_A[7:0]
D0
D1
D2
D3
D4
DATA_A[7:0] D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
DATA_B[7:0]
D0
D1
D2
D3
D4
DATA_B[7:0]
DTCLK
A Block : CLKINV=[1]
B Block : CLKINV=[0]
D1
D0
D1
D0
D2
D2
D3
D3
D4
DTCLK
A Block : CLKINV=[0]
B Block : CLKINV=[1]
DATA_A[7:0]
DATA_B[7:0]
D3
D4
DATA_A[7:0]
D0 D1 D2 D3 D4 D5 D6 D7 D8
DATA_B[7:0]
D0
D1
D2
D3
D4
DTCLK
D1
D0
D0
D2
D1
D3
D2
DATA_A[7:0] D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
D4
DATA_B[7:0]
D3
DTCLK
A Block : CLKINV=[1]
B Block : CLKINV=[1]
D2
DTCLK
DATA_A[7:0]
DATA_B[7:0]
D1
D0
D0
D1
D2
D3
D4
DTCLK
DATA_A[7:0]
D0
D1
D2
D3
DATA_A[7:0]
DATA_B[7:0]
D0
D1
D2
D3
DATA_B[7:0]
D0 D1 D2 D3 D4 D5 D6 D7 D8
D0
D1
D2
D3
D4
Output data timing
The AK8857 can control timing of output data.
○YCDELAY[2:0]-bit: Adjustment of Y and C timing.
YCDELAY[2:0]-bit
Y and C timing
[001]
Y advance 1sample toward C.
[010]
Y advance 2 sample toward C.
[011]
Y advance 3 sample toward C.
[000]
No Delay and advance.
[101]
Y delay 3 sample toward C.
[110]
Y delay 2 sample toward C.
[111]
Y delay 1 sample toward C.
[100]
Reserved
*Setting by 2 complement
Because each sample is delay/advance toward C, 1sample is equall to 1clk width.
Notes
2clk advance
4clk advance
6clk advance
Default value
6clk delay
4clk delay
2clk delay
YCDELAY[2:0] = [000]
Cb0 Y0
Cr0
Y1
Cb1 Y2
Cr1
Y3
Cb2 Y4
Cr2
Y5
Y/C default
YCDELAY[2:0] = [111]
Cb0 Y857 Cr0
Y0
Cb1 Y1
Cr1
Y2
Cb2 Y3
Cr2
Y4
1sample delay
YCDELAY[2:0] = [001]
Cb0 Y1
Y2
Cb1 Y3
Cr1
Y4
Cb2 Y5
Cr2
Y6
1sample adv.
Cr0
DTCLK
MS1189-E-01
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-53-
[AK8857VQ]
○ACTSTA[2:0]-bit: Adjustment of active video start position
ACTSTA[2:0]-bit
Line and active video start
[001]
525 Line
Starting postion is delay 1 sample
[010]
525 Line
Starting postion is delay 2 sample
[011]
525 Line
Starting postion is delay 3 sample
[000]
525 Line
Default value
[101]
[110]
[111]
525 Line
525 Line
525 Line
Starting postion is advance 3 sample
Starting postion is advance 2 sample
Starting postion is advance 1 sample
[100]
Reserved
Reserved
Notes
2clk delay
4clk delay
6clk delay
Normal
position
6clk advance
4clk advance
2clk advance
When the start position of active video is changed, the end position of active video also changed.
(Active video space is fixed)
Example : 720x487, 720x576(ITU-R BT.601)
Video Signal
HD
DVALID
HACT
128CLK
ACTSTA[2:0]
=[000]
244CLK
(264CLK)
1440CLK
Active video section
32CLK
(24CLK)
DVALID
HACT
ACTSTA[2:0]
=[001]
1sample
(2CLK)
1sample
(2CLK)
VLOCK mechanism
The AK8857 synchronizes internal operation with the input signal frame structure. If, for example,
the frame structure of the input signal comprises 524 lines, the internal operation will have a structure
of 524 lines per frame. This mechanism is termed the VLOCK mechanism. If an input signal
changes from a structure of 525 lines per frame to one of 524 lines per frame, internal operation will
change accordingly, and the VLOCK mechanism will go to UnLock via a pull-in process. In such case,
the UnLock status can be confirmed via the control register [VLOCK-bit]. Note that the time required
for locking of the VLOCK mechanism upon channel or other input signal switching will be about 2
frames. (PLL SYNC VLOCK)
MS1189-E-01
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-54-
[AK8857VQ]
Additionary, AK8857 supports “direct locking” mode that is not using VLOCK operation. (Direct SYNC
VLOCK)
VLOCKSEL-bit
[0]
[1]
Internal operation with the input signal frame structure
PLL SYNC VLOCK
Direct SYNC VLOCK
(Notice)
“Auto detection function” (Sub-Address0x0E[7]=1, 0x26[7]=1) must not use when it is being operated
on Direct SYNC VLOCK.
Auto Gain Control_AGC
The AGC of the AK8857 measures the size of the input sync signal (i.e., the difference between the
sync tip and pedestal levels), and adjusts the PGA value to bring the sync signal level to 286a or 300b
mV. The AGC function amplifies the input signal to the appropriate size and enables input to the AD
converter. The AGC function in the AK8857 is adaptive, and thus includes peak AGC as well as sync
AGC.
Peak AGC is effective for input signals in which the sync signal level is appropriate and only the active
video signal is large.
a
NTSC-M, J; NTSC-4.43; PAL-M…………………………..286mV
b
PAL-B, D, G, H, I, N; PAL-Nc; PAL-60; SECAM…………300mV
○AGCT[1:0]-bit : Settings for AGC time constant
AGCT[1:0]-bit
Time constant
Notes
[00]
Disable
AGC OFF, PGA register enabled.
[01]
Fast
T= 1Field
[10]
Middle
T= 7Fields
[11]
Slow
T= 29Fields
T is the time constant.
Manual setting of the PGA register is possible only if AGC is disabled.
○AGCC-bit : Settings for AGC non-sensing range
AGCC[1:0]-bit
Non-sensing range
[00]
±2LSB
[01]
±3LSB
[10]
±4LSB
[11]
None
Notes
○AGCFRZ-bit : Settings for freezing AGC function
AGCFRZ-bit
AGC status
Notes
[0]
Non-frozen
[1]
Frozen
Note. The gain value at the time of freezing is maintained during the frozen state, and it is then
possible to read out the gain value via the PGA1,2 Control Register.
MS1189-E-01
2010/12
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[AK8857VQ]
○AGCTL-bit : Settings for selection of quick or slow transition between peak and sync AGC
AGCTL-bit
AGC transition
Notes
[0]
Quick
[1]
Slow
Auto Color Control (ACC)
The ACC of the AK8854 measures the level of the input signal color burst, and adjusts the level to 286
or 300 mV, as appropriate.
The ACC is not applicable to SECAM input.
As in AGC, both ACC time constant and ACC freeze settings can be entered.
NTSC-M,J , NTSC-4.43 , PAL-M…………………………..286mV
PAL-B,D,G,H,I,N , PAL-Nc , PAL-60…………. 300mV
○ACCT[1:0]-bit : Settings for ACC time constant
ACCT[1:0]-bit
Time constant
[00]
Disable
[01]
Fast
[10]
Middle
[11]
Slow
Notes
ACC OFF
T= 2Fields
T= 8Fields
T= 30Fields
○ACCFRZ-bit : Settings for freezing ACC function
ACCFRZ-bit
ACC status
[0]
Non-frozen
[1]
Frozen
Notes
The ACC and Color saturation functions operate independently. If ACC is enabled, the color
saturation adjustment is applied to the signal that has been adjusted to the appropriate level by the
ACC.
No-signal output
If no input signal is found (as shown by the control bit NOSIG-bit), the output signal is black-level, blue
level (blueback), or input-state (sandstorm), depending on the register setting.
○NSIGMD-bit : Settings for output signals for no input signal
NSIGMD [1:0]-bit
Output
[00]
Black-level
[01]
Blue-level (blueback)
[10]
Input-state (sandstorm)
[11]
Reserved
MS1189-E-01
Notes
2010/12
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[AK8857VQ]
Y/C separation
The adaptive two-dimensional Y/C separation of the AK8857 utilizes a correlation detector to select
the best-correlated direction from among vertical, horizontal, and diagonal samples, and selects the
optimum Y/C separation mode. For NTSC-4.43, PAL-60, and SECAM inputs, the Y/C separation is
one-dimensional only, regardless of the setting.
○YCSEP[1:0]-bit : Settings for Y/C separation method
YCSEP[1:0]-bit
Y/C separation mode
[00]
Adaptive
[01]
1-D
[10]
2-D
Notes
1D (BPF)
NTSC-M, J, PAL-M: 3 Line 2-D
PAL-B, D, G, H, I, N, Nc: 5 Line 2-D
(*1)
[11]
Reserved
For NTSC-4.43, PAL-60, and SECAM inputs, Y/C separation is 1-D only, regardless of the setting.
C filter
The bandwidth of the C filter can be set via the register, as follows.
○C358FIL[1:0]: Settings for C filter bandwidth, for input signal with 3.58 MHz subcarrier wave
C358FIL[1:0] -bit
C filter bandwidth setting
Notes
[00]
Narrow
[01]
Medium
NTSC-M, J, PAL-M, PAL-Nc
[10]
Wide
[11]
Reserved
MS1189-E-01
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[AK8857VQ]
○C443FIL[1:0]: Settings for C filter bandwidth, for input signal with 4.43 MHz subcarrier wave
C443FIL[1:0] -bit
C filter bandwidth setting
Notes
[00]
Narrow
[01]
Medium
PAL-B,D,G,H,I,N , NTSC-4.43 , PAL-60
[10]
Wide
[11]
Reserved
Note. No bandwidth selection is possible for SECAM input.
UV filter
The UV bandwidth can be changed by switch between low pass filters types for the demodulated C
signal.
○UVFILSEL-bit : Settings for UV filter switching (CVBS or S-video input)
UVFILSEL–bit
Bandwidth
[0]
Wide
[1]
Narrow
Notes
Digital Pixel Interpolator
The digital pixel interpolator of the AK8857 aligns vertical pixel positions and it also aligns horizontal
pixel position in fixed-clock operating modes.
○INTPOLOFF-bit : Settings for pixel interpolator operation
INTPOLOFF-bit
Interpolator operation
[0]
ON
[1]
OFF
MS1189-E-01
Notes
2010/12
-58-
[AK8857VQ]
Clock
The AK8857 is operational by fixed-clock. To synchronized analog video signal, it doesn’t have PLL
internally. The input clock is 27Mhz. Only when progressive output of 720x487, VGA, WVGA output
format, the data is sampling to 54Mhz generated internally from the input clock 27Mhz.
Phase correction
In PAL-B, D, G, H, I, N, Nc, 60, and M decoding, the AK8857 performs phase correction for each line.
With this function ON, color averaging is performed for each line. In the adaptive phase correction
mode, interline phase correlation is sampled and color averaging is performed for correlated samples.
Interline color averaging is also performed in NTSC-M and J decoding.
No phase correction or color averaging is performed in SECAM decoding.
○DPAL[1:0]-bit : Settings for phase correction
DPAL[1:0]-bit
Status
[00]
Adaptive phase correction mode
[01]
Phase correction ON
[10]
Phase correction OFF
[11]
Reserved
Notes
Output interface
[1] Interface with EAV/SAV Sync
The EAV/SAV Sync code of ITU-R BT.656 standard interface can be added to the output data of
AK8857 when ITU-R BT.601 output size interlaced format is selected.
For the output size other than ITU-R BT.601 output size format, 2 pixels is added to the EAV/SAV
Sync code at the outside of DVALID signal active section. The changes also apply to V bit and Fbit
according to the lines where the polarity of VACT signal and FIELD signal is changed.
Relation between VACT and V bit
HD
HACT
DVALID
VACT
V bit
EAV
EAV
SAV
Relation between FIELD and F bit
HD
DVALID
VD
FIELD
EVEN
ODD
ODD
EVEN
F bit
EAV
SAV
EAV SAV
MS1189-E-01
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[AK8857VQ]
Realtion between DVALID and EAV/SAV Sync
DTCLK
HD
DVALID
DATA [7:0]
FF
00
00
SAV Cb0
Y0
Cr0
Y1
Cb1
Y2
Cr1
FF
00
00
EAV
Since the AK8857 data is sampling using fixed-clock, the sample number from EAV to SAV is not
guarantee. For that reason, the default data output is in SAV format.
○EAVSAV-bit : EAV/SAV sync code is superimposed to the output data setting.
EAVSAV-bit
Status
Notes
[0]
Add
Default value
[1]
No change
[2] Interface with Timing signal
The AK8857 can output the HD signal, VD signal, HACT signal, VACT signal, DVALID signal and
FIELD signal at the output pins. Please refer to the Output Data Format setting for the correct timing
of each signal.
The space between DVALID signal is changed from low to high, and HD/HACT signals is changed
from high to low is not guarantee and for that reason the sample number for 1 line also is not
guarantee. But the space between HD/HACT signals is changed from high to low and DVALID signal
is changed from low to high, the timing is fixed.
Video Signal
HD
DVALID
HACT
····· SAV
Cb0
Y0
Cr0
Y1
Cb1
Y2
Cr1
Y3
······
128CLK
244CLK
(264CLK)
1440CLK
Active video portion
Y718 Cr359 Y719
FF
··············
32CLK
(24CLK)
Fixed space
Not fixed
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[AK8857VQ]
Automatic setup processing
In auto detection mode, the AK8857 can perform automatic setup processing in accordance with the
detected signal.
Setup processing of the signal to be decoded consists of the following.
Luminance signal:
Y=(Y-7.5)/0.925
Color signal:
U=U/0.925, V=V/0.925
Automatic setup processing (AK8857 in auto detection mode)
Register setting
Detected signal
NTSC-M,J
PAL-B,D,G,H,I,N
PAL-Nc , 60
SECAM
STUPATOFF-bit
(Automatic setup
processing)
Setup-bit
[0]
[1]
[0]
PAL-M
NTSC-4.43
[1]
Detected signal setup processing
status
[0]
Disable
[1]
Disable
[0]
Enable
[1]
Enable
[0]
Enable
[1]
Disable
[0]
Enable
[1]
Enable
In the auto detection mode, the setup processing status will be determined by the register setting on
the basis of the detected signal category, with no detection as to the presence or absence of input
signal setup.
PGA (programmable gain amp)
The AK8857 digital PGA is buit internally.
The setting value can be set in range of −3dB to 10dB using ADC output data.
The register default setting is 0x1F (=0dB).
When analog video signal (0.5Vpp) is input to AIN ch, the setting value becomes the default value.
⎡ 0.625 − {0.006 × (31 − PGA)}⎤
G = 20 log ⎢
⎥⎦
0.625
⎣
G：PGA gain(dB)
PGA：PGA register setting(Dec.)
○PGA1[7:0]-bit : Sets the PGA value.
○PGA2[7:0]-bit : Sets the PGA value.
CVBS input : PGA1 is enable for A Block data output and PGA2 is enable for B Block data output.
S-video input : PGA1 is enable for luminance signal and PGA2 is enable for color signal.
Notes : If the output of A block and B block are selected from the same AIN ch, only PGA1 setting
is valid and PGA2 is not valid.
This register can read the AGC setting value.
If AGC is enabled, the PGA[7:0]-bits setting value has no effect, and the PGA setting can be
manually entered in the register only if AGC is disabled.
Signal input to the AK8857 should be made with the input level attenuated approximately 39% (-8.19
dB) by resistance splitting.
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[AK8857VQ]
Sync separation, sync detection, and black-level fine tuning
The AK8857 performs sync separation and sync detection on the digitized input signal, uses the
detected sync signal as the timing reference for the decoding process, and calculates the phase error
from the separated sync signal and applies it to control of the sampling clock. Black-level tuning can be
performed in the sync separation block. The black-level fine-tuning band, which is 10 bits wide before
REC 601 conversion, can be adjusted -8~+7 LSB in 1-LSB steps, with one step resulting in a change of
about 0.4 LSB in the output code
○BKLVL[3:0]-bit : Settings for black-level fine tuning
BKLVL[3:0]-bit
Code adjustment of black level
Approx. change in 601 level (LSB)
[0001]
+1
+0.4
[0010]
+2
+0.8
[0011]
+3
+1.2
[0100]
+4
+1.6
[0101]
+5
+2.0
[0110]
+6
+2.4
[0111]
+7
+2.8
[0000]
Default
None
[1000]
-8
-3.2
[1001]
-7
-2.8
[1010]
-6
-2.4
[1011]
-5
-2.0
[1100]
-4
-1.6
[1101]
-3
-1.2
[1110]
-2
-0.8
[1111]
-1
-0.4
The black level is adjusted upward or downward by the value of the setting, which must be in
2’s-complement form. Black-level adjustment is also enabled during the vertical blanking interval.
Digital pedestal clamp
The digitally converted input signal is clamped in the digital signal processing block. The internal clamp
position depends on the input signal type (either 286 mV sync or 300 mV sync), but pedestal position
is output as code 16 for both types. The digital pedestal clamp function can adjust the time constant
and set the coring level.
○DPCT[1:0]-bit : Settings for digital pedestal clamp time constant
DPCT[1:0]-bit
Transition time constant
Notes
[00]
Fast
[01]
Middle
[10]
Slow
[11]
Disable
Digital pedestal clamp OFF
○DPCC[1:0]-bit : Settings for digital clamp pedestal coring level
DPCC[1:0]-bit
Transition time constant (bit)
[00]
±1bit
[01]
±2bit
[10]
±3bit
[11]
Non-coring
MS1189-E-01
Notes
2010/12
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[AK8857VQ]
Color killer
In CVBS or S-video input, the chroma signal quality of the input signal is determined by comparison of
its color burst level against the threshold setting in the color killer control register. If the level is below
the threshold, the color killer is activated, resulting in processing of the input as a monochrome signal
and thus with CbCr data fixed at 0x80. Depending on the register setting, the color killer may also be
activated by failure of the color decode PLL lock.
○COLKILL-bit: Settings for color killer ON and OFF
COLKILL-bit
[0]
[1]
Notes
Enable
Disable
○CKLVL[3:0]-bit: For threshold setting; default setting [1000] = −23dB.
○CKSCM[1:0]-bit: Used for threshold setting with SECAM input
CKSCM [1:0]
[00]
{CKLVL [3:0]}
[01]
{0, CKLVL [3:1]}
[10]
{0,0, CKLVL [3:2]}
[11]
Reserved
○CKILSEL: Settings for color killer activation
CKILSEL-bit
Condition for activation
[0]
Burst level below threshold setting in CKLVL[3:0]-bits
Burst level below threshold setting in CKLVL[3:0]-bits, or
[1]
Failure of color decode PLL lock
Notes
1bit shift to right
2bit shift to right
Notes
*
* PLL lock for color decode is not activate during SECAM signal is decode. The color killer ON/OFF
status also depends on No-signal and Burst-level judgement and will not effect by CKILSEL setting.
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Image quality adjustments
Image quality adjustments consist of contrast, brightness, sharpness, color saturation, and hue
adjustment. All image quality adjustments are disabled during the vertical blanking interval, but
contrast and brightness adjustment can be enabled by the register setting.
1. Contrast adjustment
CONT[7:0]-bits: For contrast adjustment; default value 0x80 (no adjustment)
Contrast adjustment involves multiplication by the gain factor setting in this register.
equation of the multiplication can be modified by register setting as follows.
If CONTSEL = [0], then YOUT = (CONT/128) x (YIN – 128) + 128
If CONTSEL = [1], then YOUT = (CONT/128) x YIN
YOUT: Contrast obtained by the calculation
YIN: Contrast before the calculation
The
CONT: Contrast gain factor (register setting value)
The gain factor can be set in the range 0~255. If the calculated value is outside the specified
contrast range, it is clipped to the upper ‘254’ or lower ‘1’ limit. With a control bit 601LIMIT setting
of [1], the output will be in the range 16~235.
○CONTSEL-bit : Settings for contrast adjustment Inclination
CONTSEL -bit
Inclination
[0]
Toward luminance of 128
[1]
Toward luminance of 0
Notes
2. Brightness adjustment
BR[7:0]-bits: For brightness adjustment; settings in 2’s complement;
default value 0x00 (no adjustment)
Brightness adjustment involves multiplication of the 8Bit data luminance signal, after ITU-R BT.601
conversion, by the gain factor setting in this register, as follows.
YOUT = YIN + BR
YOUT: Brightness obtained by the calculation
YIN: Brightness before the calculation
BR: Brightness gain factor (register setting value)
The gain factor can be set in the range -127 to +127 in steps of 1, by 2’s complement entry. If the
calculated value is outside the specified contrast range, it is clipped to the upper ‘254’ or lower ‘1’
limit. With a control bit 601LIMIT setting of [1], the output will be in the range 16~235.
3. Color saturation adjustment
SAT[7:0]-bits: For color saturation adjustment; default value 0x80 (no adjustment)
Saturation adjustment involves multiplication of the color signal by the gain factor setting in
this register. The calculated result is U/V demodulated.
The gain factor can be set in the range 0 to 255/128, in steps of 1/128.
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4. Hue adjustment
HUE[7:0]-bits: For hue adjustment; settings in 2’s complement; default value 0x00 (no adjustment)
The AK8854 can perform hue rotation with a phase rotation range of ±45° in steps of about 0.35°.
5. Sharpness adjustment
Sharpness adjustment is performed on the luminance signal as shown in the following process
diagram. The filter characteristics and the coring level can be selected by following register. A
sharp image can be obtained by selection of the filter with the appropriate characteristics.
SHARP[1:0]-bits
Luminance signal
before processing
SHCORE[1:0]-bits
Filter
Coring
Luminance signal
after processing
Delay
○SHARP[1:0]-bit: Settings for filter characteristics selection
SHARP[1:0]-bit
Filter characteristics
[00]
No filtering
[01]
Min
[10]
Middle
[11]
Max
Notes
Filter disabled
○SHCORE[1:0]-bit : Settings for coring level after sharpness filtering
SHCORE[1:0]-bit
Coring level (LSB)
Notes
[00]
No coring
Settings apply only to
[01]
±1LSB
filtered signal.
[10]
±2LSB
[11]
±3LSB
○VBIIMGCTL-bit: Settings for brightness and contrast adjustment status (ON/OFF) during VBI
VBIIMGCTL -bit
Status during VBI
Notes
[0]
Disable
[1]
Enable
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Luminance bandwidth adjustment
Luminance bandwidth adjustment can be performed for MPEG compression etc. The band-limiting
filters for pre-compression limiting can be selected by the following register settings. Without these
filters, the frequency response of the luminance signal is determined by the decimation filter.
○LUMFIL[1:0]-bit : Settings for luminance bandwidth filter
LUMFIL [1:0]-bit
Filter characteristic
No filter.
[00]
No bandwidth limit.
[01]
Narrow
[10]
Mid
[11]
Wide
Notes
-3dB at 6.29MHz
-3dB at 2.94MHz
-3dB at 3.30MHz
-3dB at 4.00MHz
Luminance bandwidth filter
Luminance signal decimation filter
Sepia output
Sepia-colored output of the decoded signal can be obtained by the following register setting.
○SEPIA-bit : Settings for sepia output of decoded signal
(Sub-address 0x14_[6])
SEPIA –bit
Output
[0]
Normal
[1]
Sepia output
MS1189-E-01
Notes
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[AK8857VQ]
VBI information decoding
The AK8857 decodes closed-caption, closed-caption-extended, VBID(CGMS), and WSS signals on
the vertical blanking signal, and writes the decoded data into a storage register. The AK8857 reads
each data bit in Request VBI Information Register(R/W)-[3:0] as a decoding request and thereupon
enters a data wait state. Data detection and decoding to the storage register are then performed
which indicates the presence or absence of data at STATUS 2 Register-[3:0] for host. The host can
therefore determine the stored values by reading the respective storage registers. The value in each
storage register is retained until a new value is written in by data renewal. For VBID data (CGMS-A),
the CRCC code is decoded and only the arithmetic result is stored in the register.
Signal type
Superimposed line
Notes
Closed Caption
Line21
525-Line
Closed Caption Extended Data
Line284
525-Line
VBID
Line20 / 283
Line20 / 333
525-Line
625-Line
WSS
Line23
625-Line
The storage registers for each of the signal types are as follows. For storage bit allocations, please
refer to the respective register setting descriptions.
Closed Caption 1 Register, Closed Caption 2 Register
WSS 1 Register, WSS 2 Register
Extended Data 1 Register, Extended Data 2 Register
VBID 1 Register, VBID 2 Register
Start
【Request VBI Info Register】
xxRQ-bit = 1
(decode request）
If Closed Caption : CCRQ-bit
If Closed Caption Extended : EXTRQ-bit
If VBID/WSS : VBWSRQ-bit
【Status Register】Read
（デコード終了確認）
Requestに対応し
たビット= 1
Yes
No
Closed Caption ならば CCDET-bit
Closed Caption Extended ならば EXTDET-bit
VBID/WSS ならば VBWSDET-bit
リクエストに対応したデータ
レジスタのリード
Closed Caption ならば【Closed Caption 1・2 Register】
Closed Caption Extended ならば 【Extended Data 1・2 Register】
VBID/WSS ならば【VBID/WSS 1・2 Register】
Internal status indicators
○NOSIG-bit: Indicates presence or absence of signal
NOSIG –bit
Status of signal input
[0]
Signal detected
[1]
No signal detected
Notes
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○VLOCK-bit: Indicates status of VLOCK
VLOCK-bit
[0]
[1]
Status of synchronization
Synchronized
Non-synchronized
○COLKILON: Indicates status of color killer (ON/OFF)
COLKILON –bit
Status of color killer
[0]
Not operation
[1]
Operation
○SCLKMODE -bit: Indicates status of color killer
SCLKMODE –bit
[00]
[01]
[10]
[11]
Clock mode
Fixed-clock
Line-locked
Frame-locked
Reserved
○PKWHITE: Indicates status of luminance decode result after passage through AGC block
PKWHITE –bit
Status of luminance decode result
[0]
Normal
[1]
Overflow
○OVCOL: Indicates status of color decode result after passage through ACC block
OVCOL –bit
Status of color decode result
[0]
Normal
[1]
Overflow
○REALFLD-bit: Indicates decoding signal field status
REALFLD -bit
Decoding field
[0]
Even
[1]
Odd
○AGCSTS-bit: Indicates status of adaptive AGC
AGCSTS -bit
Status of AGC operation
[0]
Sync AGC operation
[1]
Peak AGC operation
Notes
Notes
Notes
Notes
Notes
Notes
Notes
○Status 2-Ragister: Indicates closed caption, extended data, VBID, and WSS signal status.
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[AK8857VQ]
○Input Video Status-Register: Indicates status of automatic input signal detection
Register
BIT
R/W
Definition
Name
Input signal subcarrier frequency:
[ ST_VSF1 : ST_VSF0 ] ( MHz )
bit 0
ST_VSF0
Status of Video
[00] : 3.57954545 (NTSC-M,J)
~
~
Sub-Carrier
R
[01] : 3.57561149 (PAL-M)
bit 1
ST_VSF1
Frequency
[10] : 3.58205625 (PAL-Nc)
[11] : 4.43361875 (PAL-B,D,G,H,I,N,60 ,
NTSC-4.43)
Input signal color encode format:
[ST_VCEN1 : ST_VCEN0]
bit 2 ST_VCEN0
Status of Video Color
[00] : NTSC
~
~
R
Encode
[01] : PAL
bit 3 ST_VCEN1
[10] : SECAM
[11] : Reserved
Input signal line frequency
Status of
bit 4
ST_VLF
R
[0]: 525 line (NTSC-M,J, 4.43, PAL-M,60)
Video Line Frequency
[1]: 625 line (PAL-B,D,G,H,I,N,Nc , SECAM)
Input
signal
monochrome
or
non-monochrome : (*1)
bit 5
ST_BW
Status of B/W Signal
R
[0] : Non-monochrome detected
[1] : Monochrome
Input signal presence or absence (*2)
bit 6
UNDEF
Un_define bit
R
[0] : Input signal detected
[1] : No input signal detected
bit 7
FIXED
Input Video Standard
fixed bit
R
Input signal detection phase (*3)
[0] : Input signal search in progress
[1] : Input signal search complete
(*1) Monochrome auto detection is enabled if the color killer setting is ON(COLKILL-bit = [1]).
ST_BW-bit changes to [1] when the color killer operates.
If the user has deliberately entered the B/W-bit setting Sub Address 0x01, input signal detection
is limited to 525/625 line detection, and only the ST_VLF information is relevant.
(*2) Shows results of input signal detection.
If an input signal is detected, the value is [0]; if no input signal is detected, the value is [1].
(*3) Shows the operating phase of the automatic input signal detector.
The value is [0] while the detection operation is in progress, and [1] when it is completed;
thus, when UNDEF-bit = [1], FIXED-bit = [0].
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The VBI information storage registers are as follows.
Closed Caption 1 Register
bit 7
bit 6
bit 5
bit 4
bit 3
CC7
CC6
CC5
CC4
CC3
Closed Caption 2 Register
bit 7
bit 6
bit 5
CC15
CC14
CC13
WSS 1 Register
bit 7
bit 6
G2-7
G2-6
bit 4
CC12
bit 5
G2-5
bit 4
EXT4
Extended Data 2 Register
bit 7
bit 6
bit 5
EXT15
EXT14
EXT13
VBID 2 Register
bit 7
bit 6
VBID7
VBID8
bit 5
VBID9
bit 4
G4-12
bit 5
VBID1
bit 4
VBID10
bit 3
G4-11
bit 3
EXT11
bit 4
VBID2
bit 3
VBID3
bit 3
VBID11
MS1189-E-01
bit 0
CC0
bit 1
CC9
bit 2
G1-2
bit 3
EXT3
bit 4
EXT12
bit 1
CC1
bit 2
CC10
bit 3
G1-3
bit 5
G4-13
Extended Data 1 Register
bit 7
bit 6
bit 5
EXT7
EXT6
EXT5
VBID 1 Register
bit 7
bit 6
Reserved
Reserved
bit 3
CC11
bit 4
G2-4
WSS 2 Register
bit 7
bit 6
Reserved
Reserved
bit 2
CC2
bit 1
G1-1
bit 2
G3-10
bit 2
EXT2
bit 0
CC8
bit 0
G1-0
bit 1
G3-9
bit 1
EXT1
bit 0
G3-8
bit 0
EXT0
bit 2
EXT10
bit 1
EXT9
bit 0
EXT8
bit 2
VBID4
bit 1
VBID5
bit 0
VBID6
bit 2
VBID12
bit 1
VBID13
bit 0
VBID14
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[AK8857VQ]
7.Device control interface
The AK8857 is controlled via I2C bus control interface, as described below.
[ I2C bus SLAVE Address]
The I2C slave address can be selected by a SELA pin setting of either [1000100] or [1000101].
Slave Address
SELA pin status
Pulldown [Low]
Pullup [High]
MSB
1
1
0
0
0
0
0
0
1
1
0
0
LSB
R/W
R/W
0
1
[I2C Control Sequence ]
(1) Write sequence
After receiving a write-mode slave address first byte, the AK8857 receives the sub-address in the
second byte and data in the subsequent bytes. The write sequence may be single-byte or multi-byte.
(a) Single-byte write sequence
Slave
Sub
S
w A
Address
Address
18-bit
8-bit
bit
A
Data
A
1bit
8-bit
1bit
Stp
(b) Multi-byte write sequence (m-bytes, sequential write operation)
Sub
Slave
Data
S
w A Address A Data(n) A
A
Address
(n+1)
(n)
11118-bit
8-bit
8-bit
8-bit
bit
bit
bit
bit
‘’’’’’’
Data
(n+m)
A
8-bit
1bit
stp
(2) Read sequence
After receiving a read-mode salve address as the first byte, the AK8857 sends data in the second
and subsequent bytes.
Slave
Sub
Slave
Data
S Addres w A Address A rS
R A Data1 A
A Data3 A
Address
2
‘’’‘’
s
(n)
8-bit
1
8-bit
1
8-bit
1
8-bit
1
8-bit
1
8-bit
’‘’’’’‘’’
‘’‘
Data n !A
8-bit
1
stp
1
Symbols and abbreviations
S : Start Condition
rS : repeated Start Condition
A : Acknowledge (SDA Low )
!A : Not Acknowledge (SDA High)
stp : Stop Condition
R/W 1 : Read 0 : Write
: Received from master device (normally microprocessor)
: Output by slave device (AK8857)
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8. Register Definitions
Sub
Register
Address
Default
R/W
Block
Function
0x00
Input Channel Select
0x00
R/W
Common
Input channel setting
0x01
AFE Control
0x01
R/W
Common
Analog front-end setting
0x02
Output Control
0x00
R/W
Common
Output data setting
0x03
Start and Delay Control
0x00
R/W
Common
Output data timing adjustment
0x04
Control 1
0x00
R/W
Common
Control register type
0x05
Control 2
0x00
R/W
Common
Control register type
0x06
Pedestal Level Control
0x00
R/W
Common
Pedestal level adjustment
0x07
Color Killer Control
0x08
R/W
Common
Color killer setting
0x08
Image Control
0x00
R/W
Common
Image control setting
0x09
High Slice Data Set
0xEB
R/W
Common
VBI slicer data high setting
0x0A
Low Slice Data Set
0x10
R/W
Common
VBI slicer data low setting
0x0B
PGA Control 1
0x3E
R/W
Common
PGA1 gain setting
0x0C
PGA Control 2
0x3E
R/W
Common
PGA2 gain setting
0x0D
Output Data Format A
0x00
R/W
A
Output data format setting
0x0E
Input Video Standard A
0x00
R/W
A
Input video signal setting
0x0F
NDMODE A
0x00
R/W
A
Auto detection limit setting
0x10
Output Pin Control 0 A
0x00
R/W
A
Output pin status setting
0x11
Output Pin Control 1 A
0x00
R/W
A
Output pin status setting
0x12
AGC & ACC A Control
0x00
R/W
A
AGC and ACC setting
0x13
Control 0 A
0x00
R/W
A
Control register type
0x14
Contrast Control A
0x80
R/W
A
Contrast adjustment
0x15
Brightness Control A
0x00
R/W
A
Brightness adjustment
0x16
Saturation Control A
0x80
R/W
A
Saturation adjustment
0x17
HUE Control A
0x00
R/W
A
Hue adjustment
0x18
Request VBI Infomation A
0x00
R/W
A
VBI interval decode request
0x19
Status 1 A
R
A
Internal status indicator
0x1A
Status 2 A
R
A
Internal status indicator
0x1B
Reserved
R
A
Reserved
0x1C
Input Video Status A
R
A
Input signal detection indicator
0x1D
Closed Caption 1 A
R
A
Closed caption data indicator
0x1E
Closed Caption 2 A
R
A
Closed caption data indicator
0x1F
WSS 1 A
R
A
WSS data indicator
0x20
WSS 2 A
R
A
WSS data indicator
0x21
Extended Data 1 A
R
A
CC-Extended data indicator
0x22
Extended Data 2 A
R
A
CC-Extended data indicator
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Sub
Address
Register
Default
R/W
Block
Function
0x23
VBID 1 A
R
A
VBID data indicator
0x24
VBID 2 A
R
A
VBID data indicator
0x25
Output Data Format A
0x00
R/W
B
Output data format setting
0x26
Input Video Standard B
0x00
R/W
B
Input video signal setting
0x27
NDMODE B
0x00
R/W
B
Auto detection limit setting
0x28
Output Pin Control 0 B
0x00
R/W
B
Output pin status setting
0x29
Output Pin Control 1 B
0x00
R/W
B
Output pin status setting
0x2A
AGC & ACC B Control
0x00
R/W
B
AGC and ACC setting
0x2B
Control 0 B
0x00
R/W
B
Control register type
0x2C
Contrast Control B
0x80
R/W
B
Contrast adjustment
0x2D
Brightness Control B
0x00
R/W
B
Brightness adjustment
0x2E
Saturation Control B
0x80
R/W
B
Saturation adjustment
0x2F
HUE Control B
0x00
R/W
B
Hue adjustment
0x30
Request VBI Infomation B
0x00
R/W
B
VBI interval decode request
0x31
Status 1 B
R
B
Internal status indicator
0x32
Status 2 B
R
B
Internal status indicator
0x33
Reserved
R
B
Reserved
0x34
Input Video Status B
R
B
Input signal detection indicator
0x35
Closed Caption 1 B
R
B
Closed caption data indicator
0x36
Closed Caption 2 B
R
B
Closed caption data indicator
0x37
WSS 1 B
R
B
WSS data indicator
0x38
WSS 2 B
R
B
WSS data indicator
0x39
Extended Data 1 B
R
B
CC-Extended data indicator
0x3A
Extended Data 2 B
R
B
CC-Extended data indicator
0x3B
VBID 1 B
R
B
VBID data indicator
0x3C
VBID 2 B
R
B
VBID data indicator
0x3D
Device and Revision ID
R
Common
Device ID and revision ID
indicator
For all other registers, write-in is prohibited.
For all reserved registers, write-in must be limited to the default value.
“Common” is Common Register
To R/W register to A block and B block can be done by REGSEL bit setting of Sub-address”0x00”.
For R/W of [Input Channel Select], [PGA Control 1], [PGA Control 2], [Device and Revision ID] register,
REGSEL bit setting is not necessary.
“A” is referred to A block register. “B” is referred to B block register.
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9. Register settings overview
Input Channel Select Register (R/W) [Sub Address 0x00]
Input signal channel selection and clock mode selection register.
Sub Address 0x00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
Default Value: 0x00
Bit 1
bit 0
P1DRV1
P1DRV0
REGSEL
AINSEL4
AINSEL3
AINSEL2
AINSEL1
AINSEL0
0
0
0
0
0
0
0
Default Value
0
Input Channel Select Register Definition
Register
Bit
R/W
Name
bit 0
~
bit 4
AINSEL0
~
AINSEL4
Analog Input
Select
Definition
A block and B lock output video signal selection :
[AINSEL4: AINSEL0]
[00000]: [A]: AIN1(CVBS), [B]: AIN4(CVBS)
[00001]: [A]: AIN1(CVBS), [B]: AIN3(CVBS)
[00010]: [A]: AIN1(CVBS), [B]: AIN2(CVBS)
[00011]: [A]: AIN1(CVBS), [B]: AIN1(CVBS) (*2)
[00100]: [A]: AIN1(CVBS), [B]: Non-decode(*1)
[00101]: [A]: AIN2(CVBS), [B]: AIN4(CVBS)
[00110]: [A]: AIN2(CVBS), [B]: AIN3(CVBS)
[00111]: [A]: AIN2(CVBS), [B]: AIN2(CVBS) (*2)
[01000]: [A]: AIN2(CVBS), [B]: AIN1(CVBS)
[01001]: [A]: AIN2(CVBS), [B]: Non-decode (*1)
[01010]: [A]: AIN3(CVBS), [B]: AIN4(CVBS)
[01011]: [A]: AIN3(CVBS), [B]: AIN3(CVBS) (*2)
[01100]: [A]: AIN3(CVBS), [B]: AIN2(CVBS)
[01101]: [A]: AIN3(CVBS), [B]: AIN1(CVBS)
R/W
[01110]: [A]: AIN3(CVBS), [B]: Non-decode (*1)
[01111]: [A]: AIN4(CVBS), [B]: AIN4(CVBS) (*2)
[10000]: [A]: AIN4(CVBS), [B]: AIN3(CVBS)
[10001]: [A]: AIN4(CVBS), [B]: AIN2(CVBS)
[10010]: [A]: AIN4(CVBS), [B]: AIN1(CVBS)
[10011]: [A]: AIN4(CVBS), [B]: Non-decode (*1)
[10100]: [A]: Non-decode, [B]: AIN4(CVBS) (*1)
[10101]: [A]: Non-decode, [B]: AIN3(CVBS) (*1)
[10110]: [A]: Non-decode, [B]: AIN2(CVBS) (*1)
[10111]: [A]: Non-decode, [B]: AIN1(CVBS) (*1)
[11000]: [A]: AIN1(Y) / AIN3(C), [B]: Non-decode (*1, *2)
[11001]: [A]: AIN1(Y) / AIN3(C), [B]: AIN1(Y) / AIN3(C) (*1, *2)
[11010]: [A]: AIN2(Y) / AIN4(C), [B]: Non-decode (*1, *2)
[11011]: [A]: AIN2(Y) / AIN4(C), [B]: AIN2(Y) / AIN4(C) (*1, *2)
[11100]: [A]: Non-decode, [B]: AIN1(Y) / AIN3(C) (*1, *2)
[11101]: [A]: Non-decode, [B]: AIN2(Y) / AIN4(C) (*1, *2)
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bit 5 REGSEL
bit 6
~
bit 7
P1DRV0
~
P1DRV1
Register
Select
Common register setting method selection (*2)
R / W [0]: A block : Write/ Read enable
[1]: B block : Write/ Read enable
PVDD1
Drive
The digital P1 output pin buffer drive setting is set according
to PVDD1 input voltage setting.(*3)
[P1DRV1: P1DRV0]
R / W [00]: PVDD1 = 3.0 ~ 3.6V
[01]: PVDD1 = 2.3 ~ 2.7V
[10]: Reserved
[11]: PVDD1 = 1.7 ~ 2.0V
(*1) If [Non-decode] is select at the output block, the output pins will be in powersave mode and the
internal digital circuit operational is stop. This will save the power consumption.
(*2) If the output of A block and B block is selected from the same channel of input video signal, the
setting of Sub-address0x01 [AFE Control Register] register only enable if REGSEL=[0] and
disable if REGSEL=[1].
During S-video signal decode, the output block register setting is enable if REGSEL=[0] and
disable if REGSEL=[1].
(*3) Digital P1 pin: DATA_A[7:0], HD_ACT_A, VD_ACT_A, DVALID_A, FIELD_A,
DATA_B[7:0], HD_ACT_B, VD_ACT_B, DVALID_B, FIELD_B, DTCLK pin.
MS1189-E-01
2010/12
-75-
[AK8857VQ]
AFE Control Register (R/W) [Sub Address 0x01] (Common Register)
Analog front end register setting.
R/W block is depends on REGSEL setting of Sub-Address “0x00”.
Sub Address 0x01
Default Value : 0x01
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
CLPWIDTH1
CLPWIDTH0
CLPSTAT1
CLPSTAT0
UDG1
UDG0
CLPG1
CLPG0
0
0
0
0
0
0
1
Default Value
0
AFE Control Register 1 Definition
Bit Register Name
R/W
Definition
Set the current value of fine clamp in analog
block
bit 0 CLPG 0
[00]: Min.
~
~
Clamp Gain
R/W
[01]: Middle 1 (Default)
bit 1 CLPG1
[10]: Middle 2
[11]: Max
Set the current value of rough clamp in analog
block.
bit 2 UDG 0
[00]: Min. (Default)
~
~
Up Down Gain
R/W
[01]: Middle 1
bit 3 UDG 1
[10]: Middle 2
[11]: Max
Set the position of clamp pulse
[ CLPSTAT1 : CLPSTAT0 ]
bit 4 CLPSTAT0
[00] : Center of horizontal sync
~
~
Clamp Start
R/W
[01] : (1/128) H delay
bit 5 CLPSTAT1
[10] : (2/128) H advance
[11] : (1/128) H advance
Set the width of clamp pulse.
[ CLPWIDTH1 : CLPWIDTH0 ]
bit 6 CLPWIDTH0
[00] : 296nsec
~
~
Clamp Pulse Width R / W
[01] : 593nsec
bit 7 CLPWIDTH1
[10] : 1.1usec
[11] : 2.2usec
If the output of A block and B block is selected from the same channel of input video signal, the setting
of Sub-address0x01 [AFE Control Register] register only enable if REGSEL=[0] and disable if
REGSEL=[1].
During S-video signal decode, the output block register setting is enable if REGSEL=[0] and disable if
REGSEL=[1].
MS1189-E-01
2010/12
-76-
[AK8857VQ]
Output Control Register (R/W) [Sub Address 0x02] (Common register)
Output data setting register.
R/W block is depends on REGSEL setting of Sub-Address “0x00”.
Sub Address 0x02
bit 7
bit 6
VBIDEC1
VBIDEC0
Default Value
0
0
bit 5
SLLVL
bit 4
TRSVSEL
bit 3
601LIMIT
Default Value: 0x00
bit 2
bit 1
bit 0
VBIL2
VBIL1
VBIL0
0
0
0
0
Output Format Register Definition
Bit
Register Name
0
0
R/W
Definition
VACT signal active starting position adjustment.
[ VBIL2 : VBIL0 ]
[000]: Default
[001]: 1Line (2Line*) advance
bit 0 VBIL0
Vertical Blanking
[010]: 2Line (4Line*) advance
~
~
R/W
Length
[011]: 3Line (6Line*) advance
bit 2 VBIL2
[100]: 4Line (8Line*) advance
[101]: 5Line (10Line*) advance
[110]: 6Line (12Line*) advance
[111]: 7Line (14Line*) advance
Output data code limit (Min-Max) setting
bit 3 601LIMIT
601 Output Limit
R/W [0] : 1-254 (Y/Cb/Cr)
[1] : 16-235 (Y) /16-240 (Cb/Cr)
Setting of lines for “Time reference signal” V-bit
value change in ITU-R BT.656 format
With 525-line input
Setting [0]: V=1 (lines 1~9 and 264~272)
V=0 (lines 10~263 and 273~525)
Time Reference
bit 4 TRSVSEL
R/W
Setting [1]: V=1 (lines 1~19 and 264~282)
Signal V Select
V=0 (lines 20~263 and 283~525)
With 625-line input
Always (regardless of setting in this register):
V=1 (lines 1~22 and 311~335)
V=0 (lines 23~310 and 336~623)
Slice level setting
bit 5 SLLVL
Slice Level
R/W [0] : Slice level approx. 25 IRE
[1] : Slice level approx. 50 IRE
Setting for type of data output during interval set in
Vertical Blanking Interval register *
bit 6 VBIDEC0
[ VBIDEC1 : VBIDEC0 ]
~
~
VBI Decode
R/W [00] : Black level data output
bit 7 VBIDEC1
[01] : Monochrome data output
[10] : Slice result data output
[11] : Reserved
*Only support progressive output size of ITU-R BT.601, VGA, WVGA format.
MS1189-E-01
2010/12
-77-
[AK8857VQ]
Start and Delay Control Register (R/W) [Sub Address 0x03] (Common register)
Output data timing adjustment register.
R/W block is depends on REGSEL setting of Sub-Address “0x00”.
Sub Address 0x03
bit 7
bit 6
Default Value : 0x00
bit 5
bit 4
bit 3
VLOCKSEL ACTSTA2 ACTSTA1 ACTSTA0 Reserved
bit 2
bit 1
bit 0
YCDELAY2 YCDELAY1 YCDELAY0
Default Value
0
0
0
0
Start and Delay Control Register Definition
Bit
Register Name
0
R/W
bit 0
~
bit 2
YCDELAY0
~
YCDELAY2
Y/C Delay Control
R/W
bit 3
Reserved
Reserved
R/W
bit 4
~
bit 6
ACTSTA0
~
ACTSTA2
Active Video Start
Control
R/W
bit 7
VLOCKSEL
Vlock Select
R/W
MS1189-E-01
0
0
0
Definition
Adjustment of Y and C timing.
[ YCDELAY2 : YCDELAY0 ]
[001] : Y advance 1sample toward C.
[010] : Y advance 2sample toward C.
[011] : Y advance 3sample toward C.
[000] : No Delay and advance.
[101] : Y delay 3 sample toward C.
[110] : Y delay 2 sample toward C.
[111] : Y delay 1 sample toward C.
[100] : Reserved
Reserved
Fine-tuning video data decode start position by
delay or advance in 1-sample units.
[ACTSTA2: ACTSTA0]
[001]: 1-sample delay
[010]: 2-sample delay
[011]: 3-sample delay
[000]: Normal start position
[101]: 3-sample advance
[110]: 2-sample advance
[111]: 1-sample advance
[100]: Reserved
Select of internal operation with the input signal
frame structure
[0]: PLL SYNC VLOCK
[1]: Direct SYNC VLOCK
2010/12
-78-
[AK8857VQ]
Control 1 Register (R/W) [Sub Address 0x04] (Common register)
Control register setting.
R/W block is depends on REGSEL setting of Sub-Address “0x00”.
Sub Address 0x04
Default Value: 0x00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Reserved
EAVSAV
CLKINV
INTPOLOFF Reserved
UVFILSEL YCSEP1
YCSEP0
0
0
0
0
Default Value
0
0
Control 1 Register Definition
Bit
Register Name
0
R/W
bit 0
~
bit 1
YCSEP0
~
YCSEP1
YC Separation
Control
R/W
bit 2
UVFILSEL
UV Filter Select
R/W
bit 3
Reserved
Reserved
R/W
bit 4
INTPOLOFF
Interpolator Mode
Select
R/W
bit 5
CLKINV
CLK Invert Set
R/W
bit 6
EAVSAV
EAV/ SAV SELECT
R/W
bit 7
Reserved
Reserved
R/W
0
Definition
Y/C separation setting
[ YCSEP1 : YCSEP0 ]
[00] : Adaptive Y/C separation
[01] : 1-dimensional Y/C separation
[10] : 2-dimensional Y/C separation
[11] : Reserved
UV filter setting
[0]: Wide
[1]: Narrow
Reserved
Pixel interpolator setting
[0]: ON
[1]: OFF
DTCLK signal output polarity selection
[0] : Normal output
(write in data at rising edge)
[1] : Data and clock reversed
(write in data at falling edge)
EAV/SAV sync code add setting
[0]: Sync code is added
[1]: not added.
Reserved
MS1189-E-01
2010/12
-79-
[AK8857VQ]
Control 2 Register (R/W) [Sub Address 0x05] (Common register)
Control register setting.
R/W block is depends on REGSEL setting of Sub-Address “0x00”.
Sub Address 0x05
Default Value : 0x00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
CKILSEL
STUPATOFF
Reserved
Reserved
Reserved
Reserved
DPAL1
DPAL0
0
0
0
0
0
0
Default Value
0
0
Control 2 Register Definition
Bit
Register Name
bit 0 DPAL0
~
~
bit 1 DPAL1
Deluxe PAL
bit 2
~ Reserved
bit 5
Reserved
bit 6 STUPATOFF
Setup Auto Control Off
bit 7 CKILSEL
Color killer Select
R/W Definition
Setting for color averaging*
(PAL phase correction block)
[ DPAL1 : DPAL0 ]
R/W [00] : Adaptive phase correction ON
[01] : Phase correction ON
[10] : Phase correction OFF
[11] : Reserved
R/W Reserved
Setup auto switching setting (ON/OFF) in auto
signal detection mode
R/W
[0] : Auto setup switching ON
[1] : Auto setup switching OFF
Color killer activation setting
[0] : Activation when burst color level is below
R/W
CKLVL[3:0]-bits threshold setting
[1] : Activation when burst color level is below
CKLVL[3:0]-bits threshold setting or
color decode PLL lock fails
MS1189-E-01
2010/12
-80-
[AK8857VQ]
Pedestal Level Control Register (R/W) [Sub Address 0x06] (Common register)
Pedestal level adjustment setting register.
R/W block is depends on REGSEL setting of Sub-Address “0x00”.
Sub Address 0x06
Default Value : 0x00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DPCC1
DPCC0
DPCT1
DPCT0
BKLVL3
BKLVL2
BKLVL1
BKLVL0
0
0
0
0
0
0
Default Value
0
0
Pedestal Level Control Register Definition
Bit
Register Name
R/W
bit 0
~
bit 3
BKLVL0
~
BKLVL3
Black Level
R/W
bit 4
~
bit 5
DPCT0
~
DPCT1
Digital Pedestal Clamp
Control
R/W
bit 6
~
bit 7
DPCC0
~
DPCC1
Digital Pedestal Clamp
Coring Control
R/W
MS1189-E-01
Definition
Setting for change from current pedestal
level by adding to or subtracting from black
level
[ BKLVL3 : BKLVL0 ]
[0001] : Add 1
[0010] : Add 2
[0011] : Add 3
[0100] : Add 4
[0101] : Add 5
[0110] : Add 6
[0111] : Add 7
[0000] : Default
[1000] : Subtract 8
[1001] : Subtract 7
[1010] : Subtract 6
[1011] : Subtract 5
[1100] : Subtract 4
[1101] : Subtract 3
[1110] : Subtract 2
[1111] : Subtract 1
Time-constant setting for digital pedestal
clamp
[ DPCT1 : DPCT0 ]
[00] : Fast
[01] : Middle
[10] : Slow
[11] : Disable
Non-sensing bandwidth setting for digital
pedestal clamp
[ DPCC1 : DPCC0 ]
[00] : ±1bit
[01] : ±2bit
[10] : ±3bit
[11] : No non-sensing band
2010/12
-81-
[AK8857VQ]
Color Killer Control Register (R/W) [Sub Address 0x07] (Common register)
Color killer setting register
R/W block is depends on REGSEL setting of Sub-Address “0x00”.
Sub Address 0x07
Default Value : 0x08
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
COLKILL
CONTSEL
CKSCM1
CKSCM0
CKLVL3
CKLVL2
CKLVL1
CKLVL0
0
0
0
1
0
0
0
Default Value
0
Color Killer Control Register Definition
Bit
Register Name
bit 0 CKLVL0
~
~
Color Killer Level Control
bit 3 CKLVL3
bit 4 CKSCM0
Color Killer Level for
~
~
SECAM
bit 5 CKSCM1
R/W
Definition
R/W
Burst level setting for color killer activation
Default value, approx. −23 dB
R/W
Burst level setting for color killer activation in
SECAM mode
Adds 2 bits to CKLVL[3:0]
bit 6
CONTSEL
Contrast Select
R/W
bit 7
COLKILL
Color killer Set
R/W
MS1189-E-01
Contrast selector
[0] : toward luminance of 128
[1] : toward luminance of 0
Color killer ON/OFF setting
[0] : Enable
[1] : Disable
2010/12
-82-
[AK8857VQ]
Image Control Register (R/W) [Sub Address 0x08] (Common register)
Sharpness control, Luminance bandwidth filter control, Sepia color output setting and VBI interval
setting register.
R/W block is depends on REGSEL setting of Sub-Address “0x00”.
Sub Address 0x08
Default Value : 0x00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
VBIIMGCTL
SEPIA
LUMFIL1
LUMFIL0
SHCORE1
SHCORE0
SHARP1
SHARP0
0
0
0
0
0
0
0
Default Value
0
Image Control Register Definition
Bit
Register Name
R/W
bit 0
~
bit 1
SHARP0
~
SHARP1
bit 2
~
bit 3
SHCORE0
~
SHCORE1
Sharpness Coring
R/W
bit 4
~
bit 5
LUMFIL0
~
LUMFIL1
Luminance Filter
R/W
bit 6
SEPIA
Sepia Output
R/W
bit 7
VBIIMGCTL
VBI Image Control
R/W
Sharpness Control
R/W
Definition
Sharpness control (filter effect) setting
[ SHARP1 : SHARP0 ]
[00] : No filtering
[01] : Min effect
[10] : Middle effect
[11] : Max effect
Setting for level of coring after passage through
sharpness filter
Enabled except with [SHARP1:SHARP0]
register setting of [00]
[ SHCORE1 : SHCORE0 ]
[00] : No coring
[01] : ±1LSB
[10] : ±2LSB
[11] : ±3LSB
Setting for luminance band limit filter
[ LUMFIL1 : LUMFIL0 ]
[00] : No filtering
[01] : Narrow
[10] : Mid
[11] : Wide
Setting (ON/OFF) for sepia coloring of decode
results *
[0]: Normal output
[1]: Sepia output
Setting (ON/OFF) for image adjustment during
brightness and contrast adjustment VBI*
[0]: Image adjustment inactive during VBI
[1]: Image adjustment active during VBI
* DOA register of Sub-address “0x10” and DOB register of Sub-address “0x28” setting takes priority
regardless to above SEPIA register setting.
MS1189-E-01
2010/12
-83-
[AK8857VQ]
High Slice Data Set Register (R/W) [Sub Address 0x09] (Common register)
Register for setting sliced data from VBI slicer to High value (Default code is 235).
R/W block is depends on REGSEL setting of Sub-Address “0x00”.
Sub Address 0x09
Default Value : 0xEB
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
H7
H6
H5
H4
H3
H2
H1
H0
1
0
1
0
1
1
Default Value
1
1
High Slice Data Set Register Definition
Bit
Register Name
bit 0
~
bit 7
H0
~
H7
R/W
High Data 0~7 Set
R/W
Definition
Register for setting sliced data from VBI slicer to
High value (Default code is 235)
Important: Corresponds to 601 special code if set
to 0x00 or 0xFF
Low Slice Data Set Register (R/W) [Sub Address 0x0A] (Common register)
Register for setting sliced data from VBI slicer to Low value (Default code is 16)
R/W block is depends on REGSEL setting of Sub-Address “0x00”.
Sub Address 0x0A
Default Value : 0x10
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
L7
L6
L5
L4
L3
L2
L1
L0
0
1
0
0
0
0
Default Value
0
0
Low Slice Data Set Register Definition
Bit
Register Name
bit 0
~
bit 7
L0
~
L7
R/W
Low Data 0~7 Set
R/W
Definition
Register for setting sliced data from VBI slicer to
Low value (Default code is 16)
Important: Corresponds to 601 special code if set
to 0x00 or 0xFF
MS1189-E-01
2010/12
-84-
[AK8857VQ]
PGA Control 1 Register (R/W) [Sub Address 0x0B]
PGA1 control register
In case of CVBS signal decode, its control the gain setting for A block output.
In case of S-Videosignal decode, its control the gain setting for Y signal output.
Sub Address 0x0B
Default Value : 0x1F
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PGA1_7
PGA1_6
PGA1_5
PGA1_4
PGA1_3
PGA1_2
PGA1_1
PGA1_0
Default Value
0
0
1
1
1
1
1
0
PGA Control 1 Register Definition
Bit
Register Name
bit 0
~
bit 7
PGA1_0
~
PGA1_7
PGA1 Gain Set
R/W
Definition
R/W
PGA gain setting, in steps of approx. 0.1 dB
*1 When CVBS signal decode, if the output of A block and B block is the same video signal, only
PGA1 control register is enable and PGA2 control register is disable.
*2 When CVBS signal decode, if the output block is selected to [non-decode], the gain setting is set
to “0x00” value.
PGA Control 2 Register (R/W) [Sub Address 0x0C]
PGA2 control register
In case of CVBS signal decode, its control the gain setting for B block output.
In case of S-Videosignal decode, its control the gain setting for C signal output.
Sub Address 0x0C
Default Value : 0x1F
bit 7
Bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PGA2_7
PGA2_6
PGA2_5
PGA2_4
PGA2_3
PGA2_2
PGA2_1
PGA2_0
Default Value
0
0
1
1
1
1
1
0
PGA Control 2 Register Definition
Bit
Register Name
R/W
Definition
bit 0
PGA2_0
~
~
PGA2 Gain Set
R/W
PGA gain setting, in steps of approx. 0.1 dB
bit 7
PGA2_7
*1 When CVBS signal decode, if the output of A block and B block is the same video signal, only PGA1
control register is enable and PGA2 control register is disable.
*2 When CVBS signal decode, if the output block is selected to [non-decode], the gain setting is set to
“0x00” value.
MS1189-E-01
2010/12
-85-
[AK8857VQ]
Output Data Format A Register (R/W) [Sub Address 0x0D] (A block register)
Output Data Format A Register (R/W) [Sub Address 0x25] (B block register)
Output Data format setting register.
This register is applied to set the A block output data.
Sub Address 0x0D, 0x25
bit 7
bit 6
Default Value: 0x00
bit 5
Reserved Reserved Reserved
bit 4
bit 3
bit 2
bit 1
bit 0
ODEVA ODFORMA3 ODFORMA2 ODFORMA1 ODFORMA0
ODEVB ODFORMB3 ODFORMB2 ODFORMB1 ODFORMB0
Default Value
0
0
0
0
Output Data Format A Register Definition
Bit
Register Name
0
R/W
bit 0
~
bit 3
ODFORMA/B0
~
ODFORMA/B3
Output Data
Format_A/B
R/W
bit 4
ODEVA/B
ODD EVEN
Select_A/B
R/W
bit 5
~
bit 7
Reserved
Reserved
R/W
0
0
0
Definition
Output data format selection :
[ODFORMA/B3: ODFORMA/B0]
[0000] : 601 (Interlace)
(525 line : 720x487)
(625 line : 720x576)
[0001] : 601 (Progressive, 60frm/s)
(525 line : 720x487)
(625 line : 720x576)
[0010] : 601 (Progressive, 30frm/s)
(525 line : 720x487)
(625 line : 720x576)
[0011]: WVGA (Interlace) (800x480)
[0100]: WVGA (Progressive, 60frm/s) (800x480)
[0101]: WVGA (Progressive, 30frm/s) (800x480)
[0110]: VGA (Interlace) (640x480)
[0111]: VGA (Progressive, 60frm/s) (640x480)
[1000]: VGA (Progressive, 30frm/s) (640x480)
[1001]: WQVGA (Progressive, 30frm/s) (400x240)
[1010]: QVGA (Progressive, 30frm/s) (320x240)
[1011]: EGA (Progressive, 30frm/s) (400x234)
[1100]: WEGA1 (Progressive, 30frm/s) (480x240)
[1101]: WEGA2 (Progressive, 30frm/s) (480x234)
Decode field selection during (Progressive,
30frm/s) output.
[0]: ODD FIELD
[1]: EVEN FIELD
Reserved
MS1189-E-01
2010/12
-86-
[AK8857VQ]
Input Video Standard A Register (R/W) [Sub Address 0x0E] (A Block Register)
Input Video Standard A Register (R/W) [Sub Address 0x26] (B Block Register)
This register is applied to set the analog input signal.
Sub Address 0x0E, 0x26
Default Value: 0x00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
AUTODETA
SETUPA
BWA
VLFA
VCENA1
VCENA0
VSCFA1
VSCFA0
AUTODETB
SETUPB
BWB
VLFB
VCENB1
VCENB0
VSCFB1
VSCFB0
0
0
0
0
0
0
0
Default Value
0
Input Video Standard A/B Register Definition
Bit
Register Name
R/W Definition
Input video signal subcarrier frequency setting
[VSCFA/B 1 : VSCFA/B 0 ] ( MHz )
bit 0 VSCFA/B 0
[00] : 3.57954545 (NTSC-M,J)
Video Sub-Carrier
~
~
R/W [01] : 3.57561149 (PAL-M)
Frequency_A/B
bit 1 VSCFA/B 1
[10] : 3.58205625 (PAL-Nc)
[11] : 4.43361875
(PAL-B,D,G,H,I,N,60,NTSC-4.43, SECAM)*1
Input signal color encode format setting
[VCENA/B 1 : VCENA/B 0]
bit 2 VCENA/B 0
Video Color
[00] : NTSC
~
~
R/W
Encode_A/B
[01] : PAL
bit 3 VCENA/B 1
[10] : SECAM
[11] : Reserved
Input signal line frequency setting
Video Line
bit 4 VLFA/B
R/W [0] : 525 line (NTSC-M,J , NTSC-4.43 , PAL-M,60)
Frequency_A/B
[1] : 625 line (PAL-B,D,G,H,I,N , PAL-Nc , SECAM)
Monochrome mode (ON/OFF) setting *2
Black
&
bit 5 BWA/B
R/W [0] : Monochrome mode OFF
White_A/B
[1] : Monochrome mode ON
Setup process setting
bit 6 SETUPA/B
Setup_A/B
R/W [0] : Process as input signal with no setup
[1] : Process as input signal with setup
Input signal auto detection setting *3
[0]: OFF (auto detection disabled; set manually)
Video Standard
bit 7 AUTODETA/B
R/W
[1]: ON (auto detection enabled)
Auto Detect_A/B
*1 For SECAM input signal, change VSCF[1:0] setting to [11].
*2 DOA register of Sub-address “0x10” and DOB register of Sub-address “0x28” setting takes priority
regardless to above BW register setting.
3
* “Auto detection function” must not use when it is being operated on Direct SYNC VLOCK
(Sub-Address0x03[7]=1).
MS1189-E-01
2010/12
-87-
[AK8857VQ]
NDMODE A Register (R/W) [Sub Address 0x0F] (A block register)
NDMODE B Register (R/W) [Sub Address 0x27] (B block register)
For limiting auto input video signal detection candidates of A block output data.
Sub Address 0x0F, 0x27
bit 7
bit 6
Default Value: 0x00
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
ND625LA ND525LA NDPAL60A NDNT443A Reserved NDSECAMA NDPALNCA NDPALMA
ND625LB ND525LB NDPAL60B NDNT443B Reserved NDSECAMB NDPALNCB NDPALMB
Default Value
0
0
0
0
0
NDMODE A/B Register Definition
Bit
Register Name
0
0
R/W
Definition
0
bit 0
NDPALMA/B
No Detect PAL-M_A/B
R/W
[0] : PAL-M candidate
[1] : PAL-M non-candidate
bit 1
NDPALNCA/B
No Detect PAL-Nc_A/B
R/W
[0] : PAL-Nc candidate
[1] : PAL-Nc non-candidate
bit 2
NDSECAMA/B
No Detect SECAM_A/B
R/W
[0] : SECAM candidate
[1] : SECAM non-candidate
bit 3
Reserved
Reserved
R/W
Reserved
bit 4
NDNT443A/B
R/W
[0] : NTSC-4.43 candidate
[1] : NTSC-4.43 non-candidate
bit 5
NDPAL60A/B
No Detect PAL-60_A/B
R/W
[0] : PAL-60 candidate
[1] : PAL-60 non-candidate
bit 6
ND525LA/B
No Detect 525Line_A/B
R/W
[0] : 525 line candidate
[1] : 525 line non-candidate
bit 7
ND625LA/B
No Detect 625Line_A/B
R/W
[0] : 625 line candidate
[1] : 625 line non-candidate
No Detect
NTSC-4.43_A/B
In making the above register settings, the following restrictions are apply,
[1] Setting both NDNT443A/B (bit 4) and NDPAL60A/B (bit 5) to [1] (High) is prohibited.
[2] Setting both ND525LA/B (bit 6) and ND625LA/B (bit 7) to [1] (High) is prohibited.
[3] To limit candidate formats, it is necessary to have the auto detection mode OFF while first setting
the register to non-limited signal status and next the NDMODE settings, and then setting the auto
detection mode to ON.
MS1189-E-01
2010/12
-88-
[AK8857VQ]
Output Pin Control 0 A Register (R/W) [Sub Address 0x10] (A block register)
Output Pin Control 0 B Register (R/W) [Sub Address 0x28] (B block register)
A block output pin output status setting
Sub Address 0x10, 0x28
bit 7
Reserved
Default Value: 0x00
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
FLA
NLA
DVALIDLA
VDACTLA
DOA1
FLB
HDACTLA
HDACTLB
NLB
DVALIDLB
VDACTLB
DOB1
DOA0
DOB0
0
0
0
0
0
0
0
Default Value
0
Output Control 0 A/B Register Definition
Bit
Register Name
R/W
bit 0
~
bit 1
DOA/B 0
~
DOA/B 1
Data Output _A/B
R/W
bit 2
VDACTLA/B
VD/ VACT Low_A/B
R/W
bit 3
DVALIDLA/B
DVALID Low_A/B
R/W
bit 4
NLA/B
NSIG Low_A/B
R/W
bit 5
HDACTLA/B
HD/HACT Low_A/B
R/W
bit 6
FLA/B
FIELD_A/B
R/W
bit 7
Reserved
Reserved
R/W
Definition
[00]: Normal output
[01]: DATA_A/B [7: 0] pin output fixed at Low
[10]: Black level output
[11]: Blue level output
[0] : Normal output
[1]: VD_ACT_A/B pin output fixed at low.
[0] : Normal output
[1]: DVALID_A/B pin output fixed at low.
[0] : Normal output
[1] : NSIG_A/B pin output fixed at low
[0] : Normal output
[1]: HD_ACT_A/B pin output fixed at low.
[0] : Normal output
[1] : FIELD_A/B pin output fixed at low
Reserved
Note: Output control via pins OE_A, OE_B, PDN, RSTN and AINSEL[4:0] (Non-decode) takes priority,
regardless of the above settings.
MS1189-E-01
2010/12
-89-
[AK8857VQ]
Output Pin Control 1 A Register (R/W) [Sub Address 0x11] (A block register)
Output Pin Control 1 B Register (R/W) [Sub Address 0x29] (B block register)
A block output pin status setting register.
Sub Address 0x11, 0x29
bit 7
bit 6
Reserved
Reserved
Default Value : 0x00
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
HDACTSELA
VDACTSELA
FIELDA
DVALIDA
VDACTA
HDACTSELB
VDACTSELB
FIELDB
DVALIDB
VDACTB
HDACTA
HDACTB
0
0
0
0
0
0
Default Value
0
0
Output Control 1 A/B Register Definition
Bit
Register Name
R/W
bit 0
HDACTA/B
HD_ACT_A/B Pin
Polarity
R/W
bit 1
VDACTA/B
VD_ACT_A/B Pin
Polarity
R/W
bit 2
DVALIDA/B
DVALID_A/B Pin
Polarity
R/W
bit 3
FIELDA/B
FIELD_A/B Pin Polarity
R/W
bit 4
VDACTSELA/B
VD/ VACT Select_A/B
R/W
bit 5
HDACTSELA/B
HD/ HACT Select_A/B
R/W
bit 6
~
bit 7
Reserved
Reserved
R/W
Definition
HD_ACT_A/B pin output polarity setting.
[0] : Active Low
[1] : Active High
VD_ACT_A/B pin output polarity setting.
[0]: Active Low
[1]: Active High
DVALID_A/B pin output polarity setting.
[0]: Active Low
[1]: Active High
FIELD_A/B pin output polarity setting.
[0]: Active Low
[1]: Active High
VD_ACT_A/B pin output signal selection :
[0] : VD signal is output.
[1] : VACT signal is output.
HD_ACT_A/B pin output signal selection :
[0] : HD signal is output.
[1] : HACT signal is output.
Reserved
Note: Output control via pins OE_A, OE_B, PDN and RSTN takes priority, regardless of the above
settings.
MS1189-E-01
2010/12
-90-
[AK8857VQ]
AGC & ACC A Control Register (R/W) [Sub Address 0x12] (A block register)
AGC & ACC B Control Register (R/W) [Sub Address 0x2A] (B block register)
AGC and ACC setting register.
Sub Address 0x12, 0x2A
Default Value : 0x00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
ACCFRZA
ACCA1
ACCA0
AGCFRZA
AGCCA1
AGCCA0
AGCTA1
AGCTA0
ACCFRZB
ACCB1
ACCB0
AGCFRZB
AGCCB1
AGCCB0
AGCTB1
AGCTB0
0
0
0
0
0
0
0
Default Value
0
AGC & ACC A/B Control Register Definition
Bit
Register Name
R/W
bit 0
~
bit 1
AGCTA/B 0
~
AGCTA/B 1
AGC Time Constant_A/B
R/W
bit 2
~
bit 3
AGCCA/B 0
~
AGCCA/B 1
AGC Coring Control_A/B
R/W
Definition
AGC time constant (T) setting*
(if disabled, PGA can be set manually)
[ AGCT1 : AGCT0 ]
[00] : Disable
[01] : Fast [ T = 1Field ]
[10] : Middle [ T =7Fields ]
[11] : Slow [ T = 29Fields ]
AGC non-sensing bandwidth (LSB) setting
[ AGCC1 : AGCC0 ]
[00] : ±2LSB
[01] : ±3LSB
[10] : ±4LSB
[11] : No non-sensing band
AGC freeze function (ON/OFF) setting
bit 4
AGCFRZA/B
AGC Freeze_A/B
R/W
bit 5
~
bit 6
ACCTA/B 0
~
ACCTA/B 1
ACC Time Constant_A/B
R/W
bit 7
ACCFRZA/B
ACC Freeze_A/B
R/W
MS1189-E-01
(AGC set values are saved during freeze)
[0] : Non-frozen
[1] : Frozen
ACC time constant (T) setting
[ ACCT1 : ACCT0 ]
[00] : Disable
[01] : Fast [ T = 2Fields ]
[10] : Middle [ T =8Fields ]
[11] : Slow [ T = 30Fields ]
ACC freeze function (ON/OFF) setting
(ACC set values are saved during freeze)
[0] : Non-frozen
[1] : Frozen
2010/12
-91-
[AK8857VQ]
Control 0 A Register (R/W) [Sub Address 0x13] (A block register)
Control 0 B Register (R/W) [Sub Address 0x2B] (B block register)
Sub Address 0x13, 0x2B
bit 7
Reserved
bit 6
Default Value: 0x00
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
NSIGMDA1 NSIGMDA0 C443FILA1 C443FILA0 C358FILA1 C358FILA0 AGCTLA
NSIGMDB1 NSIGMDB0 C443FILB1 C443FILB0 C358FILB1 C358FILB0 AGCTLB
Default Value
0
0
0
0
0
0
0
0
Control 0 A/B Register Definition
Bit
Register Name
bit 0 AGCTLA/B
bit 1 C358FILA/B 0
~
~
bit 2 C358FILA/B 1
bit 3 C443FILA/B 0
~
~
bit 4 C443FILA/B 1
bit 5 NSIGMDA/B 0
~
~
bit 6 NSIGMDA/B 1
bit 7 Reserved
R/W Definition
Transition speed setting, between
peak AGC and sync AGC
AGC Transition Level_A/B
R/W
[0] : Quick
[1] : Slow
C-filter bandwidth setting, for 3.58 MHz
subcarrier system signal
[C358FILA/B 1 : C358FILA/B 0 ]
C Filter_358 Select_A/B
R/W [00] : 3.58 Narrow
[01] : 3.58 Medium
[10] : 3.58 Wide
[11] : Reserved
C-filter bandwidth setting, for 4.43 MHz
subcarrier system signal
[C443FILA/B 1 : C443FILA/B 0 ]
C Filter_443 Select_A/B
R/W [00] : 4.43 Narrow
[01] : 4.43 Medium
[10] : 4.43 Wide
[11] : Reserved
Setting for output on no-signal detection *
[NSIGMDA/B 1 : NSIGMDA/B 0]
[00] : Black-level output
No Signal Output Mode_A/B R/W
[01] : Blue-level (Blueback) output
[10] : Input status (sandstorm) output
[11] : Reserved
Reserved
R/W Reserved
* DOA/B[1:0] register of Sub-address”0x01/0x28” takes priority regardless to no-signal detection
setting adjustment above when the DOA/B[1:0] register value is set other than [00].
MS1189-E-01
2010/12
-92-
[AK8857VQ]
Contrast Control A Register (R/W) [Sub Address 0x14] (A block register)
Contrast Control B Register (R/W) [Sub Address 0x2C] (B block register)
Contrast adjustment setting register.
Sub Address 0x14, 0x2C
Default Value: 0x80
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
CONTA7
CONTA6
CONTA5
CONTA4
CONTA3
CONTA2
CONTA1
CONTA0
CONTB7
CONTB6
CONTB5
CONTB4
CONTB3
CONTB2
CONTB1
CONTB0
0
0
0
0
0
0
Default Value
1
0
Contrast Control A/B Register Definition
Bit
Register Name
bit 0
~
bit 7
CONTA/B 0
~
CONTA/B 7
Contrast Control_A/B
R/W
Definition
R/W
Register for contrast adjustment in steps of
1/128 in range 1~255/128 from default
value of 0x80
Brightness Control A Register (R/W) [Sub Address 0x15] (A block register)
Brightness Control B Register (R/W) [Sub Address 0x2D] (B block register)
Brightness adjustment setting register
Sub Address 0x15, 0x2D
Default Value: 0x00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
BRA7
BRA6
BRA5
BRA4
BRA3
BRA2
BRA1
BRA0
BRB7
BRB6
BRB5
BRB4
BRB3
BRB2
BRB1
BRB0
0
0
0
0
0
0
Default Value
0
0
Brightness Control A/B Register Definition
Bit
Register Name
bit 0
~
bit 7
BRA/B0
~
BRA/B7
Brightness Control_A/B
R/W
Definition
R/W
Register for brightness adjustment in steps
of 1 by 8-bit code setting in 2’s complement
MS1189-E-01
2010/12
-93-
[AK8857VQ]
Saturation Control A Register (R/W) [Sub Address 0x16] (A block register)
Saturation Control B Register (R/W) [Sub Address 0x2E] (B block register)
Saturation adjustment setting register
Sub Address 0x16, 0x2E
Default Value: 0x80
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SATA7
SATA6
SATA5
SATA4
SATA3
SATA2
SATA1
SATB7
SATB6
SATB5
SATB4
SATB3
SATB2
SATB1
SATA0
SATB0
0
0
0
0
0
0
Default Value
1
0
Saturation Control A/B Register Definition
Bit
Register Name
bit 0
~
bit 7
SATA/B0
~
SATA/B7
Saturation Control_A/B
R/W
Definition
R/W
Register for saturation level adjustment in
steps of 1/128 in range 1~255/128 from
default value of 0x80 (CVBS or S-video input)
HUE Control A Register (R/W) [Sub Address 0x17] (A block register)
HUE Control B Register (R/W) [Sub Address 0x2F] (B block register)
HUE adjustment setting register.
Sub Address 0x17, 0x2F
Default Value : 0x00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
HUEA7
HUEA6
HUEA5
HUEA4
HUEA3
HUEA2
HUEA1
HUEA0
HUEB7
HUEB6
HUEB5
HUEB4
HUEB3
HUEB2
HUEB1
HUEB0
0
0
0
0
0
0
R/W
Definition
Default Value
0
0
HUE Control A/B Register Definition
Bit
Register Name
bit 0
~
bit 7
HUEA/B0
~
HUEA/B7
HUE Control_A/B
R/W
MS1189-E-01
Register for hue adjustment in steps of
1/256 in range ±45° in 2’s complement
2010/12
-94-
[AK8857VQ]
Request VBI Infomation A Register (R/W) [Sub Address 0x18] (A block register)
Request VBI Infomation B Register (R/W) [Sub Address 0x30] (B block register)
Data decode request during VBI interval setting register.
Sub Address 0x18, 0x30
Default Value: 0x00
bit 7
bit 6
bit 5
bit 4
Reserved
Reserved
Reserved
Reserved
0
0
bit 3
bit 2
bit 1
bit 0
WSSRQA
VBIDRQA
EXTRQA
CCRQA
WSSRQB
VBIDRQB
EXTRQB
CCRQB
0
0
0
0
Default Value
0
0
Request VBI Infomation A/B Register Definition
Bit
bit 0
bit 1
bit 2
bit 3
Register Name
CCRQA/B
EXTRQA/B
VBIDRQA/B
WSSRQA/B
R/W
Closed Caption
Decode Request_A/B
R/W
Extended Data
Decode Request_A/B
R/W
VBID Decode Request_A/B
WSS Decode Request_A/B
R/W
R/W
Definition
Setting (ON/OFF) for closed caption
decode request
[0] : No request (OFF)
[1] : Request (ON)
Setting (ON/OFF) for Extended Data
decode request
[0] : No request (OFF)
[1] : Request (ON)
Setting (ON/OFF) for VBID
decode request
[0] : No request (OFF)
[1] : Request (ON)
Setting (ON/OFF) for WSS
decode request
[0] : No request (OFF)
[1] : Request (ON)
bit 4
~
bit 7
Reserved
Reserved
R/W
MS1189-E-01
Reserved
2010/12
-95-
[AK8857VQ]
Status 1 A Register (R) [Sub Address 0x19] (A block register)
Status 1 B Register (R) [Sub Address 0x31] (B block register)
Sub Address 0x19, 0x31
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
OVCOLA
PKWHITEA
Reserved
CPLLA
FRMSTDA
VLOCKA
NOSIGA
OVCOLB
PKWHITEB
Reserved
CPLLB
COLKILONA
COLKILONB
FRMSTDB
VLOCKB
NOSIGB
Status 1 A/B Register Definition
Bit
Register Name
bit 0 NOSIGA/B
bit 1 VLOCKA/B
bit 2 FRMSTDA/B
R/W Definition
No Signal_A/B
Video Locked_A/B
Frame Standard_A/B
bit 3 COLKILONA/B Color Killer_A/B
bit 4 CPLLA/B
Color PLL Lock_A/B
bit 5 Reserved
Reserved
R
Input signal indicator
[0] : Input signal present
[1] : Input signal absent
R
Input signal VLOCK synchronization status
indicator
[0]: Input signal synchronized
[1]: Input signal non-synchronized
R
Input signal interlace status indicator
[0]: Input signal 525/625 interlaced
[1]: Input signal not 525/625 interlaced
Color killer status indicator *1
[0]: Color killer not operation
[1]: Color killer operation
PLL clock locked status indicator
[0]: No locked
[1]: Locked
R
Reserved
R
bit 6 PKWHITEA/B
Peak White Detection_A/B R
bit 7 OVCOLA/B
Over Color Level_A/B
R
MS1189-E-01
Luminance decode result flow status
indicator,after passage through AGC block
[0]: Normal
[1]: Overflow
Color decode result flow status indicator,
after passage through ACC block*2
[0]: Normal
[1]: Overflow (excessive color signal input)
2010/12
-96-
[AK8857VQ]
Status 2 A Register (R) [Sub Address 0x1A] (A block register)
Status 2 B Register (R) [Sub Address 0x32] (B block register)
Sub Address 0x1A, 0x32
bit 7
bit 6
Reserved
Reserved
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
AGCSTSA
REALFLDA
WSSDETA
VBIDDETA
EXTDETA
CCDETA
AGCSTSB
REALFLDB
WSSDETB
VBIDDETB
EXTDETB
CCDETB
Status 2 A/B Register Definition
Bit
Register Name
bit 0 CCDETA/B
bit 1 EXTDETA/B
bit 2 VBIDDETA/B
bit 3 WSSDETA/B
bit 4 REALFLDA/B
R/W Definition
Closed Caption Detect_A/B R
Extended Data Detect_A/B
VBID Data Detect_A/B
WSS Data Detect_A/B
Real Field_A/B
R
R
R
R
bit 5 AGCSTSA/B
AGC Status_A/B
R
bit 6
~
Reserved
bit 7
Reserved
R
MS1189-E-01
Indicator for presence of decoded data
in Closed Caption 1 2 Register
[0]: No closed caption data present
[1]: Closed caption Data present
Indicator for presence of decoded data
in Extended Data 1,2 Register
0]: No extended data present
[1]: Extended data present
Indicator for presence of decoded data
in VBID 1,2 Register
[0]: No VBID data present
[1]: VBID data present
Indicator for presence of decoded data
in WSS 1,2 Register
[0]: No WSS data present
[1]: WSS data present
Input signal field status (even/odd) indicator
[0] : EVEN field
[1] : ODD field
[0] : Sync AGC active
[1] : Peak AGC active *
Reserved
2010/12
-97-
[AK8857VQ]
Input Video Status A Register (R) [Sub Address 0x1C] (A block register)
Input Video Status B Register (R) [Sub Address 0x34] (B block register)
Sub Address 0x1C, 0x34
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
FIXEDA UNDEFA ST_B/WA ST_VLFA ST_VCENA1 ST_VCENA0 ST_VSFA1
ST_VSFA0
FIXEDB UNDEFB ST_B/WB ST_VLFB ST_VCENB1 ST_VCENB0 ST_VSFB1
ST_VSFB0
Input Video Status A/B Register Definition
BIT Register Name
bit 0
~
bit 1
ST_VSFA/B 0
~
ST_VSFA/B 1
Status of Video
Sub-Carrier
Frequency_A/B
R
bit 2
~
bit 3
ST_VCENA/B 0
~
ST_VCENA/B 1
Status of Video Color
Encode_A/B
R
bit 4
ST_VLFA/B
Status of Video Line
Frequency_A/B
R
bit 5
ST_BWA/B
Status of B/W
Signal_A/B
R
Definition
Input video signal subcarrier
frequency indicator
[ ST_VSFA/B 1 : ST_VSFA/B 0 ] ( MHz )
[00] : 3.57954545 (NTSC-M,J)
[01] : 3.57561149 (PAL-M)
[10] : 3.58205625 (PAL-Nc)
[11] : 4.43361875
(PAL-B,D,G,H,I,N,60,
NTSC-4.43, SECAM*)
Input signal color encode format indicator
[ST_VCEN1 : ST_VCEN0]
[00] : NTSC
[01] : PAL
[10] : SECAM
[11] : Reserved
Input signal line number indicator
[0] : 525 line (NTSC-M,J , NTSC-4.43 ,
PAL-M,60)
[1] : 625 line (PAL-B,D,G,H,I,N,Nc,
SECAM)
Input signal monochrome indicator
[0]: Not monochrome
Un_define_A/B
R
[1]: Monochrome
Input signal detection indicator
[0]: Input signal detected
R
[1]: Input signal not detected
Input signal detection process status
[0]: Detection process in progress
bit 6
bit 7
UNDEFA/B
FIXEDA/B
Input Video Standard
fixed_A/B
R/W
[1]: Detection process completed
*If SECAM input signal is detected, ST_VSCF[1:0] goes to [11].
MS1189-E-01
2010/12
-98-
[AK8857VQ]
Closed Caption 1 A Register (R) [Sub Address 0x1D] (A block register)
Closed Caption 1 B Register (R) [Sub Address 0x35] (B block register)
Closed Caption data storage register
Sub Address 0x1D, 0x35
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
CCA7
CCA6
CCA5
CCA4
CCA3
CCA2
CCA1
CCA0
CCB7
CCB6
CCB5
CCB4
CCB3
CCB2
CCB1
CCB0
Closed Caption 2 A Register (R) [Sub Address 0x1E] (A block register)
Closed Caption 2 B Register (R) [Sub Address 0x36] (B block register)
Closed Caption data storage register
Sub Address 0x1E, 0x36
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
CCA15
CCA14
CCA13
CCA12
CCA11
CCA10
CCA
CCA8
CCB15
CCB14
CCB13
CCB12
CCB11
CCB10
CCB
CCB8
WSS 1 A Register (R) [Sub Address 0x1F] (A block register)
WSS 1 B Register (R) [Sub Address 0x37] (B block register)
WSS data storage register
Sub Address 0x1F, 0x37
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
GA2-7
GA2-6
GA2-5
GA2-4
GA1-3
GA1-2
GA1-1
GA1-0
GB2-7
GB2-6
GB2-5
GB2-4
GB1-3
GB1-2
GB1-1
GB1-0
WSS 2 A Register (R) [Sub Address 0x20] (A block register)
WSS 2 B Register (R) [Sub Address 0x38] (B block register)
WSS data storage register
Sub Address 0x20, 0x38
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Reserved
Reserved
GA4-13
GA4-12
GA4-11
GA3-10
GA3-9
GA3-8
GB4-13
GB4-12
GB4-11
GB3-10
GB3-9
GB3-8
MS1189-E-01
2010/12
-99-
[AK8857VQ]
Extended Data 1 A Register (R) [Sub Address 0x21] (A block register)
Extended Data 1 B Register (R) [Sub Address 0x39] (B block register)
Closed Caption Extended data storage register
Sub Address 0x21, 0x39
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
EXTA7
EXTA6
EXTA5
EXTA4
EXTA3
EXTA2
EXTA1
EXTA0
EXTB7
EXTB6
EXTB5
EXTB4
EXTB3
EXTB2
EXTB1
EXTB0
Extended Data 2 A Register (R) [Sub Address 0x22] (A block register)
Extended Data 2 B Register (R) [Sub Address 0x3A] (B block register)
Closed Caption Extended data storage register
Sub Address 0x22, 0x3A
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
EXTA15
EXTA14
EXTA13
EXTA12
EXTA11
EXTA10
EXTA9
EXTA8
EXTB15
EXTB14
EXTB13
EXTB12
EXTB11
EXTB10
EXTB9
EXTB8
VBID 1 A Register (R) [Sub Address 0x23] (A block register)
VBID 1 B Register (R) [Sub Address 0x3B] (B block register)
VBID data storage register
Sub Address 0x23, 0x3B
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Reserved
Reserved
VBIDA1
VBIDA2
VBIDA3
VBIDA4
VBIDA5
VBIDA6
VBIDB1
VBIDB2
VBIDB3
VBIDB4
VBIDB5
VBIDB6
VBID 2 A Register (R) [Sub Address 0x24] (A block register)
VBID 2 B Register (R) [Sub Address 0x3C] (B block register)
VBID data storage register
Sub Address 0x24, 0x3C
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
VBIDA7
VBIDA8
VBIDA9
VBIDA10
VBIDA11
VBIDA12
VBIDA13
VBIDA14
VBIDB7
VBIDB8
VBIDB9
VBIDB10
VBIDB11
VBIDB12
VBIDB13
VBIDB14
MS1189-E-01
2010/12
-100-
[AK8857VQ]
Device and Revision ID Register (R) [Sub Address 0x3D]
Device ID and Revision indicator
Device ID: [0x39]
Revision ID: Initially 0x00; revision number changes only when control software should be modified.
Sub Address 0x3D
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
REV1
REV0
DID5
DID4
DID3
DID2
DID1
DID0
0
1
1
1
0
0
1
Default Value
0
Device and Revision ID Register Definition
Bit
Register Name
bit 0
~
bit 5
bit 6
~
bit 7
DID0
~
DID5
REV0
~
REV1
R/W
Definition
Device ID
R
Device ID indicator (0x39)
Revision ID
R
Revision ID indicator (initially 0x00)
MS1189-E-01
2010/12
-101-
[AK8857VQ]
10. System connection example
PVDD2
pull
up
Micro Processor
2
(I C Controller)
SDA SCL RSTN PDN OE_A OE_B NSIG_A NSIG_B
SELA
PVDD1
PVDD1
0.1uF
Video IN
0.033uF
47Ω
10uF
DVSS
AIN1~4
PVDD2
30Ω
PVDD2
0.1uF
IREF
VRP
10uF
DVSS
VCOM
VRN
DVDD
DVDD
0.1uF 0.1uF 0.1uF
0.1uF
6.8kΩ
AK8857VQ
10uF
DVSS
XTI
22pF
27MHz
DATA_A[7..0]
XTO
DVALID_A
22pF
VD_ACT_A
HD_ACT_A
FIELD_A
AVDD
0.1uF
DTCLK
10uF
AVDD
DATA_B[7..0]
AVSS
DVALID_B
TEST0
VD_ACT_B
HD_ACT_B
FIELD_B
TEST1
Analog GND
MS1189-E-01
Digital GND
2010/12
-102-
[AK8857VQ]
11. Package
12.0±0.2
10.0±0.2
33
49
32
64
17
10.0±0.2
12.0±0.2
48
1
16
0.5
0.08
M
0゜～ 10゜
1.25TYP
0.2±0.1
S
MS1189-E-01
1.4±0.2
0.10
1.85MAX
0.5±0.2
0.15
0.1 ＋
－ 0.1
0.1
0.15＋
－ 0.05
S
2010/12
-103-
[AK8857VQ]
12. Marking
AKM
AK8857VQ
XXXXXXX
1
AKM:
AKM Logo
AK8857VQ:
Marketing Code
XXXXXXX (7 digits): Date Code
MS1189-E-01
2010/12
-104-
[AK8857VQ]
IMPORTANT NOTICE
These products and their specifications are subject to change without notice.
Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd.
(AKM) sales office or authorized distributor concerning their current status.
AKM assumes no liability for infringement of any patent, intellectual property, or other
right in the application or use of any information contained herein.
Any export of these products, or devices or systems containing them, may require an
export license or other official approval under the law and regulations of the country of
export pertaining to customs and tariffs, currency exchange, or strategic materials.
AKM products are neither intended nor authorized for use as critical components in any
safety, life support, or other hazard related device or system, and AKM assumes no
responsibility relating to any such use, except with the express written consent of the
Representative Director of AKM. As used here:
(a) A hazard related device or system is one designed or intended for life support or
maintenance of safety or for applications in medicine, aerospace, nuclear energy, or
other fields, in which its failure to function or perform may reasonably be expected to
result in loss of life or in significant injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be
expected to result, whether directly or indirectly, in the loss of the safety or
effectiveness of the device or system containing it, and which must therefore meet very
high standards of performance and reliability.
It is the responsibility of the buyer or distributor of an AKM product who distributes,
disposes of, or otherwise places the product with a third party to notify that party in advance
of the above content and conditions, and the buyer or distributor agrees to assume any and
all responsibility and liability for and hold AKM harmless from any and all claims arising
from the use of said product in the absence of such notification.
MS1189-E-01
2010/12
-105-