AK4414EQ

[AKD4414-SA]
AKD4414-SA
AK4414 Sound Evaluation Board Rev.0
GENERAL DESCRIPTION
The AKD4414-SA is an evaluation board for AK4414, 32bit 4ch DAC, supporting DVD-Audio. The
AKD4414-SA has digital audio interfaces, enabling to interface to digital audio systems via optical or
coaxial connector.
 Ordering Guide
AKD4414-SA
---
AK4414 Evaluation Board
(Control software is attached)
FUNCTION
 Three digital audio interfaces
- Coaxial Input
- Optical Input
- 10pin Header for serial control mode
 USB control port
 On-board Analog output buffer circuit
+15V
to D3V
[+3.3V ← +15V]
Power Circuit
Regulator (T1)
[+5V ← +15V]
[+5V → +3.3V]
to AVDD
to VREFH1,2
and DVDD
USB
(CT RL)
and VDD1,2
LOUT 1
PIC18F4550
from D3V
COAX In
-15V
Power Circuit
ROUT1
AK4414
LOUT 2
ROUT2
AK4118A
Opt In
2nd Order LPF
10pin Header
(DSP)
Figure 1. AKD4414-SA Block Diagram (Note 1)
Note 1. Circuit diagram and PCB layout are attached at the end of this manual.
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 Operation Sequence
1)
Setup the power supply lines.
2) Setup the evaluation mode.
2-1) Evaluation of D/A using AK4118A (DIR) (Coaxial connector) <default>
2-2) Evaluation of D/A using AK4118A (DIR) (Optical connector)
2-3) All interface signals including master clock are fed externally (PORT2)
3) Jumper pins and Switch setting. (See the followings.)
3-1) Jumper pin setting
3-2) DIP switch setting
4) Power on.
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1) Setup the power supply lines.
Name
Color
Voltage
+15V
Red
+12+15V
-15V
Blue
-12-15V
GND
Black
0V
Breakdown
Power circuit,
Input/Output Buffer (OP Amp.)
Note
Must be connected.
Input/Output Buffer (OP Amp.)
Must be connected.
Ground
Must be connected.
Table 1. Power Supply Lines (Note 2)
Note 2. Each supply line should be distributed separately from the power supply unit
2) Evaluation Mode
2-1) D/A Evaluation using the AK4118A (DIR) (Coaxial connectior) < default >
The AK4118A generates MCLK, BICK, LRCK, SDATA1 and SDATA2 from the data from the BNC
connector (J1). Evalutations using a test CD and etc. are available(Note 3).
Setting: R46 = “open”, R48 = “short (0Ω)”
Note 3. Coaxial connection is recommended when evaluating the sound quality.
2-2) D/A Evaluation using the AK4118 (DIR) (Optical connectior)
The AK4118A generates MCLK, BICK. LRCK, SDATA1 and SDATA2 from the data from the optical
connector (PORT1). Evalutations using a test CD and etc. are available.
Setting: R46 = “short (0Ω)”, R48 = “open”
2-3) All interface signals including the master clock are supplied externally (PORT2)
Setting: R30, R32, R34, R36, R38 = “open”, R29, R31, R33, R35, R37 = “short (0Ω)”
3) Jumper Pins and Switch Setting
3-1) Jumper Pin Setting
[JP1 (DZF1)]: Selects connection to the DIF1/DZF1 pin
OPEN
: Serial Control Mode
SHORT
: Parallel Control Mode < Default >
[JP2 (DZF2)]: Selects connection to the ACKS/DZF2 pin.
OPEN
: Serial Control Mode
SHORT
: Parallel Control Mode < Default >
[JP3 (DSDR1)]: External Digital Signal (DSDR1) Input Pin Header
In serial control mode, this jumper pin can be used as an input pin header for external
digital signals.
[JP4 (PIC)]: Not for Use
Fixed to “Open”. Do not connect anything.
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3-2). SW Setting
Switch Up: “ON (H)”, Switch Down: “OFF (L)”.
[SW3] (SW DIP-2): AK4118A Setting
No.
Name
1
2
OCKS1
OCKS0
ON (“H”)
OFF (“L”)
Master Clock setting for AK4118A
Refer to Table 5
Default
ON
OFF
Table 2. AK4118A Mode Setting
[SW4] (SW DIP-6): AK4414 Setting 1
No.
Name
1
2
3
4
5
6
SMUTE
TDM1
TDM0
DEM1
DEM0
PSN
ON (“H”)
OFF (“L”)
SMUTE ON
SMUTE OFF
Audio I/F Format for AK4414
Refer to Table 6
De-emphasis Control
Refer to Table 7
Parallel Control Mode
Serial Control Mode
Table 3. AK4414-1 Mode Setting
Default
OFF
OFF
OFF
OFF
ON
ON
[SW5] (SW DIP-6): AK4414 Setting 2
No.
Name
1
SLOW
2
3
4
ACKS
DIF2
DIF1
DIF0
/CAD1
5
6
SD
/CAD0
ON (“H”)
OFF (“L”)
Digital Filter Setting
Refer to Table 8
Auto Setting Mode
Manual Setting Mode
Audio I/F Format for AK4414
Refer to Table 6
CAD1pin= “H”
CAD1pin= “L”
Digital Filter Setting
Refer to Table 8
CAD0pin= “H”
CAD0pin= “L”
Table 4. AK4414-2 Mode Setting
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Default
OFF
ON
OFF
ON
OFF
ON
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OCKS1
L
H
H
OCKS0
L
L
H
MCKO1
256fs
512fs
128fs
<Default>
Table 5. AK4118A Master Clock Setting
Mode
DIF2
DIF1
DIF0
SDTI Format
0
0
0
0
0
0
1
1
0
1
0
1
16-bit LSB justified
20-bit LSB justified
24-bit MSB justified
24-bit I2S compatible
LRCK
H/L
H/L
H/L
L/H
BICK
32fs
40fs
48fs
48fs
1
0
0
24-bit LSB justified
H/L
48fs
5
1
0
1
32-bit LSB justified
H/L
48fs
6
1
1
0
32-bit MSB justified
H/L
48fs
L/H
48fs

256fs
TDM1
TDM0
0
1
2
3
Normal
4
-
0
7
8
TDM256
1
1
1
32-bit I S compatible
0
0
0
N/A
0
0
1
N/A
0
1
0
24-bit MSB justified
2
0
1
1
24-bit I S compatible

256fs
1
0
0
24-bit LSB justified

256fs
11
1
0
1
32-bit LSB justified

256fs
12
1
1
0
32-bit MSB justified

256fs

256fs
9
10
0
1
13
TDM128
2
2
1
1
1
32-bit I S compatible
0
0
0
N/A
0
0
1
N/A
14
0
1
0
24-bit MSB justified

128fs
15
0
1
1
24-bit I2S compatible

128fs
1
1
1
0
0
24-bit LSB justified

128fs
17
1
0
1
32-bit LSB justified

128fs
18
1
1
0
32-bit MSB justified

128fs
19
1
1
1
32-bit I2S compatible

128fs
16
< Default >
Table 6. AK4414 Audio I/F Format
DEM1
0
0
1
1
DEM0
0
1
0
1
Mode
44.1kHz
OFF
48kHz
32kHz
< Default >
Table 7. De-emphasis Control
SD
0
0
1
1
SLOW
0
1
0
1
Mode
Sharp roll-off filter
Slow roll-off filter
Short delay sharp roll-off
Short delay slow roll-off
< Default >
Table 8. Digital Filter Setting
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4) Power ON
Switch Up: “ON (H)”. Switch Down: “OFF (L)”.
Power-down reset by SW1(PDN) and SW2(DIR-PDN) must be made once after power up the evaluation
board. Put the SW1 and SW2 to “L” for power-down reset of the AK4414 and AK4118A, and the return them
to “H” to release the power-down states.
[SW1] (PDN): Resets the AK4414 (Keep “H” during normal operation.)
This switch must be set to “L” once upon power up the evaluation board to reset the AK4414.
[SW2] (DIR-PDN): Resets the AK4118A (Keep “H” during normal operation.)
This switch must be set to “L” once upon power up the evaluation board to reset the
AK4118A. When not using the AK4118A, keep this switch to “L”.
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■ Board Control
The AKD4414-SA can be controlled via a USB port with a PC. Connect J2 (USB) connector to a PC with USB
cable. The control software is included in the AK4413-SA package. Refer to the “Control Software Manual”
paragraph for operational sequence of the control software.
■ External Analog Filter
The AKD4414 has a differential output circuit that outputs differential outputs of the AK4414 via a non-inverting
buffer (second order LPF, fs=106.4k, Q=0.698, G=+3.9dB) and a LPF (first order LPF, fs=284k, G=-0.84dB). A
low-noise and high-voltage operatinal amplifier the LME49710NA is used on the AKD4414. The output signal
from the BNC connector is about 2.8Vrms ([email protected]=5.0V).
+15V
6.8n
+
AOUTLN
220
+
6.8n
10k
220
LME49710NA
7
3
2 +
4
-15V
10u
0.1u
6
+
10u
0.1u
620
620
6.8n
100u
AOUTLP
220
+
7
3
+
2 4
6.8n
10k
220
LME49710NA
+
2 - 4
3 + 7
100
6
Lch
1.0n LME49710NA
10u
0.1u
6
+
0.1u
10u
+
10u
0.1u
330
200
+10u
1.0n
330
200
0.1u
560
560
100u
Figure 2. External Analog Filter
AKD4414-SA
40kHz (Double)
Filter
Internal Filter
-0.3dB
External LPF
-0.12dB
Total
-0.42dB
This table indicates typical values.
80kHz (Quad)
-1dB
-1.3dB
-2.3dB
Table 9. Frequency Responses
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■ Capacitor between VREFH and VREFL pins
Low-frequency distortion can be improved by connecting a large capacitance capacitor between the VREFH pin
and the VREFL pin. (Figure 3) Capacitors between the VREFH pin and the VREFL pin are shown as C159 and
C160 in the circuit diagram.
C=470uF
C=2200uF
C=220uF
C=10uF
C=1000uF
Figure 3. THD+N vs. Input Frequency Comparison by Capacity
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CONTROL SOFTWARE MANUAL
■ Evaluation Board and Control Software Settings
1. Set up the evaluation board as needed. According to the previous terms.
2. Connect the evaluation board and a PC with USB cable.
3. USB control is recognized as HID (Human Interface Device) on PC. When it is not recognized properly, please
disconnect the evaluation board once and reconnect it to the PC.
4. Insert the CD-ROM labeled “AKD4414 Evaluation Kit” into the CD-ROM drive.
5. Access the CD-ROM drive and double-click the icon “akd4414-sa.exe” to open the control program.
6. Begin evaluation by following the procedure below.
Figure 4. Control Software Window
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■ Operation Overview
Register map is controlled by this control software.
Frequently used buttons such as the register initializing button “Write Default”, are located outside of the tab
window. Refer to the “■ Dialog Boxes” section for details of each dialog box setting.
1. [Port Reset]: Resets the USB port of the main board.
Click this button after the control software starts up when a PC is connected to J2 (USB) port
of the AKD4414.
2. [Write Default]: Initializes register values.
Use this button to initialize the registers after the device is reset by hardware reset.
3. [All Write]: Executes all write commands of displayed registers.
4. [Save]: Saves current register settings as a file.
5. [Load]: Executes data write from a saved file.
6. [All Reg Write]: “All Reg Write” dialog box pops up.
7. [Data R/W]: “Data R/W” dialog box pops up.
8. [Sequence]: “Sequence” dialog box pops up.
9. [Sequence(File)]: “Sequence(File)” dialog box pops up.
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■ Tab Descriptions
1. [REG]: Register Map
This tab is for register read and write.
Each bit on the register map is a push-button switch.
Button Down indicates “1” and the bit name is shown in red (when read-only, the name is shown in dark red).
Button Up indicates “0” and the bit name is shown in blue (when read-only, the name is shown in gray)
Grayed out registers are read-only registers. They can not be controlled.
The registers which are not defined on the datasheet are indicated as “---”.
Figure 5. REG Window
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[Write]: Data Write Dialog
Select the [Write] button located on the right of the each corresponding address when changing two or more
bits on the same address simultaneously.
Click the [Write] button for the register pop-up dialog box shown below.
When the checkbox next to the register name is checked, the data will become “1”. When the checkbox is
not checked, the data will become “0”. Click [OK] to write the set values to the registers, or click [Cancel] to
cancel this setting.
Figure 6. Register Set Window
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■ Dialog Boxes
1.[All Req Write]
Click [All Reg Write] button in the main window to open register setting files.
Register setting files saved by [SAVE] button can be applied.
Figure 7. All Reg Write Window
[Open (left)]
[Write]
[Write All]
[Help]
[Save]
[Open (right)]
[Close]
: Open a register setting file (*.akr).
: Executes register writing.
: Executes all register writings.
Writings are executed in descending order.
: A help window pops up.
: Saves register setting file assignment. The file name is “*.mar”.
: Open a register setting assignment file that is saved as “*. mar”.
: Closes the dialog box and finishes this process.
Operating Suggestions
(1) Those files saved by [Save] button and opened by [Open] button on the right of the dialog “*.mar” should be
stored in the same folder.
(2) When register settings are changed by [Save] button in the main window, re-read the file to reflect new
register settings.
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2.[Data R/W]
Click the [Data R/W] button in the main window to open the data read/write dialog box shown below.
A data write is executed to specified address.
Figure 8. Data R/W Window
[Address] Box : Input write data address in hexadecimal numbers for data writing.
[Data] Box
: Input start data in hexadecimal numbers.
[Mask] Box : Input mask data in hexadecimal numbers.
This value “ANDed” with the write data becomes the input data.
[Write] Button : Writes data to the address specified in “Address” box(Note 4).
[Close] Button : Closes the dialog box.
Data write can be cancelled by this button instead of [Write] button.
Note 4. The register map will be updated after executing the [Write] command.
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3.[Sequence]
Click the [Sequence] button to open register sequence setting dialog box shown below.
Register sequence can be set in this dialog box.
Figure 9. Sequence Window
Sequence Setting
Set register sequence according to the following process bellow.
(1) Select a command
Use [Select] pull-down box to choose commands.
Corresponding boxes will be valid.
< Select Pull-down menu >
· No_use
: Not using this address
· Register
: Register write
· Reg(Mask) : Register write (Masked)
· Interval
: Takes an interval
· Stop
: Pauses the sequence
· End
: Ends the sequence
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(2) Input sequence
[Address]
[Data]
[Mask]
[ Interval ]
: Data address
: Write data
: Mask
The value in the [Data] box is ANDed with the value in the [Mask] box. This data
becomes the actual input data.
When Mask = 0x00, current setting is hold.
When Mask = 0xFF, the 8bit data which is set in the [Data] box is written.
When Mask =0x0F, lower 4bit data which is set in the [Data] box is written.
Upper 4bit is hold to current setting.
: Interval time
Valid boxes for each process command are shown bellow.
· No_use
· Register
· Reg(Mask)
· Interval
· Stop
· End
: None
: [Address], [Data], [Interval]
: [Address], [Data], [Mask], [Interval]
: [Interval]
: None
: None
Control Buttons
Functions of Control Buttons are shown bellow.
[Start] Button
[Help] Button
[Save] Button
[Open] Button
[Close] Button
: Executes the sequence
: A help window pops up.
: Saves sequence settings as a file. The file name is “*.aks”.
: Open a sequence setting file “*.aks”.
: Closes the dialog box and finish the process.
Stop of the sequence
When “Stop” is selected in the sequence, the process is paused. It starts again when the [Start] button is
clicked. Restart step number is shown in the “Start Step” box. When executing the process until the end of
sequence, the “Start Step” value will return to “1”.
The sequence can be started from any step by writing the step number to the “Start Step” box.
Write “1” to the “Start Step” box and click [Start] button, when restarting the process from the beginning.
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4.[Sequence(File)]
Click the [Sequence(File)] button to open sequence setting file dialog box shown below.
Files saved in the “Sequence setting dialog” can be applied in this dialog.
Figure 10. Sequence(File) Window
[Open (left)] : Open a sequence setting file (*.aks).
[Start]
: Executes the sequence setting.
[Start All]
: Executes all sequence settings.
Sequences are executed in descending order.
[Help]
: A help window pops up.
[Save]
: Saves a sequence setting file assignment. The file name is “*.mas”.
[Open(right)] : Open a saved sequence setting file assignment “*. mas”.
[Close]
: Closes the dialog box and finish the process.
Operating Suggestions
(1) Files saved by the [Save] button and opened by the [Open] button on the right of the dialog “*.mas”
should be stored in the same folder.
(2) When “Stop” is selected in the sequence the process will be paused and the message box shown below
pops up. Click “OK” to continue the process.
Figure 11. Sequence Pause Window
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Measurement Results
[Measurement condition]
 Measurement unit
 MCLK
 BICK
 fs
 Bit
 Power Supply
 Interface
 Temperature
 Operational Amplifiers
: Audio Precision System two Cascade (AP2)
: 512fs (44.1kHz), 256fs (96kHz), 128fs (192kHz)
: 64fs
: 44.1kHz, 96kHz, 192kHz
: 24bit
: AVDD= DVDD=3.3V, VDD1, 2=VREFH1, 2=5V
: Internal DIR (44.1kHz, 96kHz, 192kHz)
: Room
: LME49710NA
fs=44.1kHz
Parameter Input signal Measurement filter
S/(N+D) 1kHz, 0dB 20kHz SPCL LPF
DR
1kHz, -60dB
A-weighted
S/N
“0” data
20kHz SPCL LPF
A-weighted
LOUT1
105.0
117.5
120.0
117.6
120.0
Results
/ ROUT1 LOUT2
/ 105.3
108.5
/ 117.5
117.5
/ 119.9
119.6
/ 117.5
117.5
/ 119.9
119.9
/
/
/
/
/
/
ROUT2
104.9
117.5
119.7
117.5
119.9
LOUT1
104.5
114.7
119.9
114.7
120.0
Results
/ ROUT1 LOUT2
/ 105.0
107.7
/ 114.4
114.6
/ 119.7
119.9
/ 114.3
114.7
/ 119.8
120.0
/
/
/
/
/
/
ROUT2
104.2
114.6
119.8
114.6
120.0
LOUT1
104.2
113.9
118.8
114.4
119.6
Results
/ ROUT1 LOUT2
/ 103.7
106.0
/ 111.9
112.9
/ 115.9
117.2
/ 114.2
114.5
/ 119.6
119.8
/
/
/
/
/
/
ROUT2
104.1
112.3
116.0
114.4
119.8
fs=96kHz
Parameter Input signal Measurement filter
S/(N+D) 1kHz, 0dB
DR
1kHz, -60dB
S/N
“0” data
40kHz LPF
A-weighted
40kHz LPF
A-weighted
fs=192kHz
Parameter Input signal Measurement filter
S/(N+D) 1kHz, 0dB
DR
1kHz, -60dB
S/N
“0” data
40kHz LPF
A-weighted
40kHz LPF
A-weighted
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Plots
fs=44.1kHz
・FFT1 (fin=1kHz, Input Level=0dBFS)
AKM
AK4414 FFT (0dBFS Input) [ LOUT1/ROUT1 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=512fs, fs=44.1kHz
AKM
AK4414 FFT (0dBFS Input) [ LOUT2/ROUT2 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=512fs, fs=44.1kHz
+0
+0
-10
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
d
B
r
-80
A
-70
-80
-90
d
B
r
-100
A
-100
-90
-110
-110
-120
-120
-130
-130
-140
-140
-150
-150
-160
-160
-170
-180
20
-170
50
100
200
500
1k
2k
5k
10k
-180
20
20k
50
100
200
500
Hz
1k
2k
5k
10k
20k
5k
10k
20k
5k
10k
20k
Hz
Figure 12. LOUT1/ROUT1
Figure 13. LOUT2/ROUT2
・FFT2 (fin=1kHz, Input Level=-60dBFS)
AKM
AK4414 FFT (-60dBFS Input) [ LOUT1/ROUT1 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=512fs, fs=44.1kHz
AKM
AK4414 FFT (-60dBFS Input) [ LOUT2/ROUT2 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=512fs, fs=44.1kHz
+0
+0
-10
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
d
B
r
-80
A
-70
-80
-90
d
B
r
-100
A
-100
-90
-110
-110
-120
-120
-130
-130
-140
-140
-150
-150
-160
-160
-170
-180
20
-170
50
100
200
500
1k
2k
5k
10k
-180
20
20k
50
100
200
500
Hz
1k
2k
Hz
Figure 14. LOUT1/ROUT1
Figure 15. LOUT2/ROUT2
・FFT3 (Noise Floor)
AKM
AK4414 FFT (No Signal Input) [ LOUT1/ROUT1 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=512fs, fs=44.1kHz
AKM
AK4414 FFT (No Signal Input) [ LOUT2/ROUT2 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=512fs, fs=44.1kHz
+0
+0
-10
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
d
B
r
-80
A
-70
-80
-90
d
B
r
-100
A
-100
-90
-110
-110
-120
-120
-130
-130
-140
-140
-150
-150
-160
-160
-170
-180
20
-170
50
100
200
500
1k
2k
5k
10k
20k
-180
20
Hz
50
100
200
500
1k
2k
Hz
Figure 16. LOUT1/ROUT1
Figure 17. LOUT2/ROUT2
[KM109500]
2012/07
- 19 -
[AKD4414-SA]
・FFT4 (Out of Band Noise)
AKM
AK4414 Out of Band Noise [ LOUT1/ROUT1 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=512fs, fs=44.1kHz
AKM
AK4414 Out of Band Noise [ LOUT2/ROUT2 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=512fs, fs=44.1kHz
+0
+0
-10
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
d
B
r
-80
A
-70
-80
-90
d
B
r
-100
A
-100
-90
-110
-110
-120
-120
-130
-130
-140
-140
-150
-150
-160
-160
-170
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
50k
-180
20
100k
50
100
200
500
1k
2k
Hz
5k
10k
20k
50k
100k
Hz
Figure 18. LOUT1/ROUT1
Figure 19. LOUT2/ROUT2
・THD+N vs. Input Level
AKM
AK4414 THD+N vs. Input Level [ LOUT1/ROUT1 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=512fs, fs=44.1kHz
AKM
AK4414 THD+N vs. Input Level [ LOUT2/ROUT2 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=512fs, fs=44.1kHz
-90
-90
-95
-95
-100
-100
-105
d
B
r
-105
d
B
r
-110
A
-110
A
-115
-115
-120
-120
-125
-125
-130
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
-130
-140
+0
-130
-120
-110
-100
-90
-80
-70
dBFS
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 20. LOUT1/ROUT1
Figure 21. LOUT2/ROUT2
・THD+N vs. Input Frequency
AKM
AK4414 THD+N vs. Input Frequency [ LOUT1/ROUT1 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=512fs, fs=44.1kHz
AKM
AK4414 THD+N vs. Input Frequency [ LOUT2/ROUT2 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=512fs, fs=44.1kHz
-90
-90
-95
-95
-100
-100
-105
d
B
r
-105
d
B
r
-110
A
-110
A
-115
-115
-120
-120
-125
-125
-130
20
50
100
200
500
1k
2k
5k
10k
20k
-130
20
Hz
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 22. LOUT1/ROUT1
Figure 23. LOUT2/ROUT2
[KM109500]
2012/07
- 20 -
[AKD4414-SA]
・Linearity
AKM
AK4414 Linearity [ LOUT1/ROUT1 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=512fs, fs=44.1kHz
AKM
AK4414 Linearity [ LOUT2/ROUT2 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=512fs, fs=44.1kHz
+0
+0
-10
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
d
B
r
-60
d
B
r
-70
-70
-80
-80
A
A
-90
-90
-100
-100
-110
-110
-120
-120
-130
-130
-140
-140
-150
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
-150
-150
+0
-140
-130
-120
-110
-100
-90
-80
dBFS
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 24. LOUT1/ROUT1
Figure 25. LOUT2/ROUT2
・Frequency Response
AKM
AK4414 Frequency Response [ LOUT1/ROUT1 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=512fs, fs=44.1kHz
AKM
+0.5
+0.4
+0.4
+0.3
+0.3
+0.2
+0.2
+0.1
d
B
r
AK4414 Frequency Response [ LOUT2/ROUT2 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=512fs, fs=44.1kHz
+0.5
+0.1
d
B
r
+0
A
+0
A
-0.1
-0.1
-0.2
-0.2
-0.3
-0.3
-0.4
-0.5
-0.4
1k
2k
3k
4k
5k
6k
7k
8k
9k
10k
11k
12k
13k
14k
15k
16k
17k
18k
19k
-0.5
20k
1k
2k
3k
4k
5k
6k
7k
8k
9k
10k
Hz
11k
12k
13k
14k
15k
16k
17k
18k
19k
20k
Hz
Figure 26. LOUT1/ROUT1
Figure 27. LOUT2/ROUT2
・Crosstalk
AKM
AK4414 Crosstalk [ LOUT1/ROUT1 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=512fs, fs=44.1kHz
AKM
AK4414 Crosstalk [ LOUT2/ROUT2 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=512fs, fs=44.1kHz
-90
-90
-95
-95
-100
-100
-105
-105
-110
-110
-115
d
B
-115
d
B
-120
-120
-125
-125
-130
-130
-135
-135
-140
-140
-145
-150
20
-145
50
100
200
500
1k
2k
5k
10k
20k
-150
20
Hz
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 28. LOUT1/ROUT1
Figure 29. LOUT2/ROUT2
[KM109500]
2012/07
- 21 -
[AKD4414-SA]
fs=96kHz
・FFT1 (fin=1kHz, Input Level=0dBFS)
AKM
AK4414 FFT (0dBFS Input) [ LOUT1/ROUT1 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=256fs, fs=96kHz
AKM
AK4414 FFT (0dBFS Input) [ LOUT2/ROUT2 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=256fs, fs=96kHz
+0
+0
-10
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
d
B
r
-80
A
-70
-80
-90
d
B
r
-100
A
-100
-90
-110
-110
-120
-120
-130
-130
-140
-140
-150
-150
-160
-160
-170
-180
40
-170
50
100
200
500
1k
2k
5k
10k
20k
-180
40
40k
50
100
200
500
1k
Hz
2k
5k
10k
20k
40k
10k
20k
40k
10k
20k
40k
Hz
Figure 30. LOUT1/ROUT1
Figure 31. LOUT2/ROUT2
・FFT2 (fin=1kHz, Input Level=0dBFS, Notch)
AKM
AK4414 FFT (0dBFS Input)[ LOUT1/ROUT1 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=256fs, fs=96kHz
AKM
AK4414 FFT (0dBFS Input)[ LOUT2/ROUT2 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=256fs, fs=96kHz
+0
+0
-10
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
d
B
r
-80
A
-70
-80
-90
d
B
r
-100
A
-100
-90
-110
-110
-120
-120
-130
-130
-140
-140
-150
-150
-160
-160
-170
-180
40
-170
50
100
200
500
1k
2k
5k
10k
20k
-180
40
40k
50
100
200
500
1k
Hz
2k
5k
Hz
Figure 32. LOUT1/ROUT1
Figure 33. LOUT2/ROUT2
・FFT3 (fin=1kHz, Input Level=-60dBFS)
AKM
AK4414 FFT (-60dBFS Input) [ LOUT1/ROUT1 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=256fs, fs=96kHz
AKM
AK4414 FFT (-60dBFS Input) [ LOUT2/ROUT2 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=256fs, fs=96kHz
+0
+0
-10
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
d
B
r
-80
A
-70
-80
-90
d
B
r
-100
A
-100
-90
-110
-110
-120
-120
-130
-130
-140
-140
-150
-150
-160
-160
-170
-180
40
-170
50
100
200
500
1k
2k
5k
10k
20k
40k
-180
40
Hz
50
100
200
500
1k
2k
5k
Hz
Figure 34. LOUT1/ROUT1
Figure 35. LOUT2/ROUT2
[KM109500]
2012/07
- 22 -
[AKD4414-SA]
・FFT4 (Noise Floor)
AKM
AK4414 FFT (No Signal Input) [ LOUT1/ROUT1 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=256fs, fs=96kHz
AKM
AK4414 FFT (No Signal Input) [ LOUT2/ROUT2 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=256fs, fs=96kHz
+0
+0
-10
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
d
B
r
-80
A
-70
-80
-90
d
B
r
-100
A
-100
-90
-110
-110
-120
-120
-130
-130
-140
-140
-150
-150
-160
-160
-170
-180
40
-170
50
100
200
500
1k
2k
5k
10k
20k
-180
40
40k
50
100
200
500
1k
Hz
2k
5k
10k
20k
40k
Hz
Figure 36. LOUT1/ROUT1
Figure 37. LOUT2/ROUT2
・THD+N vs. Input Level
AKM
AK4414 THD+N vs. Input Level [ LOUT1/ROUT1 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=256fs, fs=96kHz
AKM
AK4414 THD+N vs. Input Level [ LOUT2/ROUT2 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=256fs, fs=96kHz
-90
-90
-95
-95
-100
-100
-105
d
B
r
-105
d
B
r
-110
A
-110
A
-115
-115
-120
-120
-125
-125
-130
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
-130
-140
+0
-130
-120
-110
-100
-90
-80
-70
dBFS
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 38. LOUT1/ROUT1
Figure 39. LOUT2/ROUT2
・THD+N vs. Input Frequency
AKM
AK4414 THD+N vs. Input Frequency [ LOUT1/ROUT1 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=256fs, fs=96kHz
AKM
AK4414 THD+N vs. Input Frequency [ LOUT2/ROUT2 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=256fs, fs=96kHz
-90
-90
-95
-95
-100
-100
-105
d
B
r
-105
d
B
r
-110
A
-110
A
-115
-115
-120
-120
-125
-125
-130
40
50
100
200
500
1k
2k
5k
10k
20k
40k
-130
40
Hz
50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 40. LOUT1/ROUT1
Figure 41. LOUT2/ROUT2
[KM109500]
2012/07
- 23 -
[AKD4414-SA]
・Linearity
AKM
AK4414 Linearity [ LOUT1/ROUT1 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=256fs, fs=96kHz
AKM
AK4414 Linearity [ LOUT2/ROUT2 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=256fs, fs=96kHz
+0
+0
-10
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
d
B
r
-60
d
B
r
-70
-70
-80
-80
A
A
-90
-90
-100
-100
-110
-110
-120
-120
-130
-130
-140
-140
-150
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
-150
-150
+0
-140
-130
-120
-110
-100
-90
-80
dBFS
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 42. LOUT1/ROUT1
Figure 43. LOUT2/ROUT2
・Frequency Response
AKM
AK4414 Frequency Response [ LOUT1/ROUT1 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=256fs, fs=96kHz
AKM
+0.5
+0.4
+0.4
+0.3
+0.3
+0.2
+0.2
+0.1
d
B
r
AK4414 Frequency Response [ LOUT2/ROUT2 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=256fs, fs=96kHz
+0.5
+0.1
d
B
r
+0
A
+0
A
-0.1
-0.1
-0.2
-0.2
-0.3
-0.3
-0.4
-0.4
-0.5
2k
4k
6k
8k
10k
12k
14k
16k
18k
20k
22k
24k
26k
28k
30k
32k
34k
36k
38k
-0.5
40k
2k
4k
6k
8k
10k
12k
14k
16k
18k
20k
Hz
22k
24k
26k
28k
30k
32k
34k
36k
38k
40k
Hz
Figure 44. LOUT1/ROUT1
Figure 45. LOUT2/ROUT2
・Crosstalk
AKM
AK4414 Crosstalk [ LOUT1/ROUT1 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=256fs, fs=96kHz
AKM
AK4414 Crosstalk [ LOUT2/ROUT2 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=256fs, fs=96kHz
-90
-90
-95
-95
-100
-100
-105
-105
-110
-110
-115
d
B
-115
d
B
-120
-120
-125
-125
-130
-130
-135
-135
-140
-140
-145
-150
40
-145
50
100
200
500
1k
2k
5k
10k
20k
40k
-150
40
Hz
50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 46. LOUT1/ROUT1
Figure 47. LOUT2/ROUT2
[KM109500]
2012/07
- 24 -
[AKD4414-SA]
fs=192kHz
・FFT1 (fin=1kHz, Input Level=0dBFS)
AKM
AK4414 FFT (0dBFS Input) [ LOUT1/ROUT1 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=128fs, fs=192kHz
AKM
AK4414 FFT (0dBFS Input) [ LOUT2/ROUT2 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=128fs, fs=192kHz
+0
+0
-10
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
d
B
r
-80
A
-70
-80
-90
d
B
r
-100
A
-100
-90
-110
-110
-120
-120
-130
-130
-140
-140
-150
-150
-160
-160
-170
-180
-170
90
200
500
1k
2k
5k
10k
20k
50k
-180
80k
90
200
500
1k
2k
Hz
5k
10k
20k
50k
80k
20k
50k
80k
20k
50k
80k
Hz
Figure 48. LOUT1/ROUT1
Figure 49. LOUT2/ROUT2
・FFT2 (fin=1kHz, Input Level=0dBFS, Notch)
AKM
AK4414 FFT (0dBFS Input)[ LOUT1/ROUT1 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=128fs, fs=192kHz
AKM
AK4414 FFT (0dBFS Input)[ LOUT2/ROUT2 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=128fs, fs=192kHz
+0
+0
-10
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
d
B
r
-80
A
-70
-80
-90
d
B
r
-100
A
-100
-90
-110
-110
-120
-120
-130
-130
-140
-140
-150
-150
-160
-160
-170
-180
-170
90
200
500
1k
2k
5k
10k
20k
50k
-180
80k
90
200
500
1k
2k
Hz
5k
10k
Hz
Figure 50. LOUT1/ROUT1
Figure 51. LOUT2/ROUT2
・FFT3 (fin=1kHz, Input Level=-60dBFS)
AKM
AK4414 FFT (-60dBFS Input) [ LOUT1/ROUT1 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=128fs, fs=192kHz
AKM
AK4414 FFT (-60dBFS Input) [ LOUT2/ROUT2 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=128fs, fs=192kHz
+0
+0
-10
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
d
B
r
-80
A
-70
-80
-90
d
B
r
-100
A
-100
-90
-110
-110
-120
-120
-130
-130
-140
-140
-150
-150
-160
-160
-170
-180
-170
90
200
500
1k
2k
5k
10k
20k
50k
80k
-180
Hz
90
200
500
1k
2k
5k
10k
Hz
Figure 52. LOUT1/ROUT1
Figure 53. LOUT2/ROUT2
[KM109500]
2012/07
- 25 -
[AKD4414-SA]
・FFT4 (Noise Floor)
AKM
AK4414 FFT (No Signal Input) [ LOUT1/ROUT1 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=128fs, fs=192kHz
AKM
AK4414 FFT (No Signal Input) [ LOUT2/ROUT2 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=128fs, fs=192kHz
+0
+0
-10
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
d
B
r
-80
A
-70
-80
-90
d
B
r
-100
A
-100
-90
-110
-110
-120
-120
-130
-130
-140
-140
-150
-150
-160
-160
-170
-180
-170
90
200
500
1k
2k
5k
10k
20k
50k
-180
80k
90
200
500
1k
2k
Hz
5k
10k
20k
50k
80k
-10
+0
50k
80k
Hz
Figure 54. LOUT1/ROUT1
Figure 55. LOUT2/ROUT2
・THD+N vs. Input Level
AKM
AK4414 THD+N vs. Input Level [ LOUT1/ROUT1 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=128fs, fs=192kHz
AKM
AK4414 THD+N vs. Input Level [ LOUT2/ROUT2 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=128fs, fs=192kHz
-90
-90
-95
-95
-100
-100
-105
d
B
r
-105
d
B
r
-110
A
-110
A
-115
-115
-120
-120
-125
-125
-130
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
-130
-140
+0
-130
-120
-110
-100
-90
-80
-70
dBFS
-60
-50
-40
-30
-20
dBFS
Figure 56. LOUT1/ROUT1
Figure 57. LOUT2/ROUT2
・THD+N vs. Input Frequency
AKM
AK4414 THD+N vs. Input Frequency [ LOUT1/ROUT1 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=128fs, fs=192kHz
AKM
AK4414 THD+N vs. Input Frequency [ LOUT2/ROUT2 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=128fs, fs=192kHz
-90
-90
-95
-95
-100
-100
-105
d
B
r
-105
d
B
r
-110
A
-110
A
-115
-115
-120
-120
-125
-125
-130
90
200
500
1k
2k
5k
10k
20k
50k
80k
-130
Hz
90
200
500
1k
2k
5k
10k
20k
Hz
Figure 58. LOUT1/ROUT1
Figure 59. LOUT2/ROUT2
[KM109500]
2012/07
- 26 -
[AKD4414-SA]
・Linearity
AKM
AK4414 Linearity [ LOUT1/ROUT1 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=128fs, fs=192kHz
AKM
AK4414 Linearity [ LOUT2/ROUT2 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=128fs, fs=192kHz
+0
+0
-10
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
d
B
r
-60
d
B
r
-70
-70
-80
-80
A
A
-90
-90
-100
-100
-110
-110
-120
-120
-130
-130
-140
-140
-150
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
-150
-150
+0
-140
-130
-120
-110
-100
-90
-80
dBFS
-70
-60
-50
-40
-30
-20
-10
+0
75k
80k
dBFS
Figure 60. LOUT1/ROUT1
Figure 61. LOUT2/ROUT2
・Frequency Response
AKM
AK4414 Frequency Response [ LOUT1/ROUT1 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=128fs, fs=192kHz
AKM
AK4414 Frequency Response [ LOUT2/ROUT2 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=128fs, fs=192kHz
+0.4
+0.4
+0.2
+0.2
+0
+0
-0.2
-0.2
-0.4
-0.4
-0.6
d
B
r
A
-0.6
-0.8
-1
d
B
r
-1.2
A
-0.8
-1
-1.2
-1.4
-1.4
-1.6
-1.6
-1.8
-1.8
-2
-2
-2.2
-2.2
-2.4
5k
10k
15k
20k
25k
30k
35k
40k
45k
50k
55k
60k
65k
70k
75k
-2.4
80k
5k
10k
15k
20k
25k
30k
35k
40k
Hz
45k
50k
55k
60k
65k
70k
Hz
Figure 62. LOUT1/ROUT1
Figure 63. LOUT2/ROUT2
・Crosstalk
AKM
AK4414 Crosstalk [ LOUT1/ROUT1 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=128fs, fs=192kHz
AKM
AK4414 Crosstalk [ LOUT2/ROUT2 ]
AVDD=DVDD=3.3V, VDD1,2=VREFH1,2=5V, MCLK=128fs, fs=192kHz
-90
-90
-95
-95
-100
-100
-105
-105
-110
-110
-115
d
B
-115
d
B
-120
-120
-125
-125
-130
-130
-135
-135
-140
-140
-145
-150
-145
90
200
500
1k
2k
5k
10k
20k
50k
80k
-150
Hz
90
200
500
1k
2k
5k
10k
20k
50k
80k
Hz
Figure 64. LOUT1/ROUT1
Figure 65. LOUT2/ROUT2
[KM109500]
2012/07
- 27 -
[AKD4414-SA]
Revision History
Date
(YY/MM/DD)
12/07/02
Manual
Revision
KM109500
Board
Revision
0
Reason
Page
First edition
-
Contents
IMPORTANT NOTICE
 These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
 Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products.
You are fully responsible for the incorporation of these external circuits, application circuits, software and other
related information in the design of your equipments. AKM assumes no responsibility for any losses incurred by
you or third parties arising from the use of these information herein. AKM assumes no liability for infringement
of any patent, intellectual property, or other rights in the application or use of such information contained herein.
 Any export of these products, or devices or systems containing them, may require an export license or other
official approval under the law and regulations of the country of export pertaining to customs and tariffs,
currency exchange, or strategic materials.
 AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support,
or other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system
containing it, and which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to
function or perform may reasonably be expected to result in loss of life or in significant injury or damage to
person or property.
 It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise
places the product with a third party, to notify such third party in advance of the above content and conditions,
and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless
from any and all claims arising from the use of said product in the absence of such notification.
[KM109500]
2012/07
- 28 -
4
3
2
1
VDD1
AVDD
MCLK
5
DVDD
D
D
AOUTL1P
R1
5.1
AOUTL1N
+
R2
0
+
3
PDN
NC
OUT
4
R5
0
1
R7
51
2
R6
51
3
R10
51
4
R11
51
5
R12
51
6
R13
51
7
R14
51
8
R15
51
9
1M
C3
10u(A)
10u(A)
C7
0.01u(F)
34
C6
VDD1
36
35
AOUTL1N
GND
AOUTL1P
37
39
40
41
42
38
VCM1
5
TSTO1
Vcc
TSTO2
IN
AVDD
2
L
U2
AVSS
6
1
R3
0
C5
0.01u(F)
MCLK
3
C8
0.1u
DVSS
H
5
43
4
DVDD
1
SW 1
44
C4
0.01u(F)
R4
+
C1
10u(A)
+
C2
10u(A)
PDN
VSS1
33
TC7SZ17AFS
BICK/DCLK
BICK/DCLK
VREFL1
SDATA1/DSDL1
VREFH1
SDATA2/DSDL2
AOUTR1N
32
C
TDM1/DSDR1
LRCK/DSDR2
SMUTE/CSN
SD/CAD0
DEM0/CCLK
U1
TDM1/DSDR1
AOUTR1P
AK4414
LRCK/DSDR2
NC
SMUTE/CSN
AOUTL2P
SD/CAD0
AOUTL2N
DEM0/CCLK
VREFH2
+
SDATA2/DSDL2
C9
0.01u(F)
31
10
VREFH1
AOUTR1N
29
AOUTR1P
28
27
AOUTL2P
26
AOUTL2N
25
R16
+
C11
0.01u(F)
24
C12
10u(A)
+
C160
220u(A)
10
VREFH2
R17
(open)
B
23
10u(A)
C15
+
0.01u(F)
C14
10u(A)
R21
+
C13
1M
51
51
51
51
51
R9
VDD2
JP2
DZF2
R20
0
51
C
R8
(open)
22
AOUTR2N
21
AOUTR2P
20
19
TEST
18
17
TDM0
DIF2
13
12
JP1
DZF1
VCM2
VSS2
SLOW
DIF0/CAD1
16
11
ACKS/DZF2
51
VREFL2
15
R19
DEM1/CDTI
PSN
10
14
51
DIF1/DZF1
DIF0/CAD1
R18
C159
220u(A)
30
B
DEM1/CDTI
C10
10u(A)
+
SDATA1/DSDL1
R27
R26
R25
R24
R23
R22
AOUTR2N
AOUTR2P
Title
Size
A3
- 29 5
4
3
A
VDD2
SLOW
TDM0
ACKS/DZF2
PSN
DIF2
DIF1/DZF1
A
Date:
2
AKD4414-SA
Document Number
AK4414
W ednesday, June 27, 2012
Rev
0
Sheet
1
1
of
6
5
4
3
2
10
8
6
4
2
DIRVDD
9
7
5
3
1
1
SDATA2/DSDL2
SDATA1/DSDL1
LRCK/DSDR2
BICK/DCLK
MCLK
PORT2
DSP
D3V
R28
0
+
D
+
D
C16
10u(A)
C17
10u(A)
11
10
(open)
0
DSP-LRCK/DSDR2
DIR-LRCK
R31
R32
(open)
0
DSP-SDATA2/DSDL2
R33
R34
(open)
0
25
DSP-SDATA1/DSDL1
DIR-SDATA
R35
R36
(open)
0
26
DSP-BICK/DCLK
DIR-BICK
R37
R38
(open)
0
24
LRCK
23
MCKO1
DVDD
VSS2
22
21
20
VOUT/GP7
19
UOUT/GP6
17
18
COUT/GP5
VIN/GP0
BOUT/GP4
16
TX1/GP3
15
14
R29
R30
C19
0.01u(F)
TX0/GP2
12
NC/GP1
TVDD
13
C18
0.01u(F)
DSP-MCLK
DIR-MCLK
SDTO
XTL1
BICK
XTL0
MCKO2
P/SN
DAUX
MCLK
LRCK/DSDR2
SDATA2/DSDL2
SDATA1/DSDL1
BICK/DCLK
27
C
C
9
8
R39
0
7
6
IPS1/IIC
XTO
U3
AK4118A
DIF2/RX7
XTI
28
29
30
U4
VSS1
PDN
31
R40
4
0
OUT
NC
GND
R41
0
5
DIF1/RX6
CM0/CDTO/CAD1
32
5
Vcc
IN
3
C20
0.1u
2
SW 2
1
R42
0
3
TEST2
CM1/CDTI/SDA
DIF0/RX5
OCKS1/CCLK/SCL
1
3
NC
OCKS0/CSN/CAD0
1
PORT1
VCC
2
L
34
R43
R44
47k
47k
B
35
OCKS1 4
OCKS0 3
OCKS1
OCKS0
1
2
INT1
36
SW 3
37
AVDD
38
39
R
VCOM
40
VSS3
41
RX0
42
NC
43
RX1
44
TEST1
45
46
48
47u
DIRVDD
3
2
1
C22
0.1u
+ C23
10u(A)
C21
0.01u(F)
+
GND
OUT
L1
RX2
INT0
VSS4
IPS0/RX4
RX3
DIRVDD
47
1
6
DIR-PDN
33
B
2
H
5
TC7SZ17AFS
4
4
C24
10u(A)
R45
51
R46
(open)
R47
+
OPT
DIRVDD
10k
C25
10u(A)
A
A
2
3
4
5
J1
COAX
1
C26
0.1u
R48
0
Title
R49
75
Size
A3
- 30 5
4
3
Date:
2
AKD4414-SA
Document Number
DIR
W ednesday, June 27, 2012
Rev
0
Sheet
1
2
of
6
4
3
R50
2.2u
5V => 3.3V
38
39
40
41
2
3
4
5
8
7
6
5
C
NC
NC
Vin
Vout
Vcont PCL
NC
GND
T1
TK73633AME
1
2
3
4
PIC
C36
17
16
15
14
11
10
9
8
32
35
36
1u
J2
VUSB
DD+
GND
1
2
3
4
R64
R65
42
43
44
1
0
0
C30
0.1u
VDD0
6
VDD1
VSS0
NC/ICCK/ICPGC
NC/ICDT/ICPGD
NC/ICRST_N/ICVpp
NC/ICPORTS
RC4/D-/VM
RC5/D+/VP
RC6/TX/CK
RC7/RX/DT/SDO
2
SMUTE
3
CCLK
5
DEM0
6
CDTI
11
1A
18
USB-RST
C32
0.1u
12
13
33
34
R58
100k
4
R57
100
7
R59
100
9
R60
100
SMUTE/CSN
1B
2A
2Y
U6
DEM0/CCLK
2B
TC74VHC157FK
PIC18F4550
TQFP 44-PIN
OSC1/CLKI
OSC2/CLKO/RA6
RE0/AN5/CK1SPP
RE1/AN6/CK2SPP
RE2/AN7/OESPP
U5
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2/UOE_N
RC2/CCP1/P1A
CSN
1Y
MCLR_N/Vpp/RE3
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0/CSSPP
RB3/AN9/CPP2/VPO
RB2/AN8/INT2/VMO
RB1/AN10/INT1/SCK/SCL
RB0/AN12/INT0/FLT0/SDI/SDA
RD0/SPP0
RD1/SPP1
RD2/SPP2
RD3/SPP3
RD4/SPP4
RD5/SPP5/P1B
RD6/SPP6/P1C
RD7/SPP7/P1D
R54
R55
R56
R51
R52
R53
C29
0.1u
VSS1
VDD
MCLR
PGD
PGC
GND
D
7
C28
10u(A)
28
C27
10u(A)
29
C31
1
2
3
4
5
+
+
JP4
4.7k
1
(open)
(open)
(open)
D
2
10k
10k
10k
5
VUSB
RA0/AN0
RA1/AN1
RA2/AN2/Vref-/CVref
RA3/AN3/Vref+
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS_N/HLVDIN/C2OUT
30
31
XTI
XTO
25
26
27
37
C33
22p
X1
20MHz
C34
22p
3Y
10
DEM1
JP3
DSDR1
C35
C
3A
14
470n
4A
4Y
19
20
21
22
23
24
13
TDM1
R61
R62
R63
51
51
51
1
PSN
15
DEM1/CDTI
3B
12
TDM1/DSDR1
4B
SELECT
VCC
ST
GND
16
D3V
C37
0.1u
8
+
C38
10u(A)
USB
PIC18F4550
B
B
PSN
6
5
4
3
2
1
D3V
SW4
7
8
9
10
11
12
PSN
DEM0
DEM1
TDM0
TDM1
SMUTE
RP1
D3V
TDM0
6
5
4
3
2
1
SW5
7
8
9
10
11
12
SD/CAD0
DIF0/CAD1
DIF1
DIF2
ACKS
SLOW
RP2
6
5
4
3
2
1
47k
SD/CAD0
DIF0/CAD1
DIF1/DZF1
DIF2
ACKS/DZF2
SLOW
6
5
4
3
2
1
47k
A
A
Title
Size
A3
- 31 5
4
3
Date:
2
AKD4414-SA
Document Number
SW
& Control I/F Sheet
W ednesday, June 27, 2012
1
Rev
0
3
of
6
5
4
3
2
1
C39
6.8n(F)
2
R70
10k
-
6
C44
6.8n(F)
R71
620
R72
0
C46
(open)
R73
200
C48
100p(F)
D
C43
1n(F)
LME49710NA
4
C41
100p(F)
C42
(open)
R69
560
U7
+
R77
330
R75
0
C47
(open)
3
U8
2
R74
620
C45
(short)
+
3
4
7
R68
220
6
LME49710NA
C49
100p(F)
R79
560
R76
100
1
R78
(open)
7
+
R67
220
+
D
C40
100u(A)
-
R66
0
AOUTL1P
C50
(open)
J3
LOUT1
2
3
4
5
C51
1n(F)
C52
6.8n(F)
+
R81
220
R82
220
7
C53
100u(A)
3
AOUTL1N
R83
10k
-
6
LME49710NA
4
C56
(open)
C
U9
+
2
C54
100p(F)
C55
6.8n(F)
R86
200
C61
100p(F)
+
C57
0.01u(F)
C58
C59
10u(A) 0.01u(F)
+
R80
0
R84
5.1
R85
5.1
VOP+
C
C60
10u(A)
R87
330
C62
100p(F)
C63
6.8n(F)
+
R91
220
R92
220
7
C64
100u(A)
3
AOUTR1P
2
R93
10k
-
5.1
R89
5.1
6
+
VOP-
C66
0.01u(F)
LME49710NA
C67
C68
10u(A) 0.01u(F)
C69
10u(A)
B
4
C65
100p(F)
C70
(open)
B
R88
U10
+
+
R90
0
C71
6.8n(F)
R95
560
R94
200
C74
1n(F)
R96
330
R97
620
R98
0
R105
220
3
AOUTR1N
R107
10k
-
R99
620
U12
R106
560
6
2
3
U11
6
C78
(short)
LME49710NA
R101
100
R102
(open)
1
C79
(open)
J4
ROUT1
2
3
4
5
C81
1n(F)
LME49710NA
4
C83
(open)
+
2
C82
100p(F)
C76
(open)
7
R104
220
7
C80
100u(A)
+
R103
0
R100
0
+
C75
(open)
6.8n(F)
-
C77
4
C73
100p(F)
+
C72
100p(F)
C84
6.8n(F)
A
A
R108
200
C85
100p(F)
R109
330
Title
C86
100p(F)
Size
A3
- 32 5
4
3
Date:
2
AKD4414-SA
Document Number
External
LPF1
W ednesday, June 27, 2012
Rev
0
Sheet
1
4
of
6
5
4
3
2
1
C87
6.8n(F)
2
R114
10k
-
6
C92
6.8n(F)
R115
620
R116
0
C94
(open)
R117
200
C96
100p(F)
D
C91
1n(F)
LME49710NA
4
C89
100p(F)
C90
(open)
R113
560
U13
+
R121
330
R120
0
C95
(open)
3
U14
2
R119
620
C93
(short)
+
3
4
7
R112
220
6
LME49710NA
C97
100p(F)
R123
560
R118
100
R122
(open)
7
+
R111
220
+
D
C88
100u(A)
-
R110
0
AOUTL2P
1
C98
(open)
J5
LOUT2
2
3
4
5
C99
1n(F)
C100
6.8n(F)
+
R125
220
R126
220
7
C101
100u(A)
3
AOUTL2N
R127
10k
-
6
LME49710NA
4
C103
(open)
C
U15
+
2
C102
100p(F)
C104
6.8n(F)
R130
200
C109
100p(F)
+
C105
0.01u(F)
C106 C107
10u(A) 0.01u(F)
+
R124
0
R128
5.1
R129
5.1
VOP+
C
C108
10u(A)
R131
330
C110
100p(F)
C111
6.8n(F)
+
R135
220
R136
220
7
C112
100u(A)
3
AOUTR2P
2
R137
10k
-
5.1
R133
5.1
6
+
VOP-
C114
0.01u(F)
LME49710NA
C115 C116
10u(A) 0.01u(F)
C117
10u(A)
B
4
C113
100p(F)
C119
(open)
B
R132
U16
+
+
R134
0
C118
6.8n(F)
R139
560
R138
200
C122
1n(F)
R140
330
R141
620
R142
0
R149
220
3
AOUTR2N
R151
10k
-
R143
620
U18
R150
560
6
2
3
U17
6
C126
(short)
LME49710NA
R145
100
R146
(open)
1
C127
(open)
J6
ROUT2
2
3
4
5
C129
1n(F)
LME49710NA
4
C132
(open)
+
2
C130
100p(F)
C124
(open)
7
R148
220
7
C128
100u(A)
+
R147
0
R144
0
+
C123
(open)
6.8n(F)
-
C125
4
C121
100p(F)
+
C120
100p(F)
C131
6.8n(F)
A
A
R152
200
C133
100p(F)
R153
330
Title
C134
100p(F)
Size
A3
- 33 5
4
3
Date:
2
AKD4414-SA
Document Number
External
LPF2
W ednesday, June 27, 2012
Rev
0
Sheet
1
5
of
6
5
4
J7
+15V
J8
GND
3
1
J9
-15V
VOP+
VOP-
C135
100u(A)
+
+
2
C136
100u(A)
D
D
Q1
R156
BCP 56
R157
6.8k
R173
390
+
R154
0
R155
0
R159
0
R161
0
C137
100u(A)
5.1k
R160
1
C138
0.1u
VREFH1
VDD1
VDD2
VREFH2
C139
R158
100p(F) 3.9k
D1
HZ2ALL
C140
470u(A)
C
+
C141
0.1u
C142
470u(A)
U19
AD817A/AD
1
R162
10k
C143
100p(F)
2
3
C145
100u(A)
4
+
D2
HZ2CLL
NC
NC
-IN
V+
+IN
OUT
V-
NC
7
6
5
Q2
2SB1188 CSC
6.8k
5.1k
+
C144
100u(A)
R163
3.6k
C146
100p(F)
C147
220p(F)
Q3
R167
C
8
B
R166
+
BCP 56
R168
3.3k
+
R164
0
R165
0
R169
0
C148
100u(A)
AVDD
B
DVDD
D3V
R170
1
C149
0.1u
C150
100p(F)
D3
HZ2ALL
C151
470u(A)
+
C152
0.1u
1
R171
6.8k
C154
100p(F)
2
3
C156
100u(A)
A
C153
470u(A)
U20
AD817A/AD
4
+
D4
HZ2ALL
NC
NC
-IN
V+
+IN
OUT
V-
NC
+
8
7
6
5
Q4
SB1188 CSC
+
C155
100u(A)
R172
3.3k
C157
100p(F)
C158
220p(F)
A
Title
Size
A3
- 34 5
4
3
Date:
2
AKD4414-SA
Document Number
Power
Supply
W ednesday, June 27, 2012
Rev
0
Sheet
1
6
of
6
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