AKM AK7722VQ

[AK7722]
AK7722
24bit 4ch ADC + 24bit 4ch DAC with Audio DSP
GENERAL DESCRIPTION
The AK7722 is a digital signal processor with an integrated 4ch 24bit DAC, a stereo ADC with input selector
and a 2ch input ADC. The integrated 4ch DAC, the 2ch ADC with input selector and the other 2ch ADC
feature high performance achieving 108dB, 96dB and 95dB, respectively. The integrated SRC has three
input selector enabling the DSP to operate in master mode with digital inputs. The audio DSP has
1536step/fs (at 48kHz sampling) parallel arithmetic operation performance and the 5k-word delay RAM
allows surround processing and time alignment adjusting. As the AK7722 is a RAM based DSP, it is
programmable for various user requirements. It is housed in an 80pin LQFP package.
FEATURES
[DSP Block]
- Word length: 24bit (Coefficient RAM & Data RAM: F24 floating point)
- Processing Speed: 13.6 ns (1536step/fs; fs = 48kHz)
- Multiplication: 20 x 24 → 44-bit Double precision arithmetic available
- Divider 20 / 20 → 20bit
- ALU: 48bit arithmetic operation (overflow margin 4bit) 20bit floating point arithmetic
and logic operation
- Program RAM: 3072 x 36bit
- Coefficient RAM: 2048 x 24bit (F24 floating point)
- Data RAM: 2048 x 24-bit (F24 floating point)
- Offset Register: 64 x 13bit
- Delay RAM1: 3072 x 24-bit
- Delay RAM2: 2048 x 24-bit
- Sampling rate: fs= 7.35k ~ 48kHz
- Master Clock: 1536fs
(generated from 32fs, 48fs, 64fs, 128fs, 256fs, 384fs by internal PLL)
- Master/Slave Operation
[ADC1 Block]
- Stereo with 6 Inputs Selector
- DR, S/N: 96dB (fs = 48kHz, when differential input)
- S/(N+D): 90dB (fs = 48kHz)
- Differential & Single-ended Inputs
- Digital HPF (fc=1Hz)
- 6 Analog Inputs Selector (2 differential, 4 single-ended)
- Digital Volume Control (24dB ~ -103dB, 0.5dB Step, Mute)
[ADC2 Block]
- DR, S/N: 95dB (fs = 48kHz)
- Single-ended Inputs
- Digital Volume Control (24dB ~ -103dB, 0.5dB Step, Mute)
[SRC Block]
- 3 Pair of Stereo → 1 Stereo Pair Selector
- 2ch x 1 system
- Supporting frequency: Fin = 7.35kHz ~ 96kHz → Fout = 7.35kHz ~ 48kHz
(FSO/FSI = 0.167~ 6.0)
MS1328-E-00-PB
- 1 -
2011/09
[AK7722]
[Guidance SRC Block] (GSRC)
- 1 Channel (24bit) Up-converter for Voice Guidance
- Supporting frequency: Fin = 7.35kHz ~ 12kHz → Fout = 44.1kHz or 48kHz
[DAC Block]
- 4ch (2 Stereos)
- 24bit 128 x Over-sampling advanced multi-bit (fs=8kHz~48kHz)
- DR, S/N: 108dB (Differential Output)
- S/(N+D): 90dB
- Digital Volume Control (12dB ~ -115dB, 0.5dB Step, Mute)
[Digital Interface Input/Output]
- Digital Signal Input Port (4ch):
24bit MSB justified, 24/20/16bit LSB justified and I2S Format
- Digital Signal Output Port (6ch):
24bit MSB justified, 24/16bit LSB justified and I2S Format
[Micro Computer Interface]
- I2C or 4-wired Interface
[General]
- Integrated PLL
- Integrated Regulator 3.3V → 1.8V
- Power Supply: 3.3V ± 0.3V
- Operating Temperature Range: -40˚C ~ 85˚C
- 80pin LQFP
MS1328-E-00-PB
- 2 -
2011/09
[AK7722]
■ Block Diagram
LFLT
2 DVDD
pull down
Hi-z
XTO
2
3 VSS2
Open Drain
3 AVDD
3 VSS3
XTI
REF
BICKI
LRCKI
VCOM
LDO
AVDRV
CLKGEN & CONT
TESTI1
TESTI2
DVOL
IRESETN
ADC2
2 A2INL,A2INR
SDOUTAD2
CLKOE
CLKO
ASEL[2:0]
DVOL
BICKOE
BICKO
LRCKOE
LRCKO
SDOUTAD1
SELDI5
1
0
SDIN5
2 AIN5L,AIN5R
2 AIN4L,AIN4R
2 AIN3L,AIN3R
2
DIN5
GSRC
0
MUX[2:0]
DVOL DAC2
SELDO5[1:0]
SELDI4
0
1
SRIN2
3
2
3
SDINDA2
2
MUX2[2:0]
SRCBICKI
DOUT4
0
DVOL DAC1
MUX2
SDINDA1
2
AOUT1LP
AOUT1LN
AOUT1RP
AOUT1RN
1
SRCI
3
SRCLFLT
UNLOCK
SRCO
SELDO4[1:0]
DOUT3
0
1
DIN3
IRPT
OUT3E
DOUT2
SDOUT3 / IRPT
2
3
DIN1
SDIN1
0
1
SELDI3
SRIN1
SELDO3[1:0]
0
OUT2E
SDOUT2
1
SDIN2 / JX1
2
DIN2
JX1E
JX0
3
SELDO2[1:0]
JX1
JX0
SRIN3
AOUT2LP
AOUT2LN
3
DSP
SRC
1
0
AIN1RP,AIN1RN
AOUT2RP
AOUT2RN
1
DIN4
SRCLRCKI
3
AIN2LP,AIN2LN
4 AIN2RP,AIN2RN
4 AIN1LP,AIN1LN
0
DOUT5
DSEL[1:0]
SRIN1,SRBICK1
SRLRCK1
SRCLFLT
UNLOCK
2 AIN6L,AIN6R
4
3
MUX1
GLRCKI
SRIN2,SRBICK2
SRLRCK2
5
1
GBICKI
SRIN3,SRBICK3
SRLRCK3
ADC1
DOUT1
0
OUT1E
1
JX2E
JX2
SDOUT1 / GP0
2
GP0
3
SELDO1[1:0]
WDTEN
WDT
CRC
STO
MICIF
CRCE
GP1
RDY
SO
RDY
SO
I2CSEL
RQN / CAD1
SI / CAD0
SCLK / SCL
SDA
GP1
Figure 1. Block Diagram
* Figure 1 shows a simplified diagram of the AK7722, which is not the perfect same as the actual circuit diagram.
MS1328-E-00-PB
- 3 -
2011/09
[AK7722]
CP0, CP1
DLP0, DLP1
DP0, DP1
DLRAM1:3072W x 24-Bit
DRAM
2048w x 24-Bit
CRAM
2048W x 24-Bit
OFREG
64w x 13-Bit
DLRAM2:2048W x 24-Bit
CBUS(24-Bit)
DBUS(24-Bit)
MPX24
Micon I/F
MPX20
X
Control
DEC
Y
Serial I/F
PRAM
3072w x 36-Bit
Multiply
24 x 20 → 44-Bit
PC
Stack: 5level(max)
TMP 12 x 24-Bit
24-Bit
44-Bit
PTMP(LIFO) 6 x 24-Bit
MUL
DBUS
SHIFT
48-Bit
44-Bit
A
2 x 24(,16)-Bit
DIN5 (ADC2)
2 x 24(,16)-Bit
DIN4 (ADC1)
2 x 24, 20, 16-Bit DIN3 (SRC)
B
2 x 24, 20, 16-Bit DIN2
ALU
2 x 24, 20, 16-Bit DIN1
48-Bit
Overflow Margin: 4-Bit
48-Bit
DR0 ∼ 3
48-Bit
Over Flow Data
Generator
Division 20÷20→20
2 x 24, 20, 16-Bit
DOUT5(DAC2)
2 x 24, 20, 16-Bit
DOUT4(DAC1)
2 x 24, 20, 16-Bit
DOUT3
2 x 24, 20, 16-Bit
DOUT2
2 x 24, 20, 16-Bit
DOUT1
Peak Detector
Figure 2. Main DSP Block Diagram of the AK7722
MS1328-E-00-PB
- 4 -
2011/09
[AK7722]
■ Ordering Guide
-40 ∼ +85°C
80pin LQFP
Evaluation Board for AK7722
AK7722VQ
AKD7722
SDOUT1 / GP0
SDOUOT2
SDOUT3 / IRPT
STO
SRLRCK2
SRIN2
SRBICK2
SRLRCK3
SRBICK3
SRIN3
UNLOCK
I2CSEL
INITRSTN
TESTI2
AVDRV
VSS4
DVDD
SRCLFLT
VSS5
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
AVDD
■ Pin Layout
BICKO
AOUTR2N
AOUTR2P
61
62
40
39
LRCKO
AOUTL2N
63
38
CLKO
AOUTL2P
64
37
VSS3
AOUTR1N
AOUTR1P
65
66
36
35
DVDD
AOUTL1N
67
34
SO
AOUTL1P
68
69
33
32
SI / CAD0
31
RQN / CAD1
AVDD
VCOM
80 pin LQFP
70
VSS6
71
A2INR
A2INL
72
73
AINR6
AINL6
SDA
SCLK / SCL
30
RDY
29
28
SRIN1
74
27
SRLRCK1
75
76
26
25
SDIN2 / JX1
AINR5
(TOP VIEW)
SRBICK1
SDIN1
AINL5
77
24
BICKI
AINR4
78
23
LRCKI
AINL4
79
80
22
21
JX0
GP1
XTO
XTI
VSS2
DVDD
SDIN5
GBICK
TESTI1
GLRCK
VSS1
LFLT
AVDD
AINL1P
AINR1P
AINL1N
AINR1N
AINL2P
AINR2P
AINL2N
AINL3
AINR2N
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
AINR3
pin
Input
Output
I/O
Power
MS1328-E-00-PB
5
2011/09
[AK7722]
PIN FUNCTION
No.
1
2
3
4
5
6
7
8
9
10
11
Name
AINL3
AINR2N
AINR2P
AINL2N
AINL2P
AINR1N
AINR1P
AINL1N
AINL1P
AVDD
VSS1
I/O
I
I
I
I
I
I
I
I
I
O
12 LFLT
13 TESTI1
14
15
16
17
18
GLRCKI
GBICKI
SDIN5
DVDD
VSS2
I
I
I
I
-
19 XTI
I
20 XTO
O
21 GP1
O
22 JX0
I
23 LRCKI
24 BICKI
25 SDIN1
SDIN2
26
JX1
27 SRLRCK1
28 SRBICK1
MS1328-E-00-PB
Function
Classification
ADC1 Lch Single-ended Input 3 Pin.
Analog Input
ADC1 Inverted Rch Differential Input 2 Pin
Analog Input
ADC1 Non-inverted Rch Differential Input 2 Pin
Analog Input
ADC1 Inverted Lch Differential Input 2 Pin
Analog Input
ADC1 Non-inverted Lch Differential Input 2 Pin
Analog Input
ADC1 Inverted Rch Differential Input 1 Pin
Analog Input
ADC1 Non-inverted Rch Differential Input 1 Pin
Analog Input
ADC1 Inverted Lch Differential Input 1 Pin
Analog Input
ADC1 Non-inverted Lch Differential Input 1 Pin
Analog Input
Analog Power Supply Pin 3.0 ~ 3.6V
Power Supply
Analog Ground Pin 0V
Power Supply
R and C Component Connect Pin for PLL
Refer to “7. LFLT Pin External Connection”. This pin outputs “L” during Analog Output
initial reset.
Test 1 Pin (Internal pull-down)
Test
This pin must be connected to VSS.
Frame Clock Input Pin for Voice Guidance
Digital Input
Bit Clock Input Pin for Voice Guidance
Digital Input
Serial Audio Input Pin for Voice Guidance
Digital Input
Digital Power Supply Pin 3.0~3.6V
Power Supply
Ground Pin 0V
Power Supply
Crystal oscillator input pin
Clock
Connect a crystal oscillator between this pin and the XTO pin, or input an
external clock to the XTI pin.
Crystal Oscillator Output Pin
When a crystal oscillator is used, connect it between XTI and XTO. When
Clock
an external clock is used, leave this pin open. During initial reset, the output
of this pin is not determinable.
Programmable Bit Output Pin
Digital Output
This pin outputs “L” during initial reset.
Conditional Jump Pin0
The conditional jump pin (JX0) is valid by setting control register (JX0E) to Conditional Input
“1”.
LR Channel Select Clock Pin 1
LR clock should be input to this pin in slave mode.
Serial Bit Clock Input Pin 1
I
BITCLOCK (48fs or 64fs) should be input to this pin in slave mode.
I
System Clock
Input
System Clock
Input
I Serial Data Input 1 Pin
Digital Input
I Serial Data Input 2 Pin
Digital Input
Conditional Jump Pin1
I
The conditional jump pin (JX1) is valid by setting control register (JX1E) to Conditional Input
“1”.
System Clock
I LR Channel Select Clock Pin 1 (for SRC)
Input
System Clock
I Serial Bit Clock Input Pin 1 (for SRC)
Input
6
2011/09
[AK7722]
No.
Name
29 SRIN1
SDIN3
30 RDY
31
RQN
CAD1
32
SCLK
SCL
33
SI
CAD0
34 SO
35 SDA
36 DVDD
37 VSS3
38 CLKO
39 LRCKO
40 BICKO
41
SDOUT1
Function
Classification
I/O
I Serial Data Input Pin 1 (for SRC)
Digital Input
I Serial Data Input Pin 3
Data Write Ready Output Pin for Microprocessor Interface
Microprocessor
O
This pin outputs RDY, and outputs “H” during initial reset.
Microprocessor Interface Write Request Pin (I2CSEL pin = “L”)
Interface
When initial reset state and Microcomputer interface are not in use, leave
I
RQN pin= “H”.
I I2C Bus Address Setting Pin 1 (I2CSEL pin = “H”)
I2C
Microprocessor
I Serial Data Clock Pin for Microprocessor Interface (I2CSEL pin = “L”)
When SCLK is not used, tie the SCLK pin = “H”.
Interface
2
I I C Bus Data Clock Pin (I2CSEL pin = “H”)
I2C
Microprocessor
I Serial Data Input Pin for Microprocessor Interface (I2CSEL pin = “L”)
When SI is not used, tie the SI pin = “L”.
Interface
I I2C Bus Address Setting Pin 0 (I2CSEL pin = “H”)
I2C
Serial Data Output Pin for Microprocessor Interface
Microprocessor
O
Outputs “L” during initial reset.
Interface
O I2CSEL pin = “L”
Open
Leave this pin Open. SDA outputs “L”.
2
I/O I C Bus Data Clock Pin (I2CSEL pin = “H”)
I2C
Outputs “Hi-z” during initial reset.
- Digital Power Supply Pin 3.0~3.6V
Power Supply
- Ground Pin 0V
Power Supply
Clock Output Pin
O
Clock Output
This pin outputs “L” during initial reset.
LR Channel Select Output Pin
System Clock
O
This pin outputs “L” during initial reset in master mode.
Output
Serial Bit Clock Output Pin
System Clock
O
This pin outputs “L” during initial reset in master mode.
Output
Serial Data Output1 Pin
Digital Output
O
This pin outputs “L” during initial reset.
GP0
42 SDOUT2
SDOUT3
43
IRPT
44 STO
O Programmable Bit Output Pin
Serial Data Output2 Pin
O
This pin outputs “L” during initial reset.
Serial Data Output3 Pin
O
This pin outputs “L” during initial reset.
O Interrupt Status Output Pin
Status Output Pin
O
This pin outputs “H” during initial reset.
45 SRLRCK2
I LR Channel Select Clock Pin 2 (for SRC)
46 SRBICK2
I Serial Bit Clock Input Pin 2 (for SRC)
47
SRIN2
SDIN4
48 SRLRCK3
MS1328-E-00-PB
Digital Output
Digital Output
Digital Output
Digital Output
Status
System Clock
Input
System Clock
Input
I Serial Data Input Pin 2 (for SRC)
I Serial Data Input Pin 4
Digital Input
I LR Channel Select Clock Pin 3 (for SRC)
System Clock
Input
7
2011/09
[AK7722]
No.
Name
49 SRBICK3
SRIN3
50
JX2
51 UNLOCK
52 INITRSTN
53 I2CSEL
54 TESTI2
55 AVDRV
56 VSS4
57 DVDD
58 SRCLFLT
59 VSS5
60 AVDD
61 AOUTR2N
62 AOUTR2P
63 AOUTL2N
64 AOUTL2P
65 AOUTR1N
66 AOUTR1P
67 AOUTL1N
68 AOUTL1P
69 AVDD
70 VCOM
MS1328-E-00-PB
Function
I/O
I Serial Bit Clock Input Pin 3 (for SRC)
Classification
System Clock
Input
Digital Input
I Serial Data Input Pin 3 (for SRC)
I Conditional Jump Pin2
The conditional jump pin (JX2) is valid by setting control register (JX2E) to Conditional Input
“1”.
SRC UNLOCK State Output Pin
O
SRC Status
This pin outputs “H” during initial reset.
Reset Pin (for Initialization)
I
Use to initialize the AK7722. Set this pin to “L” when power-up the
System
AK7722.
I2C BUS Select Pin (Internal pull-down)
I2CSEL pin = “L”: 4-wired Interface
I
I2C Select
I2CSEL pin = “H”: I2CBus selected mode. SCL and SDA are active.
I2CSEL should be connected to “L” (VSS) or “H” (DVDD).
Test Input 2 Pin (Internal pull-down)
I
Test
This pin must be connected to VSS4.
O AVDRV Pin
Connect a 1μF capacitor between this pin and VSS4 pin. No external
Analog Output
circuits should be connected to this pin. This pin outputs “L” during initial
reset.
- Ground Pin 0V
Power Supply
- Digital Power Supply Pin 3.0~3.6V
Power Supply
Capacitor Connect Pin for SRCPLL
Connect a 1μF capacitor between this pin and VSS4 pin. This pin outputs Analog Output
O
“L” during initial reset.
- Ground Pin 0V
Power Supply
- Analog Power Supply Pin 3.0~3.6V
Power Supply
DAC2 Inverted Rch Differential Analog Output Pin
Analog Output
O
“Hi-Z” output during initial reset
DAC2 Non-inverted Rch Differential Analog Output Pin
Analog Output
O
“Hi-Z” output during initial reset
DAC2 Inverted Lch Differential Analog Output Pin
Analog Output
O
“Hi-Z” output during initial reset
DAC2 Non-inverted Lch Differential Analog Output Pin
Analog Output
O
“Hi-Z” output during initial reset
DAC1 Inverted Rch Differential Analog Output Pin
Analog Output
O
“Hi-Z” output during initial reset
DAC1 Non-inverted Rch Differential Analog Output Pin
Analog Output
O
“Hi-Z” output during initial reset
DAC1 Inverted Lch Differential Analog Output Pin
Analog Output
O
“Hi-Z” output during initial reset
DAC1 Non-inverted Lch Differential Analog Output Pin
Analog Output
O
“Hi-Z” output during initial reset
- Analog Power Supply Pin 3.0~3.6V
Power Supply
Analog
Common
Voltage
Output
pin
O
Connect 0.1μF and 2.2μF capacitors between this pin and the VSS6 pin. No
Analog Output
external circuits should be connected to this pin. This pin outputs “L”
during initial reset.
8
2011/09
[AK7722]
No.
71
72
73
74
75
76
77
78
79
80
Name
I/O
I
I
I
I
I
I
I
I
I
VSS6
A2INR
A2INL
AINR6
AINL6
AINR5
AINL5
AINR4
AINL4
AINR3
Function
Classification
Power Supply
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Ground Pin 0V
ADC2 Rch Single-ended Input Pin
ADC2 Lch Single-ended Input Pin
ADC1 Rch Single-ended Input Pin 6
ADC1 Lch Single-ended Input Pin 6
ADC1 Rch Single-ended Input Pin 5
ADC1 Lch Single-ended Input Pin 5
ADC1 Rch Single-ended Input Pin 4
ADC1 Lch Single-ended Input Pin 4
ADC1 Rch Single-ended Input Pin 3
■ Handling of Unused Pin
The following table illustrates recommended states for open pins:
Classification
Analog
Digital
Pin Name
ANL1P, AINL1N, AINR1P, AINR1N, AINL2P, AINL2N, AINR2P
AINR2N, AINL3, AINR3, AINL4, AINR4, AINL5, AINR5, AINL6, AINR6
AOUTL1P, AOUTL1N, AOUTR1P, AOUTR1N
AOUTL2P, AOUTL2N, AOUTR2P, AOUTR2N
XTO, GP1, RDY, SO, SDA(I2CSEL= “L”), CLKO, LRCKO, BICKO, SDOUT1
SDOUT2, SDOUT3, STO, UNLOCK
TESTI1, GLRCK, GBICK, SDIN5, XTI, JX0, LRCKI, BICKI, SDIN1, SDIN2
SRLRCK1, SRBICK1, SRIN1, RQN, SI, SRLRCK2, SRBICK2, SRIN2,
SRLRCK3
SRBICK3, SRIN3, TESTI2
The relationship between the I2CSEL pin and SDA pin
I2CSEL
Micro controller
L
Interface
L
I2C-bus support
H
H
MS1328-E-00-PB
9
INITRSTN
L
H
L
H
Setting
Leave Open
Leave Open
Connect to VSS
SDA
L
L
“Hi-Z”
function
2011/09
[AK7722]
ABSOLUTE MAXIMUM RATINGS
(VSS1~VSS6=0V: Note 1)
Parameter
Symbol
Power Supply Voltage
Analog
AVDD
Digital
DVDD
Input Current (except for power supply pin )
IIN
Analog Input Voltage
VINA
Digital Input Voltage
VIND
Operating Ambient Temperature
Ta
Storage Temperature
Tstg
Note 1. All indicated voltages are with respect to ground.
Note 2. VSS1-6 must be connected to the same ground plane.
min
max
Unit
-0.3
-0.3
–
-0.3
-0.3
-40
-65
4.3
4.3
±10
AVDD+0.3
DVDD+0.3
85
150
V
V
mA
V
V
ºC
ºC
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS1~VSS6=0V: Note 1)
Parameter
Symbol
min
typ
max
Unit
Power Supply Voltage
Analog
AVDD
3.0
3.3
3.6
V
Digital
DVDD
3.0
3.3
3.6
V
Note 3. The power supply sequence for AVDD and DVDD is not critical but all power supplies must be On before start
operating the AK7722.
Note 4. Do not turn off the power supply of the AK7722 with the power supply of the surrounding device turned on.
DVDD must not exceed the pull-up of SDA and SCL of I2C BUS. (The diode exists for DVDD in the SDA and
SCL pins.)
WARNING: AKM assumes no responsibility for the usage beyond the conditions in the datasheet.
MS1328-E-00-PB
10
2011/09
[AK7722]
ANALOG CHARACTERISTICS (CODEC)
■ ADC Characteristics
1. ADC1
(Ta=25ºC; AVDD=DVDD=3.3V, BITCLK=64fs; Signal frequency 1kHz; Measurement frequency = 20Hz~20kHz
@fs=48kHz; CKM mode0 (CKM[2:0]=000); BITFS[1:0]=00(64fs); with Differential Input; in SRC reset, Unless
otherwise specified.)
Parameter
min
typ
max
Unit
Resolution
24
Bits
ADC
Section
Dynamic Characteristics
S/(N+D) (-1dBFS)
82
90
dB
Dynamic Range (A-weighted)
(Note 5)
96
dB
88
S/N (A-weighted)
96
dB
88
Inter-Channel Isolation (fin=1kHz) (Note 6)
90
110
dB
DC accuracy
Channel Gain Mismatch
0.0
0.3
dB
Analog Input
Input Voltage (Differential)
(Note 7)
Vp-p
±2.00
±2.20
±2.40
Input Voltage (Single-ended)
(Note 8)
2.00
2.20
2.40
Vp-p
Input Impedance
41
62
kΩ
Note 5. S/(N+D) when -60dB FS signal is applied.
Note 6. Inter-channel isolation between AINR and AINL with –1dB FS signal input.
Note 7. AINL1P, AINL1N, AINR1P, AINR1N, AINL2P, AINL2N, AINR2P and AINR2N pins
Note 8. AINL3, AINR3, AINL4, AINR4, AINL5, AINR5, AINL6 and AINR6 pins.
Full scale output voltage is FS=AVDD×2.2/3.3.
2. ADC2
(Ta=25ºC; AVDD=DVDD=3.3V, BITCLK=64fs; Signal frequency 1kHz; Measurement frequency =20Hz~20kHz
@fs=48kHz; CKM mode0 (CKM[2:0]=000); BITFS[1:0]=00(64fs); in SRC reset, Unless otherwise specified.)
Parameter
min
typ
max
Unit
Resolution
24
Bits
ADC
Section
Dynamic Characteristics
S/(N+D) (-1dBFS)
88
dB
80
Dynamic Range (A-weighted)
(Note 9)
95
dB
87
S/N (A-weighted)
95
dB
87
Inter-Channel Isolation (fin=1kHz) (Note 10)
90
110
dB
DC accuracy
Channel Gain Mismatch
0.1
0.3
dB
Analog Input
Input Voltage
(Note 11)
2.00
2.20
2.40
Vp-p
Input Impedance
41
62
kΩ
Note 9. S/(N+D) when -60dB FS signal is applied.
Note 10. Inter-channel isolation between AINR and AINL with –1dB FS signal input.
Note 11. Full scale output voltage is FS=AVDD×2.2/3.3.
MS1328-E-00-PB
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[AK7722]
■ DAC1/2 Characteristics
(Ta=25ºC; AVDD=DVDD=3.3V; VSS1~VSS6=0V; Signal frequency 1kHz; Measurement frequency =20Hz~20kHz
@fs=48kHz; CKM[2:0]=000, BITFS[1:0]=00, in SRC Reset) Unless otherwise specified.)
Parameter
min
typ
max
Unit
Resolution
24
Bits
DAC1
DAC2
Dynamic Characteristics
S/(N+D)
(0 dBFS)
82
90
dB
Dynamic Range (A-weighted) (Note 12)
98
108
dB
S/N (A-weighted)
98
108
dB
Inter-channel Isolation (f=1kHz) (Note 13)
90
110
dB
DC accuracy
Channel Gain Mismatch
0.0
0.5
dB
Analog output
Output Voltage
(Note 14)
3.78
4.16
4.53
Vp-p
Load Resistance
5
kΩ
Load Capacitance
30
pF
Note 12. S/(N+D) when -60dBFS signal is applied.
Note 13. Indicates isolation between each DAC’s of Lch and Rch when -1dBFS signal is applied.
Note 14. Full scale differential output voltage.
SRC CHARACTERISTICS
(Ta=25ºC; AVDD = DVDD=3.3V; VSS1~VSS6=0V, data = 24bit; measurement bandwidth = 20Hz~ FSO/2; unless
otherwise specified.)
Parameter
Symbol
min
typ
max
Unit
Resolution
24
Bits
Input Sample Rate
FSI
7.35
96
kHz
Output Sample Rate
FSO
7.35
48
kHz
THD+N
(Input= 1kHz, 0dBFS)
FSO/FSI=44.1kHz/48kHz
-112
dB
FSO/FSI=44.1kHz/96kHz
-104
dB
FSO/FSI=48kHz/44.1kHz
-112
dB
FSO/FSI=48kHz/96kHz
-112
dB
FSO/FSI=48kHz/8kHz
-111
-103
dB
FSO/FSI=8kHz/48kHz
-113
dB
FSO/FSI=8kHz/44.1kHz
-100
dB
Dynamic Range (Input= 1kHz, -60dBFS)
FSO/FSI=44.1kHz/48kHz
113
dB
FSO/FSI=44.1kHz/96kHz
113
dB
FSO/FSI=48kHz/44.1kHz
113
dB
FSO/FSI=48kHz/96kHz
113
dB
FSO/FSI=48kHz/8kHz
109
112
dB
FSO/FSI=8kHz/48kHz
113
dB
FSO/FSI=8kHz/44.1kHz
113
dB
Dynamic Range (Input= 1kHz, -60dBFS, A-weighted
FSO/FSI=44.1kHz/48kHz
115
dB
Ratio between Input and Output Sample Rate
FSO/FSI
0.167
6
-
MS1328-E-00-PB
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[AK7722]
DC CHARACTERISTICS
(Ta=-40ºC~85ºC; AVDD=DVDD=3.0~3.6V)
Parameter
Symbol
min
High Level Input Voltage
(Note 15)
VIH
80%DVDD
Low Level Input Voltage
(Note 15)
VIL
SCL,SDA High Level Input Voltage
VIH
70%DVDD
SCL,SDA Low Level Input Voltage
VIL
VOH
DVDD-0.5
High Level Output Voltage Iout=-100μA
VOL
Low Level Output Voltage Iout=100μA (Note 16)
SDA Low Level Output Voltage Iout=3mA
VOL
Input Leak Current
(Note 17)
Iin
Input Leak Current (pull-down pin)
(Note 18)
Iid
Input Leak Current (XTI pin)
Iix
typ
max
20%DVDD
30%DVDD
0.5
0.4
±10
22
26
Unit
V
V
V
V
V
V
V
μA
μA
μA
Note 15. SCL and SDA pins are not included. (SCLK pins are included)
Note 16. The SDA pin is not included.
Note 17. Pull-down pins, and the XTI pin is not included.
Note 18. TESTI1 and TESTI2 pins are internal pulled-down pin. (Typ150kΩ)
POWER CONSUMPTION
(Ta=25ºC; AVDD=DVDD=3.0~3.6V (when typ=3.3V, max=3.6V))
Parameter
min
typ
max
Unit
Power Supply Current
(Note 19)
55
AVDD
mA
65
DVDD
mA
120
AVDD+DVDD
180
mA
2
INITRSTN pin= “L” (reference) (Note 20)
mA
Note 19. The current of DVDD changes depending on the system frequency and contents of the DSP program.
Note 20. This is a reference value when using a crystal oscillator. Since most of the current are applied to the oscillator
section in the initial reset state, the value may vary according to the crystal type and the external circuit. This is
a “reference data” only.
MS1328-E-00-PB
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[AK7722]
DIGITAL FILTER CHARACTERISTICS
■ ADC Block (ADC1/2)
1. fs=48kHz
(Ta=-40ºC ~85ºC, AVDD=DVDD=3.0~3.6V, fs=48kHz, Note 21)
Parameter
Symbol
min
typ
max
Unit
Passband (±0.1dB) (Note 22)
0
18.9
PB
kHz
(-1.0dB)
kHz
20.0
(-3.0dB)
kHz
23.0
Stopband
SB
kHz
28
Passband Ripple
(Note 22)
PR
dB
±0.04
Stopband Attenuation (Note 23, Note 24)
SA
dB
68
Group Delay Distortion
ΔGD
0
μs
Group Delay
(Ts=1/fs)
GD
16
Ts
Note 21. The passband and stopband frequencies are proportional to fs (system sampling rate). High-pass filter
characteristics are not included.
Note 22. The passband is from DC to 18.9kHz when fs=48kHz.
Note 23. The stopband is 28kHz to 3.044MHz when fs=48kHz.
Note 24. When fs = 48kHz, the analog modulator samples the input signal at 512kHz. There is no attenuation of an
input signal in band (n x 3.072MHz ±28kHz; n=0, 1, 2, 3…) of integer times of the sampling frequency by the
digital filter.
■ DAC1-2
(Ta=-40 ºC ~85 ºC; AVDD=DVDD=3.0~3.6V; fs=48kHz)
Parameter
Symbol
min
typ
max
Unit
Passband (±0.05dB) (Note 25)
PB
0
21.7
kHz
(-6.0dB)
24
kHz
Stopband
(Note 25)
SB
26.2
kHz
Passband Ripple
PR
±0.01
dB
Stopband Attenuation
SA
64
dB
Group Delay (Ts=1/fs) (Note 26)
GD
24
Ts
Digital Filter + Analog Filter
Amplitude Characteristics 20Hz~20.0kHz
±0.5
dB
Note 25. The pass band and stop band frequencies are proportional to “fs” (system sampling rate), and represents
PB=0.4535fs (@±0.05dB) and SB=0.5465fs, respectively.
Note 26. The digital filter delay is calculated as the time from setting data into the input register until an analog signal is
output.
MS1328-E-00-PB
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2011/09
[AK7722]
■ SRC
(Ta=-40ºC ~85ºC; AVDD=DVDD=3.0~3.6V)
Parameter
Symbol
min
typ
max
Unit
Passband
0.980≤FSO/FSI≤6.000
PB
0
0.4583FSI
kHz
0.900≤FSO/FSI<0.990
PB
0
0.4167FSI
0.450≤FSO/FSI<0.910
PB
0
0.2177FSI
0.225≤FSO/FSI<0.455
PB
0
0.0917FSI
0.167≤FSO/FSI<0.227
PB
0
0.0917FSI
Stopband
0.980≤FSO/FSI≤6.000
SB
0.5417FSI
kHz
0.900≤FSO/FSI<0.990
SB
0.5021FSI
0.450≤FSO/FSI<0.910
SB
0.2813FSI
0.225≤FSO/FSI<0.455
SB
0.1573FSI
0.167≤FSO/FSI<0.227
SB
0.1354FSI
Passband Ripple
0.225≤FSO/FSI<0.455
PR
±0.0100
dB
0.167≤FSO/FSI<0.227
PR
±0.0612
Stopband Attenuation
SA
92.3
dB
Group Delay (Ts=1/fs) (Note 27)
GD
56
Ts
Note 27. This delay is the a period from the rising edge of SRLRCKn, just after the data is input, to the rising edge of
LRCLKO, just after the data is output, when there is no phase difference between SRLRCKn and LRCLKO.
MS1328-E-00-PB
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2011/09
[AK7722]
SWITCHING CHARACTERISTICS
■ System Clock
(Ta=-40ºC~85ºC; AVDD=DVDD=3.0~3.6V, VSS1~VSS6=0V)
Parameter
Symbol
min
XTI CKM[2:0]=000, 001, 010
a) with a Crystal Oscillator:
fXTI
CKM[2:0]=000 fs=44.1kHz
fs=48kHz
fXTI
CKM[2:0]=001 fs=44.1kHz
fs=48kHz
b) with an External Clock
Duty Cycle
40
fXTI
CKM[2:0]=000, 010 fs=44.1kHz
11.0
fs=48kHz
fXTI
CKM[2:0]=001 fs=44.1kHz
16.5
fs-48kHz
LRCKI Frequency
(Note 28)
fs
7.35
typ
max
Unit
11.2896
12.288
16.9344
18.432
-
MHz
-
MHz
50
11.2896
12.288
16.9344
18.432
60
%
MHz
12.4
18.6
48
MHz
kHz
BICKI Frequency
High Level Width
tBCLKH
64
ns
Low Level Width
tBCLKL
64
ns
Frequency
0.23
3.072
3.1
MHz
fBCLK
Note 28. LRCKI frequency and sampling rate (fs) should be the same.
Note 29. When BICKI is the source of master clock, it should be synchronized to LRCKI and the frequency is stable.
MS1328-E-00-PB
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2011/09
[AK7722]
■ SRC Input Clock
(Ta=-40ºC~85ºC; AVDD=DVDD=3.0~3.6V; VSS1~VSS6=0V)
Parameter
Symbol
min
fs
7.35
SRLRCKn Frequency
typ
max
96
Unit
kHz
3.072
6.144
MHz
ns
ns
(Ta=-40 ºC ~85 ºC; AVDD=DVDD=3.0~3.6V; VSS1~VSS6=0V)
Parameter
Symbol
min
fs
7.35
GLRCK Frequency
typ
max
12
Unit
kHz
GBICK Frequency
Frequency
High Level Width
Low Level Width
SRBICKn Frequency
Frequency
High Level Width
Low Level Width
fBCLK
tBCLKH
tBCLKL
0.23
32
32
■ GSRC Input Clock
fBCLK
tBCLKH
tBCLKL
230
100
100
512
780
kHz
ns
ns
(Ta=-40ºC~85ºC; AVDD=DVDD=3.0~3.6V)
Parameter
Symbol
INITRSTN
(Note 30)
tRST
Note 30. It must be “L” when power-up the AK7722.
min
600
typ
max
Unit
ns
■ Reset
MS1328-E-00-PB
17
2011/09
[AK7722]
■ Audio Interface (SDIN1-2, SRIN1-3, SDOUT1-3)
(Ta=-40ºC~85ºC; AVDD=DVDD=3.0~3.6V, CL=20pF)
Parameter
DSP Section Input SDIN1-2, SRIN1-3
(Note 31)
Delay Time from BICKI “↑” to LRCKI
(Note 32)
Symbol
tBLRD
min
typ
max
Unit
20
ns
Delay Time from LRCKI to BICKI “↑”
(Note 32)
tLRBD
20
Serial Data Input Latch Setup Time
tBSIDS
80
Serial Data Input Latch Hold Time
tBSIDH
80
SRC Section Input SRIN1-3
(Note 33)
Delay Time from SRBICK1-3 “↑” to SRLRCK1-3
(Note 34)
tBLRD
20
Delay Time from SRLRCK1-3 to SRBICK1-3 “↑”
(Note 34)
tLRBD
20
Serial Data Input Latch Setup Time
tBSIDS
40
Serial Data Input Latch Hold Time
tBSIDH
40
Output SDOUT1-3
(Note 31)
BICKO Frequency
fBCLK
64
BICKO Duty Factor
50
Delay Time from BICKO “↓” to LRCKO
(Note 35)
tBLRD
-20
40
Delay Time from LRCKI to Serial Data Output
(Note 36)
tLRD
80
Delay Time from BICKI to Serial Data Output
(Note 33)
tBSOD
80
Delay Time from LRCKO to Serial Data Output
(Note 36)
tLRD
80
Delay Time from BICKO to Serial Data Output
(Note 33)
tBSOD
80
SDINn → SDOUTn (n=1-2)
(Note 37)
Delay Time from SDINn to SDOUTn Data Output
tIOD
60
Note 31. BICKI=SRBICKn (n=1, 2, 3) in CKM mode 4.
Note 32. BICKI edge must not occur at the same time as LRCKI edge. The BICKI polarity is inverted in PCM mode
0/2.
Note 33. Except CKM mode 4
Note 34. SRBICK1-3 edge must not occur at the same time as SRLRCK1-3 edge. When BIEDGE bit= “1”, this value is
for SRBICK1-3 “↓” since SRBICK1-3 are polarity reversal.
Note 35. When SELBCK bit= “1”, this value is for BICKO “↑” since BICKO is polarity reversal.
Note 36. Except I2S.
Note 37. SDIN1 → SDOUT1: Control Register Setting, SELDO1[1:0]=1h, OUT1E bit= “1”
SDIN2/JX1 → SDOUT2: Control Register Setting, SELDO2[1:0]=1h, OUT2E bit= “1”
SRIN1/SDIN3 → SDOUT3: Control Register Setting, SELDI3 bit = “1”, SELDO3[1:0]=1h, OUT3E bit= “1”
MS1328-E-00-PB
18
2011/09
ns
ns
ns
ns
ns
ns
ns
fs
%
ns
ns
ns
ns
ns
ns
[AK7722]
■ Microprocessor Interface
(Ta=-40ºC~85ºC; AVDD=DVDD=3.0~3.6V; CL=20pF)
Parameter
Symbol
Microprocessor Interface Signal
RQN Fall Time
tWRF
RQN Rise Time
tWRR
SCLK Fall Time
tSF
SCLK Rise Time
tSR
SCLK Frequency
fSCLK
SCLK Low Level Width
tSCLKL
SCLK High Level Width
tSCLKH
Microprocessor → AK7722
RQN High Level Width
tWRQH
From RQN “↓” to SCLK “↓”
tWSC
From SCLK “↑” to RQN “↑”
tSCW
SI Latch Setup Time
tSIS
SI Latch Hold Time
tSIH
AK7722 → Microprocessor
Delay Time from SCLK “↓”to SO Output
tSOS
Hold Time from SCLK “↑” to SO Output (Note 38)
tSOH
Note 38. Except for, when writing to 8th bit of command code.
min
typ
max
Unit
30
30
30
30
2.1
200
200
ns
ns
ns
ns
MHz
ns
ns
500
500
800
200
200
ns
ns
ns
ns
ns
200
ns
ns
200
■ I2C BUS Interface
(Ta=-40ºC~85ºC; AVDD=DVDD=3.0~3.6V)
Parameter
I2C Timing
SCL clock frequency
Bus Free Time Between Transmissions
Start Condition Hold Time
(prior to first Clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed
by Input Filter
Capacitive load on bus
Note 39. I2C-bus is a trademark of NXP B.V.
MS1328-E-00-PB
Symbol
min
typ
max
Unit
400
fSCL
tBUF
1.3
kHz
μs
tHD:STA
0.6
μs
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
1.3
0.6
0.6
0
0.1
μs
μs
μs
μs
μs
μs
μs
μs
tSP
0.3
0.3
0.6
0
Cb
19
0.9
50
ns
400
pF
2011/09
[AK7722]
■ Timing Diagram
1/fXTI
1/fXTI
tXTI=1/fXTI
XTI
VIH
VIL
1/fs
ts=1/fs
1/fs
LRCKI
VIH
VIL
1/fBCLK
1/fBCLK
tBCLK=1/fBCLK
VIH
BICKI
VIL
tBCLKH
tBCLKL
Figure 3. System Clock
INITRSTN
tRST
VIL
Figure 4. Reset
Note 40. The INITRSTN pin must be “L” when power-up/power-down the AK7722.
MS1328-E-00-PB
- 20 -
2011/09
[AK7722]
1) Audio Interface
VIH
VIL
LRCKI
tBLRD
tLRBD
VIH
VIL
BICKI
tBSIDS
tBSIDH
VIH
VIL
SDINn
n=1, 2
Figure 5. DSP Block Input Interface in Slave Mode
50%DVDD
LRCKO
tMBL
tMBL
50%DVDD
BICKO
tBSIDS
tBSIDH
VIH
VIL
SDINn
n=1, 2
Figure 6. DSP Block Input Interface in Master Mode
VIH
VIL
SRLRCKn
tBLRD
tLRBD
VIH
VIL
SRBICKn
tBSIDS
tBSIDH
VIH
VIL
SRINn
Figure 7. SRC Block Input Interface
MS1328-E-00-PB
- 21 -
2011/09
[AK7722]
VIH
VIL
GLRCK
tBLRD
tLRBD
VIH
VIL
GBICK
tBSIDS
tBSIDH
VIH
VIL
SDIN5
Figure 8. GSRC Block Input Interface
VIH
VIL
LRCKI
tLRD
VIH
VIL
BICKI
tLRD
tBSOD
SDOUTn
n=1, 2, 3
tBSOD
50%DVDD
Figure 9. Output Interface in Slave Mode
MS1328-E-00-PB
- 22 -
2011/09
[AK7722]
2) Micro-controller Interface
VIH
VIL
RQN
tWRF
tWRR
tSF
tSR
VIH
VIL
SCLK
tSCLKL
tSCLKH
1/fSCLK
1/fSCLK
INITRSTN
VIH
VIL
RQN
VIH
VIL
tRST
tIRRQ
Figure 10. Micro-controller Interface Signal
VIH
tWRQH
RQN
VIL
VIH
SI
VIL
tSIS
tSIH
VIH
SCLK
VIL
tWSC
tSCW
tWSC
tSCW
Figure 11. Micro-controller → AK7722
MS1328-E-00-PB
- 23 -
2011/09
[AK7722]
VIH
SCLK
VIL
VIH
SO
VIL
tSOH
tSOS
Figure 12. AK7722 → Micro-controller
3) I2C-Bus Interface
VIH
SDA
VIL
tBUF
tLOW
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
tSU:DAT
tSU:STA
tSU:STO
Start
Stop
Start
2
Figure 13. I C-bus Interface
MS1328-E-00-PB
- 24 -
2011/09
[AK7722]
PACKAGE
80pin LQFP (Unit: mm)
1.60 Max.
14.0±0.2
12.0
40
12.0
61
14.0±0.
0.05~0.15
41
60
80
21
20
1
0.5
0.22±0.05
0.09~0.20
0.10 M
1.0
S
0°~10°
0.60±0.15
0.10 S
■ Materials and Lead Specification
Package:
Lead frame:
Lead-finish:
MS1328-E-00-PB
Epoxy
Copper
Soldering (Pb free) plate
- 25 -
2011/09
[AK7722]
MARKING
AK7722VQ
XXXXXXX
1) Pin#1 indication
2) Date Code: XXXXXXX (7 digits)
3) Marking Code: AK7722VQ
REVISION HISTORY
Date (YY/MM/DD)
11/09/09
MS1328-E-00-PB
Revision
00
Reason
First Edition
Page
- 26 -
Contents
2011/09
[AK7722]
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z Descriptions of external circuits, application circuits, software and other related information contained in this document are
provided only to illustrate the operation and application examples of the semiconductor products. You are fully responsible
for the incorporation of these external circuits, application circuits, software and other related information in the design of
your equipments. AKM assumes no responsibility for any losses incurred by you or third parties arising from the use of
these information herein. AKM assumes no liability for infringement of any patent, intellectual property, or other rights in
the application or use of such information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or
strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other
hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use approved with
the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to r
esult, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system conta
ining it, and which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to fun
ction or perform may reasonably be expected to result in loss of life or in significant injury or damage to
person or property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places the
product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or
distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims
arising from the use of said product in the absence of such notification.
MS1328-E-00-PB
- 27 -
2011/09
[AK7722]
Thank you for your access to AKM products information.
More detail product information is available, please contact our
sales office or authorized distributors.
MS1328-E-00-PB
- 28 -
2011/09