AK4712EN

[AKD4712-A]
AKD4712-A
AK4712 Evaluation Board Rev.0
GENERAL DESCRIPTION
AKD4712 is an evaluation board for quickly evaluating the AK4712, a High Definition A/V cap-less line
driver.
Evaluation requires audio/video analog analyzer/generator and a power supply.
„ Ordering guide
AKD4712-A ---
AK4712 Evaluation Board
(Control software and USB cable are included in this package.)
FUNCTION
• RCA connectors for analog audio output
• XLR connectors for analog audio input
• RCA connectors for SD/HD video input/output
• USB connector for serial control interface
+5V
+5V→+3.3V
Regulator
+5V→+3.3V
VSS
Regulator
VD1
VD2
VSS2
VVD
AINL+
AINL-
TVOUTL
AINR+
TVOUTR
AINR-
AK4712
ENCRCA
RCAVOUT
ENCPb
HDPb
ENCPr
HDPr
ENCY
HDY
USB
PIC18F4550
PORT
Regulator
5.0V
3.3V
Figure 1. AKD4712 Block Diagram
※Circuit diagram and PCB layout are attached at the end of this manual.
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EVALUATION BOARD MANUAL
„ Operation sequence
1) Set up the power supply lines.
Name of
Jack
Color of
Jack
Voltage
Used for
+5V
Yellow
+5V
Power supply of
AK4712
VD1
Red
+3.13∼+3.47
VD1 of AK4712
VD2
Red
+3.13∼+3.47V
VD2 of AK4712
VVD
Red
+3.13∼+3.47V
VVD of AK4712
HDVVD of AK4712
D3.3V
Red
+3.13 ∼ 3.47V
Logic Power supply
VSS
Black
0V
Analog Ground
VSS2
Black
0V
Analog Ground
DGND
Black
0V
Digital Ground
Comments
Should always be connected
Should be connected when JP9 (VD1) is OPEN.
Should be open when JP9 (VD1) is SHORT.
Should be connected when JP11 (VD2) is
OPEN.
Should be open when R51 (VD2) is SHORT.
Should be connected when JP12 (VVD) is
OPEN.
Should be open when JP12(VVD) is SHORT.
Should be connected when JP10 (D3.3V) is
OPEN.
Should be open when JP10 (D3.3V) is SHORT.
Should always be connected
Should always be connected when VD2 is
connected.
Should be connected when JP8 (GND) is
OPEN.
Should be open when JP8(GND) is SHORT.
Default of
Jack
+5V
SHORT
SHORT
SHORT
SHORT
0V
open
open
Table 1.Power supply lines
Each supply line should be distributed from the power supply unit.
2)
Set-up jumper pins. (See the following.)
3) Power on.
AK4712 should be reset once by bringing SW1 “L” upon power-up.
„ Jumper pin settings
[JP1] (AINL+_SEL): AINL+ pin input select
INPUT1:
R=20kΩ <Default>
INPUT2:
R=0Ω
[JP2] (AINR+_SEL): AINR+ pin input select
INPUT1:
R=20kΩ <Default>
INPUT2:
R=0Ω
[JP3] (MUTEN/SCL_SEL): SDA/MUTEN pin input select
SDA:
SDA
MUTEN:
MUTEN <Default>
*When I2CSEL=”L”(Hard Wired), SDA/MUTEN pin is used for audio mute.
[JP4] (UVP/SCL_SEL): SCL/UVP (Under Voltage Protection)
SCL:
SCL <Default>
UVP:
UVP
*When I2CSEL=”L”, UVP pin can be used for Under Voltage Protection.
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[JP5] (GND): AINL- pin input select
OPEN:
J5 (AINL): 3pin <Default>
SHORT: GND (Not to use)
[JP6] (GND): AINR- pin input select
OPEN:
J13 (AINR): 3pin <Default>
SHORT: GND (Not to use)
[JP7] Not for use
[JP8] (GND): Analog ground and Digital ground
OPEN:
Separated
SHORT: Common. (The connector “DGND” can be open.) <Default>
[JP9] (VD1): Regulator (+3.3V) or VD1 connector
OPEN:
VD1 pin is supplied from VD1 connector.
SHORT: VD1 pin is supplied from regulator (+3.3V). (The connector “VD1” can be open.) <Default>
[JP10] (D3.3V): Regulator (+3.3V) or D3.3V connector
OPEN:
Logic voltage is supplied from D3.3V connector.
SHORT: Logic voltage is supplied form regulator (+3.3V). (The connector “VCC” can be open.) <Default>
[JP11] (VD2): Regulator (+3.3V) or VD2 connector
OPEN:
VD2 pin is supplied from VD2 connector.
SHORT: VD2 pin is supplied from regulator (+3.3V). (The connector “VD1” can be open.) <Default>
[JP12] (VVD): Regulator (+3.3V) or VVD connector
OPEN:
VVD and HVVD pins are supplied from VVD connector.
SHORT: VVD and HVVD pins are supplied from regulator (+3.3V)
(The connector “VVD” can be open.) <Default>
[JP13] (REG-SEL): Regulator (+3.3V) from T2 or T3
T2:
Regulator supplied from T2. <Default>
T3:
Regulator supplied from T3.
The T2 regulator can supply 3.3V to all circuits by shorting JP9, JP10, JP11 and JP12 and supplying 5V to +5V
connector.
„ DIP SW Function
No.
Pin
1
MUTEN
2
I2CSEL
OFF
ON
Audio mute MUTEN bit
L: Mute
H: Unmute (default)
I2C Control Enable pin
L: Disable (Hard Wired) (default)
H: Enable (I2C)
Default
ON
OFF
When the I2CSEL pin = “L” (Hard Wired), the SDA/MUTEN pin is used for audio mute. MUTEN bit is ignored.
MUTEN pin
L
H
Audio Output Status
Mute
Unmute
(1) Hard Wired Mode
When the I2CSEL pin= “H” (I2C), MUTEN bit is used for audio mute. The SDA/MUTEN pin is used for Control Data Input.
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MUTEN bit
0
1
Audio Output Status
Mute
Unmute
(default)
(2) I2C Mode
„ Toggle SW Function
[SW2] (PDN): Resets AK4712. Keep “H” during normal operation.
„ Board Control
The AK4712 can be controlled via USB PORT with a PC. Connect PORT1 with PC by USB cable included in
AKD4712-A package. The control software is also included.
„ Analog Input/Output List
Audio
Video
Input
Output
Input
Output
Signal Name
J5(AINL+, AINL-), J12(AINR+, AINR-)
J4 (TVOUTL), J8 (TVOUTR)
J2 (ENCY), J9 (ENCPr), J6 (ENCPb),
J13 (ENCRCA)
J3 (HDY), J7 (HDPb), J11(HDPr),
J14(RCAVOUT)
Note
Typ. 2Vrms
Typ. 2Vrms
Max. 1.25Vpp
Max. 2.5Vpp
Table 2. Analog Input/Output List
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Control Software Manual
■ Evaluation Board and Control Software Settings
1.
Set up the evaluation board as needed, according to the previous terms.
2.
Connect the evaluation board to a PC with USB cable.
USB control is recognized as HID (Human Interface Device) on PC.
When it is not recognized properly, please reconnect the evaluation board to PC.
3.
Insert the CD-ROM labeled “AKD4712-A Evaluation Kit” into the CD-ROM drive.
4.
Access the CD-ROM drive and double-click the icon “akd4712-A.exe” to open the control program.
5.
Begin evaluation by following the procedure below.
[Supported OS]
Windows 2000 / XP
64bit OS is not supported.
Windows 95 / 98 / Me / NT are not supported.
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■ Operation Screen
1. Start up the control program following the above procedure.
2. After power is supplied to the evaluation board, AK4712 must be reset once by bringing SW2 (AK4712-PDN) from
“L” to “H”.
3. The control program operation screen is shown below
Figure 2. Control program window
■ Operation Overview
Register map and testing are controlled by this control software. These controls may be selected by the upper tabs.
Frequently used buttons, such as the register initializing button “Write Default”, are located outside of the switching tab
window. Refer to the “■ Dialog Box” section for details of each dialog box setting.
■ Button Functions
1. [Port Reset]: Reset connection to PC
Click this button after the control software starts up and the evaluation board is connected to the PC via USB cable.
2. [Write Default]: Register Initialization
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Use this button to initialize the registers when the device is reset by a hardware reset.
3. [All Write]: Execute write command for all registers displayed.
4. [All Read]: Execute read command for all registers displayed.
5. [Save]: Save current register settings to a file.
6. [Load]: Execute data write from a saved file.
7. [All Reg Write]: [All Reg Write] dialog box pops up.
8. [Data R/W]: [Data R/W] dialog box pops up.
9. [Read]: Read current register settings and display to the Register area (on the right of the main window).
This is different from [All Read] button as it does not reflect to the register map. It only displays the current register
values in hexadecimal numbers.
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■ Tab Functions
1. [REG]: Register Map
This tab is for register read and write.
Each bit on the register map is a push-button switch.
Button Down indicates “H” or “1” and the bit name is shown in red (when read-only the name is shown in dark red).
Button Up indicates “L” or “0” and the bit name is shown in blue (when read-only the name is shown in gray)
Grayed out registers are Read-Only registers. They can not be controlled.
The registers which are not defined on the datasheet are indicated as “---”.
Figure 3. [REG] window
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1-1. [Write]: Data Write Dialog
Select the [Write] button located on the right of the each corresponding address when changing two or more bits on
the same address simultaneously.
Click the [Write] button for the register pop-up dialog box shown below.
When the checkbox next to the register is checked, the data will become “H” or “1”. When the checkbox is not
checked, the data will become “L” or “0”. Click [OK] to write the set values to the registers, or click [Cancel] to
cancel this setting.
Figure 4. [Register Set] window
1-2. [Read]: Data Read
Click the [Read] button located on the right of the each corresponding address to execute a register read.
The current register value will be displayed in the register window as well as in the upper right hand DEBUG
window.
Button Down indicates “H” or “1” and the bit name is shown in red (when read only the bit name is shown in dark
red).
Button Up indicates “L” or “0” and the bit name is shown in blue (when read only the bit name is shown in gray)
Please be aware that button statuses will be changed by a Read command.
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2. [Tool]: Testing Tools
Evaluation testing tools are available in this tab.
Click the corresponding button for each testing tool.
Figure 5. [Tool] window
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2-1. [Repeat Test]: Repeat Test Dialog
Click the [Repeat Test] button in the Tool tab to open the repeat test dialog shown below.
A write repeat test can be executed by this dialog.
Figure 6. [Repeat Test] window
[Start] Button
: Start repeat test.
A dialog for saving a file of the test result will open when this button is clicked.
Name the file.
Test will start after inserting a filename.
[Close] Button
: Close dialog and finish process.
[Address] Box
: Input write data address in hexadecimal numbers.
[Start Data] Box
: Input start data in hexadecimal numbers.
[End Data] Box
: Input end data in hexadecimal numbers.
[Step] Box
: Input data write step interval.
[Repeat Count] Box : Input number of repeat cycles for the test writing.
[Up and Down] Box : Data write flow is changed as below.
• Checked: Writes in step interval from the start data to the end data and turns back at the end data to the
start data.
[Example]
Start Data = 00, End Data = 05, Step = 1, [ ]…for 1 count.
Data flow:
[00→01→02→03→04→05→05→04→03→02→01→00] x Repeat Count Number
• Not checked: Writes in step interval from the start data to the end data and finishes writing.
[Example]
Start Data = 00, End Data = 05, Step = 1, [ ]…for 1 count.
Data flow:
[00→01→02→03→04→05] x Repeat Count Number
[Sampling Frequency] Box: Select sampling frequency from 44.1kHz/48kHz
[Count] Box
: Indicates the count number during a repeat test.
[Lch Level] Box : Indicates the Lch Level during a repeat test.
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2-2. [Loop Setting]: Loop Dialog
Click the [Loop Setting] button in the Tool tab to open the loop setting dialog shown below.
A write test can be executed.
Figure 7. [Loop] window
[ OK ] Button
[ Cancel ] Button
[ Address ] Box
[ Start Data ] Box
[ End Data ] Box
[ Interval ] Box
[ Step ] Box
[ Mode Select ] Box
: Start loop test.
: Close dialog and finish process.
: Input data write address in hexadecimal numbers.
: Input start data in hexadecimal numbers.
: Input end data in hexadecimal numbers.
: Input data write interval time.
: Input data write step interval.
: Mode select check box.
• Checked:
Write in step interval from the start data to the end data and turn back at the end data to
start data.
[Example]
Start Data = 00, End Data = 05, Step = 1
Data flow: 00→01→02→03→04→05→05→04→03→02→01→00
• Not Checked: Write in step interval from the start data to the end data and finish write.
[Example]
Start Data = 00, End Data = 05, Step = 1
Data flow: 00→01→02→03→04→05
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■ Dialog Box
1. [All Req Write]: All Reg Write dialog box
Click [All Reg Write] button in the main window to open register setting file window shown below.
Register setting files saved by [SAVE] button may be applied.
Figure 8. [All Reg Write] window
[Open (left)]: Select a register setting file (*.akr).
[Write]: Execute register write with selected setting file.
[Write All]: Execute register write with all selected setting files.
Selected files are executed in descending order.
[Help]: Open help window.
[Save]: Save register setting file assignment. File name is “*.mar”.
[Open (right)]: Open saved register setting file assignment “*. mar”.
[Close]: Close dialog box and finish process.
~ Operating Suggestions ~
1.
2.
Files saved by [Save] button and opened by [Open] button on the right of the dialog “*.mar” should be stored in
the same folder.
When register settings are changed by [Save] button in the main window, re-read the file to reflect new register
settings.
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2. [Data R/W]: Data R/W Dialog Box
Click the [Data R/W] button in the main window for data read/write dialog box.
Data is written to the specified address.
Figure 9. [Data R/W] window
[Address] Box: Input data write address in hexadecimal numbers.
[Data] Box : Input write data in hexadecimal numbers.
[Mask] Box : Input mask data in hexadecimal numbers.
This value “ANDed” with the write data becomes the input data.
[Write]: Write data generated from Data and Mask value is written to the address specified in “Address” box.
[Read]: Read data from the address specified in “Address” box.
The result will be shown in the Read Data Box in hexadecimal numbers.
[Close]: Close dialog box and finish process.
Data write will not be executed unless [Write] is clicked.
*The register map will be updated after executing the [Write] or [Read] command.
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MEASUREMENT RESULTS
„ Audio
[Measurement condition]
• Measurement unit : Audio Precision SYS-2722
• BW
: 20Hz∼20kHz
• Power Supply
: +5V=5V, VD1=3.3V, VD2=3.3V, VVD=3.3V
• Interface
: Input: Cannon, Output: BNC
• Temperature
: Room
• Volume Gain
: 0dB
• Measurement signal line path: AINL/AINR → TVOUTL/TVOUTR
Parameter
Input signal
Measurement filter
20kLPF
Results
Lch [dB]
104.2
Results
Rch [dB]
104.6
S/(N+D)
(At 2Vrms Output)
DR
S/N
1kHz, 0dBFS
1kHz, -60dBFS
No input
22kLPF, A-weighted
22kLPF, A-weighted
109.2
109.2
109.1
109.1
Plots
Figure 1-1. FFT (1kHz, 0dBFS input) at 2Vrms output
Figure 1-2. FFT (1kHz, -60dBFS input)
Figure 1-3. FFT (Noise floor)
Figure 1-4. THD+N vs. Input Level (fin=1kHz)
Figure 1-5. THD+N vs. fin (Input Level=0dBFS)
Figure 1-6. Linearity (fin=1kHz)
Figure 1-7. Frequency Response (Input Level=0dBFS)
Figure 1-8. Crosstalk (Input Level=0dBFS)
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„ Video
[Measurement condition]
• Signal Generator : Sony Tectronix TG2000
• Measurement unit : Sony Tectronix VM700T
• Power Supply
: +5V=5V, VD1=3.3V, VD2=3.3V, VVD=3.3V
• Interface
: Input: BNC, Output: BNC
• Temperature
: Room
• Measurement signal line path: S/N: ENCRCA → RCAVOUT
DG, DP: ENCRCA → RCAVOUT
Parameter
S/N
Input Signal
0% Flat Field
DG
Modulated 5 step
DP
Modulated 5 step
Measurement Filter
BW=15kHz to 5MHz
Filter=Uni-Weighted
Results
75.2
Min: 0.00
Max: 1.34
Min: -0.04
Max: 0.16
Unit
dB
%
deg.
Plots
Figure 2-1. Noise spectrum SD/HD (Input=0% Flat Field, BW=15kHz to 5MHz, Filter=Uni-Weighted)
Figure 2-2. DG, DP (Input= Modulated 5 step)
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Plots (Audio)
AK4712 AINL/AINR Æ TVOUTL/TVOUTR: FFT: fin=1KHz, Input Level=0dB
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
-80
A
-100
-90
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 1 - 1. FFT (fin=1kHz, Input Level=0dB)
AK4712 AINL/AINR Æ TVOUTL/TVOUTR: FFT: fin=1KHz, Input Level=-60dB
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
-80
A
-100
-90
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 1 - 2. FFT (fin=1kHz Input Level=-60dB)
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AK4712 AINL/AINR Æ TVOUTL/TVOUTR: FFT: No-input
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
-80
A
-100
-90
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 1 - 3. FFT (Noise Floor)
AK4712 AINL/AINR Æ TVOUTL/TVOUTR: THD+N Amplitude vs Input Amplitude: fin=1KHz
-80
-84
-88
-92
-96
d
B
r
-100
A
-104
-108
-112
-116
-120
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
Figure 1 - 4. THD+N vs. Input level (fin=1kHz)
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AK4712 AINL/AINR Æ TVOUTL/TVOUTR: THD+N Amplitude vs Input Frequency: Input Level=0dB
-80
-84
-88
-92
-96
d
B
r
-100
A
-104
-108
-112
-116
-120
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 1 - 5. THD+N vs. Input Frequency (Input level=0dB)
AK4712 AINL/AINR Æ TVOUTL/TVOUTR: Linearity: fin=1KHz
+0
-10
-20
-30
-40
-50
d
B
r
A
-60
-70
-80
-90
-100
-110
-120
-130
-140
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
Figure 1 - 6. Linearity (fin=1kHz)
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AK4712 AINL/AINR Æ TVOUTL/TVOUTR: Frequency Response: Input Level=0dBr
+0.5
+0.45
+0.4
+0.35
+0.3
+0.25
+0.2
+0.15
+0.1
d
B
r
+0.05
A
-0.05
+0
-0.1
-0.15
-0.2
-0.25
-0.3
-0.35
-0.4
-0.45
-0.5
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 1 - 7. Frequency Response (Input level=0dB)
AK4712 AINL/AINR Æ TVOUTL/TVOUTR: Crosstalk: fin=1KHz, Input Level=0dBr / No-input
-70
-75
-80
-85
-90
-95
-100
d
B
-105
-110
-115
-120
-125
-130
-135
-140
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 1 - 8. Crosstalk (Input level=0dB)
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Plots(Video)
AK4712 ENCV Æ TVOUT: S/N: Input Signal=0% Flat Field, BW=15kHz to 5MHz, Filter=Uni-Weighted
Figure 2 - 1a. RCAVOUT Noise spectrum (Input=0% Flat Field, BW=15kHz to 5MHz, Filter=Uni-Weighted)
Figure 2 - 1b. HDY Noise spectrum (Input=0% Flat Field, BW=15kHz to 5MHz, Filter=Uni-Weighted)
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Figure 2 - 1c. HDPr Noise spectrum (Input=0% Flat Field, BW=15kHz to 5MHz, Filter=Uni-Weighted)
Figure 2 - 1d. HDPb Noise spectrum (Input=0% Flat Field, BW=15kHz to 5MHz, Filter=Uni-Weighted)
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AK4712 ENCRCA Æ RCAVOUT: DG, DP: Input Signal=Modulated 5 step
Figure 2 - 2. DG, DP (Input Signal= Modulated 5 step)
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Revision History
Date
(YY/MM/DD)
12/06/19
Manual
Revision
KM111300
Board
Reason
Revision
First Edition
0
Contents
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products. You
are fully responsible for the incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent,
intellectual property, or other rights in the application or use of such information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
<KM111300>
2012/06
-24-
3
2
1
VD1
4
VD2
5
VSS2
VSS
D
D
C
2
HDPb
3
C3
0.1u
C4
1.0u
1
C9
1.0u
2
9
8
C5
1.0u
CN3
(open)
C7
INPUT1
JP1
AINL+_SEL
22
23
VEE
CP
CN
24
25
VD1
26
VD2
27
1.0u
VCP
28
VCN
C8
4.7u
0.1u
1.0u
1
HDPr
C2
C6
U1
HDY
4.7u
+
+
CN2
(open)
C1
7
6
5
4
3
2
1
CN1
(open)
4
5
6
R6
75
3
VVEE
AINL+
VREG
AINL-
R7
75
4
R8
75
5
HDY
21
20
AK4712
SCL/UVP
10k
AINL-
3
C
TVOUTL
I2CSEL
5
TVOUTR
6
20k
15
AINR+
AINL+
20k
16
AINR-
R11
10k
R12
10k
R13
20k
R14
0
AINR-
7
AINR+
8
PDN
INPUT1
JP2
AINR+_SEL
14
13
SDA/MUTEN
12
ENCY
0.1u
11
C11
ENCPr
C10
4.7u
8
9
VVD
ENCPb
+
9
7
8
Connect the back TAB with VSS
RCAVOUT
10
6
75
R4
VSS
2
17
TVOUTR
ENCRCA
R10
7
10k
4
R9
VVD
R1
1
18
I2CSEL
HDPB
0
19
TVOUTL
HDPR
20k
R3
INPUT2
R5
RCAVOUT
R2
9
INPUT2
VSS
B
VSS
B
TP1 UVP
VSS
R15
10k
R48
MUTEN/SCL_SEL
MUTEN
SCL
22k
C12
R16
1.6k
0.1u
UVP
9
7
JP4
6
5
4
3
2
CN4
1
JP3
8
SDA
UVP/SCL_SEL
PDN
SCL
MUTEN
SDA
ENCY
ENCPr
A
ENCPb
ENCRCA
(open)
A
Title
AKD4712-A
Size
A3
Date:
5
4
3
2
Document Number
Rev
0
AK4712
Thursday, June 14, 2012
Sheet
1
1
of
4
4
Video Output
Audio Intput
J1
AINL+
ENCY
1
HDY
R18
75
2
3
4
5
2
3
4
5
C14
(short)
C13
1
AINL+
J5
AINL
1
VSS
D
J4
TVOUTL
R17
330
1
TVOUTL
0.47u
R19
10k
2
3
4
5
1
AGND
VSS
3
VSS
Audio Output
+
J3
HDY
C15
0.1u
1
1
2
J2
ENCY
2
3
4
5
2
2
Video Intput
D
3
+
5
2
3
4
5
VSS
3
VSS
1
C16
J7
HDPb
C17
0.1u
ENCPb
1
HDPb
R20
75
+
J6
ENCPb
VSS
AINL-
2
3
4
5
0.47u
JP5
GND
VSS
C18
(short)
VSS
J8
TVOUTR
R21
330
1
2
3
4
5
J10
HDPr
C19
0.1u
1
VSS
ENCPr
1
HDPr
R23
75
J11
AINR+
2
3
4
5
2
3
4
5
C20
1
1
VSS
1
ENCRCA
1
RCAVOUT
R24
75
0.47u
1
3
J14
RCAVOUT
C21
0.1u
VSS
2
3
4
5
VSS
C22
+
2
3
4
5
VSS
3
J13
ENCRCA
J12
AINR
C
AGND
AINR+
VSS
2
3
4
5
2
VSS
R22
10k
+
J9
ENCPr
VSS
2
C
+
TVOUTR
AINR0.47u
VSS
VSS
JP6
GND
VSS
VSS
B
B
A
A
Title
AKD4712-A
Size
A3
Date:
5
4
3
2
Document Number
Rev
0
Audio Video Input / Output
Thursday, June 14, 2012
Sheet
1
2
of
4
5
4
3
R25
C23
10
8
6
4
2
4.7k
2.2u
2
1
PORT2 A1-10PA-2.54DSA(open)
9
7 SCL
5 SDA
3 SDA(ACK)
1
10pin-CTRL
51(open)
51(open)
51(open)
DGND
C26
C
DGND
17
16
15
14
11
10
9
8
38
39
40
41
2
3
4
5
VSS0
6
28
PIC18F4550
TQFP 44-PIN
U2
NC/ICCK/ICPGC
NC/ICDT/ICPGD
NC/ICRST_N/ICVpp
NC/ICPORTS
OSC1/CLKI
OSC2/CLKO/RA6
RE0/AN5/CK1SPP
RE1/AN6/CK2SPP
RE2/AN7/OESPP
VUSB
32
35
36
PORT1
VUSB
DD+
GND
1
2
3
4
R43
R44
USB(B type)
0
0
42
43
44
1
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2/UOE_N
RC2/CCP1/P1A
RC4/D-/VM
RC5/D+/VP
RC6/TX/CK
RC7/RX/DT/SDO
DGND
R34
470
R38
470
R37
MCLR_N/Vpp/RE3
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0/CSSPP
RB3/AN9/CPP2/VPO
RB2/AN8/INT2/VMO
RB1/AN10/INT1/SCK/SCL
RB0/AN12/INT0/FLT0/SDI/SDA
RD0/SPP0
RD1/SPP1
RD2/SPP2
RD3/SPP3
RD4/SPP4
RD5/SPP5/P1B
RD6/SPP6/P1C
RD7/SPP7/P1D
10k
10k
10k
0.1u
VDD1
29
VSS1
1
2
3
4
5
R29
R30
R31
C27
0.1u
JP7
D3.3V
C25
10u
7
DGND
1u
SILK-SCREEN
1:VDD
2:MCLR
3:PGD
4:PGC
5:GND
R26
R27
R28
+
+
C24
10u
C28
D
D3.3V
VDD0
NC
NC
Vin
Vout
Vcont PCL
NC
GND
T1
5V => 3.3V
DGND
8
7
6
5
TK73633AME
1
2
3
4
DGND
D
RA0/AN0
RA1/AN1
RA2/AN2/Vref-/CVref
RA3/AN3/Vref+
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS_N/HLVDIN/C2OUT
18
12
13
33
34
1
3
5
9
11
13
0
D3.3V
R39
0.1u
100k
R33
10k
10k
TP2
SDA
TP3
SCL
U3
USB-RST
C29
R32
14
C30
0.1u
7
1A
2A
3A
4A
5A
6A
1Y
2Y
3Y
4Y
5Y
6Y
2
4
6
8
10
12
R35
51
R36
51
SCL
SDA
Vcc
GND
74HC07
C
DGND
30
31
C31
XTI
XTO
25
26
27
37
19
20
21
22
23
24
22p
X1
20MHz
C32
22p
C33
470n
R40
R41
R42
51
51
51
DGND
SCL
SDA
SDA(ACK)
PIC18F4550
B
B
D3.3V
K
D3.3V
MUTEN
D1
HSU119
A
I2CSEL
R50
R45
10k
0
SW 1
PDN
1
H
3
2
1
PDN
L
H
U4
1
2
3
4
5
6
7
L
3
4
SW 2
R49
2
C34
0.1u
10k
1A
1Y
2A
2Y
3A
3Y
GND
VCC
6A
6Y
5A
5Y
4A
4Y
I2CSEL
A
74HC14
R46
R47
10k
10k
DGND
C49
14
13
12
11
10
9
8
D3.3V
MUTEN
C35
0.1u
A
0.1u
Title
DGND
DGND
AKD4712-A
Size
A3
Date:
5
4
3
2
Document Number
Rev
0
uP-I/F
Thursday, June 14, 2012
Sheet
1
3
of
4
5
4
3
2
1
+5V
D
D
C36
+
JP8
47u
GND
VSS
VSS
DGND
VD1
VSS
1
IN
OUT
JP9
VD1
L1
(short)
3
1
2
VD1
2
1
VSS2
GND
T2
LM1117IDTX-3.3
+
10u
1
J15
C38
C39
0.1u
C40
0.1u
C41
10u
+
C37
47u
+
2
+5V
+5V
VSS
TJ563-Y
D3.3V
VD1
VD1
C
TP4
VD1
TP5
VD1
JP10
D3.3V
L2
(short)
1
1
TJ563-R
D3.3V
VD2
TP6
VD2
TP7
VD2
VVD
TP8
VVD
TP9
VVD
+
C42
47u
2
VD2
1
J17
C
2
VSS
1
J16
TJ563-R
DGND
VVD
1
J18
TJ563-R
TP10
D3.3V D3.3V
J19
D3.3V
1
TJ563-R
TP14 TP15 TP11 TP16 TP12 TP13
VSS VSS VSS VSS VSS VSS
B
T3
LM1117IDTX-3.3
JP13
VD2
JP11
VD2
L3
(short)
1
IN
OUT
VSS
TP17
VSS2
C44
10u
C45
0.1u
VD2
REG2
C46
0.1u
C47
10u
+
C43
47u
+
2
+
B
2
3
2
TJ563-BK
1
1
1
J20
REG1
REG_SEL
GND
VSS
VSS2
VSS2
1
J21
VVD
TJ563-BK
JP12
VVD
L4
(short)
1
VSS
2
VVD
VSS2
TP18
DGND
1
DGND
J22
1
+
C48
47u
2
TJ563-BK
DGND
VSS
A
A
Title
AKD4712-A
Size
A3
Date:
5
4
3
2
Document Number
Rev
0
Power Supplly
Thursday, June 14, 2012
Sheet
1
4
of
4
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