AK5720VT

ASAHI KASEI
[AKD5720-A]
AK5720 Evaluation Board Rev.1
GENERAL DESCRIPTION
AKD5720-A is an evaluation board for AK5720 which is low voltage 24bit analog-digital converter
developed for digital audio system. It supports Jacks for analog signal input.
This board also has a digital interface and can achieve the interface with a digital audio system through an
optical connector.
 Ordering guide
AKD5720-A ---
Evaluation board for AK5720
FUNCTION
REG
T1
(LDO 5V)
T2
(LDO 3V)
T3
(LDO 5V)
AK4118a 3.3V
T4
(LDO 3V)
DGND
T5
(LDO 3.3V)
RIN
RIN
LIN
LIN
VSS
VSS
BICK
BICK
MCLK
512fs
256fs
AK5720
VA
VA
VD
VD
LRCK
LRCK
SDTO
DAUX
PORT1
DOUT(DSP)
PORT2
DOUT(OPT)
DIT
(AK4118A)
X’tal
Figure 1. AKD5720-A Block Diagram
KM113601
2013/10
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ASAHI KASEI
[AKD5720-A]
Board Outline Chart
 Outline Chart
JP1
J4
J2
JP5
J1
JP4
JP2
U1
J6
SW1
JP3
Port1
U4
JP12
JP6
JP11
JP7
SW3
JP14
T4
T1
T3
SW2
JP9
JP8
U3
JP10
T2
Port2
JP13
J5
J3
J7
J8
Figure 2. Outline Chart
Description
(1) J1,J2(Analog data )
RCA jack, Used for Analog audio input.
(2) J3,J4, J5, J6, J7,J8(Power supply)
The Ak5720 can be powered by external power supply or by Regulator (T1, T2, T3, T4) on the evaluation board.
(3) PORT1(10pin header)
10pin header (MCLK, BICK, LRCK, SDTO, TDMI)
(4) PORT2(Digital Data)
SPDIF output (Optical output connector.)
(5) U1(AK5720)
Low voltage 24bit analog-digital converter.
(6) U2(AK4118A)
AK4118A is DIT, which transmits digital data of AK5720.
(7) SW1(Toggle switch)
Power down of AK5720
“H” :PDN of AK5720 is Hi.
“L” :PDN of AK5720 is Lo.
(8) SW2(Toggle switch)
Power down of AK4118A
“H” :PDN of AK4118A is Hi.
“L” :PDN of AK4118A is Lo.
(9) SW3(Dip switch)
Setting of AK5720 and AK4118A
See Table4.
KM113601
2013/10
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ASAHI KASEI
[AKD5720-A]
(10) JP1, JP2, JP3, JP4
Setting of audio interface format of AK5720
(11) JP5
Setting of digital filter of Ak5720
(12) JP6
Setting of input gain of AK5720
(13) JP7
Setting of AK4118a
(14) JP8
Setting of AK4118a
(15) JP9, JP10, JP11, JP12, JP13, JP14
Setting of power supply of AK5720 and AK4118a
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ASAHI KASEI
[AKD5720-A]
Evaluation Board Manual
 Operation Sequence
1) Set up the Power Supply Lines.
2) Setup the Audio I/F Evaluation Mode.
(1) Evaluation of A/D using DIT of AK4118A.
(1-1) Slave Mode (Default)
(1-2) Master Mode
(1-3) PLL Slave Mode
(2) Evaluation of A/D using external clock.
(2-1) Slave Mode
(2-2) Master Mode
(2-3) PLL Slave Mode
3) Jumper pins and SW Setting.
(1) Setting of other jumper pins
(2) Setting of SW
4) Power on
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ASAHI KASEI
[AKD5720-A]
1) Set up the power Supplies
JP9 (SEL_VA): When VA is supplied from the regulator.
・JP9 5V
: VA is supplied 5V. <Default>
3V
: VA is supplied 3V.
JP10 (SEL_VD): When VD is supplied from the regulator.
・JP10 5V : VD is supplied 5V. <Default>
3V : VD is supplied 3V.
JP11 (VD): VD line and VA line are set common or separation.
・JP11 VA
: VD line and VA line are set common.
VD
: VD line and VA line are set separation.
OPEN : VD is not supplied from the regulator. <Default>
JP12 (VA): VA is supplied from the regulator.
・JP12 OPEN : VA is not supplied from the regulator. <Default>
SHORT : VA is supplied from the regulator.
JP13 (4118a_3.3V): When power supply of AK4118A is supplied from the regulator.
・JP13 OPEN : Power supply of AK4118A is not supplied from the regulator. <Default>
SHORT : Power supply of AK4118A is supplied from the regulator.
JP14 : VSS and DGND are set common or separation.
・JP14 OPEN : VSS and DGND are set common.
SHORT : VSS and DGND are set separation. <Default>
(1) When VA, VD and 4118a_3.3V are supplied from the regulator. <Default>
Set up the power supply lines
Name
Color
Setting
Comments
VA
Red
Open
Not used. Supplied through regulator
VD
Red
Open
Not used. Supplied through regulator
VSS
Black
0V
Ground for AK5720
4118a_3.3V
Red
Open
Not used. Supplied through regulator
DGND
Black
0V
Ground for AK4118a
REG
Yellow
+7V
Power supply for the regulator.
Table 1 Setup of power supply (Used regulator)
Jumper Setting
Name
JP9
JP10
JP11
JP12
JP13
Name
JP9
JP10
Setting
Short on 5V side
Short on 5V side
VA : VD line and VA line are set common.
VD : VD line and VA line are set separation .
Short
Short
JP11
JP12
JP13
Table 2 Setting of VA=VD=5V
Setting
Short on 3V side
Short on 3V side
VA : VD line and VA line are set common.
VD : VD line and VA line are set separation .
Short
Short
Table 3 Setting of VA=VD=3V
(2) When VA, VD and 4118a_3.3V are supplied from the power supply connectors.
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ASAHI KASEI
[AKD5720-A]
Set up the power supply lines
Name
Color
Setting
Comments
VA
Red
+2.7~+5.5V Power supply for VA of AK5720.
VD
Red
+2.7~VA V Power supply for VD of AK5720.
VSS
Black
0V
Ground for AK5720.
4118a_3.3V
Red
+3.3V
Power supply for AK4118a.
DGND
Black
0V
Ground for AK4118a.
REG
Yellow
Open
Not used.
Table 4 Setup of power supply (Not used regulator)
Jumper Setting
Name
JP9
JP10
JP11
JP12
JP13
Table 5
Setting
Open
Open
Short on VA side
Short
Open
Setting of VA=VD
Name
JP9
JP10
JP11
JP12
JP13
Table 6
Setting
Open
Open
Short on VD side
Open
Open
Setting of VA≠VD
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ASAHI KASEI
[AKD5720-A]
2) Setup the Audio I/F Evaluation Mode
In case of using the AK4118A when evaluating the AK5720, the audio interface format of the AK5720 and
AK4118A must be matched.
Refer to audio interface format of AK5720 (Table 7, Table 8), and audio interface format of AK4118A (Table 10).
The AK4118A operates at sampling frequency of 32 kHz or more. If the sampling frequency is lower than 32 kHz,
please use other mode.
Refer to the datasheet for register setting of the AK5720.
(1) Evaluation of A/D using DIT of AK4118A
(1-1) Slave Mode. (Default).
PORT2 (TOTX) is used
・PORT1: Open
・AK5720: Slave mode
・Setting of JP1, JP2, JP3, JP4 : See Table 7.
・AK4118A: Master mode
・SW3(4118-DIF1) : “Lo”
Mode
JP1
(VA/
GND)
GND
Norma
l
VA
GND
VA
GND
VA
TDM
GND
VA
JP2 (CKS)
JP4
(DIF/
TDMI)
JP3
(DIF)
SDTO
Master/
Slave
DIF
Short on 1 side
L
MSB
Slave
DIF
(Short to GND)
H
I2 S
DIF
Short on 1 side
L
MSB
Master
DIF
(Short to VA)
H
I2 S
DIF
Short on 2 side
L
MSB
Master
DIF
(4.7kΩ±10% to GND)
H
I2 S
DIF
Short on 2 side
L
MSB
Master
DIF
(4.7kΩ±10% to VA)
H
I2 S
Short on 3 side
TDMI
MSB
Master
(18kΩ±10% to GND)
Short on 3 side
TDMI
MSB
Slave
(18kΩ±10% to VA)
Short on 4 side
TDMI
I2 S
Master
(82kΩ±10% to GND)
Short on 4 side
TDMI
I2 S
Slave
(82kΩ±10% to VA)
Table 7 Slave Mode (Setting of JP1,JP2, JP3, JP4)
MCLK
BICK
256/384fs (8kfs96k)
512/768fs (8kfs48k)
 48fs or
32fs
256fs (8kfs96k)
64fs
384fs (8kfs96k)
64fs
512fs (8kfs48k)
64fs
256fs (8kfs96k)
256fs
256fs (8kfs96k)
256fs
256fs (8kfs96k)
256fs
256fs (8kfs96k)
256fs
4118-DIF1
MCLK, BICK and LRCK are supplied from AK4118A to AK5720. PORT2 outputs optical data of AK5720
through AK4118A. MCLK can be selected between 512fs and 256fs by JP7.
L
AK4 118 a
Ma ste r/S la ve S elec t
512fs
256fs
EXT
512fs
256fs
H
JP7
EXT
SW 3
OR
M CLK S ele ct
KM113601
2013/10
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ASAHI KASEI
[AKD5720-A]
(1-2) Master Mode
PORT2 (TOTX) is used
・PORT1: Open
・AK5720: Master mode
・Setting of JP1, JP2, JP3, JP4 : See Table 8.
・AK4118A: Slave mode
・SW3(4118-DIF1) : “Hi”
Mode
JP1
(VA/
GND)
GND
Norma
l
VA
GND
VA
GND
VA
TDM
GND
VA
JP2 (CKS)
JP4
(DIF/
TDMI)
JP3
(DIF)
Master/
Slave
SDTO
DIF
Short on 1 side
L
MSB
Slave
DIF
(Short to GND)
H
I2 S
DIF
Short on 1 side
L
MSB
Master
DIF
(Short to VA)
H
I2 S
DIF
Short on 2 side
L
MSB
Master
DIF
(4.7kΩ±10% to GND)
H
I2 S
DIF
Short on 2 side
L
MSB
Master
DIF
(4.7kΩ±10% to VA)
H
I2 S
Short on 3 side
TDMI
MSB
Master
(18kΩ±10% to GND)
Short on 3 side
TDMI
MSB
Slave
(18kΩ±10% to VA)
Short on 4 side
TDMI
I2 S
Master
(82kΩ±10% to GND)
Short on 4 side
TDMI
I2 S
Slave
(82kΩ±10% to VA)
Table 8 Master Mode (Setting of JP1,JP2, JP3, JP4)
MCLK
BICK
256/384fs (8kfs96k)
512/768fs (8kfs48k)
 48fs or
32fs
256fs (8kfs96k)
64fs
384fs (8kfs96k)
64fs
512fs (8kfs48k)
64fs
256fs (8kfs96k)
256fs
256fs (8kfs96k)
256fs
256fs (8kfs96k)
256fs
256fs (8kfs96k)
256fs
4118-DIF1
MCLK is supplied from AK4118A or external input to AK5720. LRCK, BICK, SDTO of AK5720 are outputs to
AK4118A. PORT2 outputs optical data of AK5720 through AK4118A. MCLK can be selected between 512fs
and 256fs by JP10.
L
AK 4118a
M aster/Slave Select
OR
512fs
EXT
256fs
512fs
256fs
EXT
512fs
EXT
External clock input
H
256fs
SW 3
JP7
OR
M C LK Select
GND
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ASAHI KASEI
[AKD5720-A]
(2) Evaluation of A/D using external clock.
(2-1) Slave Mode
PORT1 (DSP) is used.
・SW2: “Lo” (AK4118A is not used)
・AK5720: Slave mode
・Setting of JP1, JP2, JP3, JP4 : See Table 7
・SW3(4118-DIF1) : “Lo”
SW2
H
2
H
L
MCLK
GND
BICK
GND
LRCK
GND
SDTO
GND
PORT1
SW3
4118-PDN
4118-DIF1
MCLK, BICK and LRCK are supplied from PORT1 to AK5720. SDTO of AK5720 is output to PORT1
L
Master/Slave Select
PDN of AK4118A
10
9
TDM
PORT1
(2-2) Master Mode
PORT1 (DSP) is used.
・SW2: “Lo” (AK4118A is not used)
・AK5720: Master mode
・Setting of JP1, JP2, JP3, JP4 : See Table 8
・SW3(4118-DIF1) : “Lo”
H
L
SW2
2
H
MCLK
GND
BICK
GND
LRCK
GND
SDTO
GND
PORT1
SW3
4118-PDN
4118-DIF1
MCLK is supplied from PORT1. LRCK, BICK , SDTO of AK5720 is output to PORT1.
L
Master/Slave Select
PDN of AK4118A
KM113601
10
9
TDM
PORT1
2013/10
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ASAHI KASEI
[AKD5720-A]
3) Jumper pins and SW Setting
(1) Setting of other jumper pins.
JP5 (FSEL): Setting of digital-filter of AK5720.
・JP5 L : Sharp Roll-Off. < Default >
H : Short Delay Sharp Roll-Off.
JP6 (GSEL): Setting of input gain of AK5720.
・JP6 L : 0dB. < Default >
H : +6dB.
JP8 : The selection of OPEN or SHORT of SDTO line, BICK line, LRCK line for AK4118A.
・JP8 SDTO : SHORT < Default >
BICK : SHORT < Default >
LRCK : SHORT < Default >
(2) Setting of SW
[SW3] (SW DIP-4): Mode setting for AK4118A.
No.
Name
1
2
3
4
4118-DIF1
4118-DIF0
4118-OCKS0
4118-OCKS1
ON (“H”)
OFF (“L”)
Default
OFF
ON
OFF
ON
See Table 10
See Table 11
Table 9 Mode setting for AK4118A
4118DIF1
4118DIF0
L
L
H
H
L
H
L
H
Mode
DAUX
SDTO
LRCK
Master Mode
24bit, Left justified 24bit, Left justified
H/L
Master Mode
24bit, I2S
24bit, I2S
L/H
Slave Mode
24bit, Left justified 24bit, Left justified
H/L
Slave Mode
24bit, I2S
24bit, I2S
L/H
Table 10 Audio I/F Format Setting for AK4118A
No.
OCKS1
0
1
2
3
0
0
1
1
OCKS0
0
1
0
1
Table 11
MCKO1
MCKO2
X’tal
256fs
256fs
256fs
256fs
128fs
256fs
512fs
256fs
512fs
128fs
64fs
128fs
Master Clock setting for AK4118A
KM113601
BICK
I/O
O
O
I
I
64fs
64fs
64-128fs
64-128fs
I/O
O
O
I
I
fs (max)
96 kHz
96 kHz
48 kHz
192 kHz
(Default)
2013/10
- 10-
ASAHI KASEI
[AKD5720-A]
4) Power on
[SW1] (5720-PDN)
: The AK5720 should be reset once bringing “L” upon power-up.
Keep “H” during normal operation.
[SW2] (4118a-PDN) : The AK4118A should be reset once bringing “L” upon power-up.
Keep “H” during normal operation.
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ASAHI KASEI
[AKD5720-A]
Revision History
Date
(yy/mm/dd)
13/10/09
Manual
Revision
KM113600
Board
Revision
0
13/10/15
KM113601
1
Reason
Page
Contents
First Edition
Specifications
change
7,8
CKS Setting Changed
IMPORTANT NOTICE
0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the information
contained in this document without notice. When you consider any use or application of AKM product
stipulated in this document (“Product”), please make inquiries the sales office of AKM or authorized
distributors as to current status of the Products.
1. All information included in this document are provided only to illustrate the operation and application
examples of AKM Products. AKM neither makes warranties or representations with respect to the accuracy
or completeness of the information contained in this document nor grants any license to any intellectual
property rights or any other rights of AKM or any third party with respect to the information in this
document. You are fully responsible for use of such information contained in this document in your product
design or applications. AKM ASSUMES NO LIABILITY FOR ANY LOSSES INCURRED BY YOU OR
THIRD PARTIES ARISING FROM THE USE OF SUCH INFORMATION IN YOUR PRODUCT
DESIGN OR APPLICATIONS.
2. The Product is neither intended nor warranted for use in equipment or systems that require extraordinarily
high levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human
life, bodily injury, serious property damage or serious public impact, including but not limited to,
equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment,
equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment,
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related to electric power, and equipment used in finance-related fields. Do not use Product for the above use
unless specifically agreed by AKM in writing.
3. Though AKM works continually to improve the Product’s quality and reliability, you are responsible for
complying with safety standards and for providing adequate designs and safeguards for your hardware,
software and systems which minimize risk and avoid situations in which a malfunction or failure of the
Product could cause loss of human life, bodily injury or damage to property, including data loss or
corruption.
4. Do not use or otherwise make available the Product or related technology or any information contained in
this document for any military purposes, including without limitation, for the design, development, use,
stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products
(mass destruction weapons). When exporting the Products or related technology or any information
contained in this document, you should comply with the applicable export control laws and regulations and
follow the procedures required by such laws and regulations. The Products and related technology may not
be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under
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5. Please contact AKM sales representative for details as to environmental matters such as the RoHS
compatibility of the Product. Please use the Product in compliance with all applicable laws and regulations
that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS
Directive. AKM assumes no liability for damages or losses occurring as a result of noncompliance with
applicable laws and regulations.
6. Resale of the Product with provisions different from the statement and/or technical features set forth in this
document shall immediately void any warranty granted by AKM for the Product and shall not create or
extend in any manner whatsoever, any liability of AKM.
7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
consent of AKM.
KM113601
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5
4
3
2
1
VA
D
D
R6
OPEN
R7
OPEN
AGND
CN1
VCOM
1
1
J1
TP2
RIN
16
5720-CKS
16
TP15
2
2
J2
LIN
TP3
RIN
FSEL
15
FSEL
5720-FSEL
15
LIN
TP14
DIF_TDMI
C3 10u
+
2
3
4
5
AGND
CKS
C2 10u
1
C
VCOM
CKS
RIN
+
2
3
4
5
TP16
+
TP1
CN2
U1
C1
0.47u
1
3
3
TP4
TP5
4
C4
10u
5
5
R1 51
5720-DIF / TDMI
14
PDN
BICK
5720-PDN
13
12
R2 51
6
6
+
5720-GSEL
C6
10u
VD
MCLK
11
R3 51
BICK
MCLK
TP10
7
7
GSEL
LRCK
10
R4 51
8
8
TP18 TP17
AGND AGND
REGO
SDTO
9
R5 51
LRCK
LRCK
10
TP9
+
MCLK
11
C7
0.1u
REGO
B
BICK
12
TP11
GSEL
C
DIF_TDMI
TP12
AK5720
VA
13
VD
VD
TP8
VSS
C5
0.1u
+
VA
TP7
14
TP13
VA
TP6
DIF / TDMI
VSS
4
AGND
LIN
SDTO
SDTO
9
B
C8
1u
16pin_L
16pin_R
AGND
AGND
AGND
A
A
Title
AKD5720-a
- 135
4
3
Size
A4
Date:
2
Document Number
ak5720
Tuesday, October 15, 2013
Rev
1
Sheet
1
1
of
4
5
4
3
2
1
K
VD
R12
A
D1
HSU119
10k
U2
1
1
L
3
D
SW1
2
H
3
2
C10
1Y
GND
VCC
2A
2Y
6
D
5
VD
4
R13
0
5720-PDN
SN74LVC2G14
0.1u
5730-PDN
1A
C9
0.1u
AGND
AGND
C
C
VA
VA
JP1
H
JP2
R8
JP6
5720-CKS
0
GND
VD
5720-GSEL
R9
4.7k
L
R10
18k
JUMPER_4
R11
AGND
AGND
82k
B
B
H
VD
H
JP3
DIF
5720-FSEL
JP4
5720-DIF / TDMI
L
JP5
VD
L
TDMI
AGND
AGND
A
A
5720-TDMI
Title
AKD5720-a
- 145
4
3
Size
A4
Date:
2
Document Number
Logic
Tuesday, October 15, 2013
Rev
1
Sheet
2
1
of
4
4
3
2
1
2
4
6
8
10
5
4118_3.3V
PORT1
10PIN-PORT
+
10u
C12
DGND
MCLK
BICK
LRCK
SDTO
TDMI
C11
1
3
5
7
9
DGND
0.1u
R14
5720-TDMI
10k
C13
0.47u
1
37
INT1
38
R
AVDD
39
40
VCOM
41
VSS3
42
RX0
43
NC
44
RX1
45
TEST1
46
RX2
VSS4
RX3
47
D
48
D
SDTO
IPS0/RX4
INT0
36
LRCK
MCLK
3
4118-DIF0
4
5
4118-DIF1
6
C
NC
OCKS0/CSN/CAD0
DIF0/RX5
OCKS1/CCLK/SCL
TEST2
CM1/CDTI/SDA
DIF1/RX6
CM0/CDTO/CAD1
U3
VSS1
PDN
35
34
4118-OCKS1
33
32
DGND
4118_3.3V
31
XTI
30
JP7
X1
24.576MHz
IPS1/IIC
XTO
29
JMP2x3
JP8
JMP2x3
2
8
C
EXT
XTL256fs
XTL512fs
10p
1
DIF2/RX7
DGND
4118-PDN
C14
7
BICK
4118-OCKS0
SDTO
BICK
LRCK
2
C15
10p
28
DGND
27
26
25
LRCK
VSS2
MCKO1
SDTO
DVDD
VOUT/GP7
VIN/GP0
UOUT/GP6
BICK
COUT/GP5
XTL1
BOUT/GP4
MCKO2
TVDD
12
XTL0
TX1/GP3
11
DAUX
TX0/GP2
10
P/SN
NC/GP1
9
4118_3.3V
0.1u
0.1u
+
C18
10u
C19
10u
SW3
SW DIP-4
L
5
6
7
8
C17
+
H
C16
4
3
2
1
24
23
22
21
20
19
18
17
16
15
14
B
13
B
4118_3.3V
4118-DIF0
4118-DIF1
4118-OCKS0
4118-OCKS1
DGND
4
3
2
1
4118_3.3V
1
R15
D2
HSU119
A
4118_3.3V
0.1u
TX
L
DGND
DGND
10k
U5
1
SW2
2
H
3
4118-PDN
2
A
C20
1
GND
3
2
3
IN
VCC
K
PORT2
C21
1A
GND
2A
1Y
VCC
2Y
6
5
4
RP1
R-PACK4R
4118_3.3V
A
4118-PDN
SN74LVC2G14
0.1u
C22
0.1u
DGND
5
4
- 153
DGND
Title
AKD5720-a
Size
A3
Date:
2
Document Number
DIT
Tuesday, October 15, 2013
Rev
1
Sheet
1
3
of
4
5
4
3
C23
+
47u
C24
10u
IN
C25
0.1u
OUT
1
2
C26
0.1u
1
+
2
T1
LM1117IDTX-5.0
GND
+7V
3
+
C27
10u
AVDD
JP14
VSS
D
AGND
JP9
T2
LM1117IDTX-ADJ
VA
OUT
+
C29
10u
1
VA 5 / 3 V
2
AGND
C31
0.1u
+
C32
10u
+7V
AGND
R17
160
REG
JP11
AVDD
VD=VA
C34
10u
C35
0.1u
VA
AGND
+
C33
47u
2
DVDD
C36
0.1u
+
1
J5
2
OUT
1
+
IN
GND
T3
LM1117IDTX-5.0
C
VD
VA
1
≠
VD
1
J4
VD
C
3
1
J3
DVDD
8.2
AGND
DGND
2
R16
120
C30
0.1u
R20
+
C28
47u
1
IN
GND
3V
3
D
JP12
VA
5V
AGND
GND DGND
VD
AGND
C37
10u
1
J6
JP10
5V
VSS
AGND
AGND
3V
3
IN
OUT
+
C38
10u
VD 5 / 3 V
AK4118_3.3V
2
C40
0.1u
+
C41
10u
1
J8
R19
160
DGND
8.2
DGND
T5
LM1117IDTX-3.3
IN
OUT
AGND
AK4118_3.3V
JP13
4118_3.3V
2
4118_3.3V
1
3
GND
AGND
B
AK4118a_3.3V
C39
0.1u
R21
1
J7
R18
120
1
B
GND
T4
LM1117IDTX-ADJ
+
C42
10u
C43
0.1u
C44
0.1u
+
C45
10u
A
+
C46
47u
2
1
A
Title
AKD5720-a
DGND
DGND
5
4
- 163
Size
A4
Date:
2
Document Number
Power Supply
Tuesday, October 15, 2013
Rev
1
Sheet
4
1
of
4
AKD5720-A Rev.1 Pattern View
Silk View of Component Side
(Perspective View of Component Side)
U4, C47, C48: No mount
- 17-
AKD5720-A Rev.1 Pattern View
Silk View of Solder Side
(Perspective View of Component Side )
- 18-
AKD5720-A Rev.1 Pattern View
Pattern View of Component Side
(Perspective View of Component Side)
- 19-
AKD5720-A Rev.1 Pattern View
Pattern View of Solder Side
(Perspective View of Component Side )
Jumper Line
- 20-
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