AK7719BECB

[AKD7719B-A]
AK7719B Evaluation Board Rev.0
GENERAL DESCRIPTION
The AKD7719B-A is an evaluation kit for the AK7719B; a digital signal processor (DSP) with digital interface
ports. The built-in asynchronous sample rate converters (SRC) enable flexible connectivity in various system
configurations. It realizes an easy evaluation of the audio system by just connecting to the target product via
digital input and output pins. A USB connection is adopted for control interface, enabling to develop DSP codes
with a PC.
■ Ordering Guide
AKD7719B-A
---
Evaluation board for AK7719B
(Main-board：AKD7719B-A-MAIN , Sub-board：AKD7719B-A-SUB)
USB Control Box
Control Software
FUNCTION
 Write/Read RAM: Access to PRAM, CRAM, OFFRAM and Registers
 Digital Audio Interface
- Test pin header
JP5(TVDD)=3.3V
TP3(GND)=0V
Regulator
1.2V
Reset
uPI/F
SDIN
SDOUT
I2C or SPI
AKM
DSP
Device
Core
PCM
I/F
Device
PCM
I/F
AK7719B
AKD7719B-A-MAIN + AKD7719B-A-SUB
Figure 1. AKD7719B-A Block Diagram
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[AKD7719B-A]
EVALUATION BORAD
■ Board View
(1)
(2)
(3)
(4)
(8)
AK7719B
(9)
(5)
AKD7719B-A-SUB
AKD7719B-A-MAIN
(7)
(6)
AKD7719B-A-MAIN + AKD7719B-A-SUB
Figure 2. AKD7719B-A Board View
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[AKD7719B-A]
■ Description
AKD7719B-A-MAIN
No.
Name
EXT (J1)
(1)
(24 pin Header)
(2)
3.3V (JP5)
TEST (J2)
(3)
(28 pin Header)
(4)
Jumper (JP3, JP4, JP6, JP7)
(5)
DIP Switch (S1, S2)
MONITOR (JP2)
(6)
(10 pin Header)
CONTROL (JP1)
(7)
(10 pin Header)
TEST (TP02-TP28)
(8)
( Test pin Header)
EXT (J101)
(9)
(20 pin Header)
Function
External System Signal Connector.
3.3V Power Supply Terminal. Use attached connection cable.
External System Connector
Power Supply Select Jumper
Pin and Signal Select Switches
AKD77XX-HFS MONITOR Board Connector. (for HF Tuning)
USB Control Box Connector
External System Connector and Monitor Pin (on Sub-Board)
External System Connector (on Sub-Board)
AKD7719B-A-MAIN
EXT(24 / 27 pin Header) Pin Layout
・24pin Pin Header [ J1 ] :
Pin No.
Name
I/O
1
EXT-BCLK1
I
2
EXT-JX0/BCLK3
I/O
3
EXT-SYNC1
I
4
EXT-JX1/SYNC3
I/O
5
EXT-SDIN1
I
6
EXT-SDIN3
I/O
7
EXT-SDOUT1
O
8
EXT-SDOUT3/GP0
I/O
9
EXT-BCLK2
O
10
EXT-SDIN4
I
11
EXT-SYNC2
O
12
EXT-SDOUT4/GP1
I/O
13
EXT-SDIN2
I
14
EXT-STO/RDY
O
15
EXT-SDOUT2
O
16
EXT-PDN
I/O
17
EXT-CSN/SCL
I/O
18
open
-
19
EXT-SO/SDA
I/O
20
GND
-
21
EXT-SCLK/CAD0
I/O
22
EXT-VDD+1.2V
O
23
EXT-SI/CAD1
I/O
24
EXT-TVDD
O
Function
These pins are connected to the AK7719B
via Buffer Level Shifter
This pin is used when controlling the AK7719B via EXT.
Refer to DIPSW Setting
This pin is used when controlling the AK7719B via EXT.
Refer to DIPSW Setting
GND
This pin is used when controlling the AK7719B via EXT.
Refer to DIPSW Setting
This pin is used for VDD supply via EXT.
Refer to JP Setting
This pin is used when controlling the AK7719B via EXT.
Refer to DIPSW Setting
This pin is used for TVDD supply via EXT.
Refer to JP Setting
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[AKD7719B-A]
・27pin Pin Header [ J2 ] :
Pin No.
Name
1
EXT-BCLK1
2
GND
3
EXT-SYNC1
4
GND
5
EXT-SDIN1
6
GND
7
EXT-SDOUT1
8
GND
9
EXT-BCLK2
10
GND
11
EXT-SYNC2
12
GND
13
EXT-SDIN2
14
GND
15
EXT-SDOUT2
16
GND
17
EXT-JX0/BCLK3
18
GND
19
EXT-JX1/SYNC3
20
GND
21
EXT-SDIN3
22
GND
23
EXT-SDOUT3/GP0
24
GND
25
EXT-SDIN4
26
GND
27
EXT-SDOUT4/GP1
I/O
I
I
I
O
O
O
I
O
I/O
I/O
I/O
I/O
I
I/O
Function
These pins are connected to the AK7719B
via Buffer Level Shifter
AKD7719B-A-SUB (AKD7719B-A-30CSP-SUB)
EXT(20pin Header) Pin / TEST Pin Layout
・20pin Pin Header [ J101 ] :
Pin No.
Name
I/O
Function
1
SYNC2-I
I
2
GND
3
BCLK2-I
I
4
GND
5
SYNC4-I
I
6
GND
7
BCLK4-I
I
8
GND
9
SYNC5-O
O
10
GND
These pins are connected to the AK7719B.
11
SYNC5-I
I
12
GND
13
BCLK5-O
O
14
GND
15
BCLK5-I
I
16
GND
17
SDIN5-I
I
18
GND
19
SDOUT5-O
O
20
GND
-
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[AKD7719B-A]
・TEST Pin Header [ TP02 – TP28] :
Pin No.
Name
I/O
02
SYNC3/JX1-I
I
03
SDIN2-I
I
04
TVDD
05
SDIN4-I
I
06
SDOUT2-O
O
07
SO/SDA-IO
I/O
08
SCLK/CAD0-I
I
10
CSN/SCL-I
I
11
SI/CAD1-I
I
12
I2C-I
I
SDOUT4/GP1/STO
O
13
/RDY-O
14
TEST-I
I
15
VSS
16
BCLK2-O
O
17
BCLK3/JX0-I
I
18
VDD
19
SYNC1-I
I
21
BCLK1-I
I
22
PDN-I
I
23
SDIN1-I
I
25
SDOUT1-O
O
26
SYNC2-O
O
27
SDOUT3/GP0-O
O
28
SDIN3-I
I
Function
These pins are connected to the AK7719B.
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[AKD7719B-A]
■ Control Box
The AKD7719B-A should be connected to a PC via an USB control box. The USB control box is connected to a PC with
an USB cable and the AKD7719B-A with 10-pin flat cable.
Set jumper pins to select control I/F (I2C or SPI).
Flat 10pin
USB
SPI(Serial)
I2C
open
short
short
open
short
open
short
open
(default)
The switch of I2C labeled on S2 should be set when changing SPI/I2C.
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[AKD7719B-A]
■ Operation Sequence
AKD7719B-A-MAIN
(1) Jumper and Test Pin Setting (near the Power Supply)
Name
JP3
3.3V
JP4
EXT-TVDD
JP6
REG
JP7
EXT-VDD
Name
TP1
TVDD
TP2
VDD
TP3
GND
Setting
Open
Short
Open
Using
External TVDD supply on TP1
TVDD = 3.3V fixed
External TVDD supply on the 24pin of J1.
(JP3: not connected)
EXT-TVDD = TVDD
External VDD input supply VDD on TP2
VDD+1.2V fixed
VDD = JP6(REG)
External VDD supply on the 22pin of J1.
(JP6: not connected)
Table 1. Jumper Pin Setting
Short
Open
Short
Open
Short
Default Setting
Short
Open
Short
Open
Color
Typ
Voltage
Voltage
Range
Red
+3.3V
+1.6~+3.6V
TVDD of AK7719
Yellow
+1.2V
+1.1~+1.3V
VDD of AK7719
Black
0V
0V
Using
Ground
Table 2. Test Pin Setting
(2) CutLand Setting
Name
CL1
7719-TVDD
CL2
CAD0
CL3
CAD1
Setting
Open
Using
7719-TVDD
independent supply
Short
7719-TVDD = TVDD
Open
CAD0 pin = L
Short
CAD0 pin = H
Open
CAD1 pin = L
Short
CAD1 pin = H
Table 3. CutLand Setting
<KM113200>
Default Setting
Short
Open
Open
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[AKD7719B-A]
(3) DIP Switch Setting
Name
8
7719[MAIN/EXT]
7
MAINIF[EXT/CTRL]
6
EXTIF[MAIN/CTRL]
5
I2C
4
JXE
3
JX0
2
JX1
1
TEST
1
PULL-UP[OFF/ON]
2
PULL-UP[OFF/ON]
3
PULL-UP[OFF/ON]
4
PULL-UP[OFF/ON]
S1
Setting
OFF(MAIN)
ON(EXT)
OFF(EXT)
ON(CTRL)
OFF(MAIN)
ON(CTRL)
OFF
ON
OFF
ON
S2
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
Using
Default Setting
Default setting fixed.
OFF
Default setting fixed.
ON
Default setting fixed.
OFF
I2C pin = “L”
I2C pin = “H”
DIPSW control of JX0/1 for the
AK7719B(MAIN or EXT) is invalid.
DIPSW control of JX0/1 for the
AK7719B(MAIN or EXT) is valid.
JX0 pin = “L”
JX0 pin = “H”
Valid when JXE =
JX1 pin = “L”
ON
JX1 pin = “H”
TEST = “L”
TEST = “H”
PULL-UP OPEN (CSN/SCL)
PULL-UP (CSN/SCL)
PULL-UP OPEN (SCLK/CAD0)
PULL-UP (SCLK/CAD0)
PULL-UP OPEN (SO/SDA)
PULL-UP (SO/SDA)
PULL-UP OPEN (PDN)
PULL-UP (PDN)
Table 4. DIPSW Setting
OFF
OFF
OFF
OFF
OFF
OFF
Control Interface Setting
AK7719B
I/F
connection
I2C
ON
OFF
ON
DIP Switch
EXTIF
MAINIF
OFF
ON
ON
OFF
ON
ON
MAIN
I2C
CONTROL
on board
SPI
CONTROL
EXT *
I2C
CONTROL
not on board
(*: Used when controlling the AK7719B which is externally connected.)
7719
OFF
OFF
ON
(default)
(4) Set up connectors. ( refer to Evaluation Mode )
(5) Power On.
(6) Run the control software (AK7719B.exe) and download the appropriate script file. ( see script section )
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[AKD7719B-A]
■ Evaluation Mode
Refer to the AK7719B datasheet for audio interface format.
(1) Evaluation Port : Port#1 to Port#2 and Port#2 to Port#1
Format : fs=8kHz, BCLK=64fs, I2S 16bit data
Condition
SYNC1
BCLK1
SDIN1
SDOUT1
SYNC2
BCLK2
SDIN2
SDOUT2
SYNC3
BCLK3
SDIN3
SDOUT3
SYNC4
BCLK4
SDIN4
SDOUT4
SYNC5
BCLK5
SDIN5
SDOUT5
INPUT
INPUT
INPUT
OUTPUT
INPUT
INPUT
INPUT
OUTPUT
INPUT
INPUT
INPUT
OUTPUT
INPUT
INPUT
INPUT
OUTPUT
INPUT
INPUT
INPUT
OUTPUT
Name
J2-3 EXT-SYNC1
J2-1 EXT-BCLK1
J2-5 EXT-SDIN1
J2-7 EXT-SDOUT1
Sub J101-1 SYNC2
Sub J101-3 BCLK2
J2-13 EXT-SDIN2
J2-15 EXT-SDOUT2
Sub TP02 SYNC3
Sub TP17 BCLK3
Sub TP28 SDIN3
Sub TP27 SDOUT3
Sub J101-5 SYNC4
Sub J101-7 BCLK4
J2-25 EXT-SDIN4
J2-27 EXT-SDOUT4
Sub J101-11 SYNC5
Sub J101-15 BCLK5
Sub J101-17 SDIN5
Sub J101-J19 SDOUT5
Clocks
1fs=8kHz
64fs=512kHz
I2S, 16bit data
Data Monitor
1fs=8kHz
64fs=512kHz
I2S, 16bit data
Data Monitor
-
(2) Evaluation Port : Port#1 to Port#3 and Port#3 to Port#1
Format : fs=8kHz, BCLK=64fs, I2S 16bit data
Condition
SYNC1
BCLK1
SDIN1
SDOUT1
SYNC2
BCLK2
SDIN2
SDOUT2
SYNC3
BCLK3
SDIN3
SDOUT3
SYNC4
BCLK4
SDIN4
SDOUT4
SYNC5
BCLK5
SDIN5
SDOUT5
INPUT
INPUT
INPUT
OUTPUT
INPUT
INPUT
INPUT
OUTPUT
INPUT
INPUT
INPUT
OUTPUT
INPUT
INPUT
INPUT
OUTPUT
INPUT
INPUT
INPUT
OUTPUT
Name
J2-3 EXT-SYNC1
J2-1 EXT-BCLK1
J2-5 EXT-SDIN1
J2-7 EXT-SDOUT1
Sub J101-1 SYNC2
Sub J101-3 BCLK2
J2-13 EXT-SDIN2
J2-15 EXT-SDOUT2
Sub TP02 SYNC3
Sub TP17 BCLK3
Sub TP28 SDIN3
Sub TP27 SDOUT3
Sub J101-5 SYNC4
Sub J101-7 BCLK4
J2-25 EXT-SDIN4
J2-27 EXT-SDOUT4
Sub J101-11 SYNC5
Sub J101-15 BCLK5
Sub J101-17 SDIN5
Sub J101-J19 SDOUT5
<KM113200>
Clocks
1fs=8kHz
64fs=512kHz
I2S, 16bit data
Data Monitor
1fs=8kHz
64fs=512kHz
I2S, 16bit data
Data Monitor
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[AKD7719B-A]
(3) Evaluation Port : Port#1 to Port#4 and Port#4 to Port#1
Format : fs=8kHz, BCLK=64fs, I2S 16bit data
Condition
SYNC1
BCLK1
SDIN1
SDOUT1
SYNC2
BCLK2
SDIN2
SDOUT2
SYNC3
BCLK3
SDIN3
SDOUT3
SYNC4
BCLK4
SDIN4
SDOUT4
SYNC5
BCLK5
SDIN5
SDOUT5
INPUT
INPUT
INPUT
OUTPUT
INPUT
INPUT
INPUT
OUTPUT
INPUT
INPUT
INPUT
OUTPUT
INPUT
INPUT
INPUT
OUTPUT
INPUT
INPUT
INPUT
OUTPUT
Name
J2-3 EXT-SYNC1
J2-1 EXT-BCLK1
J2-5 EXT-SDIN1
J2-7 EXT-SDOUT1
Sub J101-1 SYNC2
Sub J101-3 BCLK2
J2-13 EXT-SDIN2
J2-15 EXT-SDOUT2
Sub TP02 SYNC3
Sub TP17 BCLK3
Sub TP28 SDIN3
Sub TP27 SDOUT3
Sub J101-5 SYNC4
Sub J101-7 BCLK4
J2-25 EXT-SDIN4
J2-27 EXT-SDOUT4
Sub J101-11 SYNC5
Sub J101-15 BCLK5
Sub J101-17 SDIN5
Sub J101-J19 SDOUT5
Clocks
1fs=8kHz
64fs=512kHz
I2S, 16bit data
Data Monitor
1fs=8kHz
64fs=512kHz
I2S, 16bit data
Data Monitor
-
(4) Evaluation Port : Port#1 to Port#5 and Port#5 to Port#1
Format : fs=8kHz, BCLK=64fs, I2S 16bit data
Condition
SYNC1
BCLK1
SDIN1
SDOUT1
SYNC2
BCLK2
SDIN2
SDOUT2
SYNC3
BCLK3
SDIN3
SDOUT3
SYNC4
BCLK4
SDIN4
SDOUT4
SYNC5
BCLK5
SDIN5
SDOUT5
INPUT
INPUT
INPUT
OUTPUT
INPUT
INPUT
INPUT
OUTPUT
INPUT
INPUT
INPUT
OUTPUT
INPUT
INPUT
INPUT
OUTPUT
INPUT
INPUT
INPUT
OUTPUT
Name
J2-3 EXT-SYNC1
J2-1 EXT-BCLK1
J2-5 EXT-SDIN1
J2-7 EXT-SDOUT1
Sub J101-1 SYNC2
Sub J101-3 BCLK2
J2-13 EXT-SDIN2
J2-15 EXT-SDOUT2
Sub TP02 SYNC3
Sub TP17 BCLK3
Sub TP28 SDIN3
Sub TP27 SDOUT3
Sub J101-5 SYNC4
Sub J101-7 BCLK4
J2-25 EXT-SDIN4
J2-27 EXT-SDOUT4
Sub J101-11 SYNC5
Sub J101-15 BCLK5
Sub J101-17 SDIN5
Sub J101-J19 SDOUT5
<KM113200>
Clocks
1fs=8kHz
64fs=512kHz
I2S, 16bit data
Data Monitor
1fs=8kHz
64fs=512kHz
I2S, 16bit data
Data Monitor
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[AKD7719B-A]
(5) Evaluation Port : Port#1 to Port#2 and Port#2 to Port#1, Port2=Master
Format : fs=8kHz, BCLK=64fs, I2S 16bit data
Condition
SYNC1
BCLK1
SDIN1
SDOUT1
SYNC2
BCLK2
SDIN2
SDOUT2
SYNC3
BCLK3
SDIN3
SDOUT3
SYNC4
BCLK4
SDIN4
SDOUT4
SYNC5
BCLK5
SDIN5
SDOUT5
INPUT
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
OUTPUT
INPUT
INPUT
INPUT
OUTPUT
INPUT
INPUT
INPUT
OUTPUT
INPUT
INPUT
INPUT
OUTPUT
Name
J2-3 EXT-SYNC1
J2-1 EXT-BCLK1
J2-5 EXT-SDIN1
J2-7 EXT-SDOUT1
Sub J101-1 SYNC2
Sub J101-3 BCLK2
J2-13 EXT-SDIN2
J2-15 EXT-SDOUT2
Sub TP02 SYNC3
Sub TP17 BCLK3
Sub TP28 SDIN3
Sub TP27 SDOUT3
Sub J101-5 SYNC4
Sub J101-7 BCLK4
J2-25 EXT-SDIN4
J2-27 EXT-SDOUT4
Sub J101-11 SYNC5
Sub J101-15 BCLK5
Sub J101-17 SDIN5
Sub J101-J19 SDOUT5
Clocks
1fs=8kHz
64fs=512kHz
I2S, 16bit data
Data Monitor
SYNC Monitor
BCLK Monitor
I2S, 16bit data
Data Monitor
-
(6) Evaluation Port : Port#1 to Port#5 and Port#5 to Port#1, Port5=Master
Format : fs=8kHz, BCLK=64fs, I2S 16bit data
Condition
SYNC1
BCLK1
SDIN1
SDOUT1
SYNC2
BCLK2
SDIN2
SDOUT2
SYNC3
BCLK3
SDIN3
SDOUT3
SYNC4
BCLK4
SDIN4
SDOUT4
SYNC5
BCLK5
SDIN5
SDOUT5
INPUT
INPUT
INPUT
OUTPUT
INPUT
INPUT
INPUT
OUTPUT
INPUT
INPUT
INPUT
OUTPUT
INPUT
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
OUTPUT
Name
J2-3 EXT-SYNC1
J2-1 EXT-BCLK1
J2-5 EXT-SDIN1
J2-7 EXT-SDOUT1
Sub J101-1 SYNC2
Sub J101-3 BCLK2
J2-13 EXT-SDIN2
J2-15 EXT-SDOUT2
Sub TP02 SYNC3
Sub TP17 BCLK3
Sub TP28 SDIN3
Sub TP27 SDOUT3
Sub J101-5 SYNC4
Sub J101-7 BCLK4
J2-25 EXT-SDIN4
J2-27 EXT-SDOUT4
Sub J101-11 SYNC5
Sub J101-15 BCLK5
Sub J101-17 SDIN5
Sub J101-J19 SDOUT5
<KM113200>
Clocks
1fs=8kHz
64fs=512kHz
I2S, 16bit data
Data Monitor
SYNC Monitor
BCLK Monitor
I2S, 16bit data
Data Monitor
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[AKD7719B-A]
CONTROL SOFTWARE MANUAL
■ Setup of the Evaluation Board and Control Software
(1) Power the AKD7719B-A evaluation board on and connect it with a USB control box.
(2) Connect the USB control box to a PC with a USB cable.
The USB control box will be recognized as HID (Human Interface Device). When it can not be recognized
correctly (e.g., unknown device is connected), please push reset button [yellow] on the USB control box.
(3) Install AK7719B.exe to the PC. Then ready to evaluate.
The start-up image of control software is as below.
Figure 3. Start-up Image of Control Software (AK7719B_A_HF.exe)
(4) Push the “Board Init” button to make sure that this control software access registers. Only if just pushing the “PDN
Pin” button this cannot access the registers.
When the connection of PC with the USB control box is removed, it is required to restart the control software.
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[AKD7719B-A]
■ Download the DSP Program and Registers Software
1.
Register Setting and Code Downloading
1-1. Register Setting
(1) Select the SCRIPT tab to set register values.
(2) load script file
(2)
(1)
File (Example): script19B_test.txt
(Port#1 to Port#2 and Port#2 to Port#1)
Script File: xxxxx.txt
After loading the script file,
the AK7719B becomes reset state.
Confirm that DSP/Clock block are
powered-down.
(2) “script19B_test.txt” runs under the condition below.
FSMode00: 8kHz / 16bit Linear / I2S
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[AKD7719B-A]
1-2. Code Downloading
There are four code areas as shown below.
Code Area
Alias
Control Register
CONT
Program RAM
PRAM
Coefficient RAM
CRAM
Offset Register
OFREG
Function
AK7719B operation mode setup
Storage RAM for program code
Storage RAM for parameter used by program code
Pointer for delay RAM address
Table 5. AK7719B Code Area
(Note 1) All codes (CONT, PRAM, CRAM and OFREG) will be provided by AKM.
(1) Click the DownLoad tab and see if the file to be downloaded.
(1)
(2) Program, CRAM, OFREG to be
downloaded
PRAM File (Example): DSP19B_test.obj
(Port#1 to Port#2 and Port#2 to Port#1)
(2)
PRAM File: xxxxx.obj
CRAM File: xxxxx.cra
OFREG File: xxxxx.off
(3)
(4)
A
Figure 4. [Download] Dialogue of Control Software
(3) Check the “CRC_Check” box, click the Write button to download DSP programs into the AK7719B.
If a write error is occurred, check if the clocks are provided to the AK7719B.
(4) Click the DSPRSTN botton. Confirm Run state of the DSPRSTN button
Now, the AK7719B is in running state. Input signal to the Port#1(SDIN1) is output from SDOUT2 or 3 or 4 or 5.
AK7719B DSP&SRC
SDIN1
DSP
SRC
SDOUT2
SRC
SDOUT5
SRC
SDOUT3
SDOUT4
Figure 3. Signal Flow
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[AKD7719B-A]
REVISION HISTORY
Date
(yy/mm/dd)
13/04/09
Manual
Revision
KM113200
Board
Revision
0
Reason
Page
Contents
First edition
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contained in this document without notice. When you consider any use or application of AKM product
stipulated in this document (“Product”), please make inquiries the sales office of AKM or authorized
distributors as to current status of the Products.
1. All information included in this document are provided only to illustrate the operation and application
examples of AKM Products. AKM neither makes warranties or representations with respect to the accuracy
or completeness of the information contained in this document nor grants any license to any intellectual
property rights or any other rights of AKM or any third party with respect to the information in this
document. You are fully responsible for use of such information contained in this document in your product
design or applications. AKM ASSUMES NO LIABILITY FOR ANY LOSSES INCURRED BY YOU OR
THIRD PARTIES ARISING FROM THE USE OF SUCH INFORMATION IN YOUR PRODUCT
DESIGN OR APPLICATIONS.
2. The Product is neither intended nor warranted for use in equipment or systems that require extraordinarily
high levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human
life, bodily injury, serious property damage or serious public impact, including but not limited to,
equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment,
equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment,
equipment used to control combustions or explosions, safety devices, elevators and escalators, devices
related to electric power, and equipment used in finance-related fields. Do not use Product for the above use
unless specifically agreed by AKM in writing.
3. Though AKM works continually to improve the Product’s quality and reliability, you are responsible for
complying with safety standards and for providing adequate designs and safeguards for your hardware,
software and systems which minimize risk and avoid situations in which a malfunction or failure of the
Product could cause loss of human life, bodily injury or damage to property, including data loss or
corruption.
4. Do not use or otherwise make available the Product or related technology or any information contained in
this document for any military purposes, including without limitation, for the design, development, use,
stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products
(mass destruction weapons). When exporting the Products or related technology or any information
contained in this document, you should comply with the applicable export control laws and regulations and
follow the procedures required by such laws and regulations. The Products and related technology may not
be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited
under any applicable domestic or foreign laws or regulations.
5. Please contact AKM sales representative for details as to environmental matters such as the RoHS
compatibility of the Product. Please use the Product in compliance with all applicable laws and regulations
that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS
Directive. AKM assumes no liability for damages or losses occurring as a result of noncompliance with
applicable laws and regulations.
6. Resale of the Product with provisions different from the statement and/or technical features set forth in this
document shall immediately void any warranty granted by AKM for the Product and shall not create or
extend in any manner whatsoever, any liability of AKM.
7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
consent of AKM.
<KM113200>
2013/04
- 15-
5
4
3
2
1
EXT
AK7719
D
EXT-STO/RDY
AK7719-STO/RDY
EXT-BCLK1
EXT-SYNC1
EXT-SDIN1
EXT-SDOUT1
AK7719-BCLK1
AK7719-SYNC1
AK7719-SDIN1
AK7719-SDOUT1
EXT-BCLK2
EXT-SYNC2
EXT-SDIN2
EXT-SDOUT2
AK7719-BCLK2
AK7719-SYNC2
AK7719-SDIN2
AK7719-SDOUT2
D
EXT-SDIN3
EXT-SDOUT3/GP0
AK7719-SDIN3
AK7719-SDOUT3/GP0
EXT-SDIN4
EXT-SDOUT4/GP1
AK7719-SDIN4
AK7719-SDOUT4/GP1
SELECTOR
EXT-JX0/BCLK3
EXT-JX1/SYNC3
SEL-EXT-JX0/BCLK3
SEL-EXT-JX1/SYNC3
SEL-DSP-JX0/BCLK3
SEL-DSP-JX1/SYNC3
AK7719-JX0/BCLK3
AK7719-JX1/SYNC3
EXT-CSN/SCL
EXT-SCLK/CAD0
EXT-SI/CAD1
EXT-SO/SDA
SEL-EXT-CSN/SCL
SEL-EXT-SCLK/CAD0
SEL-EXT-SI/CAD1
SEL-EXT-SO/SDA
SEL-DSP-CSN/SCL
SEL-DSP-SCLK/CAD0
SEL-DSP-SI/CAD1
SEL-DSP-SO/SDA
AK7719-CSN/SCL
AK7719-SCLK/CAD0
AK7719-SI/CAD1
AK7719-SO/SDA
SEL-EXT-PDN
B
AK7719-PDN
SEL-DSP-I2C
SEL-DSP-TEST
SEL-DSP-BUFE
AK7719-I2C
AK7719-TEST
AK7719-BUFE
SEL-CTRL-RESET
SEL-CTRL-RQN
SEL-CTRL-SCK/SCL
SEL-CTRL-SI
SEL-CTRL-SO
SEL-CTRL-XCS/SDA
EXT
SEL-DSP-PDN
AK7719
MONITOR
B
SELECTOR
CTRL
CTRL-HOST
CTRL-CSN
CTRL-DSP-I2C
A
CTRL-RESET
MONITOR
CTRL-RQN
CTRL-SCK/SCL
CTRL-SI
CTRL-SO
CTRL-XCS/SDA
POWER
A
Title
POWER
AKD7719B-A-MAIN
CTRL
Size
A
- 165
4
C
mon-PDN
EXT-PDN
mon-BICK1
mon-SYNC1
mon-SDIN3
mon-SPDIF
mon-SDLED
C
3
Date:
Document Number
TOP
Monday, April 08, 2013
2
Rev
0
Sheet
1
of
1
7
5
4
3
2
1
CN1
DSP-STO/RDY
CN2
1
AK7719
DSP-JX1/SYNC3
2
D
DSP-SDIN2
消費電流測定時
Cut Land openにして
AK7719にのみ電源供給可
3
0.1uはAK7719の近くに
配置してください
DSP-PDN
7719-VDD+1.2V
C1
4
DSP-SDIN4
I2C
A5
A4
DSP-SDOUT2
U2
55
54
52
AK7719-BCLK1
AK7719-SYNC1
AK7719-SDIN1
DSP-SDOUT1
51
DSP-SYNC2
DSP-BCLK2
49
48
47
GND
GND
GND
GND
GND
GND
GND
GND
1A1
1A2
1A3
1A4
1OE1
1OE2
2OE1
2OE2
VCC
VCC
VCC
VCC
5
6
AK7719-SO/SDA
7
AK7719-SCLK/CAD0
8
1
56
28
29
AK7719-SDIN2
45
DSP-SDOUT2
44
AK7719-JX1/SYNC3
43
AK7719-JX0/BCLK3
AK7719-SDIN3
DSP-SDOUT3/GP0
DSP-STO/RDY
DSP-SDOUT4/GP1
A
AK7719-SDIN4
AK7719-I2C
AK7719-PDN
AK7719-TEST
R19
R21
0
0
42
41
40
38
37
36
34
33
31
30
1A5
1A6
1A7
1Y5
1Y6
1A8
1Y7
1Y8
1A9
1Y9
1A10
2A1
2A2
2A3
1Y10
2Y1
2Y2
2Y3
2A4
2A5
2A6
2A7
2A8
2Y4
2Y5
2Y6
2Y7
2Y8
2A9
2A10
2Y9
2Y10
VDD
SI/CAD1
VSS
CSN/SCL
A2
DSP-TEST
C3
DSP-SYNC1
E5
DSP-BCLK1
D5
DSP-SDIN1
B5
DSP-SDOUT1
C5
DSP-JX1/SYNC3
B3
TVDD
SO/SDA
TEST
STO/RDY
SYNC1
SYNC2
BCLK1
BCLK2
A1
AK7719-SI/CAD1
C1
AK7719-CSN/SCL
D1
AK7719-SO/SDA
D3
DSP-STO/RDY
E4
DSP-SYNC2
E3
DSP-BCLK2
E1
DSP-SDOUT2
E2
DSP-SDIN2
D
DSP-SYNC2
26
DSP-SDOUT1
24
DSP-SDIN1
23
DSP-PDN
22
DSP-BCLK1
21
SDIN1
C4
50
35
22
7
AK7719-CSN/SCL
0.1uF
C5
10
AK7719-SI/CAD1
11
SDOUT2
C
B4
DSP-SDIN3
C4
SDIN2
20
DSP-SYNC1
19
JX1/SYNC3
7719-VDD+1.2V
C6
JX0/BCLK3
18
0.1uF
4.7uF
2
3
5
6
R1
R2
R3
R4
51
51
51
51
8
9
R5
R6
51
51
10
12
R7
R8
51
51
DSP-SDIN2
13
R9
open
DSP-JX1/SYNC3
14
R10
open
DSP-JX0/BCLK3
15
16
17
R11
R12
R13
open
open
51
DSP-SDIN3
19
20
21
23
24
R14
R15
R16
R17
R18
51
51
51
51
51
26
27
DSP-JX0/BCLK3
SDOUT1
DSP-BCLK1
DSP-SYNC1
DSP-SDIN1
AK7719-SDOUT1
R20
R22
SDOUT4/GP1
DSP-SDOUT4/GP1
DSP-JX0/BCLK3
17
DSP-SDOUT3/GP0
DSP-SDOUT4/GP1
SDIN3
D2
12
D4
SDOUT3/GP0
SDIN4
C2
DSP-SDIN4
13
16
14
15
DSP-BCLK2
B
AK7719-SYNC2
AK7719-BCLK2
28pin_L
28pin_R
AK7719-SDOUT2
20130405改造仕様書
Port3入出力方法変更に伴う改造
R9,R10,R11,R12を
51ohm -> Openに変更。
AK7719-SDOUT3/GP0
AK7719-STO/RDY
DSP-SDIN4
DSP-I2C
DSP-PDN
DSP-TEST
AK7719-SDOUT4/GP1
A
0
0
Title
Size
B
SN74ALVCH16827
Date:
5
AK7719-SCLK/CAD0
C3
7719-TVDD
TVDD
DSP-TEST
B
B1
AK7719-BUFE
DSP-I2C
1Y1
1Y2
1Y3
1Y4
SCLK/CAD0
DSP-I2C
25
A3
9
53
46
39
32
25
18
11
4
PDN
DSP-SDOUT3/GP0
27
B2
0.1uF
0.1uF
外部システムに乗っているAK7719を使用するときは
DIP-SW(7719)をEXTにしてバッファをHiZにする
U1
7719-TVDD
C2
0.1uF
C
DSP-SDIN3
28
4
3
- 17-
2
AKD7719B-A-MAIN
Document Number
AK7719
Monday, April 08, 2013
Sheet
1
Rev
0
2
of
7
5
4
3
2
1
VDD+3.3V
C7 0.1uF
4.7k 4.7k
5
CTRL-DSP-I2C
0
7
R27
0
6
SCLB
SDAB
D
SCLA
4
R25
EN
VCCA
VCCB
U3
GND
R23 R24
D
C8 0.1uF
1
TVDD
I2CピンによってI2C双方向バッファと
2電源レベルシフタの切り替え
I2C=Lのとき、SCK,XCS,RQN.SI
I2C=Hのとき、SCL,SDA
8
VDD+3.3V
SDAA
2
R26
0
3
R28
0
PCA9517
VDD+3.3V
TVDD
C9 0.1uF C10 0.1uF
TVDD
0
HEADER 5X2
PC-RQN
PC-SI
PC-SO
PC-RESET
R35
R31
R39
R41
13
12
11
10
0
0
0
51
1B1
1B2
2B1
2B2
R83
Dip4.7k
1A1
1A2
2A1
2A2
SN74AVC4T245PW
9
8
CONTROL
4.7k 1.0k 1.0k
4
5
6
7
R36
R37
R40
R42
0
0
0
0
C
20110804改造仕様書
SCL/SDAの立上りを早くするため
1.0kに変更
CTRL-SCK/SCL
CTRL-XCS/SDA
CTRL-RQN
CTRL-SI
2DIR
1DIR
R43
2
4
6
8
10
R32 R29 R33
U4
B → A
3
2
CTRL-CSN
PC-SCK/SCL
PC-XCS/SDA
1
3
5
7
9
1OEN
2OEN
CTRL-HOST
0
15
14
4.7k 4.7k
JP1
R38
VCCB
R34 R30
GND
GND
C11 0.1uF
1
2
VCCA
VDD+3.3V
C
1
16
VDD+3.3V
20110804改造仕様書
PCA9517の信号には
プルアップ必要
VDD+3.3V
B
B
C12 0.1uF
TVDD
C13 0.1uF
7
R47
0
6
1
SCLB
SDAB
R45
VCCA
EN
SCLA
4
0
GND
5
R44
VCCB
U5
8
TVDD
SDAA
4.7k
2
R46
0
3
R48
0
CTRL-SO
CTRL-RESET
R84
PCA9517
20110804改造仕様書
PCA9517の信号には
4.7k プルアップ必要
A
A
常にA=Bの状態
SOは
←
RESETは →
Title
AKD7719B-A-MAIN
Size
B
Date:
5
4
3
- 18-
2
Document Number
Monday, April 08, 2013
CTRL
Sheet
1
Rev
0
3
of
7
5
4
3
2
1
D
D
J1
EXT-JX0/BCLK3
EXT-JX1/SYNC3
EXT-SDIN3
EXT-SDOUT3/GP0
EXT-SDIN4
EXT-SDOUT4/GP1
EXT-STO/RDY
EXT-PDN
R50
R49
R53
51
51
51
R55
51
R57
51
LED ：SDOUT3
SPDIF：SDOUT4
C
2
4
6
8
10
12
14
16
18
20
22
24
1
3
5
7
9
11
13
15
17
19
21
23
R51
R52
R54
51
51
51
R56
51
R58
R59
R60
R61
51
51
51
51
EXT-BCLK1
EXT-SYNC1
EXT-SDIN1
EXT-SDOUT1
EXT-BCLK2
EXT-SYNC2
EXT-SDIN2
EXT-SDOUT2
EXT-CSN/SCL
EXT-SO/SDA
EXT-SCLK/CAD0
EXT-SI/CAD1
EXT-VDD+1.2V
C14
C
HEADER 12X2
0.1uF
EXT
EXT-TVDD
C15
0.1uF
EXT-TVDDはMONITORレベルシフタ電源
ジャンパーで独立/TVDDの切り替え可
EXT-VDD+1.2VはEXTから安定した1.2Vが
与えられる場合に使用
B
B
J2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
1
3
5
7
9
11
13
15
17
19
21
23
25
27
A
A
HEADER 14X2
Title
AKD7719B-A-MAIN
TEST
Size
A
- 195
4
3
Date:
Document Number
Monday, April 08, 2013
2
EXT
Rev
0
Sheet
4
of
1
7
5
4
3
2
1
D
D
EXT-TVDD
VDD+3.3V
C17
0.1uF
0.1uF
B1
B2
B3
B4
B5
B6
U6
A8
A7
OEN
DIR
3
4
5
6
7
8
A1
A2
A3
A4
A5
A6
SDO-LED
SDO-SPDIF
BICK1
SYNC1
PDN
0.1uF
0.1uF
2
4
6
8
10
C
0.1uF
MONITOR
B
VCCB
SN74AVCH1T45DCK
4
DIR
B
A←B
5
VCCA
A
GND
3
2
51
1
3
5
7
9
6
C20
1
R67
C18
JP2
VDD+3.3V
C19
U7A
mon-SDIN3
51
51
51
51
51
B→A
EXT-TVDD
B
R62
R63
R64
R65
R66
HEADER 5X2
10
9
13
12
11
22
2
GND
GND
GND
SN74AVC8T245PW
B7
B8
21
20
19
18
17
16
15
14
C
mon-SDLED
mon-SPDIF
mon-BICK1
mon-SYNC1
mon-PDN
VDD+3.3V
VCCA
VCCB
VCCB
1
23
24
C16
A
A
Title
AKD7719B-A-MAIN
Size
A
- 205
4
3
Date:
Document Number
MONITOR
Sheet
Monday, April 08, 2013
2
Rev
0
5
of
1
7
5
4
3
2
1
TVDD
消費電流測定時
Cut Land openにして
AK7719にのみ電源供給可
TP1
CL1
Cut Land short
D
D
7719-TVDD
RED
1
2
1
3.3V
VDD+3.3V
TVDD
JP3
EXT-TVDD
JMP2_1
JP4
open ： TVDD = TVDDテストピン入力
short ： TVDD = 3.3Vヘッダー入力
JMP2_1
EXT-TVDD
1.0uFおよび10uFはできるだけ
REGの近くに配置してください
REG1
XC6210B-1.2
JP5
形状はVDDとGNDの
バナナとDriveBlueﾎﾞｰﾄﾞ
のような電源コネクタ
3
C21
C22
+
10uF/16V(A)
1.0uF
IN
CE
OUT
NC
C
REG+1.2V
VDD
5
4
TP2
+ C23
10uF
C24
YELLOW
REG
0.1uF
1
1
1
2
GND
HEADER 2
open ： EXT-TVDD = 12x2ヘッダー入力
short ： EXT-TVDD = JP3
2
3.3V
C
7719-VDD+1.2V
JP6
EXT-VDD+1.2V
JMP2_1
JP7
open ： VDD = VDDテストピン入力
short ： VDD = REG+1.2V
B
B
JMP2_1
EXT-VDD
open ： VDD = JP6
short&JP6=open ： VDD = 12x2ヘッダー入力
TP3
1
BLACK
A
A
Title
AKD7719B-A-MAIN
Size
A
- 215
4
3
Date:
Document Number
POWER
Sheet
Monday, April 08, 2013
2
Rev
0
6
of
1
7
5
4
3
2
1
U8
NC3
NO3
NC4
NO4
IN3-4
COM4
TVDD
12
V+
GND
9
2
1
7
5
11
9
8
7
4
5
SEL-EXT-SCLK/CAD0
IF-CAD0
EXT-SDA
CTRL-SDA
3
SEL-EXT-SI/CAD1
IF-CAD1
SEL-DSP-I2C
EXT-SCL
4
TS3A44159PW
C26
DIP-JXE
DIP-JX1
DIP-JX0
COM3
15
13
3
1
16
CTRL-SCL
TP4
TP5
TP6
TP7
LBLUE
WHITE
LBLUE
WHITE
1
10
D
NC1
NO1
NC2
NO2
IN1-2
COM2
1
6
COM1
1
2
SEL-EXT-JX1/SYNC3
1
14
SEL-EXT-JX0/BCLK3
U9
R70 R71
NC1
NO1
IN1
COM1
NC2
NO2
IN2
COM2
GND
V+
S1
5
6
7
8
PDN
SDA
SCLK
SCL
4
3
2
1
R73
R75
R76
R78
10k
4.7k
4.7k
4.7k
SW DIP-4
2
6
10
SEL-EXT-SO/SDA
COM2
COM3
COM4
TVDD
12
V+
IF-EXT-CSN/SCL
IF-CTRL-CSN/SCL
IF-EXT-SCLK/CAD0
IF-CTRL-SCLK/CAD0
15
13
3
1
16
IF-EXT-SI/CAD1
IF-CTRL-SI/CAD1
IF-EXT-SO/SDA
IF-CTRL-SO/SDA
DIP-MAINIF
7
5
11
9
8
4
NC1
NO1
NC2
NO2
IN1-2
NC3
NO3
NC4
NO4
IN3-4
GND
15
13
3
1
16
0
SEL-DSP-JX1/SYNC3
TVDD
8
EXT or DIP → DSP
D
NC1
NO1
NC2
NO2
IN1-2
COM1
NC3
NO3
NC4
NO4
IN3-4
COM3
GND
V+
COM2
COM4
14
R72
0
2
R74
0
6
R77
0
10
R79
0
SEL-DSP-CSN/SCL
SEL-DSP-SCLK/CAD0
SEL-DSP-SI/CAD1
SEL-DSP-SO/SDA
TVDD
12
EXT or CtrlBox → DSP
TS3A44159PW
C27
C
0.1uF
7
5
11
9
8
DIP-EXTIF
SEL-EXT-PDN
4
U12
DIP-EXTIF
9
2
1
DIP-MAINIF
7
4
5
TS3A44159PW
C28
0.1uF
CtrlBox → EXT/EXT → DSP
SEL-CTRL-RESET
3
CtrlBox → EXT/EXT → DSP or
EXT or CtrlBox → DSP
CtrlBox(SPI or I2C) → MAIN and EXT
B
R69
10k 10k
U11
COM1
6
SEL-DSP-JX0/BCLK3
U10
TVDD
14
0
0.1uF
DIP-SWの動作
ON(1側) ： Pull-up
OFF ： -
PULL-UP[OFF/ON]
SEL-EXT-CSN/SCL
R68
TS5A23159DGS
C25
0.1uF
C
10
NC1
NO1
IN1
COM1
NC2
NO2
IN2
COM2
GND
V+
10
6
R80
0
SEL-DSP-PDN
MONITORのPDNも共通
TVDD
8
TS5A23159DGS
C29
B
U13
SEL-CTRL-SI
IF-CAD1
IF-CTRL-SO/SDA
SEL-DSP-I2C
NC1
NO1
NC2
NO2
IN1-2
7
5
11
9
8
4
14
COM1
NC3
NO3
NC4
NO4
IN3-4
COM3
GND
V+
0.1uF
2
COM2
TVDD
6
10
COM4
12
2 1 CL2
Cut Land open
U15
2
NC
NO
IN
GND
COM
4
CAD0
CAD1
IF-CAD0
IF-CAD1
SEL-CTRL-XCS/SDA
TVDD
V+
8
7
6
5
4
3
2
1
SW DIP-8
0.1uF
3
1
6
9
10
11
12
13
14
15
16
SEL-DSP-I2C
DIP-JXE
DIP-JX0
DIP-JX1
SEL-DSP-TEST
R81
R82
10k
10k
7719[MAIN/EXT]
MAINIF[EXT/CTRL]
EXTIF[MAIN/CTRL]
I2C
JXE
JX0
JX1
TEST
R85 R86
Dip10k
Dip10k
U14
20110804改造仕様書
DIPSW ： H→L
の動作をしない不具合対応
PACK8-10k
A
5
Title
TS5A3159
C31
Size
B
0.1uF
Date:
5
SEL-DSP-BUFE
DIP-MAINIF
DIP-EXTIF
TVDD
TS3A44159PW
C30
A
DIP-SWの動作
ON(1側) ： TVDD
OFF ： Pull-down
SEL-CTRL-SO
TVDD
S2
9
8
7
6
5
4
3
2
1
IF-CAD0
15
13
3
1
16
2 1 CL3
Cut Land open
SEL-CTRL-RQN
SEL-CTRL-SCK/SCL
4
3
- 22-
2
AKD7719B-A-MAIN
Document Number
SELECTOR
Monday, April 08, 2013
Sheet
1
Rev
0
7
of
7
5
4
3
テストピン（TPｘｘ_x）はCN1/CN2－U1間に
CN1/CN2に平行に配置して下さい。
テストピンの配置が難しい場合は千鳥配置として下さい。
元のCNピン名：
CN1
STO/RDY_O
PDN-I
1
SYNC3/JX1_I
SDIN2_I
SYNC3/JX1-I
SDIN2-I
3
TP02
TP03
コンデンサC1/C2は
AK7719B-CSPの
近傍に配置して下さい。
VSS
SYNC3/JX1-I
4
SDIN4_I
5
SDOUT2_O
C
SO/SDA_IO
SCLK/CAD0_I
NC
C4
SDIN4-I
TP05
SDIN4-I
SYNC1-I
E6
BCLK1-I
D6
SDIN1-I
B6
SDOUT1-O
C6
SYNC3/JX1-I
B4
BCLK3/JX0-I
B5
SDIN3-I
C5
SDOUT3/GP0-O
D5
TP07
TP08
SDOUT2-O
CSN/SCL-I
10
SI/CAD1_I
SI/CAD1-I
11
TP10
TP11
I2C
VDD
SCLK/CAD0
VSS
SI/CAD1
TVDD
CSN/SCL
TEST
SO/SDA
SYNC1
SYNC2
BCLK1
BCLK2
SDIN1
SDIN2
SDOUT1
SDOUT2
I2C-I
12
TP12
CSN/SCL-I
SYNC3/JX1
SYNC4
BCLK3/JX0
BCLK4
SDIN3
SDIN4
SDOUT3/GP0
SDOUT4/GP1/STO/RDY
SDOUT4/GP1_O
13
TEST_I
14
SDOUT4/GP1/STO/RDY-OTP13
TEST-I
TP14
B2
SCLK/CAD0-I
A2
SI/CAD1-I
C2
CSN/SCL-I
D2
SO/SDA-IO
E5
SYNC2-IO
E4
BCLK2-IO
E3
SDIN2-I
E2
SDOUT2-O
B1
SYNC4-I
A1
BCLK4-I
C3
SDIN4-I
D3
SDOUT4/GP1/STO/RDY-O
SDIN3-I
SDOUT1-O
E1
SYNC5-IO
D1
BCLK5-IO
C1
SDIN5-I
D4
SDOUT5-O
I2C-I
SDOUT4/GP1/STO/RDY-O
SDIN5
SDOUT5
TEST-I
SDIN3-I
TP28
SDOUT3/GP0-O TP27
SI/CAD1-I
BCLK5
B
I2C-I
SCLK/CAD0-I
SYNC5
I2C_I
B3
SO/SDA-IO
9
CSN/SCL_I
A3
TEST-I
TP06
PDN
open
SYNC2-IO R101
SYNC2-O
C102
0.1uF
TVDD
SCLK/CAD0-I
8
A4
TP04
SO/SDA-IO
7
C101
0.1uF
TVDD
SDOUT2-O
6
A5
元のCNピン名：
U101
SDIN2-I
TVDD
TVDD
A6
VDD
2
1
テストピン（TPｘｘ_x）はCN1/CN2－U1間に
CN1/CN2に平行に配置して下さい。
テストピンの配置が難しい場合は千鳥配置として下さい。
CN2
AK7719B-CSP
D
2
SDOUT3/GP0-O
TP26
SYNC2-O
TP25
SDOUT1-O
SDIN1-I
TP23
SDIN1-I
PDN-I
TP22
PDN-I
BCLK1-I
TP21
BCLK1-I
SYNC1-I
TP19
SYNC1-I
VDD
TP18
VDD
BCLK3/JX0-I TP17
BCLK2-IO
R102 openBCLK2-O
VSS
BCLK3/JX0-I
TP16
BCLK2-O
TP15
VSS
28pin_L
28
SDIN3_I
27
SDOUT3/GP0_O
26
SYNC2_O
25
SDOUT1_O
24
NC
23
SDIN1_I
22
PDN_I
21
BCLK1_I
20
NC
19
SYNC1_I
18
VDD
17
BCLK3/JX0_I
16
BCLK2_O
15
VSS
D
C
B
28pin_R
J101
VSS
2
4
6
8
10
12
14
16
18
20
1
3
5
7
9
11
13
15
17
19
SYNC2-I
R103
51 SYNC2-IO
BCLK2-I
R104
51 BCLK2-IO
SYNC4-I-1
R105
51
BCLK4-I-1
R106
51
SYNC5-O
R107
0
SYNC5-I
R108
51
BCLK5-O
R109
0
BCLK5-I
R110
51
SDIN5-I-1
R111
51
SDIN5-I
0
SDOUT5-O
A
HEADER_10x2
SDOUT5-O-1R112
SYNC4-I
BCLK4-I
SYNC5-IO
A
BCLK5-IO
Title
Size
B
Date:
5
4
3
- 23-
2
AKD7719B-A-30CSP-SUB
Document Number
AKD7719B-A-30CSP-SUB
Thursday, February 07, 2013
Sheet
1
1
of
1
Rev
0