ADAP2 - QR Adapter Design

Design of a QR Adapter with Improved
Efficiency and Low Standby Power
Agenda
1. Quasi-Resonance (QR) Generalities
2. The Valley Lockout Technique
3. The NCP1379/1380
4. Step by Step Design Procedure
5. Performances of a 60 W Adapter Featuring
Valley Lockout
Agenda
1. Quasi-Resonance (QR) Generalities
2. The Valley Lockout Technique
3. The NCP1379/1380
4. Step by Step Design Procedure
5. Performances of a 60 W Adapter Featuring
Valley Lockout
What is Quasi-Square Wave Resonance ?
• MOSFET turns on when VDS(t) reaches its minimum value.
¾ Minimizes switching losses
¾ Improves the EMI signature
valley
MOSFET turns on in first valley
MOSFET turns on in second valley
Quasi-Resonance Operation
•
In DCM, VDS must drop from (Vin + Vreflect) to Vin
•
Because of Lp-Clump network Æ oscillations appear
•
Oscillation half period:
Vin
VDS
Lp
Cout
1:N
Rload
Vout
Vin + Vreflect
Vin
Vin
VDS
t x = π LpClump
SW
Clump
A Need to Limit the Switching Frequency
• In a self-oscillating QR, Fsw increases as the load decreases
Higher losses at light load if Fsw is not limited
• 2 methods to limit Fsw:
– Frequency clamp with frequency foldback
– Changing valley with valley lockout
Frequency Clamp in QR Converters
QR mode
Second valley
First valley
‰ In light load, frequency increases and hits clamp
¾ Multiple valley jumps
¾ Jumps occur at audible range
¾ Creates signal instability
Agenda
1. Quasi-Resonance (QR) Generalities
2. The Valley Lockout Technique
3. The NCP1379/1380
4. Step by Step Design Procedure
5. Performances of a 60 W Adapter Featuring
Valley Lockout
The Valley Lockout
•
As the load decreases, the controller changes valley (1st to 4th valley in
NCP1380)
The controller stays locked in a valley until the output power changes
significantly.
– No valley jumping noise
– Natural switching frequency limitation
80000
70000
VCO mode
4
2 3
1
SWITCHING FREQUENCY (Hz)
•
60000
50000
4th
3rd
2nd
1st
40000
30000
20000
QR operation
10000
0
0
10
VCO mode
20
30
OUTPUT POWER (W)
40
50
60
The Valley Lockout
•
FB comparators select the valley and pass the information to a
counter.
•
The hysteresis of FB comparators locks the valley.
•
2 possible operating set points for a given FB voltage.
VCO
4th
3rd
2nd
1st
0.8
1.2
1.6
2.0
2.4
2.8
3.2
VFB increases (POUT increases)
VFB decreases (POUT decreases)
VFB (V)
Agenda
1. Quasi-Resonance (QR) Generalities
2. The Valley Lockout Technique
3. The NCP1379/1380
4. Step by Step Design Procedure
5. Performances of a 60 W Adapter Featuring
Valley Lockout
NCP1379/1380 Features
• Operating modes:
– QR current-mode with valley lockout for noise immunity
– VCO mode in light load for improved efficiency
HV-bulk
• Protections
‰ Mass production: Q4 2009
Rstart
Ct
1
FB
2
CS
3
GND
4
NCP1380 C/D
ZCD / OPP
8
Dovp
OVP/BO
7
Vcc
6
DRV
5
Czcd
Over power protection
Soft-start
Short circuit protection
Over voltage protection
Over temperature protection
Brown-Out
Rbou
Rzcd2
–
–
–
–
–
–
Rzcd1
Rbol
Ct
Cvcc
QR Mode with Valley Lockout
•
Operating principle:
– Locks the controller into a valley (up to the 4th) according to FB voltage.
– Peak current adjusts according to FB voltage to deliver the necessary
output power.
1.40E+05
VCO mode
Fsw (Pout) for a 60 W adapter
VCO
mode
QR operation
1.20E+05
Fsw (Hz)
1.00E+05
4
2 3
1
8.00E+04
6.00E+04
4th
4.00E+04
3rd
2nd
1st
2.00E+04
0.00E+00
0
10
20
30
40
50
60
Pout (W)
•
Advantages
– Solves the valley jumping instability in QR converters
– Achieves higher min Fsw and lower max Fsw than in traditional QR converters
– Reduce the transformer size
VCO Mode
•
Occurs when VFB < 0.8 V (Pout decreasing) or VFB < 1.4 V (Pout increasing)
•
Fixed peak current (17.5% of Ipk,max), variable frequency set by the FB loop.
Ipk max
Constant peak current (17.5% of Ipk max)
Fsw1 @ Pout1
Fsw2 @ Pout2
Pout1 > Pout2
Combined ZCD and OPP
• Zero-Crossing Detection (ZCD) and Over Power Protection
(OPP) are achieved by reading the Aux. winding voltage
– ZCD function used during the off-time of MOSFET (positive voltage).
– OPP function used during the on-time of MOSFET (negative voltage)
Rzcd
1
Ropu
CS
ZCD/OPP
+
1
Aux
Ropl
ESD
protection
VZCD
+
IpFlag
50 mV
0.8 V + Vopp
0V
0.8 V
Possible restarts for ZCD
VOPP
+
-
Demag
Vth
leakage blanking
DRV
Tblank
VDRV
2
NCP1380 Versions
•
4 versions of NCP1380: A, B, C and D
OTP
OVP
NCP1380 /
A
X
X
NCP1380 /
B
X
X
BO
Latched
Over current protection
Over current protection
X
X
NCP1380 /
C
X
X
NCP1380 /
D
X
X
OTP: Over Temperature Protection
OVP: Over Voltage Protection
BO: Bown-Out
Auto-Recovery
X
X
Short-Circuit Protection
•
Internal 80 ms timer for short-circuit validation.
•
Additional CS comparator with reduced LEB to detect winding short-circuit.
•
VCS(stop) = 1.5 * VILIMIT
S
Q
DRV
Q
R
CS
LEB1
Rsense
+
FB/4
PWMreset
-
Down
Up
TIMER
IpFlag
ZCD/OPP
OPP
Reset
V ILIMIT
grand
reset
Laux
LEB2
+
-
V CS(stop)
CsStop
Stop controller
Short-Circuit Protection (A and C versions)
•
A and C versions: the fault is latched.
– VCC is pulled down to 5 V and waits for ac removal.
S
DRV
Q
Q
Vdd
R
aux
Vcc
latch
VCC
management
CSstop
fault
CS after LEB1
+
FB/4
+
V ILIMIT
grand
reset
PWMreset
Down
Up
IpFlag
TIMER
Reset
-
+
V OPP
S
Q
+
CS after LEB2
CSstop
Q
-
VCS(stop)
t LEB2 < t LEB1
R
grand
reset
VCCstop
SCR delatches
when
ICC < ICCLATCH
Short Circuit Protection (B and D)
•
Auto-recovery short circuit protection: the controller tries to restart
•
Auto-recovery imposes a low burst in fault mode.
Low average input power in fault condition
S
Q
to DRV stage
Vdd
aux
Q
R
Vcc
VCC
management
fault
CS after LEB1
+
FB/4
+
V ILIMIT
grand
reset
VCCstop
Down
Up
IpFlag
TIMER
VCC
Reset
-
+
V OPP
grand
reset
+
CS after LEB2
-
VCS(stop)
t LEB2 < t LEB1
PWMreset
CSstop
VDS
Fault Pin Combinations
• OVP / OTP
• OVP / BO
– NCP1380 A & B versions
VFault
– NCP1380 C & D versions,
NCP1379
VFault
Latch!
Latch!
OK
OK
Latch!
BO
time
• OVP and OTP or OVP and BO combined on one pin.
• Less external components needed.
time
Agenda
1. Quasi-Resonance (QR) Generalities
2. The Valley Lockout Technique
3. The NCP1379/1380
4. Step by Step Design Procedure
5. Performances of a 60 W Adapter Featuring
Valley Lockout
Step by Step Design Procedure
• Calculating the QR transformer
• Predicting the switching frequency
• Implementing Over Power Compensation
• Improving the efficiency at light load with the VCO mode
• Choosing the startup resistors
• Implementing synchronous rectification
Design Example
•
Power supply specification:
–
Vout = 19 V
–
Pout = 60 W
–
Fsw,min = 45 kHz (at Vin = 100 Vdc)
–
600 V MOSFET
–
Vin = 85 ~ 265 Vrms
–
Standby power consumption < 100 mW @ 230 Vrms
Vbulk
Vout
T1
.
.
Gnd
Turns Ratio Calculation
‰ Derate maximum MOSFET BVdss:
Vds , max = BVdss k D
kD: derating factor
‰ For a maximum bulk voltage, select the clamping voltage:
Vds,max
15% derating
Vos
Vclamp
Vclamp = Vds , max − Vin ,max − Vos
Vreflect
Vos: diode overshoot
‰ Deduce turns ratio:
N s kc (Vout + V f )
N ps =
=
Np
Vclamp
BVdss
kc: clamping coef.
kc = Vclamp / Vreflect )
Vbulk,max
How to Choose kc
kc choice dependant of Lleak (leakage inductance of the transformer)
kc value can be chosen to equilibrate MOS conduction losses and
clamping resistor losses.
600-V MOSFET
3
PRclamp
PMOS,on @ Vin,min
2
Ploss (W)
•
•
kleak=0.01
1
kleak=0.008
Ptot ≈ 2.5 W
0
1.2
PRclamp = kleak
PMOS ,on
kc
η kc − 1
1.5
kleak=0.005
1.8
2.1
kc
2.4
2.7
3
Pout
4 Pout 2
= Rdson 2
3η Vin ,min
⎛ 1
kc
+
⎜⎜
⎝ Vin ,min BVdss k D − Vin ,max − Vos
⎞
⎟⎟
⎠
Curves plotted for:
Rdson = 0.77 Ω at Tj = 110
°C
Pout = 60 W
Vin,min = 100 Vdc
Primary Peak Current and Inductance
‰ Pout =
1
Lpri I pri , peak 2 Fswη
2
DCM
Ipri,peak
ton
ton
0
toff
tv
toff
tv
‰ Tsw =
I pri , peak L pri
I pri , peak
Vin ,min
+
I pri , peak L pri N ps
Vout + V f
N ps
Pout ⎛ 1
=2
+
⎜⎜
η ⎝ Vin,min Vout + V f
+ π L pri Clump
⎞
2 Pout Clump Fsw
⎟⎟ + π
η
⎠
Coss contribution
alone.
Lpri =
2 Pout
I pri , peak 2 Fswη
RMS Current
•
Calculate maximum duty-cycle at maximum Pout and minimum Vin:
d max =
•
I pri , peak Lpri
Vin ,min
Fsw,min
Deduce primary and secondary RMS current value:
I pri ,rms = I pri , peak
I sec ,rms =
I pri , peak
N ps
d max
3
1 − d max
3
Ipri,rms and Isec,rms
Losses calculation
Design Example
‰ Based on equations from slides 11 to 14:
¾ Turns ratio:
¾ Peak current:
N ps =
kc (Vout + V f )
BVdss k D − Vin , max − Vos
I pri , peak =
=
¾ Inductance:
Lpri =
¾ Max. duty-cycle:
=
1.3 × (19 + 0.8)
⇒
600 × 0.85 − 375 − 10
N ps
2 Pout ⎛ 1
+
⎜⎜
η ⎝ Vin,min Vout + V f
⎞
2 Pout Clump Fsw
⎟⎟ + π
η
⎠
2 × 60 ⎛ 1
0.25 ⎞
2 × 60 × 250 p × 45k
+
⎜
⎟+π
0.85 ⎝ 100 19.8 ⎠
0.85
2 Pout
2 × 60
=
I pri , peak 2 Fswη 3.322 × 45k × 0.85
d max =
¾ Primary rms current:
¾ Secondary rms current:
N ps ≈ 0.25
I pri , peak Lpri
Vin ,min
Fsw,min =
I pri ,rms = I pri , peak
I sec ,rms =
⇒ Lpri = 285 µH
3.32 × 285µ
45k ⇒ d max = 0.43
100
d max
0.43
= 3.32
3
3
I pri , peak
N ps
⇒ I pri , peak = 3.32 A
⇒ I pri ,rms = 1.26 A
1 − d max 3.32 1 − 0.43
=
3
0.25
3
⇒ I sec ,rms = 5.8 A
Predicting the Switching Frequency
•
The controller changes valley as the load decreases.
=> How can we predict the switching frequency evolution as the load varies ?
•
Depending upon the power increase or decrease, the FB levels at which
the controller changes valley are different => valley lockout
Predicting the Switching Frequency
• Knowing the FB threshold values, we can calculate Fsw
evolution and the corresponding Pout.
Fsw =
1
⎛ VFB
t prop
V
+
⎜⎜
in , dc
R
Lp
4
⎝ sense
⎞ ⎛ 1
N ps
L
+
⎟⎟ p ⎜⎜
⎠ ⎝ Vin ,dc Vout + V f
⎞
⎟⎟ + (1 + 2n ) π Lp Clump
⎠
2
t prop ⎞
1 ⎛ VFB
+ Vin ,dc
Pout = L p ⎜
⎟⎟ Fswη
⎜
Lp ⎠
2 ⎝ 4 Rsense
Replace VFB by the valley thresholds
values in the previous slide
Predicting the Switching Frequency
Calculate by hand (using the previous equations) or use the Mathcad
spreadsheet to deduce the maxima of the switching frequency => EMI
Fsw (Hz)
•
1 ×10
5
8 ×10
4
6 ×10
4
4 ×10
4
83 kHz
93 kHz
VCO
mode
4th
90 kHz
sw ve sus ou
2nd
3rd
4th
3rd
VCO
mode
2 ×10
95 kHz
VN
1st
2nd
1st
Pout decreases
Pout increases
4
0
20
40
Pout (W)
60
VCO Mode
•
The switching frequency is set by the end of charge of Ct capacitor
•
The end of charge of Ct capacitor is controlled by the FB loop
Vdd
Load
Rpullup
FB
Enable VCO
mode
Ct
6.5-(10/3)Vfb
VFBth
ICt
VCO
-
Vdd
VCt
+
Ct
Ct
discharge
Controlled by FB loop
S
DRV
Q
Q
R
CS comparator
(Timing capacitor voltage)
4th Valley to VCO Mode Transition
•
Output load slightly decreases:
Load
VFB
1.4 V
0.8 V
VFBth
Tsw2
Tsw1
4th valley
VCO mode
How to Calculate Ct Capacitor ?
•
Switching frequency at the end of the 4th valley operation (VFB = 0.8 V):
Tsw,4th −VCO
•
⎛ 0.8
N ps
Vin ,max 2 ⎞ ⎛
1
=⎜
+t
+
⎟ Lp ⎜
⎜ 4 Rsense prop
⎟
⎜
Lp
⎝
⎠ ⎝ Vin ,max 2 Vout + V f
Tsw gap between 4th valley and VCO mode must not exceed 10 µs
(based on lab experiments) for VFB = 1.4 V (hysteresis):
Tsw,VCO = Tsw,4th −VCO + 10 µs
•
⎞
⎟ + 7π L p COSS
⎟
⎠
The relationship between VFB and VCt is:
VCt = 6.5 − (10 / 3)VFB = 6.5 − (10 / 3) ×1.4 = 1.83V
Ct =
I CtTsw,VCO
1.83
Ct Design Example
•
Switching frequency at the end of the 4th valley operation :
⎛ 0.8
265 2 ⎞
0.25 ⎞
⎛ 1
Tsw,4th −VCO = ⎜⎜
+ 300n
+
+ 7π 285µ × 250 p
⎟⎟ 285µ ⎜
⎟
285µ ⎠
⎝ 265 2 19 + 0.8 ⎠
⎝ 4 × 0.23
= 10.7 µs
•
Tsw gap between 4th valley and VCO mode must not exceed 10 µs
(based on lab experiments):
Tsw,VCO = Tsw,4th −VCO + 10 µs = 10.7 µ + 10 µ = 20.7 µs
•
The timing capacitor value is:
Ct =
•
I CtTsw,VCO
1.83
=
20 µ × 20.7 µ
= 226 pF
1.83
Finally, we choose Ct = 200 pF
OPP: How it Works ?
•
Laux with flyback polarity swings to –NVIN during the on time.
•
Adjust amount of OPP voltage with (Rzcd+Ropu) // Ropl.
•
VCS,max = 0.8 V + VOPP
•
The diode bypass Ropu during the off-time for optimum zero-crossing
detection.
Rzcd
Ropu
CS
ZCD/OPP
+
1
Aux
Ropl
ESD
protection
+
IpFlag
Peak current
set point
0.8 V + Vopp
100%
0.8 V
60%
+
-
Demag
Vth
leakage blanking
DRV
Tblank
370
VIN (V)
OPP Amount Needed for the Design
•
Because of the propagation delay, at high line:
I pk ( high )
•
t prop
0.8
=
+ Vin ,max 2
Rsense
Lp
I pk ( high )
0.8
600 ×10−9
=
+ 265 2
= 4.32 A
0.23
290 ×10−6
The switching frequency is:
Tsw( high )
⎛
N ps
1
= I pk ( high ) L p ⎜
+
⎜V
⎝ in ,max 2 Vout + V f
⎞
⎟ + π L p Clump
⎟
⎠
0.25 ⎞
⎛ 1
+
+ π 285 × 10−6 × 250 × 10−12 = 19.5 µs
Tsw( high ) = 4.32 × 290 × 10−6 ⎜
⎟
⎝ 265 2 19 + 0.8 ⎠
•
The power capability at high line is:
Pout ( high )
1
1
2
= Lp I pk ( high )
η
Tsw( high )
2
Pout ( high ) =
1
1
290 ×10−6 × 4.322
0.85 = 116 W
2
19.5 ×10−6
Amount of OPP Voltage Needed
• Limit the output power to Pout(limit) = 70 W at high line.
• What is the peak current Ipk(limit) corresponding to Pout(limit) ?
I pk ( limit ) =
⎛
N ps
1
+
Lp ⎜
⎜ Vin ( max ),dc Vout + V f
⎝
⎞
⎛
N ps
1
2
+
⎟⎟ + Lp ⎜⎜
V
⎠
⎝ in ( max ),dc Vout + V f
Lpη
2
⎞
L pη
π L p Clump
⎟⎟ − 2
P
out ( limit )
⎠
Pout (limit )
I pk (limit ) =
0.25 ⎞
⎛ 1
285µ ⎜
+
⎟+
⎝ 375 19 + 0.8 ⎠
1
0.25 ⎞
285µ × 0.85
π 285µ × 250p
( 285µ ) ⎛⎜ +
⎟ −2
70
⎝ 375 19 + 0.8 ⎠
= 2.67 A
285µ × 0.85
70
2
2
• Amount of OPP voltage needed:
VOPP
⎛ I pk ( limit )
= 0.8 ⎜ 1 −
⎜
I pk ( max )
⎝
⎞
⎟⎟
⎠
⎛ 2.67 ⎞
VOPP = 0.8 ⎜ 1 −
⎟ = 300 mV
4.32
⎝
⎠
Calculating the OPP Resistors
•
The amount of OPP voltage needed to limit Pout to 70 W is : VOPP = 300 mV
•
Resistor divider law:
Ropu + Rzcd
Ropl
=
Rzcd
N p ,auxVIN − VOPP
ZCD/OPP
1
VOPP
Ropu + Rzcd
Ropl
•
Ropu
=
0.18 × 375 − 0.3
= 224
0.3
We choose: Ropl = 1 kΩ and Rzcd = 1 kΩ
Ropu = 221 Ropl − Rzcd
Ropu = 223 k Ω
Aux
Ropl
Why is the OPP Non Dissipative ?
•
Input voltage information given by auxiliary winding
•
In light load: VCO mode => Tsw expands, thus the average current in the
resistor bridge decreases
I bridge,avg =
Rzcd
toff
ton
1
1
N p ,auxVIN +
VCC + V f
(
+ Ropu + Ropl Tsw
Ropu + Ropl Tsw
¾ Previous example: Ropu = 220 kΩ, Ropl = 1 kΩ, Rzcd = 1 kΩ
At light load (Pout = 4 W), ton= 1.2 µs, toff = 3.6 µs, Tsw = 40 µs
I bridge,mean =
1
1.2µ
1
3.6µ
× 0.18 × 375 +
16 = 15 µA
220k + 1k + 1k 40 µ
220k + 1k 40 µ
)
Startup Network
Bulk
D4
D3
I1
I1
Rstartup
Rstartup/3.14
Vcc
D6
D5
Vcc
D1
CVcc
Classical configuration
Laux
D2
CVcc
Laux
Improved startup dissipation
• The startup resistor can either be connected:
– To the bulk capacitor with Rstartup
– To the half-wave – for a similar charging current, take Rstartup /π
Startup Capacitor Calculation
•
CVcc calculated to allow the power supply to close the loop before VCC
falls below VCC(off)
CVcc
CVcc =
I
(
=
CC 3A
+ Qg Fsw ) treg
VCC ( on ) − VCC(off)
VCC
( 2.4m + 17n × 45000 ) ×10m = 3.9 µF
17 − 9
treg
tstartup
We choose CVcc = 4.7 µF
•
Needed startup current to charge CVcc:
I Cvcc =
VCC ( on )CVcc
tstartup
I Cvcc =
17 × 4.7 µ
= 28.5 µA
2.8
treg
Startup Resistor Calculation
•
Bulk capacitor connection
¾ Resistor calculation:
Rstartup =
Rstartup =
Pstartup
Half wave connection
¾ Resistor calculation:
Vin ,min 2
Vin ,min 2
I Cvcc + I CC ( start )
Rstartup =
85 2
= 2.76 M Ω
28.5µ + 15µ
¾ Power dissipation:
Pstartup
•
V
(
=
2 − VCC
in , max
265
(
=
2.68M
)
I Cvcc + I CC ( start )
85 2 π
= 880 k Ω
28.5µ + 15µ
¾ Power dissipation:
)
2
Rstartup
2 − 16
Rstartup =
π
2
Pstartup
= 55 mW
Pstartup
⎛ Vin ,max 2
⎞
−
V
⎜
CC ⎟
⎜
⎟
π
⎝
⎠
=
Rstartup
( 265
=
2 π − 16
880k
Half wave connection saves 39 mW !
)
2
2
= 16 mW
Synchronous Rectification
• High rms currents in secondary side Æ increased losses in
the output diode.
• Replace the diode with a MOSFET featuring a very low
RDS(on).
+
-
Increased efficiency
Degraded light load and
standby power consumption
Vout
.
Cout
.
Q sync
Gnd
Losses in the Sync. Rect. Switch
PQsync = PON + PQdiode
‰ Body diode conduction losses
PQdiode = V f I out Fswtdelay
•
Body diode conducts before
the MOSFET is turned-on.
No switching losses
Low if tdelay small
tdelay
‰ MOSFET conduction losses
.
PON = RDS ( on )120 I sec ,rms
2
Vout
Cout
.
Q sync
Rload
Gnd
‰ Losses in the Sync. Rect. switch are mainly conduction losses.
Choosing the Sync. Rect. MOSFET
Target around 1 W conduction losses in Sync. Rect. switch to avoid
using an heatsink.
RDSon120 =
Vout = 19 V
Fsw,min = 45 kHz
Universal mains
1W
I sec , RMS 2
RDSon110 = 70 mΩ
6
Ploss (W)
•
MBR20H150
RDSon110 = 50 mΩ
4
RDSon110 = 30 mΩ
2
0
1
2
3
4
Iout (A)
5
6
60 W QR Sync. Rect. Calculations
‰ Body diode losses:
PQdiode = V f I out Fswtdelay = 0.7 × 3.2 × 45000 × 70n
PQdiode = 7 mW
‰ MOSFET losses:
PON = RDS ( on )120 I sec ,rms 2 = 30m × 5.82
PON = 1W
‰ Total Sync. Rect. switch losses: PQsync = 1 + 0.007 ≈ 1W
‰ Losses into the MBR20200 diode: 2.6 W
Power loss saving: 1.6 W
Agenda
1. Quasi-Resonance (QR) Generalities
2. The valley lockout technique
3. The NCP1379/1380
4. Step by step design procedure
5. Performances of a 60 W adapter featuring
valley lockout
60 W Demo Board Schematic
C1
2.2n
R4
18k
R11
18k
Rx
10
X18
KBU4K
R18
1k
+
.
IN
R2
1500k
-
R1
240k
C18
100n
D4
1N4148
C14
100u
10 mH
2A
L1
R19
1Meg
R13
1Meg
C6
22p
R14
1k
D8
1N4148
X2
35V
1
8
2
7
3
6
4
5
C5b
680uF
C7
100uF
35V
Gnd
25V
C15
2.2nF
Type = Y1
Gnd
R5
27k
R9
1k
C13
100u
D7
1N4148
M1
IPA60R385
R16
10
C5
1n
C8
220p
T1
D6
1N967
R29
1k
R12
1Meg
C9
330nF
C5a
680uF
R6
1200k
X1
DIP8
D2
MBR20H150
.
D5
1N4937
D1
1N4937
.
Vout
L3
2.2u
TO-220
C17
10n
X4
NTC
C11
4.7u
C4
200p
D3
1N4148
Q1
BC857
R3
47k
R26
0.47
C20
100n
NCP1380B in a 19 V, 60 W adapter
R27
0.47
R15
1k
C10
47n
X5
TL431_G
Gnd
R7
39k
R8
10k
Startup
•
•
Startup resistor connected to
the bulk rail (Rstartup = 2.7 MΩ)
Tstartup = 2.68 s
VCC
•
•
Startup resistor connected to the
half-wave (Rstartup = 910 kΩ)
Tstartup = 2.1 s
VCC
Transient Load Step
•
•
Load step:
3% to 100% of output load
with a slew rate of 1 A / µs
Vin = 230 Vrms
The overshoot / undershoot is 1% of the nominal value of Vout
Short-Circuit
•
VCC
•
•
VCC(off)
VDRV
A short-circuit is made at the
board output.
The circuit pulses with a low
burst (5%)
The measured averaged input
power is: Pin = 412.4 mW for
Vin = 230 Vrms
Efficiency
230 Vrms
115 Vrms
Pout (W)
Pout (%)
Pin (W)
Eff. (%)
Pout (W)
Pout (%)
Pin (W)
Eff. (%)
60.6
100
68.65
88.3
60.6
100
68.00
89.1
45.5
75
51.29
88.7
45.5
75
51.43
88.4
30.3
50
34.40
88.2
30.3
50
34.78
87.3
15.2
25
17.61
86.4
15.2
25
17.66
86.1
1.0
1.30
76.4
1.0
1.325
75.4
0.7
0.94
74.5
0.7
0.958
73.0
0.5
0.69
72.0
0.5
0.71
70.2
Average efficiency
(25, 50, 75, 100% of Pout,max): 87.9%
Average efficiency
(25, 50, 75, 100% of Pout,max): 87.7%
Improving the No Load Consumption
•
At very low output load, the TL431 bias is removed using a special
circuit:
Vout
L3
2.2u
.
.
D2
MBR20H150
C5a
680uF
35V
C15
2.2nF
Type = Y1
C5b
680uF
C7
100uF
35V
Gnd
25V
R9
1k
Gnd
TL431 bias
suppresion
circuit
R5
27k
R7
39k
C10
47n
X5
TL431_G
R8
10k
Gnd
No Load Consumption
• Rstartup connected to the bulk rail:
– Without TL431 bias:
Pout = 0 W
115 Vrms
230 Vrms
Pin = 60 mW
Pin = 98 mW
115 Vrms
230 Vrms
Pin = 98 mW
Pin = 128 mW
– With TL431 bias:
Pout = 0 W
3 MΩ resistor to discharge X2 capacitor included
No Load Consumption
• Rstartup connected to the half wave:
– Without TL431 bias, Rstartup = 1.1 MΩ (Tstartup = 2.6 s @ 85 Vrms)
Pout = 0 W
115 Vrms
230 Vrms
Pin = 55 mW
Pin = 90 mW
3 MΩ resistor to discharge X2 capacitor included
Synchronous Rectification Schematic
Vout
L3
0.5u
T1
.
IRFS4321
C5a
680µF
C5b
680µF
35V
35V
M3
C7
100uF
Gnd
16V
C15
2.2nF
Gnd
R28
10
D2
1N4148
R10
75
TL431 and NCP4302
bias suppression
circuit
R9
1k
R5
27k
X1
DIP4302
R7
39k
1
Sync
Vcc 8
7
DRV
3
2
Trig
4
5
Dlyadj
C10
47n
Gnd 6
R8
10k
R30
15k
R31
110k
Gnd
•
TL431 and NCP4302
bias removed at light
load.
Efficiency and No Load Consumption
115 Vrms
230 Vrms
Pout (W)
Pout (%)
Pin (W)
Eff. (%)
Pout (W)
Pout (%)
Pin (W)
Eff. (%)
60.5
100
67.18
90.1
60.5
100
66.48
91.0
45.4
75
50.23
90.5
45.4
75
50.38
90.1
30.3
50
33.78
89.8
30.3
50
34.2
88.6
15.2
25
17.39
87.4
15.2
25
17.48
86.8
1.0
1.319
75.7
1.0
1.368
72.9
0.7
0.945
74.0
0.7
0.992
70.5
0.5
0.690
72.4
0.5
0.737
67.6
Average efficiency (25, 50, 75, 100% of Pout,max): 89.5%
‰ No load consumption:
Pout = 0 W
Average efficiency (25, 50, 75, 100% of Pout,max): 89.1%
115 Vrms
230 Vrms
Pin = 62 mW
Pin = 107 mW
Conclusion
•
The valley lockout technique allows to solve the valley jumping problem
in QR power supplies.
•
NCP1380, NCP1379 features:
• QR current-mode with valley lockout for noise immunity for high load.
• VCO mode in light load for improved efficiency.
• OPP, OVP, BO, OTP, soft-start for building safe power supplies
•
A complete design method has been presented.
•
It is possible to achieve standby power consumption below 100 mW at
230 Vrms with the NCP1380.
•
Good efficiency at light load with Sync. Rect if the bias of the TL431 and
the Sync. Rec. controller is removed.
•
Mathcad spreadsheet and simulations models available.
For More Information
•
View the extensive portfolio of power management products from ON
Semiconductor at www.onsemi.com
•
View reference designs, design notes, and other material supporting
the design of highly efficient power supplies at
www.onsemi.com/powersupplies
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